commit ddb927ee30784e8e1aca4b5de81a32879dc6fd84 Author: yuquanjun Date: Sun Jul 5 04:31:26 2026 +0800 Initial: CW32F030 reference + CW32L012 BLDC port Add working CW32F030 BLDC Hall PID reference firmware and port the application to CW32L012 with Keil MDK project QQT912_L012. Co-authored-by: Cursor diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..a08e7c7 --- /dev/null +++ b/.gitignore @@ -0,0 +1,29 @@ +# Keil MDK build outputs +Objects/ +Listings/ +*.uvguix.* +*.uvguix +*.dep +*.crf +*.d +*.o +*.axf +*.htm +*.lnp +*.map +*.build_log.htm +*.lst + +# J-Link +JLinkLog.txt +JLinkSettings.ini + +# IDE +.vscode/ +.idea/ +*.swp +*~ + +# OS +Thumbs.db +Desktop.ini diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_DataSheet_CN_V1.8.pdf b/原单片机-CW32F030/MCU厂资料/CW32F030_DataSheet_CN_V1.8.pdf new file mode 100644 index 0000000..b9fcf4d Binary files /dev/null and b/原单片机-CW32F030/MCU厂资料/CW32F030_DataSheet_CN_V1.8.pdf differ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2.zip b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2.zip new file mode 100644 index 0000000..b4c1dbc Binary files /dev/null and b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2.zip differ diff --git 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + adc_sgl_ext_trig + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030 -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + adc_sgl_ext_trig + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_adc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_adc.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_ext_trig/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_ext_trig/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_ext_trig/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_ext_trig/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_ext_trig/USER/inc/main.h new file mode 100644 index 0000000..9d0674c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_ext_trig/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void LED_Init(void); + +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_ext_trig/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_ext_trig/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..c0caa09 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_ext_trig/USER/src/interrupts_cw32f030.c @@ -0,0 +1,421 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_adc.h" +#include "cw32f030_gtim.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +extern volatile uint8_t gFlagIrq; + + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + ADC_GetITStatusAll(&gFlagIrq); + ADC_ClearITPendingAll(); + GTIM_ClearITPendingBit(CW_GTIM1, GTIM_IT_OV); + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + if (GTIM_GetITStatus(CW_GTIM1, GTIM_IT_OV)) + { + GTIM_ClearITPendingBit(CW_GTIM1, GTIM_IT_OV); + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_ext_trig/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_ext_trig/USER/src/main.c new file mode 100644 index 0000000..4eb9494 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_ext_trig/USER/src/main.c @@ -0,0 +1,195 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-09-22 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_systick.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_adc.h" +#include "cw32f030_gtim.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint16_t valueAdc; +uint32_t valueAdcAcc; +volatile uint8_t gFlagIrq; +uint16_t gCntEoc = 0; +uint8_t cntSample; +float fTsDegree; + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief ADC I/O初始化 + * + */ +void ADC_PortInit(void) +{ + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk); + //打开ADC时钟 + REGBITS_SET(CW_SYSCTRL->APBEN2, SYSCTRL_APBEN2_ADC_Msk); + //set PA01 as AIN1 INPUT + PA01_ANALOG_ENABLE(); +} + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOB_Msk); + /* Configure the GPIO_LED pin */ + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + //LEDs are off. + PB08_SETLOW(); + PB09_SETLOW(); +} + +/** + * @brief GTIM初始化 + * + */ +void GTIM_Init(void) +{ + GTIM_InitTypeDef GTIM_InitStruct; + //打开GTIM时钟 + REGBITS_SET(CW_SYSCTRL->APBEN1, SYSCTRL_APBEN1_GTIM1_Msk); + GTIM_InitStruct.Mode = GTIM_MODE_TIME; + GTIM_InitStruct.OneShotMode = GTIM_COUNT_CONTINUE; + GTIM_InitStruct.Prescaler = GTIM_PRESCALER_DIV256; + GTIM_InitStruct.ReloadValue = 31249ul; //1s. + GTIM_InitStruct.ToggleOutState = ENABLE; + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + GTIM_ITConfig(CW_GTIM1, GTIM_IT_OV, ENABLE); + NVIC_ClearPendingIRQ(GTIM1_IRQn); + //NVIC_EnableIRQ(GTIM1_IRQn); + //NVIC_SetPriority(GTIM1_IRQn, 0x03); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + ADC_InitTypeDef ADC_InitStructure; + ADC_WdtTypeDef ADC_WdtStructure; + ADC_SingleChTypeDef ADC_SingleChStructure; + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + //配置ADC测试IO口 + ADC_PortInit(); + //LED初始化 + LED_Init(); + GTIM_Init(); + //ADC默认值初始化 + ADC_StructInit(&ADC_InitStructure); + //Test only + ADC_InitStructure.ADC_VrefSel = ADC_Vref_BGR2p5; + //ADC_InitStructure.ADC_VrefSel = ADC_Vref_BGR1p5; //Another option + //ADC模拟看门狗通道初始化 + ADC_WdtInit(&ADC_WdtStructure); + //配置单通道转换模式 + ADC_SingleChStructure.ADC_DiscardEn = ADC_DiscardNull; + ADC_SingleChStructure.ADC_Chmux = ADC_TsInput; //ADC_ExInputCH1; //选择ADC转换通道 // + ADC_SingleChStructure.ADC_InitStruct = ADC_InitStructure; + ADC_SingleChStructure.ADC_WdtStruct = ADC_WdtStructure; + ADC_SingleChOneModeCfg(&ADC_SingleChStructure); + ADC_ITConfig(ADC_IT_EOC, ENABLE); + ADC_EnableIrq(ADC_INT_PRIORITY); + ADC_ClearITPendingAll(); + //ADC使能 + ADC_Enable(); + //ADC外部中断触发源配置 + ADC_ExtTrigCfg(ADC_TRIG_GTIM1, ENABLE); + GTIM_Cmd(CW_GTIM1, ENABLE); + while (1) + { + while (!(gFlagIrq & ADC_ISR_EOC_Msk)); + gFlagIrq = 0u; + PB09_TOG(); + valueAdc = ADC_GetConversionValue(); + ADC_GetTsVref2V5(&fTsDegree); + //ADC_GetTsVref1V5(&fTsDegree); //Must select accordingly ADC_Vref_BGR1p5 first. + //等待ADC外部中断触发源启动下一次ADC转换 + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_ext_trig/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_ext_trig/readme.txt new file mode 100644 index 0000000..4e43d40 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_ext_trig/readme.txt @@ -0,0 +1,27 @@ +示例目的： + 演示定时器外部触发启动ADC转换，定时1s采样芯片温度。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. GTIM1的时钟源为PCLK，256分频 + 5. PB09设置为PUSH-PULL输出 + 6. ADC的时钟源为PCLK，2分频 + +演示说明： + 通用定时器GTIM1定时1s自动触发ADC模块进行转换，ADC通道为MCU内部温度传感器TS。 + PB09输出电平翻转，LED1将0.5Hz的频率闪烁。 + +使用说明： ++ EWARM + 1. 打开adc_sgl_ext_trig.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开adc_sgl_ext_trig.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/EWARM/adc_sgl_pwm_out.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/EWARM/adc_sgl_pwm_out.ewd new file mode 100644 index 0000000..d09623c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/EWARM/adc_sgl_pwm_out.ewd @@ -0,0 +1,3269 @@ + + + + 2 + + Release + + ARM + + 0 + + C-SPY + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + adc_sgl_pwm_out + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U56FF71065178565626600287 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U4294967295 -O78 -S5 -ZTIFSpeedSel1000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8027 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + valueAdc + + + 1 + 1 + valueReload + + + 2 + 1 + valuePosWidth + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\ADC + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_adc.c + cw32f030_adc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + cw32f030_gtim.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/MDK/adc_sgl_pwm_out.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/MDK/adc_sgl_pwm_out.uvprojx new file mode 100644 index 0000000..75a0da9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/MDK/adc_sgl_pwm_out.uvprojx @@ -0,0 +1,471 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + adc_sgl_pwm_out + 0x4 + ARM-ADS + 6100001::V6.10.1::.\ARMCLANG + 1 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + adc_sgl_pwm_out + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 5 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_adc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_adc.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/USER/inc/main.h new file mode 100644 index 0000000..ef31228 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/USER/inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +//#define TSSOP20_EN + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void LED_Init(void); +void PWM_PortInit(void); +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..bfa69a4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/USER/src/interrupts_cw32f030.c @@ -0,0 +1,419 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_adc.h" +#include "cw32f030_gtim.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +extern volatile uint8_t gFlagIrq; + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + gFlagIrq = CW_ADC->ISR; + CW_ADC->ICR = 0x00; + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + if (GTIM_GetITStatus(CW_GTIM1, GTIM_IT_OV)) + { + GTIM_ClearITPendingBit(CW_GTIM1, GTIM_IT_OV); + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/USER/src/main.c new file mode 100644 index 0000000..490d3b0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/USER/src/main.c @@ -0,0 +1,281 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-09-23 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_systick.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_adc.h" +#include "cw32f030_gtim.h" +#include "cw32f030_flash.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint16_t valueAdc; +uint32_t valueAdcAcc; +volatile uint8_t gFlagIrq; +uint16_t gCntEoc = 0; +uint8_t cntSample; +float fTsDegree; +//... +uint32_t valuePeriod; +uint32_t valuePosWidth; +uint32_t valueReload = 0xFFFFu; +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief PWM I/O初始化 + * + */ +void PWM_PortInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + /* PA5 PWM 输出 */ + __RCC_GPIOA_CLK_ENABLE(); + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_5; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + PA05_AFx_GTIM2CH1(); +} + +/** + * @brief ADC I/O初始化 + * + */ +void ADC_PortInit(void) +{ + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk); + //打开ADC时钟 + REGBITS_SET(CW_SYSCTRL->APBEN2, SYSCTRL_APBEN2_ADC_Msk); + //set PA01 as AIN1 INPUT + PA01_ANALOG_ENABLE(); +} + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; +#ifdef TSSOP20_EN + //打开GPIO时钟 + __RCC_GPIOA_CLK_ENABLE(); + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_7; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + __RCC_GPIOB_CLK_ENABLE(); + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_1; + //GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + //GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + //LEDs are off. + PB01_SETLOW(); + PA07_SETLOW(); +#else + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOB_Msk); + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + //LEDs are off. + PB08_SETLOW(); + PB09_SETLOW(); +#endif +} + +/** + * @brief GTIM初始化 + * + */ +void GTIM_Init(void) +{ + GTIM_InitTypeDef GTIM_InitStruct; + //打开GTIM1时钟 + REGBITS_SET(CW_SYSCTRL->APBEN1, SYSCTRL_APBEN1_GTIM1_Msk); + GTIM_InitStruct.Mode = GTIM_MODE_TIME; + GTIM_InitStruct.OneShotMode = GTIM_COUNT_CONTINUE; + GTIM_InitStruct.Prescaler = GTIM_PRESCALER_DIV1024; + GTIM_InitStruct.ReloadValue = 62499ul; //T=1s. + GTIM_InitStruct.ToggleOutState = DISABLE; + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + GTIM_ITConfig(CW_GTIM1, GTIM_IT_OV, ENABLE); + NVIC_ClearPendingIRQ(GTIM1_IRQn); + NVIC_EnableIRQ(GTIM1_IRQn); + NVIC_SetPriority(GTIM1_IRQn, 0x03); + //GTIM_Cmd(CW_GTIM1, ENABLE); + //打开GTIM2时钟 + __RCC_GTIM2_CLK_ENABLE(); + //GTIM_InitStruct.Mode = GTIM_MODE_TIME; + //GTIM_InitStruct.OneShotMode = GTIM_COUNT_CONTINUE; + //GTIM_InitStruct.Prescaler = GTIM_PRESCALER_DIV1024; + GTIM_InitStruct.ReloadValue = 0xFFFFu; + GTIM_InitStruct.ToggleOutState = ENABLE; + GTIM_TimeBaseInit(CW_GTIM2, >IM_InitStruct); + valuePeriod = GTIM_InitStruct.ReloadValue; + valuePosWidth = valuePeriod >> 1u; + GTIM_OCInit(CW_GTIM2, GTIM_CHANNEL1, GTIM_OC_OUTPUT_PWM_HIGH); + GTIM_SetCompare1(CW_GTIM2, valuePosWidth); + //GTIM_ITConfig(CW_GTIM2, GTIM_IT_OV, ENABLE); + GTIM_Cmd(CW_GTIM2, ENABLE); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + uint8_t res; + ADC_InitTypeDef ADC_InitStructure; + ADC_WdtTypeDef ADC_WdtStructure; + ADC_SingleChTypeDef ADC_SingleChStructure; + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + //以下从HSI切换到PLL + RCC_PLL_Enable(RCC_PLLSOURCE_HSI, 8000000UL, RCC_PLL_MUL_8); //开启PLL，PLL源为HSI + //打开FLASH时钟 + __RCC_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_3); + res = RCC_SysClk_Switch(RCC_SYSCLKSRC_PLL); //切换系统时钟到PLL：64MHz。 + if (res > 0) //切换系统时钟失败 + { +#ifdef TSSOP20_EN + PB01_SETHIGH(); + PA07_SETHIGH(); +#else + //LEDs are on. + PB08_SETHIGH(); + PB09_SETHIGH(); +#endif + while (1); + } + else + { + } + //配置ADC测试IO口 + ADC_PortInit(); + //LED初始化 + LED_Init(); + PWM_PortInit(); + GTIM_Init(); + //ADC默认值初始化 + ADC_StructInit(&ADC_InitStructure); + //ADC模拟看门狗通道初始化 + ADC_WdtInit(&ADC_WdtStructure); + ADC_InitStructure.ADC_ClkDiv = ADC_Clk_Div128; //ADCCLK:500KHz. + ADC_InitStructure.ADC_InBufEn = ADC_BufEnable; + ADC_InitStructure.ADC_SampleTime = ADC_SampTime10Clk; + //配置单通道转换模式 + ADC_SingleChStructure.ADC_DiscardEn = ADC_DiscardNull; + ADC_SingleChStructure.ADC_Chmux = ADC_ExInputCH1; //选择ADC转换通道 + ADC_SingleChStructure.ADC_InitStruct = ADC_InitStructure; + ADC_SingleChStructure.ADC_WdtStruct = ADC_WdtStructure; + ADC_SingleChOneModeCfg(&ADC_SingleChStructure); + ADC_ITConfig(ADC_IT_EOC, ENABLE); + ADC_EnableIrq(ADC_INT_PRIORITY); + ADC_ClearITPendingAll(); + //ADC使能 + ADC_Enable(); + //ADC外部中断触发源配置 + ADC_ExtTrigCfg(ADC_TRIG_GTIM1, ENABLE); + GTIM_Cmd(CW_GTIM1, ENABLE); + while (1) + { + while (!(gFlagIrq & ADC_ISR_EOC_Msk)); + gFlagIrq = 0u; +#ifdef TSSOP20_EN + PB01_TOG(); +#else + PB09_TOG(); +#endif + valueAdc = ADC_GetConversionValue(); + //positive slope + //valueReload =(4095u * 62500ul) / (4999u * valueAdc + 4095u); + valueReload = ((4095u * 125000ul) / (4999u * valueAdc + 4095u) + 1) >> 1; //Rounding. + valuePosWidth = valueReload >> 1u; + GTIM_SetCounterValue(CW_GTIM2, 0u); //reset. + GTIM_SetReloadValue(CW_GTIM2, valueReload); + GTIM_SetCompare1(CW_GTIM2, valuePosWidth); + //等待ADC外部中断触发源启动下一次ADC转换 + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/readme.txt new file mode 100644 index 0000000..2d64032 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_pwm_out/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 演示定时器外部触发启动ADC转换，定时1s采样AIN1，并以PWM方波输出ADC采样值。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟源为PLL，PLL时钟源为HSI时钟6分频：8MHz，PLL8倍频，PCLK、HCLK不分频，PCLK=HCLK=SysClk=64MHz + 4. GTIM1、GTIM2的时钟源为PCLK，1024分频 + 5. PB09设置为PUSH-PULL输出 + 6. ADC的时钟源为PCLK，128分频 + +演示说明： + 通用定时器GTIM1定时1s自动触发ADC模块进行转换，ADC通道为AIN1:PA01。 + 通用定时器GTIM2将AIN1的ADC采样值转换成频率可变的PWM方波，占空比50%。 + ADC采样值为0时，PWM方波频率为1Hz；ADC采样值为4095时，PWM方波频率为5KHz。 + PB09输出电平翻转，LED1将0.5Hz的频率闪烁。 + +使用说明： ++ EWARM + 1. 打开adc_sgl_pwm_out.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开adc_sgl_pwm_out.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/EWARM/adc_sgl_sw.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/EWARM/adc_sgl_sw.ewd new file mode 100644 index 0000000..d09623c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/EWARM/adc_sgl_sw.ewd @@ -0,0 +1,3269 @@ + + + + 2 + + Release + + ARM + + 0 + + C-SPY + 2 + + 28 + 1 + 0 + + + + + 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--- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/EWARM/adc_sgl_sw.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\adc_sgl_sw.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/MDK/adc_sgl_sw.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/MDK/adc_sgl_sw.uvoptx new file mode 100644 index 0000000..c92c61b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/MDK/adc_sgl_sw.uvoptx @@ -0,0 +1,359 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + adc_sgl_sw + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U57FF73067186485052160667 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + -U -O206 -S0 -C0 -P00 -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FN1 -FC800 -FD20000000 -FF0FlashCW32F002 -FL04000 -FS00 -FP0($$Device:CW32F002F3$Flash\FlashCW32F002.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + + + + 0 + 1 + valueAdc + + + + + 1 + 2 + 0x12600 + 0 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\ADC + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_adc.c + cw32f030_adc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/MDK/adc_sgl_sw.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/MDK/adc_sgl_sw.uvprojx new file mode 100644 index 0000000..991a566 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/MDK/adc_sgl_sw.uvprojx @@ -0,0 +1,461 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + adc_sgl_sw + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC800 -FN1 -FF0FlashCW32F002 -FS00 -FL04000 -FP0($$Device:CW32F002F3$Flash\FlashCW32F002.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + adc_sgl_sw + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_adc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_adc.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/USER/inc/main.h new file mode 100644 index 0000000..2d4cfe9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/USER/inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +//#define SGL_ONE_MODE_EN /*!< 单输入通道单次采样模式 */ +#define SGL_MORE_MODE_EN /*!< 单输入通道多次采样模式 */ +//#define SGL_CONTINUOUS_MODE_EN /*!< 单输入通道连续采样模式 */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void LED_Init(void); +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..6a520dc --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/USER/src/interrupts_cw32f030.c @@ -0,0 +1,421 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_adc.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +extern volatile uint8_t gFlagIrq; +extern uint16_t gCntEoc; + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + gFlagIrq = CW_ADC->ISR; + CW_ADC->ICR = 0x00; +#ifdef SGL_MORE_MODE_EN + if (gFlagIrq & ADC_ISR_EOC_Msk) + { + gCntEoc++; + } +#endif + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/USER/src/main.c new file mode 100644 index 0000000..3530405 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/USER/src/main.c @@ -0,0 +1,197 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-09-22 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_systick.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_adc.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint16_t valueAdc; +uint32_t valueAdcAcc; +volatile uint8_t gFlagIrq; +uint16_t gCntEoc = 0; +uint8_t cntSample; + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief ADC I/O初始化 + * + */ +void ADC_PortInit(void) +{ + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk); + //打开ADC时钟 + REGBITS_SET(CW_SYSCTRL->APBEN2, SYSCTRL_APBEN2_ADC_Msk); + //set PA01 as AIN1 INPUT + PA01_ANALOG_ENABLE(); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + ADC_InitTypeDef ADC_InitStructure; + ADC_WdtTypeDef ADC_WdtStructure; + ADC_SingleChTypeDef ADC_SingleChStructure; + //LED初始化 + LED_Init(); + //配置ADC测试IO口 + ADC_PortInit(); + //ADC默认值初始化 + ADC_StructInit(&ADC_InitStructure); + //ADC工作时钟配置 +#ifdef SGL_MORE_MODE_EN + ADC_InitStructure.ADC_ClkDiv = ADC_Clk_Div4; +#else + ADC_InitStructure.ADC_ClkDiv = ADC_Clk_Div1; +#endif + //ADC模拟看门狗通道初始化 + ADC_WdtInit(&ADC_WdtStructure); + //配置单通道转换模式 + ADC_SingleChStructure.ADC_DiscardEn = ADC_DiscardNull; + ADC_SingleChStructure.ADC_Chmux = ADC_ExInputCH1; //选择ADC转换通道，AIN1:PA01 + ADC_SingleChStructure.ADC_InitStruct = ADC_InitStructure; + ADC_SingleChStructure.ADC_WdtStruct = ADC_WdtStructure; +#ifdef SGL_ONE_MODE_EN + ADC_SingleChOneModeCfg(&ADC_SingleChStructure); + ADC_ITConfig(ADC_IT_EOC, ENABLE); +#elif defined (SGL_MORE_MODE_EN) + cntSample = 0xFF; //转换次数为0xFF + 1次. + ADC_SingleChMoreModeCfg(&ADC_SingleChStructure, cntSample); + ADC_ITConfig(ADC_IT_EOC | ADC_IT_EOA, ENABLE); +#elif defined (SGL_CONTINUOUS_MODE_EN) + ADC_SingleChContinuousModeCfg(&ADC_SingleChStructure); + ADC_ITConfig(ADC_IT_EOC, ENABLE); +#else +#error "Please select ADC's running mode first in main.h!" +#endif + //ADC_ITConfig(ADC_IT_EOC | ADC_IT_EOA, ENABLE); + ADC_EnableIrq(ADC_INT_PRIORITY); + ADC_ClearITPendingAll(); + //ADC使能 + ADC_Enable(); + + ADC_SoftwareStartConvCmd(ENABLE); + while (1) + { +#ifdef SGL_MORE_MODE_EN + while (!(gFlagIrq & ADC_ISR_EOA_Msk)); + gFlagIrq = 0u; + ADC_GetAccResult(&valueAdcAcc); + if (gCntEoc != (cntSample + 1)) + { + PB08_SETHIGH(); + PB09_SETHIGH(); + while (1); //error issue. + } + gCntEoc = 0u; +#else + while (!(gFlagIrq & ADC_ISR_EOC_Msk)); + gFlagIrq = 0u; + valueAdc = ADC_GetConversionValue(); +#endif + PB09_TOG(); +#ifndef SGL_CONTINUOUS_MODE_EN + ADC_SoftwareStartConvCmd(ENABLE); //启动下一次ADC转换 +#endif + } +} + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOB_Msk); + /* Configure the GPIO_LED pin */ + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + //LEDs are off. + PB08_SETLOW(); + PB09_SETLOW(); +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/readme.txt new file mode 100644 index 0000000..31f2c94 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_sw/readme.txt @@ -0,0 +1,28 @@ +示例目的： + 演示软件启动ADC单通道转换，支持单通道单次、多次、连续等3种转换模式。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. ADC的时钟源为PCLK，1或者4分频 + 5. PB08/09设置为PUSH-PULL输出 + +演示说明： + ADC通道为AIN1:PA01。 + ADC转换完成，PB09输出电平翻转。 + 多次转换模式时，如果实际完成转换次数与设定值不等时，PB08/09全部点亮。 + 注意：修改main.h中的转换模式宏定义，即可实现各种转换模式的测试。 + +使用说明： ++ EWARM + 1. 打开adc_sgl_sw.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开adc_sgl_sw.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/EWARM/adc_sgl_wdt.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/EWARM/adc_sgl_wdt.ewd new file mode 100644 index 0000000..d09623c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/EWARM/adc_sgl_wdt.ewd @@ -0,0 +1,3269 @@ + + + + 2 + + Release + + ARM + + 0 + + C-SPY + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + adc_sgl_wdt + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + adc_sgl_wdt + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_adc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_adc.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_systick.c + 1 + ..\..\..\..\Libraries\src\cw32f030_systick.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/USER/inc/main.h new file mode 100644 index 0000000..9d0674c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void LED_Init(void); + +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..0ee73c7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/USER/src/interrupts_cw32f030.c @@ -0,0 +1,414 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_adc.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +extern volatile uint8_t gFlagIrq; + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + ADC_GetITStatusAll(&gFlagIrq); + ADC_ClearITPendingAll(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/USER/src/main.c new file mode 100644 index 0000000..5e7ddc9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/USER/src/main.c @@ -0,0 +1,180 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-09-23 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_systick.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_adc.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint16_t valueAdc; +uint32_t valueAdcAcc; +volatile uint8_t gFlagIrq; +uint16_t gCntEoc = 0; +uint8_t cntSample; + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief ADC I/O初始化 + * + */ +void ADC_PortInit(void) +{ + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk); + //打开ADC时钟 + REGBITS_SET(CW_SYSCTRL->APBEN2, SYSCTRL_APBEN2_ADC_Msk); + //set PA01 as AIN1 INPUT + PA01_ANALOG_ENABLE(); +} + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOB_Msk); + /* Configure the GPIO_LED pin */ + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + //LEDs are off. + PB08_SETLOW(); + PB09_SETLOW(); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + ADC_InitTypeDef ADC_InitStructure; + ADC_WdtTypeDef ADC_WdtStructure; + ADC_SingleChTypeDef ADC_SingleChStructure; + RCC_HSI_Enable(RCC_HSIOSC_DIV2); //配置系统时钟为HSI 24M + InitTick(24000000ul); //初始化SysTick + //配置ADC测试IO口 + ADC_PortInit(); + //LED初始化 + LED_Init(); + //ADC默认值初始化 + ADC_StructInit(&ADC_InitStructure); + //ADC模拟看门狗通道初始化 + ADC_WdtInit(&ADC_WdtStructure); + ADC_WdtStructure.ADC_WdtAll = ADC_WdtEnable; //使能模拟看门狗 + ADC_WdtStructure.ADC_WdtlIrq = ADC_WdtlEnable; //模拟看门狗下阈值中断使能 + ADC_WdtStructure.ADC_WdtCh = ADC_WdtCh1; //使能模拟看门狗通道：AIN1 + ADC_WdtStructure.ADC_Vtl = 0x600; //模拟看门狗检测低阈值 + //配置单通道转换模式 + ADC_SingleChStructure.ADC_DiscardEn = ADC_DiscardNull; + ADC_SingleChStructure.ADC_Chmux = ADC_ExInputCH1; //选择ADC转换通道，AIN1:PA01 + ADC_SingleChStructure.ADC_InitStruct = ADC_InitStructure; + ADC_SingleChStructure.ADC_WdtStruct = ADC_WdtStructure; + ADC_SingleChOneModeCfg(&ADC_SingleChStructure); + ADC_ITConfig(ADC_IT_WDTL, ENABLE); + //ADC_ITConfig(ADC_IT_EOC | ADC_IT_WDTL, ENABLE); + ADC_EnableIrq(ADC_INT_PRIORITY); + ADC_ClearITPendingAll(); + //ADC使能 + ADC_Enable(); + ADC_SoftwareStartConvCmd(ENABLE); + while (1) + { + if ((gFlagIrq & ADC_ISR_WDTL_Msk) > 0) + { + gFlagIrq = 0u; + PB09_TOG(); + SysTickDelay(1000); //1s. + } + valueAdc = ADC_GetConversionValue(); + ADC_SoftwareStartConvCmd(ENABLE); //启动下一次ADC转换 + } +} + +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn */ + uwTick += uwTickFreq; + /* USER CODE END SysTick_IRQn */ +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/readme.txt new file mode 100644 index 0000000..4f2b875 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sgl_wdt/readme.txt @@ -0,0 +1,27 @@ +示例目的： + 演示ADC模块单通道模拟看门狗功能。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. ADC的时钟源为PCLK，1分频 + 5. PB08/09设置为PUSH-PULL输出 + +演示说明： + 软件触发ADC模块进行单通道单次转换。 + ADC模拟看门狗通道为AIN1:PA01，下阈值为0x600。 + 外接可调直流电源到PA01，ADC转换完成，如果采样值小于下阈值，则PB09输出电平翻转。 + +使用说明： ++ EWARM + 1. 打开adc_sgl_wdt.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开adc_sgl_wdt.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/EWARM/adc_sqr_irq_sw.board b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/EWARM/adc_sqr_irq_sw.board new file mode 100644 index 0000000..20280b0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/EWARM/adc_sqr_irq_sw.board @@ -0,0 +1,7 @@ + + + + $PROJ_DIR$\flashloader\FlashLoader_CW030.flash + CODE 0x0 0x11fff + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/EWARM/adc_sqr_irq_sw.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/EWARM/adc_sqr_irq_sw.ewd new file mode 100644 index 0000000..357d3ec --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/EWARM/adc_sqr_irq_sw.ewd @@ -0,0 +1,3088 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 32 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + adc_sqr_irq_sw + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030 -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + adc_sqr_irq_sw + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_adc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_adc.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/USER/inc/main.h new file mode 100644 index 0000000..2db9653 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/USER/inc/main.h @@ -0,0 +1,78 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* 序列通道连续采样模式 */ +//#define SQR_CONTINUOUS_MODE_EN +/* 序列通道扫描采样模式 */ +//#define SQR_SCAN_MODE_EN +/* 序列通道多次采样模式 */ +//#define SQR_MORE_MODE_EN +/* 序列通道断续采样模式 */ +#define SQR_BREAK_MODE_EN +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void LED_Init(void); +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..f871aa1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/USER/src/interrupts_cw32f030.c @@ -0,0 +1,421 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_adc.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +extern volatile uint8_t gFlagIrq; +extern uint16_t gCntEoc; + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + gFlagIrq = CW_ADC->ISR; + CW_ADC->ICR = 0x00; +#ifdef SQR_MORE_MODE_EN + if (gFlagIrq & ADC_ISR_EOC_Msk) + { + gCntEoc++; + } +#endif + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/USER/src/main.c new file mode 100644 index 0000000..612b2fb --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/USER/src/main.c @@ -0,0 +1,240 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-09-22 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_systick.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_adc.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint16_t valueAdc; +uint16_t gAdcResult[4]; +uint32_t valueAdcAcc; +volatile uint8_t gFlagIrq; +uint16_t gCntEoc = 0; +uint8_t cntSample; + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief ADC I/O初始化 + * + */ +void ADC_PortInit(void) +{ + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk); + //打开ADC时钟 + REGBITS_SET(CW_SYSCTRL->APBEN2, SYSCTRL_APBEN2_ADC_Msk); + //set PA01 as AIN1 INPUT + PA01_ANALOG_ENABLE(); + //set PA02 as AIN2 INPUT + PA02_ANALOG_ENABLE(); + //set PA05 as AIN5 INPUT + PA05_ANALOG_ENABLE(); + //set PA07 as AIN7 INPUT + PA07_ANALOG_ENABLE(); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + ADC_InitTypeDef ADC_InitStructure; + ADC_SerialChTypeDef ADC_SerialChStructure; + //LED初始化 + LED_Init(); + //配置ADC测试IO口 + ADC_PortInit(); + //ADC初始化 + ADC_StructInit(&ADC_InitStructure); + //ADC工作时钟配置 +#ifdef SQR_BREAK_MODE_EN + ADC_InitStructure.ADC_ClkDiv = ADC_Clk_Div1; +#else + ADC_InitStructure.ADC_ClkDiv = ADC_Clk_Div16; +#endif + //ADC序列扫描转换模式配置 + ADC_SerialChStructure.ADC_Sqr0Chmux = ADC_SqrVddaDiV3; //ADC_SqrCh1; + ADC_SerialChStructure.ADC_Sqr1Chmux = ADC_SqrTs; //ADC_SqrCh2; // + ADC_SerialChStructure.ADC_Sqr2Chmux = ADC_SqrVref1P2; //ADC_SqrCh5; + ADC_SerialChStructure.ADC_Sqr3Chmux = ADC_SqrCh7; + ADC_SerialChStructure.ADC_SqrEns = ADC_SqrEns03; + ADC_SerialChStructure.ADC_InitStruct = ADC_InitStructure; +#ifdef SQR_CONTINUOUS_MODE_EN + /* 序列通道连续采样模式 */ + ADC_SerialChContinuousModeCfg(&ADC_SerialChStructure); + ADC_ITConfig(ADC_IT_EOS, ENABLE); +#elif defined (SQR_SCAN_MODE_EN) + /* 序列通道扫描采样模式 */ + ADC_SerialChScanModeCfg(&ADC_SerialChStructure); + ADC_ITConfig(ADC_IT_EOS, ENABLE); +#elif defined (SQR_MORE_MODE_EN) + /* 序列通道多次采样模式 */ + cntSample = 0xFF; //转换次数为0xFF + 1次. + ADC_SerialChMoreModeCfg(&ADC_SerialChStructure, cntSample); + ADC_ITConfig(ADC_IT_EOC | ADC_IT_EOA, ENABLE); +#elif defined (SQR_BREAK_MODE_EN) + /* 序列通道断续采样模式 */ + ADC_SerialChBreakModeCfg(&ADC_SerialChStructure); + ADC_ITConfig(ADC_IT_EOC | ADC_IT_EOS, ENABLE); +#else +#error "Please select ADC's running mode first in main.h!" +#endif + //ADC_ITConfig(ADC_IT_EOC | ADC_IT_EOS | ADC_IT_EOA, ENABLE); + ADC_EnableIrq(ADC_INT_PRIORITY); + ADC_ClearITPendingAll(); + //ADC使能 + ADC_Enable(); + ADC_SoftwareStartConvCmd(ENABLE); + while (1) + { +#ifdef SQR_CONTINUOUS_MODE_EN + /* 序列通道连续采样模式 */ + while (!(gFlagIrq & ADC_ISR_EOS_Msk)); + gFlagIrq = 0u; + //while(!(gFlagIrq & ADC_ISR_EOS_Msk)); + ADC_GetSqr0Result(gAdcResult); + ADC_GetSqr1Result(&gAdcResult[1]); + ADC_GetSqr2Result(&gAdcResult[2]); + ADC_GetSqr3Result(&gAdcResult[3]); +#elif defined (SQR_SCAN_MODE_EN) + /* 序列通道扫描采样模式 */ + while (!(gFlagIrq & ADC_ISR_EOS_Msk)); + gFlagIrq = 0u; + ADC_GetSqr0Result(gAdcResult); + ADC_GetSqr1Result(&gAdcResult[1]); + ADC_GetSqr2Result(&gAdcResult[2]); + ADC_GetSqr3Result(&gAdcResult[3]); +#elif defined (SQR_MORE_MODE_EN) + /* 序列通道多次采样模式 */ + while (!(gFlagIrq & ADC_ISR_EOA_Msk)); + gFlagIrq = 0u; + ADC_GetSqr0Result(gAdcResult); //Get data. + ADC_GetSqr1Result(&gAdcResult[1]); + ADC_GetSqr2Result(&gAdcResult[2]); + ADC_GetSqr3Result(&gAdcResult[3]); + ADC_GetAccResult(&valueAdcAcc); + if (gCntEoc != (cntSample + 1)) + { + PB08_SETHIGH(); + PB09_SETHIGH(); + while (1); //error issue. + } + gCntEoc = 0u; +#elif defined (SQR_BREAK_MODE_EN) + /* 序列通道断续采样模式 */ + while (!(gFlagIrq & ADC_ISR_EOC_Msk)); + gFlagIrq &= (~ADC_ISR_EOC_Msk); + if (gFlagIrq & ADC_ISR_EOS_Msk) + { + gFlagIrq = 0u; + ADC_GetSqr0Result(gAdcResult); + ADC_GetSqr1Result(&gAdcResult[1]); + ADC_GetSqr2Result(&gAdcResult[2]); + ADC_GetSqr3Result(&gAdcResult[3]); + } +#endif + PB09_TOG(); +#ifndef SQR_CONTINUOUS_MODE_EN + ADC_SoftwareStartConvCmd(ENABLE); //启动下一次ADC转换 +#endif + } +} + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOB_Msk); + /* Configure the GPIO_LED pin */ + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + //LEDs are off. + PB08_SETLOW(); + PB09_SETLOW(); +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/readme.txt new file mode 100644 index 0000000..b5481f9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ADC/adc_sqr_irq_sw/readme.txt @@ -0,0 +1,28 @@ +示例目的： + 演示软件触发ADC模块进行序列转换，支持序列连续、扫描、多次、断续等4种转换模式。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. ADC的时钟源为PCLK，1或者16分频 + 5. PB08/09设置为PUSH-PULL输出 + +演示说明： + ADC SQR通道分别为：VDDA/3, TS, BGR基准电压1.2V, AIN7:PA07。 + ADC转换完成，PB09输出电平翻转。 + 序列多次转换模式时，如果实际完成转换次数与设定值不等时，PB08/09全部点亮。 + 注意：修改main.h中的转换模式宏定义，即可实现各种转换模式的测试。 + +使用说明： ++ EWARM + 1. 打开adc_sqr_irq_sw.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开adc_sqr_irq_sw.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/EWARM/project.ewd new file mode 100644 index 0000000..3cd3bd1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/EWARM/project.ewd @@ -0,0 +1,1484 @@ + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/EWARM/project.ewp new file mode 100644 index 0000000..70345d8 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/EWARM/project.ewp @@ -0,0 +1,2154 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 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a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/EWARM/project.eww new file mode 100644 index 0000000..c78ed98 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/MDK/project.uvoptx new file mode 100644 index 0000000..7e878f7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/MDK/project.uvoptx @@ -0,0 +1,326 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ATIM_BaseTimer + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_atim.c + cw32f030_atim.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/MDK/project.uvprojx new file mode 100644 index 0000000..eae4454 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/MDK/project.uvprojx @@ -0,0 +1,454 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + ATIM_BaseTimer + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.5 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + ATIM_BaseTimer + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_atim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_atim.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..9638565 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ +extern void ATIM_IRQHandlerCallBack(void); +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/USER/inc/main.h new file mode 100644 index 0000000..391ee15 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/USER/inc/main.h @@ -0,0 +1,65 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "cw32f030_atim.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "interrupts_cw32f030.h" +#include "system_cw32f030.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..99c9c52 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/USER/src/interrupts_cw32f030.c @@ -0,0 +1,406 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + ATIM_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/USER/src/main.c new file mode 100644 index 0000000..2e903e5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/USER/src/main.c @@ -0,0 +1,153 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void ATIM_IRQHandlerCallBack(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief ATIM边沿对齐模式，向上计数，PCLK作为时钟源 + * 中断服务程序中，检测溢出翻转PA0 + * @return int32_t + */ +int32_t main(void) +{ + ATIM_InitTypeDef ATIM_InitStruct; + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + ATIM_InitStruct.BufferState = ENABLE; //使能缓存寄存器 + ATIM_InitStruct.ClockSelect = ATIM_CLOCK_PCLK; //选择PCLK时钟计数 + ATIM_InitStruct.CounterAlignedMode = ATIM_COUNT_MODE_EDGE_ALIGN; //边沿对齐 + ATIM_InitStruct.CounterDirection = ATIM_COUNTING_UP; //向上计数； + ATIM_InitStruct.CounterOPMode = ATIM_OP_MODE_REPETITIVE; //连续运行模式 + ATIM_InitStruct.OverFlowMask = DISABLE; // 重复计数器上溢出不屏蔽 + ATIM_InitStruct.Prescaler = ATIM_Prescaler_DIV1; // 1分频 + ATIM_InitStruct.ReloadValue = 9999; // 重载周期9999+1 + ATIM_InitStruct.RepetitionCounter = 0; // 重复周期0 + ATIM_InitStruct.UnderFlowMask = DISABLE; // 重复计数下溢出不屏蔽 + ATIM_Init(&ATIM_InitStruct); + ATIM_ITConfig(ATIM_CR_IT_OVE, ENABLE); // 有重复计数器溢出产生进入中断 + ATIM_Cmd(ENABLE); + while (1) + { + /* 中断服务程序见ATIM_IRQHandlerCallBack() */ + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + RCC_HSI_Enable(RCC_HSIOSC_DIV6); // 配置PCLK为8MHz + __RCC_ATIM_CLK_ENABLE(); + __RCC_GPIOA_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_0; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(ATIM_IRQn); + __enable_irq(); +} + +void ATIM_IRQHandlerCallBack(void) +{ + if (ATIM_GetITStatus(ATIM_IT_OVF)) + { + ATIM_ClearITPendingBit(ATIM_IT_OVF); + PA00_TOG(); + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/readme.txt new file mode 100644 index 0000000..3f82842 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/ATIM_BaseTimer/readme.txt @@ -0,0 +1,26 @@ +示例目的： + 演示ATIM的基本计数用法。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. ATIM边沿计数，上计数模式，不分频，ARR设置为9999，溢出周期1.25ms + 5. PA00设置为PUSH-PULL输出 + +演示说明： + ATIM以8MHz时钟进行计数，设置ARR寄存器为9999，则ATIM将每1.25ms溢出一次，并触发 + 中断服务程序。中断服务程序中，PA00输出电平翻转。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/EWARM/project.ewd new file mode 100644 index 0000000..3cd3bd1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/EWARM/project.ewd @@ -0,0 +1,1484 @@ + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/EWARM/project.ewp new file mode 100644 index 0000000..6001d95 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/EWARM/project.ewp @@ -0,0 +1,2163 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_btim.c + + + + Utilities + + $PROJ_DIR$\..\..\..\..\Utilities\log.c + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/EWARM/project.eww new file mode 100644 index 0000000..c78ed98 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/MDK/project.uvoptx new file mode 100644 index 0000000..9a46981 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/MDK/project.uvoptx @@ -0,0 +1,391 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 171 + 1 +
1842
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\project\../USER/src/main.c\171 + + + + + 0 + 1 + duration + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\ATIM + 35905 + + + System Viewer\BTIM1 + 35904 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_atim.c + cw32f030_atim.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_btim.c + cw32f030_btim.c + 0 + 0 + + + + + Utilities + 1 + 0 + 0 + 0 + + 4 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Utilities\log.c + log.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/MDK/project.uvprojx new file mode 100644 index 0000000..38bbe95 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/MDK/project.uvprojx @@ -0,0 +1,472 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\Utilities + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + cw32f030_atim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_atim.c + + + cw32f030_btim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_btim.c + + + + + Utilities + + + log.c + 1 + ..\..\..\..\Utilities\log.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/USER/inc/main.h new file mode 100644 index 0000000..ea251e0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_atim.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_btim.h" +#include "log.h" +#include "cw32f030_uart.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +void GTIM1_IRQHandlerCallback(void); + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..9975ceb --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ +extern void ATIM_IRQHandlerCallBack(void); + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + ATIM_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/USER/src/main.c new file mode 100644 index 0000000..1293be6 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/USER/src/main.c @@ -0,0 +1,171 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void ATIM_IRQHandlerCallBack(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief 配置ATIM位主设备， BTIM1为从设备。 + * PB0作为TOGN指示BTIM1的工作状态 + * ATIM在计数溢出后，进中断服务程序，产生一个软件更新， + * BTIM1统计软件更新的个数。 + * + * @return int32_t + */ +int32_t main(void) +{ + ATIM_InitTypeDef ATIM_InitStruct; + BTIM_TimeBaseInitTypeDef BTIM_TimeBaseStruct; + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + LogInit(); + printf("Initial is beginning...\n"); + BTIM_TimeBaseStruct.BTIM_Mode = BTIM_Mode_COUNTER; + BTIM_TimeBaseStruct.BTIM_OPMode = BTIM_OPMode_Repetitive; + BTIM_TimeBaseStruct.BTIM_Period = 99; + BTIM_TimeBaseStruct.BTIM_Prescaler = BTIM_PRS_DIV1; + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_TimeBaseStruct); + BTIM_SelectInputTrigger(CW_BTIM1, BTIM_TS_ITR); + BTIM_Cmd(CW_BTIM1, ENABLE); + BTIM_OutputToggleCmd(CW_BTIM1, ENABLE); + RCC_BTIM1ITRSelect(RCC_TIMITR_ATIM); + ATIM_InitStruct.BufferState = DISABLE; + ATIM_InitStruct.ClockSelect = ATIM_CLOCK_PCLK; + ATIM_InitStruct.CounterAlignedMode = ATIM_COUNT_MODE_EDGE_ALIGN; + ATIM_InitStruct.CounterDirection = ATIM_COUNTING_UP; + ATIM_InitStruct.CounterOPMode = ATIM_OP_MODE_REPETITIVE; + ATIM_InitStruct.OverFlowMask = DISABLE; + ATIM_InitStruct.Prescaler = ATIM_Prescaler_DIV8; // 计算时钟1MHz + ATIM_InitStruct.ReloadValue = 99; // 溢出周期100us + ATIM_InitStruct.RepetitionCounter = 0; + ATIM_InitStruct.UnderFlowMask = DISABLE; + ATIM_Init(&ATIM_InitStruct); + ATIM_MasterModeConfig(ATIM_MASTER_OUTPUT_UG); + ATIM_ITConfig(ATIM_CR_IT_OVE, ENABLE); + ATIM_Cmd(ENABLE); + printf("ATIM is running.\n"); + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + __RCC_ATIM_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); + __RCC_BTIM_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_0; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + PB00_AFx_BTIM1TOGN(); + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(ATIM_IRQn); + __enable_irq(); +} + +void ATIM_IRQHandlerCallBack(void) +{ + if (ATIM_GetITStatus(ATIM_IT_OVF)) + { + ATIM_ClearITPendingBit(ATIM_IT_OVF); + CW_ATIM->CR_f.UG = 1; + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** +* @brief Reports the name of the source file and the source line number +* where the assert_param error has occurred. +* @param file: pointer to the source file name +* @param line: assert_param error line source number +* @retval None +*/ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/readme.txt new file mode 100644 index 0000000..36e7448 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_master_btim1_slaver/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 演示ATIM作为主机，BTIM作为从机的级联使用 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. ATIM边沿计数，上计数模式，8分频，ARR设置为99，溢出周期100us, 主模式 + 5. BTIM1使用ATIM的软件更新位UG作为计数时钟的来源，即100us计数一次，ARR设置为99， + 则BTIM1每10ms溢出一次。 + 6. PB00设置为BTIM1TOGN的输出。 + 7. 串口UART1作为调试串口,打印调试信息(PA8->TXD),波特率115200 +演示说明： + ATIM以1MHz时钟进行计数，设置ARR寄存器为99，则ATIM将每100us溢出一次，并触发 + 中断服务程序。中断服务程序中，对CR.UG位写1,向BTIM1提供计时信号。PB00将每10ms + 翻转一次. + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/EWARM/project.ewd new file mode 100644 index 0000000..3cd3bd1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/EWARM/project.ewd @@ -0,0 +1,1484 @@ + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/EWARM/project.ewp new file mode 100644 index 0000000..ca8702a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/EWARM/project.ewp @@ -0,0 +1,2166 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_btim.c + + + + Doc + + + Utilities + + $PROJ_DIR$\..\..\..\..\Utilities\log.c + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/EWARM/project.eww new file mode 100644 index 0000000..c78ed98 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/MDK/project.uvoptx new file mode 100644 index 0000000..8ab0400 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/MDK/project.uvoptx @@ -0,0 +1,421 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 111 + 1 +
5800
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\project\../USER/src/main.c\111 + + + 1 + 0 + 175 + 1 +
2026
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### uVision Project, (C) Keil Software
+ + + + project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\Utilities + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + cw32f030_atim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_atim.c + + + cw32f030_btim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_btim.c + + + + + Doc + + + Utilities + + + log.c + 1 + ..\..\..\..\Utilities\log.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/USER/inc/main.h new file mode 100644 index 0000000..a0f38f9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/USER/inc/main.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "cw32f030_atim.h" +#include "cw32f030_btim.h" +#include "cw32f030_flash.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030_uart.h" +#include "interrupts_cw32f030.h" +#include "log.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void GTIM1_IRQHandlerCallback(void); + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..9975ceb --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ +extern void ATIM_IRQHandlerCallBack(void); + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + ATIM_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/USER/src/main.c new file mode 100644 index 0000000..b05eebc --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/USER/src/main.c @@ -0,0 +1,220 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void ATIM_IRQHandlerCallBack(void); +void GenerateTestSignal(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +static uint32_t PWMPeriod = 0; +static uint32_t PWMWidth = 0; +static uint8_t ProcessState = 0; + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief 使用ATIM的CH1A通道对PWM输入信号进行测量，CH1A双边沿捕获测量周期与脉宽。 + * ATIM_CH1A：PB02 + * 将同一个PWM输入信号引入到PB02上。 + * PCLK的频率为8MHz + * 使用PA7作为BTIM1的TOGP输出，产生测试信号 + * @return int32_t + */ +int32_t main(void) +{ + ATIM_InitTypeDef ATIM_InitStruct; + ATIM_ICInitTypeDef ATIM_ICInitStruct; + ProcessState = 0; + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + LogInit(); + GenerateTestSignal(); + printf("Generating test signal\n"); + printf("ATIM Initial...\n"); + ATIM_InitStruct.BufferState = DISABLE; + ATIM_InitStruct.ClockSelect = ATIM_CLOCK_PCLK; + ATIM_InitStruct.CounterAlignedMode = ATIM_COUNT_MODE_EDGE_ALIGN; + ATIM_InitStruct.CounterDirection = ATIM_COUNTING_UP; + ATIM_InitStruct.CounterOPMode = ATIM_OP_MODE_REPETITIVE; + ATIM_InitStruct.OverFlowMask = DISABLE; + ATIM_InitStruct.Prescaler = ATIM_Prescaler_DIV1; + ATIM_InitStruct.ReloadValue = 0xFFFF; + ATIM_InitStruct.RepetitionCounter = 0; + ATIM_InitStruct.UnderFlowMask = DISABLE; + ATIM_Init(&ATIM_InitStruct); + ATIM_ICInitStruct.ICFilter = ATIM_ICFILTER_NONE; + ATIM_ICInitStruct.ICPolarity = ATIM_ICPOLARITY_BOTHEDGE; + ATIM_IC1AInit(&ATIM_ICInitStruct); + ATIM_ITConfig(ATIM_CR_IT_OVE, ENABLE); + ATIM_CH1Config(ATIM_CHxA_CIE, ENABLE); + ATIM_Cmd(ENABLE); + printf("ATIM is running.\n"); + while (1) + { + if (ProcessState == 1) + { + printf("Input PWM period is %dns\n", PWMPeriod * 125); + printf("Input PWM positive is %dns\n", PWMWidth * 125); + ProcessState = 0; + } + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + __RCC_ATIM_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_2; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + PB02_AFx_ATIMCH1A(); + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(ATIM_IRQn); + __enable_irq(); +} + +void ATIM_IRQHandlerCallBack(void) +{ + static uint8_t stage = 0; + static uint32_t cnt = 0; + if (ATIM_GetITStatus(ATIM_IT_OVF)) + { + ATIM_ClearITPendingBit(ATIM_IT_OVF); + if (stage) + { + cnt++; + } + } + if (ATIM_GetITStatus(ATIM_IT_C1AF)) + { + ATIM_ClearITPendingBit(ATIM_IT_C1AF); + if (stage == 0) + { + PWMPeriod = ATIM_GetCapture1A(); + cnt = 0; + stage++; + } + else if (stage == 1) + { + PWMWidth = ATIM_GetCapture1A() + cnt * 0x10000UL - PWMPeriod; + stage++; + } + else if (stage == 2) + { + PWMPeriod = ATIM_GetCapture1A() + cnt * 0x10000UL - PWMPeriod; + stage = 0; + ProcessState = 1; + } + } +} + +void GenerateTestSignal(void) +{ + BTIM_TimeBaseInitTypeDef BTIM_InitStruct = {0}; + GPIO_InitTypeDef GPIO_InitStruct = {0}; + BTIM_InitStruct.BTIM_Mode = BTIM_Mode_TIMER; + BTIM_InitStruct.BTIM_OPMode = BTIM_OPMode_Repetitive; + BTIM_InitStruct.BTIM_Period = 49; + BTIM_InitStruct.BTIM_Prescaler = BTIM_PRS_DIV16; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_7; + __RCC_BTIM_CLK_ENABLE(); + __RCC_GPIOA_CLK_ENABLE(); + PA07_AFx_BTIM1TOGP(); + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_InitStruct); + BTIM_OutputToggleCmd(CW_BTIM1, ENABLE); + BTIM_Cmd(CW_BTIM1, ENABLE); +} +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/readme.txt new file mode 100644 index 0000000..33aeaa1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_input/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 演示ATIM作为主机，BTIM作为从机的级联使用 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. ATIM边沿计数，上计数模式，不分频，ARR设置为0xFFFF， + 输入捕获, 使用CH1A双边沿捕获 + 5. BTIM1以500KHz的频率计时,ARR设置为49,以5KHz的频率硬件翻转TOGP引脚 + 6. PA07设置为BTIM1TOGP的输出。 + 7. 串口UART1作为调试串口,打印调试信息(PA8->TXD),波特率115200 + 8. PB02设置为ATIM_CH1A + +演示说明： + 使用杜邦线将PA07和PB02连接, UART1将打印PA02引脚信号的周期和正脉宽. + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/EWARM/project.ewd new file mode 100644 index 0000000..3cd3bd1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/EWARM/project.ewd @@ -0,0 +1,1484 @@ + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 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$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/EWARM/project.ewp new file mode 100644 index 0000000..6001d95 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/EWARM/project.ewp @@ -0,0 +1,2163 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + 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+ + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_atim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_btim.c + + + + Utilities + + $PROJ_DIR$\..\..\..\..\Utilities\log.c + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/EWARM/project.eww new file mode 100644 index 0000000..c78ed98 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/MDK/project.uvoptx new file mode 100644 index 0000000..74b2f7d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/MDK/project.uvoptx @@ -0,0 +1,357 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_atim.c + cw32f030_atim.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_btim.c + cw32f030_btim.c + 0 + 0 + + + + + Utilities + 1 + 0 + 0 + 0 + + 4 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Utilities\log.c + log.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/MDK/project.uvprojx new file mode 100644 index 0000000..38bbe95 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/MDK/project.uvprojx @@ -0,0 +1,472 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\Utilities + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + cw32f030_atim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_atim.c + + + cw32f030_btim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_btim.c + + + + + Utilities + + + log.c + 1 + ..\..\..\..\Utilities\log.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/USER/inc/main.h new file mode 100644 index 0000000..6d966f5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "cw32f030_atim.h" +#include "cw32f030_btim.h" +#include "cw32f030_flash.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030_uart.h" +#include "interrupts_cw32f030.h" +#include "log.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +void GTIM1_IRQHandlerCallback(void); + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..9975ceb --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ +extern void ATIM_IRQHandlerCallBack(void); + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + ATIM_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/USER/src/main.c new file mode 100644 index 0000000..1d2b281 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/USER/src/main.c @@ -0,0 +1,196 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void ATIM_IRQHandlerCallBack(void); +void GenerateTestSignal(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief 使用ATIM的CH2B通道输出PWM信号。PWM的频率设为100Hz + * ATIM_CH2B：PB14 + * PCLK的频率为8MHz + * PB14推动一个LED灯，实现呼吸灯的效果。设定5s完成50个等级的改变 + * @return int32_t + */ +int32_t main(void) +{ + ATIM_InitTypeDef ATIM_InitStruct; + ATIM_OCInitTypeDef ATIM_OCInitStruct; + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + LogInit(); + printf("ATIM Initial...\n"); + ATIM_InitStruct.BufferState = DISABLE; + ATIM_InitStruct.ClockSelect = ATIM_CLOCK_PCLK; + ATIM_InitStruct.CounterAlignedMode = ATIM_COUNT_MODE_EDGE_ALIGN; + ATIM_InitStruct.CounterDirection = ATIM_COUNTING_UP; + ATIM_InitStruct.CounterOPMode = ATIM_OP_MODE_REPETITIVE; + ATIM_InitStruct.OverFlowMask = DISABLE; + ATIM_InitStruct.Prescaler = ATIM_Prescaler_DIV8; // 计数时钟1MHz + ATIM_InitStruct.ReloadValue = 9999; // 溢出周期10ms + ATIM_InitStruct.RepetitionCounter = 0; + ATIM_InitStruct.UnderFlowMask = DISABLE; + ATIM_Init(&ATIM_InitStruct); + ATIM_OCInitStruct.BufferState = ENABLE; + ATIM_OCInitStruct.OCDMAState = DISABLE; + ATIM_OCInitStruct.OCInterruptSelect = ATIM_OC_IT_UP_COUNTER; + ATIM_OCInitStruct.OCInterruptState = ENABLE; + ATIM_OCInitStruct.OCMode = ATIM_OCMODE_PWM1; + ATIM_OCInitStruct.OCPolarity = ATIM_OCPOLARITY_NONINVERT; + ATIM_OC2BInit(&ATIM_OCInitStruct); + ATIM_ITConfig(ATIM_CR_IT_OVE, ENABLE); + ATIM_CH2Config(ATIM_CHxB_CIE, ENABLE); + ATIM_SetCompare2B(0); + ATIM_Cmd(ENABLE); + ATIM_CtrlPWMOutputs(ENABLE); + printf("ATIM is running.\n"); + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + __RCC_ATIM_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_14; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + PB14_AFx_ATIMCH2B(); + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(ATIM_IRQn); + __enable_irq(); +} + +void ATIM_IRQHandlerCallBack(void) +{ + static uint16_t duration = 0; + static uint8_t cnt = 1; + static uint8_t dir = 0; + if (ATIM_GetITStatus(ATIM_IT_OVF)) + { + ATIM_ClearITPendingBit(ATIM_IT_OVF); + if (cnt++ > 10) + { + cnt = 1; + if (!dir) + { + duration += 200; + if (duration >= 10000) + { + dir = 1; + } + } + else + { + duration -= 200; + if (duration == 0) + { + dir = 0; + } + } + ATIM_SetCompare2B(duration); + } + } + if (ATIM_GetITStatus(ATIM_IT_C2BF)) + { + ATIM_ClearITPendingBit(ATIM_IT_C2BF); + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/readme.txt new file mode 100644 index 0000000..917dc78 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output/readme.txt @@ -0,0 +1,27 @@ +示例目的： + 演示ATIM的输出比较功能,生成PWM波形 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. ATIM边沿计数，上计数模式，8分频，计数时钟1MHz,ARR设置为9999，10ms溢出, + 输出比较, 使用ATIM的CH2B通道输出PWM信号。PWM的频率设为100Hz + 5. 串口UART1作为调试串口,打印调试信息(PA8->TXD),波特率115200 + 6. PB14设置为ATIM_CH2B通道的输出. + +演示说明： + PB14推动一个LED灯，实现呼吸灯的效果。设定5s完成50个等级的改变. + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/EWARM/project.ewd new file mode 100644 index 0000000..3cd3bd1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/EWARM/project.ewd @@ -0,0 +1,1484 @@ + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/EWARM/project.ewp new file mode 100644 index 0000000..de82185 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/EWARM/project.ewp @@ -0,0 +1,2194 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 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$PROJ_DIR$\..\..\..\..\Utilities\log.c + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/EWARM/project.eww new file mode 100644 index 0000000..c78ed98 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/MDK/project.uvoptx new file mode 100644 index 0000000..57d962c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/MDK/project.uvoptx @@ -0,0 +1,370 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + JL2CM3 + -U4294967295 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030 -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + duration + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\ATIM + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_atim.c + cw32f030_atim.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_btim.c + cw32f030_btim.c + 0 + 0 + + + + + Utilities + 1 + 0 + 0 + 0 + + 4 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Utilities\log.c + log.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/MDK/project.uvprojx new file mode 100644 index 0000000..f3d48ec --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/MDK/project.uvprojx @@ -0,0 +1,471 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\Utilities + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + cw32f030_atim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_atim.c + + + cw32f030_btim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_btim.c + + + + + Utilities + + + log.c + 1 + ..\..\..\..\Utilities\log.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..9bc5b4d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,94 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/USER/inc/main.h new file mode 100644 index 0000000..a0f38f9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/USER/inc/main.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "cw32f030_atim.h" +#include "cw32f030_btim.h" +#include "cw32f030_flash.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030_uart.h" +#include "interrupts_cw32f030.h" +#include "log.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void GTIM1_IRQHandlerCallback(void); + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..187d79d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/USER/src/interrupts_cw32f030.c @@ -0,0 +1,396 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ +extern void ATIM_IRQHandlerCallBack(void); + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + ATIM_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/USER/src/main.c new file mode 100644 index 0000000..38b9d19 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/USER/src/main.c @@ -0,0 +1,180 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void ATIM_IRQHandlerCallBack(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief 使用ATIM的CH1通道输出互补PWM信号 + * ATIM_CH1A： PB2 + * ATIM_CH1B: PB13 + * PCLK的频率为8MHz + * + * @return int32_t + */ +int32_t main(void) +{ + ATIM_InitTypeDef ATIM_InitStruct; + ATIM_OCInitTypeDef ATIM_OCInitStruct; + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + LogInit(); + printf("ATIM Initial...\n"); + ATIM_InitStruct.BufferState = DISABLE; + ATIM_InitStruct.ClockSelect = ATIM_CLOCK_PCLK; + ATIM_InitStruct.CounterAlignedMode = ATIM_COUNT_MODE_EDGE_ALIGN; + ATIM_InitStruct.CounterDirection = ATIM_COUNTING_UP; + ATIM_InitStruct.CounterOPMode = ATIM_OP_MODE_REPETITIVE; + ATIM_InitStruct.OverFlowMask = DISABLE; + ATIM_InitStruct.Prescaler = ATIM_Prescaler_DIV8; // 计算时钟1MHz + ATIM_InitStruct.ReloadValue = 99; // 溢出周期100us + ATIM_InitStruct.RepetitionCounter = 0; + ATIM_InitStruct.UnderFlowMask = DISABLE; + ATIM_Init(&ATIM_InitStruct); + ATIM_OCInitStruct.BufferState = DISABLE; + ATIM_OCInitStruct.OCDMAState = DISABLE; + ATIM_OCInitStruct.OCInterruptSelect = ATIM_OC_IT_UP_COUNTER; + ATIM_OCInitStruct.OCInterruptState = ENABLE; + ATIM_OCInitStruct.OCMode = ATIM_OCMODE_PWM1; + ATIM_OCInitStruct.OCPolarity = ATIM_OCPOLARITY_NONINVERT; + ATIM_OC1AInit(&ATIM_OCInitStruct); + ATIM_OC1BInit(&ATIM_OCInitStruct); + ATIM_ITConfig(ATIM_CR_IT_OVE, ENABLE); + ATIM_CH1Config(ATIM_CHxB_CIE | ATIM_CHxA_CIE, ENABLE); + ATIM_SetCompare1A(50); + ATIM_SetCompare1B(90); + ATIM_PWMOutputConfig(OCREFA_TYPE_SINGLE, OUTPUT_TYPE_COMP, 1); + ATIM_CtrlPWMOutputs(ENABLE); + ATIM_Cmd(ENABLE); + printf("ATIM is running.\n"); + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + __RCC_ATIM_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_2 | GPIO_PIN_13; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + PB02_AFx_ATIMCH1A(); + PB13_AFx_ATIMCH1B(); + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(ATIM_IRQn); + __enable_irq(); +} + +void ATIM_IRQHandlerCallBack(void) +{ + if (ATIM_GetITStatus(ATIM_IT_OVF)) + { + ATIM_ClearITPendingBit(ATIM_IT_OVF); + } + if (ATIM_GetITStatus(ATIM_IT_C1BF)) + { + ATIM_ClearITPendingBit(ATIM_IT_C1BF); + } + if (ATIM_GetITStatus(ATIM_IT_C1AF)) + { + ATIM_ClearITPendingBit(ATIM_IT_C1AF); + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/readme.txt new file mode 100644 index 0000000..53dc897 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_pwm_output_comp/readme.txt @@ -0,0 +1,28 @@ +示例目的： + 演示ATIM的PWM互补输出功能 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. ATIM边沿计数，上计数模式，8分频，计数时钟1MHz,ARR设置为99，100us溢出, + 输出比较, 使用ATIM的CH1A和CH1B通道输出互补的PWM信号。 + 5. 串口UART1作为调试串口,打印调试信息(PA8->TXD),波特率115200 + 6. PB13设置为ATIM_CH1B通道的输出. + 7. PB02设置为ATIM_CH1A通道的输出. + +演示说明： + PB14推动一个LED灯，实现呼吸灯的效果。设定5s完成50个等级的改变. + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/EWARM/project.ewd new file mode 100644 index 0000000..4d9cc90 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/EWARM/project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/EWARM/project.ewp new file mode 100644 index 0000000..6001d95 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/EWARM/project.ewp @@ -0,0 +1,2163 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + 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Utilities + + $PROJ_DIR$\..\..\..\..\Utilities\log.c + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/EWARM/project.eww new file mode 100644 index 0000000..bc949a7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/EWARM/project.eww @@ -0,0 +1,6 @@ + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/MDK/project.uvoptx new file mode 100644 index 0000000..11908fb --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/MDK/project.uvoptx @@ -0,0 +1,364 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + duration + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_atim.c + cw32f030_atim.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_btim.c + cw32f030_btim.c + 0 + 0 + + + + + Utilities + 1 + 0 + 0 + 0 + + 4 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Utilities\log.c + log.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/MDK/project.uvprojx new file mode 100644 index 0000000..38bbe95 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/MDK/project.uvprojx @@ -0,0 +1,472 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\Utilities + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + cw32f030_atim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_atim.c + + + cw32f030_btim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_btim.c + + + + + Utilities + + + log.c + 1 + ..\..\..\..\Utilities\log.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..9638565 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ +extern void ATIM_IRQHandlerCallBack(void); +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/USER/inc/main.h new file mode 100644 index 0000000..36d4136 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/USER/inc/main.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "cw32f030_atim.h" +#include "cw32f030_btim.h" +#include "cw32f030_flash.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030_uart.h" +#include "interrupts_cw32f030.h" +#include "log.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..99c9c52 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/USER/src/interrupts_cw32f030.c @@ -0,0 +1,406 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + ATIM_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/USER/src/main.c new file mode 100644 index 0000000..e346b54 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/USER/src/main.c @@ -0,0 +1,168 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void ATIM_IRQHandlerCallBack(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief 配置ATIM为从设备， BTIM1为主设备。 + * BTIM1使用内部时钟PCLK计数，4分频，频率为1MHz，单次运行，50ms溢出，触发ATIM运行 + * + * @return int32_t + */ +int32_t main(void) +{ + ATIM_InitTypeDef ATIM_InitStruct; + BTIM_TimeBaseInitTypeDef BTIM_TimeBaseStruct; + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + LogInit(); + printf("Initial is beginning...\n"); + ATIM_InitStruct.BufferState = DISABLE; + ATIM_InitStruct.ClockSelect = ATIM_CLOCK_PCLK; + ATIM_InitStruct.CounterAlignedMode = ATIM_COUNT_MODE_EDGE_ALIGN; + ATIM_InitStruct.CounterDirection = ATIM_COUNTING_UP; + ATIM_InitStruct.CounterOPMode = ATIM_OP_MODE_SINGLE; + ATIM_InitStruct.OverFlowMask = DISABLE; + ATIM_InitStruct.Prescaler = ATIM_Prescaler_DIV1; // 计算时钟4MHz + ATIM_InitStruct.ReloadValue = 39999; // 溢出周期10ms + ATIM_InitStruct.RepetitionCounter = 0; + ATIM_InitStruct.UnderFlowMask = DISABLE; + ATIM_Init(&ATIM_InitStruct); + ATIM_SlaverModeConfig(ATIM_SLAVER_TYPE_TRIGGER); + ATIM_TriggerSelect(ATIM_TRIGGER_SOURCE_ITR); + ATIM_ITConfig(ATIM_CR_IT_OVE, ENABLE); + RCC_ATIMITRSelect(RCC_TIMITR_BTIM1); + BTIM_TimeBaseStruct.BTIM_Mode = BTIM_Mode_TIMER; + BTIM_TimeBaseStruct.BTIM_OPMode = BTIM_OPMode_Repetitive; + BTIM_TimeBaseStruct.BTIM_Period = 49999; + BTIM_TimeBaseStruct.BTIM_Prescaler = BTIM_PRS_DIV4; + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_TimeBaseStruct); + BTIM_OutputToggleCmd(CW_BTIM1, ENABLE); + BTIM_Cmd(CW_BTIM1, ENABLE); + printf("ATIM is running.\n"); + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + RCC_HSI_Enable(RCC_HSIOSC_DIV12); + __RCC_ATIM_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); + __RCC_BTIM_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_0 | GPIO_PIN_9; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + PB00_AFx_BTIM1TOGN(); + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + PB09_SETLOW(); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(ATIM_IRQn); + __enable_irq(); +} + +void ATIM_IRQHandlerCallBack(void) +{ + if (ATIM_GetITStatus(ATIM_IT_OVF)) + { + ATIM_ClearITPendingBit(ATIM_IT_OVF); + PB09_TOG(); + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/readme.txt new file mode 100644 index 0000000..d621ec6 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_slaver_btim1_master/readme.txt @@ -0,0 +1,32 @@ +示例目的： + 演示ATIM作为从设备，配合BTIM主设备的使用 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟12分频，4MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=4MHz + 4. ATIM边沿计数，上计数模式，不分频，计数时钟4MHz,ARR设置为39999，10ms溢出, + 单次运行。溢出中断程序中翻转PB09的电平输出。 + 5. 串口UART1作为调试串口,打印调试信息(PA8->TXD),波特率115200 + 6. PB09设置为PUSH-PULL输出. + 7. PB00设置为BTIM1的TOGN. + 8. BTIM1使用内部时钟PCLK计数，4分频，频率为1MHz，单次运行，50ms溢出，触发ATIM运行 + +演示说明： + 程序运行后，BTIM1每50ms溢出触发ATIM启动一次计时，ATIM计时10ms后停止， + BTIM1每次溢出后PB00的电平翻转一次，ATIM溢出后，计时停止，并翻转PB09的电平 + 因PB00和PB09的初始电平相同，PB09的波形比PB00延时10ms + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/EWARM/project.ewd new file mode 100644 index 0000000..3cd3bd1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/EWARM/project.ewd @@ -0,0 +1,1484 @@ + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/EWARM/project.ewp new file mode 100644 index 0000000..79249ae --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/EWARM/project.ewp @@ -0,0 +1,2163 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Utilities\cw32f030c8t6_startkit.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_adc.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/EWARM/project.eww new file mode 100644 index 0000000..c78ed98 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/MDK/project.uvoptx new file mode 100644 index 0000000..8373326 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/MDK/project.uvoptx @@ -0,0 +1,386 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=120,153,364,299,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U4294967295 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030_72K -FS00 -FL012000 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 81 + 1 +
3810
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\project\../USER/src/main.c\81 + + + + + 0 + 1 + ADC_ConvertedVoltage + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_atim.c + cw32f030_atim.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Utilities\cw32f030c8t6_startkit.c + cw32f030c8t6_startkit.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_adc.c + cw32f030_adc.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/MDK/project.uvprojx new file mode 100644 index 0000000..e185000 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/MDK/project.uvprojx @@ -0,0 +1,470 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\Utilities + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_atim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_atim.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030c8t6_startkit.c + 1 + ..\..\..\..\Utilities\cw32f030c8t6_startkit.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + cw32f030_adc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_adc.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/USER/inc/main.h new file mode 100644 index 0000000..47dee2a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "cw32f030_adc.h" +#include "cw32f030_atim.h" +#include "cw32f030_flash.h" +#include "cw32f030_gpio.h" +#include "cw32f030_iwdt.h" +#include "cw32f030_rcc.h" +#include "cw32f030c8t6_startkit.h" +#include "interrupts_cw32f030.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ +extern uint16_t ADC_ConvertedValue; +extern float ADC_ConvertedVoltage; +extern uint8_t ADC_ConvertedFlag; + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..f9c68ca --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/USER/src/interrupts_cw32f030.c @@ -0,0 +1,412 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ +extern void ATIM_IRQHandlerCallBack(void); +extern void ADC_IRQHandlerCallBack(void); + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + ADC_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + ATIM_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/USER/src/main.c new file mode 100644 index 0000000..cdae36e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/USER/src/main.c @@ -0,0 +1,238 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void ATIM_IRQHandlerCallBack(void); +static void ATIM_Config(void); +static void ADC_Config(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint16_t ADC_ConvertedValue = 0; +float ADC_ConvertedVoltage = 0.0; +uint8_t ADC_ConvertedFlag = 0; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief 本例中，ATIM在PWM模式下配置，ATIM的OC3B时间用于触发ADC + * ADC配置为单通道单次转换 + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + RCC_Configuration(); // HSI时钟源，PLL倍频64MHz，PCLK=HCLK=64MHz + /* GPIO Configuration */ + GPIO_Configuration(); + ATIM_Config(); + ADC_Config(); + /* NVIC Configuration */ + NVIC_Configuration(); + while (1) + { + if (ADC_ConvertedFlag) + { + ADC_ConvertedFlag = 0; + ADC_ConvertedVoltage = ADC_ConvertedValue * 3.3 / 0xfff; + } + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + /* 0. HSI使能并校准 */ + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + /* 1. 设置HCLK和PCLK的分频系数　*/ + RCC_HCLKPRS_Config(RCC_HCLK_DIV1); + RCC_PCLKPRS_Config(RCC_PCLK_DIV1); + /* 2. 使能PLL，通过HSI倍频到64MHz */ + RCC_PLL_Enable(RCC_PLLSOURCE_HSI, 8000000, 8); // HSI 默认输出频率8MHz + RCC_PLL_OUT(); + ///< 当使用的时钟源HCLK大于48M,小于等于72MHz：设置FLASH 读等待周期为3 cycle + __RCC_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_3); + /* 3. 时钟切换到PLL */ + RCC_SysClk_Switch(RCC_SYSCLKSRC_PLL); + RCC_SystemCoreClockUpdate(64000000); + /* 4.使能外设时钟 */ + __RCC_GPIOA_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); + __RCC_ATIM_CLK_ENABLE(); + __RCC_ADC_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_9; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + PB00_ANALOG_ENABLE(); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_0; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); +} + +/** + * @brief ATIM边沿对齐，上计数，64分频，DCLK=1MHz，period=10ms + * OC3B匹配事件触发ADC + */ +static void ATIM_Config(void) +{ + ATIM_InitTypeDef ATIM_InitStruct; + ATIM_OCInitTypeDef ATIM_OCInitStruct; + __RCC_ATIM_CLK_ENABLE(); + ATIM_InitStruct.BufferState = ENABLE; //使能缓存寄存器 + ATIM_InitStruct.ClockSelect = ATIM_CLOCK_PCLK; //选择PCLK时钟计数 + ATIM_InitStruct.CounterAlignedMode = ATIM_COUNT_MODE_EDGE_ALIGN; //边沿对齐 + ATIM_InitStruct.CounterDirection = ATIM_COUNTING_UP; //向上计数； + ATIM_InitStruct.CounterOPMode = ATIM_OP_MODE_REPETITIVE; //连续运行模式 + ATIM_InitStruct.OverFlowMask = DISABLE; // 重复计数器上溢出不屏蔽 + ATIM_InitStruct.Prescaler = ATIM_Prescaler_DIV64; // 1分频 + ATIM_InitStruct.ReloadValue = 9999; // 重载周期9999+1 + ATIM_InitStruct.RepetitionCounter = 0; // 重复周期0 + ATIM_InitStruct.UnderFlowMask = DISABLE; // 重复计数下溢出不屏蔽 + ATIM_Init(&ATIM_InitStruct); + ATIM_OCInitStruct.BufferState = DISABLE; + ATIM_OCInitStruct.OCDMAState = DISABLE; + ATIM_OCInitStruct.OCInterruptSelect = ATIM_OC_IT_UP_COUNTER; + ATIM_OCInitStruct.OCInterruptState = DISABLE; + ATIM_OCInitStruct.OCMode = ATIM_OCMODE_PWM1; + ATIM_OCInitStruct.OCPolarity = ATIM_OCPOLARITY_NONINVERT; + ATIM_OC3BInit(&ATIM_OCInitStruct); + ATIM_ADCTriggerConfig(ATIM_ADC_TRIGGER_CH3B, ENABLE); + ATIM_SetCompare3B(4999); + ATIM_ITConfig(ATIM_CR_IT_OVE, ENABLE); + ATIM_Cmd(ENABLE); +} + +/** + * @brief ADC 使用通道8单次转换，转换结束后触发中断 + * + */ +static void ADC_Config(void) +{ + ADC_InitTypeDef ADC_InitStruct; + __RCC_ADC_CLK_ENABLE(); + ADC_InitStruct.ADC_AccEn = DISABLE; + ADC_InitStruct.ADC_Align = ADC_AlignRight; + ADC_InitStruct.ADC_ClkDiv = ADC_Clk_Div4; // ADCCLK=16MHz + ADC_InitStruct.ADC_DMAEn = DISABLE; + ADC_InitStruct.ADC_InBufEn = DISABLE; + ADC_InitStruct.ADC_OpMode = ADC_SingleChOneMode; + ADC_InitStruct.ADC_SampleTime = ADC_SampTime5Clk; + ADC_InitStruct.ADC_TsEn = DISABLE; + ADC_InitStruct.ADC_VrefSel = ADC_Vref_VDDA; + ADC_Init(&ADC_InitStruct); + CW_ADC->CR1_f.CHMUX = 8; // PB0 + ADC_ExtTrigCfg(ADC_TRIG_ATIM, ENABLE); + ADC_ITConfig(ADC_IT_EOC, ENABLE); + ADC_Enable(); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(ATIM_IRQn); + NVIC_EnableIRQ(ADC_IRQn); + __enable_irq(); +} + +void ATIM_IRQHandlerCallBack(void) +{ + if (ATIM_GetITStatus(ATIM_IT_OVF)) + { + ATIM_ClearITPendingBit(ATIM_IT_OVF); + PB09_TOG(); + } +} + +void ADC_IRQHandlerCallBack(void) +{ + if (ADC_GetITStatus(ADC_IT_EOC)) + { + ADC_ClearITPendingBit(ADC_IT_EOC); + ADC_ConvertedValue = ADC_GetConversionValue(); + ADC_ConvertedFlag = 1; + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/readme.txt new file mode 100644 index 0000000..a2cd7ad --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/ATIM/atim_trigger_adc/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 演示ATIM触发ADC采样的功能。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，通过PLL倍频到64MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=64MHz + 4. ATIM边沿计数，上计数模式，64分频，ARR设置为9999，溢出周期10ms, + 当OC3B匹配事件发生时触发ADC + 5. ADC 使用通道8单次转换，转换结束后触发中断 + 6. PB00设置为ADC的输入 + 7. PB09设置为PUSH-PULL输出 + +演示说明： + 本例中，ATIM在PWM模式下配置ATIM的OC3B时间用于触发ADC + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + 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$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/EWARM/Project.ewp new file mode 100644 index 0000000..58db4c3 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/EWARM/Project.ewp @@ -0,0 +1,2160 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_awt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/MDK/Project.uvoptx new file mode 100644 index 0000000..0fbc4e6 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/MDK/Project.uvoptx @@ -0,0 +1,333 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FN1 -FC1000 -FD20000000 -FF0FlashCW32F030 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FS00 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_awt.c + cw32f030_awt.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/MDK/Project.uvprojx new file mode 100644 index 0000000..f07396c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/MDK/Project.uvprojx @@ -0,0 +1,459 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030 -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_awt.c + 1 + ..\..\..\..\Libraries\src\cw32f030_awt.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/USER/inc/main.h new file mode 100644 index 0000000..2f6160d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..d4fc5c1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/USER/src/interrupts_cw32f030.c @@ -0,0 +1,412 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_awt.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +extern uint8_t intflag; +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + intflag = 1; + AWT_ClearITPendingBit(AWT_IT_UD); + //CW_GPIOF->TOG |= 3; + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/USER/src/main.c new file mode 100644 index 0000000..5a7c36b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/USER/src/main.c @@ -0,0 +1,177 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-18 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_awt.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_systick.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +AWT_TimeCntInitTypeDef AWT_TimeCntInitStruct; + +uint8_t intflag; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle GPIOA.00 + ** + ******************************************************************************/ +int32_t main(void) +{ + RCC_APBPeriphClk_Enable2(RCC_APB2_PERIPH_AWT, ENABLE); //Open AWT and GPIOA Clk + RCC_AHBPeriphClk_Enable(RCC_AHB_PERIPH_GPIOA | RCC_AHB_PERIPH_GPIOB | RCC_AHB_PERIPH_GPIOF, ENABLE); //Open GPIOA &GPIOB Clk + /* NVIC Configuration */ + NVIC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + RCC_SystemCoreClockUpdate(RCC_Sysctrl_GetHClkFreq()); + PB08_SETHIGH(); + PB09_SETHIGH(); + FirmwareDelay(2000000); + PB08_SETLOW(); + PB09_SETLOW(); + FirmwareDelay(2000000); + RCC_LSE_Enable(RCC_LSE_MODE_OSC, RCC_LSE_AMP_NORMAL, RCC_LSE_DRIVER_LARGER); + AWT_TimeCntStructInit(&AWT_TimeCntInitStruct); + AWT_TimeCntInitStruct.AWT_ClkSource = AWT_CLKSOURCE_LSE; + AWT_TimeCntInitStruct.AWT_Prescaler = AWT_PRS_DIV32768; + AWT_TimeCntInitStruct.AWT_Mode = AWT_MODE_TIMECNT; + AWT_TimeCntInitStruct.AWT_Period = 4; + AWT_TimeCntInit(&AWT_TimeCntInitStruct); + intflag = 0; + //使能AWT下溢出中断 + AWT_ITConfig(AWT_IT_UD, ENABLE); + AWT_Cmd(ENABLE); + //DeepSleep唤醒时，保持原系统时钟来源 + RCC_WAKEUPCLK_Config(RCC_SYSCTRL_WAKEUPCLKDIS); + while (1) + { + //进入深度睡眠模式前，须降低系统频率到4M以下。当前为HSIOSC时钟，48M，6分频后HCLK为8M。 + RCC_HSI_Enable(RCC_HSIOSC_DIV12); //48M/12=4M + SCB->SCR = 0X04; + __WFI(); + //退出深度睡眠模式，恢复原时钟频率。 + RCC_HSI_Enable(RCC_HSIOSC_DIV6); //48M/6=8M + if (intflag == 1) + { + intflag = 0; + for (uint8_t i = 0; i < 6; i++) + { + PB08_TOG(); + PB09_TOG(); + FirmwareDelay(100000); + } + } + FirmwareDelay(500000); + } +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + //PB8/PB9 推挽输出 + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + PB08_SETLOW(); + PB09_SETLOW(); +} + + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(AWT_IRQn); + __enable_irq(); +} + + + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/readme.txt new file mode 100644 index 0000000..d11e220 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSE/readme.txt @@ -0,0 +1,24 @@ +示例目的： + AWT采用LSI作为工作时钟，进行AWT的休眠唤醒测试 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟LSE + 3. 系统时钟设置为LSE，32.768KHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=32.768KHz + 4. AWT的时钟设置为LSE，32768分频 + +演示说明： + AWT以1Hz时钟进行计数，设置ARR寄存器为4，则AWT将每5S溢出一次，产生溢出中断标志。程序完成定时器相关参数设置，并打开定时器溢出中断，然后进入低功耗，等待被AWT溢出中断唤醒。当5S时间到后，AWT溢出中断标志产生，唤醒MCU，进入中断处理，然后接着处理主循环中睡眠指令后面的任务。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_awt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/MDK/Project.uvoptx new file mode 100644 index 0000000..25d62ef --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/MDK/Project.uvoptx @@ -0,0 +1,338 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_awt.c + cw32f030_awt.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/MDK/Project.uvprojx new file mode 100644 index 0000000..72cf38b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/MDK/Project.uvprojx @@ -0,0 +1,459 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 0 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_awt.c + 1 + ..\..\..\..\Libraries\src\cw32f030_awt.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/USER/inc/main.h new file mode 100644 index 0000000..2f6160d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..d4fc5c1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/USER/src/interrupts_cw32f030.c @@ -0,0 +1,412 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_awt.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +extern uint8_t intflag; +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + intflag = 1; + AWT_ClearITPendingBit(AWT_IT_UD); + //CW_GPIOF->TOG |= 3; + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/USER/src/main.c new file mode 100644 index 0000000..0b79325 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/USER/src/main.c @@ -0,0 +1,178 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-18 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_awt.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_flash.h" +#include "cw32f030_systick.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +AWT_TimeCntInitTypeDef AWT_TimeCntInitStruct; + +uint8_t intflag; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle GPIOA.00 + ** + ******************************************************************************/ +int32_t main(void) +{ + RCC_APBPeriphClk_Enable2(RCC_APB2_PERIPH_AWT, ENABLE); //Open AWT Clk + RCC_AHBPeriphClk_Enable(RCC_AHB_PERIPH_GPIOA | RCC_AHB_PERIPH_GPIOB | RCC_AHB_PERIPH_GPIOF, ENABLE); //Open GPIOA & GPIOB & GPIOF Clk + /* NVIC Configuration */ + NVIC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + RCC_SystemCoreClockUpdate(RCC_Sysctrl_GetHClkFreq()); + PB08_SETHIGH(); + PB09_SETHIGH(); + FirmwareDelay(2000000); + PB08_SETLOW(); + PB09_SETLOW(); + FirmwareDelay(2000000); + RCC_LSI_Enable(); + AWT_TimeCntStructInit(&AWT_TimeCntInitStruct); + AWT_TimeCntInitStruct.AWT_ClkSource = AWT_CLKSOURCE_LSI; + AWT_TimeCntInitStruct.AWT_Prescaler = AWT_PRS_DIV32768; + AWT_TimeCntInitStruct.AWT_Mode = AWT_MODE_TIMECNT; + AWT_TimeCntInitStruct.AWT_Period = 4; + AWT_TimeCntInit(&AWT_TimeCntInitStruct); + intflag = 0; + //使能AWT下溢出中断 + AWT_ITConfig(AWT_IT_UD, ENABLE); + AWT_Cmd(ENABLE); + //DeepSleep唤醒时，保持原系统时钟来源 + RCC_WAKEUPCLK_Config(RCC_SYSCTRL_WAKEUPCLKDIS); + while (1) + { + //进入深度睡眠模式前，须降低系统频率到4M以下。当前为HSIOSC时钟，48M，6分频后HCLK为8M。 + RCC_HSI_Enable(RCC_HSIOSC_DIV12); //48M/12=4M + SCB->SCR = 0X04; + __WFI(); + //退出深度睡眠模式，恢复原时钟频率。 + RCC_HSI_Enable(RCC_HSIOSC_DIV6); //48M/6=8M + if (intflag == 1) + { + intflag = 0; + for (uint8_t i = 0; i < 6; i++) + { + PB08_TOG(); + PB09_TOG(); + FirmwareDelay(100000); + } + } + FirmwareDelay(500000); + } +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + //PB8/PB9 推挽输出 + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + PB08_SETLOW(); + PB09_SETLOW(); +} + + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(AWT_IRQn); + __enable_irq(); +} + + + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/readme.txt new file mode 100644 index 0000000..8f23d1a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_DeepSleep_LSI/readme.txt @@ -0,0 +1,24 @@ +示例目的： + AWT采用LSI作为工作时钟，进行AWT的休眠唤醒测试 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟LSI + 3. 系统时钟设置为LSI，32.768KHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=32.768KHz + 4. AWT的时钟设置为LSI，32768分频 + +演示说明： + AWT以1Hz时钟进行计数，设置ARR寄存器为4，则AWT将每5S溢出一次，产生溢出中断标志。程序完成定时器相关参数设置，并打开定时器溢出中断，然后进入低功耗，等待被AWT溢出中断唤醒。当5S时间到后，AWT溢出中断标志产生，唤醒MCU，进入中断处理，然后接着处理主循环中睡眠指令后面的任务。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/EWARM/Awt_timer.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/EWARM/Awt_timer.ewp new file mode 100644 index 0000000..b88dbd6 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/EWARM/Awt_timer.ewp @@ -0,0 +1,2154 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/EWARM/Project.ewp new file mode 100644 index 0000000..b88dbd6 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/EWARM/Project.ewp @@ -0,0 +1,2154 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/MDK/Awt_timer.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/MDK/Awt_timer.uvoptx new file mode 100644 index 0000000..f71c2eb --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/MDK/Awt_timer.uvoptx @@ -0,0 +1,321 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Awt_timer + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + -UV0010M9E -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_awt.c + cw32f030_awt.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/MDK/Awt_timer.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/MDK/Awt_timer.uvprojx new file mode 100644 index 0000000..29f3173 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/MDK/Awt_timer.uvprojx @@ -0,0 +1,454 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Awt_timer + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030 -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Awt_timer + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_awt.c + 1 + ..\..\..\..\Libraries\src\cw32f030_awt.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/USER/inc/main.h new file mode 100644 index 0000000..208c89a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/USER/inc/main.h @@ -0,0 +1,68 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/USER/src/main.c new file mode 100644 index 0000000..9ceece2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/USER/src/main.c @@ -0,0 +1,149 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-18 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_awt.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_systick.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +AWT_TimeCntInitTypeDef AWT_TimeCntInitStruct; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle PB08、PB09 + ** + ******************************************************************************/ +int32_t main(void) +{ + RCC_APBPeriphClk_Enable2(RCC_APB2_PERIPH_AWT, ENABLE); //Open AWT Clk + RCC_AHBPeriphClk_Enable(RCC_AHB_PERIPH_GPIOA | RCC_AHB_PERIPH_GPIOB, ENABLE); //Open GPIOA &GPIOB Clk + /* NVIC Configuration */ + NVIC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + AWT_TimeCntStructInit(&AWT_TimeCntInitStruct); + AWT_TimeCntInitStruct.AWT_ClkSource = AWT_CLKSOURCE_HSIOSC; + AWT_TimeCntInitStruct.AWT_Prescaler = AWT_PRS_DIV32768; + AWT_TimeCntInitStruct.AWT_Mode = AWT_MODE_TIMECNT; + AWT_TimeCntInitStruct.AWT_Period = 145; + AWT_TimeCntInit(&AWT_TimeCntInitStruct); + AWT_Cmd(ENABLE); + while (1) + { + //查询溢出标志，清标志，闪灯，用示波器观测PB08及PB09口线波形，测量定时时间是否正确 + if (SET == AWT_GetITStatus(AWT_IT_UD)) + { + AWT_ClearITPendingBit(AWT_IT_UD); + PB08_TOG(); + PB09_TOG(); + } + } +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + //PB8/PB9 推挽输出 + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + PB08_SETLOW(); + PB09_SETLOW(); +} + + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ +} + + + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/readme.txt new file mode 100644 index 0000000..f06c9c5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/AWT/Awt_timer/readme.txt @@ -0,0 +1,25 @@ +示例目的： + 控制AWT定时器以固定的时间间隔产生中断，并在中断中控制口线电平翻转 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. AWT的时钟设置为HSIOSC，32768分频 + 5. PB08、PB09设置为PUSH-PULL输出 + +演示说明： + AWT以48/32768 MHz时钟进行计数，设置ARR寄存器为145，则AWT将每100ms溢出一次，并产生溢出标志。程序循环查询溢出溢出标志，溢出标志有效后，清除标志，并进行PB08和PB09端口翻转。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/EWARM/project.ewd new file mode 100644 index 0000000..6ff2a70 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/EWARM/project.ewd @@ -0,0 +1,3088 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 32 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + 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$PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + $PROJ_DIR$\..\USER\src\main.c + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/EWARM/project.eww new file mode 100644 index 0000000..bc949a7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/EWARM/project.eww @@ -0,0 +1,6 @@ + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/MDK/project.uvoptx new file mode 100644 index 0000000..f19fc30 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/MDK/project.uvoptx @@ -0,0 +1,327 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + BaseTimer + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FN1 -FC1000 -FD20000000 -FF0FlashCW32F030 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FS00 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\BTIM1 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_btim.c + cw32f030_btim.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/MDK/project.uvprojx new file mode 100644 index 0000000..de0793b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/MDK/project.uvprojx @@ -0,0 +1,455 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + BaseTimer + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030 -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + BaseTimer + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_btim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_btim.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/USER/inc/main.h new file mode 100644 index 0000000..1c25914 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_btim.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..bafd80b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/USER/src/interrupts_cw32f030.c @@ -0,0 +1,413 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + if (BTIM_GetITStatus(CW_BTIM1, BTIM_IT_OV)) + { + BTIM_ClearITPendingBit(CW_BTIM1, BTIM_IT_OV); + PB09_TOG(); + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/USER/src/main.c new file mode 100644 index 0000000..704c3c8 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/USER/src/main.c @@ -0,0 +1,141 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-08-23 + * + * @copyright Copyright (c) 2021 + * +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +BTIM_TimeBaseInitTypeDef BTIM_TimeBaseInitStruct; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + RCC_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + BTIM_TimeBaseInitStruct.BTIM_Mode = BTIM_Mode_TIMER; + BTIM_TimeBaseInitStruct.BTIM_Period = 49999; + BTIM_TimeBaseInitStruct.BTIM_Prescaler = BTIM_PRS_DIV8; + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_TimeBaseInitStruct); + BTIM_ITConfig(CW_BTIM1, BTIM_IT_OV, ENABLE); + BTIM_Cmd(CW_BTIM1, ENABLE); + while (1) + { + /* 中断服务程序中 PB9输出翻转 */ + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + // CW_SYSCTRL->APBEN2_f.BTIM = 1U; + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + __RCC_BTIM_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_9; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(BTIM1_IRQn); + __enable_irq(); +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/readme.txt new file mode 100644 index 0000000..4e109ca --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer/readme.txt @@ -0,0 +1,26 @@ +示例目的： + 控制基本定时器BTIM1以固定的时间间隔产生中断，并在中断中控制口线电平翻转 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. BTIM1的时钟设置为PCLK，8分频 + 5. PB09设置为PUSH-PULL输出 + +演示说明： + BTIM1以1MHz时钟进行计数，设置ARR寄存器为49999，则BTIM1将每50ms溢出一次，并触发 + 中断服务程序。中断服务程序中，PB09输出电平翻转，LED1将10Hz的频率闪烁。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/EWARM/Project.ewd new file mode 100644 index 0000000..4564814 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/EWARM/Project.ewp new file mode 100644 index 0000000..cc7d14c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/EWARM/Project.ewp @@ -0,0 +1,2154 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/EWARM/Project.eww new file mode 100644 index 0000000..284f58c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/EWARM/Project.eww @@ -0,0 +1,6 @@ + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/MDK/Project.uvoptx new file mode 100644 index 0000000..360330f --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/MDK/Project.uvoptx @@ -0,0 +1,338 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + ((BTIM_TypeDef*) 0x40014800UL) + + + 1 + 1 + BTIM_TimeBaseInitStruct + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_btim.c + cw32f030_btim.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/MDK/Project.uvprojx new file mode 100644 index 0000000..8d80460 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/MDK/Project.uvprojx @@ -0,0 +1,455 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_btim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_btim.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/USER/inc/main.h new file mode 100644 index 0000000..1c25914 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_btim.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..240d0a0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/USER/src/interrupts_cw32f030.c @@ -0,0 +1,412 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ +extern void BTIM1_IRQHandleCallback(void); +extern void BTIM2_IRQHandleCallback(void); +extern void BTIM3_IRQHandleCallback(void); + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + BTIM1_IRQHandleCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + BTIM2_IRQHandleCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + BTIM3_IRQHandleCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/USER/src/main.c new file mode 100644 index 0000000..abfc937 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/USER/src/main.c @@ -0,0 +1,184 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-08-23 + * + * @copyright Copyright (c) 2021 + * +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +BTIM_TimeBaseInitTypeDef BTIM_TimeBaseInitStruct; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + RCC_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + /* 使用BTIM1的OV信号作为BTIM2的ITR输入，实现对PCLK的任意分频 */ + BTIM_TimeBaseInitStruct.BTIM_Mode = BTIM_Mode_TIMER; + BTIM_TimeBaseInitStruct.BTIM_Period = 49999; + BTIM_TimeBaseInitStruct.BTIM_Prescaler = BTIM_PRS_DIV8; + BTIM_TimeBaseInitStruct.BTIM_OPMode = BTIM_OPMode_Repetitive; + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_TimeBaseInitStruct); + BTIM_TimeBaseInitStruct.BTIM_Mode = BTIM_Mode_COUNTER; + BTIM_TimeBaseInitStruct.BTIM_Period = 9; + BTIM_TimeBaseInitStruct.BTIM_Prescaler = BTIM_PRS_DIV1; + BTIM_TimeBaseInitStruct.BTIM_OPMode = BTIM_OPMode_Repetitive; + BTIM_TimeBaseInit(CW_BTIM2, &BTIM_TimeBaseInitStruct); + RCC_BTIM2ITRSelect(RCC_TIMITR_BTIM1); + BTIM_SelectInputTrigger(CW_BTIM2, BTIM_TS_ITR); + BTIM_OutputToggleCmd(CW_BTIM2, ENABLE); // BTIM2的toggle输出使能，用于测量 + BTIM_ITConfig(CW_BTIM1, BTIM_IT_OV, ENABLE); + BTIM_ITConfig(CW_BTIM2, BTIM_IT_OV, ENABLE); + BTIM_Cmd(CW_BTIM2, ENABLE); + BTIM_Cmd(CW_BTIM1, ENABLE); + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + // CW_SYSCTRL->APBEN2_f.BTIM = 1U; + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + __RCC_BTIM_CLK_ENABLE(); + __RCC_GPIOA_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_5; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); // PA5 + PA05_AFx_BTIM2TOGP(); // BTIM2的TOG输出分配到PA5 + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_9 | GPIO_PIN_8; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + PB09_SETLOW(); + PB08_SETLOW(); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(BTIM1_IRQn); + NVIC_EnableIRQ(BTIM2_IRQn); + __enable_irq(); +} + +void BTIM1_IRQHandleCallback(void) +{ + if (BTIM_GetITStatus(CW_BTIM1, BTIM_IT_OV)) + { + BTIM_ClearITPendingBit(CW_BTIM1, BTIM_IT_OV); + PB09_TOG(); + } +} + +void BTIM2_IRQHandleCallback(void) +{ + if (BTIM_GetITStatus(CW_BTIM2, BTIM_IT_OV)) + { + BTIM_ClearITPendingBit(CW_BTIM2, BTIM_IT_OV); + PB08_TOG(); + } +} + +void BTIM3_IRQHandleCallback(void) +{ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/readme.txt new file mode 100644 index 0000000..17cc80a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_BTIM1andBTIM2ITR/readme.txt @@ -0,0 +1,31 @@ +示例目的： + 控制基本定时器BTIM1与BTIM2内部级联，扩展定时器的计数/计时范围 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. BTIM1的时钟设置为PCLK，8分频 + 5. BTIM2的时钟为BTIM1的OV信号，不分频 + 6. PB09设置为PUSH-PULL输出 + 7. PB08设置为PUSH-PULL输出 + 8. PA05设置为BTIM2的TOGP输出 + +演示说明： + BTIM1以1MHz时钟进行计数，设置ARR寄存器为49999，则BTIM1将每50ms溢出一次，并触发 + 中断服务程序。中断服务程序中，PB09输出电平翻转，LED1将10Hz的频率闪烁。 + BTIM2以BTIM1的溢出信号OV进行计数，设置ARR寄存器为9，则BTIM1将每500ms溢出一次，并触发 + 中断服务程序。中断服务程序中，PB08输出电平翻转，LED2将1Hz的频率闪烁。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/EWARM/Project.ewd new file mode 100644 index 0000000..4564814 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/EWARM/Project.ewp new file mode 100644 index 0000000..cc7d14c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/EWARM/Project.ewp @@ -0,0 +1,2154 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/EWARM/Project.eww new file mode 100644 index 0000000..284f58c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/EWARM/Project.eww @@ -0,0 +1,6 @@ + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/MDK/Project.uvoptx new file mode 100644 index 0000000..9704855 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/MDK/Project.uvoptx @@ -0,0 +1,336 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\BTIM1 + 35905 + + + System Viewer\BTIM2 + 35904 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_btim.c + cw32f030_btim.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/MDK/Project.uvprojx new file mode 100644 index 0000000..8d80460 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/MDK/Project.uvprojx @@ -0,0 +1,455 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_btim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_btim.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/USER/inc/main.h new file mode 100644 index 0000000..1c25914 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_btim.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..2e6a3f4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/USER/src/interrupts_cw32f030.c @@ -0,0 +1,411 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ +extern void BTIM1_IRQHandleCallback(void); +extern void BTIM2_IRQHandleCallback(void); +extern void BTIM3_IRQHandleCallback(void); + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + BTIM1_IRQHandleCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + BTIM2_IRQHandleCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + BTIM3_IRQHandleCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/USER/src/main.c new file mode 100644 index 0000000..2e9df0f --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/USER/src/main.c @@ -0,0 +1,189 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-08-24 + * + * @copyright Copyright (c) 2021 + * + * 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +BTIM_TimeBaseInitTypeDef BTIM_TimeBaseInitStruct; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + RCC_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); // 设置PA12作为ETR的输入引脚 + /* 先设置GATE信号的极性，再设置定时器的模式，否则会引起误触发 */ + BTIM_SelectInputTrigger(CW_BTIM1, BTIM_TS_ETR); + BTIM_ETRConfig(CW_BTIM1, BTIM_ETR_Polarity_Positive, BTIM_EXT_FILTER_PCLK_N6); + BTIM_TimeBaseInitStruct.BTIM_Mode = BTIM_Mode_GATE; + BTIM_TimeBaseInitStruct.BTIM_Period = 49999; + BTIM_TimeBaseInitStruct.BTIM_Prescaler = BTIM_PRS_DIV8; + BTIM_TimeBaseInitStruct.BTIM_OPMode = BTIM_OPMode_Repetitive; + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_TimeBaseInitStruct); + BTIM_TimeBaseInitStruct.BTIM_Mode = BTIM_Mode_TIMER; + BTIM_TimeBaseInitStruct.BTIM_Period = 15624; + BTIM_TimeBaseInitStruct.BTIM_Prescaler = BTIM_PRS_DIV512; + BTIM_TimeBaseInitStruct.BTIM_OPMode = BTIM_OPMode_Repetitive; + BTIM_TimeBaseInit(CW_BTIM2, &BTIM_TimeBaseInitStruct); + BTIM_OutputToggleCmd(CW_BTIM2, ENABLE); // BTIM2的toggle输出使能，作为BTIM1的GATE信号 + BTIM_ITConfig(CW_BTIM1, BTIM_IT_OV, ENABLE); + BTIM_ITConfig(CW_BTIM2, BTIM_IT_OV, ENABLE); + BTIM_Cmd(CW_BTIM1, ENABLE); + BTIM_Cmd(CW_BTIM2, ENABLE); + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + // CW_SYSCTRL->APBEN2_f.BTIM = 1U; + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + __RCC_BTIM_CLK_ENABLE(); + __RCC_GPIOA_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + PA12_AFx_BTIMETR(); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT_PULLDOWN; + GPIO_InitStruct.Pins = GPIO_PIN_12; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); // PA12 + PA05_AFx_BTIM2TOGP(); // BTIM2的TOG输出分配到PA5 + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_5; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); // PA5 + PB09_SETLOW(); + PB08_SETHIGH(); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_9 | GPIO_PIN_8; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(BTIM1_IRQn); + NVIC_EnableIRQ(BTIM2_IRQn); + __enable_irq(); +} + +void BTIM1_IRQHandleCallback(void) +{ + if (BTIM_GetITStatus(CW_BTIM1, BTIM_IT_OV)) + { + BTIM_ClearITPendingBit(CW_BTIM1, BTIM_IT_OV); + PB09_TOG(); + } +} + +void BTIM2_IRQHandleCallback(void) +{ + if (BTIM_GetITStatus(CW_BTIM2, BTIM_IT_OV)) + { + BTIM_ClearITPendingBit(CW_BTIM2, BTIM_IT_OV); + PB08_TOG(); + } +} +void BTIM3_IRQHandleCallback(void) +{ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/readme.txt new file mode 100644 index 0000000..e7ceabf --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRGate/readme.txt @@ -0,0 +1,38 @@ +示例目的： + 演示基本定时器BTIM的门控功能。BTIM的使能信号EN设置为有效时，需门控信号有效，定时器方才计数。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. BTIM1的时钟设置为PCLK，8分频，门控模式 + 5. PA12复用功能配置为BTIM_ETR，作为GATE信号的输入端口, PCLK,6点滤波 + 6. PB09设置为PUSH-PULL输出 + 7. PB08设置为PUSH-PULL输出 + 8. BTIM2的时钟设置为PCLK， 512分频 + 9. PA05设置为BTIM2的TOGP输出 + + +演示说明： + BTIM1配置为门控功能，以1MHz时钟进行计数，设置ARR寄存器为49999； + BTIM2配置为定时模式，以15625Hz时钟频率计数，设置ARR寄存器为15624，设置TOGP输出使能， + PA05的电平每1s翻转一次。 + BTIM2每秒钟溢出一次，溢出后，触发中断服务程序。中断服务程序中，PB08输出电平翻转，并 + 保持和PA05相同的极性，LED2将2Hz的频率闪烁。 + 使用杜邦线将PA05脚与PA12脚连接，则当PA05输出高电平时，LED2亮起，BTIM1将每50ms溢出一次， + 并触发中断服务程序。中断服务程序中，PB09输出电平翻转，LED1将10Hz的频率闪烁。 + 当PA05输出低电平时，LED2灭，BTIM1停止计数，LED1不闪烁。 + + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/EWARM/Project.ewd new file mode 100644 index 0000000..4564814 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 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$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/EWARM/Project.ewp new file mode 100644 index 0000000..cc7d14c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/EWARM/Project.ewp @@ -0,0 +1,2154 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_btim.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/EWARM/Project.eww new file mode 100644 index 0000000..284f58c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/EWARM/Project.eww @@ -0,0 +1,6 @@ + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/MDK/Project.uvoptx new file mode 100644 index 0000000..eee65f9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/MDK/Project.uvoptx @@ -0,0 +1,332 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U4294967295 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030 -FS00 -FL012000 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\BTIM1 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_btim.c + cw32f030_btim.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/MDK/Project.uvprojx new file mode 100644 index 0000000..4371130 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/MDK/Project.uvprojx @@ -0,0 +1,455 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_btim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_btim.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..ac198d9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,100 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ +extern void GPIOA_IRQHandleCallback(void); + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/USER/inc/main.h new file mode 100644 index 0000000..1c25914 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_btim.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..4a636f0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/USER/src/interrupts_cw32f030.c @@ -0,0 +1,412 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ +extern void BTIM1_IRQHandleCallback(void); +extern void BTIM2_IRQHandleCallback(void); +extern void BTIM3_IRQHandleCallback(void); + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + GPIOA_IRQHandleCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + BTIM1_IRQHandleCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + BTIM2_IRQHandleCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + BTIM3_IRQHandleCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/USER/src/main.c new file mode 100644 index 0000000..6839c4e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/USER/src/main.c @@ -0,0 +1,182 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-08-24 + * + * @copyright Copyright (c) 2021 + * + * 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +BTIM_TimeBaseInitTypeDef BTIM_TimeBaseInitStruct; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + RCC_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); // 设置PA12作为ETR的输入引脚 + /* 先设置触发信号的极性，再设置定时器的模式，否则会引起误触发 */ + BTIM_SelectInputTrigger(CW_BTIM1, BTIM_TS_ETR); + BTIM_ETRConfig(CW_BTIM1, BTIM_ETR_Polarity_Negative, BTIM_EXT_FILTER_NONE); + BTIM_TimeBaseInitStruct.BTIM_Mode = BTIM_Mode_TRIGGER; + BTIM_TimeBaseInitStruct.BTIM_Period = 15624; + BTIM_TimeBaseInitStruct.BTIM_Prescaler = BTIM_PRS_DIV512; + BTIM_TimeBaseInitStruct.BTIM_OPMode = BTIM_OPMode_Single; + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_TimeBaseInitStruct); + BTIM_ITConfig(CW_BTIM1, BTIM_IT_OV, ENABLE); + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + // CW_SYSCTRL->APBEN2_f.BTIM = 1U; + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + __RCC_BTIM_CLK_ENABLE(); + __RCC_GPIOA_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + PA12_AFx_BTIMETR(); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT_PULLDOWN; + GPIO_InitStruct.Pins = GPIO_PIN_12; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); // PA12 + PB09_SETLOW(); + PB08_SETHIGH(); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_9 | GPIO_PIN_8; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + GPIO_InitStruct.IT = GPIO_IT_FALLING; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_1; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); // PA1 -> KEY1 +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(BTIM1_IRQn); + NVIC_EnableIRQ(GPIOA_IRQn); + __enable_irq(); +} + +void BTIM1_IRQHandleCallback(void) +{ + if (BTIM_GetITStatus(CW_BTIM1, BTIM_IT_OV)) + { + BTIM_ClearITPendingBit(CW_BTIM1, BTIM_IT_OV); + PB09_SETLOW(); + } +} +void BTIM2_IRQHandleCallback(void) +{ +} +void BTIM3_IRQHandleCallback(void) +{ +} + +void GPIOA_IRQHandleCallback(void) +{ + if (CW_GPIOA->ISR_f.PIN1) // 中断中，直接操作寄存器，速度快 + { + CW_GPIOA->ICR_f.PIN1 = 0; // 清标志 + PB09_SETHIGH(); + } +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/readme.txt new file mode 100644 index 0000000..4a3c39b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_ETRTrigger/readme.txt @@ -0,0 +1,36 @@ +示例目的： + 演示基本定时器BTIM的触发启动功能。设置BTIM的EN为0，当触发信号有效时，定时器启动计数。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. BTIM1的时钟设置为PCLK，512分频，触发启动模式，触发类型下降沿 + 5. PA12复用功能配置为BTIM_ETR，作为外部触发信号的输入端口 + 6. PB09设置为PUSH-PULL输出 + 7. PB08设置为PUSH-PULL输出 + 8. PA01设置为中断输入口，中断类型下降沿 + + +演示说明： + BTIM1配置为触发启动模式，单次运行，以15625Hz时钟频率计数，设置ARR寄存器为15624； + BTIM1计时满1s后溢出，溢出后，触发中断服务程序。中断服务程序中，PB09输出低电平， + LED1灭。 + 使用杜邦线将PA01脚与PA12脚连接，当按下KEY1时，将触发BTIM1启动计数，同时GPIOA的 + 中断服务程序中，PB09输出高电平，LED1亮。 + 每按下KEY1一次，LED1亮1s后熄灭。 + LED2常亮作为电压指示等。 + + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/EWARM/project.ewd new file mode 100644 index 0000000..91e99d1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/EWARM/project.ewd @@ -0,0 +1,3088 @@ + + + 3 + + Release + + ARM + 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b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/EWARM/project.ewp new file mode 100644 index 0000000..9ee9a36 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/EWARM/project.ewp @@ -0,0 +1,2197 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 27 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_atim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_btim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Utilities\cw32f030c8t6_startkit.c + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + $PROJ_DIR$\..\USER\src\main.c + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/EWARM/project.eww new file mode 100644 index 0000000..c78ed98 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/MDK/project.uvoptx new file mode 100644 index 0000000..cd18e70 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/MDK/project.uvoptx @@ -0,0 +1,444 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=120,153,364,299,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U4294967295 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030_72K -FS00 -FL012000 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 75 + 1 +
0
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### uVision Project, (C) Keil Software
+ + + + project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\Utilities + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_atim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_atim.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030c8t6_startkit.c + 1 + ..\..\..\..\Utilities\cw32f030c8t6_startkit.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + cw32f030_adc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_adc.c + + + cw32f030_btim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_btim.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/USER/inc/main.h new file mode 100644 index 0000000..16837f3 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_btim.h" +#include "cw32f030_rcc.h" +#include "cw32f030_flash.h" +#include "cw32f030_gpio.h" +#include "cw32f030c8t6_startkit.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..37c3b75 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/USER/src/interrupts_cw32f030.c @@ -0,0 +1,414 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ +extern void BTIM1_IRQHandleCallback(void); +extern void BTIM2_IRQHandleCallback(void); +extern void BTIM3_IRQHandleCallback(void); + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + BTIM1_IRQHandleCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + BTIM2_IRQHandleCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + BTIM3_IRQHandleCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/USER/src/main.c new file mode 100644 index 0000000..2890a02 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/USER/src/main.c @@ -0,0 +1,191 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-08-24 + * + * @copyright Copyright (c) 2021 + * + * 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +static void BTIM_Config(void); +static void LED1_Config(void); +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +BTIM_TimeBaseInitTypeDef BTIM_InitStructure; +LED_InitTypeDef LED1; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + RCC_Configuration(); // + /* GPIO Configuration */ + GPIO_Configuration(); + LED1_Config(); + BTIM_Config(); + /* NVIC Configuration */ + NVIC_Configuration(); + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + /* 0. HSE使能 */ + __RCC_GPIOF_CLK_ENABLE(); + PF00_ANALOG_ENABLE(); + PF01_ANALOG_ENABLE(); + RCC_HSE_Enable(RCC_HSE_MODE_OSC, 16000000, RCC_HSE_DRIVER_NORMAL, RCC_HSE_FLT_CLOSE); + RCC_HSE_OUT(); + /* 1. 设置HCLK和PCLK的分频系数　*/ + RCC_HCLKPRS_Config(RCC_HCLK_DIV1); + RCC_PCLKPRS_Config(RCC_PCLK_DIV1); + /* 2. 使能PLL，通过HSI倍频到64MHz */ + RCC_PLL_Enable(RCC_PLLSOURCE_HSEOSC, 16000000, 4); // + RCC_PLL_OUT(); + ///< 当使用的时钟源HCLK大于48M,小于等于72MHz：设置FLASH 读等待周期为3 cycle + __RCC_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_3); + /* 3. 时钟切换到PLL */ + RCC_SysClk_Switch(RCC_SYSCLKSRC_PLL); + RCC_SystemCoreClockUpdate(64000000); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + __RCC_GPIOA_CLK_ENABLE(); + PA07_AFx_BTIM1TOGP(); + PA09_AFx_BTIM1TOGP(); + PA10_AFx_BTIM1TOGN(); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(BTIM1_IRQn); + __enable_irq(); +} + +static void BTIM_Config(void) +{ + __RCC_BTIM_CLK_ENABLE(); + BTIM_InitStructure.BTIM_Mode = BTIM_Mode_TIMER; + BTIM_InitStructure.BTIM_OPMode = BTIM_OPMode_Repetitive; + BTIM_InitStructure.BTIM_Prescaler = BTIM_PRS_DIV1024; // 64MHz / 1024分频=62500Hz + BTIM_InitStructure.BTIM_Period = 62500 / 20 - 1; // 20Hz溢出一次，触发TOG得到10Hz输出 + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_InitStructure); + BTIM_OutputToggleCmd(CW_BTIM1, ENABLE); + BTIM_ITConfig(CW_BTIM1, BTIM_IT_OV, ENABLE); + BTIM_Cmd(CW_BTIM1, ENABLE); +} + +static void LED1_Config(void) +{ + LED1.LED_Port = CW_GPIOB; + LED1.LED_Pin = GPIO_PIN_9; + LED_Init(&LED1); +} +void BTIM1_IRQHandleCallback(void) +{ + if (BTIM_GetITStatus(CW_BTIM1, BTIM_IT_OV)) + { + BTIM_ClearITPendingBit(CW_BTIM1, BTIM_IT_OV); + LED1.LED_Toggle(&LED1); + } +} +void BTIM2_IRQHandleCallback(void) +{ +} +void BTIM3_IRQHandleCallback(void) +{ +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/readme.txt new file mode 100644 index 0000000..aea8c38 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/BTIM/BaseTimer_Toggle_10Hz/readme.txt @@ -0,0 +1,33 @@ +示例目的： + 演示基本定时器BTIM的TOG输出功能，不需要中断和口线寄存器的操作，完全由硬件实现方波的输出。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSE，16MHz + 3. 系统时钟设置为PLL时钟，为HSE频率的4倍频，64MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=64MHz + 4. BTIM1的时钟设置为PCLK，1024分频， + 5. PA07,PA09,PA10设置为PUSH-PULL输出, 复用为BTIM1的TOG输出 + 6. PB09设置为PUSH-PULL输出 + 7. PB08设置为PUSH-PULL输出 + + + +演示说明： + BTIM1的计数时钟为64MHz/1024=62500Hz，设置ARR寄存器为62500 / 20 - 1，BTIM1每50ms溢出一次； + 溢出后，触发中断服务程序。中断服务程序中，PB09输出翻转，LED1闪烁，用于指示。 + PA07和PA09输出TOGP，PA10输出TOGN，可以示波器观测波形。 + + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + 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b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/EWARM/Project.ewp new file mode 100644 index 0000000..4d9c265 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/EWARM/Project.ewp @@ -0,0 +1,2151 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_digitalsign.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/MDK/DigitalSign.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/MDK/DigitalSign.uvoptx new file mode 100644 index 0000000..fcf8f5e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/MDK/DigitalSign.uvoptx @@ -0,0 +1,344 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + DigitalSign + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + Chip_Type + + + 1 + 1 + Pin_Count + + + 2 + 1 + Chip_Uid + + + 3 + 1 + Chip_Uid + + + + + 1 + 0 + 0x00012626 + 0 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_digitalsign.c + cw32f030_digitalsign.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/MDK/DigitalSign.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/MDK/DigitalSign.uvprojx new file mode 100644 index 0000000..bd87e05 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/MDK/DigitalSign.uvprojx @@ -0,0 +1,449 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + DigitalSign + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + DigitalSign + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 0 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_digitalsign.c + 1 + ..\..\..\..\Libraries\src\cw32f030_digitalsign.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/USER/inc/main.h new file mode 100644 index 0000000..2f6160d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/USER/src/main.c new file mode 100644 index 0000000..212e51f --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/USER/src/main.c @@ -0,0 +1,116 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-25 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_rcc.h" +#include "cw32f030_digitalsign.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +uint8_t Chip_Type[24]; +uint16_t Pin_Count; +uint32_t Flash_Size; +uint32_t Ram_Size; +uint8_t Chip_Uid[10]; + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle GPIOA.00 + ** + ******************************************************************************/ +int32_t main(void) +{ + RCC_AHBPeriphClk_Enable(RCC_AHB_PERIPH_GPIOB, ENABLE); //Open GPIOB Clk + CW_GPIOB->ANALOG_f.PIN6 = 0U; //Digital + CW_GPIOB->BRR_f.BRR6 = 1U; //Reset PB08 + CW_GPIOB->DIR_f.PIN6 = 0U; //Output + DIGITALSIGN_GetChipType(Chip_Type); + Pin_Count = DIGITALSIGN_GetPinCount(); + Flash_Size = DIGITALSIGN_GetFlashSize(); + Ram_Size = DIGITALSIGN_GetRamSize(); + DIGITALSIGN_GetChipUid(Chip_Uid); + while (1) + { + CW_GPIOB->TOG = bv8; + CW_GPIOB->TOG = bv6; + FirmwareDelay(100000); + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/readme.txt new file mode 100644 index 0000000..34feaf6 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DIGITALSIGN/DigitalSign/readme.txt @@ -0,0 +1,24 @@ +示例目的： + 读取数字签名相关内容。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + + +演示说明： + 程序依次读取芯片类型/引脚数/FLASH容量/RAM容量以及芯片UID，然后通过TOG PB08口线来持续闪灯。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + 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b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/EWARM/Project.ewp new file mode 100644 index 0000000..b6ccc04 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/EWARM/Project.ewp @@ -0,0 +1,2157 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/MDK/Project.uvoptx new file mode 100644 index 0000000..13a256c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/MDK/Project.uvoptx @@ -0,0 +1,373 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + ST-LINKIII-KEIL_SWO + -U56FF71065178565626600287 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030_64K -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 193 + 1 +
3784
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\Project\../USER/src/main.c\193 + + + + + 0 + 1 + ADC_Result_Array,0x0A + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\DMA + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_dma.c + cw32f030_dma.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_adc.c + cw32f030_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/MDK/Project.uvprojx new file mode 100644 index 0000000..04a1c01 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/MDK/Project.uvprojx @@ -0,0 +1,460 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060061::V5.06 update 1 (build 61)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.5 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_dma.c + 1 + ..\..\..\..\Libraries\src\cw32f030_dma.c + + + cw32f030_adc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_adc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/USER/inc/main.h new file mode 100644 index 0000000..008b504 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gpio.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +//#define DMA_CYCLE_EN +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..11bcccd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/USER/src/interrupts_cw32f030.c @@ -0,0 +1,416 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_adc.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + +void DMA_CHANNEL1_IRQ_FUNCTION(void); + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + DMA_CHANNEL1_IRQ_FUNCTION(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + if (ADC_GetITStatus(ADC_IT_EOC) != RESET) + { + ADC_ClearITPendingBit(ADC_IT_EOC); + ADC_SoftwareStartConvCmd(ENABLE); //启动下一次ADC转换 + PB09_TOG(); + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/USER/src/main.c new file mode 100644 index 0000000..0672777 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/USER/src/main.c @@ -0,0 +1,211 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-21 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_rcc.h" +#include "cw32f030_dma.h" +#include "cw32f030_adc.h" +#include "cw32f030_gpio.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +#define DMA_CYCLE_EN 1 +uint32_t ADC_Result_Array[16] = {0}; + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +static void ZeroMemory(uint8_t *buf, uint32_t size) +{ + uint32_t i = 0; + for (i = 0; i < size; i ++) + { + *buf = 0x0; + } +} + +static void Error_Handle() +{ + while (1); +} + +void DMA_CHANNEL1_IRQ_FUNCTION(void) +{ + if (DMA_GetITStatus(DMA_IT_TC1)) + { + DMA_ClearITPendingBit(DMA_IT_TC1); + PB08_TOG(); +#ifdef DMA_CYCLE_EN + CW_DMACHANNEL1->CNT = 0x10010; //重置CNT计数 + CW_DMACHANNEL1->DSTADDR = (uint32_t)(&ADC_Result_Array[0]); //重置目的地址 + DMA_Cmd(CW_DMACHANNEL1, ENABLE); //使能DMA +#else + ADC_Disable(); //传输完成，停止ADC +#endif + } + if (DMA_GetITStatus(DMA_IT_TE1)) + { + DMA_ClearITPendingBit(DMA_IT_TE1); + Error_Handle(); + } +} +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_ClearPendingIRQ(DMACH1_IRQn); + NVIC_EnableIRQ(DMACH1_IRQn); + __enable_irq(); +} + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ** + ******************************************************************************/ + +int32_t main(void) +{ + ADC_InitTypeDef ADC_InitStruct; + DMA_InitTypeDef DMA_InitStruct; + RCC_AHBPeriphClk_Enable(RCC_AHB_PERIPH_DMA | RCC_AHB_PERIPH_GPIOA | RCC_AHB_PERIPH_GPIOB, ENABLE); //Open DMA and GPIOA/B Clk + RCC_APBPeriphClk_Enable2(RCC_APB2_PERIPH_ADC, ENABLE); //Open ADC Clk + //PB8/PB9 推挽输出 + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + PB08_SETLOW(); + PB09_SETLOW(); + //配置ADC测试IO口 + PA00_ANALOG_ENABLE() ; //PA00 (AIN0) + //ADC初始化 + ADC_InitStruct.ADC_OpMode = ADC_SingleChOneMode; //单通道单次转换模式 + ADC_InitStruct.ADC_ClkDiv = ADC_Clk_Div128; //PCLK + ADC_InitStruct.ADC_SampleTime = ADC_SampTime5Clk; //5个ADC时钟周期 + ADC_InitStruct.ADC_VrefSel = ADC_Vref_VDDA; //VDDA参考电压 + ADC_InitStruct.ADC_InBufEn = ADC_BufEnable; //开启跟随器 + ADC_InitStruct.ADC_TsEn = ADC_TsDisable; //内置温度传感器禁用 + ADC_InitStruct.ADC_DMAEn = ADC_DmaEnable; //ADC转换完成触发DMA传输 + ADC_InitStruct.ADC_Align = ADC_AlignRight; //ADC转换结果右对齐 + ADC_InitStruct.ADC_AccEn = ADC_AccDisable; //转换结果累加不使能 + ADC_Init(&ADC_InitStruct); //初始化ADC配置 + CW_ADC->CR1_f.DISCARD = FALSE; //配置数据更新策略，不包含在ADC结构体中 + CW_ADC->CR1_f.CHMUX = ADC_Vref1P2Input; //ADC_ExInputCH0; //配置ADC输入通道，不包含在ADC结构体中 + ADC_ClearITPendingBit(ADC_IT_EOC); + ADC_ITConfig(ADC_IT_EOC, ENABLE); + ADC_EnableNvic(ADC_INT_PRIORITY); + DMA_StructInit(&DMA_InitStruct); + ZeroMemory((uint8_t *)&ADC_Result_Array[0], sizeof(ADC_Result_Array)); + DMA_InitStruct.DMA_Mode = DMA_MODE_BLOCK; + DMA_InitStruct.DMA_TransferWidth = DMA_TRANSFER_WIDTH_32BIT; + DMA_InitStruct.DMA_SrcInc = DMA_SrcAddress_Fix; +#ifdef DMA_CYCLE_EN + DMA_InitStruct.DMA_DstInc = DMA_DstAddress_Increase; +#else + DMA_InitStruct.DMA_DstInc = DMA_DstAddress_Fix; +#endif + DMA_InitStruct.DMA_TransferCnt = 16; + DMA_InitStruct.DMA_SrcAddress = (uint32_t) &(CW_ADC->RESULT0); + DMA_InitStruct.DMA_DstAddress = (uint32_t)&ADC_Result_Array[0]; + DMA_InitStruct.TrigMode = DMA_HardTrig; + DMA_InitStruct.HardTrigSource = DMA_HardTrig_ADC_TRANSCOMPLETE; + DMA_Init(CW_DMACHANNEL1, &DMA_InitStruct); + DMA_ClearITPendingBit(DMA_IT_ALL); + DMA_ITConfig(CW_DMACHANNEL1, DMA_IT_TC | DMA_IT_TE, ENABLE); //使能DMA_CHANNEL1中断 + NVIC_Configuration(); //使能DMA_CHANNEL1中断 + DMA_Cmd(CW_DMACHANNEL1, ENABLE); //使能DMA + //ADC使能 + ADC_Enable(); + ADC_SoftwareStartConvCmd(ENABLE); + while (1) + { + // PB08_TOG(); + // PB09_TOG(); + FirmwareDelay(1000000); + } +} + + + + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/readme.txt new file mode 100644 index 0000000..380f1b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_hw_trigger_block/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 通过ADC转换完成标志触发DMA方式实现外设到内存的DMA传输：无CPU干涉情况下将ADC转换数据传输到目的地址BUFFER的DMA传输。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + +演示说明： + 配置DMA的传输方式为硬件触发，DMA硬件触发源为ADC转换完成标志，DMA传输完成中断并使能。配置ADC为单次单通道转换模式，ADC转换完成中断并使能。ADC转换完成后，产生ADC转换完成标志，触发DMA将数据传到到目标BUFFER，同时产生ADC完成中断，在ADC转换完成中断服务程序中重新启动下一次ADC转换。16次ADC转换完成（程序设置，用户可自行配置）并触发DMA传输后，产生DMA传输完成中断标志，在DMA传输完成中断中重新配置DMA的计数寄存器并重新使能DMA，开启新一轮的数据传输。在DMA循环传输过程中，LED灯持续闪烁，如发生传输错误则MCU被挂起，LED不再闪烁。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null 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+ + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/MDK/Dma_sw_trigger_interrupt.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/MDK/Dma_sw_trigger_interrupt.uvoptx new file mode 100644 index 0000000..03465ca --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/MDK/Dma_sw_trigger_interrupt.uvoptx @@ -0,0 +1,331 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Dma_sw_trigger_interrupt + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + aDST_Buffer + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_dma.c + cw32f030_dma.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/MDK/Dma_sw_trigger_interrupt.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/MDK/Dma_sw_trigger_interrupt.uvprojx new file mode 100644 index 0000000..919f219 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/MDK/Dma_sw_trigger_interrupt.uvprojx @@ -0,0 +1,453 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Dma_sw_trigger_interrupt + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Dma_sw_trigger_interrupt + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4098 + + 0 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_dma.c + 1 + ..\..\..\..\Libraries\src\cw32f030_dma.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/USER/inc/main.h new file mode 100644 index 0000000..2f6160d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..4b19007 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/USER/src/interrupts_cw32f030.c @@ -0,0 +1,409 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + +void DMA_CHANNEL1_IRQ_FUNCTION(void); + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + DMA_CHANNEL1_IRQ_FUNCTION(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/USER/src/main.c new file mode 100644 index 0000000..2d313f7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/USER/src/main.c @@ -0,0 +1,230 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-25 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_rcc.h" +#include "cw32f030_dma.h" +#include "cw32f030_gpio.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +#define BUFFER_SIZE 32U +uint32_t aSRC_Const_Buffer[BUFFER_SIZE] = +{ + 0x01020304, 0x05060708, 0x090A0B0C, 0x0D0E0F10, + 0x11121314, 0x15161718, 0x191A1B1C, 0x1D1E1F20, + 0x21222324, 0x25262728, 0x292A2B2C, 0x2D2E2F30, + 0x31323334, 0x35363738, 0x393A3B3C, 0x3D3E3F40, + 0x41424344, 0x45464748, 0x494A4B4C, 0x4D4E4F50, + 0x51525354, 0x55565758, 0x595A5B5C, 0x5D5E5F60, + 0x61626364, 0x65666768, 0x696A6B6C, 0x6D6E6F70, + 0x71727374, 0x75767778, 0x797A7B7C, 0x7D7E7F80 +}; + +uint32_t aDST_Buffer[BUFFER_SIZE]; + +uint8_t TransOverFlag; + +int32_t myMemcmp(uint8_t *mem1, uint8_t *mem2, uint32_t bytesize) +{ + int i = 0; + uint8_t *p = mem1; + uint8_t *q = mem2; + if (p == NULL || q == NULL) + { + return -1; + } + for (i = 0; i < bytesize; i++, p++, q++) + { + if (*p != *q) + { + return -1; + } + } + return 0; +} + +void ZeroMemory(uint8_t *buf, uint32_t size) +{ + uint32_t i = 0; + for (i = 0; i < size; i ++) + { + *buf = 0x0; + } +} + +void Error_Handle() +{ + while (1); +} + +void DMA_CHANNEL1_IRQ_FUNCTION(void) +{ + if (DMA_GetITStatus(DMA_IT_TC1)) + { + DMA_ClearITPendingBit(DMA_IT_TC1); + TransOverFlag = 1; + } + if (DMA_GetITStatus(DMA_IT_TE1)) + { + DMA_ClearITPendingBit(DMA_IT_TE1); + Error_Handle(); + } +} +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_ClearPendingIRQ(DMACH1_IRQn); + NVIC_EnableIRQ(DMACH1_IRQn); + __enable_irq(); +} + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle GPIOA.00 + ** + ******************************************************************************/ +int32_t main(void) +{ + DMA_InitTypeDef DMA_InitStruct; + RCC_AHBPeriphClk_Enable(RCC_AHB_PERIPH_DMA | RCC_AHB_PERIPH_GPIOB, ENABLE); //Open DMA and GPIOA Clk + //PB8/PB9 推挽输出 + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + PB08_SETLOW(); + PB09_SETLOW(); + TransOverFlag = 0; + DMA_StructInit(&DMA_InitStruct); + ZeroMemory((uint8_t *)&aDST_Buffer[0], sizeof(aDST_Buffer)); + DMA_InitStruct.DMA_Mode = DMA_MODE_BLOCK; + DMA_InitStruct.DMA_TransferWidth = DMA_TRANSFER_WIDTH_32BIT; + DMA_InitStruct.DMA_SrcInc = DMA_SrcAddress_Increase; + DMA_InitStruct.DMA_DstInc = DMA_DstAddress_Increase; + DMA_InitStruct.DMA_TransferCnt = BUFFER_SIZE; + DMA_InitStruct.DMA_SrcAddress = (uint32_t)&aSRC_Const_Buffer[0]; + DMA_InitStruct.DMA_DstAddress = (uint32_t)&aDST_Buffer[0]; + DMA_InitStruct.TrigMode = DMA_SWTrig; + DMA_Init(CW_DMACHANNEL1, &DMA_InitStruct); + DMA_ClearITPendingBit(DMA_IT_ALL); + DMA_ITConfig(CW_DMACHANNEL1, DMA_IT_TC | DMA_IT_TE, ENABLE); //使能DMA_CHANNEL1中断 + NVIC_Configuration(); //使能DMA_CHANNEL1中断 + DMA_Cmd(CW_DMACHANNEL1, ENABLE); //使能DMA + DMA_SWTrigCmd(CW_DMACHANNEL1); //软件触发DMA传输 + while (1) + { + if (TransOverFlag == 1) + { + TransOverFlag = 0; + if (myMemcmp((uint8_t *)&aDST_Buffer[0], (uint8_t *)&aSRC_Const_Buffer[0], BUFFER_SIZE) == -1) + { + Error_Handle(); + } + else + { + while (1) + { + PB08_TOG(); + PB09_TOG(); + FirmwareDelay(1000000); + } + } + } + else + { + PB08_TOG(); + PB09_TOG(); + FirmwareDelay(100000); + } + } +} + + + + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/readme.txt new file mode 100644 index 0000000..a1f5c84 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_interrupt/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 通过软件触发DMA方式实现内存到内存的DMA传输：无CPU干涉情况下的源地址BUFFER到目的地址BUFFER的DMA传输。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + +演示说明： + 正确配置DMA的传输方式，配置DMA传输完成中断并使能，通过软件设置启动DMA传输。DMA传输完成中断服务程序中置传输完成标志TransOverFlag为1。主循环中进行传输完成标志TransOverFlag判断：未完成传输时LED灯快闪，已完成传输则比较目的地址BUFFER和源地址BUFFER的内容是否相同，相同则LED灯慢闪，否则不闪灯。注意：由于DMA传输过程非常快，LED灯快闪过程基本看不见，属于正常现象。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 5 + 1 + 0 + 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a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/EWARM/Project.ewp new file mode 100644 index 0000000..a7c3580 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/EWARM/Project.ewp @@ -0,0 +1,2154 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + 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Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/MDK/Dma_sw_trigger_poll.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/MDK/Dma_sw_trigger_poll.uvoptx new file mode 100644 index 0000000..7330fa3 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/MDK/Dma_sw_trigger_poll.uvoptx @@ -0,0 +1,331 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Dma_sw_trigger_poll + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + aDST_Buffer + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_dma.c + cw32f030_dma.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/MDK/Dma_sw_trigger_poll.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/MDK/Dma_sw_trigger_poll.uvprojx new file mode 100644 index 0000000..5d079fb --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/MDK/Dma_sw_trigger_poll.uvprojx @@ -0,0 +1,453 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Dma_sw_trigger_poll + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Dma_sw_trigger_poll + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4098 + + 0 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_dma.c + 1 + ..\..\..\..\Libraries\src\cw32f030_dma.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/USER/inc/main.h new file mode 100644 index 0000000..2f6160d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..4b19007 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/USER/src/interrupts_cw32f030.c @@ -0,0 +1,409 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + +void DMA_CHANNEL1_IRQ_FUNCTION(void); + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + DMA_CHANNEL1_IRQ_FUNCTION(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/USER/src/main.c new file mode 100644 index 0000000..c0709d5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/USER/src/main.c @@ -0,0 +1,203 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-25 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_rcc.h" +#include "cw32f030_dma.h" +#include "cw32f030_gpio.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +#define BUFFER_SIZE 32U +uint32_t aSRC_Const_Buffer[BUFFER_SIZE] = +{ + 0x01020304, 0x05060708, 0x090A0B0C, 0x0D0E0F10, + 0x11121314, 0x15161718, 0x191A1B1C, 0x1D1E1F20, + 0x21222324, 0x25262728, 0x292A2B2C, 0x2D2E2F30, + 0x31323334, 0x35363738, 0x393A3B3C, 0x3D3E3F40, + 0x41424344, 0x45464748, 0x494A4B4C, 0x4D4E4F50, + 0x51525354, 0x55565758, 0x595A5B5C, 0x5D5E5F60, + 0x61626364, 0x65666768, 0x696A6B6C, 0x6D6E6F70, + 0x71727374, 0x75767778, 0x797A7B7C, 0x7D7E7F80 +}; + +uint32_t aDST_Buffer[BUFFER_SIZE]; + +int32_t myMemcmp(uint8_t *mem1, uint8_t *mem2, uint32_t bytesize) +{ + int i = 0; + uint8_t *p = mem1; + uint8_t *q = mem2; + if (p == NULL || q == NULL) + { + return -1; + } + for (i = 0; i < bytesize; i++, p++, q++) + { + if (*p != *q) + { + return -1; + } + } + return 0; +} + +void ZeroMemory(uint8_t *buf, uint32_t size) +{ + uint32_t i = 0; + for (i = 0; i < size; i ++) + { + *buf = 0x0; + } +} + +void Error_Handle() +{ + while (1); +} + +void DMA_CHANNEL1_IRQ_FUNCTION(void) +{ +} +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + // NVIC_ClearPendingIRQ(DMACH1_IRQn); + // NVIC_EnableIRQ(DMACH1_IRQn); + __enable_irq(); +} + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle GPIOA.00 + ** + ******************************************************************************/ +int32_t main(void) +{ + DMA_InitTypeDef DMA_InitStruct; + RCC_AHBPeriphClk_Enable(RCC_AHB_PERIPH_DMA | RCC_AHB_PERIPH_GPIOB, ENABLE); //Open DMA and GPIOB Clk + //PB8/PB9 推挽输出 + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + PB08_SETLOW(); + PB09_SETLOW(); + DMA_StructInit(&DMA_InitStruct); + ZeroMemory((uint8_t *)&aDST_Buffer[0], sizeof(aDST_Buffer)); + DMA_InitStruct.DMA_Mode = DMA_MODE_BLOCK; + DMA_InitStruct.DMA_TransferWidth = DMA_TRANSFER_WIDTH_32BIT; + DMA_InitStruct.DMA_SrcInc = DMA_SrcAddress_Increase; + DMA_InitStruct.DMA_DstInc = DMA_DstAddress_Increase; + DMA_InitStruct.DMA_TransferCnt = BUFFER_SIZE; + DMA_InitStruct.DMA_SrcAddress = (uint32_t)&aSRC_Const_Buffer[0]; + DMA_InitStruct.DMA_DstAddress = (uint32_t)&aDST_Buffer[0]; + DMA_InitStruct.TrigMode = DMA_SWTrig; + DMA_Init(CW_DMACHANNEL1, &DMA_InitStruct); + DMA_Cmd(CW_DMACHANNEL1, ENABLE); //使能DMA + DMA_SWTrigCmd(CW_DMACHANNEL1); //软件触发DMA传输 + //等待传输完成 + while (DMA_GetFlagStatus(CW_DMACHANNEL1) != DMA_CHANNEL_STATUS_TRANSCOMPLETE); + if (myMemcmp((uint8_t *)&aDST_Buffer[0], (uint8_t *)&aSRC_Const_Buffer[0], BUFFER_SIZE) == -1) + { + Error_Handle(); + } + else + { + while (1) + { + PB08_TOG(); + PB09_TOG(); + FirmwareDelay(1000000); + } + } +} + + + + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/readme.txt new file mode 100644 index 0000000..84cd894 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/DMA/Dma_sw_trigger_poll/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 通过软件触发DMA方式实现内存到内存的DMA传输：无CPU干涉情况下的源地址BUFFER到目的地址BUFFER的DMA传输。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + +演示说明： + 正确配置DMA的传输方式，不配置中断，通过软件设置启动DMA传输。主循环中进行传输完成标志判断，获取到传输完成标志后，比较目的地址BUFFER和源地址BUFFER的内容是否相同，相同则闪灯，否则不闪灯。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/EWARM/project.ewd new file mode 100644 index 0000000..916b5e7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/EWARM/project.ewd @@ -0,0 +1,1484 @@ + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/EWARM/project.ewp new file mode 100644 index 0000000..ee89cd1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/EWARM/project.ewp @@ -0,0 +1,2157 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/EWARM/project.eww new file mode 100644 index 0000000..bc949a7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/EWARM/project.eww @@ -0,0 +1,6 @@ + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/MDK/project.uvoptx new file mode 100644 index 0000000..be6e660 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/MDK/project.uvoptx @@ -0,0 +1,343 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + GTIM_PWM_output + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + ST-LINKIII-KEIL_SWO + -U56FF71065178565626600287 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030_64K -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + cw32f030_gtim.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/MDK/project.uvprojx new file mode 100644 index 0000000..4516613 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/MDK/project.uvprojx @@ -0,0 +1,460 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + GTIM_PWM_output + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + GTIM_PWM_output + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/USER/inc/main.h new file mode 100644 index 0000000..816f3ce --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/USER/inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gtim.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030_flash.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..e0adfc4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/USER/src/interrupts_cw32f030.c @@ -0,0 +1,405 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +__weak void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/USER/src/main.c new file mode 100644 index 0000000..97d311b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/USER/src/main.c @@ -0,0 +1,192 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint32_t Period = 500; // 周期，单位us +uint32_t PosWidth = 0; // 正脉宽，单位us +uint8_t Dir = 1; // 计数方向 1增加，0 减少 +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void PWM_OutputConfig(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief GTIM1计数，CH3通道比较，PB08做PWM输出 + * 中断服务程序中，每4000个周期，增加1/4 + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + PWM_OutputConfig(); + /* NVIC Configuration */ + NVIC_Configuration(); + while (1) + { + /* 中断服务程序见GTIM1_IRQHandler() */ + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + /* 0. HSI使能并校准 */ + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + /* 1. 设置HCLK和PCLK的分频系数　*/ + RCC_HCLKPRS_Config(RCC_HCLK_DIV1); + RCC_PCLKPRS_Config(RCC_PCLK_DIV1); + /* 2. 使能PLL，通过HSI倍频到48MHz */ + RCC_PLL_Enable(RCC_PLLSOURCE_HSI, 8000000, 6); // HSI 默认输出频率8MHz + RCC_PLL_OUT(); + ///< 当使用的时钟源HCLK大于24M,小于等于48MHz：设置FLASH 读等待周期为2 cycle + __RCC_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_2); + /* 3. 时钟切换到PLL */ + RCC_SysClk_Switch(RCC_SYSCLKSRC_PLL); + RCC_SystemCoreClockUpdate(48000000); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + /* PB8(LED2) 作为GTIM1的CH3 PWM 输出 */ + __RCC_GPIOB_CLK_ENABLE(); + PB08_AFx_GTIM1CH3(); + PB08_DIGTAL_ENABLE(); + PB08_DIR_OUTPUT(); + PB08_PUSHPULL_ENABLE(); + PB08_SPEED_HIGH(); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(GTIM1_IRQn); + __enable_irq(); +} + +void PWM_OutputConfig(void) +{ + GTIM_InitTypeDef GTIM_InitStruct; + __RCC_GTIM1_CLK_ENABLE(); + GTIM_InitStruct.Mode = GTIM_MODE_TIME; + GTIM_InitStruct.OneShotMode = GTIM_COUNT_CONTINUE; + GTIM_InitStruct.Prescaler = GTIM_PRESCALER_DIV16; // DCLK = PCLK / 16 = 48MHz/16 = 3MHz + GTIM_InitStruct.ReloadValue = Period * 3 - 1; + GTIM_InitStruct.ToggleOutState = DISABLE; + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + GTIM_OCInit(CW_GTIM1, GTIM_CHANNEL3, GTIM_OC_OUTPUT_PWM_HIGH); + GTIM_SetCompare3(CW_GTIM1, PosWidth); + GTIM_ITConfig(CW_GTIM1, GTIM_IT_OV, ENABLE); + GTIM_Cmd(CW_GTIM1, ENABLE); +} + +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + // 中断每500us进入一次，每50ms改变一次PosWidth + static uint16_t TimeCnt = 0; + GTIM_ClearITPendingBit(CW_GTIM1, GTIM_IT_OV); + if (TimeCnt++ >= 100) // 50ms + { + TimeCnt = 0; + if (Dir) + { + PosWidth += 15; // 5us + } + else + { + PosWidth -= 15; + } + if (PosWidth >= Period * 3) + { + Dir = 0; + } + if (0 == PosWidth) + { + Dir = 1; + } + GTIM_SetCompare3(CW_GTIM1, PosWidth); + } + /* USER CODE END */ +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/readme.txt new file mode 100644 index 0000000..543a0d8 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_PWM_output/readme.txt @@ -0,0 +1,30 @@ +示例目的： + 模拟软件发生故障时，窗口看门狗WWDT复位系统的功能。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为PLL，由HSI提供的8MHz时钟6倍频到48MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=48MHz + 4. GTIM1的分频系数设置为16，ARR设置为1499，则溢出时长为500us + 5. PB08设置为GTIM1的CH3 + + +演示说明： + 系统时钟由HSI提供，通过PLL倍频到48MHz。GTIM1经16分频后，以3MHz的频率计数， + ARR设置为1499，GTIM1的溢出周期为500us。GTIM1每500us进入一次中断，每50ms改变 + 一次CH3的CCR寄存器的值，即改变PWM的正脉宽，步长为5us，先递增到ARR，然后递减 + 到0，如此反复，LED2初始为亮，先逐步变暗，然后逐步变亮，如此反复。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/EWARM/project.ewd new file mode 100644 index 0000000..916b5e7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/EWARM/project.ewd @@ -0,0 +1,1484 @@ + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/EWARM/project.ewp new file mode 100644 index 0000000..ecbc80e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/EWARM/project.ewp @@ -0,0 +1,2160 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/EWARM/project.eww new file mode 100644 index 0000000..bc949a7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/EWARM/project.eww @@ -0,0 +1,6 @@ + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/MDK/project.uvoptx new file mode 100644 index 0000000..cd24a14 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/MDK/project.uvoptx @@ -0,0 +1,357 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + GTIM_SPWM_output + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + SPWM_Table + + + 1 + 1 + SPWM_Table200 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\USER\src\PWM_sine.c + PWM_sine.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + cw32f030_gtim.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/MDK/project.uvprojx new file mode 100644 index 0000000..4f406e5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/MDK/project.uvprojx @@ -0,0 +1,465 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + GTIM_SPWM_output + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + GTIM_timer_toggle_out + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + PWM_sine.c + 1 + ..\USER\src\PWM_sine.c + + + + + Driver + + + cw32f030_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/inc/PWM_sine.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/inc/PWM_sine.h new file mode 100644 index 0000000..1bb53d2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/inc/PWM_sine.h @@ -0,0 +1,60 @@ + + +#ifndef __PWM_SINE_H +#define __PWM_SINE_H + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include +#include "base_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ +extern const uint16_t SPWM_Table[1000]; + +//extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable + +/** + ******************************************************************************* + ** This hook is part of wait loops. + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __PWM_SINE_H__ */ + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/inc/main.h new file mode 100644 index 0000000..6a2b5cc --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/inc/main.h @@ -0,0 +1,67 @@ +/** + * @file main.h + * @author WHXY + * @brief Header for main.c file. + * This file contains the common defines of the application. + * @version 0.1 + * @date 2021-04-22 + * + * @copyright Copyright (c) 2021 + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030_flash.h" +#include "cw32f030_gtim.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/src/PWM_sine.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/src/PWM_sine.c new file mode 100644 index 0000000..8a6e0e1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/src/PWM_sine.c @@ -0,0 +1,142 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file PWM_sine.c + * @brief + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ + +#include "PWM_sine.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +const uint16_t SPWM_Table[1000] = +{ + 30376, 30565, 30753, 30942, 31130, 31319, 31507, 31695, 31883, 32071, 32259, 32447, 32635, 32823, 33010, 33198, 33385, 33572, 33759, 33946, + 34133, 34320, 34506, 34693, 34879, 35065, 35250, 35436, 35621, 35806, 35991, 36175, 36360, 36544, 36728, 36911, 37094, 37277, 37460, 37643, + 37825, 38007, 38188, 38369, 38550, 38731, 38911, 39091, 39270, 39449, 39628, 39806, 39984, 40162, 40339, 40516, 40692, 40868, 41043, 41218, + 41393, 41567, 41741, 41914, 42087, 42259, 42431, 42602, 42773, 42943, 43113, 43282, 43451, 43619, 43787, 43954, 44121, 44287, 44452, 44617, + 44781, 44945, 45108, 45271, 45433, 45594, 45755, 45915, 46074, 46233, 46391, 46549, 46706, 46862, 47018, 47172, 47327, 47480, 47633, 47785, + 47937, 48087, 48237, 48387, 48535, 48683, 48830, 48977, 49122, 49267, 49411, 49555, 49697, 49839, 49980, 50120, 50259, 50398, 50536, 50673, + 50809, 50944, 51079, 51213, 51346, 51478, 51609, 51739, 51869, 51997, 52125, 52252, 52378, 52503, 52627, 52750, 52873, 52994, 53115, 53235, + 53353, 53471, 53588, 53704, 53819, 53933, 54047, 54159, 54270, 54380, 54490, 54598, 54705, 54812, 54917, 55022, 55125, 55228, 55329, 55430, + 55529, 55628, 55725, 55822, 55917, 56012, 56105, 56197, 56289, 56379, 56468, 56556, 56644, 56730, 56815, 56899, 56982, 57064, 57144, 57224, + 57303, 57380, 57457, 57532, 57606, 57680, 57752, 57823, 57893, 57962, 58029, 58096, 58162, 58226, 58289, 58351, 58412, 58472, 58531, 58589, + 58645, 58701, 58755, 58808, 58860, 58911, 58961, 59010, 59057, 59103, 59148, 59192, 59235, 59277, 59318, 59357, 59395, 59432, 59468, 59503, + 59536, 59569, 59600, 59630, 59659, 59687, 59713, 59739, 59763, 59786, 59808, 59829, 59848, 59866, 59884, 59899, 59914, 59928, 59940, 59952, + 59962, 59970, 59978, 59985, 59990, 59994, 59997, 59999, 60000, 59999, 59997, 59994, 59990, 59985, 59978, 59970, 59962, 59952, 59940, 59928, + 59914, 59899, 59884, 59866, 59848, 59829, 59808, 59786, 59763, 59739, 59713, 59687, 59659, 59630, 59600, 59569, 59536, 59503, 59468, 59432, + 59395, 59357, 59318, 59277, 59235, 59192, 59148, 59103, 59057, 59010, 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16548, 16380, 16212, 16045, 15878, 15712, 15547, 15382, + 15218, 15054, 14891, 14728, 14566, 14405, 14244, 14084, 13925, 13766, 13608, 13450, 13293, 13137, 12981, 12827, 12672, 12519, 12366, 12214, + 12062, 11912, 11762, 11612, 11464, 11316, 11169, 11022, 10877, 10732, 10588, 10444, 10302, 10160, 10019, 9879, 9740, 9601, 9463, 9326, + 9190, 9055, 8920, 8786, 8653, 8521, 8390, 8260, 8130, 8002, 7874, 7747, 7621, 7496, 7372, 7249, 7126, 7005, 6884, 6764, + 6646, 6528, 6411, 6295, 6180, 6066, 5952, 5840, 5729, 5619, 5509, 5401, 5294, 5187, 5082, 4977, 4874, 4771, 4670, 4569, + 4470, 4371, 4274, 4177, 4082, 3987, 3894, 3802, 3710, 3620, 3531, 3443, 3355, 3269, 3184, 3100, 3017, 2935, 2855, 2775, + 2696, 2619, 2542, 2467, 2393, 2319, 2247, 2176, 2106, 2037, 1970, 1903, 1837, 1773, 1710, 1648, 1587, 1527, 1468, 1410, + 1354, 1298, 1244, 1191, 1139, 1088, 1038, 989, 942, 896, 851, 807, 764, 722, 681, 642, 604, 567, 531, 496, + 463, 430, 399, 369, 340, 312, 286, 260, 236, 213, 191, 170, 151, 133, 115, 100, 85, 71, 59, 47, + 37, 29, 21, 14, 9, 5, 2, 0, 0, 0, 2, 5, 9, 14, 21, 29, 37, 47, 59, 71, + 85, 100, 115, 133, 151, 170, 191, 213, 236, 260, 286, 312, 340, 369, 399, 430, 463, 496, 531, 567, + 604, 642, 681, 722, 764, 807, 851, 896, 942, 989, 1038, 1088, 1139, 1191, 1244, 1298, 1354, 1410, 1468, 1527, + 1587, 1648, 1710, 1773, 1837, 1903, 1970, 2037, 2106, 2176, 2247, 2319, 2393, 2467, 2542, 2619, 2696, 2775, 2855, 2935, + 3017, 3100, 3184, 3269, 3355, 3443, 3531, 3620, 3710, 3802, 3894, 3987, 4082, 4177, 4274, 4371, 4470, 4569, 4670, 4771, + 4874, 4977, 5082, 5187, 5294, 5401, 5509, 5619, 5729, 5840, 5952, 6066, 6180, 6295, 6411, 6528, 6646, 6764, 6884, 7005, + 7126, 7249, 7372, 7496, 7621, 7747, 7874, 8002, 8130, 8260, 8390, 8521, 8653, 8786, 8920, 9055, 9190, 9326, 9463, 9601, + 9740, 9879, 10019, 10160, 10302, 10444, 10588, 10732, 10877, 11022, 11169, 11316, 11464, 11612, 11762, 11912, 12062, 12214, 12366, 12519, + 12672, 12827, 12981, 13137, 13293, 13450, 13608, 13766, 13925, 14084, 14244, 14405, 14566, 14728, 14891, 15054, 15218, 15382, 15547, 15712, + 15878, 16045, 16212, 16380, 16548, 16717, 16886, 17056, 17226, 17397, 17568, 17740, 17912, 18085, 18258, 18432, 18606, 18781, 18956, 19131, + 19307, 19483, 19660, 19837, 20015, 20193, 20371, 20550, 20729, 20908, 21088, 21268, 21449, 21630, 21811, 21992, 22174, 22356, 22539, 22722, + 22905, 23088, 23271, 23455, 23639, 23824, 24008, 24193, 24378, 24563, 24749, 24934, 25120, 25306, 25493, 25679, 25866, 26053, 26240, 26427, + 26614, 26801, 26989, 27176, 27364, 27552, 27740, 27928, 28116, 28304, 28492, 28680, 28869, 29057, 29246, 29434, 29623, 29811, 29999, 30188 +}; + +static const uint16_t SPWM_Table200[200] = +{ + 31883, 32823, 33759, 34693, 35621, 36544, 37460, 38369, 39270, 40162, 41043, 41914, 42773, 43619, 44452, 45271, 46074, 46862, 47633, 48387, + 49122, 49839, 50536, 51213, 51869, 52503, 53115, 53704, 54270, 54812, 55329, 55822, 56289, 56730, 57144, 57532, 57893, 58226, 58531, 58808, + 59057, 59277, 59468, 59630, 59763, 59866, 59940, 59985, 60000, 59985, 59940, 59866, 59763, 59630, 59468, 59277, 59057, 58808, 58531, 58226, + 57893, 57532, 57144, 56730, 56289, 55822, 55329, 54812, 54270, 53704, 53115, 52503, 51869, 51213, 50536, 49839, 49122, 48387, 47633, 46862, + 46074, 45271, 44452, 43619, 42773, 41914, 41043, 40162, 39270, 38369, 37460, 36544, 35621, 34693, 33759, 32823, 31883, 30942, 30000, 29057, + 28116, 27176, 26240, 25306, 24378, 23455, 22539, 21630, 20729, 19837, 18956, 18085, 17226, 16380, 15547, 14728, 13925, 13137, 12366, 11612, + 10877, 10160, 9463, 8786, 8130, 7496, 6884, 6295, 5729, 5187, 4670, 4177, 3710, 3269, 2855, 2467, 2106, 1773, 1468, 1191, + 942, 722, 531, 369, 236, 133, 59, 14, 0, 14, 59, 133, 236, 369, 531, 722, 942, 1191, 1468, 1773, + 2106, 2467, 2855, 3269, 3710, 4177, 4670, 5187, 5729, 6295, 6884, 7496, 8130, 8786, 9463, 10160, 10877, 11612, 12366, 13137, + 13925, 14728, 15547, 16380, 17226, 18085, 18956, 19837, 20729, 21630, 22539, 23455, 24378, 25306, 26240, 27176, 28116, 29057, 29999, 30942 +}; + +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ + +/** + * @brief This get value from SPWM_Table(i) + */ + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..458c7a4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/src/interrupts_cw32f030.c @@ -0,0 +1,435 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ + +#include "../inc/main.h" +#include "../inc/interrupts_cw32f030.h" +#include "../inc/PWM_sine.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ +extern uint32_t Period; +extern uint32_t PosWidth; + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + static uint16_t i = 0; + static uint16_t j = 0; + /* USER CODE BEGIN */ + if (GTIM_GetITStatus(CW_GTIM1, GTIM_IT_OV)) + { + GTIM_ClearITPendingBit(CW_GTIM1, GTIM_IT_OV); + if (j < 2) //每个SPWM值输出2次 + { + j++; + } + else + { + if (i < 1000) + // GTIM_SetCompare1(CW_GTIM1, (SPWM_Table[i++] >> 4)); //减少 CC1 会降低 SPWM周期 + { + GTIM_SetCompare1(CW_GTIM1, (SPWM_Table[i++])); + } + else + { + i = 0; + } + j = 0; + } + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/src/main.c new file mode 100644 index 0000000..ccfa673 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/USER/src/main.c @@ -0,0 +1,139 @@ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle GPIOA.00 + ** + ******************************************************************************/ + +/** + * @brief 使用HSI=48MHz，PCLK = 48M，（频率大于24M 需要配置FlashWait=2） + * GTIM1定时，48MHz 输入, PA6（CH1）输出 SPWM + * + * @return int32_t + */ +int32_t main(void) +{ + GTIM_InitTypeDef GTIM_InitStruct; + /* System Clocks Configuration */ + RCC_Configuration(); + RCC_AHBPeriphClk_Enable(RCC_AHB_PERIPH_FLASH, ENABLE); // 打开FLASH时钟 + FLASH_SetLatency(FLASH_Latency_2); // 频率大于24M需要配置FlashWait=2 + RCC_HSI_Enable(RCC_HSIOSC_DIV1); // 修改HSI分频为1，PCLK = HSI + /* GPIO Configuration */ + GPIO_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + GTIM_InitStruct.Mode = GTIM_MODE_TIME; + GTIM_InitStruct.OneShotMode = GTIM_COUNT_CONTINUE; + GTIM_InitStruct.Prescaler = GTIM_PRESCALER_DIV1; + //GTIM_InitStruct.ReloadValue = 60100UL >> 4; // PWM频率为 48M/60100*16=12k, SPWM频率 = 12k/2/200=30Hz + GTIM_InitStruct.ReloadValue = 60100UL - 1; // PWM频率为 48M/60100=800Hz, SPWM周期 = 800/2/1000= 0.4Hz + GTIM_InitStruct.ToggleOutState = DISABLE; + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + GTIM_OCInit(CW_GTIM1, GTIM_CHANNEL1, GTIM_OC_OUTPUT_PWM_HIGH); + GTIM_SetCompare1(CW_GTIM1, 0); + GTIM_ITConfig(CW_GTIM1, GTIM_IT_OV, ENABLE); + GTIM_Cmd(CW_GTIM1, ENABLE); + while (1) + { + /* 中断服务程序见interrupts_cw32f030.c */ + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + __RCC_GTIM1_CLK_ENABLE(); // GTIM1时钟使能 +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + /* PA6 PWM 输出 */ + __RCC_GPIOA_CLK_ENABLE(); + PA06_AFx_GTIM1CH1(); + PA06_DIR_OUTPUT(); + PA06_DIGTAL_ENABLE(); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(GTIM1_IRQn); + __enable_irq(); +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/readme.txt new file mode 100644 index 0000000..7a5cf1b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_SPWM_output/readme.txt @@ -0,0 +1,27 @@ +示例目的： + 控制GTIM输出正弦调制的PWM波形。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI，不分频，48MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=48MHz + 4. GTIM1由PCLK提供时钟，ARR为（60100 -1），PWM的频率为48MHz/60100=800Hz + 5. PA06设置为输出复用，GTIM1的CH1 + +演示说明： + GTIM1设置为比较输出的PWM模式，PWM的频率为800Hz。在中断中，通过查表的方式 + 改变GTIM1的CH1通道的比较值，实现PWM的正弦调制。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/EWARM/project.ewd new file mode 100644 index 0000000..916b5e7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/EWARM/project.ewd @@ -0,0 +1,1484 @@ + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 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$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/EWARM/project.ewp new file mode 100644 index 0000000..ee89cd1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/EWARM/project.ewp @@ -0,0 +1,2157 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + 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a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/EWARM/project.eww new file mode 100644 index 0000000..bc949a7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/EWARM/project.eww @@ -0,0 +1,6 @@ + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/MDK/project.uvoptx new file mode 100644 index 0000000..996ef6d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/MDK/project.uvoptx @@ -0,0 +1,339 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + GTIM_timer_toggle_out + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\GTIM1 + 35905 + + + + + + + Startup + 0 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + cw32f030_gtim.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/MDK/project.uvprojx new file mode 100644 index 0000000..5b53729 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/MDK/project.uvprojx @@ -0,0 +1,459 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + GTIM_timer_toggle_out + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + GTIM_timer_toggle_out + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/USER/inc/main.h new file mode 100644 index 0000000..e1d08df --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/USER/inc/main.h @@ -0,0 +1,74 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gtim.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_btim.h" +#include "cw32f030_flash.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..fa7e9c2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/USER/src/interrupts_cw32f030.c @@ -0,0 +1,406 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/USER/src/main.c new file mode 100644 index 0000000..532068f --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/USER/src/main.c @@ -0,0 +1,151 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief GTIM1计数溢出后，使PB12、PB13的输出翻转，PB09通过查询OV位翻转输出 + * @return int32_t + */ +int32_t main(void) +{ + GTIM_InitTypeDef GTIM_InitStruct; + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + GTIM_InitStruct.Mode = GTIM_MODE_TIME; + GTIM_InitStruct.OneShotMode = GTIM_COUNT_CONTINUE; + GTIM_InitStruct.Prescaler = GTIM_PRESCALER_DIV1024; + GTIM_InitStruct.ReloadValue = 9374; + GTIM_InitStruct.ToggleOutState = ENABLE; + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + GTIM_Cmd(CW_GTIM1, ENABLE); + while (1) + { + if (GTIM_GetITStatus(CW_GTIM1, GTIM_IT_OV)) + { + GTIM_ClearITPendingBit(CW_GTIM1, GTIM_IT_OV); + PB09_TOG(); + } + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + __RCC_GTIM1_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); + __RCC_FLASH_CLK_ENABLE(); // 打开FLASH时钟 + FLASH_SetLatency(FLASH_Latency_2); // 频率大于24M需要配置FlashWait=2 + RCC_HSI_Enable(RCC_HSIOSC_DIV1); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + /* PB12:GTIM1_TOGN AF6 + PB13:GTIM1_TOGP AF6 + */ + PB12_AFx_GTIM1TOGN(); + PB13_AFx_GTIM1TOGP(); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_12 | GPIO_PIN_13; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + /* PB09 输出 */ + PB09_DIGTAL_ENABLE(); + PB09_DIR_OUTPUT(); + PB09_PUSHPULL_ENABLE(); + PB09_SETHIGH(); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + /* __disable_irq(); + NVIC_EnableIRQ(GTIM1_IRQn); + __enable_irq(); */ +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/readme.txt new file mode 100644 index 0000000..ceed059 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/GTIM_timer_toggle_out/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 演示GTIM的TOGGLE输出功能。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI，不分频，48MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=48MHz + 4. GTIM1的分频系数设置为1024，ARR设置为48000000/1024/5-1，则GTIM1每 + 200ms溢出一次。 + 5. PB12，PB13复用为GTIM1_TOGN，GTIM1_TOGP + 6. 设置PB09为PUSH-PULL输出,驱动LED1 + +演示说明： + 程序运行后,PB12和PB13以2.5Hz的频率输出互补的方便，PB13的波形和PB09的 + 波形的相位一致。LED1以200ms的间隔闪烁。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/EWARM/project.ewd new file mode 100644 index 0000000..916b5e7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/EWARM/project.ewd @@ -0,0 +1,1484 @@ + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/EWARM/project.ewp new file mode 100644 index 0000000..acf95b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/EWARM/project.ewp @@ -0,0 +1,2160 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/EWARM/project.eww new file mode 100644 index 0000000..bc949a7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/EWARM/project.eww @@ -0,0 +1,6 @@ + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/MDK/project.uvoptx new file mode 100644 index 0000000..29300de --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/MDK/project.uvoptx @@ -0,0 +1,371 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + JL2CM3 + -U4294967295 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8027 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030 -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + CW_SYSCTRL + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\BTIM1 + 35905 + + + System Viewer\GTIM1 + 35903 + + + System Viewer\SYSCTRL + 35904 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + cw32f030_gtim.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_btim.c + cw32f030_btim.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/MDK/project.uvprojx new file mode 100644 index 0000000..59997dc --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/MDK/project.uvprojx @@ -0,0 +1,464 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + GTIM_timer_toggle_out + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_btim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_btim.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..e6ca935 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ +extern void GTIM1_IRQHandlerCallBack(void); +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/USER/inc/main.h new file mode 100644 index 0000000..e1d08df --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/USER/inc/main.h @@ -0,0 +1,74 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gtim.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_btim.h" +#include "cw32f030_flash.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..16efdcc --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + GTIM1_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/USER/src/main.c new file mode 100644 index 0000000..757d974 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/USER/src/main.c @@ -0,0 +1,164 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle GPIOA.00 + ** + ******************************************************************************/ + +/** + * @brief 使用BTIM1作为GTIM1的分频器，对PCLK进行48000分频 + * @return int32_t + */ +int32_t main(void) +{ + GTIM_InitTypeDef GTIM_InitStruct; + BTIM_TimeBaseInitTypeDef BTIM_InitStruct; + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + GTIM_InitStruct.Mode = GTIM_MODE_COUNTER; + GTIM_InitStruct.OneShotMode = GTIM_COUNT_CONTINUE; + GTIM_InitStruct.Prescaler = 1; // 计数时钟为TRS时，分频值不能为0，否则计数异常 + GTIM_InitStruct.ReloadValue = 999; + GTIM_InitStruct.ToggleOutState = DISABLE; + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + GTIM1_ITRConfig(ITR_SOURCE_BTIM1); + BTIM_InitStruct.BTIM_Mode = BTIM_Mode_TIMER; + BTIM_InitStruct.BTIM_OPMode = BTIM_OPMode_Repetitive; + BTIM_InitStruct.BTIM_Period = 47999; + BTIM_InitStruct.BTIM_Prescaler = BTIM_PRS_DIV1; + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_InitStruct); + GTIM_ITConfig(CW_GTIM1, GTIM_IT_OV, ENABLE); + GTIM_Cmd(CW_GTIM1, ENABLE); + BTIM_Cmd(CW_BTIM1, ENABLE); + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + // CW_SYSCTRL->APBEN1_f.GTIM1 = 1U; // + __RCC_FLASH_CLK_ENABLE(); // 打开FLASH时钟 + FLASH_SetLatency(FLASH_Latency_2); // 频率大于24M需要配置FlashWait=2 + RCC_HSI_Enable(RCC_HSIOSC_DIV1); + __RCC_BTIM_CLK_ENABLE(); + __RCC_GTIM1_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + PB09_DIGTAL_ENABLE(); + PB09_DIR_OUTPUT(); + PB09_PUSHPULL_ENABLE(); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(GTIM1_IRQn); + __enable_irq(); +} + +void GTIM1_IRQHandlerCallBack(void) +{ + if (GTIM_GetITStatus(CW_GTIM1, GTIM_IT_OV)) + { + GTIM_ClearITPendingBit(CW_GTIM1, GTIM_IT_OV); + PB09_TOG(); + } +} +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/readme.txt new file mode 100644 index 0000000..4308b02 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_counter_itr/readme.txt @@ -0,0 +1,28 @@ +示例目的： + GTIM和BTIM内部互联，可实现定时器的任意分频。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI，不分频，48MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=48MHz + 4. BTIM1由PCLK提供计数时钟，设置ARR为48000-1，则BTIM1 1ms溢出一次； + 5. GTIM1的计数时钟由BTIM1的溢出信号OV提供，设置ARR为1000-1，则GTIM1 + 1s溢出一次。 + 6. 设置PB09为PUSH-PULL输出,驱动LED1 + +演示说明： + 程序运行后,LED1每2s改变一次亮灭状态。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/EWARM/project.ewd new file mode 100644 index 0000000..916b5e7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/EWARM/project.ewd @@ -0,0 +1,1484 @@ + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 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$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/EWARM/project.ewp new file mode 100644 index 0000000..a633cee --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/EWARM/project.ewp @@ -0,0 +1,2157 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/EWARM/project.eww new file mode 100644 index 0000000..bc949a7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/EWARM/project.eww @@ -0,0 +1,6 @@ + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/MDK/project.uvoptx new file mode 100644 index 0000000..5bbdfb2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/MDK/project.uvoptx @@ -0,0 +1,360 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 79 + 1 +
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+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\GTIM_timer_toggle_out\../USER/src/main.c\79 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\GPIOB + 35904 + + + System Viewer\GTIM1 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + cw32f030_gtim.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/MDK/project.uvprojx new file mode 100644 index 0000000..cc8b5fa --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/MDK/project.uvprojx @@ -0,0 +1,460 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + GTIM_timer_toggle_out + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..e6ca935 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ +extern void GTIM1_IRQHandlerCallBack(void); +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/USER/inc/main.h new file mode 100644 index 0000000..9f73735 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/USER/inc/main.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "cw32f030_btim.h" +#include "cw32f030_flash.h" +#include "cw32f030_gpio.h" +#include "cw32f030_gtim.h" +#include "cw32f030_rcc.h" +#include "interrupts_cw32f030.h" +#include "system_cw32f030.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..5f08d9b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/USER/src/interrupts_cw32f030.c @@ -0,0 +1,408 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ + +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + GTIM1_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/USER/src/main.c new file mode 100644 index 0000000..f23d031 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/USER/src/main.c @@ -0,0 +1,160 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief GTIM1作为门控计数,PB2作为门控信号的输入引脚 + * @return int32_t + */ +int32_t main(void) +{ + GTIM_InitTypeDef GTIM_InitStruct; + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + GTIM_InitStruct.Mode = GTIM_MODE_GATE; + GTIM_InitStruct.OneShotMode = GTIM_COUNT_CONTINUE; + GTIM_InitStruct.Prescaler = GTIM_PRESCALER_DIV1024; + GTIM_InitStruct.ReloadValue = 9374; + GTIM_InitStruct.ToggleOutState = DISABLE; + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + GTIM_ETRConfig(CW_GTIM1, GTIM_ETR_POL_FALL_LOW, GTIM_ETR_FILTER_PCLKDIV8_N6); + GTIM_ITConfig(CW_GTIM1, GTIM_IT_OV, ENABLE); + GTIM_Cmd(CW_GTIM1, ENABLE); + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + __RCC_FLASH_CLK_ENABLE(); + __RCC_GTIM1_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); + __RCC_GPIOA_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_2); + RCC_HSI_Enable(RCC_HSIOSC_DIV1); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + /* PB2 ETR引脚 */ + GPIO_InitTypeDef GPIO_InitStruct; + PB02_AFx_GTIM1ETR(); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_InitStruct.Pins = GPIO_PIN_2; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_9; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_1; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(GTIM1_IRQn); + __enable_irq(); +} + +void GTIM1_IRQHandlerCallBack(void) +{ + if (GTIM_GetITStatus(CW_GTIM1, GTIM_IT_OV)) + { + GTIM_ClearITPendingBit(CW_GTIM1, GTIM_IT_OV); + PB09_TOG(); + } +} +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** +* @brief Reports the name of the source file and the source line number +* where the assert_param error has occurred. +* @param file: pointer to the source file name +* @param line: assert_param error line source number +* @retval None +*/ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/readme.txt new file mode 100644 index 0000000..32ea07f --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_gate/readme.txt @@ -0,0 +1,31 @@ +示例目的： + 演示GTIM的GATE控制计数。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI，不分频，48MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=48MHz + 4. GTIM1的分频系数设置为1024，ARR设置为48000000/1024/5-1，则GTIM1每 + 200ms溢出一次。 + 5. 设置PB2为输入复用，GTIM1_ETR, + 6. 设置PB09为PUSH-PULL输出,驱动LED1 + 7. 设置GTIM1_ETR的极性为低电平有效 + 8. 设置PA01为输入。 + 9. 使能GTIM1的中断溢出。 + +演示说明： + 使用杜邦线将PA01与PB2连接，按下KEY1键，并保持，则LED1以200ms的间隔闪烁。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/EWARM/project.ewd new file mode 100644 index 0000000..916b5e7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/EWARM/project.ewd @@ -0,0 +1,1484 @@ + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/EWARM/project.ewp new file mode 100644 index 0000000..a633cee --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/EWARM/project.ewp @@ -0,0 +1,2157 @@ + + + 3 + + Release + + ARM + + 0 + + General + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/EWARM/project.eww new file mode 100644 index 0000000..bc949a7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/EWARM/project.eww @@ -0,0 +1,6 @@ + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/MDK/project.uvoptx new file mode 100644 index 0000000..b346287 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/MDK/project.uvoptx @@ -0,0 +1,339 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\GTIM1 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + cw32f030_gtim.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/MDK/project.uvprojx new file mode 100644 index 0000000..cc8b5fa --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/MDK/project.uvprojx @@ -0,0 +1,460 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + GTIM_timer_toggle_out + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..e6ca935 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ +extern void GTIM1_IRQHandlerCallBack(void); +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/USER/inc/main.h new file mode 100644 index 0000000..9f73735 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/USER/inc/main.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "cw32f030_btim.h" +#include "cw32f030_flash.h" +#include "cw32f030_gpio.h" +#include "cw32f030_gtim.h" +#include "cw32f030_rcc.h" +#include "interrupts_cw32f030.h" +#include "system_cw32f030.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..5f08d9b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/USER/src/interrupts_cw32f030.c @@ -0,0 +1,408 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ + +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + GTIM1_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/USER/src/main.c new file mode 100644 index 0000000..723219c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/USER/src/main.c @@ -0,0 +1,163 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief GTIM1作为门控计数,PB2作为Trigger信号的输入引脚 + * @return int32_t + */ +int32_t main(void) +{ + GTIM_InitTypeDef GTIM_InitStruct; + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + GTIM_InitStruct.Mode = GTIM_MODE_TRIGGER; + GTIM_InitStruct.OneShotMode = GTIM_COUNT_CONTINUE; + GTIM_InitStruct.Prescaler = GTIM_PRESCALER_DIV1024; + GTIM_InitStruct.ReloadValue = 9374; + GTIM_InitStruct.ToggleOutState = DISABLE; + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + GTIM_ETRConfig(CW_GTIM1, GTIM_ETR_POL_RISE_HIGH, GTIM_ETR_FILTER_NONE); + GTIM_ITConfig(CW_GTIM1, GTIM_IT_OV, ENABLE); + while (1) + { + if (PA02_GETVALUE() == 0) + { + GTIM_Cmd(CW_GTIM1, DISABLE); + } + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + __RCC_FLASH_CLK_ENABLE(); + __RCC_GTIM1_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); + __RCC_GPIOA_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_2); + RCC_HSI_Enable(RCC_HSIOSC_DIV1); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + /* PB2 ETR引脚 */ + GPIO_InitTypeDef GPIO_InitStruct; + PB02_AFx_GTIM1ETR(); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_2; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_9; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_1 | GPIO_PIN_2; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(GTIM1_IRQn); + __enable_irq(); +} + +void GTIM1_IRQHandlerCallBack(void) +{ + if (GTIM_GetITStatus(CW_GTIM1, GTIM_IT_OV)) + { + GTIM_ClearITPendingBit(CW_GTIM1, GTIM_IT_OV); + PB09_TOG(); + } +} +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/readme.txt new file mode 100644 index 0000000..0760d27 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_etr_trigger/readme.txt @@ -0,0 +1,33 @@ +示例目的： + 演示GTIM的触发启动计数的功能。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI，不分频，48MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=48MHz + 4. GTIM1的分频系数设置为1024，ARR设置为48000000/1024/5-1，则GTIM1每 + 200ms溢出一次。 + 5. 设置PB2为输入复用，GTIM1_ETR, + 6. 设置PB09为PUSH-PULL输出,驱动LED1 + 7. 设置GTIM1_ETR的极性为上升沿有效 + 8. 设置PA01为输入。 + 9. 使能GTIM1的中断溢出。 + 10. 设置PA02为输入。 + +演示说明： + 使用杜邦线将PA01与PB2连接，按下KEY1键后释放，则LED1以200ms的间隔闪烁。 + 按下KEY2后，GTIM1停止计数，LED1不闪烁。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/EWARM/project.ewd new file mode 100644 index 0000000..0088482 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/EWARM/project.ewd @@ -0,0 +1,3088 @@ + + + 3 + + Release + + ARM + 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b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/EWARM/project.ewp new file mode 100644 index 0000000..916c069 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/EWARM/project.ewp @@ -0,0 +1,2157 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gtim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_btim.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/EWARM/project.eww new file mode 100644 index 0000000..bc949a7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/EWARM/project.eww @@ -0,0 +1,6 @@ + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/MDK/project.uvoptx new file mode 100644 index 0000000..980e196 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/MDK/project.uvoptx @@ -0,0 +1,345 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + PWMPeriod + + + 1 + 1 + PWMWidth + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + cw32f030_gtim.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_btim.c + cw32f030_btim.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/MDK/project.uvprojx new file mode 100644 index 0000000..27395f1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/MDK/project.uvprojx @@ -0,0 +1,459 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + GTIM_timer_toggle_out + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_btim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_btim.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..e6ca935 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ +extern void GTIM1_IRQHandlerCallBack(void); +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/USER/inc/main.h new file mode 100644 index 0000000..803d1ec --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "cw32f030_flash.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gtim.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_btim.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..5f08d9b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/USER/src/interrupts_cw32f030.c @@ -0,0 +1,408 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ + +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + GTIM1_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/USER/src/main.c new file mode 100644 index 0000000..7f1d0e7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/USER/src/main.c @@ -0,0 +1,190 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +static uint32_t PWMPeriod = 0; +static uint32_t PWMWidth = 0; + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief 使用GTIM1的CH1和CH2两个通道对PWM输入信号进行测量，CH1测量周期， + * CH2测量脉宽。 + * GTIM1_CH1：PA06 + * GTIM1_CH2: PA07 + * 将同一个PWM输入信号引入到PA06和PA07上。 + * @return int32_t + */ +int32_t main(void) +{ + GTIM_InitTypeDef GTIM_InitStruct; + GTIM_ICInitTypeDef GTIM_ICInitStruct; + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + GTIM_InitStruct.Mode = GTIM_MODE_TIME; + GTIM_InitStruct.OneShotMode = GTIM_COUNT_CONTINUE; + GTIM_InitStruct.Prescaler = GTIM_PRESCALER_DIV1; + GTIM_InitStruct.ReloadValue = 0xFFFF; + GTIM_InitStruct.ToggleOutState = DISABLE; + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + GTIM_ICInitStruct.CHx = GTIM_CHANNEL1; + GTIM_ICInitStruct.ICFilter = GTIM_CHx_FILTER_NONE; + GTIM_ICInitStruct.ICInvert = GTIM_CHx_INVERT_ON; + GTIM_ICInitStruct.ICPolarity = GTIM_ICPolarity_Rising; + GTIM_ICInit(CW_GTIM1, >IM_ICInitStruct); + GTIM_ICInitStruct.CHx = GTIM_CHANNEL2; + GTIM_ICInitStruct.ICPolarity = GTIM_ICPolarity_Falling; + GTIM_ICInit(CW_GTIM1, >IM_ICInitStruct); + GTIM_ITConfig(CW_GTIM1, GTIM_IT_CC1 | GTIM_IT_CC2 | GTIM_IT_OV, ENABLE); + GTIM_Cmd(CW_GTIM1, ENABLE); + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + __RCC_GTIM1_CLK_ENABLE(); + __RCC_GPIOA_CLK_ENABLE(); + RCC_HSI_Enable(RCC_HSIOSC_DIV6); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_6 | GPIO_PIN_7; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + PA06_AFx_GTIM1CH1(); + PA07_AFx_GTIM1CH2(); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(GTIM1_IRQn); + __enable_irq(); +} + +void GTIM1_IRQHandlerCallBack(void) +{ + static uint8_t stage = 0; + static uint32_t cnt = 0; + if (GTIM_GetITStatus(CW_GTIM1, GTIM_IT_OV)) + { + GTIM_ClearITPendingBit(CW_GTIM1, GTIM_IT_OV); + if (stage == 1) + { + cnt++; + } + } + if (GTIM_GetITStatus(CW_GTIM1, GTIM_IT_CC1)) + { + if (stage == 0) + { + PWMPeriod = GTIM_GetCapture1(CW_GTIM1); + stage = 1; + } + else if (stage == 1) + { + PWMPeriod = GTIM_GetCapture1(CW_GTIM1) + cnt * 65536 - PWMPeriod; + stage = 0; + cnt = 0; + } + GTIM_ClearITPendingBit(CW_GTIM1, GTIM_IT_CC1); + } + if (GTIM_GetITStatus(CW_GTIM1, GTIM_IT_CC2)) + { + if (stage == 1) + { + PWMWidth = GTIM_GetCapture2(CW_GTIM1) + cnt * 65536 - PWMPeriod; + } + GTIM_ClearITPendingBit(CW_GTIM1, GTIM_IT_CC2); + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** +* @brief Reports the name of the source file and the source line number +* where the assert_param error has occurred. +* @param file: pointer to the source file name +* @param line: assert_param error line source number +* @retval None +*/ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/readme.txt new file mode 100644 index 0000000..ea3a89e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/GTIM/gtim_pwm_input/readme.txt @@ -0,0 +1,28 @@ +示例目的： + 演示GTIM的输入捕获功能，测量PWM的频率和脉宽。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI，6分频，8MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=8MHz + 4. GTIM1不分频 + 5. 设置PA06复用为GTIM1_CH1, 上升沿触发捕获 + 6. 设置PA07复用为GTIM1_CH2，下降沿触发捕获。 + +演示说明： + 使用GTIM1的CH1和CH2两个通道对PWM输入信号进行测量，CH1测量周期， + CH2测量脉宽。 将同一个PWM输入信号引入到PA06和PA07上。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/EWARM/project.ewd new file mode 100644 index 0000000..0643ff9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/EWARM/project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/EWARM/project.ewp new file mode 100644 index 0000000..1e319f4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/EWARM/project.ewp @@ -0,0 +1,2163 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 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$PROJ_DIR$\..\..\..\..\Utilities\cw32f030c8t6_startkit.c + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/EWARM/project.eww new file mode 100644 index 0000000..bc949a7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/EWARM/project.eww @@ -0,0 +1,6 @@ + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/MDK/project.uvoptx new file mode 100644 index 0000000..e93b177 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/MDK/project.uvoptx @@ -0,0 +1,402 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + IWDT + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=474,100,885,602,0)(1007=-1,-1,-1,-1,0)(1008=786,152,1162,388,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 112 + 1 +
3168
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\IWDT\../USER/src/main.c\112 + + + + + 0 + 1 + LED1 + + + 1 + 1 + LED + + + 2 + 1 + IdealCount,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\IWDT + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_wwdt.c + cw32f030_wwdt.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_iwdt.c + cw32f030_iwdt.c + 0 + 0 + + + + + Utilities + 1 + 0 + 0 + 0 + + 4 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Utilities\cw32f030c8t6_startkit.c + cw32f030c8t6_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/MDK/project.uvprojx new file mode 100644 index 0000000..1cf7b6a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/MDK/project.uvprojx @@ -0,0 +1,473 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + IWDT + 0x4 + ARM-ADS + 6190000::V6.19::ARMCLANG + 1 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + IWDT + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 5 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\Utilities + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + cw32f030_wwdt.c + 1 + ..\..\..\..\Libraries\src\cw32f030_wwdt.c + + + cw32f030_iwdt.c + 1 + ..\..\..\..\Libraries\src\cw32f030_iwdt.c + + + + + Utilities + + + cw32f030c8t6_startkit.c + 1 + ..\..\..\..\Utilities\cw32f030c8t6_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..16911df --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,101 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ +extern void GPIOA_IRQHandlerCallback(void); +extern void WDT_IRQHandlerCallback(void); +extern void SysTick_HandlerCallback(void); +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/USER/inc/main.h new file mode 100644 index 0000000..c729253 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/USER/inc/main.h @@ -0,0 +1,70 @@ +/** + * @file main.h + * @author WHXY + * @brief Header for main.c file. + * This file contains the common defines of the application. + * @version 0.1 + * @date 2021-04-22 + * + * @copyright Copyright (c) 2021 + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +//#include "device.h" +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_iwdt.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030c8t6_startkit.h" +#include "cw32f030_flash.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..ef0cdc3 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/USER/src/interrupts_cw32f030.c @@ -0,0 +1,305 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/main.h" +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + WDT_IRQHandlerCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM + */ +void GTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C + */ +void I2C_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI + */ +void SPI_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/USER/src/main.c new file mode 100644 index 0000000..48a150d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/USER/src/main.c @@ -0,0 +1,204 @@ +/** + * @file main.c + * @author WHXY + * @brief 本示例说明如何定期更新 IWDT 重载计数器，以及如何模拟软件故障，使编程好 + * 的时间段到期时生成 MCU IWDT 中断。 + * -独立看门狗超时设置为 250 ms + * -系统节拍配置为每 250 ms 产生一个中断 + * -在系统节拍中断服务例程中，将重载独立看门狗计数器以防止独立看门狗复位，并且将 + * 闪烁 LED1（PB9） + * -PA1 引脚连接的按钮S1配置为在其下降沿上产生中断 + * -在 NVIC 中，将PA1对应中断向量且优先级等于0，并且 SysTick 中断向量优先级设置 + * 为 1（PA1的中断优先于 SysTick 中断）。 + * - 按钮S1（PA1）用于模拟软件故障：S1按下后，进入对应的中断服务程序，且中断标志 + * 位不清零，CPU不会进入入系统节拍中断例程，因此不会重载独立看门狗计数器。 + * 当独立看门狗计数器溢出时，独立看门狗将产生一个中断。 + * 程序发生IWDT中断后，LED2翻转。 + * @version 0.1 + * @date 2021-04-22 + * + * @copyright Copyright (c) 2021 + * + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + * +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IWDT_DURATION 250 // 250ms +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ +LED_InitTypeDef LED1, LED2; + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * @return int32_t + */ +int32_t main(void) +{ + IWDT_InitTypeDef IWDT_InitStruct = {0}; + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + SysTick_Config(SystemCoreClock / 1000 * 250); // 250ms + LED1.LED_Port = CW_GPIOB; + LED1.LED_Pin = GPIO_PIN_9; + LED_Init(&LED1); + LED1.LED_Off(&LED1); + LED2.LED_Port = CW_GPIOB; + LED2.LED_Pin = GPIO_PIN_8; + LED_Init(&LED2); + LED2.LED_Off(&LED2); + IWDT_InitStruct.IWDT_ITState = ENABLE; + IWDT_InitStruct.IWDT_OverFlowAction = IWDT_OVERFLOW_ACTION_INT; //溢出后产生中断不复位 + IWDT_InitStruct.IWDT_Pause = IWDT_SLEEP_PAUSE; + IWDT_InitStruct.IWDT_Prescaler = IWDT_Prescaler_DIV4; + IWDT_InitStruct.IWDT_ReloadValue = (IWDT_FREQ >> 2) / 1000 * 280 - 1; // 由于IWDT的时钟为RC10K, 设置为280实际溢出时间为256ms左右 + IWDT_InitStruct.IWDT_WindowValue = 0xFFF; + IWDT_Init(&IWDT_InitStruct); + IWDT_Cmd(); + /* NVIC Configuration */ + NVIC_Configuration(); + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + /* 0. HSI使能并校准 */ + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + /* 1. 设置HCLK和PCLK的分频系数　*/ + RCC_HCLKPRS_Config(RCC_HCLK_DIV1); + RCC_PCLKPRS_Config(RCC_PCLK_DIV1); + /* 2. 使能PLL，通过HSI倍频到48MHz */ + RCC_PLL_Enable(RCC_PLLSOURCE_HSI, 8000000, 6); // HSI 默认输出频率8MHz + RCC_PLL_OUT(); + ///< 当使用的时钟源HCLK大于24M,小于等于48MHz：设置FLASH 读等待周期为2 cycle + __RCC_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_2); + /* 3. 时钟切换到PLL */ + RCC_SysClk_Switch(RCC_SYSCLKSRC_PLL); + RCC_SystemCoreClockUpdate(48000000); + /* 4. 配置外设时钟 */ + __RCC_IWDT_CLK_ENABLE(); //使能IWDT模块 + __RCC_GPIOB_CLK_ENABLE(); + __RCC_GPIOA_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + /* 配置PA1为按键输入 */ + GPIO_InitStruct.IT = GPIO_IT_FALLING; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_1; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(WDT_IRQn); + NVIC_SetPriority(GPIOA_IRQn, 0); + NVIC_SetPriority(SysTick_IRQn, 1); + NVIC_EnableIRQ(GPIOA_IRQn); + __enable_irq(); +} + +void GPIOA_IRQHandlerCallback(void) +{ +} + +void SysTick_HandlerCallback(void) +{ + LED1.LED_Toggle(&LED1); + IWDT_Refresh(); +} + +void WDT_IRQHandlerCallback(void) +{ + if (CW_IWDT->SR & IWDT_SR_OV_Msk) + { + IWDT_ClearOVFlag(); + LED2.LED_Toggle(&LED2); + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/readme.txt new file mode 100644 index 0000000..e36d911 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_int/readme.txt @@ -0,0 +1,39 @@ +示例目的： + 模拟软件发生故障时，独立看门狗IWDT产生中断。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为PLL，由HSI提供的8MHz时钟6倍频到48MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=48MHz + 4. IWDT由独立时钟RC10K经4分频，即0.4ms计数一次 + 5. PB09设置为PUSH-PULL输出 + 6. PB08设置为PUSH-PULL输出 + 7. PA01设置为输入 + 8. 系统节拍定时器设置为250ms产生一次中断 + +演示说明： + 系统时钟由HSI提供，通过PLL倍频到48MHz。配置IWDT的ARR为699，即IWDT的计时时常为 + （699 + 1）* 0.4ms = 280ms，并且溢出后产生中断，不复位。 + 系统节拍配置为每 250 ms 产生一个中断，中断复位程序中闪烁 LED1（PB9），并喂狗。 + PA1 引脚连接的按钮S1配置为在其下降沿上产生中断。 + 在 NVIC 中，将PA1对应中断向量且优先级等于0，并且 SysTick 中断向量优先级设置为1 + （PA1的中断优先于 SysTick 中断）。 + 按钮KEY1（PA1）用于模拟软件故障：KEY1按下后，进入对应的中断服务程序，且中断标志 + 位不清零，CPU不会进入系统节拍中断服务程序，因此不会重载IWDT计数器。 + 当IWDT计数器溢出时，IWDT将产生一个中断。中断服务程序中LED2的状态翻转。 + 当程序正常运行时，LED1以250ms的间隔闪烁，当按下KEY1后，LED1不再闪烁，状态长亮或 + 长灭，LED2开始闪烁，间隔大约280ms。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/EWARM/project.ewd new file mode 100644 index 0000000..916b5e7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/EWARM/project.ewd @@ -0,0 +1,1484 @@ + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 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$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/EWARM/project.ewp new file mode 100644 index 0000000..1e319f4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/EWARM/project.ewp @@ -0,0 +1,2163 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_wwdt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_iwdt.c + + + + Utilities + + $PROJ_DIR$\..\..\..\..\Utilities\cw32f030c8t6_startkit.c + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/EWARM/project.eww new file mode 100644 index 0000000..bc949a7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/EWARM/project.eww @@ -0,0 +1,6 @@ + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/MDK/project.uvoptx new file mode 100644 index 0000000..a2dc2c4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/MDK/project.uvoptx @@ -0,0 +1,380 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + IWDT + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=474,100,885,602,0)(1007=-1,-1,-1,-1,0)(1008=786,152,1162,388,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + LED1 + + + 1 + 1 + LED + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\IWDT + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 1 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_wwdt.c + cw32f030_wwdt.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_iwdt.c + cw32f030_iwdt.c + 0 + 0 + + + + + Utilities + 0 + 0 + 0 + 0 + + 4 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Utilities\cw32f030c8t6_startkit.c + cw32f030c8t6_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/MDK/project.uvprojx new file mode 100644 index 0000000..73169db --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/MDK/project.uvprojx @@ -0,0 +1,471 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + IWDT + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + IWDT + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\Utilities + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + cw32f030_wwdt.c + 1 + ..\..\..\..\Libraries\src\cw32f030_wwdt.c + + + cw32f030_iwdt.c + 1 + ..\..\..\..\Libraries\src\cw32f030_iwdt.c + + + + + Utilities + + + cw32f030c8t6_startkit.c + 1 + ..\..\..\..\Utilities\cw32f030c8t6_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..16911df --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,101 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ +extern void GPIOA_IRQHandlerCallback(void); +extern void WDT_IRQHandlerCallback(void); +extern void SysTick_HandlerCallback(void); +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/USER/inc/main.h new file mode 100644 index 0000000..c729253 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/USER/inc/main.h @@ -0,0 +1,70 @@ +/** + * @file main.h + * @author WHXY + * @brief Header for main.c file. + * This file contains the common defines of the application. + * @version 0.1 + * @date 2021-04-22 + * + * @copyright Copyright (c) 2021 + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +//#include "device.h" +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_iwdt.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030c8t6_startkit.h" +#include "cw32f030_flash.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..e51d003 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/USER/src/interrupts_cw32f030.c @@ -0,0 +1,401 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + +void SysTick_Handler(void) +{ + SysTick_HandlerCallback(); +} + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + WDT_IRQHandlerCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + GPIOA_IRQHandlerCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/USER/src/main.c new file mode 100644 index 0000000..366c54c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/USER/src/main.c @@ -0,0 +1,211 @@ +/** + * @file main.c + * @author WHXY + * @brief 本示例说明如何定期更新 IWDT 重载计数器，以及如何模拟软件故障，使编程好 + * 的时间段到期时生成 MCU IWDT 复位。 + * -独立看门狗超时设置为 250 ms + * -系统节拍配置为每 250 ms 产生一个中断 + * -在系统节拍中断服务例程中，将重载独立看门狗计数器以防止独立看门狗复位，并且将 + * 闪烁 LED1（PB9） + * -PA1 引脚连接的按钮S1配置为在其下降沿上产生中断 + * -在 NVIC 中，将PA1对应中断向量且优先级等于0，并且 SysTick 中断向量优先级设置 + * 为 1（PA1的中断优先于 SysTick 中断）。 + * - 按钮S1（PA1）用于模拟软件故障：S1按下后，进入对应的中断服务程序，且中断标志 + * 位不清零，CPU不会进入入系统节拍中断例程，因此不会重载独立看门狗计数器。 + * 当独立看门狗计数器溢出时，独立看门狗将产生一个复位。 + * 程序发生IWDT复位后，LED2亮起。 + * @version 0.1 + * @date 2021-04-22 + * + * @copyright Copyright (c) 2021 + * +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IWDT_DURATION 250 // 250ms +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ +LED_InitTypeDef LED1, LED2; + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * @return int32_t + */ +int32_t main(void) +{ + IWDT_InitTypeDef IWDT_InitStruct = {0}; + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + SysTick_Config(SystemCoreClock / 1000 * 250); // 250ms + LED1.LED_Port = CW_GPIOB; + LED1.LED_Pin = GPIO_PIN_9; + LED_Init(&LED1); + LED1.LED_On(&LED1); + for (volatile int32_t i = 5000000; i; i--); + LED1.LED_Off(&LED1); + LED2.LED_Port = CW_GPIOB; + LED2.LED_Pin = GPIO_PIN_8; + LED_Init(&LED2); + LED2.LED_Off(&LED2); + IWDT_InitStruct.IWDT_ITState = DISABLE; + IWDT_InitStruct.IWDT_OverFlowAction = IWDT_OVERFLOW_ACTION_RESET; + IWDT_InitStruct.IWDT_Pause = IWDT_SLEEP_PAUSE; + IWDT_InitStruct.IWDT_Prescaler = IWDT_Prescaler_DIV128; + IWDT_InitStruct.IWDT_ReloadValue = 800; // 10s + IWDT_InitStruct.IWDT_WindowValue = 0xFFF; + IWDT_Init(&IWDT_InitStruct); + IWDT_Cmd(); + while (!CW_IWDT->SR_f.RUN); + IWDT_Refresh(); + /* NVIC Configuration */ + NVIC_Configuration(); + if (RCC_GetRstFlag(RCC_FLAG_IWDTRST)) + { + LED2.LED_On(&LED2); + // RCC_ClearRstFlag(RCC_FLAG_IWDTRST); + } + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + /* 0. HSI使能并校准 */ + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + /* 1. 设置HCLK和PCLK的分频系数　*/ + RCC_HCLKPRS_Config(RCC_HCLK_DIV1); + RCC_PCLKPRS_Config(RCC_PCLK_DIV1); + /* 2. 使能PLL，通过HSI倍频到48MHz */ + RCC_PLL_Enable(RCC_PLLSOURCE_HSI, 8000000, 6); // HSI 默认输出频率8MHz + RCC_PLL_OUT(); + ///< 当使用的时钟源HCLK大于24M,小于等于48MHz：设置FLASH 读等待周期为2 cycle + __RCC_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_2); + /* 3. 时钟切换到PLL */ + RCC_SysClk_Switch(RCC_SYSCLKSRC_PLL); + RCC_SystemCoreClockUpdate(48000000); + /* 4. 配置外设时钟 */ + __RCC_IWDT_CLK_ENABLE(); //使能IWDT模块 + __RCC_GPIOB_CLK_ENABLE(); + __RCC_GPIOA_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + /* 配置PA1为按键输入 */ + GPIO_InitStruct.IT = GPIO_IT_FALLING; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_1; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + // NVIC_EnableIRQ(WDT_IRQn); + NVIC_SetPriority(GPIOA_IRQn, 0); + NVIC_SetPriority(SysTick_IRQn, 1); + NVIC_EnableIRQ(GPIOA_IRQn); + __enable_irq(); +} + +void GPIOA_IRQHandlerCallback(void) +{ + LED1.LED_Off(&LED1); +} + +void SysTick_HandlerCallback(void) +{ + // LED1.LED_Toggle(&LED1); + // IWDT_Refresh(); +} + +void WDT_IRQHandlerCallback(void) +{ +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/readme.txt new file mode 100644 index 0000000..620c4a5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IWDT/IWDT_reset/readme.txt @@ -0,0 +1,38 @@ +示例目的： + 模拟软件发生故障时，独立看门狗IWDT复位系统的功能。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为PLL，由HSI提供的8MHz时钟6倍频到48MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=48MHz + 4. IWDT由独立时钟RC10K经128分频，即12.8ms计数一次 + 5. PB09设置为PUSH-PULL输出 + 6. PB08设置为PUSH-PULL输出 + 7. PA01设置为输入 + 8. 系统节拍定时器设置为250ms产生一次中断 + +演示说明： + 系统时钟由HSI提供，频率48MHz。配置IWDT的ARR为800，即IWDT的计时时常为 + （800 + 1）* 12.8ms = 10s，当IWDT计数溢出后，系统复位 + 系统节拍配置为每 250 ms 产生一个中断，中断复位程序中闪烁 LED1（PB9），并喂狗。 + PA1 引脚连接的按钮S1配置为在其下降沿上产生中断。 + 在 NVIC 中，将PA1对应中断向量且优先级等于0，并且 SysTick 中断向量优先级设置为1 + （PA1的中断优先于 SysTick 中断）。 + 按钮KEY1（PA1）用于模拟软件故障：KEY1按下后，进入对应的中断服务程序，且中断标志 + 位不清零，CPU不会进入系统节拍中断服务程序，因此不会重载IWDT计数器。 + 当IWDT计数器溢出时，IWDT将复位系统。程序发生IWDT复位后，LED2亮起。 + + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/EWARM/project.ewd new file mode 100644 index 0000000..4564814 --- /dev/null +++ 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$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/EWARM/project.ewp new file mode 100644 index 0000000..d856ec9 --- /dev/null +++ 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_atim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Utilities\cw32f030c8t6_startkit.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gtim.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/EWARM/project.eww new file mode 100644 index 0000000..c78ed98 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/MDK/project.uvoptx new file mode 100644 index 0000000..b13b0ed --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/MDK/project.uvoptx @@ -0,0 +1,381 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=120,153,364,299,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U4294967295 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030_72K -FS00 -FL012000 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + ADC_ConvertedVoltage + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_atim.c + cw32f030_atim.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Utilities\cw32f030c8t6_startkit.c + cw32f030c8t6_startkit.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_adc.c + cw32f030_adc.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + cw32f030_gtim.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/MDK/project.uvprojx new file mode 100644 index 0000000..df2ff0e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/MDK/project.uvprojx @@ -0,0 +1,475 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\Utilities + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_atim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_atim.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030c8t6_startkit.c + 1 + ..\..\..\..\Utilities\cw32f030c8t6_startkit.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + cw32f030_adc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_adc.c + + + cw32f030_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/USER/inc/main.h new file mode 100644 index 0000000..c681677 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/USER/inc/main.h @@ -0,0 +1,77 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_rcc.h" +#include "cw32f030_flash.h" +#include "cw32f030_iwdt.h" +#include "cw32f030_gpio.h" +#include "cw32f030_gtim.h" +#include "cw32f030c8t6_startkit.h" + + + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ +extern uint16_t ADC_ConvertedValue; +extern float ADC_ConvertedVoltage; +extern uint8_t ADC_ConvertedFlag; + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..0c89748 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/USER/src/interrupts_cw32f030.c @@ -0,0 +1,410 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/USER/src/main.c new file mode 100644 index 0000000..06a095e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/USER/src/main.c @@ -0,0 +1,238 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +static void GTIM1_Config(void); +static void GTIM2_Config(void); +static void LED2_Init(void); +void IrDA_Send(const uint8_t *pData, uint16_t len); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +LED_InitTypeDef LED2; +uint32_t DelayTime; +static uint8_t DataBuffer[10] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A}; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + RCC_Configuration(); // HSI时钟源，PLL倍频64MHz，PCLK=HCLK=64MHz + /* SWD 口将做普通IO口用，这段代码防止不能烧程序 */ + LED2_Init(); + LED2.LED_On(&LED2); + // for (DelayTime=0x1ffffff;DelayTime; --DelayTime); + // LED2.LED_Off(&LED2); + /* 关闭SWD口 */ + // GPIO_SWD2GPIO(); + /* GPIO Configuration */ + GPIO_Configuration(); + GTIM1_Config(); + GTIM2_Config(); + CW_SYSCTRL->IRMOD_f.MOD = 0; + /* NVIC Configuration */ + NVIC_Configuration(); + while (1) + { + IrDA_Send(DataBuffer, 10); + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + /* 0. HSI使能并校准 */ + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + /* 1. 设置HCLK和PCLK的分频系数　*/ + RCC_HCLKPRS_Config(RCC_HCLK_DIV1); + RCC_PCLKPRS_Config(RCC_PCLK_DIV1); + /* 2. 使能PLL，通过HSI倍频到64MHz */ + RCC_PLL_Enable(RCC_PLLSOURCE_HSI, 8000000, 8); // HSI 默认输出频率8MHz + RCC_PLL_OUT(); + ///< 当使用的时钟源HCLK大于48M,小于等于72MHz：设置FLASH 读等待周期为3 cycle + __RCC_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_3); + /* 3. 时钟切换到PLL */ + RCC_SysClk_Switch(RCC_SYSCLKSRC_PLL); + RCC_SystemCoreClockUpdate(64000000); +} + +/** + * @brief Configure the GPIO Pins. + * 测试：同时配置PA13和PB9为IR_OUT,是否可以同时输出 + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + __RCC_GPIOA_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); + // PA13_AFx_IROUT(); + PB09_AFx_IROUT(); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_13; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + // GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + GPIO_InitStruct.Pins = GPIO_PIN_9; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); +} + + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + __enable_irq(); +} + +/** + * @brief GTIM1设置为PWM，产生38KHz的载波 + * + */ +static void GTIM1_Config(void) +{ + GTIM_InitTypeDef GTIM_InitStruct; + __RCC_GTIM1_CLK_ENABLE(); + GTIM_InitStruct.Mode = GTIM_MODE_TIME; + GTIM_InitStruct.OneShotMode = GTIM_COUNT_CONTINUE; + GTIM_InitStruct.Prescaler = GTIM_PRESCALER_DIV4; // DCLK = 16MHz + GTIM_InitStruct.ReloadValue = 16000 / 38 - 1; + GTIM_InitStruct.ToggleOutState = DISABLE; + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + GTIM_OCInit(CW_GTIM1, GTIM_CHANNEL1, GTIM_OC_OUTPUT_PWM_LOW); + GTIM_SetCompare1(CW_GTIM1, GTIM_InitStruct.ReloadValue / 3); + GTIM_Cmd(CW_GTIM1, ENABLE); +} + +static void GTIM2_Config(void) +{ + GTIM_InitTypeDef GTIM_InitStruct; + __RCC_GTIM2_CLK_ENABLE(); + GTIM_InitStruct.Mode = GTIM_MODE_TIME; + GTIM_InitStruct.OneShotMode = GTIM_COUNT_CONTINUE; + GTIM_InitStruct.Prescaler = GTIM_PRESCALER_DIV64; // DCLK = 1MHz + GTIM_InitStruct.ReloadValue = 2240 - 1; + GTIM_InitStruct.ToggleOutState = DISABLE; + GTIM_TimeBaseInit(CW_GTIM2, >IM_InitStruct); + GTIM_OCInit(CW_GTIM2, GTIM_CHANNEL1, GTIM_OC_OUTPUT_PWM_LOW); + GTIM_SetCompare1(CW_GTIM2, 560); + // GTIM_Cmd(CW_GTIM2, ENABLE); +} + +static void LED2_Init(void) +{ + LED2.LED_Port = CW_GPIOB; + LED2.LED_Pin = GPIO_PIN_8; + LED_Init(&LED2); +} + +void IrDA_Send(const uint8_t *pData, uint16_t len) +{ + uint8_t i; + CW_GTIM1->CR0_f.EN = 1; + while (len--) + { + for (i = 0; i < 8; i++) + { + if (*pData & (1 << i)) + { + CW_GTIM2->CR0_f.EN = 0; + CW_GTIM2->ICR_f.OV = 0; + CW_GTIM2->CNT = 0; + CW_GTIM2->CCR1 = 560; + CW_GTIM2->ARR = 2239; + CW_GTIM2->CR0_f.EN = 1; + while (!CW_GTIM2->ISR_f.OV); + } + else + { + CW_GTIM2->CR0_f.EN = 0; + CW_GTIM2->ICR_f.OV = 0; + CW_GTIM2->CNT = 0; + CW_GTIM2->CCR1 = 560; + CW_GTIM2->ARR = 1119; + CW_GTIM2->CR0_f.EN = 1; + while (!CW_GTIM2->ISR_f.OV) + ; + } + } + } + CW_GTIM1->CNT = 0; + CW_GTIM1->CR0_f.EN = 0; +} +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/readme.txt new file mode 100644 index 0000000..220882c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_UPD6121/readme.txt @@ -0,0 +1,26 @@ +示例目的： + 演示GTIM1和GTIM2联合产生IrDA的输出波形 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，PLL 8倍频至64MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=64MHz + 4. GTIM1生成38kHz载波 + 5. GTIM2使用PWM模式调制GTIM1的38KHz载波。 + +演示说明： + PB09输出IrDA调制的波形。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/EWARM/project.ewd new file mode 100644 index 0000000..03f4ad3 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/EWARM/project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + 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+ $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_uart.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/EWARM/project.eww new file mode 100644 index 0000000..c78ed98 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/MDK/project.uvoptx new file mode 100644 index 0000000..348e7c3 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/MDK/project.uvoptx @@ -0,0 +1,410 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=120,153,364,299,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U4294967295 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030_72K -FS00 -FL012000 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 217 + 1 +
2476
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\project\../USER/src/main.c\217 + + + + + 0 + 1 + ADC_ConvertedVoltage + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_atim.c + cw32f030_atim.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Utilities\cw32f030c8t6_startkit.c + cw32f030c8t6_startkit.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_adc.c + cw32f030_adc.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + cw32f030_gtim.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/MDK/project.uvprojx new file mode 100644 index 0000000..2e5be9d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/MDK/project.uvprojx @@ -0,0 +1,480 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\Utilities + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_atim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_atim.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030c8t6_startkit.c + 1 + ..\..\..\..\Utilities\cw32f030c8t6_startkit.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + cw32f030_adc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_adc.c + + + cw32f030_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/USER/inc/main.h new file mode 100644 index 0000000..775bf25 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/USER/inc/main.h @@ -0,0 +1,78 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_rcc.h" +#include "cw32f030_flash.h" +#include "cw32f030_iwdt.h" +#include "cw32f030_gpio.h" +#include "cw32f030_gtim.h" +#include "cw32f030_uart.h" +#include "cw32f030c8t6_startkit.h" + + + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ +extern uint16_t ADC_ConvertedValue; +extern float ADC_ConvertedVoltage; +extern uint8_t ADC_ConvertedFlag; + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..0c89748 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/USER/src/interrupts_cw32f030.c @@ -0,0 +1,410 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/USER/src/main.c new file mode 100644 index 0000000..a3a1cf6 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/USER/src/main.c @@ -0,0 +1,215 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +static void GTIM1_Config(void); +static void UART1_Config(void); +static void LED2_Init(void); +void IrDA_Send(const uint8_t *pData, uint16_t len); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +LED_InitTypeDef LED2; +uint32_t DelayTime; +static uint8_t DataBuffer[10] = {0xFF, 0xC3, 0x55, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A}; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + RCC_Configuration(); // HSI时钟源，PLL倍频64MHz，PCLK=HCLK=64MHz + LED2_Init(); + LED2.LED_On(&LED2); + /* GPIO Configuration */ + GPIO_Configuration(); + GTIM1_Config(); + UART1_Config(); + CW_SYSCTRL->IRMOD_f.MOD = 8; + /* NVIC Configuration */ + NVIC_Configuration(); + while (1) + { + IrDA_Send(DataBuffer, 3); + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + /* 0. HSI使能并校准 */ + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + /* 1. 设置HCLK和PCLK的分频系数　*/ + RCC_HCLKPRS_Config(RCC_HCLK_DIV1); + RCC_PCLKPRS_Config(RCC_PCLK_DIV1); + /* 2. 使能PLL，通过HSI倍频到64MHz */ + RCC_PLL_Enable(RCC_PLLSOURCE_HSI, 8000000, 8); // HSI 默认输出频率8MHz + RCC_PLL_OUT(); + ///< 当使用的时钟源HCLK大于48M,小于等于72MHz：设置FLASH 读等待周期为3 cycle + __RCC_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_3); + /* 3. 时钟切换到PLL */ + RCC_SysClk_Switch(RCC_SYSCLKSRC_PLL); + RCC_SystemCoreClockUpdate(64000000); +} + +/** + * @brief Configure the GPIO Pins. + * 测试：同时配置PA13和PB9为IR_OUT,是否可以同时输出 + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + __RCC_GPIOA_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); + // PA13_AFx_IROUT(); + PB09_AFx_IROUT(); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_13; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + // GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + GPIO_InitStruct.Pins = GPIO_PIN_9; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); +} + + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(ATIM_IRQn); + NVIC_EnableIRQ(ADC_IRQn); + __enable_irq(); +} + +/** + * @brief GTIM1设置为PWM，产生115.2KHz的载波 + * + */ +static void GTIM1_Config(void) +{ + GTIM_InitTypeDef GTIM_InitStruct; + __RCC_GTIM1_CLK_ENABLE(); + GTIM_InitStruct.Mode = GTIM_MODE_TIME; + GTIM_InitStruct.OneShotMode = GTIM_COUNT_CONTINUE; + GTIM_InitStruct.Prescaler = GTIM_PRESCALER_DIV4; // DCLK = 16MHz + GTIM_InitStruct.ReloadValue = 138; // 115.2kHz 载波频率 = 16000 / 115.2 - 1 + GTIM_InitStruct.ToggleOutState = DISABLE; + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + GTIM_OCInit(CW_GTIM1, GTIM_CHANNEL1, GTIM_OC_OUTPUT_PWM_LOW); + GTIM_SetCompare1(CW_GTIM1, (GTIM_InitStruct.ReloadValue + 1) / 16 * 3); + GTIM_Cmd(CW_GTIM1, ENABLE); +} + +static void UART1_Config(void) +{ + USART_InitTypeDef USART_InitStruct; + __RCC_UART1_CLK_ENABLE(); + USART_InitStruct.USART_BaudRate = 115200; + USART_InitStruct.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStruct.USART_Mode = USART_Mode_Tx; // 发送使能 + USART_InitStruct.USART_Over = USART_Over_16; + USART_InitStruct.USART_Parity = USART_Parity_No; + USART_InitStruct.USART_Source = USART_Source_PCLK; + USART_InitStruct.USART_StartBit = USART_StartBit_LL; + USART_InitStruct.USART_StopBits = USART_StopBits_1; + USART_InitStruct.USART_UclkFreq = SystemCoreClock; + USART_Init(CW_UART1, &USART_InitStruct); +} + +static void LED2_Init(void) +{ + LED2.LED_Port = CW_GPIOB; + LED2.LED_Pin = GPIO_PIN_8; + LED_Init(&LED2); +} + +void IrDA_Send(const uint8_t *pData, uint16_t len) +{ + CW_GTIM1->CNT = 0; + CW_GTIM1->CR0_f.EN = 1; + while (len--) + { + USART_SendData_8bit(CW_UART1, *pData); + while (CW_UART1->ISR_f.TXBUSY) + ; + pData++; + } + CW_GTIM1->CR0_f.EN = 0; +} +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/readme.txt new file mode 100644 index 0000000..86c7291 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/IrDA/IrDA_uart1/readme.txt @@ -0,0 +1,26 @@ +示例目的： + 演示GTIM1和UART1联合产生IrDA的输出波形 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，PLL 8倍频至64MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=64MHz + 4. GTIM1生成115.2kHz载波 + 5. UART1的TXD调制GTIM1的产生的载波。 + +演示说明： + PB09输出IrDA调制的波形。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/EWARM/lvd_detect_falling_irq.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/EWARM/lvd_detect_falling_irq.ewd new file mode 100644 index 0000000..d09623c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/EWARM/lvd_detect_falling_irq.ewd @@ -0,0 +1,3269 @@ + + + + 2 + + Release + + ARM + + 0 + + C-SPY + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 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/dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/EWARM/lvd_detect_falling_irq.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\lvd_detect_falling_irq.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/MDK/lvd_detect_falling_irq.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/MDK/lvd_detect_falling_irq.uvoptx new file mode 100644 index 0000000..3c61d6c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/MDK/lvd_detect_falling_irq.uvoptx @@ -0,0 +1,333 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + lvd_detect_falling_irq + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U4294967295 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_lvd.c + cw32f030_lvd.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/MDK/lvd_detect_falling_irq.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/MDK/lvd_detect_falling_irq.uvprojx new file mode 100644 index 0000000..12978a8 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/MDK/lvd_detect_falling_irq.uvprojx @@ -0,0 +1,461 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + lvd_detect_falling_irq + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + lvd_detect_falling_irq + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_lvd.c + 1 + ..\..\..\..\Libraries\src\cw32f030_lvd.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/USER/inc/main.h new file mode 100644 index 0000000..c177984 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void LVD_PortInit(void); +void LED_Init(void); +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..090d4ec --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/USER/src/interrupts_cw32f030.c @@ -0,0 +1,413 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_lvd.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +extern volatile boolean_t gFlagIrq; +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + LVD_ClearIrq(); + gFlagIrq = TRUE; + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/USER/src/main.c new file mode 100644 index 0000000..84d8da8 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/USER/src/main.c @@ -0,0 +1,161 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-07-14 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_systick.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_lvd.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +volatile boolean_t gFlagIrq = FALSE; + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief LVD I/O初始化 + * + */ +void LVD_PortInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk | SYSCTRL_AHBEN_GPIOB_Msk); + //打开LVD时钟:PCLK. + //... + //set PA08 as output + GPIO_InitStructure.Pins = GPIO_PIN_8; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + //set PA08 as LVD output + PA08_AFx_LVDOUT(); + //set PB11 as LVD source + PB11_ANALOG_ENABLE(); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + LVD_InitTypeDef LVD_InitStruct = {0}; + //LED初始化 + LED_Init(); + //配置测试IO口 + LVD_PortInit(); + LVD_InitStruct.LVD_Action = LVD_Action_Irq; //配置中断功能 + LVD_InitStruct.LVD_Source = LVD_Source_PB11; //配置LVD输入口 + LVD_InitStruct.LVD_Threshold = LVD_Threshold_2p0V; //配置LVD基准电压 + LVD_InitStruct.LVD_FilterEn = LVD_Filter_Enable; + LVD_InitStruct.LVD_FilterClk = LVD_FilterClk_RC150K; + LVD_InitStruct.LVD_FilterTime = LVD_FilterTime_4095Clk; + LVD_Init(&LVD_InitStruct); + LVD_TrigConfig(LVD_TRIG_FALL, ENABLE); + LVD_EnableIrq(LVD_INT_PRIORITY); + LVD_ClearIrq(); + FirmwareDelay(4800); //delay100us(1); + LVD_Enable(); //LVD使能 + while (1) + { + if (gFlagIrq) + { + PB09_TOG(); + gFlagIrq = FALSE; + } + } +} + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOB_Msk); + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + //LEDs are off. + PB08_SETLOW(); + PB09_SETLOW(); +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/readme.txt new file mode 100644 index 0000000..b0aa342 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_falling_irq/readme.txt @@ -0,0 +1,27 @@ +示例目的： + 演示LVD模块的下降沿触发中断功能。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. LVD的滤波时钟源为RC150K + 5. PB08/09设置为PUSH-PULL输出 + +演示说明： + LVD输入通道为PB11，输出端口为PA08，门限电压为2V。 + 外接可调直流电源，当LVD输入通道电压低于门限电压时刻，PB09输出电平翻转一次。 + LVD输入通道电压保持低于或者高于门限电压，PB09输出电平不变。 + +使用说明： ++ EWARM + 1. 打开lvd_detect_falling_irq.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开lvd_detect_falling_irq.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/EWARM/lvd_detect_fallingrising_irq.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/EWARM/lvd_detect_fallingrising_irq.ewd new file mode 100644 index 0000000..d09623c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/EWARM/lvd_detect_fallingrising_irq.ewd @@ -0,0 +1,3269 @@ + + + + 2 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a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/EWARM/lvd_detect_fallingrising_irq.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/EWARM/lvd_detect_fallingrising_irq.eww new file mode 100644 index 0000000..32dfb24 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/EWARM/lvd_detect_fallingrising_irq.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\lvd_detect_fallingrising_irq.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/MDK/lvd_detect_fallingrising_irq.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/MDK/lvd_detect_fallingrising_irq.uvoptx new file mode 100644 index 0000000..1d91336 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/MDK/lvd_detect_fallingrising_irq.uvoptx @@ -0,0 +1,333 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + lvd_detect_fallingrising_irq + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U4294967295 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_lvd.c + cw32f030_lvd.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/MDK/lvd_detect_fallingrising_irq.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/MDK/lvd_detect_fallingrising_irq.uvprojx new file mode 100644 index 0000000..45c7bfe --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/MDK/lvd_detect_fallingrising_irq.uvprojx @@ -0,0 +1,461 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + lvd_detect_fallingrising_irq + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + lvd_detect_fallingrising_irq + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_lvd.c + 1 + ..\..\..\..\Libraries\src\cw32f030_lvd.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/USER/inc/main.h new file mode 100644 index 0000000..c177984 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void LVD_PortInit(void); +void LED_Init(void); +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..090d4ec --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/USER/src/interrupts_cw32f030.c @@ -0,0 +1,413 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_lvd.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +extern volatile boolean_t gFlagIrq; +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + LVD_ClearIrq(); + gFlagIrq = TRUE; + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/USER/src/main.c new file mode 100644 index 0000000..ab4db70 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/USER/src/main.c @@ -0,0 +1,161 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-07-14 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_systick.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_lvd.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +volatile boolean_t gFlagIrq = FALSE; + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief LVD I/O初始化 + * + */ +void LVD_PortInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk | SYSCTRL_AHBEN_GPIOB_Msk); + //打开LVD时钟:PCLK. + //... + //set PA08 as output + GPIO_InitStructure.Pins = GPIO_PIN_8; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + //set PA08 as LVD output + PA08_AFx_LVDOUT(); + //set PB11 as LVD source + PB11_ANALOG_ENABLE(); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + LVD_InitTypeDef LVD_InitStruct = {0}; + //LED初始化 + LED_Init(); + //配置测试IO口 + LVD_PortInit(); + LVD_InitStruct.LVD_Action = LVD_Action_Irq; //配置中断功能 + LVD_InitStruct.LVD_Source = LVD_Source_PB11; //配置LVD输入口 + LVD_InitStruct.LVD_Threshold = LVD_Threshold_2p0V; //配置LVD基准电压 + LVD_InitStruct.LVD_FilterEn = LVD_Filter_Enable; + LVD_InitStruct.LVD_FilterClk = LVD_FilterClk_RC150K; + LVD_InitStruct.LVD_FilterTime = LVD_FilterTime_4095Clk; + LVD_Init(&LVD_InitStruct); + LVD_TrigConfig(LVD_TRIG_FALL | LVD_TRIG_RISE, ENABLE); + LVD_EnableIrq(LVD_INT_PRIORITY); + LVD_ClearIrq(); + FirmwareDelay(4800); //delay100us(1); + LVD_Enable(); //LVD使能 + while (1) + { + if (gFlagIrq) + { + PB09_TOG(); + gFlagIrq = FALSE; + } + } +} + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOB_Msk); + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + //LEDs are off. + PB08_SETLOW(); + PB09_SETLOW(); +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/readme.txt new file mode 100644 index 0000000..21299f0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_fallingrising_irq/readme.txt @@ -0,0 +1,27 @@ +示例目的： + 演示LVD模块的上升沿、下降沿触发中断功能。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. LVD的滤波时钟源为RC150K + 5. PB08/09设置为PUSH-PULL输出 + +演示说明： + LVD输入通道为PB11，输出端口为PA08，门限电压为2V。 + 外接可调直流电源，当LVD输入通道电压低于或者高于门限电压时刻，PB09输出电平翻转一次。 + LVD输入通道电压保持低于或者高于门限电压，PB09输出电平不变。 + +使用说明： ++ EWARM + 1. 打开lvd_detect_fallingrising_irq.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开lvd_detect_fallingrising_irq.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/EWARM/lvd_detect_level_irq.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/EWARM/lvd_detect_level_irq.ewd new file mode 100644 index 0000000..d09623c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/EWARM/lvd_detect_level_irq.ewd @@ -0,0 +1,3269 @@ + + + + 2 + + Release + + ARM + + 0 + + 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b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/EWARM/lvd_detect_level_irq.eww new file mode 100644 index 0000000..66c6696 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/EWARM/lvd_detect_level_irq.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\lvd_detect_level_irq.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/MDK/lvd_detect_level_irq.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/MDK/lvd_detect_level_irq.uvoptx new file mode 100644 index 0000000..ff1c8f1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/MDK/lvd_detect_level_irq.uvoptx @@ -0,0 +1,345 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + lvd_detect_level_irq + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U4294967295 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_lvd.c + cw32f030_lvd.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_systick.c + cw32f030_systick.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/MDK/lvd_detect_level_irq.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/MDK/lvd_detect_level_irq.uvprojx new file mode 100644 index 0000000..3801b5a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/MDK/lvd_detect_level_irq.uvprojx @@ -0,0 +1,466 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + lvd_detect_level_irq + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + lvd_detect_level_irq + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_lvd.c + 1 + ..\..\..\..\Libraries\src\cw32f030_lvd.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_systick.c + 1 + ..\..\..\..\Libraries\src\cw32f030_systick.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/USER/inc/main.h new file mode 100644 index 0000000..c177984 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void LVD_PortInit(void); +void LED_Init(void); +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..cf19178 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/USER/src/interrupts_cw32f030.c @@ -0,0 +1,414 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_lvd.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +extern volatile boolean_t gFlagIrq; +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + LVD_ClearIrq(); + gFlagIrq = TRUE; + LVD_DisableNvic(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/USER/src/main.c new file mode 100644 index 0000000..cdd43f6 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/USER/src/main.c @@ -0,0 +1,173 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-07-27 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_systick.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_lvd.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +volatile boolean_t gFlagIrq = FALSE; + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief LVD I/O初始化 + * + */ +void LVD_PortInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk | SYSCTRL_AHBEN_GPIOB_Msk); + //打开LVD时钟:PCLK. + //... + //set PA08 as output + GPIO_InitStructure.Pins = GPIO_PIN_8; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + //set PA08 as LVD output + PA08_AFx_LVDOUT(); + //set PB11 as LVD source + PB11_ANALOG_ENABLE(); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + LVD_InitTypeDef LVD_InitStruct = {0}; + RCC_HSI_Enable(RCC_HSIOSC_DIV2); //配置系统时钟为HSI 24M + InitTick(24000000ul); //初始化SysTick + //LED初始化 + LED_Init(); + //配置测试IO口 + LVD_PortInit(); + LVD_InitStruct.LVD_Action = LVD_Action_Irq; //配置中断功能 + LVD_InitStruct.LVD_Source = LVD_Source_PB11; //配置LVD输入口 + LVD_InitStruct.LVD_Threshold = LVD_Threshold_2p0V; //配置LVD基准电压 + LVD_InitStruct.LVD_FilterEn = LVD_Filter_Enable; + LVD_InitStruct.LVD_FilterClk = LVD_FilterClk_RC150K; + LVD_InitStruct.LVD_FilterTime = LVD_FilterTime_4095Clk; + LVD_Init(&LVD_InitStruct); + LVD_TrigConfig(LVD_TRIG_LEVEL, ENABLE); + LVD_EnableIrq(LVD_INT_PRIORITY); + LVD_ClearIrq(); + FirmwareDelay(4800); //delay100us(1); + LVD_Enable(); //LVD使能 + while (1) + { + if (gFlagIrq) + { + PB09_TOG(); + gFlagIrq = FALSE; + SysTickDelay(1000); //1s. + LVD_EnableNvic(LVD_INT_PRIORITY); //LVD中断使能 + } + } +} + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOB_Msk); + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + //LEDs are off. + PB08_SETLOW(); + PB09_SETLOW(); +} + +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn */ + uwTick += uwTickFreq; + /* USER CODE END SysTick_IRQn */ +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/readme.txt new file mode 100644 index 0000000..a3c2873 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/LVD/lvd_detect_level_irq/readme.txt @@ -0,0 +1,28 @@ +示例目的： + 演示LVD模块的电平触发中断功能。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟2分频，24MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=24MHz + 4. LVD的滤波时钟源为RC150K + 5. PB08/09设置为PUSH-PULL输出 + +演示说明： + LVD输入通道为PB11，输出端口为PA08，门限电压为2V。 + 外接可调直流电源，当LVD输入通道电压低于门限电压时，PB09输出电平翻转。 + 延时1s之后，重新监测LVD输入通道电压。 + 如果仍然低于门限电压时，PB09输出电平继续翻转；如果高于门限电压时，PB09输出电平不变。 + +使用说明： ++ EWARM + 1. 打开lvd_detect_falling_irq.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开lvd_detect_falling_irq.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/EWARM/PWR_CurrentConsumption.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/EWARM/PWR_CurrentConsumption.ewd new file mode 100644 index 0000000..9d4bb91 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/EWARM/PWR_CurrentConsumption.ewd @@ -0,0 +1,3269 @@ + + + + 2 + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_adc.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/EWARM/PWR_CurrentConsumption.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/EWARM/PWR_CurrentConsumption.eww new file mode 100644 index 0000000..5716d78 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/EWARM/PWR_CurrentConsumption.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\PWR_CurrentConsumption.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/MDK/PWR_CurrentConsumption.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/MDK/PWR_CurrentConsumption.uvoptx new file mode 100644 index 0000000..31e4067 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/MDK/PWR_CurrentConsumption.uvoptx @@ -0,0 +1,393 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + PWR_CurrentConsumption + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U4294967295 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\USER\src\cw32f030_pwr_modes.c + cw32f030_pwr_modes.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_systick.c + cw32f030_systick.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_pwr.c + cw32f030_pwr.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_vc.c + cw32f030_vc.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_adc.c + cw32f030_adc.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + 4 + 13 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/MDK/PWR_CurrentConsumption.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/MDK/PWR_CurrentConsumption.uvprojx new file mode 100644 index 0000000..1559789 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/MDK/PWR_CurrentConsumption.uvprojx @@ -0,0 +1,486 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + PWR_CurrentConsumption + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + PWR_CurrentConsumption + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + cw32f030_pwr_modes.c + 1 + ..\USER\src\cw32f030_pwr_modes.c + + + + + Driver + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_systick.c + 1 + ..\..\..\..\Libraries\src\cw32f030_systick.c + + + cw32f030_pwr.c + 1 + ..\..\..\..\Libraries\src\cw32f030_pwr.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_vc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_vc.c + + + cw32f030_adc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_adc.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/inc/cw32f030_pwr_modes.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/inc/cw32f030_pwr_modes.h new file mode 100644 index 0000000..e4f2843 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/inc/cw32f030_pwr_modes.h @@ -0,0 +1,35 @@ +/* + * cw32f030_pwr_modes.h + * + * Created on: 2021Äê6ÔÂ04ÈÕ + * Author: Socrates + */ + +#ifndef _CW32F030_PWR_MODES_H +#define _CW32F030_PWR_MODES_H + +/* Includes ------------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#if !defined (SLEEP_MODE) && !defined (DEEPSLEEP_MODE) + + /* Uncomment the corresponding line to select the CW32F030 Low Power mode + you want to mesure */ + //#define SLEEP_MODE + #define DEEPSLEEP_MODE +#endif + +//#define SLEEP_LSE_EN + +#if !defined (SLEEP_MODE) && !defined (DEEPSLEEP_MODE) + #error "Please select first the target CW32F030 Low Power mode to be measured (in cw32f030_pwr_modes.h file)" +#endif + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void SleepModeTest(void); +void DeepSleepModeTest(void); + +void HclkOutTest(void); +#endif /* _CW32F030_PWR_MODES_H */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/inc/main.h new file mode 100644 index 0000000..91c9f9a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void BSP_PB_Init(void); +void LED_Init(void); +void Error_Handler(void); +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/src/cw32f030_pwr_modes.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/src/cw32f030_pwr_modes.c new file mode 100644 index 0000000..9727192 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/src/cw32f030_pwr_modes.c @@ -0,0 +1,282 @@ +/* + * cw32f030_pwr_modes.c + * + * Created on: 2021年12月20日 + * Author: Socrates + */ + +/** + ****************************************************************************** + * @file PWR/PWR_CurrentConsumption/cw32f030_pwr_modes.c + * @author WHXY + * @brief This file provides firmware functions to manage the following + * functionalities of the CW32F030 Low Power Modes: + * - Sleep Mode + * - DeepSleep mode with or without RTC + ******************************************************************************/ + + + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_pwr_modes.h" +#include "main.h" +#include "cw32f030_pwr.h" +#include "cw32f030_gpio.h" +#include "cw32f030_systick.h" +#include "cw32f030_rcc.h" +#include "cw32f030_flash.h" +#include "cw32f030_vc.h" +#include "cw32f030_adc.h" + +/** @addtogroup CW32F030_HAL_Examples + * @{ + */ + +/** @addtogroup PWR_CurrentConsumption + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* RTC handler declaration */ +//RTC_HandleTypeDef RTCHandle; + +/* Private function prototypes -----------------------------------------------*/ +static void SYSCLKConfig_DeepSleep(void); + +/* Private functions ---------------------------------------------------------*/ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +extern volatile uint8_t gKeyStatus; +/* USER CODE END EV */ + +/** + * @brief This function configures the system to enter Sleep mode for + * current consumption measurement purpose. + * Sleep Mode + * ========== + * - System Running at HSI (24 MHz) + * - Code running from Internal FLASH + * - All peripherals disabled. + * - Wakeup using EXTI Line (User push-button) + * @param None + * @return None + */ +void SleepModeTest(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + PWR_InitTypeDef PWR_InitStructure; + /* Configure all GPIO as analog to reduce current consumption on non used IOs */ + /* Enable GPIOs clock */ + /* Warning : Reconfiguring all GPIO will close the connexion with the debugger */ + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk | SYSCTRL_AHBEN_GPIOB_Msk | \ + SYSCTRL_AHBEN_GPIOC_Msk | SYSCTRL_AHBEN_GPIOF_Msk); + GPIO_InitStructure.Mode = GPIO_MODE_ANALOG; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_InitStructure.IT = GPIO_IT_NONE; + GPIO_InitStructure.Pins = GPIO_PIN_All; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + GPIO_Init(CW_GPIOC, &GPIO_InitStructure); + GPIO_Init(CW_GPIOF, &GPIO_InitStructure); + /* Disable GPIOs clock */ + REGBITS_CLR(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk | SYSCTRL_AHBEN_GPIOB_Msk | \ + SYSCTRL_AHBEN_GPIOC_Msk | SYSCTRL_AHBEN_GPIOF_Msk); + /* Configure User push-button as external interrupt generator */ + BSP_PB_Init(); + /*Suspend Tick increment to prevent wakeup by Systick interrupt. + Otherwise the Systick interrupt will wake up the device within 1ms (HAL time base)*/ + SuspendTick(); + /* Request to enter SLEEP mode */ + //HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); + PWR_InitStructure.PWR_Sevonpend = PWR_Sevonpend_Disable; + PWR_InitStructure.PWR_SleepDeep = PWR_SleepDeep_Disable; + PWR_InitStructure.PWR_SleepOnExit = PWR_SleepOnExit_Disable; + PWR_Config(&PWR_InitStructure); + PWR_GotoLpmMode(); + /* Resume Tick interrupt if disabled prior to sleep mode entry*/ + ResumeTick(); + /* Initialize led */ + LED_Init(); +} + +/** + * @brief This function configures the system to enter Deep-Sleep mode + * for current consumption measurement purpose. + * Deep-Sleep Mode + * ========== + * - No IWDG + * - Wakeup using EXTI Line (User push-button) + * @param None + * @return None + */ +void DeepSleepModeTest(void) +{ + uint8_t res = 0u; + GPIO_InitTypeDef GPIO_InitStructure; + PWR_InitTypeDef PWR_InitStructure; + /* Configure all GPIO as analog to reduce current consumption on non used IOs */ + /* Warning : Reconfiguring all GPIO will close the connexion with the debugger */ + /* Enable GPIOs clock */ + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk | SYSCTRL_AHBEN_GPIOB_Msk | \ + SYSCTRL_AHBEN_GPIOC_Msk | SYSCTRL_AHBEN_GPIOF_Msk); + GPIO_InitStructure.Mode = GPIO_MODE_ANALOG; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_InitStructure.IT = GPIO_IT_NONE; + GPIO_InitStructure.Pins = GPIO_PIN_All; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + GPIO_Init(CW_GPIOC, &GPIO_InitStructure); + GPIO_Init(CW_GPIOF, &GPIO_InitStructure); + //关闭GPIO时钟 + REGBITS_CLR(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk | SYSCTRL_AHBEN_GPIOB_Msk | \ + SYSCTRL_AHBEN_GPIOC_Msk | SYSCTRL_AHBEN_GPIOF_Msk); + /* Configure User Button */ + BSP_PB_Init(); + //如果使能了VC,则应等待VC_SR.READY置1后方可进入DeepSleep模式 + //打开VC时钟 + RCC_APBPeriphClk_Enable2(RCC_APB2_PERIPH_VC, ENABLE); + if (VC1_GetEnableStatus() == SET) + { + //等待VC1稳定 + while (!(VC1_GetFlagStatus(VC_FLAG_READY))) + { + ; + } + if (VC2_GetEnableStatus() == SET) + { + //等待VC2稳定 + while (!(VC2_GetFlagStatus(VC_FLAG_READY))) + { + ; + } + } + } + else if (VC2_GetEnableStatus() == SET) + { + //等待VC2稳定 + while (!(VC2_GetFlagStatus(VC_FLAG_READY))) + { + ; + } + } + else + { + //关闭VC时钟 + RCC_APBPeriphClk_Enable2(RCC_APB2_PERIPH_VC, DISABLE); + } + /* Configures system clock after wake-up from DeepSleep: enable HSI and PLL with HSI as source*/ + // 唤醒后自动使用内部高速时钟（HSI） + RCC_WAKEUPCLK_Config(RCC_SYSCTRL_WAKEUPCLKEN); + /* Enter Stop Mode */ + PWR_InitStructure.PWR_Sevonpend = PWR_Sevonpend_Disable; + PWR_InitStructure.PWR_SleepDeep = PWR_SleepDeep_Enable; + PWR_InitStructure.PWR_SleepOnExit = PWR_SleepOnExit_Disable; + PWR_Config(&PWR_InitStructure); + //打开FLASH时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_FLASH_Msk); + REGBITS_SET(CW_FLASH->CR1, FLASH_CR1_STANDBY_Msk); //打开FLASH低功耗使能控制 + //关闭FLASH时钟 + REGBITS_CLR(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_FLASH_Msk); + //进入深度休眠模式前应当将HCLK的时钟频率修改为不大于4MHz + RCC_HSI_Enable(RCC_HSIOSC_DIV12); //配置系统时钟为HSI 4M +#ifdef SLEEP_LSE_EN + /*Suspend Tick increment to prevent wakeup by Systick interrupt. + Otherwise the Systick interrupt will wake up the device within 1ms (HAL time base)*/ + //SuspendTick(); //Comment it if using HSI. + //Open LSE. + RCC_LSE_Enable(RCC_LSE_MODE_OSC, RCC_LSE_AMP_NORMAL, RCC_LSE_DRIVER_LARGER); //开启外部高速时钟LSE + //Switch clock to LSE from HSI + res = RCC_SysClk_Switch(RCC_SYSCLKSRC_LSE); //切换系统时钟到LSE + if (res == 0x00) //切换系统时钟成功 + { + RCC_HSI_Disable(); //切换时钟到LSE后关闭源时钟HSI + FirmwareDelay(1400); + } + else + { + Error_Handler(); + } +#endif + PWR_GotoLpmMode(); +#ifdef SLEEP_LSE_EN + /* Resume Tick interrupt if disabled prior to sleep mode entry*/ + //ResumeTick(); + RCC_LSE_Disable(); +#endif + /* Configures system clock after wake-up from DeepSleep: enable HSI and PLL with HSI as source*/ + SYSCLKConfig_DeepSleep(); + /* Initialize LED on the board */ + LED_Init(); + /* Inserted Delay */ + SysTickDelay(200); + /* Turn LED1 On */ + PB09_SETHIGH(); +} + + +/** + * @brief Configures system clock after wake-up from DeepSleep: enable HSE, PLL + * and select PLL as system clock source. + * @param None + * @return None + */ +static void SYSCLKConfig_DeepSleep(void) +{ + uint8_t res = 0u; + //uint32_t pFLatency = 0; + /* Get the Oscillators configuration according to the internal RCC registers */ + RCC_HSI_Enable(RCC_HSIOSC_DIV2); //配置系统时钟为HSI 24M + /* Activate PLL with HSI as source,72MHz */ + RCC_PLL_Enable(RCC_PLLSOURCE_HSI, 24000000ul, RCC_PLL_MUL_3); + //打开FLASH时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_FLASH_Msk); + FLASH_SetLatency(FLASH_Latency_3); //系统时钟大于24M需要配置FlashWait + //关闭FLASH时钟 + REGBITS_CLR(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_FLASH_Msk); + res = RCC_SysClk_Switch(RCC_SYSCLKSRC_PLL); //切换系统时钟到PLL + if (res == 0x00) //切换系统时钟成功 + { + FirmwareDelay(100000); + } + else + { + Error_Handler(); + } + /* Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers */ + RCC_HCLKPRS_Config(RCC_HCLK_DIV1); + RCC_PCLKPRS_Config(RCC_PCLK_DIV1); + RCC_SYSCLKSRC_Config(RCC_SYSCLKSRC_PLL); +} + +/** + * @brief 系统时钟测试 + * + */ +void HclkOutTest(void) +{ + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk); + //配置PA3,PA4为输出 + REGBITS_CLR(CW_GPIOA->ANALOG, bv3 | bv4); + REGBITS_CLR(CW_GPIOA->DIR, bv3 | bv4); + PA03_AFx_PCLKOUT(); //配置PA03输出PCLK + PA04_AFx_HCLKOUT(); //配置PA04输出HCLK +} +/** + * @} + */ + +/** + * @} + */ + +/*****************************END OF FILE****/ + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..3e00b7d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/src/interrupts_cw32f030.c @@ -0,0 +1,416 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +extern volatile uint8_t gKeyStatus; +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + if (REGBITS_GET(CW_GPIOA->ISR, GPIOx_ISR_PIN1_Msk) > 0) + { + gKeyStatus = 1; + //清除CW_GPIO中断标志 + GPIOA_INTFLAG_CLR(GPIOx_ICR_PIN1_Msk); + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/src/main.c new file mode 100644 index 0000000..19fdbcb --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/USER/src/main.c @@ -0,0 +1,206 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-09-22 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_systick.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_pwr.h" + +#include "cw32f030_flash.h" +// +#include "cw32f030_pwr_modes.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +volatile uint8_t gKeyStatus; /* set to 1 after User Button interrupt */ +volatile uint32_t gFlagWakeUpIrq = 0; /* set to 1 after RTC alarm interrupt */ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + RCC_HSI_Enable(RCC_HSIOSC_DIV2); //配置系统时钟为HSI 24M + //Enable Systick Clk + InitTick(24000000ul); //初始化SysTick + //Test only. + HclkOutTest(); + //LED初始化 + LED_Init(); + while (1) + { + /* Configure User push-button as external interrupt generator */ + BSP_PB_Init(); + gKeyStatus = 0; + /* Wait until User push-button is pressed to enter the Low Power mode. + In the meantime, LED is blinks */ + do + { + /* Toggle LED */ + PB09_TOG(); + SysTickDelay(1000); //1s. + } + while (gKeyStatus == 0); + /* Make sure LED is turned off to + reduce low power mode consumption */ + PB09_SETLOW(); +#if defined (SLEEP_MODE) + /* Sleep Mode Entry + - System Running at HSI (24 MHz) + - Code running from Internal FLASH + - All peripherals disabled. + - Wakeup using EXTI Line (User push-button PA.01) + */ + SleepModeTest(); +#elif defined (DEEPSLEEP_MODE) + /* DeepSleep Mode Entry + - No IWDG + - Wakeup using EXTI Line (User push-button PA.01) + */ + DeepSleepModeTest(); +#else +#error "Please select low power mode first!" +#endif /* SLEEP_MODE */ + //Test only. + HclkOutTest(); + } +} + +/** + * @brief Configure User push-button as external interrupt generator + * + */ +void BSP_PB_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk); + GPIO_InitStructure.Pins = GPIO_PIN_1; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + //Configure Button pin as input with External interrupt + GPIO_InitStructure.IT = GPIO_IT_FALLING; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + //Enable and set Button EXTI Interrupt to the lowest priority + NVIC_SetPriority(GPIOA_IRQn, 0x03); + //清除中断标志并使能NVIC + GPIOA_INTFLAG_CLR(GPIOx_ICR_PIN1_Msk); + NVIC_EnableIRQ(GPIOA_IRQn); +} + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOB_Msk); + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + //LEDs are off. + PB08_SETLOW(); + PB09_SETLOW(); +} + +/** + * @brief This function is executed in case of error occurrence. + * + */ +void Error_Handler(void) +{ + while (1) + { + /* Turn LED1,LED2 on */ + PB08_SETHIGH(); + PB09_SETHIGH(); + } +} + +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn */ + uwTick += uwTickFreq; + /* USER CODE END SysTick_IRQn */ +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/readme.txt new file mode 100644 index 0000000..c619ec4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/PWR/PWR_CurrentConsumption/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 演示MCU通过按键进入/退出休眠和深度休眠模式。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI，LSE + 3. 系统时钟源为HSI时钟2分频，24MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=24MHz + 4. PA01设置为按键(KEY1)中断输入 + 5. PB08/09设置为PUSH-PULL输出 + +演示说明： + 上电后，MCU处于正常工作模式，PB09(LED1)输出电平延时1s不断翻转。 + 第一次按下KEY1，MCU进入休眠或者深度休眠模式，LED1熄灭。 + 再一次按下KEY1，MCU退出休眠或者深度休眠模式，LED1点亮且不断翻转，MCU返回正常工作模式。 + 注意：修改cw32f030_pwr_modes.h中的宏定义，即可选择低功耗模式。 + + +使用说明： ++ EWARM + 1. 打开PWR_CurrentConsumption.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开PWR_CurrentConsumption.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/EWARM/Project.ewd new file mode 100644 index 0000000..e6bf369 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/EWARM/Project.ewp new file mode 100644 index 0000000..17c37c9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/EWARM/Project.ewp @@ -0,0 +1,2160 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + Utilities + + $PROJ_DIR$\..\..\..\..\Utilities\log.c + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/MDK/Project.uvoptx new file mode 100644 index 0000000..eb1d543 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/MDK/Project.uvoptx @@ -0,0 +1,385 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + DLGUARM + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 111 + 1 +
8438
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\Project\../USER/src/main.c\111 + + + + + 0 + 1 + PosWidth,0x0A + + + 1 + 1 + Period,0x10 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\UART2 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rtc.c + cw32f030_rtc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Utilities + 1 + 0 + 0 + 0 + + 4 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Utilities\log.c + log.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/MDK/Project.uvprojx new file mode 100644 index 0000000..3f4a254 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/MDK/Project.uvprojx @@ -0,0 +1,466 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.5 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\Utilities + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_rtc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rtc.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Utilities + + + log.c + 1 + ..\..\..\..\Utilities\log.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/USER/inc/main.h new file mode 100644 index 0000000..23f7678 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/USER/inc/main.h @@ -0,0 +1,68 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "cw32f030_rcc.h" +#include "cw32f030_rtc.h" +#include "cw32f030_spi.h" +#include "cw32f030_uart.h" +#include "interrupts_cw32f030.h" +#include "log.h" +#include "system_cw32f030.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..053d972 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +extern void RTC_IRQHandlerCallBack(void); +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + RTC_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/USER/src/main.c new file mode 100644 index 0000000..ecc51a8 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/USER/src/main.c @@ -0,0 +1,213 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void delay(uint16_t ms); +void ShowTime(void); +void RTC_IRQHandlerCallBack(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle GPIOA.00 + ** + ******************************************************************************/ + +/** + * @brief RTC时钟测试，初始化日历，使用间隔中断0.5秒通过Log输出日期时间 + * @return int32_t + */ +int32_t main(void) +{ + RTC_InitTypeDef RTC_InitStruct; + RTC_AlarmTypeDef RTC_AlarmStruct; + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + LogInit(); + printf("RTC Init...\r\n"); + printf(" (RTC CR0:%04x,CR1:%04x,CR2:%04x,RESET FLAG:0x%08x)\r\n", CW_RTC->CR0, CW_RTC->CR1, CW_RTC->CR2, CW_SYSCTRL->RESETFLAG); + //RCC_HSE_Enable(RCC_HSE_MODE_OSC, RCC_HSE_FREQ_GT24M,RCC_HSE_DRIVER_NORMAL, RCC_HSE_FLT_CLOSE); //选择HSE为RTC时钟 + RCC_LSE_Enable(RCC_LSE_MODE_OSC, RCC_LSE_AMP_NORMAL, RCC_LSE_DRIVER_NORMAL); // 选择LSE为RTC时钟 + //RCC_LSI_Enable(); // 选择LSI为RTC时钟 + RTC_InitStruct.DateStruct.Day = 0x21; //设置日期，DAY、MONTH、YEAR必须为BCD方式，星期为0~6，代表星期日，星期一至星期六 + RTC_InitStruct.DateStruct.Month = RTC_Month_June; + RTC_InitStruct.DateStruct.Week = RTC_Weekday_Monday; + RTC_InitStruct.DateStruct.Year = 0x21; + printf("-------Set Date as 20%x/%x/%x\r\n", RTC_InitStruct.DateStruct.Year, RTC_InitStruct.DateStruct.Month, RTC_InitStruct.DateStruct.Day); + RTC_InitStruct.TimeStruct.Hour = 0x2; //设置时间，HOUR、MINIUTE、SECOND必须为BCD方式，用户须保证HOUR、AMPM、H24之间的关联正确性 + RTC_InitStruct.TimeStruct.Minute = 0x58; + RTC_InitStruct.TimeStruct.Second = 0x59; + RTC_InitStruct.TimeStruct.AMPM = 1; + RTC_InitStruct.TimeStruct.H24 = 0; + printf("-------Set Time as %02x:%02x:%02x\r\n", RTC_InitStruct.TimeStruct.Hour, RTC_InitStruct.TimeStruct.Minute, RTC_InitStruct.TimeStruct.Second); + RTC_InitStruct.RTC_ClockSource = RTC_RTCCLK_FROM_LSE; + RTC_Init(&RTC_InitStruct); // 用户需选定需要使用的时钟源 + printf("=====Set interval period as 0.5s...\r\n"); + RTC_SetInterval(RTC_INTERVAL_EVERY_0_5S); + /* 设置闹钟为工作日上午的6：45 */ + printf("=====Set AlarmA at 6:45 on workday...\r\n"); + RTC_AlarmStruct.RTC_AlarmMask = RTC_AlarmMask_WeekMON | RTC_AlarmMask_WeekTUE | + RTC_AlarmMask_WeekWED | RTC_AlarmMask_WeekTHU | + RTC_AlarmMask_WeekFRI; + RTC_AlarmStruct.RTC_AlarmTime.Hour = 6; + RTC_AlarmStruct.RTC_AlarmTime.Minute = 0x45; + RTC_AlarmStruct.RTC_AlarmTime.Second = 0; + RTC_SetAlarm(RTC_Alarm_A, &RTC_AlarmStruct); + RTC_AlarmCmd(RTC_Alarm_A, ENABLE); + printf("=====Enable ALRAMA and INTERVAL IT...\r\n"); + RTC_ITConfig(RTC_IT_ALARMA | RTC_IT_INTERVAL, ENABLE); + while (1) + { + if (CW_RTC->KEY) + { + __breakpoint(0); + } + } +} + + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + RCC_LSI_Enable(); + RCC_LSE_Enable(RCC_LSE_MODE_OSC, RCC_LSE_AMP_NORMAL, RCC_LSE_DRIVER_NORMAL); + RCC_APBPeriphClk_Enable1(RCC_APB1_PERIPH_RTC, ENABLE); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(RTC_IRQn); + __enable_irq(); +} + +void delay(uint16_t ms) +{ + uint32_t i; + for (; ms > 0; ms--) + { + i = 796; + while (i--); + } +} + +void ShowTime(void) +{ + RTC_TimeTypeDef RTC_TimeStruct; + RTC_DateTypeDef RTC_DateStruct; + static uint8_t *WeekdayStr[7] = {"SUN", "MON", "TUE", "WED", "THU", "FRI", "SAT"}; + static uint8_t *H12AMPMStr[2][2] = {{"AM", "PM"}, {"", ""}}; + RTC_GetDate(&RTC_DateStruct); + RTC_GetTime(&RTC_TimeStruct); + printf(".Date is 20%02x/%02x/%02x(%s).Time is %02x%s:%02x:%02x\r\n", RTC_DateStruct.Year, RTC_DateStruct.Month, RTC_DateStruct.Day, WeekdayStr[RTC_DateStruct.Week], RTC_TimeStruct.Hour, H12AMPMStr[RTC_TimeStruct.H24][RTC_TimeStruct.AMPM], RTC_TimeStruct.Minute, RTC_TimeStruct.Second); +} + +void RTC_IRQHandlerCallBack(void) +{ + if (RTC_GetITState(RTC_IT_ALARMA)) + { + RTC_ClearITPendingBit(RTC_IT_ALARMA); + printf("*********Alarm!!!!\r\n"); + } + if (RTC_GetITState(RTC_IT_INTERVAL)) + { + RTC_ClearITPendingBit(RTC_IT_INTERVAL); + ShowTime(); + } +} + + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/readme.txt new file mode 100644 index 0000000..8ebfa24 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Calendar/readme.txt @@ -0,0 +1,26 @@ +示例目的： + RTC时钟测试，初始化日历，使用间隔中断0.5秒通过Log输出日期时间 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI， LSE使能 + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. RTC使用LSE作为时钟输入 + 5. 串口UART1作为调试串口,打印调试信息(PA8->TXD),波特率115200 + + +演示说明： + 每0.5秒通过Log输出日期时间. + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/EWARM/Project.ewd new file mode 100644 index 0000000..e6bf369 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 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$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/EWARM/Project.ewp new file mode 100644 index 0000000..17c37c9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/EWARM/Project.ewp @@ -0,0 +1,2160 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/MDK/Project.uvoptx new file mode 100644 index 0000000..7c0620e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/MDK/Project.uvoptx @@ -0,0 +1,415 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + -UAny -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L031.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32L031C8T6$Flash\FlashCW32L031.FLM) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + + + + 0 + 1 + PosWidth,0x0A + + + 1 + 1 + Period,0x10 + + + 2 + 1 + ((ADC_TypeDef*) 0x40012400UL)->RESULT0,0x0A + + + + + 1 + 0 + 0 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\ADC + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 1 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rtc.c + cw32f030_rtc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_adc.c + cw32f030_adc.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_pwr.c + cw32f030_pwr.c + 0 + 0 + + + + + Utilities + 1 + 0 + 0 + 0 + + 4 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\Utilities\log.c + log.c + 0 + 0 + + + + + doc + 0 + 0 + 0 + 0 + + 5 + 12 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/MDK/Project.uvprojx new file mode 100644 index 0000000..5fc6e12 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/MDK/Project.uvprojx @@ -0,0 +1,486 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L031 -FS00 -FL010000 -FP0($$Device:CW32L031C8T6$Flash\FlashCW32L031.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\Utilities + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_rtc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rtc.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_adc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_adc.c + + + cw32f030_pwr.c + 1 + ..\..\..\..\Libraries\src\cw32f030_pwr.c + + + + + Utilities + + + log.c + 1 + ..\..\..\..\Utilities\log.c + + + + + doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/USER/inc/main.h new file mode 100644 index 0000000..bb992dd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/USER/inc/main.h @@ -0,0 +1,68 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "cw32f030_rcc.h" +#include "cw32f030_rtc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_uart.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_adc.h" +#include "system_cw32f030.h" +#include "cw32f030_pwr.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..ec9acb8 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/USER/src/interrupts_cw32f030.c @@ -0,0 +1,411 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +extern void RTC_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + RTC_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + GPIOA_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + GPIOB_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/USER/src/main.c new file mode 100644 index 0000000..462051d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/USER/src/main.c @@ -0,0 +1,290 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void RTC_Configuration(void); +void ADC_Configuration(void); +void Sleep_Configuration(void); +void delay(uint16_t ms); +void RTC_IRQHandlerCallBack(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint32_t flag = 0; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle GPIOA.00 + ** + ******************************************************************************/ + +/** + * @brief RTC时钟测试，初始化日历，使用间隔中断0.5秒通过Log输出日期时间 + * @return int32_t + */ +int32_t main(void) +{ + uint32_t cnt; + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + RTC_Configuration(); + ADC_Configuration(); + Sleep_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); + while (1) + { + if (flag & bv0) + { + flag &= ~bv0; + ADC_Enable(); // 低功耗模式下开启了ADC的自动关闭功能，再次使用ADC时，需要置EN位 + ADC_SoftwareStartConvCmd(ENABLE); + while (!CW_ADC->ISR_f.EOC); + for (cnt = 0; cnt < 5; cnt++) + { + PB08_TOG(); + PB09_TOG(); + delay(100); + } + } + if (flag & bv1) + { + flag &= ~bv1; + PB09_SETHIGH(); + delay(500); + } + if (flag & bv2) + { + flag &= ~bv2; + PB08_SETHIGH(); + delay(500); + } + PB08_SETLOW(); + PB09_SETLOW(); + PWR_GotoLpmMode(); + } +} + + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + RCC_HSI_Enable(RCC_HSIOSC_DIV6); // 8MHz主频 + RCC_LSI_Enable(); // 内部低速时钟作为RTC时钟源，精度较差 + // 如需要RTC走时精度高，需要使用外部高精度晶体作为时钟源 + // RCC_LSE_Enable(RCC_LSE_MODE_OSC, RCC_LSE_AMP_NORMAL, RCC_LSE_DRIVER_NORMAL); + RCC_APBPeriphClk_Enable1(RCC_APB1_PERIPH_RTC, ENABLE); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + // PA4 PB4唤醒 + GPIO_InitTypeDef GPIO_InitStructure = {0}; + GPIO_InitStructure.IT = GPIO_IT_FALLING | GPIO_IT_RISING; // 双沿触发中断 + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; // 输入上拉 + GPIO_InitStructure.Pins = GPIO_PIN_4; + __RCC_GPIOA_CLK_ENABLE(); // 开GPIOA模块的时钟 + __RCC_GPIOB_CLK_ENABLE(); // 开GPIOB模块的时钟 + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + GPIO_ConfigFilter(CW_GPIOA, GPIO_PIN_4, GPIO_FLTCLK_LSI); // 休眠时，中断唤醒通过LSI时钟去抖动。 + GPIO_ConfigFilter(CW_GPIOB, GPIO_PIN_4, GPIO_FLTCLK_LSI); + CW_GPIOA->ICR = 0x0000; + CW_GPIOB->ICR = 0x0000; // 清中断标志 + GPIO_InitStructure.IT = GPIO_IT_NONE; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + PB08_SETLOW(); + PB09_SETHIGH(); +} + +void RTC_Configuration(void) +{ + RTC_InitTypeDef RTC_InitStruct = {0}; + RTC_AlarmTypeDef RTC_AlarmStruct = {0}; + __RCC_RTC_CLK_ENABLE(); // 开RTC模块的时钟 + RCC_LSI_Enable(); // 选择LSI为RTC时钟，在配置RTC时钟前，时钟源必须有效 + RTC_InitStruct.DateStruct.Day = 0x21; //设置日期，DAY、MONTH、YEAR必须为BCD方式，星期为0~6，代表星期日，星期一至星期六 + RTC_InitStruct.DateStruct.Month = RTC_Month_July; + RTC_InitStruct.DateStruct.Week = RTC_Weekday_Thursday; + RTC_InitStruct.DateStruct.Year = 0x22; // 2022-7-21 + RTC_InitStruct.TimeStruct.Hour = 0x2; //设置时间，HOUR、MINIUTE、SECOND必须为BCD方式，用户须保证HOUR、AMPM、H24之间的关联正确性 + RTC_InitStruct.TimeStruct.Minute = 0x58; + RTC_InitStruct.TimeStruct.Second = 0x55; + RTC_InitStruct.TimeStruct.AMPM = RTC_H12_PM; + RTC_InitStruct.TimeStruct.H24 = 0; // 12小时制 PM 2：58：55 + RTC_InitStruct.RTC_ClockSource = RTC_RTCCLK_FROM_LSI; + RTC_Init(&RTC_InitStruct); // 用户需选定需要使用的时钟源 + /* 设置闹钟在30秒闹一次 */ + RTC_AlarmStruct.RTC_AlarmMask = RTC_AlarmMask_All & (~RTC_AlarmMask_Seconds); // 和秒位匹配 + RTC_AlarmStruct.RTC_AlarmTime.Hour = 0x01; + RTC_AlarmStruct.RTC_AlarmTime.Minute = 0x01; + RTC_AlarmStruct.RTC_AlarmTime.Second = 0x30; + RTC_SetAlarm(RTC_Alarm_A, &RTC_AlarmStruct); + RTC_AlarmCmd(RTC_Alarm_A, ENABLE); + RTC_ITConfig(RTC_IT_ALARMA, ENABLE); +} + +void ADC_Configuration(void) +{ + ADC_InitTypeDef ADC_InitStructure = {0}; + ADC_WdtTypeDef ADC_WdtStructure = {0}; + ADC_SingleChTypeDef ADC_SingleChStructure = {0}; + __RCC_ADC_CLK_ENABLE(); // ADC模块时钟打开 + //ADC默认值初始化 + ADC_StructInit(&ADC_InitStructure); + //ADC工作时钟配置 + ADC_InitStructure.ADC_ClkDiv = ADC_Clk_Div2; // ADCCLK= 4MHz + ADC_InitStructure.ADC_VrefSel = ADC_Vref_VDDA; + //ADC模拟看门狗通道初始化 + ADC_WdtInit(&ADC_WdtStructure); + //配置单通道转换模式 + ADC_SingleChStructure.ADC_DiscardEn = ADC_DiscardNull; + ADC_SingleChStructure.ADC_Chmux = ADC_VddaDiV3Input; //选择ADC转换通道 VDDA/3 + ADC_SingleChStructure.ADC_InitStruct = ADC_InitStructure; + ADC_SingleChStructure.ADC_WdtStruct = ADC_WdtStructure; + ADC_SingleChOneModeCfg(&ADC_SingleChStructure); + ADC_AutoStop(ADC_AutoStopEnable); // 低功耗，使能ADC的自动关闭模式 + ADC_ClearITPendingAll(); + //ADC使能 + ADC_Enable(); + ADC_SoftwareStartConvCmd(ENABLE); +} + +void Sleep_Configuration(void) +{ + PWR_InitTypeDef PWR_InitStructure; + PWR_InitStructure.PWR_Sevonpend = PWR_Sevonpend_Disable; + PWR_InitStructure.PWR_SleepDeep = PWR_SleepDeep_Enable; + PWR_InitStructure.PWR_SleepOnExit = PWR_SleepOnExit_Disable; + PWR_Config(&PWR_InitStructure); +} + + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(RTC_IRQn); + NVIC_EnableIRQ(GPIOA_IRQn); + NVIC_EnableIRQ(GPIOB_IRQn); + __enable_irq(); +} + +void delay(uint16_t ms) +{ + uint32_t i; + for (; ms > 0; ms--) + { + i = 796; + while (i--); + } +} + + + +void RTC_IRQHandlerCallBack(void) +{ + if (RTC_GetITState(RTC_IT_ALARMA)) + { + RTC_ClearITPendingBit(RTC_IT_ALARMA); + flag |= 1; + } +} + +void GPIOA_IRQHandlerCallBack() +{ + CW_GPIOA->ICR = 0x0000; + flag |= 1 << 1; +} +void GPIOB_IRQHandlerCallBack() +{ + CW_GPIOB->ICR = 0x0000; + flag |= 1 << 2; +} + + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/readme.txt new file mode 100644 index 0000000..8ebfa24 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/RTC/RTC_Wakeup/readme.txt @@ -0,0 +1,26 @@ +示例目的： + RTC时钟测试，初始化日历，使用间隔中断0.5秒通过Log输出日期时间 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI， LSE使能 + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. RTC使用LSE作为时钟输入 + 5. 串口UART1作为调试串口,打印调试信息(PA8->TXD),波特率115200 + + +演示说明： + 每0.5秒通过Log输出日期时间. + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/EWARM/Project.ewd new file mode 100644 index 0000000..800c43b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + 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$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/EWARM/Project.ewp new file mode 100644 index 0000000..f07e3c6 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/EWARM/Project.ewp @@ -0,0 +1,2160 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_dma.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/MDK/Project.uvoptx new file mode 100644 index 0000000..69927a8 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/MDK/Project.uvoptx @@ -0,0 +1,387 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + TxBuffer1 + + + 1 + 1 + RxBuffer2 + + + 2 + 1 + TransferStatus1 + + + 3 + 1 + ARRAY_SZ(TxBuffer1) + + + 4 + 1 + TxBuffer2 + + + 5 + 1 + RxBuffer1 + + + 6 + 1 + TransferStatus2 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_spi.c + cw32f030_spi.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_dma.c + cw32f030_dma.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/MDK/Project.uvprojx new file mode 100644 index 0000000..dc87275 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/MDK/Project.uvprojx @@ -0,0 +1,483 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_spi.c + 1 + ..\..\..\..\Libraries\src\cw32f030_spi.c + + + cw32f030_dma.c + 1 + ..\..\..\..\Libraries\src\cw32f030_dma.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/USER/inc/main.h new file mode 100644 index 0000000..b2192bc --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/USER/inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_spi.h" +#include "cw32f030_dma.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/USER/src/main.c new file mode 100644 index 0000000..0f95f0b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/USER/src/main.c @@ -0,0 +1,332 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//SPIy MASTER +#define SPIy CW_SPI1 +#define SPIy_CLK RCC_APB2_PERIPH_SPI1 +#define SPIy_APBClkENx RCC_APBPeriphClk_Enable2 + +//SPIy GPIO +#define SPIy_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define SPIy_GPIO CW_GPIOA +#define SPIy_SCK_PIN GPIO_PIN_10 +#define SPIy_MISO_PIN GPIO_PIN_11 +#define SPIy_MOSI_PIN GPIO_PIN_12 +#define SPIy_AF_SCK PA10_AFx_SPI1SCK() +#define SPIy_AF_MISO PA11_AFx_SPI1MISO() +#define SPIy_AF_MOSI PA12_AFx_SPI1MOSI() + +//SPIz SLAVE +#define SPIz CW_SPI2 +#define SPIz_CLK RCC_APB1_PERIPH_SPI2 +#define SPIz_APBClkENx RCC_APBPeriphClk_Enable1 + +//SPIz GPIO +#define SPIz_GPIO_CLK RCC_AHB_PERIPH_GPIOB +#define SPIz_GPIO CW_GPIOB +#define SPIz_SCK_PIN GPIO_PIN_13 +#define SPIz_MISO_PIN GPIO_PIN_14 +#define SPIz_MOSI_PIN GPIO_PIN_15 +#define SPIz_AF_SCK PB13_AFx_SPI2SCK() +#define SPIz_AF_MISO PB14_AFx_SPI2MISO() +#define SPIz_AF_MOSI PB15_AFx_SPI2MOSI() + +//DMA +#define SPIz_RX_DMACHANNEL CW_DMACHANNEL1 +#define SPIz_TX_DMACHANNEL CW_DMACHANNEL2 +#define SPIz_DMA_RxTrigSource DMA_HardTrig_SPI2_RXBufferNE +#define SPIz_DMA_TxTrigSource DMA_HardTrig_SPI2_TXBufferE +#define BufferSize ARRAY_SZ(TxBuffer1) +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void DMA_Configuration(void); +void SPI_Configuration(void); +TestStatus Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxBuffer1[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, + 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, + 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, + 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23 + }; +uint8_t TxBuffer2[] = {0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, + 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, + 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, + 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83 + }; +uint8_t RxBuffer1[BufferSize]; +uint8_t RxBuffer2[BufferSize]; +uint8_t TxCounter = 0, RxCounter = 0; +volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置DMA + DMA_Configuration(); + //配置SPI + SPI_Configuration(); + /**********************SPIy Loop Send -- SPIz DMA Receive*******************/ + //使能SPIz DMA RX + SPI_DMACmd(SPIz, SPI_DMAReq_Rx, ENABLE); + //软件NSS，选中SPIz + SPI_NSSInternalSoftwareConfig(SPIz, SPI_NSSInternalSoft_Reset); + while (TxCounter < BufferSize) + { + //SPIy 发送 + while (SPI_GetFlagStatus(SPIy, SPI_FLAG_TXE) == RESET); + SPI_SendData(SPIy, TxBuffer1[TxCounter++]); + //SPIZ通过DMA接收 + } + //等待DMA接收完成 + while (DMA_GetFlagStatus(SPIz_RX_DMACHANNEL) != DMA_CHANNEL_STATUS_TRANSCOMPLETE); + //释放SPIz + SPI_NSSInternalSoftwareConfig(SPIz, SPI_NSSInternalSoft_Set); + /*****************SPIy Loop Send and Receive -- SPIz DMA Send****************/ + TxCounter = 0; + //读DR以清除RXNE标志位 + SPI_ReceiveData(SPIy); + //失能SPIz DMA RX + SPI_DMACmd(SPIz, SPI_DMAReq_Rx, DISABLE); + //清空发送缓冲区和移位寄存器 + SPI_FlushSendBuff(SPIz); + //使能SPIz DMA TX + SPI_DMACmd(SPIz, SPI_DMAReq_Tx, ENABLE); + //软件NSS，选中SPIz + SPI_NSSInternalSoftwareConfig(SPIz, SPI_NSSInternalSoft_Reset); + while (TxCounter < BufferSize) + { + //SPIy 发送 + while (SPI_GetFlagStatus(SPIy, SPI_FLAG_TXE) == RESET); + SPI_SendData(SPIy, TxBuffer1[TxCounter++]); + //SPIZ通过DMA发送 + //SPIy 接收 + while (SPI_GetFlagStatus(SPIy, SPI_FLAG_RXNE) == RESET); + RxBuffer1[RxCounter++] = SPI_ReceiveData(SPIy); + } + //释放SPIz + SPI_NSSInternalSoftwareConfig(SPIz, SPI_NSSInternalSoft_Set); + //检查收发数据一致性 + TransferStatus1 = Buffercmp(TxBuffer1, RxBuffer2, BufferSize); + TransferStatus2 = Buffercmp(TxBuffer2, RxBuffer1, BufferSize); + if (TransferStatus1 == PASSED && TransferStatus2 == PASSED) //PASSED + { + //LED1亮 + PB09_SETHIGH(); + } + else //FAILED + { + //LED2亮 + PB08_SETHIGH(); + } + while (1) + { + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 24MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV2); + //外设时钟使能 + RCC_AHBPeriphClk_Enable(SPIy_GPIO_CLK | SPIz_GPIO_CLK | RCC_AHB_PERIPH_DMA | RCC_AHB_PERIPH_GPIOB, ENABLE); + SPIy_APBClkENx(SPIy_CLK, ENABLE); + SPIz_APBClkENx(SPIz_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //SPI SCK MOSI MISO 复用 + SPIy_AF_SCK; + SPIy_AF_MISO; + SPIy_AF_MOSI; + SPIz_AF_SCK; + SPIz_AF_MISO; + SPIz_AF_MOSI; + //推挽输出 + GPIO_InitStructure.Pins = SPIy_SCK_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(SPIy_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.Pins = SPIy_MOSI_PIN; + GPIO_Init(SPIy_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.Pins = SPIz_MISO_PIN; + GPIO_Init(SPIz_GPIO, &GPIO_InitStructure); + //浮空输入 + GPIO_InitStructure.Pins = SPIz_SCK_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT; + GPIO_Init(SPIz_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.Pins = SPIz_MOSI_PIN; + GPIO_Init(SPIz_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.Pins = SPIy_MISO_PIN; + GPIO_Init(SPIy_GPIO, &GPIO_InitStructure); + //PB9 LED1 / PB8 LED2 + GPIO_InitStructure.Pins = GPIO_PIN_9 | GPIO_PIN_8; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + //LED灭 + PB09_SETLOW(); + PB08_SETLOW(); +} + +/** + * @brief 配置DMA + * + */ +void DMA_Configuration(void) +{ + DMA_InitTypeDef DMA_InitStructure; + //初始化SPIz DMA TX + DMA_InitStructure.DMA_Mode = DMA_MODE_BLOCK; + DMA_InitStructure.DMA_TransferWidth = DMA_TRANSFER_WIDTH_8BIT; + DMA_InitStructure.DMA_SrcInc = DMA_SrcAddress_Increase; + DMA_InitStructure.DMA_DstInc = DMA_DstAddress_Fix; + DMA_InitStructure.TrigMode = DMA_HardTrig; + DMA_InitStructure.HardTrigSource = SPIz_DMA_TxTrigSource; + DMA_InitStructure.DMA_TransferCnt = BufferSize; + DMA_InitStructure.DMA_SrcAddress = (uint32_t)TxBuffer2; + DMA_InitStructure.DMA_DstAddress = (uint32_t)&SPIz->DR; + DMA_Init(SPIz_TX_DMACHANNEL, &DMA_InitStructure); + DMA_Cmd(SPIz_TX_DMACHANNEL, ENABLE); + //初始化SPIz DMA RX + DMA_InitStructure.DMA_Mode = DMA_MODE_BLOCK; + DMA_InitStructure.DMA_TransferWidth = DMA_TRANSFER_WIDTH_8BIT; + DMA_InitStructure.DMA_SrcInc = DMA_SrcAddress_Fix; + DMA_InitStructure.DMA_DstInc = DMA_DstAddress_Increase; + DMA_InitStructure.TrigMode = DMA_HardTrig; + DMA_InitStructure.HardTrigSource = SPIz_DMA_RxTrigSource; + DMA_InitStructure.DMA_TransferCnt = BufferSize; + DMA_InitStructure.DMA_SrcAddress = (uint32_t)&SPIz->DR; + DMA_InitStructure.DMA_DstAddress = (uint32_t)RxBuffer2; + DMA_Init(SPIz_RX_DMACHANNEL, &DMA_InitStructure); + DMA_Cmd(SPIz_RX_DMACHANNEL, ENABLE); +} + +/** + * @brief 配置SPI 3Mbit/s + * + */ +void SPI_Configuration() +{ + SPI_InitTypeDef SPI_InitStructure; + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; // 双线全双工 + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; // 主机模式 + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; // 帧数据长度为8bit + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; // 时钟空闲电平为低 + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; // 第一个边沿采样 + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; // 片选信号由SSI寄存器控制 + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8; // 波特率为PCLK的8分频 + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; // 最高有效位 MSB 收发在前 + SPI_InitStructure.SPI_Speed = SPI_Speed_Low; // 低速SPI + SPI_Init(SPIy, &SPI_InitStructure); + SPI_InitStructure.SPI_Mode = SPI_Mode_Slave; // 从机模式 + SPI_Init(SPIz, &SPI_InitStructure); + SPI_Cmd(SPIy, ENABLE); + SPI_Cmd(SPIz, ENABLE); +} + +/** + * @brief Compares two buffers + * + * @param pBuffer1 :buffers to be compared + * @param pBuffer2 :buffers to be compared + * @param BufferLength :buffer's length + * @return TestStatus + * @arg PASSED: pBuffer1 identical to pBuffer2 + * @arg FAILED: pBuffer1 differs from pBuffer2 + */ +TestStatus Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + pBuffer1++; + pBuffer2++; + } + return PASSED; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/readme.txt new file mode 100644 index 0000000..36de90c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA/readme.txt @@ -0,0 +1,40 @@ +示例目的： + SPI通过DMA收发数据示例。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟2分频，24MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=24MHz + 4. SPI，波特率为PCLK的8分频，3Mbps + 5. DMA，硬件触发 BLOCK 传输模式 + 6. PB09（LED1）设置为PUSH-PULL输出 + 7. PB08（LED2）设置为PUSH-PULL输出 + +演示说明： + SPIy（主机）查询方式（TXE）发送TxBuffer1缓冲区中的数据， + SPIz（从机）通过DMA接收数据，存储到RxBuffer2缓冲区。 + + SPIy（主机）查询方式（TXE）发送TxBuffer1缓冲区中的数据， + 同时SPIz（从机）通过DMA发送TxBuffer2缓冲区中的数据， + SPIy（主机）查询方式（RXNE）接收数据，并存储到RxBuffer1缓冲区。 + + 比较TxBuffer1和RxBuffer2，TxBuffer2和RxBuffer1， + 如果数据一致，则LED1亮，否则LED2亮。 + +硬件连接： + SPIy_SCK (PA10) -- SPIz_SCK (PB13) + SPIy_MISO (PA11) -- SPIz_MISO (PB14) + SPIy_MOSI (PA12) -- SPIz_MOSI (PB15) + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/EWARM/Project.ewd new file mode 100644 index 0000000..800c43b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + 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$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/EWARM/Project.ewp new file mode 100644 index 0000000..07d528a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/EWARM/Project.ewp @@ -0,0 +1,2163 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/MDK/Project.uvoptx new file mode 100644 index 0000000..fbb0639 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/MDK/Project.uvoptx @@ -0,0 +1,413 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + TxBuffer1 + + + 1 + 1 + RxBuffer2 + + + 2 + 1 + TransferStatus1 + + + 3 + 1 + ARRAY_SZ(TxBuffer1) + + + 4 + 1 + TxBuffer2 + + + 5 + 1 + RxBuffer1 + + + 6 + 1 + TransferStatus2 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\DMACHANNEL1 + 35903 + + + System Viewer\DMACHANNEL2 + 35904 + + + System Viewer\SPI2 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_spi.c + cw32f030_spi.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_dma.c + cw32f030_dma.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/MDK/Project.uvprojx new file mode 100644 index 0000000..289a927 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/MDK/Project.uvprojx @@ -0,0 +1,488 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_spi.c + 1 + ..\..\..\..\Libraries\src\cw32f030_spi.c + + + cw32f030_dma.c + 1 + ..\..\..\..\Libraries\src\cw32f030_dma.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/USER/inc/main.h new file mode 100644 index 0000000..896d274 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/USER/inc/main.h @@ -0,0 +1,74 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_spi.h" +#include "cw32f030_dma.h" +#include "cw32f030_flash.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/USER/src/main.c new file mode 100644 index 0000000..2283a96 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/USER/src/main.c @@ -0,0 +1,320 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define SPI_MASTER //主机模式 +//#define SPI_SLAVE //从机模式 + +//SPI +#define SPIx CW_SPI2 +#define SPIx_CLK RCC_APB1_PERIPH_SPI2 +#define SPIx_APBClkENx RCC_APBPeriphClk_Enable1 + +//SPI GPIO +#define SPIx_SCK_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define SPIx_SCK_GPIO_PORT CW_GPIOA +#define SPIx_SCK_GPIO_PIN GPIO_PIN_2 +#define SPIx_SCK_AF() PA02_AFx_SPI2SCK() + +#define SPIx_MISO_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define SPIx_MISO_GPIO_PORT CW_GPIOA +#define SPIx_MISO_GPIO_PIN GPIO_PIN_0 +#define SPIx_MISO_AF() PA00_AFx_SPI2MISO() + +#define SPIx_MOSI_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define SPIx_MOSI_GPIO_PORT CW_GPIOA +#define SPIx_MOSI_GPIO_PIN GPIO_PIN_1 +#define SPIx_MOSI_AF() PA01_AFx_SPI2MOSI() + +#define SPIx_CS_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define SPIx_CS_GPIO_PORT CW_GPIOA +#define SPIx_CS_GPIO_PIN GPIO_PIN_3 +#define SPIx_CS_AF() PA03_AFx_SPI2CS() + +//CS LOW or HIGH +#define SPIx_CS_LOW() PA03_SETLOW() +#define SPIx_CS_HIGH() PA03_SETHIGH() + +//DMA +#define SPIx_RX_DMACHANNEL CW_DMACHANNEL1 +#define SPIx_TX_DMACHANNEL CW_DMACHANNEL2 +#define SPIx_DMA_RxTrigSource DMA_HardTrig_SPI2_RXBufferNE +#define SPIx_DMA_TxTrigSource DMA_HardTrig_SPI2_TXBufferE +#define BufferSize ARRAY_SZ(TxBuffer) +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void DMA_Configuration(void); +void SPI_Configuration(void); +TestStatus Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxBuffer[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, + 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, + 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, + 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x55 + }; +uint8_t RxBuffer[BufferSize]; +volatile TestStatus TransferStatus = FAILED; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置DMA + DMA_Configuration(); + //配置SPI + SPI_Configuration(); +#ifdef SPI_MASTER + //拉低CS，选中SPI从机 + SPIx_CS_LOW(); +#endif +#ifdef SPI_SLAVE + //清空发送缓冲区和移位寄存器 + SPI_FlushSendBuff(SPIx); +#endif + //使能SPI DMA TX and RX + SPI_DMACmd(SPIx, SPI_DMAReq_Tx | SPI_DMAReq_Rx, ENABLE); + while (1) + { + if (RxBuffer[BufferSize - 1] == 0x55) //传输完成 + { +#ifdef SPI_MASTER + SPIx_CS_HIGH(); +#endif + //LED1亮 + PB01_SETHIGH(); + //检查收发数据一致性 + TransferStatus = Buffercmp(RxBuffer, TxBuffer, BufferSize); + if (TransferStatus == PASSED) //PASSED + { + //LED2亮 + PA07_SETHIGH(); + } + } + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //外设时钟使能 + RCC_AHBPeriphClk_Enable(SPIx_SCK_GPIO_CLK | SPIx_MISO_GPIO_CLK | SPIx_MOSI_GPIO_CLK | SPIx_CS_GPIO_CLK | \ + RCC_AHB_PERIPH_DMA | RCC_AHB_PERIPH_GPIOA | RCC_AHB_PERIPH_GPIOB | RCC_AHB_PERIPH_FLASH, ENABLE); + SPIx_APBClkENx(SPIx_CLK, ENABLE); + //SYSCLK = PLL = 64MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + RCC_PLL_Enable(RCC_PLLSOURCE_HSI, 8000000, RCC_PLL_MUL_8); + FLASH_SetLatency(FLASH_Latency_3); //频率大于48M需要配置FlashWait=3 + RCC_SysClk_Switch(RCC_SYSCLKSRC_PLL); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //SPI SCK MOSI MISO 复用 + SPIx_SCK_AF(); + SPIx_MISO_AF(); + SPIx_MOSI_AF(); +#ifdef SPI_MASTER + //推挽输出 SCK MOSI CS + GPIO_InitStructure.Pins = SPIx_SCK_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(SPIx_SCK_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = SPIx_MOSI_GPIO_PIN; + GPIO_Init(SPIx_MOSI_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = SPIx_CS_GPIO_PIN; + GPIO_Init(SPIx_CS_GPIO_PORT, &GPIO_InitStructure); + //浮空输入 MISO + GPIO_InitStructure.Pins = SPIx_MISO_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT; + GPIO_Init(SPIx_MISO_GPIO_PORT, &GPIO_InitStructure); + //拉高CS + SPIx_CS_HIGH(); +#endif +#ifdef SPI_SLAVE + //SPI CS复用 + SPIx_CS_AF(); + //推挽输出 MISO + GPIO_InitStructure.Pins = SPIx_MISO_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(SPIx_MISO_GPIO_PORT, &GPIO_InitStructure); + //浮空输入 SCK MOSI CS + GPIO_InitStructure.Pins = SPIx_SCK_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT; + GPIO_Init(SPIx_SCK_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = SPIx_MOSI_GPIO_PIN; + GPIO_Init(SPIx_MOSI_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = SPIx_CS_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(SPIx_CS_GPIO_PORT, &GPIO_InitStructure); +#endif + //PB1 LED1 / PA7 LED2 + GPIO_InitStructure.Pins = GPIO_PIN_1; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.Pins = GPIO_PIN_7; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + //LED灭 + PB01_SETLOW(); + PA07_SETLOW(); +} + +/** + * @brief 配置DMA + * + */ +void DMA_Configuration(void) +{ + DMA_InitTypeDef DMA_InitStructure; + //初始化SPI DMA TX + DMA_InitStructure.DMA_Mode = DMA_MODE_BLOCK; + DMA_InitStructure.DMA_TransferWidth = DMA_TRANSFER_WIDTH_8BIT; + DMA_InitStructure.DMA_SrcInc = DMA_SrcAddress_Increase; + DMA_InitStructure.DMA_DstInc = DMA_DstAddress_Fix; + DMA_InitStructure.TrigMode = DMA_HardTrig; + DMA_InitStructure.HardTrigSource = SPIx_DMA_TxTrigSource; + DMA_InitStructure.DMA_TransferCnt = BufferSize; + DMA_InitStructure.DMA_SrcAddress = (uint32_t)TxBuffer; + DMA_InitStructure.DMA_DstAddress = (uint32_t)&SPIx->DR; + DMA_Init(SPIx_TX_DMACHANNEL, &DMA_InitStructure); + DMA_Cmd(SPIx_TX_DMACHANNEL, ENABLE); + //初始化SPI DMA RX + DMA_InitStructure.DMA_Mode = DMA_MODE_BLOCK; + DMA_InitStructure.DMA_TransferWidth = DMA_TRANSFER_WIDTH_8BIT; + DMA_InitStructure.DMA_SrcInc = DMA_SrcAddress_Fix; + DMA_InitStructure.DMA_DstInc = DMA_DstAddress_Increase; + DMA_InitStructure.TrigMode = DMA_HardTrig; + DMA_InitStructure.HardTrigSource = SPIx_DMA_RxTrigSource; + DMA_InitStructure.DMA_TransferCnt = BufferSize; + DMA_InitStructure.DMA_SrcAddress = (uint32_t)&SPIx->DR; + DMA_InitStructure.DMA_DstAddress = (uint32_t)RxBuffer; + DMA_Init(SPIx_RX_DMACHANNEL, &DMA_InitStructure); + DMA_Cmd(SPIx_RX_DMACHANNEL, ENABLE); +} + +/** + * @brief 配置SPI 16Mbps + * + */ +void SPI_Configuration() +{ + SPI_InitTypeDef SPI_InitStructure; + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; // 双线全双工 + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; // 主机模式 + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; // 帧数据长度为8bit + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; // 时钟空闲电平为低 + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; // 第一个边沿采样 + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; // 片选信号由SSI寄存器控制 + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; // 波特率为PCLK的4分频 + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; // 最高有效位 MSB 收发在前 + SPI_InitStructure.SPI_Speed = SPI_Speed_High; // 高速SPI +#ifdef SPI_SLAVE + SPI_InitStructure.SPI_Mode = SPI_Mode_Slave; // 从机模式 + SPI_InitStructure.SPI_NSS = SPI_NSS_Hard; // SPI_CS引脚电平决定本机是否被选中 +#endif + SPI_Init(SPIx, &SPI_InitStructure); + SPI_Cmd(SPIx, ENABLE); +} + +/** + * @brief Compares two buffers + * + * @param pBuffer1 :buffers to be compared + * @param pBuffer2 :buffers to be compared + * @param BufferLength :buffer's length + * @return TestStatus + * @arg PASSED: pBuffer1 identical to pBuffer2 + * @arg FAILED: pBuffer1 differs from pBuffer2 + */ +TestStatus Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + pBuffer1++; + pBuffer2++; + } + return PASSED; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/readme.txt new file mode 100644 index 0000000..b6aa663 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_DMA_TwoBoards/readme.txt @@ -0,0 +1,39 @@ +示例目的： + SPI主从通信示例（带DMA）。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC，PLL + 3. 系统时钟设置为HSIOSC时钟3分频，PLL的4倍频，64MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=64MHz + 4. SPI，波特率为PCLK的4分频，16Mbps + 5. DMA，硬件触发 BLOCK 传输模式 + +演示说明： + - + #define SPI_MASTER //主机模式 + SPI_MASTER通过DMA发送TxBuffer缓冲区中的数据，通过DMA接收数据到RxBuffer缓冲区。 + DMA传输完成后，LED1亮，比较TxBuffer和RxBuffer，如果数据一致，则LED2亮。 + + - + #define SPI_SLAVE //从机模式 + SPI_SLAVE通过DMA发送TxBuffer缓冲区中的数据，通过DMA接收数据到RxBuffer缓冲区。 + DMA传输完成后，LED1亮，比较TxBuffer和RxBuffer，如果数据一致，则LED2亮。 + +硬件连接： + SPI_MASTER SCK (PA02)-- SPI_SLAVE SCK (PA02) + SPI_MASTER MISO (PA00)-- SPI_SLAVE MISO (PA00) + SPI_MASTER MOSI (PA01)-- SPI_SLAVE MOSI (PA01) + SPI_MASTER CS (PA03)-- SPI_SLAVE CS (PA03) + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/EWARM/Project.ewd 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$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/EWARM/Project.ewp new file mode 100644 index 0000000..d27bd0b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/EWARM/Project.ewp @@ -0,0 +1,2165 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + 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+ + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + Retarget + + $PROJ_DIR$\..\..\..\..\Utilities\write.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_uart.c + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\cw32_eval_spi_flash.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + $PROJ_DIR$\..\USER\src\main.c + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/MDK/Project.uvoptx new file mode 100644 index 0000000..22992e2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/MDK/Project.uvoptx @@ -0,0 +1,374 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + TxBuffer + + + 1 + 1 + UniqueID + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\USER\src\cw32_eval_spi_flash.c + cw32_eval_spi_flash.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_spi.c + cw32f030_spi.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/MDK/Project.uvprojx new file mode 100644 index 0000000..986fda7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/MDK/Project.uvprojx @@ -0,0 +1,472 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4098 + + 0 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 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+ ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + cw32_eval_spi_flash.c + 1 + ..\USER\src\cw32_eval_spi_flash.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_spi.c + 1 + ..\..\..\..\Libraries\src\cw32f030_spi.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/inc/cw32_eval_spi_flash.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/inc/cw32_eval_spi_flash.h new file mode 100644 index 0000000..3608c33 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/inc/cw32_eval_spi_flash.h @@ -0,0 +1,150 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32_EVAL_SPI_FLASH_H +#define __CW32_EVAL_SPI_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_spi.h" + +/****************************************************************************** + * type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * pre-processor symbols/macros ('#define') + ******************************************************************************/ +//Manufacturer and Device Identification (W25Q64) +#define sDeviceID 0x16 +#define sManufactDeviceID 0xEF16 +#define sJedecID 0xEF4017 + +/* SPI FLASH supported commands */ +#define FLASH_CMD_WriteEnable 0x06 +#define FLASH_CMD_WriteDisable 0x04 +#define FLASH_CMD_ReadStatusReg1 0x05 +#define FLASH_CMD_ReadStatusReg2 0x35 +#define FLASH_CMD_WriteStatusReg1 0x01 +#define FLASH_CMD_WriteStatusReg2 0x31 +#define FLASH_CMD_ReadData 0x03 +#define FLASH_CMD_FastReadData 0x0B +#define FLASH_CMD_FastReadDual 0x3B +#define FLASH_CMD_PageProgram 0x02 +#define FLASH_CMD_SectorErase 0x20 +#define FLASH_CMD_BlockErase 0xD8 +#define FLASH_CMD_ChipErase 0xC7 +#define FLASH_CMD_PowerDown 0xB9 +#define FLASH_CMD_ReleasePowerDown 0xAB +#define FLASH_CMD_DeviceID 0xAB +#define FLASH_CMD_ManufactDeviceID 0x90 +#define FLASH_CMD_JedecID 0x9F +#define FLASH_CMD_UniqueID 0x4B + +/* Write In Progress (WIP) flag */ +#define FLASH_WIP_FLAG 0x01 + +#define FLASH_DUMMY_BYTE 0xFF + +#define SPI_FLASH_PageSize 256 +#define SPI_FLASH_PerWritePageSize 256 + +//SPIx +#define FLASH_SPIx CW_SPI1 +#define FLASH_SPI_CLK RCC_APB2_PERIPH_SPI1 +#define FLASH_SPI_APBClkENx RCC_APBPeriphClk_Enable2 + +//SPIx GPIO +#define FLASH_SPI_SCK_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define FLASH_SPI_SCK_GPIO_PORT CW_GPIOA +#define FLASH_SPI_SCK_GPIO_PIN GPIO_PIN_10 + +#define FLASH_SPI_MISO_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define FLASH_SPI_MISO_GPIO_PORT CW_GPIOA +#define FLASH_SPI_MISO_GPIO_PIN GPIO_PIN_11 + +#define FLASH_SPI_MOSI_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define FLASH_SPI_MOSI_GPIO_PORT CW_GPIOA +#define FLASH_SPI_MOSI_GPIO_PIN GPIO_PIN_12 + +#define FLASH_SPI_CS_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define FLASH_SPI_CS_GPIO_PORT CW_GPIOA +#define FLASH_SPI_CS_GPIO_PIN GPIO_PIN_15 + +//GPIO AF +#define FLASH_SPI_AF_SCK PA10_AFx_SPI1SCK() +#define FLASH_SPI_AF_MISO PA11_AFx_SPI1MISO() +#define FLASH_SPI_AF_MOSI PA12_AFx_SPI1MOSI() + +//CS LOW or HIGH +#define FLASH_SPI_CS_LOW() PA15_SETLOW() +#define FLASH_SPI_CS_HIGH() PA15_SETHIGH() + +/****************************************************************************** +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ + + +/****************************************************************************** +* Global function prototypes +******************************************************************************/ + +/* SPI FLASH 初始化*/ +void SPI_FLASH_Init(void); + +/* Low layer functions */ +uint8_t SPI_FLASH_ReadByte(void); +uint8_t SPI_FLASH_SendByte(uint8_t byte); +uint16_t SPI_FLASH_SendHalfWord(uint16_t HalfWord); +void SPI_FLASH_WriteEnable(void); +void SPI_FLASH_WaitForWriteEnd(void); + +/* 读写状态寄存器 */ +uint8_t SPI_FLASH_ReadStatusReg1(void); +uint8_t SPI_FLASH_ReadStatusReg2(void); +void SPI_FLASH_WriteStatusReg1(uint8_t status); +void SPI_FLASH_WriteStatusReg2(uint8_t status); + +/* High layer functions */ +void SPI_FLASH_SectorErase(uint32_t SectorAddr); +void SPI_FLASH_BlockErase(uint32_t BlockAddr); +void SPI_FLASH_ChipErase(void); + +void SPI_FLASH_PageWrite(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite); +void SPI_FLASH_BufferWrite(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite); +void SPI_FLASH_BufferRead(uint8_t *pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead); +void SPI_FLASH_StartReadSequence(uint32_t ReadAddr); + +uint8_t SPI_FLASH_DeviceID(void); +uint16_t SPI_FLASH_ManufactDeviceID(void); +uint32_t SPI_FLASH_JedecID(void); +void SPI_FLASH_UniqueID(uint8_t *pBuffer); +void SPI_FLASH_PowerDown(void); +void SPI_FLASH_WAKEUP(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CW32_EVAL_SPI_FLASH_H */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/inc/main.h new file mode 100644 index 0000000..b6e2fc1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/inc/main.h @@ -0,0 +1,74 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_uart.h" +#include "cw32f030_spi.h" +#include "cw32_eval_spi_flash.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/src/cw32_eval_spi_flash.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/src/cw32_eval_spi_flash.c new file mode 100644 index 0000000..8a39933 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/src/cw32_eval_spi_flash.c @@ -0,0 +1,557 @@ +/** + * @file cw32_eval_spi_flash.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-26 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32_eval_spi_flash.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief 配置SPI FLASH + * + */ +void SPI_FLASH_Init(void) +{ + SPI_InitTypeDef SPI_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + /************************GPIO Configuration***********************/ + RCC_AHBPeriphClk_Enable(FLASH_SPI_SCK_GPIO_CLK | FLASH_SPI_MISO_GPIO_CLK | FLASH_SPI_MOSI_GPIO_CLK | FLASH_SPI_CS_GPIO_CLK, ENABLE); + FLASH_SPI_APBClkENx(FLASH_SPI_CLK, ENABLE); + //SPI SCK MOSI MISO 复用 + FLASH_SPI_AF_SCK; + FLASH_SPI_AF_MISO; + FLASH_SPI_AF_MOSI; + //CS + GPIO_InitStructure.Pins = FLASH_SPI_CS_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(FLASH_SPI_CS_GPIO_PORT, &GPIO_InitStructure); + //SCK + GPIO_InitStructure.Pins = FLASH_SPI_SCK_GPIO_PIN; + GPIO_Init(FLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); + //MOSI + GPIO_InitStructure.Pins = FLASH_SPI_MOSI_GPIO_PIN; + GPIO_Init(FLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); + //MISO + GPIO_InitStructure.Pins = FLASH_SPI_MISO_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT; + GPIO_Init(FLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); + //拉高CS + FLASH_SPI_CS_HIGH(); + /************************SPI Configuration***********************/ + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; // 双线全双工 + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; // 主机模式 + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; // 帧数据长度为8bit + SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; // 时钟空闲电平为高 + SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; // 第二个边沿采样 + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; // 片选信号由SSI寄存器控制 + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8; // 波特率为PCLK的8分频 + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; // 最高有效位 MSB 收发在前 + SPI_InitStructure.SPI_Speed = SPI_Speed_Low; // 低速SPI + SPI_Init(FLASH_SPIx, &SPI_InitStructure); + SPI_Cmd(FLASH_SPIx, ENABLE); +} + +/** + * @brief 通过SPI读取一个字节的数据 + * + * @return uint8_t :接收到的数据 + */ +uint8_t SPI_FLASH_ReadByte(void) +{ + return (SPI_FLASH_SendByte(FLASH_DUMMY_BYTE)); +} + +/** + * @brief 通过SPI发送一个字节的数据，并返回接收到的一个字节数据 + * + * @param byte :待发送的数据 + * @return uint8_t :接收到的数据 + */ +uint8_t SPI_FLASH_SendByte(uint8_t byte) +{ + while (SPI_GetFlagStatus(FLASH_SPIx, SPI_FLAG_TXE) == RESET); + SPI_SendData(FLASH_SPIx, byte); + while (SPI_GetFlagStatus(FLASH_SPIx, SPI_FLAG_RXNE) == RESET); + return SPI_ReceiveData(FLASH_SPIx); +} + +/** + * @brief 通过SPI发送两个字节的数据，并返回接收到的两个字节数据 + * + * @param HalfWord :待发送的数据 + * @return uint16_t :接收到的数据 + */ +uint16_t SPI_FLASH_SendHalfWord(uint16_t HalfWord) +{ + while (SPI_GetFlagStatus(FLASH_SPIx, SPI_FLAG_TXE) == RESET); + SPI_SendData(FLASH_SPIx, HalfWord); + while (SPI_GetFlagStatus(FLASH_SPIx, SPI_FLAG_RXNE) == RESET); + return SPI_ReceiveData(FLASH_SPIx); +} + +/** + * @brief 向FLASH发送 写使能 指令 + * + */ +void SPI_FLASH_WriteEnable(void) +{ + FLASH_SPI_CS_LOW(); + //发送 写使能 指令 + SPI_FLASH_SendByte(FLASH_CMD_WriteEnable); + FLASH_SPI_CS_HIGH(); +} + +/** + * @brief 等待擦除或编程完成 + * + */ +void SPI_FLASH_WaitForWriteEnd(void) +{ + uint8_t flashstatus = 0; + FLASH_SPI_CS_LOW(); + // 发送 读状态寄存器1 指令 + SPI_FLASH_SendByte(FLASH_CMD_ReadStatusReg1); + do + { + //读FLASH状态寄存器 + flashstatus = SPI_FLASH_ReadByte(); + } + while ((flashstatus & FLASH_WIP_FLAG) == SET); //正在写入，继续循环 + FLASH_SPI_CS_HIGH(); +} + +/** + * @brief 读状态寄存器1 + * + * @return uint8_t + */ +uint8_t SPI_FLASH_ReadStatusReg1(void) +{ + uint8_t flashstatus = 0; + FLASH_SPI_CS_LOW(); + // 发送 读状态寄存器1 指令 + SPI_FLASH_SendByte(FLASH_CMD_ReadStatusReg1); + flashstatus = SPI_FLASH_ReadByte(); + FLASH_SPI_CS_HIGH(); + return flashstatus; +} + +/** + * @brief 读状态寄存器2 + * + * @return uint8_t + */ +uint8_t SPI_FLASH_ReadStatusReg2(void) +{ + uint8_t flashstatus = 0; + FLASH_SPI_CS_LOW(); + // 发送 读状态寄存器2 指令 + SPI_FLASH_SendByte(FLASH_CMD_ReadStatusReg2); + flashstatus = SPI_FLASH_ReadByte(); + FLASH_SPI_CS_HIGH(); + return flashstatus; +} + +/** + * @brief 写状态寄存器1 + * + * @param status + */ +void SPI_FLASH_WriteStatusReg1(uint8_t status) +{ + //发送 写使能 指令 + SPI_FLASH_WriteEnable(); + FLASH_SPI_CS_LOW(); + // 发送 写状态寄存器1 指令 + SPI_FLASH_SendByte(FLASH_CMD_WriteStatusReg1); + //发送 状态寄存器1 设定值 + SPI_FLASH_SendByte(status); + FLASH_SPI_CS_HIGH(); + //等待写入完成 + SPI_FLASH_WaitForWriteEnd(); +} + +/** + * @brief 写状态寄存器2 + * + * @param status + */ +void SPI_FLASH_WriteStatusReg2(uint8_t status) +{ + //发送 写使能 指令 + SPI_FLASH_WriteEnable(); + FLASH_SPI_CS_LOW(); + // 发送 写状态寄存器2 指令 + SPI_FLASH_SendByte(FLASH_CMD_WriteStatusReg2); + //发送 状态寄存器2 设定值 + SPI_FLASH_SendByte(status); + FLASH_SPI_CS_HIGH(); + //等待写入完成 + SPI_FLASH_WaitForWriteEnd(); +} + +/** + * @brief 扇区擦除 4KB + * + * @param SectorAddr :待擦除的扇区地址 + */ +void SPI_FLASH_SectorErase(uint32_t SectorAddr) +{ + //发送 写使能 指令 + SPI_FLASH_WriteEnable(); + //等待写入完成 + // SPI_FLASH_WaitForWriteEnd(); + FLASH_SPI_CS_LOW(); + //发送 扇区擦除 指令 + SPI_FLASH_SendByte(FLASH_CMD_SectorErase); + //发送 待擦除扇区地址 + SPI_FLASH_SendByte((SectorAddr & 0xFF0000) >> 16); + SPI_FLASH_SendByte((SectorAddr & 0xFF00) >> 8); + SPI_FLASH_SendByte(SectorAddr & 0xFF); + FLASH_SPI_CS_HIGH(); + //等待擦除完成 + SPI_FLASH_WaitForWriteEnd(); +} + +/** + * @brief 块擦除 64KB + * + * @param BlockAddr :待擦除的块地址 + */ +void SPI_FLASH_BlockErase(uint32_t BlockAddr) +{ + //发送 写使能 指令 + SPI_FLASH_WriteEnable(); + //等待写入完成 + // SPI_FLASH_WaitForWriteEnd(); + FLASH_SPI_CS_LOW(); + //发送 块擦除 指令 + SPI_FLASH_SendByte(FLASH_CMD_BlockErase); + //发送 待擦除块地址 + SPI_FLASH_SendByte((BlockAddr & 0xFF0000) >> 16); + SPI_FLASH_SendByte((BlockAddr & 0xFF00) >> 8); + SPI_FLASH_SendByte(BlockAddr & 0xFF); + FLASH_SPI_CS_HIGH(); + //等待擦除完成 + SPI_FLASH_WaitForWriteEnd(); +} + +/** + * @brief 整片擦除 + * + */ +void SPI_FLASH_ChipErase(void) +{ + //发送 写使能 指令 + SPI_FLASH_WriteEnable(); + FLASH_SPI_CS_LOW(); + //发送 整片擦除 指令 + SPI_FLASH_SendByte(FLASH_CMD_ChipErase); + FLASH_SPI_CS_HIGH(); + //等待擦除完成 + SPI_FLASH_WaitForWriteEnd(); +} + +/** + * @brief 页写入数据 + * + * @param pBuffer :待写入数据的指针 + * @param WriteAddr :写入地址 + * @param NumByteToWrite :写入数据长度 + * @note + * -需要先擦除 + * -NumByteToWrite <= SPI_FLASH_PerWritePageSize + */ +void SPI_FLASH_PageWrite(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite) +{ + //发送 写使能 指令 + SPI_FLASH_WriteEnable(); + FLASH_SPI_CS_LOW(); + //发送 页写入 指令 + SPI_FLASH_SendByte(FLASH_CMD_PageProgram); + //发送 写地址 + SPI_FLASH_SendByte((WriteAddr & 0xFF0000) >> 16); + SPI_FLASH_SendByte((WriteAddr & 0xFF00) >> 8); + SPI_FLASH_SendByte(WriteAddr & 0xFF); + //写入数据 + while (NumByteToWrite--) + { + SPI_FLASH_SendByte(*pBuffer); + pBuffer++; + } + FLASH_SPI_CS_HIGH(); + //等待写入完成 + SPI_FLASH_WaitForWriteEnd(); +} + +/** + * @brief 写入不定量数据 + * + * @param pBuffer :待写入数据的指针 + * @param WriteAddr :写入地址 + * @param NumByteToWrite :写入数据长度 + * @note + * -需要先擦除 + */ +void SPI_FLASH_BufferWrite(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite) +{ + uint8_t NumOfPage = 0, NumOfSingle = 0, Addr = 0, count = 0, temp = 0; + Addr = WriteAddr % SPI_FLASH_PageSize; + count = SPI_FLASH_PageSize - Addr; + NumOfPage = NumByteToWrite / SPI_FLASH_PageSize; + NumOfSingle = NumByteToWrite % SPI_FLASH_PageSize; + if (Addr == 0) /* WriteAddr 刚好按页对齐 */ + { + if (NumOfPage == 0) /* NumByteToWrite < SPI_FLASH_PageSize */ + { + SPI_FLASH_PageWrite(pBuffer, WriteAddr, NumByteToWrite); + } + else /* NumByteToWrite >= SPI_FLASH_PageSize */ + { + while (NumOfPage--) + { + SPI_FLASH_PageWrite(pBuffer, WriteAddr, SPI_FLASH_PageSize); + WriteAddr += SPI_FLASH_PageSize; + pBuffer += SPI_FLASH_PageSize; + } + if (NumOfSingle != 0) + { + SPI_FLASH_PageWrite(pBuffer, WriteAddr, NumOfSingle); + } + } + } + else /* WriteAddr 与 SPI_FLASH_PageSize 不对齐 */ + { + if (NumOfPage == 0) /* NumByteToWrite < SPI_FLASH_PageSize */ + { + if (NumOfSingle > count) /*!< (NumByteToWrite + WriteAddr) > SPI_FLASH_PageSize */ + { + temp = NumOfSingle - count; + //写完当前页 + SPI_FLASH_PageWrite(pBuffer, WriteAddr, count); + WriteAddr += count; + pBuffer += count; + //写剩余数据 + SPI_FLASH_PageWrite(pBuffer, WriteAddr, temp); + } + else + { + SPI_FLASH_PageWrite(pBuffer, WriteAddr, NumByteToWrite); + } + } + else /* NumByteToWrite >= SPI_FLASH_PageSize */ + { + NumByteToWrite -= count; + NumOfPage = NumByteToWrite / SPI_FLASH_PageSize; + NumOfSingle = NumByteToWrite % SPI_FLASH_PageSize; + //先写完当前页，以后地址将对齐 + SPI_FLASH_PageWrite(pBuffer, WriteAddr, count); + WriteAddr += count; + pBuffer += count; + //WriteAddr 刚好按页对齐 + while (NumOfPage--) + { + SPI_FLASH_PageWrite(pBuffer, WriteAddr, SPI_FLASH_PageSize); + WriteAddr += SPI_FLASH_PageSize; + pBuffer += SPI_FLASH_PageSize; + } + if (NumOfSingle != 0) + { + SPI_FLASH_PageWrite(pBuffer, WriteAddr, NumOfSingle); + } + } + } +} + +/** + * @brief 读数据 + * + * @param pBuffer :存储读出数据的指针 + * @param ReadAddr :读取地址 + * @param NumByteToRead :读取数据长度 + */ +void SPI_FLASH_BufferRead(uint8_t *pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead) +{ + FLASH_SPI_CS_LOW(); + //发送 读数据 指令 + SPI_FLASH_SendByte(FLASH_CMD_ReadData); + //发送 读地址 + SPI_FLASH_SendByte((ReadAddr & 0xFF0000) >> 16); + SPI_FLASH_SendByte((ReadAddr & 0xFF00) >> 8); + SPI_FLASH_SendByte(ReadAddr & 0xFF); + //读数据 + while (NumByteToRead--) + { + *pBuffer = SPI_FLASH_ReadByte(); + pBuffer++; + } + FLASH_SPI_CS_HIGH(); +} + +/** + * @brief 启动读取数据字节序列 + * + * @param ReadAddr :读取地址 + */ +void SPI_FLASH_StartReadSequence(uint32_t ReadAddr) +{ + FLASH_SPI_CS_LOW(); + //发送 读数据 指令 + SPI_FLASH_SendByte(FLASH_CMD_ReadData); + //发送 读地址 + SPI_FLASH_SendByte((ReadAddr & 0xFF0000) >> 16); + SPI_FLASH_SendByte((ReadAddr & 0xFF00) >> 8); + SPI_FLASH_SendByte(ReadAddr & 0xFF); +} + +/** + * @brief 读取Device ID + * + * @return uint8_t :Device ID + */ +uint8_t SPI_FLASH_DeviceID(void) +{ + uint8_t Temp = 0; + FLASH_SPI_CS_LOW(); + //发送 读Device ID 指令 + SPI_FLASH_SendByte(FLASH_CMD_DeviceID); + SPI_FLASH_SendByte(FLASH_DUMMY_BYTE); + SPI_FLASH_SendByte(FLASH_DUMMY_BYTE); + SPI_FLASH_SendByte(FLASH_DUMMY_BYTE); + //读数据 + Temp = SPI_FLASH_ReadByte(); + FLASH_SPI_CS_HIGH(); + return Temp; +} + +/** + * @brief 读取Manufacturer / Device ID + * + * @return uint16_t :Manufacturer / Device ID + */ +uint16_t SPI_FLASH_ManufactDeviceID(void) +{ + uint16_t Temp = 0, Temp0 = 0, Temp1 = 0; + FLASH_SPI_CS_LOW(); + //发送 读Manufacturer / Device ID 指令 + SPI_FLASH_SendByte(FLASH_CMD_ManufactDeviceID); + SPI_FLASH_SendByte(0x00); + SPI_FLASH_SendByte(0x00); + SPI_FLASH_SendByte(0x00); + //读数据 + Temp0 = SPI_FLASH_ReadByte(); + Temp1 = SPI_FLASH_ReadByte(); + FLASH_SPI_CS_HIGH(); + Temp = (Temp0 << 8) | Temp1; + return Temp; +} + +/** + * @brief 读取JEDEC ID + * + * @return uint32_t :JEDEC ID + */ +uint32_t SPI_FLASH_JedecID(void) +{ + uint32_t Temp = 0, Temp0 = 0, Temp1 = 0, Temp2 = 0; + FLASH_SPI_CS_LOW(); + //发送 读JEDEC ID 指令 + SPI_FLASH_SendByte(FLASH_CMD_JedecID); + //读数据 + Temp0 = SPI_FLASH_ReadByte(); + Temp1 = SPI_FLASH_ReadByte(); + Temp2 = SPI_FLASH_ReadByte(); + FLASH_SPI_CS_HIGH(); + Temp = (Temp0 << 16) | (Temp1 << 8) | Temp2; + return Temp; +} + +/** + * @brief 读取Unique ID (64bit) + * + * @param pBuffer :存放UID的Buffer + */ +void SPI_FLASH_UniqueID(uint8_t *pBuffer) +{ + uint8_t NumByteToRead = 8; + FLASH_SPI_CS_LOW(); + //发送 读Unique ID 指令 + SPI_FLASH_SendByte(FLASH_CMD_UniqueID); + SPI_FLASH_SendByte(FLASH_DUMMY_BYTE); + SPI_FLASH_SendByte(FLASH_DUMMY_BYTE); + SPI_FLASH_SendByte(FLASH_DUMMY_BYTE); + SPI_FLASH_SendByte(FLASH_DUMMY_BYTE); + //读数据 + while (NumByteToRead--) + { + *pBuffer = SPI_FLASH_ReadByte(); + pBuffer++; + } + FLASH_SPI_CS_HIGH(); +} + +/** + * @brief 进入掉电模式 + * + */ +void SPI_FLASH_PowerDown(void) +{ + FLASH_SPI_CS_LOW(); + //发送 掉电 指令 + SPI_FLASH_SendByte(FLASH_CMD_PowerDown); + FLASH_SPI_CS_HIGH(); +} + +/** + * @brief 唤醒 + * + */ +void SPI_FLASH_WAKEUP(void) +{ + FLASH_SPI_CS_LOW(); + //发送 Release Power-down or High Performance Mode 指令 + SPI_FLASH_SendByte(FLASH_CMD_ReleasePowerDown); + FLASH_SPI_CS_HIGH(); +} + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/src/main.c new file mode 100644 index 0000000..f4a6201 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/USER/src/main.c @@ -0,0 +1,277 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTx +#define DEBUG_USARTx CW_UART1 +#define DEBUG_USART_CLK RCC_APB2_PERIPH_UART1 +#define DEBUG_USART_APBClkENx RCC_APBPeriphClk_Enable2 +#define DEBUG_USART_BaudRate 9600 +#define DEBUG_USART_UclkFreq 24000000 + +//UARTx GPIO +#define DEBUG_USART_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define DEBUG_USART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_USART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_RX_GPIO_PIN GPIO_PIN_9 + +//GPIO AF +#define DEBUG_USART_AFTX PA08_AFx_UART1TXD() +#define DEBUG_USART_AFRX PA09_AFx_UART1RXD() + +#define BufferSize (ARRAY_SZ(TxBuffer) - 1) + +#define FLASH_WriteAddress 0x00000 +#define FLASH_ReadAddress FLASH_WriteAddress +#define FLASH_SectorToEraseAddress FLASH_WriteAddress +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); +TestStatus Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength); + +#if defined ( __ICCARM__ ) + #define PUTCHAR_PROTOTYPE int MyLowLevelPutchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxBuffer[] = "CW32F030 SPI FLASH Example"; +uint8_t RxBuffer[BufferSize]; + +uint8_t DeviceID = 0; +uint16_t ManufactDeviceID = 0; +uint32_t JedecID = 0; +uint8_t UniqueID[8]; + +volatile TestStatus TransferStatus = FAILED; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置UART + UART_Configuration(); + //配置SPI + SPI_FLASH_Init(); + printf("\r\nCW32F030 SPI FLASH Example\r\n"); + DeviceID = SPI_FLASH_DeviceID(); + ManufactDeviceID = SPI_FLASH_ManufactDeviceID(); + JedecID = SPI_FLASH_JedecID(); + SPI_FLASH_UniqueID(UniqueID); + printf("\r\nDeviceID = 0x%X\r\nManufactDeviceID = 0x%X\r\nJedecID = 0x%X", DeviceID, ManufactDeviceID, JedecID); + printf("\r\nUniqueID = 0x "); + for (uint8_t i = 0; i < 8; i++) + { + printf("%X ", UniqueID[i]); + } + /* Check JEDEC ID */ + if (JedecID == sJedecID) + { + printf("\r\n\nFLASH Detected\r\n");; + //擦除扇区 4KB + SPI_FLASH_SectorErase(FLASH_SectorToEraseAddress); + //写数据 + SPI_FLASH_BufferWrite(TxBuffer, FLASH_WriteAddress, BufferSize); + printf("\r\n写入的数据为：%s\r\n", TxBuffer); + //读数据 + SPI_FLASH_BufferRead(RxBuffer, FLASH_ReadAddress, BufferSize); + printf("\r\n读出的数据为：%s\r\n", RxBuffer); + //检查写入的数据与读出的数据是否一致 + TransferStatus = Buffercmp(TxBuffer, RxBuffer, BufferSize); + //擦除扇区 4KB + SPI_FLASH_SectorErase(FLASH_SectorToEraseAddress); + //读数据 + SPI_FLASH_BufferRead(RxBuffer, FLASH_ReadAddress, BufferSize); + if (TransferStatus == PASSED) + { + PB09_SETHIGH(); + printf("\r\nFLASH Success\r\n"); + } + else + { + PB08_SETHIGH(); + printf("\r\nFLASH Error 1\r\n"); + } + for (uint8_t j = 0; j < BufferSize; j++) + { + if (RxBuffer[j] != 0xFF) + { + PB08_SETHIGH(); + printf("\r\nFLASH Error 2\r\n"); + } + } + } + else// (FlashID ！= sFLASH_ID) + { + PB08_SETHIGH(); + printf("\r\nFLASH Error 3\r\n"); + } + while (1) + { + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 24MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV2); + //外设时钟使能 + RCC_AHBPeriphClk_Enable(DEBUG_USART_GPIO_CLK | RCC_AHB_PERIPH_GPIOB, ENABLE); + DEBUG_USART_APBClkENx(DEBUG_USART_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //UART TX RX 复用 + DEBUG_USART_AFTX; + DEBUG_USART_AFRX; + GPIO_InitStructure.Pins = DEBUG_USART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = DEBUG_USART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStructure); + //PB9 LED1 / PB8 LED2 + GPIO_InitStructure.Pins = GPIO_PIN_9 | GPIO_PIN_8; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + //LED灭 + PB09_SETLOW(); + PB08_SETLOW(); +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + USART_InitTypeDef USART_InitStructure; + USART_InitStructure.USART_BaudRate = DEBUG_USART_BaudRate; + USART_InitStructure.USART_Over = USART_Over_16; + USART_InitStructure.USART_Source = USART_Source_PCLK; + USART_InitStructure.USART_UclkFreq = DEBUG_USART_UclkFreq; + USART_InitStructure.USART_StartBit = USART_StartBit_FE; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(DEBUG_USARTx, &USART_InitStructure); +} + +/** + * @brief Compares two buffers + * + * @param pBuffer1 :buffers to be compared + * @param pBuffer2 :buffers to be compared + * @param BufferLength :buffer's length + * @return TestStatus + * @arg PASSED: pBuffer1 identical to pBuffer2 + * @arg FAILED: pBuffer1 differs from pBuffer2 + */ +TestStatus Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + pBuffer1++; + pBuffer2++; + } + return PASSED; +} + +/** + * @brief Retargets the C library printf function to the USART. + * + */ +PUTCHAR_PROTOTYPE +{ + USART_SendData_8bit(DEBUG_USARTx, (uint8_t)ch); + + while (USART_GetFlagStatus(DEBUG_USARTx, USART_FLAG_TXE) == RESET); + + return ch; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/readme.txt new file mode 100644 index 0000000..775aa8d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FLASH/readme.txt @@ -0,0 +1,49 @@ +示例目的： + SPI读写外部FLASH（W25Q64）。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟2分频，24MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=24MHz + 4. SPI，波特率为PCLK的8分频，3Mbps + 5. UART的传输时钟设置为PCLK + 6. PB09（LED1）设置为PUSH-PULL输出 + 7. PB08（LED2）设置为PUSH-PULL输出 + + +演示说明： + 读外部FLASH的DeviceID、ManufactDeviceID、JedecID、UniqueID，并通过UART打印到串口助手。 + + 当读取的JedecID正确时： + 写入TxBuffer缓冲区中的数据到FLASH第1页。 + 读取FLASH第1页数据，并存储到RxBuffer缓冲区。 + 检查写入的数据与读出的数据是否一致： + 一致，打印“FLASH Success”，LED1亮， + 否则，打印“FLASH Error 1”，LED2亮。 + 擦除4KB扇区，读取FLASH第1页数据，并存储到RxBuffer缓冲区。 + RxBuffer缓冲区中数据存在‘1’时，打印“FLASH Error 2”，LED2亮。 + + 当读取的JedecID不正确时： + 打印“FLASH Error 3”，LED2亮。 + +硬件连接： + SPI1_SCK (PA10) -- FLASH SCK + SPI1_MISO (PA11) -- FLASH MISO + SPI1_MOSI (PA12) -- FLASH MOSI + SPI1_CS (PA15) -- FLASH CS + + UART1_TXD (PA08) -- PC_RX + UART1_RXD (PA09) -- PC_TX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/EWARM/Project.ewd new file mode 100644 index 0000000..800c43b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/EWARM/Project.ewp new file mode 100644 index 0000000..5ed80c5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/EWARM/Project.ewp @@ -0,0 +1,2157 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 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+ + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_spi.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/MDK/Project.uvoptx new file mode 100644 index 0000000..1add5e6 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/MDK/Project.uvoptx @@ -0,0 +1,403 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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+ 0 + 0 + 0 + 0 + 0 + 0 + ..\USER\src\main.c + + + + + + + 0 + 1 + PosWidth,0x0A + + + 1 + 1 + Period,0x10 + + + 2 + 1 + RxBuffer1 + + + 3 + 1 + RxBuffer2 + + + 4 + 1 + RxBuffer1[0] + + + 5 + 1 + RxBuffer2[0] + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_spi.c + cw32f030_spi.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/MDK/Project.uvprojx new file mode 100644 index 0000000..286cd00 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/MDK/Project.uvprojx @@ -0,0 +1,461 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_spi.c + 1 + ..\..\..\..\Libraries\src\cw32f030_spi.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/USER/inc/main.h new file mode 100644 index 0000000..df18f62 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/USER/inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_spi.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/USER/src/main.c new file mode 100644 index 0000000..46d20f4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/USER/src/main.c @@ -0,0 +1,268 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//SPIy MASTER +#define SPIy CW_SPI1 +#define SPIy_CLK RCC_APB2_PERIPH_SPI1 +#define SPIy_APBClkENx RCC_APBPeriphClk_Enable2 + +//SPIy GPIO +#define SPIy_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define SPIy_GPIO CW_GPIOA +#define SPIy_SCK_PIN GPIO_PIN_10 +#define SPIy_MISO_PIN GPIO_PIN_11 +#define SPIy_MOSI_PIN GPIO_PIN_12 +#define SPIy_AF_SCK PA10_AFx_SPI1SCK() +#define SPIy_AF_MISO PA11_AFx_SPI1MISO() +#define SPIy_AF_MOSI PA12_AFx_SPI1MOSI() + +//SPIz SLAVE +#define SPIz CW_SPI2 +#define SPIz_CLK RCC_APB1_PERIPH_SPI2 +#define SPIz_APBClkENx RCC_APBPeriphClk_Enable1 + +//SPIz GPIO +#define SPIz_GPIO_CLK RCC_AHB_PERIPH_GPIOB +#define SPIz_GPIO CW_GPIOB +#define SPIz_SCK_PIN GPIO_PIN_13 +#define SPIz_MISO_PIN GPIO_PIN_14 +#define SPIz_MOSI_PIN GPIO_PIN_15 +#define SPIz_AF_SCK PB13_AFx_SPI2SCK() +#define SPIz_AF_MISO PB14_AFx_SPI2MISO() +#define SPIz_AF_MOSI PB15_AFx_SPI2MOSI() + +#define BufferSize ARRAY_SZ(TxBuffer1) +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void SPI_Configuration(void); +TestStatus Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxBuffer1[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, + 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, + 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, + 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23 + }; +uint8_t TxBuffer2[] = {0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, + 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, + 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, + 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83 + }; +uint8_t RxBuffer1[BufferSize]; +uint8_t RxBuffer2[BufferSize]; +uint8_t TxCounter = 0, RxCounter = 0; +volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置SPI + SPI_Configuration(); + /**************************SPIy <-> SPIz**********************/ + //软件NSS，选中SPIz + SPI_NSSInternalSoftwareConfig(SPIz, SPI_NSSInternalSoft_Reset); + while (TxCounter < BufferSize) + { + //发送 + while (SPI_GetFlagStatus(SPIy, SPI_FLAG_TXE) == RESET); + SPI_SendData(SPIz, TxBuffer2[TxCounter]); + SPI_SendData(SPIy, TxBuffer1[TxCounter++]); + //接收 + while (SPI_GetFlagStatus(SPIz, SPI_FLAG_RXNE) == RESET); + RxBuffer2[RxCounter] = SPI_ReceiveData(SPIz); + while (SPI_GetFlagStatus(SPIy, SPI_FLAG_RXNE) == RESET); + RxBuffer1[RxCounter++] = SPI_ReceiveData(SPIy); + } + //释放SPIz + SPI_NSSInternalSoftwareConfig(SPIz, SPI_NSSInternalSoft_Set); + //检查收发数据一致性 + TransferStatus1 = Buffercmp(TxBuffer1, RxBuffer2, BufferSize); + TransferStatus2 = Buffercmp(TxBuffer2, RxBuffer1, BufferSize); + if (TransferStatus1 == PASSED && TransferStatus2 == PASSED) //PASSED + { + //LED1亮 + PB09_SETHIGH(); + } + else //FAILED + { + //LED2亮 + PB08_SETHIGH(); + } + while (1) + { + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 24MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV2); + //外设时钟使能 + RCC_AHBPeriphClk_Enable(SPIy_GPIO_CLK | SPIz_GPIO_CLK | RCC_AHB_PERIPH_GPIOB, ENABLE); + SPIy_APBClkENx(SPIy_CLK, ENABLE); + SPIz_APBClkENx(SPIz_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //SPI SCK MOSI MISO 复用 + SPIy_AF_SCK; + SPIy_AF_MISO; + SPIy_AF_MOSI; + SPIz_AF_SCK; + SPIz_AF_MISO; + SPIz_AF_MOSI; + //推挽输出 + GPIO_InitStructure.Pins = SPIy_SCK_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(SPIy_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.Pins = SPIy_MOSI_PIN; + GPIO_Init(SPIy_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.Pins = SPIz_MISO_PIN; + GPIO_Init(SPIz_GPIO, &GPIO_InitStructure); + //浮空输入 + GPIO_InitStructure.Pins = SPIz_SCK_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT; + GPIO_Init(SPIz_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.Pins = SPIz_MOSI_PIN; + GPIO_Init(SPIz_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.Pins = SPIy_MISO_PIN; + GPIO_Init(SPIy_GPIO, &GPIO_InitStructure); + //PB9 LED1 / PB8 LED2 + GPIO_InitStructure.Pins = GPIO_PIN_9 | GPIO_PIN_8; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + //LED灭 + PB09_SETLOW(); + PB08_SETLOW(); +} + +/** + * @brief 配置RCC 3Mbit/s + * + */ +void SPI_Configuration() +{ + SPI_InitTypeDef SPI_InitStructure; + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; // 双线全双工 + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; // 主机模式 + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; // 帧数据长度为8bit + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; // 时钟空闲电平为低 + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; // 第一个边沿采样 + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; // 片选信号由SSI寄存器控制 + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8; // 波特率为PCLK的8分频 + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; // 最高有效位 MSB 收发在前 + SPI_InitStructure.SPI_Speed = SPI_Speed_Low; // 低速SPI + SPI_Init(SPIy, &SPI_InitStructure); + SPI_InitStructure.SPI_Mode = SPI_Mode_Slave; // 从机模式 + SPI_Init(SPIz, &SPI_InitStructure); + SPI_Cmd(SPIy, ENABLE); + SPI_Cmd(SPIz, ENABLE); +} + +/** + * @brief Compares two buffers + * + * @param pBuffer1 :buffers to be compared + * @param pBuffer2 :buffers to be compared + * @param BufferLength :buffer's length + * @return TestStatus + * @arg PASSED: pBuffer1 identical to pBuffer2 + * @arg FAILED: pBuffer1 differs from pBuffer2 + */ +TestStatus Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + pBuffer1++; + pBuffer2++; + } + return PASSED; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/readme.txt new file mode 100644 index 0000000..3803144 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_FullDuplex_ComPolling/readme.txt @@ -0,0 +1,36 @@ +示例目的： + SPI全双工模式主从通信（查询方式）。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟2分频，24MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=24MHz + 4. SPI，波特率为PCLK的8分频，3Mbps + 5. PB09（LED1）设置为PUSH-PULL输出 + 6. PB08（LED2）设置为PUSH-PULL输出 + + +演示说明： + SPIz（从机）将TxBuffer2缓冲区中的数据写入DR寄存器， + SPIy（主机）将TxBuffer1缓冲区中的数据写入DR寄存器，启动传输。 + 传输完成后，SPIz读取DR寄存器并存储到RxBuffer2缓冲区，SPIy读取DR寄存器并存储到RxBuffer1缓冲区。 + 比较TxBuffer1和RxBuffer2、TxBuffer2和RxBuffer1， + 如果数据一致，LED1亮，否则LED2亮。 + +硬件连接： + SPIy_SCK (PA10) -- SPIz_SCK (PB13) + SPIy_MISO (PA11) -- SPIz_MISO (PB14) + SPIy_MOSI (PA12) -- SPIz_MOSI (PB15) + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/EWARM/Project.ewd new file mode 100644 index 0000000..800c43b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 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$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/EWARM/Project.ewp new file mode 100644 index 0000000..5ed80c5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/EWARM/Project.ewp @@ -0,0 +1,2157 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_spi.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/MDK/Project.uvoptx new file mode 100644 index 0000000..99e7bbf --- /dev/null +++ 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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=2171,217,2582,719,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + TxCounter + + + 1 + 1 + RxCounter + + + 2 + 1 + TxBuffer + + + 3 + 1 + RxBuffer + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_spi.c + cw32f030_spi.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/MDK/Project.uvprojx new file mode 100644 index 0000000..286cd00 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/MDK/Project.uvprojx @@ -0,0 +1,461 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_spi.c + 1 + ..\..\..\..\Libraries\src\cw32f030_spi.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/USER/inc/main.h new file mode 100644 index 0000000..df18f62 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/USER/inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_spi.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..3e2eab4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/USER/src/interrupts_cw32f030.c @@ -0,0 +1,422 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +#define BufferSize 42 +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +extern uint8_t TxCounter, RxCounter; +extern uint8_t TxBuffer[], RxBuffer[]; +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + if (SPI_GetITStatus(CW_SPI1, SPI_IT_TXE) != RESET) + { + if (TxCounter == BufferSize - 1) + { + SPI_ITConfig(CW_SPI1, SPI_IT_TXE, DISABLE); + } + SPI_SendData(CW_SPI1, TxBuffer[TxCounter++]); + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + if (SPI_GetITStatus(CW_SPI2, SPI_IT_RXNE) != RESET) + { + RxBuffer[RxCounter++] = SPI_ReceiveData(CW_SPI2); + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/USER/src/main.c new file mode 100644 index 0000000..89e66c7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/USER/src/main.c @@ -0,0 +1,266 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//SPIy MASTER +#define SPIy CW_SPI1 +#define SPIy_CLK RCC_APB2_PERIPH_SPI1 +#define SPIy_APBClkENx RCC_APBPeriphClk_Enable2 + +//SPIy GPIO +#define SPIy_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define SPIy_GPIO CW_GPIOA +#define SPIy_SCK_PIN GPIO_PIN_10 +#define SPIy_MOSI_PIN GPIO_PIN_12 +#define SPIy_AF_SCK PA10_AFx_SPI1SCK() +#define SPIy_AF_MOSI PA12_AFx_SPI1MOSI() + +//SPIz SLAVE +#define SPIz CW_SPI2 +#define SPIz_CLK RCC_APB1_PERIPH_SPI2 +#define SPIz_APBClkENx RCC_APBPeriphClk_Enable1 + +//SPIz GPIO +#define SPIz_GPIO_CLK RCC_AHB_PERIPH_GPIOB +#define SPIz_GPIO CW_GPIOB +#define SPIz_SCK_PIN GPIO_PIN_13 +#define SPIz_MOSI_PIN GPIO_PIN_15 +#define SPIz_AF_SCK PB13_AFx_SPI2SCK() +#define SPIz_AF_MOSI PB15_AFx_SPI2MOSI() + +//中断 +#define SPIy_IRQ SPI1_IRQn +#define SPIz_IRQ SPI2_IRQn + +#define BufferSize ARRAY_SZ(TxBuffer) +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void SPI_Configuration(void); +TestStatus Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxBuffer[] = {0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, + 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, + 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, + 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83, + 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A + }; +uint8_t RxBuffer[BufferSize]; +uint8_t TxCounter = 0, RxCounter = 0; +volatile TestStatus TransferStatus = FAILED; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置SPI + SPI_Configuration(); + //配置NVIC + NVIC_Configuration(); + //使能 SPIz RXNE 中断 + SPI_ITConfig(SPIz, SPI_IT_RXNE, ENABLE); + //软件NSS，选中SPIz + SPI_NSSInternalSoftwareConfig(SPIz, SPI_NSSInternalSoft_Reset); + //使能 SPIy TXE 中断 + SPI_ITConfig(SPIy, SPI_IT_TXE, ENABLE); + //等待收发完成 + while (RxCounter < BufferSize); + //释放SPIz + SPI_NSSInternalSoftwareConfig(SPIz, SPI_NSSInternalSoft_Set); + //检查收发数据一致性 + TransferStatus = Buffercmp(TxBuffer, RxBuffer, BufferSize); + if (TransferStatus == PASSED) //PASSED + { + //LED1亮 + PB09_SETHIGH(); + } + else //FAILED + { + //LED2亮 + PB08_SETHIGH(); + } + while (1) + { + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 24MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV2); + //外设时钟使能 + RCC_AHBPeriphClk_Enable(SPIy_GPIO_CLK | SPIz_GPIO_CLK | RCC_AHB_PERIPH_GPIOB, ENABLE); + SPIy_APBClkENx(SPIy_CLK, ENABLE); + SPIz_APBClkENx(SPIz_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //SPI SCK MOSI 复用 + SPIy_AF_SCK; + SPIy_AF_MOSI; + SPIz_AF_SCK; + SPIz_AF_MOSI; + //推挽输出 + GPIO_InitStructure.Pins = SPIy_SCK_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(SPIy_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.Pins = SPIy_MOSI_PIN; + GPIO_Init(SPIy_GPIO, &GPIO_InitStructure); + //浮空输入 + GPIO_InitStructure.Pins = SPIz_SCK_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT; + GPIO_Init(SPIz_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.Pins = SPIz_MOSI_PIN; + GPIO_Init(SPIz_GPIO, &GPIO_InitStructure); + //PB9 LED1 / PB8 LED2 + GPIO_InitStructure.Pins = GPIO_PIN_9 | GPIO_PIN_8; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + //LED灭 + PB09_SETLOW(); + PB08_SETLOW(); +} + +/** + * @brief 配置RCC 3Mbit/s + * + */ +void SPI_Configuration() +{ + SPI_InitTypeDef SPI_InitStructure; + SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_TxOnly; // 单工单发 + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; // 主机模式 + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; // 帧数据长度为8bit + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; // 时钟空闲电平为低 + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; // 第一个边沿采样 + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; // 片选信号由SSI寄存器控制 + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8; // 波特率为PCLK的8分频 + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; // 最高有效位 MSB 收发在前 + SPI_InitStructure.SPI_Speed = SPI_Speed_Low; // 低速SPI + SPI_Init(SPIy, &SPI_InitStructure); + SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_RxOnly; // 单工单收 + SPI_InitStructure.SPI_Mode = SPI_Mode_Slave; // 从机模式 + SPI_Init(SPIz, &SPI_InitStructure); + SPI_Cmd(SPIy, ENABLE); + SPI_Cmd(SPIz, ENABLE); +} + +/** + * @brief 配置NVIC + * + */ +void NVIC_Configuration(void) +{ + //优先级，无优先级分组 + NVIC_SetPriority(SPIy_IRQ, 1); + NVIC_SetPriority(SPIz_IRQ, 0); + //SPI中断使能 + NVIC_EnableIRQ(SPIy_IRQ); + NVIC_EnableIRQ(SPIz_IRQ); +} + +/** + * @brief Compares two buffers + * + * @param pBuffer1 :buffers to be compared + * @param pBuffer2 :buffers to be compared + * @param BufferLength :buffer's length + * @return TestStatus + * @arg PASSED: pBuffer1 identical to pBuffer2 + * @arg FAILED: pBuffer1 differs from pBuffer2 + */ +TestStatus Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + pBuffer1++; + pBuffer2++; + } + return PASSED; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/readme.txt new file mode 100644 index 0000000..8973af4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/SPI/SPI_Simplex_Interrupt/readme.txt @@ -0,0 +1,33 @@ +示例目的： + SPI单工模式主从通信（中断方式）。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟2分频，24MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=24MHz + 4. SPI，波特率为PCLK的8分频，3Mbps + 5. PB09（LED1）设置为PUSH-PULL输出 + 6. PB08（LED2）设置为PUSH-PULL输出 + +演示说明： + SPIy（主机）中断方式发送TxBuffer缓冲区中的数据。 + SPIz（从机）中断方式接收数据，并存储到RxBuffer缓冲区。 + 比较TxBuffer和RxBuffer， + 如果数据一致，LED1亮，否则LED2亮。 + +硬件连接： + SPIy_SCK (PA10) -- SPIz_SCK (PB13) + SPIy_MOSI (PA12) -- SPIz_MOSI (PB15) + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/EWARM/Project.ewd new file mode 100644 index 0000000..1b43b26 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/EWARM/Project.ewd @@ -0,0 +1,1456 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/EWARM/Project.ewp new file mode 100644 index 0000000..7860bf2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/EWARM/Project.ewp @@ -0,0 +1,2154 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + 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b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/MDK/Project.uvoptx new file mode 100644 index 0000000..749a76b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/MDK/Project.uvoptx @@ -0,0 +1,306 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/MDK/Project.uvprojx new file mode 100644 index 0000000..eea29ec --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/MDK/Project.uvprojx @@ -0,0 +1,455 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/USER/inc/main.h new file mode 100644 index 0000000..2f6160d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/USER/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/USER/readme.txt new file mode 100644 index 0000000..6d76c6e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/USER/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 演示普通GPIO口PA00的定时翻转。 + +硬件资源： + 1. CW32F030CxTx StarKit + 2. 时钟HSI + 3. 系统时钟默认为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + +演示说明： + 采用默认时钟配置，PA00配置为推挽输出，在主函数中每10ms对PA00的输出电平进行翻转，利用示波器观察PA00的波形情况。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开systick_delay.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/USER/src/main.c new file mode 100644 index 0000000..7287e0c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/Template/Template/USER/src/main.c @@ -0,0 +1,103 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle GPIOA.00 + ** + ******************************************************************************/ +int32_t main(void) +{ + CW_SYSCTRL->AHBEN_f.GPIOA = 1U; //Open GPIOA Clk + CW_GPIOA->ANALOG_f.PIN0 = 0U; //Digital + CW_GPIOA->BRR_f.BRR0 = 1U; //Reset PA00 + CW_GPIOA->DIR_f.PIN0 = 0U; //Output + while (1) + { + CW_GPIOA->TOG = bv0; + FirmwareDelay(10000); + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/EWARM/Project.ewd new file mode 100644 index 0000000..800c43b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 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$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/EWARM/Project.ewp new file mode 100644 index 0000000..66e631a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/EWARM/Project.ewp @@ -0,0 +1,2160 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gtim.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/MDK/Project.uvoptx new file mode 100644 index 0000000..a4f8584 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/MDK/Project.uvoptx @@ -0,0 +1,351 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=943,140,1354,642,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\UART1 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + cw32f030_gtim.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/MDK/Project.uvprojx new file mode 100644 index 0000000..34924ad --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/MDK/Project.uvprojx @@ -0,0 +1,483 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + gpio_input_output + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + cw32f030_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gtim.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/USER/inc/main.h new file mode 100644 index 0000000..ecb7322 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_uart.h" +#include "cw32f030_gtim.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..1499906 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/USER/src/interrupts_cw32f030.c @@ -0,0 +1,414 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + uint8_t TxRxBuffer; + if (USART_GetITStatus(CW_UART1, USART_IT_RC) != RESET) + { + USART_ClearITPendingBit(CW_UART1, USART_IT_RC); + TxRxBuffer = USART_ReceiveData_8bit(CW_UART1); + USART_SendData_8bit(CW_UART1, TxRxBuffer); + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/USER/src/main.c new file mode 100644 index 0000000..65dc757 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/USER/src/main.c @@ -0,0 +1,276 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTx +#define DEBUG_USARTx CW_UART1 +#define DEBUG_USART_CLK RCC_APB2_PERIPH_UART1 +#define DEBUG_USART_APBClkENx RCC_APBPeriphClk_Enable2 +#define DEBUG_USART_BaudRate 9600 +#define DEBUG_USART_UclkFreq 8000000 + +//UARTx GPIO +#define DEBUG_USART_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define DEBUG_USART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_USART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_RX_GPIO_PIN GPIO_PIN_9 + +//GPIO AF +#define DEBUG_USART_AFTX PA08_AFx_UART1TXD() +#define DEBUG_USART_AFRX PA09_AFx_UART1RXD() + +//中断 +#define DEBUG_USART_IRQ UART1_IRQn + +//GTIM +#define DEBUG_GTIMx CW_GTIM1 +#define DEBUG_GTIM_CLK RCC_APB1_PERIPH_GTIM1 +#define DEBUG_GTIM_APBClkENx RCC_APBPeriphClk_Enable1 +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); +void GTIM_Configuration(void); +void NVIC_Configuration(void); +void USART_SendString(UART_TypeDef *USARTx, char *String); +void AutoBaudRate(UART_TypeDef *USARTx, GTIM_TypeDef *GTIMx); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置UART + UART_Configuration(); + //配置GTIM + GTIM_Configuration(); + //配置NVIC + NVIC_Configuration(); + //使能UARTx RC中断 + USART_ITConfig(DEBUG_USARTx, USART_IT_RC, ENABLE); + USART_SendString(DEBUG_USARTx, "\r\nCW32F030 UART AutoBaudRate\r\n"); + USART_SendString(DEBUG_USARTx, "\r\nPC发送以0xF8作为数据头的数据流\r\n"); + //自动波特率检测 + AutoBaudRate(DEBUG_USARTx, DEBUG_GTIMx); + while (1) + { + //中断收发 + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 8MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + //外设时钟使能 + RCC_AHBPeriphClk_Enable(DEBUG_USART_GPIO_CLK, ENABLE); + DEBUG_USART_APBClkENx(DEBUG_USART_CLK, ENABLE); + DEBUG_GTIM_APBClkENx(DEBUG_GTIM_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //UART TX RX 复用 + DEBUG_USART_AFTX; + DEBUG_USART_AFRX; + GPIO_InitStructure.IT = GPIO_IT_NONE; + GPIO_InitStructure.Pins = DEBUG_USART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = DEBUG_USART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStructure); +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + USART_InitTypeDef USART_InitStructure; + USART_InitStructure.USART_BaudRate = DEBUG_USART_BaudRate; + USART_InitStructure.USART_Over = USART_Over_16; + USART_InitStructure.USART_Source = USART_Source_PCLK; + USART_InitStructure.USART_UclkFreq = DEBUG_USART_UclkFreq; + USART_InitStructure.USART_StartBit = USART_StartBit_FE; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(DEBUG_USARTx, &USART_InitStructure); +} + +/** + * @brief 配置GTIM + * + */ +void GTIM_Configuration(void) +{ + GTIM_InitTypeDef GTIM_InitStructure; + GTIM_InitStructure.Mode = GTIM_MODE_GATE; //门控模式 + GTIM_InitStructure.OneShotMode = GTIM_COUNT_CONTINUE; + GTIM_InitStructure.Prescaler = GTIM_PRESCALER_DIV1; //PCLK计数 + GTIM_InitStructure.ReloadValue = 0xFFFF; + GTIM_InitStructure.ToggleOutState = DISABLE; + GTIM_TimeBaseInit(DEBUG_GTIMx, >IM_InitStructure); + //ETR来源为DEBUG_USARTx的RXD信号 + CW_SYSCTRL->GTIMETR_f.GTIM1ETR = 1; + //ETR极性及滤波器：低电平、无滤波 + GTIM_ETRConfig(DEBUG_GTIMx, GTIM_ETR_POL_FALL_LOW, GTIM_ETR_FILTER_NONE); +} + +/** + * @brief 配置NVIC + * + */ +void NVIC_Configuration(void) +{ + //优先级，无优先级分组 + NVIC_SetPriority(DEBUG_USART_IRQ, 0); + //UARTx中断使能 + NVIC_EnableIRQ(DEBUG_USART_IRQ); +} + +/** + * @brief 发送字符串 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param String :待发送的字符串 + */ +void USART_SendString(UART_TypeDef *USARTx, char *String) +{ + while (*String != '\0') + { + USART_SendData_8bit(USARTx, *String); + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXE) == RESET); + String++; + } + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXBUSY) == SET); +} + +/** + * @brief 自动波特率检测 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @note + * -16倍采样 + * -GTIMx.CNT未作溢出处理 + */ +void AutoBaudRate(UART_TypeDef *USARTx, GTIM_TypeDef *GTIMx) +{ + uint32_t temp; + //失能RXEN + USARTx->CR1_f.RXEN = 0; + //使能RXD上升沿中断 + REGBITS_SET(DEBUG_USART_RX_GPIO_PORT->RISEIE, DEBUG_USART_RX_GPIO_PIN); + //开启GTIM + GTIMx->CR0_f.EN = 1; + while (REGBITS_GET(DEBUG_USART_RX_GPIO_PORT->ISR, DEBUG_USART_RX_GPIO_PIN) == RESET); + //失能RXD上升沿中断 + REGBITS_CLR(DEBUG_USART_RX_GPIO_PORT->RISEIE, DEBUG_USART_RX_GPIO_PIN); + //关闭GTIM + GTIMx->CR0_f.EN = 0; + //清除中断标志 + REGBITS_CLR(DEBUG_USART_RX_GPIO_PORT->ICR, DEBUG_USART_RX_GPIO_PIN); + //计算BRRI、BRRF + temp = ((GTIMx->CNT) + 2) / 4; + USARTx->BRRI = (uint16_t)(temp >> 4); + USARTx->BRRF = (uint16_t)(temp & 0x0F); + //使能RXEN + USARTx->CR1_f.RXEN = 1; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/readme.txt new file mode 100644 index 0000000..3f4ed6e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_AutoBaudRate/readme.txt @@ -0,0 +1,30 @@ +示例目的： + UART自动波特率检测。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟6分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为PCLK + 5. GTIM的时钟为PCLK + +演示说明： + PC（主机）发送以0xF8作为数据头的数据流，UART从机等待从主机接收数据， + 然后开始自动波特率检测，更新波特率设置，并回传接收到的数据至PC。 + +硬件连接： + UART1_TXD (PA08) -- PC_RX + UART1_RXD (PA09) -- PC_TX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/EWARM/Project.ewd new file mode 100644 index 0000000..800c43b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/EWARM/Project.ewp new file mode 100644 index 0000000..247be59 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/EWARM/Project.ewp @@ -0,0 +1,2163 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 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+ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/MDK/Project.uvoptx new file mode 100644 index 0000000..e7b3497 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/MDK/Project.uvoptx @@ -0,0 +1,370 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + TxRxBuffer + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\DMA + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_dma.c + cw32f030_dma.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_systick.c + cw32f030_systick.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/MDK/Project.uvprojx new file mode 100644 index 0000000..69ad435 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/MDK/Project.uvprojx @@ -0,0 +1,471 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + gpio_input_output + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + cw32f030_dma.c + 1 + ..\..\..\..\Libraries\src\cw32f030_dma.c + + + cw32f030_systick.c + 1 + ..\..\..\..\Libraries\src\cw32f030_systick.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/USER/inc/main.h new file mode 100644 index 0000000..4c1b829 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/USER/inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_uart.h" +#include "cw32f030_dma.h" +#include "cw32f030_systick.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/USER/src/main.c new file mode 100644 index 0000000..c5db0be --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/USER/src/main.c @@ -0,0 +1,255 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//HCLK for SysTick +#define HCLKFREQ 8000000 +//UARTx +#define DEBUG_USARTx CW_UART1 +#define DEBUG_USART_CLK RCC_APB2_PERIPH_UART1 +#define DEBUG_USART_APBClkENx RCC_APBPeriphClk_Enable2 +#define DEBUG_USART_BaudRate 9600 +#define DEBUG_USART_UclkFreq 8000000 + +//UARTx GPIO +#define DEBUG_USART_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define DEBUG_USART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_USART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_RX_GPIO_PIN GPIO_PIN_9 + +//GPIO AF +#define DEBUG_USART_AFTX PA08_AFx_UART1TXD() +#define DEBUG_USART_AFRX PA09_AFx_UART1RXD() + +//DMA +#define DEBUG_USART_TX_DMA CW_DMACHANNEL2 +#define DEBUG_USART_RX_DMA CW_DMACHANNEL1 +#define DEBUG_USART_TxTrigSource DMA_HardTrig_UART1_TXBufferE +#define DEBUG_USART_RxTrigSource DMA_HardTrig_UART1_RXBufferNE +#define DEBUG_DMA_BUFFSIZE 5000 +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); +void DMA_Configuration(void); +void USART_SendString(UART_TypeDef *USARTx, char *String); +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxRxBuffer[DEBUG_DMA_BUFFSIZE]; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置UART + UART_Configuration(); + //配置DMA + DMA_Configuration(); + //初始化SysTick + InitTick(HCLKFREQ); + USART_SendString(DEBUG_USARTx, "\r\nCW32F030 UART DMA Transmission\r\n"); + //填充TxRxBuffer + for (int i = 0; i < DEBUG_DMA_BUFFSIZE; i++) + { + TxRxBuffer[i] = i; + } + //使能UART DMA TXD + USART_DMACmd(DEBUG_USARTx, USART_DMAReq_Tx, ENABLE); + while (1) + { + //CPU空闲，LED1闪烁 + PB09_TOG(); + SysTickDelay(500); + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 8MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + //外设时钟使能 + RCC_AHBPeriphClk_Enable(DEBUG_USART_GPIO_CLK | RCC_AHB_PERIPH_DMA | RCC_AHB_PERIPH_GPIOB, ENABLE); + DEBUG_USART_APBClkENx(DEBUG_USART_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //UART TX RX 复用 + DEBUG_USART_AFTX; + DEBUG_USART_AFRX; + GPIO_InitStructure.Pins = DEBUG_USART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = DEBUG_USART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStructure); + //PB9 LED1 + GPIO_InitStructure.Pins = GPIO_PIN_9; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + USART_InitTypeDef USART_InitStructure; + USART_InitStructure.USART_BaudRate = DEBUG_USART_BaudRate; + USART_InitStructure.USART_Over = USART_Over_16; + USART_InitStructure.USART_Source = USART_Source_PCLK; + USART_InitStructure.USART_UclkFreq = DEBUG_USART_UclkFreq; + USART_InitStructure.USART_StartBit = USART_StartBit_FE; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(DEBUG_USARTx, &USART_InitStructure); +} + +/** + * @brief 配置DMA + * + */ +void DMA_Configuration(void) +{ + DMA_InitTypeDef DMA_InitStructure; + //初始化DMA TX + DMA_InitStructure.DMA_Mode = DMA_MODE_BLOCK; + DMA_InitStructure.DMA_TransferWidth = DMA_TRANSFER_WIDTH_8BIT; + DMA_InitStructure.DMA_SrcInc = DMA_SrcAddress_Increase; + DMA_InitStructure.DMA_DstInc = DMA_DstAddress_Fix; + DMA_InitStructure.TrigMode = DMA_HardTrig; + DMA_InitStructure.HardTrigSource = DEBUG_USART_TxTrigSource; + DMA_InitStructure.DMA_TransferCnt = DEBUG_DMA_BUFFSIZE; + DMA_InitStructure.DMA_SrcAddress = (uint32_t)TxRxBuffer; + DMA_InitStructure.DMA_DstAddress = (uint32_t)&DEBUG_USARTx->TDR; + DMA_Init(DEBUG_USART_TX_DMA, &DMA_InitStructure); + DMA_Cmd(DEBUG_USART_TX_DMA, ENABLE); + // //初始化DMA RX + // DMA_InitStructure.DMA_Mode = DMA_MODE_BLOCK; + // DMA_InitStructure.DMA_TransferWidth = DMA_TRANSFER_WIDTH_8BIT; + // DMA_InitStructure.DMA_SrcInc = DMA_SrcAddress_Fix; + // DMA_InitStructure.DMA_DstInc = DMA_DstAddress_Increase; + // DMA_InitStructure.TrigMode = DMA_HardTrig; + // DMA_InitStructure.HardTrigSource = DEBUG_USART_RxTrigSource; + // DMA_InitStructure.DMA_TransferCnt = DEBUG_DMA_BUFFSIZE; + // DMA_InitStructure.DMA_SrcAddress = (uint32_t)&DEBUG_USARTx->RDR; + // DMA_InitStructure.DMA_DstAddress = (uint32_t)TxRxBuffer; + // DMA_Init(DEBUG_USART_RX_DMA, &DMA_InitStructure); + // DMA_Cmd(DEBUG_USART_RX_DMA, ENABLE); +} + +/** + * @brief 发送字符串 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param String :待发送的字符串 + */ +void USART_SendString(UART_TypeDef *USARTx, char *String) +{ + while (*String != '\0') + { + USART_SendData_8bit(USARTx, *String); + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXE) == RESET); + String++; + } + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXBUSY) == SET); +} + +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn */ + uwTick += uwTickFreq; + /* USER CODE END SysTick_IRQn */ +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/readme.txt new file mode 100644 index 0000000..fbfe63f --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DMA/readme.txt @@ -0,0 +1,32 @@ +示例目的： + UART通过DMA发送数据示例。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟6分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为PCLK + 5. DMA，硬件触发 BLOCK 传输模式 + 6. PB09（LED1）设置为PUSH-PULL输出 + +演示说明： + 通过for循环初始化TxRxBuffer缓冲区， + UART通过DMA发送TxRxBuffer缓冲区中的数据至串口调试助手，无需CPU的干预， + 此时，LED1同时闪烁。 + +硬件连接： + UART1_TXD (PA08) -- PC_RX + UART1_RXD (PA09) -- PC_TX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/EWARM/Project.ewd new file mode 100644 index 0000000..800c43b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/EWARM/Project.ewp new file mode 100644 index 0000000..6da552c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/EWARM/Project.ewp @@ -0,0 +1,2163 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + 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+ $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_pwr.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/MDK/Project.uvoptx new file mode 100644 index 0000000..0825067 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/MDK/Project.uvoptx @@ -0,0 +1,387 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=2308,181,2719,683,1)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + DLGUARM + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=105,137,292,353,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + TxRxBufferSize + + + 1 + 1 + TxRxBuffer + + + + + 1 + 0 + 0x40010030 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_systick.c + cw32f030_systick.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_pwr.c + cw32f030_pwr.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/MDK/Project.uvprojx new file mode 100644 index 0000000..7e9a138 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/MDK/Project.uvprojx @@ -0,0 +1,471 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + cw32f030_systick.c + 1 + ..\..\..\..\Libraries\src\cw32f030_systick.c + + + cw32f030_pwr.c + 1 + ..\..\..\..\Libraries\src\cw32f030_pwr.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/USER/inc/main.h new file mode 100644 index 0000000..1e7f28e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/USER/inc/main.h @@ -0,0 +1,74 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_systick.h" +#include "cw32f030_uart.h" +#include "cw32f030_pwr.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..1de1bf1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/USER/src/interrupts_cw32f030.c @@ -0,0 +1,408 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + USART_ClearITPendingBit(CW_UART1, USART_IT_RC); + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/USER/src/main.c new file mode 100644 index 0000000..33c3a9a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/USER/src/main.c @@ -0,0 +1,321 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//HCLK for SysTick +#define HCLKFREQ 8000000 +//UARTx +#define DEBUG_USARTx CW_UART1 +#define DEBUG_USART_CLK RCC_APB2_PERIPH_UART1 +#define DEBUG_USART_APBClkENx RCC_APBPeriphClk_Enable2 +#define DEBUG_USART_BaudRate 9600 +#define DEBUG_USART_UclkFreq 32800 + +//UARTx GPIO +#define DEBUG_USART_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define DEBUG_USART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_USART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_RX_GPIO_PIN GPIO_PIN_9 + +//GPIO AF +#define DEBUG_USART_AFTX PA08_AFx_UART1TXD() +#define DEBUG_USART_AFRX PA09_AFx_UART1RXD() + +//中断 +#define DEBUG_USART_IRQ UART1_IRQn + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); +void PWR_Configuration(void); +void NVIC_Configuration(void); +void USART_SendString(UART_TypeDef *USARTx, char *String); +void USART_SendBuf_Polling(UART_TypeDef *USARTx, uint8_t *TxBuf, uint8_t TxCnt); +uint8_t USART_RecvBuf_Polling(UART_TypeDef *USARTx, uint8_t *RxBuf); +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxRxBufferSize; +uint8_t TxRxBuffer[300]; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置UART + UART_Configuration(); + //配置低功耗模式 + PWR_Configuration(); + //配置NVIC + NVIC_Configuration(); + //初始化SysTick + InitTick(HCLKFREQ); + //DeepSleep唤醒时，保持原系统时钟来源 + RCC_WAKEUPCLK_Config(RCC_SYSCTRL_WAKEUPCLKDIS); + USART_SendString(DEBUG_USARTx, "\r\nCW32F030 UART DeepSleep mode LSE/LSI\r\n"); + while (1) + { + //进入深度休眠模式 + USART_SendString(DEBUG_USARTx, "\r\nEnter DeepSleep mode\r\n"); + USART_SendString(DEBUG_USARTx, "\r\nPC send data to wake up MCU\r\n"); + //使能UARTx RC中断 + USART_ITConfig(DEBUG_USARTx, USART_IT_RC, ENABLE); + PWR_GotoLpmMode(); + //失能UARTx RC中断 + USART_ITConfig(CW_UART1, USART_IT_RC, DISABLE); + //唤醒后轮询收发 + TxRxBufferSize = USART_RecvBuf_Polling(DEBUG_USARTx, TxRxBuffer); + USART_SendBuf_Polling(DEBUG_USARTx, TxRxBuffer, TxRxBufferSize); + //闪灯 + for (int i = 0; i < 10; i++) + { + PB09_TOG(); + SysTickDelay(500); + } + } +} + +/** + * @brief 外设时钟使能 + * + */ +void RCC_Configuration(void) +{ + //复位后延时 + InitTick(8000000); + SysTickDelay(1000); + //SYSCLK = HSI = 8MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + RCC_LSI_Enable(); + //外设时钟使能 + RCC_AHBPeriphClk_Enable(DEBUG_USART_GPIO_CLK | RCC_AHB_PERIPH_GPIOB, ENABLE); + DEBUG_USART_APBClkENx(DEBUG_USART_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //UART TX RX 复用 + DEBUG_USART_AFTX; + DEBUG_USART_AFRX; + GPIO_InitStructure.Pins = DEBUG_USART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = DEBUG_USART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStructure); + //PB9 LED1 + GPIO_InitStructure.Pins = GPIO_PIN_9; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + PB09_SETLOW(); +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + USART_InitTypeDef USART_InitStructure; + USART_InitStructure.USART_BaudRate = DEBUG_USART_BaudRate; + USART_InitStructure.USART_Over = USART_Over_sp; //专用采样 + USART_InitStructure.USART_Source = USART_Source_LSI; //传输时钟 UCLK = LSI + USART_InitStructure.USART_UclkFreq = DEBUG_USART_UclkFreq; + USART_InitStructure.USART_StartBit = USART_StartBit_FE; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(DEBUG_USARTx, &USART_InitStructure); +} + +/** + * @brief 配置低功耗模式 + * + */ +void PWR_Configuration(void) +{ + PWR_InitTypeDef PWR_InitStructure; + PWR_InitStructure.PWR_Sevonpend = PWR_Sevonpend_Disable; + PWR_InitStructure.PWR_SleepDeep = PWR_SleepDeep_Enable; //Deep Sleep + PWR_InitStructure.PWR_SleepOnExit = PWR_SleepOnExit_Disable; + PWR_Config(&PWR_InitStructure); +} + +/** + * @brief 配置NVIC + * + */ +void NVIC_Configuration(void) +{ + //优先级，无优先级分组 + NVIC_SetPriority(DEBUG_USART_IRQ, 0); + //UARTx中断使能 + NVIC_EnableIRQ(DEBUG_USART_IRQ); +} + +/** + * @brief 发送字符串 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param String :待发送的字符串 + */ +void USART_SendString(UART_TypeDef *USARTx, char *String) +{ + while (*String != '\0') + { + USART_SendData_8bit(USARTx, *String); + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXE) == RESET); + String++; + } + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXBUSY) == SET); +} + +/** + * @brief 发送8位数组 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param TxBuf :待发送的数组 + * @param TxCnt :待发送的数组元素个数 + */ +void USART_SendBuf_Polling(UART_TypeDef *USARTx, uint8_t *TxBuf, uint8_t TxCnt) +{ + while (TxCnt) + { + USART_SendData_8bit(USARTx, *TxBuf); + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXE) == RESET); + TxBuf++; + TxCnt--; + } + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXBUSY) == SET); +} + +/** + * @brief 接收8位数组 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param RxBuf :接收Buf + * @return uint8_t :接收的字符个数 + */ +uint8_t USART_RecvBuf_Polling(UART_TypeDef *USARTx, uint8_t *RxBuf) +{ + uint8_t RxCnt = 0; + RxBuf[RxCnt] = USART_ReceiveData_8bit(USARTx); + RxCnt++; + do + { + //等待RC + while (USART_GetFlagStatus(USARTx, USART_FLAG_RC) == RESET); + //清RC + USART_ClearFlag(USARTx, USART_FLAG_RC); + //ERROR: PE or FE + if (USART_GetFlagStatus(USARTx, USART_FLAG_PE | USART_FLAG_FE)) + { + USART_ClearFlag(USARTx, USART_FLAG_PE | USART_FLAG_FE); + RxCnt = 0x00; + } + else + { + RxBuf[RxCnt] = USART_ReceiveData_8bit(USARTx); + RxCnt++; + } + } + while (RxBuf[RxCnt - 1] != '\n'); + return RxCnt; +} + +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn */ + uwTick += uwTickFreq; + /* USER CODE END SysTick_IRQn */ +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/readme.txt new file mode 100644 index 0000000..908c59b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_LSELSI/readme.txt @@ -0,0 +1,32 @@ +示例目的： + UART深度休眠模式示例（传输时钟为LSI）。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟6分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为LSI + 5. PB09（LED1）设置为PUSH-PULL输出 + +演示说明： + 程序启动一段时间后进入深度休眠模式， + PC发送数据可唤醒MCU，唤醒后UART轮询接收数据，并存储到TxRxBuffer缓冲区， + UART接收到'\n'后不再接收数据，然后将TxRxBuffer缓冲区中的数据回传至PC。 + 传输结束后，LED1闪烁5s，并再次进入深度休眠模式。 + +硬件连接： + UART1_TXD (PA08) -- PC_RX + UART1_RXD (PA09) -- PC_TX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/EWARM/Project.ewd new file mode 100644 index 0000000..800c43b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 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+ $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_pwr.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/MDK/Project.uvoptx new file mode 100644 index 0000000..7c2a5d5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/MDK/Project.uvoptx @@ -0,0 +1,393 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=1006,209,1417,711,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + DLGUARM + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=105,137,292,353,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + TxRxBufferSize + + + 1 + 1 + TxRxBuffer + + + + + 1 + 0 + 0x40010030 + 0 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\GPIOB + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_systick.c + cw32f030_systick.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_pwr.c + cw32f030_pwr.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/MDK/Project.uvprojx new file mode 100644 index 0000000..7e9a138 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/MDK/Project.uvprojx @@ -0,0 +1,471 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + cw32f030_systick.c + 1 + ..\..\..\..\Libraries\src\cw32f030_systick.c + + + cw32f030_pwr.c + 1 + ..\..\..\..\Libraries\src\cw32f030_pwr.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/USER/inc/main.h new file mode 100644 index 0000000..1e7f28e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/USER/inc/main.h @@ -0,0 +1,74 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_systick.h" +#include "cw32f030_uart.h" +#include "cw32f030_pwr.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b814657 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/USER/src/interrupts_cw32f030.c @@ -0,0 +1,409 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + REGBITS_CLR(CW_GPIOA->ICR, GPIO_PIN_9); + USART_ClearITPendingBit(CW_UART1, USART_IT_RC); + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/USER/src/main.c new file mode 100644 index 0000000..dd940f6 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/USER/src/main.c @@ -0,0 +1,317 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//HCLK for SysTick +#define HCLKFREQ 8000000 +//UARTx +#define DEBUG_USARTx CW_UART1 +#define DEBUG_USART_CLK RCC_APB2_PERIPH_UART1 +#define DEBUG_USART_APBClkENx RCC_APBPeriphClk_Enable2 +#define DEBUG_USART_BaudRate 9600 +#define DEBUG_USART_UclkFreq 8000000 + +//UARTx GPIO +#define DEBUG_USART_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define DEBUG_USART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_USART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_RX_GPIO_PIN GPIO_PIN_9 + +//GPIO AF +#define DEBUG_USART_AFTX PA08_AFx_UART1TXD() +#define DEBUG_USART_AFRX PA09_AFx_UART1RXD() + +//GPIO下降沿中断 +#define DEBUG_USART_RX_GPIO_IRQ GPIOA_IRQn + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); +void PWR_Configuration(void); +void NVIC_Configuration(void); +void USART_SendString(UART_TypeDef *USARTx, char *String); +void USART_SendBuf_Polling(UART_TypeDef *USARTx, uint8_t *TxBuf, uint8_t TxCnt); +uint8_t USART_RecvBuf_Polling(UART_TypeDef *USARTx, uint8_t *RxBuf); +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxRxBufferSize; +uint8_t TxRxBuffer[300]; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置UART + UART_Configuration(); + //配置低功耗模式 + PWR_Configuration(); + //配置NVIC + NVIC_Configuration(); + //初始化SysTick + InitTick(HCLKFREQ); + //DeepSleep唤醒时，保持原系统时钟来源 + RCC_WAKEUPCLK_Config(RCC_SYSCTRL_WAKEUPCLKDIS); + USART_SendString(DEBUG_USARTx, "\r\nCW32F030 UART DeepSleep mode PCLK\r\n"); + while (1) + { + //进入深度休眠模式 + USART_SendString(DEBUG_USARTx, "\r\nEnter DeepSleep mode\r\n"); + USART_SendString(DEBUG_USARTx, "\r\nPC send data to wake up MCU\r\n"); + //使能RXD下降沿中断 + REGBITS_SET(DEBUG_USART_RX_GPIO_PORT->FALLIE, DEBUG_USART_RX_GPIO_PIN); + PWR_GotoLpmMode(); + //失能RXD下降沿中断 + REGBITS_CLR(DEBUG_USART_RX_GPIO_PORT->FALLIE, DEBUG_USART_RX_GPIO_PIN); + //唤醒后轮询收发 + TxRxBufferSize = USART_RecvBuf_Polling(DEBUG_USARTx, TxRxBuffer); + USART_SendBuf_Polling(DEBUG_USARTx, TxRxBuffer, TxRxBufferSize); + //闪灯 + for (int i = 0; i < 10; i++) + { + PB09_TOG(); + SysTickDelay(500); + } + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //复位后延时 + InitTick(8000000); + SysTickDelay(1000); + //SYSCLK = HSI = 8MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + //外设时钟使能 + RCC_AHBPeriphClk_Enable(DEBUG_USART_GPIO_CLK | RCC_AHB_PERIPH_GPIOB, ENABLE); + DEBUG_USART_APBClkENx(DEBUG_USART_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //UART TX RX 复用 + DEBUG_USART_AFTX; + DEBUG_USART_AFRX; + GPIO_InitStructure.Pins = DEBUG_USART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = DEBUG_USART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStructure); + //PB9 LED1 + GPIO_InitStructure.Pins = GPIO_PIN_9; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + PB09_SETLOW(); +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + USART_InitTypeDef USART_InitStructure; + USART_InitStructure.USART_BaudRate = DEBUG_USART_BaudRate; + USART_InitStructure.USART_Over = USART_Over_16; + USART_InitStructure.USART_Source = USART_Source_PCLK; + USART_InitStructure.USART_UclkFreq = DEBUG_USART_UclkFreq; + USART_InitStructure.USART_StartBit = USART_StartBit_LL; //低电平 + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(DEBUG_USARTx, &USART_InitStructure); +} + +/** + * @brief 配置低功耗模式 + * + */ +void PWR_Configuration(void) +{ + PWR_InitTypeDef PWR_InitStructure; + PWR_InitStructure.PWR_Sevonpend = PWR_Sevonpend_Disable; + PWR_InitStructure.PWR_SleepDeep = PWR_SleepDeep_Enable; //Deep Sleep + PWR_InitStructure.PWR_SleepOnExit = PWR_SleepOnExit_Disable; + PWR_Config(&PWR_InitStructure); +} + +/** + * @brief 配置NVIC + * + */ +void NVIC_Configuration(void) +{ + //优先级，无优先级分组 + NVIC_SetPriority(DEBUG_USART_RX_GPIO_IRQ, 0); + //GPIO RXD中断使能 + NVIC_EnableIRQ(DEBUG_USART_RX_GPIO_IRQ); +} + +/** + * @brief 发送字符串 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param String :待发送的字符串 + */ +void USART_SendString(UART_TypeDef *USARTx, char *String) +{ + while (*String != '\0') + { + USART_SendData_8bit(USARTx, *String); + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXE) == RESET); + String++; + } + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXBUSY) == SET); +} + +/** + * @brief 发送8位数组 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param TxBuf :待发送的数组 + * @param TxCnt :待发送的数组元素个数 + */ +void USART_SendBuf_Polling(UART_TypeDef *USARTx, uint8_t *TxBuf, uint8_t TxCnt) +{ + while (TxCnt) + { + USART_SendData_8bit(USARTx, *TxBuf); + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXE) == RESET); + TxBuf++; + TxCnt--; + } + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXBUSY) == SET); +} + +/** + * @brief 接收8位数组 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param RxBuf :接收Buf + * @return uint8_t :接收的字符个数 + */ +uint8_t USART_RecvBuf_Polling(UART_TypeDef *USARTx, uint8_t *RxBuf) +{ + uint8_t RxCnt = 0; + do + { + //等待RC + while (USART_GetFlagStatus(USARTx, USART_FLAG_RC) == RESET); + //清RC + USART_ClearFlag(USARTx, USART_FLAG_RC); + //ERROR: PE or FE + if (USART_GetFlagStatus(USARTx, USART_FLAG_PE | USART_FLAG_FE)) + { + USART_ClearFlag(USARTx, USART_FLAG_PE | USART_FLAG_FE); + RxCnt = 0x00; + } + else + { + RxBuf[RxCnt] = USART_ReceiveData_8bit(USARTx); + RxCnt++; + } + } + while (RxBuf[RxCnt - 1] != '\n'); + return RxCnt; +} + +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn */ + uwTick += uwTickFreq; + /* USER CODE END SysTick_IRQn */ +} +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/readme.txt new file mode 100644 index 0000000..33bbaa9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_DeepSleep_PCLK/readme.txt @@ -0,0 +1,33 @@ +示例目的： + UART深度休眠模式示例（传输时钟为PCLK）。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟6分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为PCLK + 5. PB09（LED1）设置为PUSH-PULL输出 + 6. UART1_RXD(PA09)下降沿中断 + +演示说明： + 程序启动一段时间后进入深度休眠模式， + PC发送数据可唤醒MCU，唤醒后UART轮询接收数据，并存储到TxRxBuffer缓冲区， + UART接收到'\n'后不再接收数据，然后将TxRxBuffer缓冲区中的数据回传至PC。 + 传输结束后，LED1闪烁5s，并再次进入深度休眠模式。 + +硬件连接： + UART1_TXD (PA08) -- PC_RX + UART1_RXD (PA09) -- PC_TX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/EWARM/Project.ewd new file mode 100644 index 0000000..800c43b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + 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a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/MDK/Project.uvoptx new file mode 100644 index 0000000..ef5ad6e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/MDK/Project.uvoptx @@ -0,0 +1,400 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=1441,104,1852,606,0)(1007=1760,222,1967,443,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + DLGUARM + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=105,137,292,353,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + RxBuffer1 + + + 1 + 1 + RxBuffer2 + + + 2 + 1 + TransferStatus1 + + + 3 + 1 + TransferStatus2 + + + 4 + 1 + TxBuffer1 + + + 5 + 1 + TxBuffer2 + + + 6 + 1 + NbrOfDataToRead2 + + + 7 + 1 + NbrOfDataToRead1 + + + + + 0 + 2 + TxBuffer1 + + + + + 1 + 0 + 0x40010030 + 0 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/MDK/Project.uvprojx new file mode 100644 index 0000000..889ad87 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/MDK/Project.uvprojx @@ -0,0 +1,478 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/USER/inc/main.h new file mode 100644 index 0000000..e088fbf --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_uart.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/USER/src/main.c new file mode 100644 index 0000000..42dc864 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/USER/src/main.c @@ -0,0 +1,262 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTy +#define USARTy CW_UART1 +#define USARTy_CLK RCC_APB2_PERIPH_UART1 +#define USARTy_APBClkENx RCC_APBPeriphClk_Enable2 + +#define USARTy_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define USARTy_GPIO CW_GPIOA +#define USARTy_TxPin GPIO_PIN_8 +#define USARTy_AFTX PA08_AFx_UART1TXD() +#define USARTy_TXPUR PA08_PUR_ENABLE(); + +//UARTz +#define USARTz CW_UART2 +#define USARTz_CLK RCC_APB1_PERIPH_UART2 +#define USARTz_APBClkENx RCC_APBPeriphClk_Enable1 + +#define USARTz_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define USARTz_GPIO CW_GPIOA +#define USARTz_TxPin GPIO_PIN_6 +#define USARTz_AFTX PA06_AFx_UART2TXD() +#define USARTz_TXPUR PA06_PUR_ENABLE() + +#define USARTyz_BaudRate 9600 +#define USARTyz_UclkFreq 8000000 + +#define TxBufferSize1 (ARRAY_SZ(TxBuffer1) - 1) +#define TxBufferSize2 (ARRAY_SZ(TxBuffer2) - 1) + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); +TestStatus Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxBuffer1[] = "\r\nCW32F030 UART HalfDuplex: USARTy -> USARTz\r\n"; +uint8_t TxBuffer2[] = "\r\nCW32F030 UART HalfDuplex: USARTz -> USARTy\r\n"; +uint8_t RxBuffer1[TxBufferSize2]; +uint8_t RxBuffer2[TxBufferSize1]; +uint32_t NbrOfDataToRead1 = TxBufferSize2; +uint32_t NbrOfDataToRead2 = TxBufferSize1; +uint8_t TxCounter1 = 0, RxCounter1 = 0; +uint8_t TxCounter2 = 0, RxCounter2 = 0; +volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED; + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置UART + UART_Configuration(); + //单线半双工 USARTy + USART_HalfDuplexCmd(USARTy, ENABLE); + //单线半双工 USARTz + USART_HalfDuplexCmd(USARTz, ENABLE); + //USARTy -> USARTz + while (NbrOfDataToRead2--) + { + //USARTy发送一个字节数据 + USART_SendData_8bit(USARTy, TxBuffer1[TxCounter1++]); + while (USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET); + //USARTz 等待RC + while (USART_GetFlagStatus(USARTz, USART_FLAG_RC) == RESET); + USART_ClearFlag(USARTz, USART_FLAG_RC); + RxBuffer2[RxCounter2++] = USART_ReceiveData_8bit(USARTz); + } + //USARTz -> USARTy + while (NbrOfDataToRead1--) + { + //USARTz发送一个字节数据 + USART_SendData_8bit(USARTz, TxBuffer2[TxCounter2++]); + while (USART_GetFlagStatus(USARTz, USART_FLAG_TXE) == RESET); + //USARTy 等待RC + while (USART_GetFlagStatus(USARTy, USART_FLAG_RC) == RESET); + USART_ClearFlag(USARTy, USART_FLAG_RC); + RxBuffer1[RxCounter1++] = USART_ReceiveData_8bit(USARTy); + } + //检查收发数据一致性 + TransferStatus1 = Buffercmp(TxBuffer1, RxBuffer2, TxBufferSize1); + TransferStatus2 = Buffercmp(TxBuffer2, RxBuffer1, TxBufferSize2); + if (TransferStatus1 == PASSED && TransferStatus2 == PASSED) //PASSED + { + //LED1亮 + PB09_SETHIGH(); + } + else //FAILED + { + //LED2亮 + PB08_SETHIGH(); + } + while (1) + { + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 8MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + //外设时钟使能 + RCC_AHBPeriphClk_Enable(USARTy_GPIO_CLK | USARTz_GPIO_CLK | RCC_AHB_PERIPH_GPIOB, ENABLE); + USARTy_APBClkENx(USARTy_CLK, ENABLE); + USARTz_APBClkENx(USARTz_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //UART TX 复用 + USARTy_AFTX; + USARTz_AFTX; + //UART TX PUR + USARTy_TXPUR; + USARTz_TXPUR; + GPIO_InitStructure.Pins = USARTy_TxPin; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD; //开漏输出 + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(USARTy_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.Pins = USARTz_TxPin; + GPIO_Init(USARTz_GPIO, &GPIO_InitStructure); + //PB9 LED1 / PB8 LED2 + GPIO_InitStructure.Pins = GPIO_PIN_9 | GPIO_PIN_8; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + //LED灭 + PB09_SETLOW(); + PB08_SETLOW(); +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + USART_InitTypeDef USART_InitStructure; + USART_InitStructure.USART_BaudRate = USARTyz_BaudRate; + USART_InitStructure.USART_Over = USART_Over_16; + USART_InitStructure.USART_Source = USART_Source_PCLK; + USART_InitStructure.USART_UclkFreq = USARTyz_UclkFreq; + USART_InitStructure.USART_StartBit = USART_StartBit_FE; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(USARTy, &USART_InitStructure); + USART_Init(USARTz, &USART_InitStructure); +} + +/** + * @brief Compares two buffers + * + * @param pBuffer1 :buffers to be compared + * @param pBuffer2 :buffers to be compared + * @param BufferLength :buffer's length + * @return TestStatus + * @arg PASSED: pBuffer1 identical to pBuffer2 + * @arg FAILED: pBuffer1 differs from pBuffer2 + */ +TestStatus Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + pBuffer1++; + pBuffer2++; + } + return PASSED; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/readme.txt new file mode 100644 index 0000000..5aa9c7f --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HalfDuplex/readme.txt @@ -0,0 +1,36 @@ +示例目的： + UART单线半双工通信示例。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟6分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为PCLK + 5. PB09（LED1）设置为PUSH-PULL输出 + 6. PB08（LED2）设置为PUSH-PULL输出 + +演示说明： + USARTy查询方式（TXE）发送TxBuffer1缓冲区中的数据， + USARTz查询方式（RC）接收数据，并存储到RxBuffer2缓冲区。 + + USARTz查询方式（TXE）发送TxBuffer2缓冲区中的数据， + USARTy查询方式（RC）接收数据，并存储到RxBuffer1缓冲区。 + + 比较TxBuffer1和RxBuffer2、TxBuffer2和RxBuffer1， + 如果数据一致，则LED1亮，否则LED2亮。 + +硬件连接： + UART1_TXD (PA08) -- UART2_TXD (PA06) + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/EWARM/Project.ewd new file mode 100644 index 0000000..800c43b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/EWARM/Project.ewd @@ -0,0 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$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/EWARM/Project.ewp new file mode 100644 index 0000000..cb24b91 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/EWARM/Project.ewp @@ -0,0 +1,2157 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_uart.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/MDK/Project.uvoptx new file mode 100644 index 0000000..b1e90b1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/MDK/Project.uvoptx @@ -0,0 +1,351 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Template + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + RxCounter + + + 1 + 1 + RxBuffer + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\UART1 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/MDK/Project.uvprojx new file mode 100644 index 0000000..4202374 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/MDK/Project.uvprojx @@ -0,0 +1,478 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Template + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/USER/inc/main.h new file mode 100644 index 0000000..6adb2e7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_uart.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/USER/src/main.c new file mode 100644 index 0000000..c3e4838 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/USER/src/main.c @@ -0,0 +1,204 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTx +#define DEBUG_USARTx CW_UART1 +#define DEBUG_USART_CLK RCC_APB2_PERIPH_UART1 +#define DEBUG_USART_APBClkENx RCC_APBPeriphClk_Enable2 +#define DEBUG_USART_BaudRate 9600 +#define DEBUG_USART_UclkFreq 8000000 + +//UARTx GPIO +#define DEBUG_USART_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define DEBUG_USART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_USART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_RX_GPIO_PIN GPIO_PIN_9 +#define DEBUG_USART_CTS_GPIO_PORT CW_GPIOA +#define DEBUG_USART_CTS_GPIO_PIN GPIO_PIN_10 +#define DEBUG_USART_RTS_GPIO_PORT CW_GPIOA +#define DEBUG_USART_RTS_GPIO_PIN GPIO_PIN_11 + +//GPIO AF +#define DEBUG_USART_AFTX PA08_AFx_UART1TXD() +#define DEBUG_USART_AFRX PA09_AFx_UART1RXD() +#define DEBUG_USART_AFCTS PA10_AFx_UART1CTS() +#define DEBUG_USART_AFRTS PA11_AFx_UART1RTS() + +#define TxBufferSize (ARRAY_SZ(TxBuffer) - 1) +#define RxBufferSize 0xFF + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxBuffer[] = "\r\nCW32F030 UART HwFlowControl: UART <-> PC\r\n"; +uint8_t RxBuffer[RxBufferSize]; +uint8_t NbrOfDataToTransfer = TxBufferSize; +uint8_t TxCounter = 0, RxCounter = 0; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置UART + UART_Configuration(); + //UART -> PC + while (NbrOfDataToTransfer--) + { + USART_SendData_8bit(DEBUG_USARTx, TxBuffer[TxCounter++]); + while (USART_GetFlagStatus(DEBUG_USARTx, USART_FLAG_TXE) == RESET); + } + //PC -> UART + do + { + if ((USART_GetFlagStatus(DEBUG_USARTx, USART_FLAG_RC) != RESET) && (RxCounter < RxBufferSize)) + { + RxBuffer[RxCounter] = USART_ReceiveData_8bit(DEBUG_USARTx); + USART_SendData_8bit(DEBUG_USARTx, RxBuffer[RxCounter++]); + while (USART_GetFlagStatus(DEBUG_USARTx, USART_FLAG_TXE) == RESET); + USART_ClearFlag(DEBUG_USARTx, USART_FLAG_RC); + } + } + while ((RxBuffer[RxCounter - 1] != '\n') && (RxCounter != RxBufferSize)); + while (1) + { + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 8MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + //外设时钟使能 + RCC_AHBPeriphClk_Enable(DEBUG_USART_GPIO_CLK, ENABLE); + DEBUG_USART_APBClkENx(DEBUG_USART_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //UART TX RX CTS RTS 复用 + DEBUG_USART_AFTX; + DEBUG_USART_AFRX; + DEBUG_USART_AFCTS; + DEBUG_USART_AFRTS; + GPIO_InitStructure.Pins = DEBUG_USART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = DEBUG_USART_RTS_GPIO_PIN; + GPIO_Init(DEBUG_USART_RTS_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = DEBUG_USART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = DEBUG_USART_CTS_GPIO_PIN; + GPIO_Init(DEBUG_USART_CTS_GPIO_PORT, &GPIO_InitStructure); +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + USART_InitTypeDef USART_InitStructure; + USART_InitStructure.USART_BaudRate = DEBUG_USART_BaudRate; + USART_InitStructure.USART_Over = USART_Over_16; + USART_InitStructure.USART_Source = USART_Source_PCLK; + USART_InitStructure.USART_UclkFreq = DEBUG_USART_UclkFreq; + USART_InitStructure.USART_StartBit = USART_StartBit_FE; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS_CTS; //CTS、RTS + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(DEBUG_USARTx, &USART_InitStructure); +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/readme.txt new file mode 100644 index 0000000..643d62b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_HwFlowControl/readme.txt @@ -0,0 +1,33 @@ +示例目的： + UART硬件流控（RTS、CTS）示例。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟6分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为PCLK + +演示说明： + UART发送TxBuffer缓冲区中的数据至PC； + PC发送数据，UART接收数据并存储到RxBuffer缓冲区， + UART将RxBuffer缓冲区中的数据回传至PC。 + 当UART接收到'\n'，或接收数据量超过RxBufferSize后，传输结束。 + +硬件连接： + UART1_TXD (PA08) -- PC_RX + UART1_RXD (PA09) -- PC_TX + UART1_CTS (PA10) -- CTS + UART1_RTS (PA11) -- RTS + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/EWARM/Project.ewd new file mode 100644 index 0000000..800c43b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/EWARM/Project.ewp new file mode 100644 index 0000000..cb24b91 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/EWARM/Project.ewp @@ -0,0 +1,2157 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/MDK/Project.uvoptx new file mode 100644 index 0000000..f4479f0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/MDK/Project.uvoptx @@ -0,0 +1,364 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + DLGUARM + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=105,137,292,353,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + TxRxBuffer + + + + + 1 + 0 + 0x40010030 + 0 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\UART1 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/MDK/Project.uvprojx new file mode 100644 index 0000000..889ad87 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/MDK/Project.uvprojx @@ -0,0 +1,478 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/USER/inc/main.h new file mode 100644 index 0000000..e088fbf --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_uart.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..e482911 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/USER/src/interrupts_cw32f030.c @@ -0,0 +1,414 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + uint8_t TxRxBuffer; + if (USART_GetITStatus(CW_UART1, USART_IT_RC) != RESET) + { + TxRxBuffer = USART_ReceiveData_8bit(CW_UART1); + USART_SendData_8bit(CW_UART1, TxRxBuffer); + USART_ClearITPendingBit(CW_UART1, USART_IT_RC); + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/USER/src/main.c new file mode 100644 index 0000000..0eab8dd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/USER/src/main.c @@ -0,0 +1,210 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTx +#define DEBUG_USARTx CW_UART1 +#define DEBUG_USART_CLK RCC_APB2_PERIPH_UART1 +#define DEBUG_USART_APBClkENx RCC_APBPeriphClk_Enable2 +#define DEBUG_USART_BaudRate 9600 +#define DEBUG_USART_UclkFreq 8000000 + +//UARTx GPIO +#define DEBUG_USART_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define DEBUG_USART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_USART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_RX_GPIO_PIN GPIO_PIN_9 + +//GPIO AF +#define DEBUG_USART_AFTX PA08_AFx_UART1TXD() +#define DEBUG_USART_AFRX PA09_AFx_UART1RXD() + +//中断 +#define DEBUG_USART_IRQ UART1_IRQn + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); +void NVIC_Configuration(void); +void USART_SendString(UART_TypeDef *USARTx, char *String); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置UART + UART_Configuration(); + //配置NVIC + NVIC_Configuration(); + //使能UARTx RC中断 + USART_ITConfig(DEBUG_USARTx, USART_IT_RC, ENABLE); + USART_SendString(DEBUG_USARTx, "\r\nCW32F030 UART Interrupt\r\n"); + while (1) + { + //中断收发 + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 8MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + //外设时钟使能 + RCC_AHBPeriphClk_Enable(DEBUG_USART_GPIO_CLK, ENABLE); + DEBUG_USART_APBClkENx(DEBUG_USART_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //UART TX RX 复用 + DEBUG_USART_AFTX; + DEBUG_USART_AFRX; + GPIO_InitStructure.Pins = DEBUG_USART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = DEBUG_USART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStructure); +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + USART_InitTypeDef USART_InitStructure; + USART_InitStructure.USART_BaudRate = DEBUG_USART_BaudRate; + USART_InitStructure.USART_Over = USART_Over_16; + USART_InitStructure.USART_Source = USART_Source_PCLK; + USART_InitStructure.USART_UclkFreq = DEBUG_USART_UclkFreq; + USART_InitStructure.USART_StartBit = USART_StartBit_FE; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(DEBUG_USARTx, &USART_InitStructure); +} + +/** + * @brief 配置NVIC + * + */ +void NVIC_Configuration(void) +{ + //优先级，无优先级分组 + NVIC_SetPriority(DEBUG_USART_IRQ, 0); + //UARTx中断使能 + NVIC_EnableIRQ(DEBUG_USART_IRQ); +} + +/** + * @brief 发送字符串 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param String :待发送的字符串 + */ +void USART_SendString(UART_TypeDef *USARTx, char *String) +{ + while (*String != '\0') + { + USART_SendData_8bit(USARTx, *String); + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXE) == RESET); + String++; + } + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXBUSY) == SET); +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/readme.txt new file mode 100644 index 0000000..a3ea8c3 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Interrupt/readme.txt @@ -0,0 +1,28 @@ +示例目的： + UART中断方式接收数据示例。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟6分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为PCLK + +演示说明： + PC发送数据，UART中断方式接收数据，并回传至PC。 + +硬件连接： + UART1_TXD (PA08) -- PC_RX + UART1_RXD (PA09) -- PC_TX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/EWARM/Project.ewd new file mode 100644 index 0000000..800c43b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/EWARM/Project.ewp new file mode 100644 index 0000000..cb24b91 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/EWARM/Project.ewp @@ -0,0 +1,2157 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/MDK/Project.uvoptx new file mode 100644 index 0000000..3e06bd2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/MDK/Project.uvoptx @@ -0,0 +1,351 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Template + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + TxRxBufferSize + + + 1 + 1 + TxRxBuffer + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\UART1 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/MDK/Project.uvprojx new file mode 100644 index 0000000..4202374 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/MDK/Project.uvprojx @@ -0,0 +1,478 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Template + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/USER/inc/main.h new file mode 100644 index 0000000..6adb2e7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_uart.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/USER/src/main.c new file mode 100644 index 0000000..df27b23 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/USER/src/main.c @@ -0,0 +1,231 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTx +#define DEBUG_USARTx CW_UART1 +#define DEBUG_USART_CLK RCC_APB2_PERIPH_UART1 +#define DEBUG_USART_APBClkENx RCC_APBPeriphClk_Enable2 +#define DEBUG_USART_BaudRate 9600 +#define DEBUG_USART_UclkFreq 32800 + +//UARTx GPIO +#define DEBUG_USART_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define DEBUG_USART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_USART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_RX_GPIO_PIN GPIO_PIN_9 + +//GPIO AF +#define DEBUG_USART_AFTX PA08_AFx_UART1TXD() +#define DEBUG_USART_AFRX PA09_AFx_UART1RXD() + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); +void USART_SendBuf_Polling(UART_TypeDef *USARTx, uint8_t *TxBuf, uint8_t TxCnt); +uint8_t USART_RecvBuf_Polling(UART_TypeDef *USARTx, uint8_t *RxBuf); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxRxBufferSize; +uint8_t TxRxBuffer[] = "\r\nCW32F030 UART Dedicated Sampling\r\n"; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置UART + UART_Configuration(); + USART_SendBuf_Polling(DEBUG_USARTx, TxRxBuffer, ARRAY_SZ(TxRxBuffer) - 1); + while (1) + { + //轮询收发 + TxRxBufferSize = USART_RecvBuf_Polling(DEBUG_USARTx, TxRxBuffer); + USART_SendBuf_Polling(DEBUG_USARTx, TxRxBuffer, TxRxBufferSize); + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 8MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + RCC_LSI_Enable(); + //外设时钟使能 + RCC_AHBPeriphClk_Enable(DEBUG_USART_GPIO_CLK, ENABLE); + DEBUG_USART_APBClkENx(DEBUG_USART_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //UART TX RX 复用 + DEBUG_USART_AFTX; + DEBUG_USART_AFRX; + GPIO_InitStructure.Pins = DEBUG_USART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = DEBUG_USART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStructure); +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + USART_InitTypeDef USART_InitStructure; + USART_InitStructure.USART_BaudRate = DEBUG_USART_BaudRate; + USART_InitStructure.USART_Over = USART_Over_sp; //专用采样 + USART_InitStructure.USART_Source = USART_Source_LSI; //传输时钟 UCLK = LSI + USART_InitStructure.USART_UclkFreq = DEBUG_USART_UclkFreq; + USART_InitStructure.USART_StartBit = USART_StartBit_FE; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(DEBUG_USARTx, &USART_InitStructure); +} + +/** + * @brief 发送8位数组 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param TxBuf :待发送的数组 + * @param TxCnt :待发送的数组元素个数 + */ +void USART_SendBuf_Polling(UART_TypeDef *USARTx, uint8_t *TxBuf, uint8_t TxCnt) +{ + while (TxCnt) + { + USART_SendData_8bit(USARTx, *TxBuf); + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXE) == RESET); + TxBuf++; + TxCnt--; + } + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXBUSY) == SET); +} + +/** + * @brief 接收8位数组 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param RxBuf :接收Buf + * @return uint8_t :接收的字符个数 + */ +uint8_t USART_RecvBuf_Polling(UART_TypeDef *USARTx, uint8_t *RxBuf) +{ + uint8_t RxCnt = 0; + do + { + //等待RC + while (USART_GetFlagStatus(USARTx, USART_FLAG_RC) == RESET); + //清RC + USART_ClearFlag(USARTx, USART_FLAG_RC); + //ERROR: PE or FE + if (USART_GetFlagStatus(USARTx, USART_FLAG_PE | USART_FLAG_FE)) + { + USART_ClearFlag(USARTx, USART_FLAG_PE | USART_FLAG_FE); + RxCnt = 0x00; + } + else + { + RxBuf[RxCnt] = USART_ReceiveData_8bit(USARTx); + RxCnt++; + } + } + while (RxBuf[RxCnt - 1] != '\n'); + return RxCnt; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/readme.txt new file mode 100644 index 0000000..91a6c08 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_LSELSI_Polling/readme.txt @@ -0,0 +1,30 @@ +示例目的： + UART查询方式发送和接收数据示例（专用采样）。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟6分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为LSI + +演示说明： + PC发送数据，UART查询方式（RC）接收数据，并存储到TxRxBuffer缓冲区； + 当UART接收到'\n'后，停止接收数据。 + UART查询方式（TXE）发送TxRxBuffer缓冲区中的数据至PC。 + +硬件连接： + UART1_TXD (PA08) -- PC_RX + UART1_RXD (PA09) -- PC_TX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/EWARM/Project.ewd new file mode 100644 index 0000000..800c43b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/EWARM/Project.ewp new file mode 100644 index 0000000..cb24b91 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/EWARM/Project.ewp @@ -0,0 +1,2157 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + 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--git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/MDK/Project.uvoptx new file mode 100644 index 0000000..674abb4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/MDK/Project.uvoptx @@ -0,0 +1,406 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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+ 0 + 0 + 0 + 0 + 0 + 1 + C:\Users\Administrator\Desktop\CW32F030_StdPeriph_Lib\Examples\UART\UART_MultiProcessor - 鍓湰\USER\src\interrupts_cw32f030.c + + \\Project\../USER/src/interrupts_cw32f030.c\409 + + + + + 0 + 1 + TxCounter + + + 1 + 1 + RxCounter + + + 2 + 1 + TransferStatus1 + + + 3 + 1 + TransferStatus2 + + + 4 + 1 + RxBuffer2 + + + 5 + 1 + RxBuffer1 + + + + + 1 + 0 + 0x40010030 + 0 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\UART2 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/MDK/Project.uvprojx new file mode 100644 index 0000000..889ad87 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/MDK/Project.uvprojx @@ -0,0 +1,478 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/USER/inc/main.h new file mode 100644 index 0000000..e088fbf --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_uart.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..18aabe3 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/USER/src/interrupts_cw32f030.c @@ -0,0 +1,419 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +extern uint8_t TxCounter, RxCounter; +extern uint8_t TxBuffer2[], RxBuffer2[]; +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + //USARTz RC + if (USART_GetITStatus(CW_UART2, USART_IT_RC) != RESET) + { + USART_ClearITPendingBit(CW_UART2, USART_IT_RC); + if ((USART_ReceiveData(CW_UART2) & 0x100) == RESET) //数据帧 + { + RxBuffer2[RxCounter] = USART_ReceiveData(CW_UART2); + USART_SendData(CW_UART2, TxBuffer2[TxCounter++]); + } + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/USER/src/main.c new file mode 100644 index 0000000..f2798c9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/USER/src/main.c @@ -0,0 +1,286 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTy +#define USARTy CW_UART1 +#define USARTy_CLK RCC_APB2_PERIPH_UART1 +#define USARTy_APBClkENx RCC_APBPeriphClk_Enable2 + +#define USARTy_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define USARTy_GPIO CW_GPIOA +#define USARTy_TxPin GPIO_PIN_8 +#define USARTy_RxPin GPIO_PIN_9 +#define USARTy_AFTX PA08_AFx_UART1TXD() +#define USARTy_AFRX PA09_AFx_UART1RXD() + +//UARTz +#define USARTz CW_UART2 +#define USARTz_CLK RCC_APB1_PERIPH_UART2 +#define USARTz_APBClkENx RCC_APBPeriphClk_Enable1 + +#define USARTz_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define USARTz_GPIO CW_GPIOA +#define USARTz_TxPin GPIO_PIN_6 +#define USARTz_RxPin GPIO_PIN_7 +#define USARTz_AFTX PA06_AFx_UART2TXD() +#define USARTz_AFRX PA07_AFx_UART2RXD() + +#define USARTyz_BaudRate 9600 +#define USARTyz_UclkFreq 8000000 + +//中断 +#define USARTz_IRQ UART2_IRQn + +#define BufferSize ARRAY_SZ(TxBuffer1) + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); +void NVIC_Configuration(void); +TestStatus Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxBuffer1[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, + 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, + 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, + 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23 + }; +uint8_t TxBuffer2[] = {0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, + 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, + 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, + 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83 + }; +uint8_t RxBuffer1[BufferSize]; +uint8_t RxBuffer2[BufferSize]; +uint8_t TxCounter = 0, RxCounter = 0; +volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED; + +uint8_t sADDR = 0xA5; +uint8_t sMASK = 0xFF; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置UART + UART_Configuration(); + //配置NVIC + NVIC_Configuration(); + //USARTz RC中断 + USART_ITConfig(USARTz, USART_IT_RC, ENABLE); + //配置多机通信 USARTz + USART_SetMultiMode(USARTz, sADDR, sMASK); + /**********************USARTy -> USARTz*************************/ + //USARTy发送地址帧，寻址到USARTz + USART_SendData(USARTy, 0x100 | sADDR); + while (USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET); + while (TxCounter < BufferSize) + { + //USARTy 发送 + USART_SendData(USARTy, TxBuffer1[TxCounter]); + while (USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET); + //USARTZ 中断接收 + //USARTy 接收 + while (USART_GetFlagStatus(USARTy, USART_FLAG_RC) == RESET); + RxBuffer1[RxCounter++] = USART_ReceiveData(USARTy); + USART_ClearFlag(USARTy, USART_FLAG_RC); + } + //检查收发数据一致性 + TransferStatus1 = Buffercmp(TxBuffer1, RxBuffer2, BufferSize); + TransferStatus2 = Buffercmp(TxBuffer2, RxBuffer1, BufferSize); + if (TransferStatus1 == PASSED && TransferStatus2 == PASSED) //PASSED + { + //LED1亮 + PB09_SETHIGH(); + } + else //FAILED + { + //LED2亮 + PB08_SETHIGH(); + } + while (1) + { + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 8MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + //外设时钟使能 + RCC_AHBPeriphClk_Enable(USARTy_GPIO_CLK | USARTz_GPIO_CLK | RCC_AHB_PERIPH_GPIOB, ENABLE); + USARTy_APBClkENx(USARTy_CLK, ENABLE); + USARTz_APBClkENx(USARTz_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //UART TX RX 复用 + USARTy_AFTX; + USARTy_AFRX; + USARTz_AFTX; + USARTz_AFRX; + GPIO_InitStructure.Pins = USARTy_TxPin; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(USARTy_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.Pins = USARTz_TxPin; + GPIO_Init(USARTz_GPIO, &GPIO_InitStructure); + //PB9 LED1 / PB8 - LED2 + GPIO_InitStructure.Pins = GPIO_PIN_9 | GPIO_PIN_8; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.Pins = USARTy_RxPin; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(USARTy_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.Pins = USARTz_RxPin; + GPIO_Init(USARTz_GPIO, &GPIO_InitStructure); + //LED灭 + PB09_SETLOW(); + PB08_SETLOW(); +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + USART_InitTypeDef USART_InitStructure; + USART_InitStructure.USART_BaudRate = USARTyz_BaudRate; + USART_InitStructure.USART_Over = USART_Over_16; + USART_InitStructure.USART_Source = USART_Source_PCLK; + USART_InitStructure.USART_UclkFreq = USARTyz_UclkFreq; + USART_InitStructure.USART_StartBit = USART_StartBit_FE; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_User ; //自定义校验 + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(USARTy, &USART_InitStructure); + USART_Init(USARTz, &USART_InitStructure); +} + +/** + * @brief 配置NVIC + * + */ +void NVIC_Configuration(void) +{ + //优先级，无优先级分组 + NVIC_SetPriority(USARTz_IRQ, 0); + //UARTx中断使能 + NVIC_EnableIRQ(USARTz_IRQ); +} + +/** + * @brief Compares two buffers + * + * @param pBuffer1 :buffers to be compared + * @param pBuffer2 :buffers to be compared + * @param BufferLength :buffer's length + * @return TestStatus + * @arg PASSED: pBuffer1 identical to pBuffer2 + * @arg FAILED: pBuffer1 differs from pBuffer2 + */ +TestStatus Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + pBuffer1++; + pBuffer2++; + } + return PASSED; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/readme.txt new file mode 100644 index 0000000..fea3935 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_MultiProcessor/readme.txt @@ -0,0 +1,37 @@ +示例目的： + UART多机通信模式示例。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟6分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为PCLK + 5. PB09（LED1）设置为PUSH-PULL输出 + 6. PB08（LED2）设置为PUSH-PULL输出 + +演示说明： + USARTy（主机）发送地址帧0xA5寻址到USARTz（从机）。 + + USARTy（主机）查询方式（TXE）发送TxBuffer1缓冲区中的数据； + USARTz（从机）中断方式接收数据帧，并存储到RxBuffer2缓冲区，同时发送TxBuffer2缓冲区中的数据到USARTy（主机）； + USARTy（主机）查询方式（RC）接收数据，并存储到RxBuffer1缓冲区。 + + 比较TxBuffer1和RxBuffer2、TxBuffer2和RxBuffer1， + 如果数据一致，LED1亮，否则LED2亮。 + +硬件连接： + UART1_TXD (PA08) -- UART2_RXD (PA07) + UART1_RXD (PA09) -- UART2_TXD (PA06) + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/EWARM/Project.ewd new file mode 100644 index 0000000..d718518 --- /dev/null +++ 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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Template + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 73 + 1 +
2882
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + \\Template\../../../../Libraries/src/cw32f030_uart.c\73 + + + + + 0 + 1 + TxRxBufferSize + + + 1 + 1 + TxRxBuffer + + + 2 + 1 + USART_InitStructure + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\UART1 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/MDK/Project.uvprojx new file mode 100644 index 0000000..5e15fda --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/MDK/Project.uvprojx @@ -0,0 +1,462 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Template + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/USER/inc/main.h new file mode 100644 index 0000000..6adb2e7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_uart.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/USER/src/main.c new file mode 100644 index 0000000..0ada2ad --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/USER/src/main.c @@ -0,0 +1,230 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTx +#define DEBUG_USARTx CW_UART1 +#define DEBUG_USART_CLK RCC_APB2_PERIPH_UART1 +#define DEBUG_USART_APBClkENx RCC_APBPeriphClk_Enable2 +#define DEBUG_USART_BaudRate 9600 +#define DEBUG_USART_UclkFreq 8000000 + +//UARTx GPIO +#define DEBUG_USART_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define DEBUG_USART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_USART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_RX_GPIO_PIN GPIO_PIN_9 + +//GPIO AF +#define DEBUG_USART_AFTX PA08_AFx_UART1TXD() +#define DEBUG_USART_AFRX PA09_AFx_UART1RXD() + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); +void USART_SendBuf_Polling(UART_TypeDef *USARTx, uint8_t *TxBuf, uint8_t TxCnt); +uint8_t USART_RecvBuf_Polling(UART_TypeDef *USARTx, uint8_t *RxBuf); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxRxBufferSize; +uint8_t TxRxBuffer[] = "\r\nCW32F030 UART Polling\r\n"; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置UART + UART_Configuration(); + USART_SendBuf_Polling(DEBUG_USARTx, TxRxBuffer, ARRAY_SZ(TxRxBuffer) - 1); + while (1) + { + //轮询收发 + TxRxBufferSize = USART_RecvBuf_Polling(DEBUG_USARTx, TxRxBuffer); + USART_SendBuf_Polling(DEBUG_USARTx, TxRxBuffer, TxRxBufferSize); + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 8MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + //外设时钟使能 + RCC_AHBPeriphClk_Enable(DEBUG_USART_GPIO_CLK, ENABLE); + DEBUG_USART_APBClkENx(DEBUG_USART_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //UART TX RX 复用 + DEBUG_USART_AFTX; + DEBUG_USART_AFRX; + GPIO_InitStructure.Pins = DEBUG_USART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = DEBUG_USART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStructure); +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + USART_InitTypeDef USART_InitStructure; + USART_InitStructure.USART_BaudRate = DEBUG_USART_BaudRate; + USART_InitStructure.USART_Over = USART_Over_16; + USART_InitStructure.USART_Source = USART_Source_PCLK; + USART_InitStructure.USART_UclkFreq = DEBUG_USART_UclkFreq; + USART_InitStructure.USART_StartBit = USART_StartBit_FE; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(DEBUG_USARTx, &USART_InitStructure); +} + +/** + * @brief 发送8位数组 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param TxBuf :待发送的数组 + * @param TxCnt :待发送的数组元素个数 + */ +void USART_SendBuf_Polling(UART_TypeDef *USARTx, uint8_t *TxBuf, uint8_t TxCnt) +{ + while (TxCnt) + { + USART_SendData_8bit(USARTx, *TxBuf); + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXE) == RESET); + TxBuf++; + TxCnt--; + } + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXBUSY) == SET); +} + +/** + * @brief 接收8位数组 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param RxBuf :接收Buf + * @return uint8_t :接收的字符个数 + */ +uint8_t USART_RecvBuf_Polling(UART_TypeDef *USARTx, uint8_t *RxBuf) +{ + uint8_t RxCnt = 0; + do + { + //等待RC + while (USART_GetFlagStatus(USARTx, USART_FLAG_RC) == RESET); + //清RC + USART_ClearFlag(USARTx, USART_FLAG_RC); + //ERROR: PE or FE + if (USART_GetFlagStatus(USARTx, USART_FLAG_PE | USART_FLAG_FE)) + { + USART_ClearFlag(USARTx, USART_FLAG_PE | USART_FLAG_FE); + RxCnt = 0x00; + } + else + { + RxBuf[RxCnt] = USART_ReceiveData_8bit(USARTx); + RxCnt++; + } + } + while (RxBuf[RxCnt - 1] != '\n'); + return RxCnt; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/readme.txt new file mode 100644 index 0000000..18df057 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Polling/readme.txt @@ -0,0 +1,30 @@ +示例目的： + UART查询方式发送和接收数据示例（16倍采样）。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟6分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为PCLK + +演示说明： + PC发送数据，UART查询方式（RC）接收数据，并存储到TxRxBuffer缓冲区； + 当UART接收到'\n'后，停止接收数据。 + UART查询方式（TXE）发送TxRxBuffer缓冲区中的数据至PC。 + +硬件连接： + UART1_TXD (PA08) -- PC_RX + UART1_RXD (PA09) -- PC_TX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/EWARM/Project.ewd new file mode 100644 index 0000000..800c43b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/EWARM/Project.ewp new file mode 100644 index 0000000..cb24b91 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/EWARM/Project.ewp @@ -0,0 +1,2157 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_uart.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/MDK/Project.uvoptx new file mode 100644 index 0000000..150387e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/MDK/Project.uvoptx @@ -0,0 +1,354 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Template + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + TxRxBufferSize + + + 1 + 1 + TxRxBuffer + + + 2 + 1 + USART_InitStructure + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\SYSCTRL + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/MDK/Project.uvprojx new file mode 100644 index 0000000..4b85296 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/MDK/Project.uvprojx @@ -0,0 +1,460 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Template + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/USER/inc/main.h new file mode 100644 index 0000000..6adb2e7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_uart.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/USER/src/main.c new file mode 100644 index 0000000..f424f3d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/USER/src/main.c @@ -0,0 +1,190 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTx +#define DEBUG_USARTx CW_UART1 +#define DEBUG_USART_CLK RCC_APB2_PERIPH_UART1 +#define DEBUG_USART_APBClkENx RCC_APBPeriphClk_Enable2 +#define DEBUG_USART_BaudRate 9600 +#define DEBUG_USART_UclkFreq 8000000 + +//UARTx GPIO +#define DEBUG_USART_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define DEBUG_USART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_USART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_RX_GPIO_PIN GPIO_PIN_9 + +//GPIO AF +#define DEBUG_USART_AFTX PA08_AFx_UART1TXD() +#define DEBUG_USART_AFRX PA09_AFx_UART1RXD() +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); + +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置UART + UART_Configuration(); + printf("\r\nCW32F030 UART Printf Example\r\n"); + while (1) + { + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 8MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + //外设时钟使能 + RCC_AHBPeriphClk_Enable(DEBUG_USART_GPIO_CLK, ENABLE); + DEBUG_USART_APBClkENx(DEBUG_USART_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //UART TX RX 复用 + DEBUG_USART_AFTX; + DEBUG_USART_AFRX; + GPIO_InitStructure.Pins = DEBUG_USART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = DEBUG_USART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStructure); +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + USART_InitTypeDef USART_InitStructure; + USART_InitStructure.USART_BaudRate = DEBUG_USART_BaudRate; + USART_InitStructure.USART_Over = USART_Over_16; + USART_InitStructure.USART_Source = USART_Source_PCLK; + USART_InitStructure.USART_UclkFreq = DEBUG_USART_UclkFreq; + USART_InitStructure.USART_StartBit = USART_StartBit_FE; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(DEBUG_USARTx, &USART_InitStructure); +} + +/** + * @brief Retargets the C library printf function to the USART. + * + */ +PUTCHAR_PROTOTYPE +{ + USART_SendData_8bit(DEBUG_USARTx, (uint8_t)ch); + + while (USART_GetFlagStatus(DEBUG_USARTx, USART_FLAG_TXE) == RESET); + + return ch; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/readme.txt new file mode 100644 index 0000000..8dea1fd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Printf/readme.txt @@ -0,0 +1,28 @@ +示例目的： + 将C库的printf函数重定向到UART。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟6分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为PCLK + +演示说明： + 使用UART在串口调试助手上输出printf调试信息。 + +硬件连接： + UART1_TXD (PA08) -- PC_RX + UART1_RXD (PA09) -- PC_TX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/EWARM/Project.ewd new file mode 100644 index 0000000..800c43b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/EWARM/Project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + 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$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/EWARM/Project.ewp new file mode 100644 index 0000000..e147d1c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/EWARM/Project.ewp @@ -0,0 +1,2160 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/MDK/Project.uvoptx new file mode 100644 index 0000000..b010e5a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/MDK/Project.uvoptx @@ -0,0 +1,429 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=1441,104,1852,606,0)(1007=1760,222,1967,443,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + DLGUARM + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=105,137,292,353,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 142 + 1 +
1496
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\Project\../USER/src/main.c\142 + + + + + 0 + 1 + TransferStatus1 + + + 1 + 1 + TransferStatus2 + + + 2 + 1 + TxBuffer1 + + + 3 + 1 + TxBuffer2 + + + 4 + 1 + NbrOfDataToRead1 + + + 5 + 1 + NbrOfDataToRead2 + + + 6 + 1 + RxBuffer2 + + + 7 + 1 + RxBuffer1 + + + + + 0 + 2 + TxBuffer1 + + + + + 1 + 0 + 0x40010030 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_spi.c + cw32f030_spi.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/MDK/Project.uvprojx new file mode 100644 index 0000000..fb3bb9c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/MDK/Project.uvprojx @@ -0,0 +1,483 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_uart.c + 1 + ..\..\..\..\Libraries\src\cw32f030_uart.c + + + cw32f030_spi.c + 1 + ..\..\..\..\Libraries\src\cw32f030_spi.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/USER/inc/main.h new file mode 100644 index 0000000..c12bbce --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_uart.h" +#include "cw32f030_spi.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/USER/src/main.c new file mode 100644 index 0000000..d953de4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/USER/src/main.c @@ -0,0 +1,322 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTx SPIx +#define DEBUG_USARTx CW_UART1 +#define DEBUG_USART_CLK RCC_APB2_PERIPH_UART1 +#define DEBUG_USART_APBClkENx RCC_APBPeriphClk_Enable2 + +#define DEBUG_SPIx CW_SPI1 +#define DEBUG_SPI_CLK RCC_APB2_PERIPH_SPI1 +#define DEBUG_SPI_APBClkENx RCC_APBPeriphClk_Enable2 + +//UARTx GPIO +#define DEBUG_USART_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define DEBUG_USART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_USART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_USART_RX_GPIO_PIN GPIO_PIN_9 +// #define DEBUG_USART_CS_GPIO_PORT CW_GPIOA +// #define DEBUG_USART_CS_GPIO_PIN GPIO_PIN_0 + +//SPIx GPIO +#define DEBUG_SPI_GPIO_CLK RCC_AHB_PERIPH_GPIOA +#define DEBUG_SPI_SCK_GPIO_PORT CW_GPIOA +#define DEBUG_SPI_SCK_GPIO_PIN GPIO_PIN_10 +#define DEBUG_SPI_MISO_GPIO_PORT CW_GPIOA +#define DEBUG_SPI_MISO_GPIO_PIN GPIO_PIN_11 +// #define DEBUG_SPI_CS_GPIO_PORT CW_GPIOA +// #define DEBUG_SPI_CS_GPIO_PIN GPIO_PIN_15 + +//GPIO AF +#define DEBUG_USART_AFTX PA08_AFx_UART1TXD() +#define DEBUG_USART_AFRX PA09_AFx_UART1RXD() +#define DEBUG_SPI_AFSCK PA10_AFx_SPI1SCK() +#define DEBUG_SPI_AFMISO PA11_AFx_SPI1MISO() +// #define DEBUG_SPI_AFCS PA15_AFx_SPI1CS() + +// #define SPI_CS_LOW() PA00_SETLOW() +// #define SPI_CS_HIGH() PA00_SETHIGH() + +#define TxBufferSize1 (ARRAY_SZ(TxBuffer1) - 1) +#define TxBufferSize2 (ARRAY_SZ(TxBuffer2) - 1) + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); +void SPI_Configuration(void); +TestStatus Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxBuffer1[] = "\r\nCW32F030 UART Synchronous: UART -> SPI\r\n"; +uint8_t TxBuffer2[] = "\r\nCW32F030 UART Synchronous: SPI -> UART\r\n"; +uint8_t RxBuffer1[TxBufferSize2]; +uint8_t RxBuffer2[TxBufferSize1]; +uint32_t NbrOfDataToRead1 = TxBufferSize2; +uint32_t NbrOfDataToRead2 = TxBufferSize1; +uint8_t TxCounter1 = 0, RxCounter1 = 0; +uint8_t TxCounter2 = 0, RxCounter2 = 0; +volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED; + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + //配置GPIO + GPIO_Configuration(); + //配置UART 同步半双工模式 + UART_Configuration(); + //配置SPI 单线半双工模式 + SPI_Configuration(); + /*************************** UART -> SPI *************************/ + USART_DirectionModeCmd(DEBUG_USARTx, USART_Mode_Tx, ENABLE); + //SPI 仅接收 + SPI_BiDirectionalLineConfig(DEBUG_SPIx, SPI_Direction_Rx); + //拉低片选 + SPI_NSSInternalSoftwareConfig(DEBUG_SPIx, SPI_NSSInternalSoft_Reset); + // SPI_CS_LOW(); + while (NbrOfDataToRead2--) + { + //UART发送一个字节数据 + USART_SendData_8bit(DEBUG_USARTx, TxBuffer1[TxCounter1++]); + while (USART_GetFlagStatus(DEBUG_USARTx, USART_FLAG_TXE) == RESET); + //SPI 等待RXNE + while (SPI_GetFlagStatus(DEBUG_SPIx, SPI_FLAG_RXNE) == RESET); + RxBuffer2[RxCounter2++] = SPI_ReceiveData(DEBUG_SPIx); + } + //拉高片选 + SPI_NSSInternalSoftwareConfig(DEBUG_SPIx, SPI_NSSInternalSoft_Set); + // SPI_CS_HIGH(); + /*************************** SPI -> UART **************************/ + //SPI 仅发送 + SPI_BiDirectionalLineConfig(DEBUG_SPIx, SPI_Direction_Tx); + //SPI 清空发送缓冲区和移位寄存器 + SPI_FlushSendBuff(DEBUG_SPIx); + SPI_SendData(DEBUG_SPIx, TxBuffer2[TxCounter2++]); + //拉低片选 + SPI_NSSInternalSoftwareConfig(DEBUG_SPIx, SPI_NSSInternalSoft_Reset); + // SPI_CS_LOW(); + USART_DirectionModeCmd(DEBUG_USARTx, USART_Mode_Tx, DISABLE); + USART_DirectionModeCmd(DEBUG_USARTx, USART_Mode_Rx, ENABLE); + while (NbrOfDataToRead1--) + { + //查询TXE，SPI发送一个字节数据 + while (SPI_GetFlagStatus(DEBUG_SPIx, SPI_FLAG_TXE) == RESET); + SPI_SendData(DEBUG_SPIx, TxBuffer2[TxCounter2++]); + //UART 等待RC + while (USART_GetFlagStatus(DEBUG_USARTx, USART_FLAG_RC) == RESET); + RxBuffer1[RxCounter1++] = USART_ReceiveData_8bit(DEBUG_USARTx); + //清除RC后，立即开始接收下一个字节数据 + USART_ClearFlag(DEBUG_USARTx, USART_FLAG_RC); + } + //拉高片选 + SPI_NSSInternalSoftwareConfig(DEBUG_SPIx, SPI_NSSInternalSoft_Set); + // SPI_CS_HIGH(); + //检查收发数据一致性 + TransferStatus1 = Buffercmp(TxBuffer1, RxBuffer2, TxBufferSize1); + TransferStatus2 = Buffercmp(TxBuffer2, RxBuffer1, TxBufferSize2); + if (TransferStatus1 == PASSED && TransferStatus2 == PASSED) //PASSED + { + //LED1亮 + PB09_SETHIGH(); + } + else //FAILED + { + //LED2亮 + PB08_SETHIGH(); + } + while (1) + { + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 24MHz = HCLK = PCLK + RCC_HSI_Enable(RCC_HSIOSC_DIV2); + //外设时钟使能 + RCC_AHBPeriphClk_Enable(DEBUG_USART_GPIO_CLK | DEBUG_SPI_GPIO_CLK | RCC_AHB_PERIPH_GPIOB, ENABLE); + DEBUG_USART_APBClkENx(DEBUG_USART_CLK, ENABLE); + DEBUG_SPI_APBClkENx(DEBUG_SPI_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //UART TX RX 复用 + DEBUG_USART_AFTX; + DEBUG_USART_AFRX; + //SPI SCK MISO CS 复用 + DEBUG_SPI_AFSCK; + DEBUG_SPI_AFMISO; + // DEBUG_SPI_AFCS; + //UART TX RX CS 推挽输出 + GPIO_InitStructure.Pins = DEBUG_USART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStructure); + GPIO_InitStructure.Pins = DEBUG_USART_RX_GPIO_PIN; + GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStructure); + // GPIO_InitStructure.Pins = DEBUG_USART_CS_GPIO_PIN; + // GPIO_Init(DEBUG_USART_CS_GPIO_PORT, &GPIO_InitStructure); + //SPI MISO 推挽输出 + GPIO_InitStructure.Pins = DEBUG_SPI_MISO_GPIO_PIN; + GPIO_Init(DEBUG_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); + //SPI SCK 浮空输入 + GPIO_InitStructure.Pins = DEBUG_SPI_SCK_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT; + GPIO_Init(DEBUG_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); + //SPI CS 上拉输入 + // GPIO_InitStructure.Pins = DEBUG_SPI_CS_GPIO_PIN; + // GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + // GPIO_Init(DEBUG_SPI_CS_GPIO_PORT, &GPIO_InitStructure); + //PB9 LED1 / PB8 - LED2 + GPIO_InitStructure.Pins = GPIO_PIN_9 | GPIO_PIN_8; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + //LED灭 + PB09_SETLOW(); + PB08_SETLOW(); +} + +/** + * @brief 配置UART 同步模式 2Mbps + * + */ +void UART_Configuration(void) +{ + USART_ClockInitTypeDef USART_ClockInitStructure; + USART_ClockInitStructure.USART_Clock = USART_Clock_Enable; + USART_ClockInitStructure.USART_Source = USART_Source_PCLK; + USART_ClockInit(DEBUG_USARTx, &USART_ClockInitStructure); +} + +/** + * @brief 配置SPI 单线半双工 从机 + * + */ +void SPI_Configuration(void) +{ + SPI_InitTypeDef SPI_InitStructure; + SPI_InitStructure.SPI_Direction = SPI_Direction_1Lines_HalfDuplex; // 单线半双工 + SPI_InitStructure.SPI_Mode = SPI_Mode_Slave; // 从机模式 + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; // 帧数据长度为8bit + SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; // 时钟空闲电平为高 + SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; // 第二个边沿采样 + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; // SSI寄存器的值决定本机是否被选中 + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; // 波特率为PCLK的2分频 + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_LSB; // 最低有效位 LSB 收发在前 + SPI_InitStructure.SPI_Speed = SPI_Speed_Low; // 低速SPI + SPI_Init(DEBUG_SPIx, &SPI_InitStructure); + SPI_Cmd(DEBUG_SPIx, ENABLE); +} + +/** + * @brief Compares two buffers + * + * @param pBuffer1 :buffers to be compared + * @param pBuffer2 :buffers to be compared + * @param BufferLength :buffer's length + * @return TestStatus + * @arg PASSED: pBuffer1 identical to pBuffer2 + * @arg FAILED: pBuffer1 differs from pBuffer2 + */ +TestStatus Buffercmp(uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + pBuffer1++; + pBuffer2++; + } + return PASSED; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/readme.txt new file mode 100644 index 0000000..b98d1a9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/UART/UART_Synchronous/readme.txt @@ -0,0 +1,39 @@ +示例目的： + UART和SPI之间进行同步半双工模式的通讯。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟2分频，24MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=24MHz + 4. UART的传输时钟设置为PCLK，12分频 + 5. SPI的时钟设置为PCLK，2分频 + 6. PB09（LED1）设置为PUSH-PULL输出 + 7. PB08（LED2）设置为PUSH-PULL输出 + +演示说明： + UART查询方式（TXE）发送TxBuffer1缓冲区的数据到SPI； + SPI查询方式（RXNE）接收数据，并存储到RxBuffer2缓冲区。 + + SPI查询方式（TXE）发送TxBuffer2缓冲区的数据到UART； + UART查询方式（RC）接收数据，并存储到RxBuffer1缓冲区。 + + 比较TxBuffer1和RxBuffer2、TxBuffer2和RxBuffer1， + 如果数据一致，LED1亮，否则LED2亮。 + +硬件连接： + UART1_TXD (PA08) -- SPI1_SCK (PA10) + UART1_RXD (PA09) -- SPI1_MISO (PA11) + UART CS (PA00) -- SPI1_CS (PA15) (可选 硬件NSS) + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/EWARM/vc_detect_fallingRising_irq.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/EWARM/vc_detect_fallingRising_irq.ewd new file mode 100644 index 0000000..d09623c --- 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + vc_detect_fallingRising_irq + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + vc_detect_fallingRising_irq + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_vc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_vc.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_adc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_adc.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/USER/inc/main.h new file mode 100644 index 0000000..4776cfb --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void LED_Init(void); +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..cc650a9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/USER/src/interrupts_cw32f030.c @@ -0,0 +1,413 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_vc.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +extern volatile boolean_t gFlagIrq; +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + VC1_ClearIrq(); + gFlagIrq = TRUE; + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/USER/src/main.c new file mode 100644 index 0000000..ec6b3cf --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/USER/src/main.c @@ -0,0 +1,175 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-07-14 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_systick.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_vc.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +volatile boolean_t gFlagIrq = FALSE; + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief VC I/O初始化 + * + */ +void VC_PortInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk); + //打开VC时钟 + REGBITS_SET(CW_SYSCTRL->APBEN2, SYSCTRL_APBEN2_VC_Msk); + //set PA11 as output + GPIO_InitStructure.Pins = GPIO_PIN_11; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + //set PA11 as VC output + PA11_AFx_VC1OUT(); + //set PA00 as VC1_CH0 P-INPUT + PA00_ANALOG_ENABLE(); + //set PA01 as VC1_CH1 N-INPUT + PA01_ANALOG_ENABLE(); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + VC_InitTypeDef VC_InitStruct; + VC_BlankTypeDef VC_BlankStruct; + VC_OutTypeDef VC_OutStruct; + //LED初始化 + LED_Init(); + //配置测试IO口 + VC_PortInit(); + //VC通道初始化 + VC_InitStruct.VC_InputP = VC_InputP_Ch0; + VC_InitStruct.VC_InputN = VC_InputN_Bgr1P2; //VC_InputN_Ch1; // + VC_InitStruct.VC_Hys = VC_Hys_10mV; + VC_InitStruct.VC_Resp = VC_Resp_High; + VC_InitStruct.VC_FilterEn = VC_Filter_Enable; + VC_InitStruct.VC_FilterClk = VC_FltClk_RC150K; + VC_InitStruct.VC_FilterTime = VC_FltTime_4095Clk; + VC_InitStruct.VC_Window = VC_Window_Disable; + VC_InitStruct.VC_Polarity = VC_Polarity_Low; + VC1_ChannelInit(&VC_InitStruct); + //VC Blank窗口初始化 + VC1VC2_BlankInit(&VC_BlankStruct); + VC1_BlankCfg(&VC_BlankStruct); + //VC输出连接初始化 + VC1VC2_OutInit(&VC_OutStruct); + VC1_OutputCfg(&VC_OutStruct); + //VC中断设置 + VC1_ITConfig(VC_IT_FALL | VC_IT_RISE, ENABLE); + VC1_EnableIrq(VC_INT_PRIORITY); + VC1_ClearIrq(); + VC1_EnableChannel(); + while (1) + { + if (gFlagIrq) + { + PB09_TOG(); + gFlagIrq = FALSE; + } + } +} + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOB_Msk); + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + //LEDs are off. + PB08_SETLOW(); + PB09_SETLOW(); +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/readme.txt new file mode 100644 index 0000000..3cb34a3 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_fallingRising_irq/readme.txt @@ -0,0 +1,27 @@ +示例目的： + 演示VC模块的输出信号上升沿/下降沿触发中断功能。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. VC的滤波时钟源为RC150K + 5. PB08/09设置为PUSH-PULL输出 + +演示说明： + VC输入P通道为PA00，N通道为BGR基准电压1.2V，VC输出端口为PA11。 + 外接可调直流电源，当VC输入P通道电压低于或者高于N通道电压时刻，PB09（LED）输出电平翻转一次。 + 保持P通道电压低于N通道电压，或者高于N通道电压时，PB09输出电平不变； + +使用说明： ++ EWARM + 1. 打开vc_detect_fallingRising_irq.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开vc_detect_fallingRising_irq.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/EWARM/vc_detect_falling_irq.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/EWARM/vc_detect_falling_irq.ewd new file mode 100644 index 0000000..d09623c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/EWARM/vc_detect_falling_irq.ewd @@ -0,0 +1,3269 @@ + + + + 2 + + Release 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a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/EWARM/vc_detect_falling_irq.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/EWARM/vc_detect_falling_irq.eww new file mode 100644 index 0000000..1fbfd0b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/EWARM/vc_detect_falling_irq.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\vc_detect_falling_irq.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/MDK/vc_detect_falling_irq.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/MDK/vc_detect_falling_irq.uvoptx new file mode 100644 index 0000000..733b3eb --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/MDK/vc_detect_falling_irq.uvoptx @@ -0,0 +1,345 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + vc_detect_falling_irq + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U4294967295 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_vc.c + cw32f030_vc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_adc.c + cw32f030_adc.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/MDK/vc_detect_falling_irq.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/MDK/vc_detect_falling_irq.uvprojx new file mode 100644 index 0000000..b1fc029 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/MDK/vc_detect_falling_irq.uvprojx @@ -0,0 +1,466 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + vc_detect_falling_irq + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + vc_detect_falling_irq + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_vc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_vc.c + + + cw32f030_adc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_adc.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/USER/inc/main.h new file mode 100644 index 0000000..8b10f5f --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void LED_Init(void); +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..cc650a9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/USER/src/interrupts_cw32f030.c @@ -0,0 +1,413 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_vc.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +extern volatile boolean_t gFlagIrq; +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + VC1_ClearIrq(); + gFlagIrq = TRUE; + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/USER/src/main.c new file mode 100644 index 0000000..330c79c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/USER/src/main.c @@ -0,0 +1,175 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-08-04 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_systick.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_vc.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +volatile boolean_t gFlagIrq = FALSE; + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief VC I/O初始化 + * + */ +void VC_PortInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk); + //打开VC时钟 + REGBITS_SET(CW_SYSCTRL->APBEN2, SYSCTRL_APBEN2_VC_Msk); + //set PA11 as output + GPIO_InitStructure.Pins = GPIO_PIN_11; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + //set PA11 as VC output + PA11_AFx_VC1OUT(); + //set PA00 as VC1_CH0 P-INPUT + PA00_ANALOG_ENABLE(); + //set PA01 as VC1_CH1 N-INPUT + PA01_ANALOG_ENABLE(); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + VC_InitTypeDef VC_InitStruct; + VC_BlankTypeDef VC_BlankStruct; + VC_OutTypeDef VC_OutStruct; + //LED初始化 + LED_Init(); + //配置测试IO口 + VC_PortInit(); + //VC通道初始化 + VC_InitStruct.VC_InputP = VC_InputP_Ch0; + VC_InitStruct.VC_InputN = VC_InputN_Bgr1P2; //VC_InputN_Ch1; // + VC_InitStruct.VC_Hys = VC_Hys_10mV; + VC_InitStruct.VC_Resp = VC_Resp_High; + VC_InitStruct.VC_FilterEn = VC_Filter_Enable; + VC_InitStruct.VC_FilterClk = VC_FltClk_RC150K; + VC_InitStruct.VC_FilterTime = VC_FltTime_4095Clk; + VC_InitStruct.VC_Window = VC_Window_Disable; + VC_InitStruct.VC_Polarity = VC_Polarity_Low; + VC1_ChannelInit(&VC_InitStruct); + //VC Blank窗口初始化 + VC1VC2_BlankInit(&VC_BlankStruct); + VC1_BlankCfg(&VC_BlankStruct); + //VC输出连接初始化 + VC1VC2_OutInit(&VC_OutStruct); + VC1_OutputCfg(&VC_OutStruct); + //VC中断设置 + VC1_ITConfig(VC_IT_FALL, ENABLE); + VC1_EnableIrq(VC_INT_PRIORITY); + VC1_ClearIrq(); + VC1_EnableChannel(); + while (1) + { + if (gFlagIrq) + { + PB09_TOG(); + gFlagIrq = FALSE; + } + } +} + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOB_Msk); + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + //LEDs are off. + PB08_SETLOW(); + PB09_SETLOW(); +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/readme.txt new file mode 100644 index 0000000..d0eeb82 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_falling_irq/readme.txt @@ -0,0 +1,27 @@ +示例目的： + 演示VC模块的输出信号下降沿触发中断功能。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. VC的滤波时钟源为RC150K + 5. PB08/09设置为PUSH-PULL输出 + +演示说明： + VC输入P通道为PA00，N通道为BGR基准电压1.2V，VC输出端口为PA11。 + 外接可调直流电源，当VC输入P通道电压低于N通道电压时刻，PB09（LED）输出电平翻转一次。 + 保持P通道电压低于N通道电压，或者调节P通道电压高于N通道电压时，PB09输出电平不变； + +使用说明： ++ EWARM + 1. 打开vc_detect_falling_irq.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开vc_detect_falling_irq.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/EWARM/vc_detect_high_irq.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/EWARM/vc_detect_high_irq.ewd new file mode 100644 index 0000000..d09623c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/EWARM/vc_detect_high_irq.ewd @@ -0,0 +1,3269 @@ + + + + 2 + + Release + + ARM + + 0 + + C-SPY + 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b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/EWARM/vc_detect_high_irq.eww new file mode 100644 index 0000000..9021d72 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/EWARM/vc_detect_high_irq.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\vc_detect_high_irq.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/MDK/vc_detect_high_irq.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/MDK/vc_detect_high_irq.uvoptx new file mode 100644 index 0000000..68218f4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/MDK/vc_detect_high_irq.uvoptx @@ -0,0 +1,379 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + vc_detect_high_irq + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + DLGUARM + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U4294967295 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + CW_ADC->RESULT0,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\ADC + 35904 + + + System Viewer\VC1 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_vc.c + cw32f030_vc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_adc.c + cw32f030_adc.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_systick.c + cw32f030_systick.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/MDK/vc_detect_high_irq.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/MDK/vc_detect_high_irq.uvprojx new file mode 100644 index 0000000..8ed4ea4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/MDK/vc_detect_high_irq.uvprojx @@ -0,0 +1,471 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + vc_detect_high_irq + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + vc_detect_high_irq + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_vc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_vc.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_adc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_adc.c + + + cw32f030_systick.c + 1 + ..\..\..\..\Libraries\src\cw32f030_systick.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/USER/inc/main.h new file mode 100644 index 0000000..8b10f5f --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void LED_Init(void); +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..ad961c5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/USER/src/interrupts_cw32f030.c @@ -0,0 +1,414 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_vc.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +extern volatile boolean_t gFlagIrq; +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + VC1_ClearIrq(); + gFlagIrq = TRUE; + VC_DisableNvic(VC1_IRQn); + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/USER/src/main.c new file mode 100644 index 0000000..e81c5e2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/USER/src/main.c @@ -0,0 +1,186 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-08-04 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_systick.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_vc.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +volatile boolean_t gFlagIrq = FALSE; + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief VC I/O初始化 + * + */ +void VC_PortInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOA_Msk); + //打开VC时钟 + REGBITS_SET(CW_SYSCTRL->APBEN2, SYSCTRL_APBEN2_VC_Msk); + //set PA11 as output + GPIO_InitStructure.Pins = GPIO_PIN_11; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + //set PA11 as VC output + PA11_AFx_VC1OUT(); + //set PA00 as VC1_CH0 P-INPUT + PA00_ANALOG_ENABLE(); + //set PA01 as VC1_CH1 N-INPUT + PA01_ANALOG_ENABLE(); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + VC_InitTypeDef VC_InitStruct; + VC_BlankTypeDef VC_BlankStruct; + VC_OutTypeDef VC_OutStruct; + RCC_HSI_Enable(RCC_HSIOSC_DIV2); //配置系统时钟为HSI 24M + InitTick(24000000ul); //初始化SysTick + //LED初始化 + LED_Init(); + //配置测试IO口 + VC_PortInit(); + //VC通道初始化 + VC_InitStruct.VC_InputP = VC_InputP_Ch0; + VC_InitStruct.VC_InputN = VC_InputN_Bgr1P2; //VC_InputN_Ch1; // + VC_InitStruct.VC_Hys = VC_Hys_10mV; + VC_InitStruct.VC_Resp = VC_Resp_High; + VC_InitStruct.VC_FilterEn = VC_Filter_Enable; + VC_InitStruct.VC_FilterClk = VC_FltClk_RC150K; + VC_InitStruct.VC_FilterTime = VC_FltTime_4095Clk; + VC_InitStruct.VC_Window = VC_Window_Disable; + VC_InitStruct.VC_Polarity = VC_Polarity_Low; + VC1_ChannelInit(&VC_InitStruct); + //VC Blank窗口初始化 + VC1VC2_BlankInit(&VC_BlankStruct); + VC1_BlankCfg(&VC_BlankStruct); + //VC输出连接初始化 + VC1VC2_OutInit(&VC_OutStruct); + VC1_OutputCfg(&VC_OutStruct); + //VC中断设置 + VC1_ITConfig(VC_IT_HIGH, ENABLE); + VC1_EnableIrq(VC_INT_PRIORITY); + VC1_ClearIrq(); + VC1_EnableChannel(); + while (1) + { + if (gFlagIrq) + { + PB09_TOG(); + gFlagIrq = FALSE; + SysTickDelay(1000); //1s. + VC_EnableNvic(VC1_IRQn, VC_INT_PRIORITY); + } + } +} + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + //打开GPIO时钟 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOB_Msk); + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + //LEDs are off. + PB08_SETLOW(); + PB09_SETLOW(); +} + +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn */ + uwTick += uwTickFreq; + /* USER CODE END SysTick_IRQn */ +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/readme.txt new file mode 100644 index 0000000..4174e58 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/VC/vc_detect_high_irq/readme.txt @@ -0,0 +1,28 @@ +示例目的： + 演示VC模块的输出信号高电平触发中断功能。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. VC的滤波时钟源为RC150K + 5. PB08/09设置为PUSH-PULL输出 + +演示说明： + VC输入P通道为PA00，N通道为BGR基准电压1.2V，VC输出端口为PA11。 + 外接可调直流电源，当VC输入P通道电压高于N通道电压时，PB09（LED）输出电平翻转。 + 延时1s之后，重新监测VC输入P通道电压，如果仍然高于N通道电压时，PB09输出电平继续翻转； + 如果低于N通道电压时，PB09输出电平不变。 + +使用说明： ++ EWARM + 1. 打开vc_detect_high_irq.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开vc_detect_high_irq.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/EWARM/project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/EWARM/project.ewd new file mode 100644 index 0000000..7026791 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/EWARM/project.ewd @@ -0,0 +1,3276 @@ + + + 4 + + Release + + ARM + + 0 + + C-SPY + 2 + + 33 + 1 + 0 + + + + + + + + + + + + + + + + + + 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a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/EWARM/project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/EWARM/project.ewp new file mode 100644 index 0000000..be59898 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/EWARM/project.ewp @@ -0,0 +1,2219 @@ + + + 4 + + Release + + ARM + + 0 + + General + 3 + + 36 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 38 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + ILINK + 0 + + 27 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + debug + + ARM + + 0 + + General + 3 + + 36 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 38 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + ILINK + 0 + + 27 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + ::CMSIS + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_wwdt.c + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + $PROJ_DIR$\..\USER\src\main.c + + + + Utilities + + $PROJ_DIR$\..\..\..\..\Utilities\cw32f030c8t6_startkit.c + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/EWARM/project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/EWARM/project.eww new file mode 100644 index 0000000..bc949a7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/EWARM/project.eww @@ -0,0 +1,6 @@ + + + $WS_DIR$\project.ewp + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/MDK/project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/MDK/project.uvoptx new file mode 100644 index 0000000..82b8d99 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/MDK/project.uvoptx @@ -0,0 +1,350 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + WWDT + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_wwdt.c + cw32f030_wwdt.c + 0 + 0 + + + + + Utilities + 0 + 0 + 0 + 0 + + 4 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Utilities\cw32f030c8t6_startkit.c + cw32f030c8t6_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/MDK/project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/MDK/project.uvprojx new file mode 100644 index 0000000..c00f73c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/MDK/project.uvprojx @@ -0,0 +1,466 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + WWDT + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + WWDT + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\Utilities + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + cw32f030_wwdt.c + 1 + ..\..\..\..\Libraries\src\cw32f030_wwdt.c + + + + + Utilities + + + cw32f030c8t6_startkit.c + 1 + ..\..\..\..\Utilities\cw32f030c8t6_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/USER/inc/main.h new file mode 100644 index 0000000..f065164 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/USER/inc/main.h @@ -0,0 +1,68 @@ +/** + * @file main.h + * @author WHXY + * @brief Header for main.c file. + * This file contains the common defines of the application. + * @version 0.1 + * @date 2021-04-22 + * + * @copyright Copyright (c) 2021 + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "cw32f030_wwdt.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030c8t6_startkit.h" +#include "cw32f030_flash.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..aed0e85 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/USER/src/interrupts_cw32f030.c @@ -0,0 +1,406 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +__weak void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/USER/src/main.c new file mode 100644 index 0000000..020604f --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/USER/src/main.c @@ -0,0 +1,212 @@ +/** + * @file main.c + * @author WHXY + * @brief 本示例，系统时钟由HSI提供，通过PLL倍频到48MHz。 + * -配置WWDT喂狗窗口246~350ms，允许预溢出中断 + * -配置系统节拍配置为每 250 ms 产生一个中断，中断复位程序中闪烁 LED1（PB9），并 + * 喂狗。 + * -PA1 引脚连接的按钮S1配置为在其下降沿上产生中断 + * -在 NVIC 中，将PA1对应中断向量且优先级等于0，并且 SysTick 中断向量优先级设置 + * 为 1（PA1的中断优先于 SysTick 中断）。 + * - 按钮S1（PA1）用于模拟软件故障：S1按下后，进入对应的中断服务程序，且中断标志 + * 位不清零，CPU不会进入入系统节拍中断例程，因此不会重载WWDT计数器。 + * 当WWDT计数器预溢出时，WWDT将产生一个POV中断。 + * 程序发生WWDT中断后，LED1长亮，延后2个喂狗周期后，系统复位。 + * 若系统发生过WWDT复位，则LED2亮。 + * @version 0.1 + * @date 2021-04-22 + * + * @copyright Copyright (c) 2021 + * + *代码许可和免责信息 + *武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + *生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + *导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + *含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + *或条件。 + *无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + *即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + *或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + *损失。 + *某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + *全部上述排除或限制可能并不适用于您。 + *******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +static void WWDT_Config(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +LED_InitTypeDef LED1, LED2; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + RCC_Configuration(); + /* GPIO Configuration */ + GPIO_Configuration(); + /* LED 初始化 */ + LED1.LED_Port = CW_GPIOB; + LED1.LED_Pin = GPIO_PIN_9; + LED_Init(&LED1); + LED1.LED_On(&LED1); + LED2.LED_Port = CW_GPIOB; + LED2.LED_Pin = GPIO_PIN_8; + LED_Init(&LED2); + LED2.LED_Off(&LED2); + /* 节拍定时器初始化 */ + SysTick_Config(SystemCoreClock / 1000 * 250); // 250ms 产生一次中断 + /* 配置WWDT */ + WWDT_Config(); + /* NVIC Configuration */ + NVIC_Configuration(); + if (RCC_GetRstFlag(RCC_FLAG_WWDTRST)) + { + LED2.LED_On(&LED2); + } + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + /* 0. HSI使能并校准 */ + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + /* 1. 设置HCLK和PCLK的分频系数　*/ + RCC_HCLKPRS_Config(RCC_HCLK_DIV1); + RCC_PCLKPRS_Config(RCC_PCLK_DIV1); + /* 2. 使能PLL，通过HSI倍频到48MHz */ + RCC_PLL_Enable(RCC_PLLSOURCE_HSI, 8000000, 6); // HSI 默认输出频率8MHz + RCC_PLL_OUT(); + ///< 当使用的时钟源HCLK大于24M,小于等于48MHz：设置FLASH 读等待周期为2 cycle + __RCC_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_2); + /* 3. 时钟切换到PLL */ + RCC_SysClk_Switch(RCC_SYSCLKSRC_PLL); + RCC_SystemCoreClockUpdate(48000000); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + __RCC_GPIOA_CLK_ENABLE(); + /* 配置PA1为按键输入 */ + GPIO_InitStruct.IT = GPIO_IT_FALLING; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_1; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_SetPriority(SysTick_IRQn, 1); + NVIC_SetPriority(GPIOA_IRQn, 0); + NVIC_SetPriority(WDT_IRQn, 0); + NVIC_EnableIRQ(WDT_IRQn); + NVIC_EnableIRQ(GPIOA_IRQn); + __enable_irq(); +} + +static void WWDT_Config(void) +{ + WWDT_InitTypeDef WWDT_InitStruct = {0}; + __RCC_WWDT_CLK_ENABLE(); + WWDT_InitStruct.WWDT_CounterValue = 0x7F; + WWDT_InitStruct.WWDT_ITState = ENABLE; + WWDT_InitStruct.WWDT_Prescaler = WWDT_Prescaler_DIV262144; // 183Hz,T=5.46ms + WWDT_InitStruct.WWDT_WindowValue = 82; + WWDT_Init(&WWDT_InitStruct); + WWDT_Cmd(); +} + +void SysTick_Handler(void) +{ + WWDT_FEED(0x7F); + LED1.LED_Toggle(&LED1); +} + +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + static uint8_t flag = 0; + WWDT_ClearFlag(); + if (flag < 2) + { + WWDT_FEED(0x7F); + LED1.LED_On(&LED1); // 首次中断后，喂2次狗，LED1常亮，指示要复位 + flag++; + } + /* USER CODE END */ +} +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** +* @brief Reports the name of the source file and the source line number +* where the assert_param error has occurred. +* @param file: pointer to the source file name +* @param line: assert_param error line source number +* @retval None +*/ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/readme.txt new file mode 100644 index 0000000..2f3c497 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/WWDT/WWDT/readme.txt @@ -0,0 +1,38 @@ +示例目的： + 模拟软件发生故障时，窗口看门狗WWDT复位系统的功能。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为PLL，由HSI提供的8MHz时钟6倍频到48MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=48MHz + 4. WWDT由PCLK经262144分频，即5.46ms计数一次 + 5. PB09设置为PUSH-PULL输出 + 6. PB08设置为PUSH-PULL输出 + 7. PA01设置为输入 + 8. 系统节拍定时器设置为250ms产生一次中断 + +演示说明： + 系统时钟由HSI提供，通过PLL倍频到48MHz。配置WWDT喂狗窗口246~350ms（窗口范围0x52~0x40），允许预溢出中断， + 系统节拍配置为每 250 ms 产生一个中断，中断复位程序中闪烁 LED1（PB9），并喂狗。 + PA1 引脚连接的按钮S1配置为在其下降沿上产生中断。 + 在 NVIC 中，将PA1对应中断向量且优先级等于0，并且 SysTick 中断向量优先级设置为1 + （PA1的中断优先于 SysTick 中断）。 + 按钮KEY1（PA1）用于模拟软件故障：KEY1按下后，进入对应的中断服务程序，且中断标志 + 位不清零，CPU不会进入系统节拍中断服务程序，因此不会重载WWDT计数器。 + 当WWDT计数器预溢出时，WWDT将产生一个POV中断。 + 程序发生WWDT中断后，LED1长亮，延后2个喂狗周期后，系统复位。 + 若系统发生过WWDT复位，则LED2亮。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/cleanup.bat b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/cleanup.bat new file mode 100644 index 0000000..0f0ba62 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/cleanup.bat @@ -0,0 +1,53 @@ +del *.bak /s +del *.orig /s +:: keil +del *.axf /s +del *.htm /s +del *.hex /s +del *.lnp /s +del *.sct /s +del *.crf /s +del *.d /s +del *.o /s +del *.dep /s +del *.map /s +del *.lst /s +del *.i /s +del *.scvd /s +del *.uvguix.* /s +del *.Socrates /s +del /s/q output +del JLink*.* /s + +:: IAR +rem del *.hex /s +del *.out /s +del *.sim /s +del *.linf /s +del *.pbi /s +rem del *.o /s +del *.xcl /s +del *.browse /s +del *.pbd /s +del *.pbw /s +del Backup*.ewp /s +del *.ewt /s +del *.reggroups /s +del *.crun /s +del *.dbgdt /s +del *.cspy.* /s +del *.wsdt /s +del *.jlink /s + +del *.svd /s +del *.bak /s + +cd %~dp0 +for /F "delims=" %%a in ('dir /ad/s/b output') do rd /s/q "%%~a" +for /F "delims=" %%a in ('dir /ad/s/b settings') do rd /s/q "%%~a" +for /F "delims=" %%a in ('dir /ad/s/b Release') do rd /s/q "%%~a" +for /F "delims=" %%a in ('dir /ad/s/b RTE') do rd /s/q "%%~a" +for /F "delims=" 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$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/EWARM/Project.ewp new file mode 100644 index 0000000..abe4fac --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/EWARM/Project.ewp @@ -0,0 +1,2148 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_crc.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/MDK/crc_calc.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/MDK/crc_calc.uvoptx new file mode 100644 index 0000000..90bb4af --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/MDK/crc_calc.uvoptx @@ -0,0 +1,326 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + crc_calc + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + tmp1 + + + 1 + 1 + tmp2 + + + 2 + 1 + tmp3 + + + + + 0 + 2 + tmp2 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 1 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_crc.c + cw32f030_crc.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/MDK/crc_calc.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/MDK/crc_calc.uvprojx new file mode 100644 index 0000000..4db7700 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/MDK/crc_calc.uvprojx @@ -0,0 +1,444 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + crc_calc + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + crc_calc + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_crc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_crc.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/USER/inc/main.h new file mode 100644 index 0000000..208c89a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/USER/inc/main.h @@ -0,0 +1,68 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/USER/src/main.c new file mode 100644 index 0000000..16ba5ea --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/USER/src/main.c @@ -0,0 +1,174 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-25 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_crc.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** 计算CRC16 / CRC32 + ** + ******************************************************************************/ + +//========================================================================= + +uint32_t tmp1, tmp2, tmp3; + +//========================================================================= + +int32_t main(void) +{ + uint8_t Raw08[8] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77 }; + uint16_t Raw16[4] = { 0x1100, 0x3322, 0x5544, 0x7766 }; + uint32_t Raw32[2] = { 0x33221100, 0x77665544 }; + //========================================================================= + //enable CRC CLK + CW_SYSCTRL->AHBEN_f.CRC = 1; + //========================================================================= + //CRC16_IBM 采用三种位宽计算CRC16值，其结果应相同 + tmp1 = CRC16_Calc_8bit(CRC16_IBM, Raw08, 8); //按Byte计算CRC16 + tmp2 = CRC16_Calc_16bit(CRC16_IBM, Raw16, 4); //按HalfWord计算CRC16 + tmp3 = CRC16_Calc_32bit(CRC16_IBM, Raw32, 2); //按Word计算CRC16 + __asm("BKPT 0"); //请在此处观察tmp1/tmp2/tmp3的值是否相等 + //========================================================================= + //CRC16_MAXIM 采用三种位宽计算CRC16值，其结果应相同 + tmp1 = CRC16_Calc_8bit(CRC16_MAXIM, Raw08, 8); //按Byte计算CRC16 + tmp2 = CRC16_Calc_16bit(CRC16_MAXIM, Raw16, 4); //按HalfWord计算CRC16 + tmp3 = CRC16_Calc_32bit(CRC16_MAXIM, Raw32, 2); //按Word计算CRC16 + __asm("BKPT 0"); //请在此处观察tmp1/tmp2/tmp3的值是否相等 + //========================================================================= + //CRC16_USB 采用三种位宽计算CRC16值，其结果应相同 + tmp1 = CRC16_Calc_8bit(CRC16_USB, Raw08, 8); //按Byte计算CRC16 + tmp2 = CRC16_Calc_16bit(CRC16_USB, Raw16, 4); //按HalfWord计算CRC16 + tmp3 = CRC16_Calc_32bit(CRC16_USB, Raw32, 2); //按Word计算CRC16 + __asm("BKPT 0"); //请在此处观察tmp1/tmp2/tmp3的值是否相等 + //========================================================================= + //CRC16_MODBUS 采用三种位宽计算CRC16值，其结果应相同 + tmp1 = CRC16_Calc_8bit(CRC16_MODBUS, Raw08, 8); //按Byte计算CRC16 + tmp2 = CRC16_Calc_16bit(CRC16_MODBUS, Raw16, 4); //按HalfWord计算CRC16 + tmp3 = CRC16_Calc_32bit(CRC16_MODBUS, Raw32, 2); //按Word计算CRC16 + __asm("BKPT 0"); //请在此处观察tmp1/tmp2/tmp3的值是否相等 + //========================================================================= + //CRC16_CCITT 采用三种位宽计算CRC16值，其结果应相同 + tmp1 = CRC16_Calc_8bit(CRC16_CCITT, Raw08, 8); //按Byte计算CRC16 + tmp2 = CRC16_Calc_16bit(CRC16_CCITT, Raw16, 4); //按HalfWord计算CRC16 + tmp3 = CRC16_Calc_32bit(CRC16_CCITT, Raw32, 2); //按Word计算CRC16 + __asm("BKPT 0"); //请在此处观察tmp1/tmp2/tmp3的值是否相等 + //========================================================================= + //CRC16_CCITTFALSE 采用三种位宽计算CRC16值，其结果应相同 + tmp1 = CRC16_Calc_8bit(CRC16_CCITTFALSE, Raw08, 8); //按Byte计算CRC16 + tmp2 = CRC16_Calc_16bit(CRC16_CCITTFALSE, Raw16, 4); //按HalfWord计算CRC16 + tmp3 = CRC16_Calc_32bit(CRC16_CCITTFALSE, Raw32, 2); //按Word计算CRC16 + __asm("BKPT 0"); //请在此处观察tmp1/tmp2/tmp3的值是否相等 + //========================================================================= + //CRC16_X25 采用三种位宽计算CRC16值，其结果应相同 + tmp1 = CRC16_Calc_8bit(CRC16_X25, Raw08, 8); //按Byte计算CRC16 + tmp2 = CRC16_Calc_16bit(CRC16_X25, Raw16, 4); //按HalfWord计算CRC16 + tmp3 = CRC16_Calc_32bit(CRC16_X25, Raw32, 2); //按Word计算CRC16 + __asm("BKPT 0"); //请在此处观察tmp1/tmp2/tmp3的值是否相等 + //========================================================================= + //CRC16_XMODEM 采用三种位宽计算CRC16值，其结果应相同 + tmp1 = CRC16_Calc_8bit(CRC16_XMODEM, Raw08, 8); //按Byte计算CRC16 + tmp2 = CRC16_Calc_16bit(CRC16_XMODEM, Raw16, 4); //按HalfWord计算CRC16 + tmp3 = CRC16_Calc_32bit(CRC16_XMODEM, Raw32, 2); //按Word计算CRC16 + __asm("BKPT 0"); //请在此处观察tmp1/tmp2/tmp3的值是否相等 + //========================================================================= + //CRC32_DEFAULT 采用三种位宽计算CRC32值，其结果应相同 + tmp1 = CRC32_Calc_8bit(CRC32_DEFAULT, Raw08, 8); //按Byte计算CRC32 + tmp2 = CRC32_Calc_16bit(CRC32_DEFAULT, Raw16, 4); //按HalfWord计算CRC32 + tmp3 = CRC32_Calc_32bit(CRC32_DEFAULT, Raw32, 2); //按Word计算CRC32 + __asm("BKPT 0"); //请在此处观察tmp1/tmp2/tmp3的值是否相等 + //========================================================================= + //CRC32_MPEG2 采用三种位宽计算CRC32值，其结果应相同 + tmp1 = CRC32_Calc_8bit(CRC32_MPEG2, Raw08, 8); //按Byte计算CRC32 + tmp2 = CRC32_Calc_16bit(CRC32_MPEG2, Raw16, 4); //按HalfWord计算CRC32 + tmp3 = CRC32_Calc_32bit(CRC32_MPEG2, Raw32, 2); //按Word计算CRC32 + __asm("BKPT 0"); //请在此处观察tmp1/tmp2/tmp3的值是否相等 + while (1) + { + ; + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/readme.txt new file mode 100644 index 0000000..9eb7176 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/crc/crc_calc/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 测试10种不同CRC算法在3种不同输入位宽方式下的计算结果是否相同。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + +演示说明： + 通过调试工具，结合软件断点，依次观察10种不同算法模式在3种不同输入数据位宽方式下得到的结果是否相同。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/EWARM/Project.ewd new file mode 100644 index 0000000..31f9e8e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/EWARM/Project.ewd @@ -0,0 +1,3104 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 32 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/EWARM/Project.ewp new file mode 100644 index 0000000..cfbbf98 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/EWARM/Project.ewp @@ -0,0 +1,2182 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 27 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 35 + 1 + 0 + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + $PROJ_DIR$\..\USER\src\main.c + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/MDK/flash_EraseWrite.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/MDK/flash_EraseWrite.uvoptx new file mode 100644 index 0000000..6c5d0bb --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/MDK/flash_EraseWrite.uvoptx @@ -0,0 +1,334 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + flash_EraseWrite + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030 -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM)) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + 0 + 71 + 1 +
1164
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\flash_EraseWrite\../USER/src/main.c\71 + + + + + 1 + 0 + 0 + 0 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/MDK/flash_EraseWrite.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/MDK/flash_EraseWrite.uvprojx new file mode 100644 index 0000000..12ae606 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/MDK/flash_EraseWrite.uvprojx @@ -0,0 +1,449 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + flash_EraseWrite + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030 -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + flash_EraseWrite + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/USER/inc/main.h new file mode 100644 index 0000000..2f6160d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/USER/src/main.c new file mode 100644 index 0000000..278912e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/USER/src/main.c @@ -0,0 +1,160 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-25 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_flash.h" +#include "cw32f030_gpio.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint8_t AddrBuf[256]; + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Main function of project + * //对PAGE127进行擦除，并验证。 + * //对PAGE127进行写入，并验证。 + * @return int32_t + */ + +int32_t main(void) +{ + uint8_t Flag, tmp8; + uint16_t i; + //时钟初始化 + RCC_Configuration(); + //PB8/PB9 推挽输出 + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + PB08_SETLOW(); + PB09_SETLOW(); + //erase + FLASH_UnlockPages(512 * 127, 512 * 127); //解锁最后一个页面 + Flag = FLASH_ErasePages(512 * 127, 512 * 127); //擦除最后一个页面 + FLASH_LockAllPages(); + if (Flag) + { + while (1); //擦除失败 + } + for (i = 0; i <= 255; i++) + { + tmp8 = *((volatile uint8_t *)(512 * 127 + i)); + if (tmp8 != 0xFF) + { + while (1); //对擦除后的结果进行验证失败 + } + } + //write + for (i = 0; i <= 255; i++) + { + AddrBuf[i] = i; + } + FLASH_UnlockPages(512 * 127, 512 * 127); //解锁最后一个页面 + Flag = FLASH_WriteBytes(512 * 127, AddrBuf, 256); + FLASH_LockAllPages(); + if (Flag) + { + while (1); //写入失败 + } + //read + for (i = 0; i <= 255; i++) + { + tmp8 = *((volatile uint8_t *)(512 * 127 + i)); + if (tmp8 != i) + { + while (1); //对写入的数据进行验证失败 + } + } + //结束 + while (1) + { + PB08_TOG(); + PB09_TOG(); + FirmwareDelay(1000000); + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + CW_SYSCTRL->AHBEN_f.FLASH = 1; + CW_SYSCTRL->AHBEN_f.GPIOB = 1; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/readme.txt new file mode 100644 index 0000000..d28aef8 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/flash/flash_EraseWrite/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 对MCU内置的FLASH的最后一个页面（第127页）依次进行擦除/写/读操作，并对比写入和读取的数据是否一致。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + +演示说明： + 采用默认时钟配置，开启FLASH的操作时钟。依次对MCU内置FLASH的最后一个页面（127页）进行擦除、写以及读取，然后对比写入和读取的数据是否相同。如果擦除、写、读取数据操作或者读写数据不一致则挂起，否则完成后会闪灯提示。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/EWARM/Project.ewd new file mode 100644 index 0000000..82cfe5c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/EWARM/Project.ewd @@ -0,0 +1,3088 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 32 + 1 + 0 + + + + + + + + + + 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XDS100_ID + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + debug + + ARM + + 0 + + C-SPY + 2 + + 32 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/EWARM/Project.ewp new file mode 100644 index 0000000..ca4550a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/EWARM/Project.ewp @@ -0,0 +1,2153 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + 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$PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + $PROJ_DIR$\..\USER\src\main.c + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/MDK/Project.uvoptx new file mode 100644 index 0000000..3298008 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/MDK/Project.uvoptx @@ -0,0 +1,360 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U4294967295 -O206 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FN1 -FC1000 -FD20000000 -FF0FlashCW32F030 -FL010000 -FS00 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + 0 + 0 + 84 + 1 +
1002
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\Project\../USER/src/main.c\84 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\GPIOB + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/MDK/Project.uvprojx new file mode 100644 index 0000000..d42cf73 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/MDK/Project.uvprojx @@ -0,0 +1,462 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.5 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030 -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/USER/inc/main.h new file mode 100644 index 0000000..ea85b13 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/USER/inc/main.h @@ -0,0 +1,64 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030_systick.h" +#include "interrupts_cw32f030.h" +#include "system_cw32f030.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..fa7e9c2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/USER/src/interrupts_cw32f030.c @@ -0,0 +1,406 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/USER/src/main.c new file mode 100644 index 0000000..e6b9b2b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/USER/src/main.c @@ -0,0 +1,120 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define LED_GPIO_PORT CW_GPIOB +#define LED_GPIO_PINS GPIO_PIN_8 | GPIO_PIN_9 + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +void Delay(uint16_t nCount); +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** LED1, LED2闪烁 + ** + ******************************************************************************/ +int32_t main(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + __RCC_GPIOB_CLK_ENABLE(); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = LED_GPIO_PINS; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(LED_GPIO_PORT, &GPIO_InitStruct); + while (1) + { + GPIO_TogglePin(LED_GPIO_PORT, LED_GPIO_PINS); + Delay(0xFFFF); + } +} + +/** + * @brief 循环延时 + * + * @param nCount + */ +void Delay(__IO uint16_t nCount) +{ + /* Decrement nCount value */ + while (nCount != 0) + { + nCount--; + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/readme.txt new file mode 100644 index 0000000..8cb5bc3 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_blink/readme.txt @@ -0,0 +1,24 @@ +示例目的： + 演示GPIO的位翻转 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. PB08， PB09设置为PUSH-PULL输出 + +演示说明： + LED1和LED2闪烁。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/EWARM/Project.ewd new file mode 100644 index 0000000..74ca909 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/EWARM/Project.ewd @@ -0,0 +1,1456 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/EWARM/Project.ewp new file mode 100644 index 0000000..7860bf2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/EWARM/Project.ewp @@ -0,0 +1,2154 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/MDK/Project.uvoptx new file mode 100644 index 0000000..502ee03 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/MDK/Project.uvoptx @@ -0,0 +1,326 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/MDK/Project.uvprojx new file mode 100644 index 0000000..fd0f3ca --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/MDK/Project.uvprojx @@ -0,0 +1,454 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/USER/inc/main.h new file mode 100644 index 0000000..99a97f0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030_systick.h" +#include "interrupts_cw32f030.h" +#include "system_cw32f030.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..fa7e9c2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/USER/src/interrupts_cw32f030.c @@ -0,0 +1,406 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/USER/src/main.c new file mode 100644 index 0000000..4edd7d1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/USER/src/main.c @@ -0,0 +1,104 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** 从PA03/PA04输出HCLK及PCLK，并翻转PA05管脚 + ** + ******************************************************************************/ +int32_t main(void) +{ + CW_SYSCTRL->AHBEN_f.GPIOA = 1; //Open GPIOA Clk + //配置PA3,PA4,PA5为输出 + REGBITS_CLR(CW_GPIOA->ANALOG, bv3 | bv4 | bv5); //当同时操作多个管脚时建议使用REGBITS_xxx宏以提高效率 + REGBITS_CLR(CW_GPIOA->DIR, bv3 | bv4 | bv5); + PA03_AFx_PCLKOUT(); //配置PA03输出PCLK + PA04_AFx_HCLKOUT(); //配置PA04输出HCLK + while (1) + { + CW_GPIOA->TOG = bv5; //翻转PA05 + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/readme.txt new file mode 100644 index 0000000..3d358c1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_hclk_pclk/readme.txt @@ -0,0 +1,24 @@ +示例目的： + 演示GPIO复用为PCLK、HCLK时钟的输出脚。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. PA3作为PCLK输出、PA4作为HCLK输出、PA5普通输出 + +演示说明： + PA3、PA4输出8MHz的时钟，PA5翻转。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/EWARM/Project.ewd new file mode 100644 index 0000000..74ca909 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/EWARM/Project.ewd @@ -0,0 +1,1456 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/EWARM/Project.ewp new file mode 100644 index 0000000..7860bf2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/EWARM/Project.ewp @@ -0,0 +1,2154 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/MDK/Project.uvoptx new file mode 100644 index 0000000..ba16f9e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/MDK/Project.uvoptx @@ -0,0 +1,326 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/MDK/Project.uvprojx new file mode 100644 index 0000000..eea29ec --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/MDK/Project.uvprojx @@ -0,0 +1,455 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/USER/inc/main.h new file mode 100644 index 0000000..99a97f0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030_systick.h" +#include "interrupts_cw32f030.h" +#include "system_cw32f030.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..fa7e9c2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/USER/src/interrupts_cw32f030.c @@ -0,0 +1,406 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/USER/src/main.c new file mode 100644 index 0000000..600d0e5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/USER/src/main.c @@ -0,0 +1,131 @@ + +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle GPIOA + ** + ******************************************************************************/ +int32_t main(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + CW_SYSCTRL->AHBEN_f.GPIOA = 1; //Open GPIOA Clk + //set PA00 / PA01 / PA02 / PA03 as output + GPIO_InitStruct.Pins = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + //set PA08 / PA09 as inupt with pur / int = none + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + while (1) + { + //----------------------------------------------------------------------- + //以下调用函数法读写PIN + if (GPIO_ReadPin(CW_GPIOA, GPIO_PIN_8)) + { + GPIO_WritePin(CW_GPIOA, GPIO_PIN_0 | GPIO_PIN_1, GPIO_Pin_SET); + } + else + { + GPIO_WritePin(CW_GPIOA, GPIO_PIN_0 | GPIO_PIN_1, GPIO_Pin_RESET); + } + //----------------------------------------------------------------------- + //以下采用宏读写PIN + if (PA09_GETVALUE()) + { + PA02_SETHIGH(); + PA03_TOG(); + } + else + { + PA02_SETLOW(); + } + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/readme.txt new file mode 100644 index 0000000..cb96109 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_input_output/readme.txt @@ -0,0 +1,24 @@ +示例目的： + 演示GPIO通过库函数和宏定义的方法完整初始化配置和输入输出的读写操作 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. PA00 / PA01 / PA02 / PA03 输出，PA08 / PA09输入上拉 + +演示说明： + 。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/EWARM/Project.ewd new file mode 100644 index 0000000..74ca909 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/EWARM/Project.ewd @@ -0,0 +1,1456 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/EWARM/Project.ewp new file mode 100644 index 0000000..7860bf2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/EWARM/Project.ewp @@ -0,0 +1,2154 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/MDK/Project.uvoptx new file mode 100644 index 0000000..ba16f9e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/MDK/Project.uvoptx @@ -0,0 +1,326 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/MDK/Project.uvprojx new file mode 100644 index 0000000..eea29ec --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/MDK/Project.uvprojx @@ -0,0 +1,455 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/USER/inc/main.h new file mode 100644 index 0000000..99a97f0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030_systick.h" +#include "interrupts_cw32f030.h" +#include "system_cw32f030.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..ec52b4a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/USER/src/interrupts_cw32f030.c @@ -0,0 +1,408 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +extern void GPIOA_IRQHandlerCallback(void); +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + GPIOA_IRQHandlerCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/USER/src/main.c new file mode 100644 index 0000000..b7b5ab7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/USER/src/main.c @@ -0,0 +1,123 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define LED_GPIO_PORT CW_GPIOB +#define LED_GPIO_PINS GPIO_PIN_8 | GPIO_PIN_9 +#define KEY_GPIO_PORT CW_GPIOA +#define KEY_GPIO_PINS GPIO_PIN_1 | GPIO_PIN_2 +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * + * @return int32_t + */ +int32_t main(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + __RCC_GPIOA_CLK_ENABLE(); // 使能GPIO的配置时钟 + __RCC_GPIOB_CLK_ENABLE(); + GPIO_InitStruct.IT = GPIO_IT_RISING | GPIO_IT_FALLING; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = KEY_GPIO_PINS; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(KEY_GPIO_PORT, &GPIO_InitStruct); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = LED_GPIO_PINS; + GPIO_Init(LED_GPIO_PORT, &GPIO_InitStruct); + //清除PA00中断标志并使能NVIC + GPIOA_INTFLAG_CLR(bv1 | bv2); + NVIC_EnableIRQ(GPIOA_IRQn); + //---------------------------------------------------------------------- + //相关程序在中断服务GPIOA_IRQHandler中进行处理 + while (1) + { + } +} + +void GPIOA_IRQHandlerCallback(void) +{ + if (CW_GPIOA->ISR_f.PIN1) + { + GPIOA_INTFLAG_CLR(bv1); + PB09_TOG(); + } + if (CW_GPIOA->ISR_f.PIN2) + { + GPIOA_INTFLAG_CLR(bv2); + PB08_TOG(); + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/readme.txt new file mode 100644 index 0000000..dd0cf4b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_default/readme.txt @@ -0,0 +1,25 @@ +示例目的： + 演示GPIO的默认中断的使用 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. PA01，PA02 中断输入，PB01， PB02输出 + +演示说明： + 按下KEY1，LED1的状态改变，松开KEY1， LED1的状态改变。 + 按下KEY2，LED2的状态改变，松开KEY2， LED2的状态改变。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/EWARM/Project.ewd new file mode 100644 index 0000000..74ca909 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/EWARM/Project.ewd @@ -0,0 +1,1456 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/EWARM/Project.ewp new file mode 100644 index 0000000..7860bf2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/EWARM/Project.ewp @@ -0,0 +1,2154 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/MDK/Project.uvoptx new file mode 100644 index 0000000..ba16f9e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/MDK/Project.uvoptx @@ -0,0 +1,326 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/MDK/Project.uvprojx new file mode 100644 index 0000000..eea29ec --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/MDK/Project.uvprojx @@ -0,0 +1,455 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/USER/inc/main.h new file mode 100644 index 0000000..99a97f0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030_systick.h" +#include "interrupts_cw32f030.h" +#include "system_cw32f030.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..ec52b4a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/USER/src/interrupts_cw32f030.c @@ -0,0 +1,408 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +extern void GPIOA_IRQHandlerCallback(void); +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + GPIOA_IRQHandlerCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/USER/src/main.c new file mode 100644 index 0000000..1f4d1fd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/USER/src/main.c @@ -0,0 +1,125 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define LED_GPIO_PORT CW_GPIOB +#define LED_GPIO_PINS GPIO_PIN_8 | GPIO_PIN_9 +#define KEY_GPIO_PORT CW_GPIOA +#define KEY_GPIO_PINS GPIO_PIN_1 | GPIO_PIN_2 +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * + * @return int32_t + */ +int32_t main(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + __RCC_GPIOA_CLK_ENABLE(); // 使能GPIO的配置时钟 + __RCC_GPIOB_CLK_ENABLE(); + GPIO_InitStruct.IT = GPIO_IT_RISING | GPIO_IT_FALLING; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = KEY_GPIO_PINS; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(KEY_GPIO_PORT, &GPIO_InitStruct); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = LED_GPIO_PINS; + GPIO_Init(LED_GPIO_PORT, &GPIO_InitStruct); + //配置中断滤波 + GPIO_ConfigFilter(CW_GPIOA, bv1, GPIO_FLTCLK_RC150K); + //清除PA00中断标志并使能NVIC + GPIOA_INTFLAG_CLR(bv1 | bv2); + NVIC_EnableIRQ(GPIOA_IRQn); + //---------------------------------------------------------------------- + //相关程序在中断服务GPIOA_IRQHandler中进行处理 + while (1) + { + } +} + +void GPIOA_IRQHandlerCallback(void) +{ + if (CW_GPIOA->ISR_f.PIN1) + { + GPIOA_INTFLAG_CLR(bv1); + PB09_TOG(); + } + if (CW_GPIOA->ISR_f.PIN2) + { + GPIOA_INTFLAG_CLR(bv2); + PB08_TOG(); + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/readme.txt new file mode 100644 index 0000000..1c16aee --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_int_filter/readme.txt @@ -0,0 +1,25 @@ +示例目的： + 演示GPIO的中断滤波的使用 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. PA01，PA02 中断输入，PB01， PB02输出 + +演示说明： + 按下KEY1，LED1的状态改变，松开KEY1， LED1的状态改变。 + 按下KEY2，LED2的状态改变，松开KEY2， LED2的状态改变。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/EWARM/Project.ewd new file mode 100644 index 0000000..74ca909 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/EWARM/Project.ewd @@ -0,0 +1,1456 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/EWARM/Project.ewp new file mode 100644 index 0000000..078cd79 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/EWARM/Project.ewp @@ -0,0 +1,2157 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_systick.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/MDK/Project.uvoptx new file mode 100644 index 0000000..553a5cc --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/MDK/Project.uvoptx @@ -0,0 +1,338 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_systick.c + cw32f030_systick.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/MDK/Project.uvprojx new file mode 100644 index 0000000..bab4824 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/MDK/Project.uvprojx @@ -0,0 +1,459 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + cw32f030_systick.c + 1 + ..\..\..\..\Libraries\src\cw32f030_systick.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/USER/inc/main.h new file mode 100644 index 0000000..99a97f0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030_systick.h" +#include "interrupts_cw32f030.h" +#include "system_cw32f030.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..fa7e9c2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/USER/src/interrupts_cw32f030.c @@ -0,0 +1,406 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/USER/src/main.c new file mode 100644 index 0000000..a24536c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/USER/src/main.c @@ -0,0 +1,131 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** 将SWD端口配置成通用GPIO功能 + ** + ******************************************************************************/ +int32_t main(void) +{ + uint32_t tmp32; + //================================================================================ + //复位后延时2秒再将SWD接口变成GPIO，防止芯片被锁死 + InitTick(8000000); //SYSTICK 的工作频率为8MHz，每ms中断一次 + SysTickDelay(2000); + //================================================================================ + //Open GPIOA Clk + CW_SYSCTRL->AHBEN_f.GPIOA = 1; + //将PA13 / PA14 配置成通用GPIO功能 + GPIO_SWD2GPIO(); + //配置 PA13 / PA14 为数字功能 - 输出 + REGBITS_CLR(CW_GPIOA->ANALOG, bv13 | bv14); + REGBITS_CLR(CW_GPIOA->DIR, bv13 | bv14); + tmp32 = GetTick() + 10000; + while (GetTick() < tmp32) //在10秒内为GPIO功能 + { + PA13_SETHIGH(); + PA14_SETHIGH(); + PA14_SETLOW(); + PA13_SETLOW(); + PA14_SETHIGH(); + PA14_SETLOW(); + } + //================================================================================ + //配置 PA13 / PA14 为UART1.RXD / UART1.TXD + REGBITS_CLR(CW_GPIOA->ANALOG, bv13 | bv14); //设置PA13/PA14为数字功能 + REGBITS_MODIFY(CW_GPIOA->DIR, bv13 | bv14, bv13); //设置PA13为输入，PA14为输出 + PA13_AFx_UART1RXD(); //配置PA13为UART1.RXD + PA14_AFx_UART1TXD(); //配置PA14为UART1.TXD + //================================================================================ + while (1) + { + ; + } + //================================================================================ +} + +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn */ + uwTick += uwTickFreq; + /* USER CODE END SysTick_IRQn */ +} +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/readme.txt new file mode 100644 index 0000000..5384744 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_swd_io/readme.txt @@ -0,0 +1,25 @@ +示例目的： + 演示SWD端口配置为GPIO和UART端口功能。 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. PA13和PA14 + +演示说明： + 程序上电2S后，PA13和PA14从默认的SWD功能切换为GPIO，PA13和PA14在电平翻转10秒 + 后，功能切换为UART1的RXD和TXD. + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/EWARM/Project.ewd new file mode 100644 index 0000000..74ca909 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/EWARM/Project.ewd @@ -0,0 +1,1456 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/EWARM/Project.ewp new file mode 100644 index 0000000..7860bf2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/EWARM/Project.ewp @@ -0,0 +1,2154 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32f030.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/EWARM/Project.eww new file mode 100644 index 0000000..b38d0cd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/EWARM/Project.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\Project.ewp + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/MDK/Project.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/MDK/Project.uvoptx new file mode 100644 index 0000000..ba16f9e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/MDK/Project.uvoptx @@ -0,0 +1,326 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/MDK/Project.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/MDK/Project.uvprojx new file mode 100644 index 0000000..eea29ec --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/MDK/Project.uvprojx @@ -0,0 +1,455 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/USER/inc/main.h new file mode 100644 index 0000000..99a97f0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030_systick.h" +#include "interrupts_cw32f030.h" +#include "system_cw32f030.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..ec52b4a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/USER/src/interrupts_cw32f030.c @@ -0,0 +1,408 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "../inc/interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +extern void GPIOA_IRQHandlerCallback(void); +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + GPIOA_IRQHandlerCallback(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/USER/src/main.c new file mode 100644 index 0000000..c7e7883 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/USER/src/main.c @@ -0,0 +1,133 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define KEY_GPIO_PORT CW_GPIOA +#define KEY_GPIO_PINS GPIO_PIN_1 | GPIO_PIN_2 +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ** + ******************************************************************************/ +int32_t main(void) +{ + uint8_t tmp8; + GPIO_InitTypeDef GPIO_InitStruct; + __RCC_GPIOA_CLK_ENABLE(); // 使能GPIO的配置时钟 + __RCC_GPIOB_CLK_ENABLE(); + GPIO_InitStruct.IT = GPIO_IT_FALLING; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = KEY_GPIO_PINS; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(KEY_GPIO_PORT, &GPIO_InitStruct); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = 0xFF00; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + //配置中断滤波为LSI，脉冲宽度小于LSI的则不会触发中断 + GPIO_ConfigFilter(CW_GPIOA, bv1 | bv2, GPIO_FLTCLK_LSI); + PB09_SETHIGH(); + //等待PA01所在的端口为低后才进入DEEPSLEEP，以防止芯片被锁死（不能再进行调试） + while (PA01_GETVALUE()); + GPIO_HighByte_Write(CW_GPIOB, 0); //从高8bit输出唤醒次数 + //清除PA01中断标志并使能NVIC //相关程序在中断服务GPIOA_IRQHandler中进行处理 + GPIOA_INTFLAG_CLR(bv1 | bv2); + NVIC_EnableIRQ(GPIOA_IRQn); + tmp8 = 0x00; + while (1) + { + SCB->SCR = 0x04; + __WFI(); + tmp8++; + GPIO_HighByte_Write(CW_GPIOB, tmp8); //从高8bit输出唤醒次数 + } +} + +void GPIOA_IRQHandlerCallback(void) +{ + if (CW_GPIOA->ISR_f.PIN1) + { + GPIOA_INTFLAG_CLR(bv1); + } + if (CW_GPIOA->ISR_f.PIN2) + { + GPIOA_INTFLAG_CLR(bv2); + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/readme.txt new file mode 100644 index 0000000..f586c65 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/gpio/gpio_wakeup_filter/readme.txt @@ -0,0 +1,25 @@ +示例目的： + 演示GPIO通过库函数和宏定义的方法完整初始化配置和输入输出的读写操作 + +硬件资源： + 1. CW32F030C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. PA01 / PA02输入 ，PB08 / PB09输出。 + +演示说明： + 进入DeepSleep mode前，LED1亮，按下KEY1，进入DeepSleep mode，LED1熄灭，LED2亮。 + 按下KEY1或KEY2可唤醒MCU，LED2翻转，变量tmp记录唤醒次数，然后再次进入DeepSleep mode。。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + i2c_cw24c02_int + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + u8Recdata + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_i2c.c + cw32f030_i2c.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + + + ::CMSIS + 1 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/MDK/i2c_cw24c02_int.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/MDK/i2c_cw24c02_int.uvprojx new file mode 100644 index 0000000..4ad31e3 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/MDK/i2c_cw24c02_int.uvprojx @@ -0,0 +1,455 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + i2c_cw24c02_int + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + i2c_cw24c02_int + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4098 + + 0 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + cw32f030_i2c.c + 1 + ..\..\..\..\Libraries\src\cw32f030_i2c.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/USER/inc/main.h new file mode 100644 index 0000000..3576f49 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/USER/inc/main.h @@ -0,0 +1,75 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "base_types.h" + +#include "cw32f030_i2c.h" +#include "cw32f030_gpio.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +void I2c1EepromReadWriteInterruptFunction(void); +void I2c2EepromReadWriteInterruptFunction(void); + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..5c1a0bf --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/USER/src/interrupts_cw32f030.c @@ -0,0 +1,409 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + I2c1EepromReadWriteInterruptFunction(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + I2c2EepromReadWriteInterruptFunction(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/USER/src/main.c new file mode 100644 index 0000000..ddefec9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/USER/src/main.c @@ -0,0 +1,373 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-04-29 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +#include "main.h" + +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +#define TESTI2C 2 //I2C1 = 1 I2C2 = 2 + +#define I2C1_SCL_GPIO_PORT CW_GPIOB +#define I2C1_SCL_GPIO_PIN GPIO_PIN_10 //如果改动口线则GPIO初始化代码需要做同步修改 +#define I2C1_SDA_GPIO_PORT CW_GPIOB +#define I2C1_SDA_GPIO_PIN GPIO_PIN_11 //如果改动口线则GPIO初始化代码需要做同步修改 + +#define I2C2_SCL_GPIO_PORT CW_GPIOB +#define I2C2_SCL_GPIO_PIN GPIO_PIN_0 //如果改动口线则GPIO初始化代码需要做同步修改 +#define I2C2_SDA_GPIO_PORT CW_GPIOB +#define I2C2_SDA_GPIO_PIN GPIO_PIN_1 //如果改动口线则GPIO初始化代码需要做同步修改 + +//EEPROM内部地址 +uint8_t u8Addr = 0x00; //地址字节 +#define WRITELEN 8 //写数据长度 +#define READLEN 8 //读数据长度 +#define WriteReadCycle 35 //写读次数,每次写入数据为n+i(n为次数，i=0~7) + +uint8_t u8Senddata[8] = {0x66, 0x02, 0x03, 0x04, 0x05, 0x60, 0x70, 0x20}; +uint8_t u8Senddata2[8] = {0x55, 0xAA, 0xAA, 0x55, 0x55, 0xAA, 0x55, 0xAA}; +uint8_t u8Recdata[16] = {0x00}; +uint8_t u8SendLen = 0; +uint8_t u8RecvLen = 0; +uint8_t SendFlg = 0, Comm_flg = 0; +uint8_t u8recvflg = 0; +uint8_t u8State = 0; + +uint8_t receivedflag = 0; //读取完成标志 + + +/** + * @brief I2C1 EEPROM读写中断函数 + * + */ +void I2c1EepromReadWriteInterruptFunction(void) +{ + u8State = I2C_GetState(CW_I2C1); + switch (u8State) + { + case 0x08: //发送完START信号 + I2C_GenerateSTART(CW_I2C1, DISABLE); + I2C_Send7bitAddress(CW_I2C1, I2C_SLAVEADDRESS, 0X00); + break; + case 0x10: //发送完重复起始信号 + I2C_GenerateSTART(CW_I2C1, DISABLE); + if (0 == SendFlg) + { + I2C_Send7bitAddress(CW_I2C1, I2C_SLAVEADDRESS, 0X00); //写命令 + } + else + { + I2C_Send7bitAddress(CW_I2C1, I2C_SLAVEADDRESS, 0X01); //读命令,eeprom 随机读 + } + break; + case 0x18: //发送完SLA+W/R字节 + I2C_GenerateSTART(CW_I2C1, DISABLE); + I2C_SendData(CW_I2C1, u8Addr); //发送访问EEPROM的目标地址字节 + break; + case 0x20: //发送完SLA+W后从机返回NACK + case 0x38: //主机在发送 SLA+W 阶段或者发送数据阶段丢失仲裁 或者 主机在发送 SLA+R 阶段或者回应 NACK 阶段丢失仲裁 + case 0x30: //发送完一个数据字节后从机返回NACK + case 0x48: //发送完SLA+R后从机返回NACK + I2C_GenerateSTOP(CW_I2C1, ENABLE); + I2C_GenerateSTART(CW_I2C1, ENABLE); + break; + case 0x58: //接收到一个数据字节，且NACK已回复 + u8Recdata[u8RecvLen++] = I2C_ReceiveData(CW_I2C1);//所有数据读取完成，NACK已发送 + receivedflag = 1; + I2C_GenerateSTOP(CW_I2C1, ENABLE);//发送停止条件 + break; + case 0x28: //发送完1字节数据：发送EEPROM中memory地址也会产生，发送后面的数据也会产生 + if (0 == SendFlg) + { + if (u8SendLen < WRITELEN) + { + I2C_SendData(CW_I2C1, u8Senddata[u8SendLen++]); + } + else + { + u8SendLen = 0; + Comm_flg = 1; + SendFlg = 1; + I2C_GenerateSTOP(CW_I2C1, ENABLE);//发送完数据，发送停止信号 + } + } + else //SendFlg=1为读，SendFlg=0为写。读数据发送完地址字节后，重复起始条件 + { + CW_I2C1->CR_f.STA = 1; //set start //发送重复START信号,START生成函数改写后，会导致0X10状态被略过，故此处不调用函数 + I2C_GenerateSTOP(CW_I2C1, DISABLE); + } + break; + case 0x40: //发送完SLA+R信号，开始接收数据 + u8RecvLen = 0; + if (READLEN > 1) + { + I2C_AcknowledgeConfig(CW_I2C1, ENABLE); //读取数据超过1个字节才发送ACK + } + break; + case 0x50: //接收完一字节数据，在接收最后1字节数据之前设置AA=0; + u8Recdata[u8RecvLen++] = I2C_ReceiveData(CW_I2C1); + if (u8RecvLen == READLEN - 1) + { + I2C_AcknowledgeConfig(CW_I2C1, DISABLE);; + } + break; + } + I2C_ClearIrq(CW_I2C1); +} + +/** + * @brief I2C2 EEPROM读写中断函数 + * + */ +void I2c2EepromReadWriteInterruptFunction(void) +{ + u8State = I2C_GetState(CW_I2C2); + switch (u8State) + { + case 0x08: //发送完START信号 + I2C_GenerateSTART(CW_I2C2, DISABLE); + I2C_Send7bitAddress(CW_I2C2, I2C_SLAVEADDRESS, 0X00); + break; + case 0x10: //发送完重复起始信号 + I2C_GenerateSTART(CW_I2C2, DISABLE); + if (0 == SendFlg) + { + I2C_Send7bitAddress(CW_I2C2, I2C_SLAVEADDRESS, 0X00); //写命令 + } + else + { + I2C_Send7bitAddress(CW_I2C2, I2C_SLAVEADDRESS, 0X01); //读命令,eeprom 随机读 + } + break; + case 0x18: //发送完SLA+W/R字节 + I2C_GenerateSTART(CW_I2C2, DISABLE); + I2C_SendData(CW_I2C2, u8Addr); //发送访问EEPROM的目标地址字节 + break; + case 0x20: //发送完SLA+W后从机返回NACK + case 0x38: //主机在发送 SLA+W 阶段或者发送数据阶段丢失仲裁 或者 主机在发送 SLA+R 阶段或者回应 NACK 阶段丢失仲裁 + case 0x30: //发送完一个数据字节后从机返回NACK + case 0x48: //发送完SLA+R后从机返回NACK + I2C_GenerateSTOP(CW_I2C2, ENABLE); + I2C_GenerateSTART(CW_I2C2, ENABLE); + break; + case 0x58: //接收到一个数据字节，且NACK已回复 + u8Recdata[u8RecvLen++] = I2C_ReceiveData(CW_I2C2);//所有数据读取完成，NACK已发送 + receivedflag = 1; + I2C_GenerateSTOP(CW_I2C2, ENABLE);//发送停止条件 + break; + case 0x28: //发送完1字节数据：发送EEPROM中memory地址也会产生，发送后面的数据也会产生 + if (0 == SendFlg) //SendFlg=0为写 + { + if (u8SendLen < WRITELEN) + { + I2C_SendData(CW_I2C2, u8Senddata[u8SendLen++]); + } + else + { + u8SendLen = 0; + Comm_flg = 1; + SendFlg = 1; + I2C_GenerateSTOP(CW_I2C2, ENABLE);//发送完数据，发送停止信号 + } + } + else //SendFlg=1为读。读数据发送完地址字节后，重复起始条件 + { + CW_I2C2->CR_f.STA = 1; //set start //发送重复START信号,START生成函数改写后，会导致0X10状态被略过，故此处不调用函数 + I2C_GenerateSTOP(CW_I2C2, DISABLE); + } + break; + case 0x40: //发送完SLA+R信号，开始接收数据 + u8RecvLen = 0; + if (READLEN > 1) + { + I2C_AcknowledgeConfig(CW_I2C2, ENABLE); //读取数据超过1个字节才发送ACK + } + break; + case 0x50: //接收完一字节数据，在接收最后1字节数据之前设置AA=0; + u8Recdata[u8RecvLen++] = I2C_ReceiveData(CW_I2C2); + if (u8RecvLen == READLEN - 1) + { + I2C_AcknowledgeConfig(CW_I2C2, DISABLE);; + } + break; + } + I2C_ClearIrq(CW_I2C2); +} + + +int32_t main(void) +{ + I2C_InitTypeDef I2C_InitStruct; + uint16_t tempcnt = 0 ; + //时钟初始化 + RCC_Configuration(); + //IO口初始化 + GPIO_Configuration(); + //I2C初始化 + I2C_InitStruct.I2C_Baud = 0x01;//500K=(8000000/(8*(1+1)) + I2C_InitStruct.I2C_BaudEn = ENABLE; + I2C_InitStruct.I2C_FLT = DISABLE; + I2C_InitStruct.I2C_AA = DISABLE; +#if(0x01 == TESTI2C) + I2C1_DeInit(); + I2C_Master_Init(CW_I2C1, &I2C_InitStruct); //初始化模块 +#elif(0x02 == TESTI2C) + I2C2_DeInit(); + I2C_Master_Init(CW_I2C2, &I2C_InitStruct); //初始化模块 +#endif + //中断设置 + NVIC_Configuration(); + //I2C模块开始工作 +#if(0x01 == TESTI2C) + I2C_Cmd(CW_I2C1, ENABLE); //模块使能 +#elif(0x02 == TESTI2C) + I2C_Cmd(CW_I2C2, ENABLE); //模块使能 +#endif + tempcnt = 0; + for (uint8_t i = 0; i < 8; i++) + { + u8Senddata[i] = i; + } + while (1) + { +#if(0x01 == TESTI2C) + I2C_GenerateSTART(CW_I2C1, ENABLE); //开始信号 +#elif(0x02 == TESTI2C) + I2C_GenerateSTART(CW_I2C2, ENABLE); //开始信号 +#endif + while (1) + { + //等待数据发送完成 + while (!Comm_flg) ; + FirmwareDelay(3000); + //启动读数据过程 + Comm_flg = 0; + receivedflag = 0; +#if(0x01 == TESTI2C) + I2C_GenerateSTART(CW_I2C1, ENABLE); //开始信号 +#elif(0x02 == TESTI2C) + I2C_GenerateSTART(CW_I2C2, ENABLE); //开始信号 +#endif + //等待数据读取完成 + while (!receivedflag) ; + //初始化下一次写数据 + receivedflag = 0; + SendFlg = 0; + u8RecvLen = 0; + tempcnt++; + for (uint8_t i = 0; i < 8; i++) + { + u8Senddata[i] = tempcnt + i; + } + break; + } + //测试次数完成，退出 + if (tempcnt >= WriteReadCycle) + { + break; + } + } + while (1); +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + CW_SYSCTRL->AHBEN_f.GPIOB = 1; +#if(0x01 == TESTI2C) + CW_SYSCTRL->APBEN1_f.I2C1 = 1U; // +#elif(0x02 == TESTI2C) + CW_SYSCTRL->APBEN1_f.I2C2 = 1U; // +#endif +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; +#if(0x01 == TESTI2C) + PB10_AFx_I2C1SCL(); + PB11_AFx_I2C1SDA(); + GPIO_InitStructure.Pins = I2C1_SCL_GPIO_PIN | I2C1_SDA_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(I2C1_SCL_GPIO_PORT, &GPIO_InitStructure); +#elif(0x02 == TESTI2C) + PB00_AFx_I2C2SCL(); + PB01_AFx_I2C2SDA(); + GPIO_InitStructure.Pins = I2C2_SCL_GPIO_PIN | I2C2_SDA_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(I2C2_SCL_GPIO_PORT, &GPIO_InitStructure); +#endif +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); +#if(0x01 == TESTI2C) + NVIC_EnableIRQ(I2C1_IRQn); +#elif(0x02 == TESTI2C) + NVIC_EnableIRQ(I2C2_IRQn); +#endif + __enable_irq(); +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/readme.txt new file mode 100644 index 0000000..e51121f --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_int/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 利用I2C接口，采用中断方式读写EEPROM芯片（CW24C02）。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + +演示说明： +1、采用默认时钟配置，初始化I2C为主接口，500KHz，使能I2C中断。 +2、I2C写时序：根据CW24C02手册，采用页写模式：依次发送START信号、SLA+W字节、目标地址字节、以及最多8字节（受CW24C02每页8字节限制）数据，最后发送STOP信号。 +3、I2C读时序：根据CW24C02手册，采用顺序读模式：先通过字节写模式完成SLA+W字节以及目标地址发送，然后发送重复START信号、SLA+R，并根据需要读取的字节数产生对应字节的时钟信号，最后发送STOP信号。 +4、程序流程：程序完成I2C主设备配置后，先将u8Senddata数组中的内容写入到EEPROM的第1页（CW24C02每页8字节）：发送START信号后，I2C模块会产生状态改变中断，在中断服务程序中根据不同状态值进行不同处理，直到完成CW24C02的页写模式所有数据字节以及STOP信号发送，发送完成后置写操作流程完成标志。主循环中判断到写操作流程完成后，启动从EERROM的第1页数据读取流程：发送启动信号后，I2C模块会产生状态改变中断，在中断服务程序中根据不同状态值进行不同处理，直到完成CW24C02的顺序读模式所有数据字节发送及读取，在发送完STOP信号后置读操作流程完成标志。主循环中判断读操作流程完成后，初始化u8Senddata数组内容，重复下一次测试过程。完成WriteReadCycle变量设置的测试次数后退出。 +5、注意实际测试时需要更改I2C/GPIO口线、时钟配置以及GPIO配置都需要修改。 +6、注意由于EEPROM器件限制，在两次写入数据之间需要加入一定的等待延时，以等待EEPROM实际的写操作完成，否则后续的或者写操作会失败。 +7、I2C从机设备地址目前统一在cw32f030_i2c.h文件中进行定义，在来回测试EEPROM读写和两块单板进行主从通信时需要注意修改。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开i2c_cw24c02_int.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/EWARM/Project.ewp new file mode 100644 index 0000000..473cd8a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/EWARM/Project.ewp @@ -0,0 +1,2154 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + 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a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/MDK/i2c_cw24c02_poll.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/MDK/i2c_cw24c02_poll.uvoptx new file mode 100644 index 0000000..dbbbbf5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/MDK/i2c_cw24c02_poll.uvoptx @@ -0,0 +1,360 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + i2c_cw24c02_poll + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + ST-LINKIII-KEIL_SWO + -U35FF72063446353947361757 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030_64K -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 104 + 1 +
1792
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\i2c_cw24c02_poll\../USER/src/main.c\104 + + + + + 0 + 1 + buffertest + + + 1 + 1 + u8Recdata,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_i2c.c + cw32f030_i2c.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/MDK/i2c_cw24c02_poll.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/MDK/i2c_cw24c02_poll.uvprojx new file mode 100644 index 0000000..b41390a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/MDK/i2c_cw24c02_poll.uvprojx @@ -0,0 +1,454 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + i2c_cw24c02_poll + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.5 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + i2c_cw24c02_poll + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4098 + + 0 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_i2c.c + 1 + ..\..\..\..\Libraries\src\cw32f030_i2c.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/USER/inc/main.h new file mode 100644 index 0000000..b6533e5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/USER/inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "base_types.h" + +#include "cw32f030_i2c.h" +#include "cw32f030_gpio.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/USER/src/main.c new file mode 100644 index 0000000..13b39dc --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/USER/src/main.c @@ -0,0 +1,174 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-04-29 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +#include "main.h" + + +#define TESTI2C 2 //I2C1 = 1 I2C2 = 2 + +#define I2C1_SCL_GPIO_PORT CW_GPIOB +#define I2C1_SCL_GPIO_PIN GPIO_PIN_10 //如果改动口线则GPIO初始化代码需要做同步修改 +#define I2C1_SDA_GPIO_PORT CW_GPIOB +#define I2C1_SDA_GPIO_PIN GPIO_PIN_11 //如果改动口线则GPIO初始化代码需要做同步修改 + +#define I2C2_SCL_GPIO_PORT CW_GPIOB +#define I2C2_SCL_GPIO_PIN GPIO_PIN_0 //如果改动口线则GPIO初始化代码需要做同步修改 +#define I2C2_SDA_GPIO_PORT CW_GPIOB +#define I2C2_SDA_GPIO_PIN GPIO_PIN_1 //如果改动口线则GPIO初始化代码需要做同步修改 + + +//EEPROM内部地址 +#define WRITEADDRESS 0 //写入或者读取的EEPROM的地址 +#define WriteReadCycle 22 //写读次数,每次写入数据为n+i(n为次数，i=0~7) + +uint8_t u8Senddata[8] = {0x66, 0x02, 0x03, 0x04, 0x05, 0x60, 0x70, 0x20}; +uint8_t u8Senddata2[8] = {0x55, 0xAA, 0xAA, 0x55, 0x55, 0xAA, 0x55, 0xAA}; +uint8_t u8Recdata[16] = {0x00}; +uint8_t u8SendLen = 0; +uint8_t u8RecvLen = 0; +uint8_t SendFlg = 0, Comm_flg = 0; +uint8_t u8recvflg = 0; +uint8_t u8State = 0; + + +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + + +int32_t main(void) +{ + uint16_t tempcnt = 0 ; + I2C_InitTypeDef I2C_InitStruct; + //时钟初始化 + RCC_Configuration(); + //IO口初始化 + GPIO_Configuration(); + //I2C初始化 + I2C_InitStruct.I2C_BaudEn = ENABLE; + I2C_InitStruct.I2C_Baud = 0x01;//500K=(8000000/(8*(1+1)) + I2C_InitStruct.I2C_FLT = DISABLE; + I2C_InitStruct.I2C_AA = DISABLE; +#if(0X01 == TESTI2C) + I2C1_DeInit(); + I2C_Master_Init(CW_I2C1, &I2C_InitStruct); //初始化模块 + I2C_Cmd(CW_I2C1, ENABLE); //模块使能 +#elif(0X02 == TESTI2C) + I2C2_DeInit(); + I2C_Master_Init(CW_I2C2, &I2C_InitStruct); //初始化模块 + I2C_Cmd(CW_I2C2, ENABLE); //模块使能 +#endif + while (1) + { +#if(0X01 == TESTI2C) + I2C_MasterWriteEepromData(CW_I2C1, WRITEADDRESS, u8Senddata, 8); + FirmwareDelay(3000); + I2C_MasterWriteEepromData(CW_I2C1, WRITEADDRESS + 8, u8Senddata2, 8); + FirmwareDelay(3000); + I2C_MasterReadEepomData(CW_I2C1, WRITEADDRESS, u8Recdata, 16); +#elif(0X02 == TESTI2C) + I2C_MasterWriteEepromData(CW_I2C2, WRITEADDRESS, u8Senddata, 8); + FirmwareDelay(3000); + I2C_MasterWriteEepromData(CW_I2C2, WRITEADDRESS + 8, u8Senddata2, 8); + FirmwareDelay(3000); + I2C_MasterReadEepomData(CW_I2C2, WRITEADDRESS, u8Recdata, 16); +#endif + tempcnt++; + for (uint8_t i = 0; i < 8; i++) + { + u8Senddata[i] = tempcnt + i; + } + if (tempcnt >= WriteReadCycle) + { + break; + } + } + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + CW_SYSCTRL->AHBEN_f.GPIOB = 1; +#if(0X01 == TESTI2C) + CW_SYSCTRL->APBEN1_f.I2C1 = 1U; // +#elif(0X02 == TESTI2C) + CW_SYSCTRL->APBEN1_f.I2C2 = 1U; // +#endif +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; +#if(0X01 == TESTI2C) + PB10_AFx_I2C1SCL(); + PB11_AFx_I2C1SDA(); + GPIO_InitStructure.Pins = I2C1_SCL_GPIO_PIN | I2C1_SDA_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(I2C1_SCL_GPIO_PORT, &GPIO_InitStructure); +#elif(0X02 == TESTI2C) + PB00_AFx_I2C2SCL(); + PB01_AFx_I2C2SDA(); + GPIO_InitStructure.Pins = I2C2_SCL_GPIO_PIN | I2C2_SDA_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(I2C2_SCL_GPIO_PORT, &GPIO_InitStructure); +#endif +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/readme.txt new file mode 100644 index 0000000..4780ecd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_cw24c02_poll/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 利用I2C接口，采用轮询方式读写EEPROM芯片（CW24C02）。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + +演示说明： +1、采用默认时钟配置，初始化I2C为主接口，500KHz，不使能I2C中断。 +2、I2C写时序：根据CW24C02手册，采用页写模式：依次发送START信号、SLA+W字节、目标地址字节、以及最多8字节（受CW24C02每页8字节限制）数据，最后发送STOP信号。 +3、I2C读时序：根据CW24C02手册，采用顺序读模式：先通过字节写模式完成SLA+W字节以及目标地址发送，然后发送重复START信号、SLA+R，并根据需要读取的字节数产生对应字节的时钟信号，最后发送STOP信号。 +4、程序流程：程序完成I2C主设备配置后，先将u8Senddata/u8Senddata2数组中的内容依次写入到EEPROM的第1/2页（CW24C02每页8字节）：发送START信号后，I2C模块会产生状态改变，程序持续查询I2C模块状态并根据不同状态值进行不同处理，直到完成CW24C02的页写模式所有数据字节以及STOP信号发送。然后启动从EERROM的起始地址开始的16字节（第1/2页）数据读取流程：发送启动信号后，I2C模块会产生状态改变，程序持续查询I2C模块状态并根据不同状态值进行不同处理，直到完成CW24C02的顺序读模式所有数据字节发送及接收，并发送STOP信号，完成读操作流程。然后重新初始化u8Senddata数组内容，重复下一次测试过程。完成WriteReadCycle变量设置的测试次数后退出。 +5、注意实际测试时需要更改I2C/GPIO口线、时钟配置以及GPIO配置都需要修改。 +6、注意由于EEPROM器件限制，在两次写入数据之间需要加入一定的等待延时，以等待EEPROM实际的写操作完成，否则后续的或者写操作会失败。 +7、I2C从机设备地址目前统一在cw32f030_i2c.h文件中进行定义，在来回测试EEPROM读写和两块单板进行主从通信时需要注意修改。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开i2c_cw24c02_poll.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/MDK/Template.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/MDK/Template.uvoptx new file mode 100644 index 0000000..4b28ac3 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/MDK/Template.uvoptx @@ -0,0 +1,350 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\Template\../USER/src/main.c\98 + + + + + 0 + 1 + u8Recdata + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_i2c.c + cw32f030_i2c.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/MDK/Template.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/MDK/Template.uvprojx new file mode 100644 index 0000000..795007f --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/MDK/Template.uvprojx @@ -0,0 +1,455 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Template + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4098 + + 0 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_i2c.c + 1 + ..\..\..\..\Libraries\src\cw32f030_i2c.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/USER/inc/main.h new file mode 100644 index 0000000..b6533e5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/USER/inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "base_types.h" + +#include "cw32f030_i2c.h" +#include "cw32f030_gpio.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/USER/src/main.c new file mode 100644 index 0000000..43bbcdd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/USER/src/main.c @@ -0,0 +1,170 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-04-29 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +#include "main.h" + + +#define TESTI2C 2 //I2C1 = 1 I2C2 = 2 + +#define I2C1_SCL_GPIO_PORT CW_GPIOB +#define I2C1_SCL_GPIO_PIN GPIO_PIN_10 //如果改动口线则GPIO初始化代码需要做同步修改 +#define I2C1_SDA_GPIO_PORT CW_GPIOB +#define I2C1_SDA_GPIO_PIN GPIO_PIN_11 //如果改动口线则GPIO初始化代码需要做同步修改 + +#define I2C2_SCL_GPIO_PORT CW_GPIOB +#define I2C2_SCL_GPIO_PIN GPIO_PIN_0 //如果改动口线则GPIO初始化代码需要做同步修改 +#define I2C2_SDA_GPIO_PORT CW_GPIOB +#define I2C2_SDA_GPIO_PIN GPIO_PIN_1 //如果改动口线则GPIO初始化代码需要做同步修改 + +//uint8_t u8Addr = 0x00; //从机目标地址字节 +#define WRITELEN 8 //写数据长度 +#define READLEN 8 //读数据长度 +#define WriteReadCycle 30 //写读次数,每次写入数据为n+i(n为次数，i=0~7) + +//广播地址时，地址发送0x00，广播地址从机只接收，不回传 +uint8_t u8Senddata[16] = {0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x60, 0x70, 0x80, 0x90, 0xa0, 0xb0, 0xc0, 0xd0, 0xe0, 0xf0}; +uint8_t u8Recdata[16] = {0x00}; +uint8_t u8SendLen = 0; +uint8_t u8RecvLen = 0; +uint8_t SendFlg = 0, Comm_flg = 0; +uint8_t u8recvflg = 0; +uint8_t u8State = 0; + +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +int32_t main(void) +{ + uint16_t tempcnt = 0 ; + I2C_InitTypeDef I2C_InitStruct; + //时钟初始化 + RCC_Configuration(); + //I2C的IO口初始化 + GPIO_Configuration(); + //I2C初始化 + I2C_InitStruct.I2C_BaudEn = ENABLE; + I2C_InitStruct.I2C_Baud = 0x01; //500K=(8000000/(8*(1+1)) + I2C_InitStruct.I2C_FLT = DISABLE; + I2C_InitStruct.I2C_AA = DISABLE; +#if(0X01 == TESTI2C) + I2C1_DeInit(); + I2C_Master_Init(CW_I2C1, &I2C_InitStruct); //初始化模块 + I2C_Cmd(CW_I2C1, ENABLE); //模块使能 +#elif(0X02 == TESTI2C) + I2C2_DeInit(); + I2C_Master_Init(CW_I2C2, &I2C_InitStruct); //初始化模块 + I2C_Cmd(CW_I2C2, ENABLE); //模块使能 +#endif + while (1) + { +#if(0X01 == TESTI2C) + I2C_MasterSendDataToSlave(CW_I2C1, u8Senddata, 16); //主机发送16字节数据 + FirmwareDelay(1600); + I2C_MasterRecDataFromSlave(CW_I2C1, u8Recdata, 8); //主机读取8字节数据 +#elif(0X02 == TESTI2C) + I2C_MasterSendDataToSlave(CW_I2C2, u8Senddata, 16); //主机发送16字节数据 + FirmwareDelay(1600); + I2C_MasterRecDataFromSlave(CW_I2C2, u8Recdata, 8); //主机读取8字节数据 +#endif + tempcnt++; + for (uint8_t i = 0; i < 8; i++) + { + u8Senddata[i] = tempcnt + i; + } + if (tempcnt >= WriteReadCycle) + { + break; + } + } + while (1) + { + } +} + + + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + CW_SYSCTRL->AHBEN_f.GPIOB = 1; +#if(0X01 == TESTI2C) + CW_SYSCTRL->APBEN1_f.I2C1 = 1U; // +#elif(0X02 == TESTI2C) + CW_SYSCTRL->APBEN1_f.I2C2 = 1U; // +#endif +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; +#if(0X01 == TESTI2C) + PB10_AFx_I2C1SCL(); + PB11_AFx_I2C1SDA(); + GPIO_InitStructure.Pins = I2C1_SCL_GPIO_PIN | I2C1_SDA_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD; //GPIO_MODE_OUTPUT_PP; // + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(I2C1_SCL_GPIO_PORT, &GPIO_InitStructure); +#elif(0X02 == TESTI2C) + PB00_AFx_I2C2SCL(); + PB01_AFx_I2C2SDA(); + GPIO_InitStructure.Pins = I2C2_SCL_GPIO_PIN | I2C2_SDA_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD; //GPIO_MODE_OUTPUT_PP; // + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(I2C2_SCL_GPIO_PORT, &GPIO_InitStructure); +#endif +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/readme.txt new file mode 100644 index 0000000..c20eddc --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_master_poll/readme.txt @@ -0,0 +1,30 @@ +示例目的： + 利用I2C接口， 实现I2C主设备功能，和I2C从机进行数据通信。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + +演示说明： +1、采用默认时钟配置，初始化I2C为主接口，500KHz，不使能I2C中断。 +2、主从通信主设备I2C发送时序：依次发送START信号、SLA+W字节、多个数据字节，最后发送STOP信号。 +3、主从通信主设备I2C接收时序：依次发送START信号、SLA+R字节，然后接收多个数据字节，最后发送STOP信号。 +4、程序流程：程序完成I2C主设备配置后，先将u8Senddata数组中的内容发给从机：发送START信号后，I2C模块会产生状态改变，程序持续查询I2C模块状态并根据不同状态值进行不同处理，直到完成SLA+W、所有待发送的数据字节以及STOP信号的发送。然后启动数据接收流程：发送启动信号后，I2C模块会产生状态改变，程序持续查询I2C模块状态并根据不同状态值进行不同处理，直到完成SLA+R、所有待接收字节的接收，以及STOP信号发送。然后重新初始化u8Senddata数组内容，重复下一次测试过程。完成WriteReadCycle变量设置的测试次数后退出。 +5、注意实际测试时需要更改I2C/GPIO口线、时钟配置以及GPIO配置都需要修改。 +6、注意主从通信时，需要连接从机单板对应I2C总线到单板的EEPROM接口上(标号CN11,VDDE/SCL/SDA三根口线都要连接，以给I2C提供上拉电阻) +7、I2C从机设备地址目前统一在cw32f030_i2c.h文件中进行定义，在来回测试EEPROM读写和两块单板进行主从通信时需要注意修改。 +8、注意主机完成发送流程后，需要等待从机准备好后再开始接收流程，具体需要等待的时间取决于从机的处理速度。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开Template.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + 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b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/MDK/i2c_mcu_slave_poll.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/MDK/i2c_mcu_slave_poll.uvoptx new file mode 100644 index 0000000..4a0ad10 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/MDK/i2c_mcu_slave_poll.uvoptx @@ -0,0 +1,337 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + i2c_mcu_slave_poll + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U35FF72063446353947361757 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030_64K -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\I2C2 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 1 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_i2c.c + cw32f030_i2c.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/MDK/i2c_mcu_slave_poll.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/MDK/i2c_mcu_slave_poll.uvprojx new file mode 100644 index 0000000..0f6bf03 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/MDK/i2c_mcu_slave_poll.uvprojx @@ -0,0 +1,455 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + i2c_mcu_slave_poll + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + i2c_mcu_slave_poll + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 0 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_i2c.c + 1 + ..\..\..\..\Libraries\src\cw32f030_i2c.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/USER/inc/main.h new file mode 100644 index 0000000..b6533e5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/USER/inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" +#include "base_types.h" + +#include "cw32f030_i2c.h" +#include "cw32f030_gpio.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/USER/src/main.c new file mode 100644 index 0000000..2b13a8e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/USER/src/main.c @@ -0,0 +1,154 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-04-29 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +#include "main.h" + +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +#define TESTI2C 2 //I2C1 = 1 I2C2 = 2 + +#define I2C1_SCL_GPIO_PORT CW_GPIOB +#define I2C1_SCL_GPIO_PIN GPIO_PIN_10 //如果改动口线则GPIO初始化代码需要做同步修改 +#define I2C1_SDA_GPIO_PORT CW_GPIOB +#define I2C1_SDA_GPIO_PIN GPIO_PIN_11 //如果改动口线则GPIO初始化代码需要做同步修改 + +#define I2C2_SCL_GPIO_PORT CW_GPIOB +#define I2C2_SCL_GPIO_PIN GPIO_PIN_0 //如果改动口线则GPIO初始化代码需要做同步修改 +#define I2C2_SDA_GPIO_PORT CW_GPIOB +#define I2C2_SDA_GPIO_PIN GPIO_PIN_1 //如果改动口线则GPIO初始化代码需要做同步修改 + + +uint8_t u8Recdata[30] = {0x00}; //存放接收到的数据 +uint32_t u32SendLen = 0; //存放接收数据的长度 +uint32_t u32RecvLen = 0; //存放发送数据的长度 +uint8_t u8State = 0; //I2C模块状态 + + +/** + * @brief + * + * @return int32_t + */ +int32_t main(void) +{ + I2C_InitTypeDef I2C_InitStruct; + //时钟初始化 + RCC_Configuration(); + //IO口初始化 + GPIO_Configuration(); + //I2C初始化 + I2C_InitStruct.I2C_OwnSlaveAddr0 = OwnSlaveAddress0; //TEST ADDRESS0 + I2C_InitStruct.I2C_OwnSlaveAddr1 = OwnSlaveAddress1; //TEST ADDRESS1 + I2C_InitStruct.I2C_OwnSlaveAddr2 = OwnSlaveAddress2; //TEST ADDRESS2 + I2C_InitStruct.I2C_OwnGc = DISABLE; + I2C_InitStruct.I2C_FLT = DISABLE; + I2C_InitStruct.I2C_AA = DISABLE; +#if(0X01 == TESTI2C) + I2C1_DeInit(); + I2C_Slave_Init(CW_I2C1, &I2C_InitStruct); //初始化模块 + I2C_Cmd(CW_I2C1, ENABLE);//模块使能 + I2C_AcknowledgeConfig(CW_I2C1, ENABLE); //ACK打开 +#elif(0X02 == TESTI2C) + I2C2_DeInit(); + I2C_Slave_Init(CW_I2C2, &I2C_InitStruct); //初始化模块 + I2C_Cmd(CW_I2C2, ENABLE);//模块使能 + I2C_AcknowledgeConfig(CW_I2C2, ENABLE); //ACK打开 +#endif + while (1) + { +#if(0X01 == TESTI2C) + I2C_SlaveRecDataFromMaster(CW_I2C1, u8Recdata, &u32RecvLen); //等主机写数据 + I2C_SlaveSendDataToMaster(CW_I2C1, u8Recdata, &u32SendLen); //等主机读数据 +#elif(0X02 == TESTI2C) + I2C_SlaveRecDataFromMaster(CW_I2C2, u8Recdata, &u32RecvLen); //等主机写数据 + I2C_SlaveSendDataToMaster(CW_I2C2, u8Recdata, &u32SendLen); //等主机读数据 +#endif + } +} + + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + CW_SYSCTRL->AHBEN_f.GPIOB = 1; +#if(0X01 == TESTI2C) + CW_SYSCTRL->APBEN1_f.I2C1 = 1U; // +#elif(0X02 == TESTI2C) + CW_SYSCTRL->APBEN1_f.I2C2 = 1U; // +#endif +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; +#if(0X01 == TESTI2C) + PB10_AFx_I2C1SCL(); + PB11_AFx_I2C1SDA(); + GPIO_InitStructure.Pins = I2C1_SCL_GPIO_PIN | I2C1_SDA_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(I2C1_SCL_GPIO_PORT, &GPIO_InitStructure); +#elif(0X02 == TESTI2C) + PB00_AFx_I2C2SCL(); + PB01_AFx_I2C2SDA(); + GPIO_InitStructure.Pins = I2C2_SCL_GPIO_PIN | I2C2_SDA_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(I2C2_SCL_GPIO_PORT, &GPIO_InitStructure); +#endif +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/readme.txt new file mode 100644 index 0000000..710b627 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/i2c/i2c_mcu_slave_poll/readme.txt @@ -0,0 +1,30 @@ +示例目的： + 利用I2C接口， 实现I2C从设备功能，和I2C主机进行数据通信。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + +演示说明： +1、采用默认时钟配置，初始化I2C为主接口，500KHz，不使能I2C中断。 +2、主从通信从设备I2C接收时序：根据I2C模块状态变化，接收保存数据并回应ACK，直到主动回应NACK或者收到STOP信号。 +3、主从通信从设备I2C发送时序：根据I2C模块状态变化，发送数据，直到收到NACK信号或者STOP信号。 +4、程序流程：程序完成I2C从设备配置后，循环持续等待I2C模块的状态改变，收到SLA+W字节后，循环接收主机发送的所有数据的接收。然后启动数据接收流程：循环持续等待I2C模块的状态改变，收到SLA+R之后，循环发送数据，直到收到NACK信号或者STOP信号，完成所有字节发送。然后重复下一次测试过程。 +5、注意实际测试时需要更改I2C/GPIO口线、时钟配置以及GPIO配置都需要修改。 +6、注意主从通信时，需要连接从机单板对应I2C总线到单板的EEPROM接口上(标号CN11,VDDE/SCL/SDA三根口线都要连接，以给I2C提供上拉电阻) +7、I2C从机设备地址目前统一在cw32f030_i2c.h文件中进行定义，在来回测试EEPROM读写和两块单板进行主从通信时需要注意修改。 + + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开i2c_mcu_slave_poll.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + 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b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/MDK/rcc_hclkout.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/MDK/rcc_hclkout.uvoptx new file mode 100644 index 0000000..f74b84e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/MDK/rcc_hclkout.uvoptx @@ -0,0 +1,328 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rcc_hclkout + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U4294967295 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030 -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 1 + 0 + 0x001007AC + 0 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\SYSCTRL + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/MDK/rcc_hclkout.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/MDK/rcc_hclkout.uvprojx new file mode 100644 index 0000000..7e7430e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/MDK/rcc_hclkout.uvprojx @@ -0,0 +1,450 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rcc_hclkout + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + rcc_hclkout + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/USER/inc/main.h new file mode 100644 index 0000000..2f6160d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/USER/src/main.c new file mode 100644 index 0000000..cdbe442 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/USER/src/main.c @@ -0,0 +1,106 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-25 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample output HCLK + ** + ******************************************************************************/ +int32_t main(void) +{ + /******************************************************************** + HCLK Output Test. + HCLK 输出到PA04管脚，请通过PA04观察HCLK频率 + *******************************************************************/ + RCC_HSI_Enable(RCC_HSIOSC_DIV2); + RCC_HSI_OUT(); //PB00输出HSI + RCC_HCLKPRS_Config(RCC_HCLK_DIV1); + RCC_HCLK_OUT(); //PA04输出HCLK + while (1) {;} +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/readme.txt new file mode 100644 index 0000000..aad9a8c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hclkout/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 利用HCLK时钟输出功能将HCLK时钟从PA04引脚输出。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟6分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + +演示说明： + 采用默认时钟配置，并设置HCLK时钟输出，用示波器观测PA04引脚的波形，默认程序为8MHz。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开rcc_hclkout.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + debug + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 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$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/EWARM/Project.ewp new file mode 100644 index 0000000..15c631d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/EWARM/Project.ewp @@ -0,0 +1,2157 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_systick.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/MDK/rcc_hsi_hse.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/MDK/rcc_hsi_hse.uvoptx new file mode 100644 index 0000000..dd2e0a0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/MDK/rcc_hsi_hse.uvoptx @@ -0,0 +1,333 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rcc_hsi_hse + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U4294967295 -O78 -S6 -ZTIFSpeedSel500 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8027 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030 -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/MDK/rcc_hsi_hse.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/MDK/rcc_hsi_hse.uvprojx new file mode 100644 index 0000000..11952e0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/MDK/rcc_hsi_hse.uvprojx @@ -0,0 +1,454 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rcc_hsi_hse + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + rcc_hsi_hse + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/USER/inc/main.h new file mode 100644 index 0000000..2f6160d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/USER/src/main.c new file mode 100644 index 0000000..31c8811 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/USER/src/main.c @@ -0,0 +1,161 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-25 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_flash.h" +#include "cw32f030_systick.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample HSI switch to HSE, HSE switch to HSI. + ** + ******************************************************************************/ +int32_t main(void) +{ + uint8_t res = 0; + GPIO_InitTypeDef GPIO_InitStruct; + RCC_HSI_Enable(RCC_HSIOSC_DIV2); //配置系统时钟为HSI 24M + RCC_AHBPeriphClk_Enable(RCC_AHB_PERIPH_FLASH, ENABLE); //打开FLASH时钟 + //PB8/PB9 推挽输出 + CW_SYSCTRL->AHBEN_f.GPIOB = 1; + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + PB08_SETLOW(); + PB09_SETLOW(); + RCC_PCLK_OUT(); //通过PA03观察PCLK频率 + RCC_HCLK_OUT(); //通过PA04观察HCLK频率 + while (1) + { + //============================================================================ + //以下从HSI切换到HSE + RCC_HSE_Enable(RCC_HSE_MODE_OSC, 16000000, RCC_HSE_DRIVER_NORMAL, RCC_HSE_FLT_CLOSE); //开启外部高速时钟，实际频率需要根据实际晶体频率重新配置 + FLASH_SetLatency(FLASH_Latency_2); //频率大于24M需要配置FlashWait=2 + res = RCC_SysClk_Switch(RCC_SYSCLKSRC_HSE); //切换系统时钟到外部高速时钟 + if (res == 0x00) //切换系统时钟成功 + { + PB08_SETHIGH(); + PB09_SETHIGH(); + RCC_HSI_Disable(); + FirmwareDelay(50000); + } + else + { + while (1) + { + PB08_TOG(); + PB09_TOG(); + FirmwareDelay(10000000); + } + } + RCC_HSE_OUT(); //通过PB02观察HSE频率 + //============================================================================ + //以下从HSE切换到HSI + RCC_HSI_Enable(RCC_HSIOSC_DIV1); //开启内部高速时钟HSI = HSIOSC / 1 + FLASH_SetLatency(FLASH_Latency_2); //频率大于24M需要配置FlashWait=2 + res = RCC_SysClk_Switch(RCC_SYSCLKSRC_HSI); //切换系统时钟到内部高速时钟 + if (res == 0x00) //切换系统时钟成功 + { + FLASH_SetLatency(FLASH_Latency_2); //频率大于24M需要配置FlashWait=2 + PB08_SETLOW(); + PB09_SETLOW(); + RCC_HSE_Disable(); + FirmwareDelay(64000); + } + else + { + while (1) + { + PB08_TOG(); + PB09_TOG(); + FirmwareDelay(10000000); + } + } + RCC_HSI_OUT(); //通过PB00观察HSI频率 + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/readme.txt new file mode 100644 index 0000000..723ecd8 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_hse/readme.txt @@ -0,0 +1,24 @@ +示例目的： + 系统时钟源在HSI和HSE之间进行切换。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI和LSE + 3. HSI作为系统时钟时，设置为HSIOSC到HSI时钟的分频比为1，则SysClk为48MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=48MHz，注意此时需要正确配置FLASH的读访问等待周期。 + 4. HSE作为系统时钟时，16MHz。PCLK、HCLK不分频，PCLK=HCLK=SysClk=16MHz。 + +演示说明： + 程序循环在HSI和HSE时钟之间进行切换，正常切换则LED快闪（100mS亮，100mS熄），如果切换失败，则LED灯会慢闪（1S亮，1S熄）。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开rcc_hsi_hse.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 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$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + debug + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 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$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/EWARM/Project.ewp new file mode 100644 index 0000000..49d197c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/EWARM/Project.ewp @@ -0,0 +1,2151 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/MDK/rcc_hsi_lse.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/MDK/rcc_hsi_lse.uvoptx new file mode 100644 index 0000000..f95e57e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/MDK/rcc_hsi_lse.uvoptx @@ -0,0 +1,312 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rcc_hsi_lse + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/MDK/rcc_hsi_lse.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/MDK/rcc_hsi_lse.uvprojx new file mode 100644 index 0000000..c98d553 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/MDK/rcc_hsi_lse.uvprojx @@ -0,0 +1,448 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rcc_hsi_lse + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + rcc_hsi_lse + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4098 + + 0 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/USER/inc/main.h new file mode 100644 index 0000000..2f6160d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/USER/src/main.c new file mode 100644 index 0000000..dbd96eb --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/USER/src/main.c @@ -0,0 +1,152 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-25 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample HSI switch to LSI, LSI switch to HSI. + ** + ******************************************************************************/ +int32_t main(void) +{ + uint8_t res = 0U; + GPIO_InitTypeDef GPIO_InitStruct; + //PB8/PB9 推挽输出 + CW_SYSCTRL->AHBEN_f.GPIOB = 1; + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + PB08_SETLOW(); + PB09_SETLOW(); + RCC_PCLK_OUT(); //通过PA03观察PCLK频率 + RCC_HCLK_OUT(); //通过PA04观察HCLK频率 + while (1) + { + //============================================================================ + //以下从HSI切换到LSE + RCC_LSE_Enable(RCC_LSE_MODE_OSC, RCC_LSE_AMP_LARGER, RCC_LSE_DRIVER_LARGER); //开启外部高速时钟LSE + res = RCC_SysClk_Switch(RCC_SYSCLKSRC_LSE); //切换系统时钟到LSE + if (res == 0x00) //切换系统时钟成功 + { + PB08_SETHIGH(); + PB09_SETHIGH(); + RCC_HSI_Disable(); //切换时钟到LSE后关闭源时钟HSI + FirmwareDelay(400); + } + else + { + while (1) + { + PB08_TOG(); + PB09_TOG(); + FirmwareDelay(4000); + } + } + //============================================================================ + //以下从LSE切换到HSI + RCC_HSI_Enable(RCC_HSIOSC_DIV2); //开启内部高速时钟HSI = HSIOSC / 2 + res = RCC_SysClk_Switch(RCC_SYSCLKSRC_HSI); //切换系统时钟到HSI + if (res == 0x00) //切换系统时钟成功 + { + PB08_SETLOW(); + PB09_SETLOW(); + RCC_LSE_Disable(); //切换时钟到HSI后关闭LSE时钟 + FirmwareDelay(275000); //about 100mS + } + else + { + while (1) + { + PB08_TOG(); + PB09_TOG(); + FirmwareDelay(10000000); + } + } + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/readme.txt new file mode 100644 index 0000000..1b98dac --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lse/readme.txt @@ -0,0 +1,24 @@ +示例目的： + 系统时钟源在HSI和LSE之间进行切换。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI和LSI + 3. HSI作为系统时钟时，设置为HSIOSC到HSI时钟的分频比为2，则SysClk为24MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=24MHz + 4. LSE作为系统时钟时，32.768K。PCLK、HCLK不分频，PCLK=HCLK=SysClk=32.768KHz。 + +演示说明： + 程序循环在HSI和LSE时钟之间进行切换，正常切换则LED快闪（100mS亮，100mS熄），如果切换失败，则LED灯会慢闪（1S亮，1S熄）。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开rcc_hsi_lse.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + debug + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 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$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/EWARM/Project.ewp new file mode 100644 index 0000000..49d197c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/EWARM/Project.ewp @@ -0,0 +1,2151 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/MDK/rcc_hsi_lsi.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/MDK/rcc_hsi_lsi.uvoptx new file mode 100644 index 0000000..bbfba7e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/MDK/rcc_hsi_lsi.uvoptx @@ -0,0 +1,312 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rcc_hsi_lsi + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/MDK/rcc_hsi_lsi.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/MDK/rcc_hsi_lsi.uvprojx new file mode 100644 index 0000000..888749d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/MDK/rcc_hsi_lsi.uvprojx @@ -0,0 +1,448 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rcc_hsi_lsi + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + rcc_hsi_lsi + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4098 + + 0 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/USER/inc/main.h new file mode 100644 index 0000000..2f6160d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/USER/src/main.c new file mode 100644 index 0000000..14b0dad --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/USER/src/main.c @@ -0,0 +1,152 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-25 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample HSI switch to LSI, LSI switch to HSI. + ** + ******************************************************************************/ +int32_t main(void) +{ + uint8_t res = 0U; + GPIO_InitTypeDef GPIO_InitStruct; + //PB8/PB9 推挽输出 + CW_SYSCTRL->AHBEN_f.GPIOB = 1; + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + PB08_SETLOW(); + PB09_SETLOW(); + RCC_PCLK_OUT(); //通过PA03观察PCLK频率 + RCC_HCLK_OUT(); //通过PA04观察HCLK频率 + while (1) + { + //============================================================================ + //以下从HSI切换到LSI + RCC_LSI_Enable(); //开启外部高速时钟LSI + res = RCC_SysClk_Switch(RCC_SYSCLKSRC_LSI); //切换系统时钟到LSI + if (res == 0x00) //系统时钟切换成功 + { + PB08_SETHIGH(); + PB09_SETHIGH(); + RCC_HSI_Disable(); //切换时钟到PLL后关闭源时钟HSI + FirmwareDelay(400); //about 100mS + } + else + { + while (1) + { + PB08_TOG(); + PB09_TOG(); + FirmwareDelay(4000); + } + } + //============================================================================ + //以下从LSI切换到HSI + RCC_HSI_Enable(RCC_HSIOSC_DIV2); //开启内部高速时钟HSI = HSIOSC / 2 + res = RCC_SysClk_Switch(RCC_SYSCLKSRC_HSI); //切换系统时钟到HSI + if (res == 0x00) //系统时钟切换成功 + { + PB08_SETLOW(); + PB09_SETLOW(); + RCC_LSI_Disable(); //切换时钟到HSI后关闭LSI时钟 + FirmwareDelay(275000); //about 100mS + } + else + { + while (1) + { + PB08_TOG(); + PB09_TOG(); + FirmwareDelay(10000000); + } + } + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/readme.txt new file mode 100644 index 0000000..e8a1314 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_lsi/readme.txt @@ -0,0 +1,24 @@ +示例目的： + 系统时钟源在HSI和LSI之间进行切换。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI和LSI + 3. HSI作为系统时钟时，设置为HSIOSC到HSI时钟的分频比为2，则SysClk为24MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=24MHz + 4. LSI作为系统时钟时，32.8K。PCLK、HCLK不分频，PCLK=HCLK=SysClk=32.8KHz。 + +演示说明： + 程序循环在HSI和LSI时钟之间进行切换，正常切换则LED快闪（100mS亮，100mS熄），如果切换失败，则LED灯会慢闪（1S亮，1S熄）。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开rcc_hsi_lsi.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + debug + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 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$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/EWARM/Project.ewp new file mode 100644 index 0000000..883654e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/EWARM/Project.ewp @@ -0,0 +1,2154 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/MDK/rcc_hsi_pll(src_hse).uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/MDK/rcc_hsi_pll(src_hse).uvoptx new file mode 100644 index 0000000..9b60b7c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/MDK/rcc_hsi_pll(src_hse).uvoptx @@ -0,0 +1,324 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rcc_hsi_pll(src_hse) + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/MDK/rcc_hsi_pll(src_hse).uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/MDK/rcc_hsi_pll(src_hse).uvprojx new file mode 100644 index 0000000..6a20296 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/MDK/rcc_hsi_pll(src_hse).uvprojx @@ -0,0 +1,453 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rcc_hsi_pll(src_hse) + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + rcc_hsi_pll(src_hse) + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4098 + + 0 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/USER/inc/main.h new file mode 100644 index 0000000..2f6160d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/USER/src/main.c new file mode 100644 index 0000000..6155290 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/USER/src/main.c @@ -0,0 +1,158 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-25 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_flash.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample HSI switch to PLL, PLL switch to HSI. + ** + ******************************************************************************/ +int32_t main(void) +{ + uint8_t res = 0U; + GPIO_InitTypeDef GPIO_InitStruct; + RCC_AHBPeriphClk_Enable(RCC_AHB_PERIPH_FLASH, ENABLE); //打开FLASH时钟 + //PB8/PB9 推挽输出 + CW_SYSCTRL->AHBEN_f.GPIOB = 1; + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + PB08_SETLOW(); + PB09_SETLOW(); + RCC_PCLK_OUT(); //通过PA03观察PCLK频率 + RCC_HCLK_OUT(); //通过PA04观察HCLK频率 + while (1) + { + //============================================================================ + //以下从HSI切换到PLL + RCC_HSE_Enable(RCC_HSE_MODE_OSC, 16000000, RCC_HSE_DRIVER_NORMAL, RCC_HSE_FLT_CLOSE); //开启外部高速时钟HSE，实际频率需要根据实际晶体频率进行填写 + RCC_PLL_Enable(RCC_PLLSOURCE_HSEOSC, 16000000, RCC_PLL_MUL_2); //开启PLL，PLL时钟来源为HSE + FLASH_SetLatency(FLASH_Latency_2); //频率大于24M需要配置FlashWait=2 + res = RCC_SysClk_Switch(RCC_SYSCLKSRC_PLL); //切换系统时钟到PLL + if (res == 0x0U) //切换系统时钟成功 + { + PB08_SETHIGH(); + PB09_SETHIGH(); + RCC_HSI_Disable(); //切换时钟到PLL后关闭源时钟HSI + FirmwareDelay(400000); + } + else + { + while (1) + { + PB08_TOG(); + PB09_TOG(); + FirmwareDelay(10000000); + } + } + //============================================================================ + //以下从PLL切换到HSI + RCC_HSI_Enable(RCC_HSIOSC_DIV2); //开启内部高速时钟HSI = HSIOSC / 2 + res = RCC_SysClk_Switch(RCC_SYSCLKSRC_HSI); //切换系统时钟到HSI + if (res == 0x0U) //切换系统时钟成功 + { + FLASH_SetLatency(FLASH_Latency_1); + PB08_SETLOW(); + PB09_SETLOW(); + RCC_PLL_Disable(); //切换时钟到HSI后关闭PLL时钟 + RCC_HSE_Disable(); //切换时钟到HSI后关闭HSE时钟 + FirmwareDelay(275000); + } + else + { + while (1) + { + PB08_TOG(); + PB09_TOG(); + FirmwareDelay(10000000); + } + } + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/readme.txt new file mode 100644 index 0000000..1ed0673 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hse)/readme.txt @@ -0,0 +1,24 @@ +示例目的： + 系统时钟源在HSI和PLL（参考时钟为HSE）之间进行切换。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI和PLL + 3. HSI作为系统时钟时，设置为HSIOSC到HSI时钟的分频比为2，则SysClk为24MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=24MHz + 4. PLL作为系统时钟时，PLL输入参考时钟选择HSE时钟（16MHz），经过2倍频，PLL输出32MHz时钟。PCLK、HCLK不分频，PCLK=HCLK=SysClk=32MHz，此时需要注意设置FLASH的读访问等待周期，否则程序无法运行。 + +演示说明： + 程序循环在HSI和PLL时钟之间进行切换，通过观察LED灯，正常切换则LED快闪（100mS亮，100mS熄），如果切换失败，则LED灯会慢闪（1S亮，1S熄）。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开rcc_hsi_pll(src_hse).uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32f030.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32f030.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/MDK/rcc_hsi_pll(src_hsi).uvoptx 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + rcc_hsi_pll(src_hsi) + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.5 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + rcc_hsi_pll(src_hsi) + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4098 + + 0 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_flash.c + 1 + ..\..\..\..\Libraries\src\cw32f030_flash.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/USER/inc/main.h new file mode 100644 index 0000000..2f6160d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/USER/src/main.c new file mode 100644 index 0000000..f0af0c9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/USER/src/main.c @@ -0,0 +1,155 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-25 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" +#include "cw32f030_flash.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample HSI switch to PLL, PLL switch to HSI. + ** + ******************************************************************************/ +int32_t main(void) +{ + uint8_t res = 0U; + RCC_AHBPeriphClk_Enable(RCC_AHB_PERIPH_FLASH, ENABLE); //打开FLASH时钟 + //PB8/PB9 推挽输出 + CW_SYSCTRL->AHBEN_f.GPIOB = 1; + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + PB08_SETLOW(); + PB09_SETLOW(); + RCC_PCLK_OUT(); //通过PA03观察PCLK频率 + RCC_HCLK_OUT(); //通过PA04观察HCLK频率 + RCC_HSI_Enable(RCC_HSIOSC_DIV2); //设置HSI = HSIOSC/2 + while (1) + { + //============================================================================ + //以下从HSI切换到PLL + RCC_PLL_Enable(RCC_PLLSOURCE_HSI, 24000000, RCC_PLL_MUL_2); //开启PLL，PLL源为HSI + FLASH_SetLatency(FLASH_Latency_2); //频率大于24M需要配置FlashWait=2 + res = RCC_SysClk_Switch(RCC_SYSCLKSRC_PLL); //切换系统时钟到PLL + if (res == 0x00) //切换系统时钟成功 + { + PB08_SETHIGH(); + PB09_SETHIGH(); + FirmwareDelay(600000); + } + else + { + while (1) + { + PB08_TOG(); + PB09_TOG(); + FirmwareDelay(10000000); + } + } + //============================================================================ + //以下从PLL切换到HSI + res = RCC_SysClk_Switch(RCC_SYSCLKSRC_HSI); //切换系统时钟到HSI + if (res == 0x00) //切换系统时钟成功 + { + FLASH_SetLatency(FLASH_Latency_1); //系统时钟小于等于24M需要配置FlashWait = 0 + PB08_SETLOW(); + PB09_SETLOW(); + RCC_PLL_Disable(); //切换时钟到HSI后关闭PLL时钟 + FirmwareDelay(300000); + } + else + { + while (1) + { + PB08_TOG(); + PB09_TOG(); + FirmwareDelay(10000000); + } + } + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/readme.txt new file mode 100644 index 0000000..4352203 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_hsi_pll(src_hsi)/readme.txt @@ -0,0 +1,24 @@ +示例目的： + 系统时钟源在HSI和PLL（参考时钟为HSI）之间进行切换。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI和PLL + 3. HSI作为系统时钟时，设置为HSIOSC到HSI时钟的分频比为2，则SysClk为24MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=24MHz + 4. PLL作为系统时钟时，PLL输入参考时钟选择HSI时钟（24MHz），经过2倍频，PLL输出48MHz时钟。PCLK、HCLK不分频，PCLK=HCLK=SysClk=48MHz，此时需要注意设置FLASH的读访问等待周期，否则程序无法运行。 + +演示说明： + 程序循环在HSI和PLL时钟之间进行切换，通过观察LED灯，正常切换则LED快闪（100mS亮，100mS熄），如果切换失败，则LED灯会慢闪（1S亮，1S熄）。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开rcc_hsi_pll(src_hsi).uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + debug + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/EWARM/Project.ewp new file mode 100644 index 0000000..49d197c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/EWARM/Project.ewp @@ -0,0 +1,2151 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + + General + 3 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/MDK/rcc_mco.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/MDK/rcc_mco.uvoptx new file mode 100644 index 0000000..ad38a40 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/MDK/rcc_mco.uvoptx @@ -0,0 +1,312 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rcc_mco + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/MDK/rcc_mco.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/MDK/rcc_mco.uvprojx new file mode 100644 index 0000000..ec313c0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/MDK/rcc_mco.uvprojx @@ -0,0 +1,448 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rcc_mco + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + rcc_mco + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4098 + + 0 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/USER/inc/main.h new file mode 100644 index 0000000..2f6160d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/USER/src/main.c new file mode 100644 index 0000000..775d27a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/USER/src/main.c @@ -0,0 +1,146 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-25 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle MCO + ** + ******************************************************************************/ +int32_t main(void) +{ + RCC_HSI_Enable(RCC_HSIOSC_DIV2); //24M + /******************************************************************** + 1. MCO toggle HCLK Test. MCO_CLK = HCLK + *******************************************************************/ + RCC_MCO_OUT(RCC_MCO_SRC_HCLK, RCC_MCO_DIV1); + /******************************************************************** + 2. MCO toggle PCLK Test. MCO_CLK = PCLK / 2 + *******************************************************************/ + // RCC_MCO_OUT( RCC_MCO_SRC_PCLK, RCC_MCO_DIV2 ); + /******************************************************************** + 3. MCO toggle HSI Test. MCO_CLK = HSIOSC / 8 + *******************************************************************/ + // RCC_MCO_OUT( RCC_MCO_SRC_HSI , RCC_MCO_DIV8 ); + /******************************************************************** + 4. MCO toggle LSI Test. MCO_CLK = LSI / 64 + *******************************************************************/ + // RCC_LSI_Enable(); + // RCC_MCO_OUT( RCC_MCO_SRC_LSI , RCC_MCO_DIV64 ); + /******************************************************************** + 5. MCO toggle HSE Test. MCO_CLK = HSE / 128 + *******************************************************************/ + // RCC_HSE_Enable( RCC_HSE_MODE_OSC, 16000000, RCC_HSE_DRIVER_NORMAL, RCC_HSE_FLT_CLOSE); + // RCC_MCO_OUT( RCC_MCO_SRC_HSE , RCC_MCO_DIV128 ); + /******************************************************************** + 6. MCO toggle LSE Test. MCO_CLK = LSE / 256 + *******************************************************************/ + // RCC_LSE_Enable( RCC_LSE_MODE_OSC ,RCC_LSE_AMP_LARGER, RCC_LSE_DRIVER_LARGER ); + // RCC_MCO_OUT( RCC_MCO_SRC_LSE , RCC_MCO_DIV256 ); + /******************************************************************** + 7. MCO toggle PLL Test. MCO_CLK = PLL / 1 + *******************************************************************/ + // RCC_HSE_Enable( RCC_HSE_MODE_OSC, 16000000, RCC_HSE_DRIVER_NORMAL, RCC_HSE_FLT_CLOSE ); + // RCC_PLL_Enable( RCC_PLLSOURCE_HSEOSC, 16000000, RCC_PLL_MUL_2 ); + // RCC_MCO_OUT( RCC_MCO_SRC_PLL , RCC_MCO_DIV1 ); + /******************************************************************** + 8. MCO toggle RC150K Test. MCO_CLK = RC150K + 需要开启端口RC150K滤波或者VC滤波 + *******************************************************************/ + // RCC_AHBPeriphClk_Enable(RCC_AHB_PERIPH_GPIOA, ENABLE); //打开GPIOA时钟 + // GPIO_ConfigFilter( CW_GPIOA, GPIO_PIN_8, GPIO_FLTCLK_RC150K ); //选择GPIOA.08滤波为RC150K + // RCC_MCO_OUT( RCC_MCO_SRC_RC150K, RCC_MCO_DIV1 ); + /******************************************************************** + 9. MCO toggle RC10K Test. MCO_CLK = RC10K + 需要开启端口RC10K滤波或者VC滤波 + *******************************************************************/ + // RCC_AHBPeriphClk_Enable(RCC_AHB_PERIPH_GPIOA, ENABLE); //打开GPIOA时钟 + // GPIO_ConfigFilter( CW_GPIOA, GPIO_PIN_8, GPIO_FLTCLK_RC10K ); //选择GPIOA.08滤波为RC10K + // RCC_MCO_OUT( RCC_MCO_SRC_RC10K, RCC_MCO_DIV1 ); + while (1) {;} +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/readme.txt new file mode 100644 index 0000000..5be9fa4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_mco/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 利用MCO时钟输出功能将各种所需要观测的时钟从PA08引脚输出，用户可根据需要修改时钟源和分频比。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟2分频，24MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=24MHz + +演示说明： + 采用默认时钟配置，并设置MCO时钟输出，用户可根据需要修改时钟源和分频比，修改完成并下载后，用示波器观测PA08引脚的波形，默认程序为24MHz时钟信号。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开rcc_mco.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/EWARM/Project.ewp new file mode 100644 index 0000000..ee89cc4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/EWARM/Project.ewp @@ -0,0 +1,2148 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + debug + + ARM + + 0 + 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Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32f030_rcc.c + + + + Doc + + + ::CMSIS + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/EWARM/Project.eww b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/EWARM/Project.eww new file mode 100644 index 0000000..e0fd14b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/MDK/rcc_pclkout.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/MDK/rcc_pclkout.uvoptx new file mode 100644 index 0000000..4f99204 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/MDK/rcc_pclkout.uvoptx @@ -0,0 +1,300 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rcc_pclkout + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/MDK/rcc_pclkout.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/MDK/rcc_pclkout.uvprojx new file mode 100644 index 0000000..800d6c5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/MDK/rcc_pclkout.uvprojx @@ -0,0 +1,443 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rcc_pclkout + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.3 + + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + rcc_pclkout + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4098 + + 0 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/USER/inc/main.h new file mode 100644 index 0000000..2f6160d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/USER/src/main.c new file mode 100644 index 0000000..fdf9123 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/USER/src/main.c @@ -0,0 +1,106 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-25 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_rcc.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample output PCLK + ** + ******************************************************************************/ +int32_t main(void) +{ + /******************************************************************** + PCLK Output Test. + PCLK 输出到PA03管脚，请通过PA03观察PCLK频率 + *******************************************************************/ + RCC_HSI_Enable(RCC_HSIOSC_DIV2); //24M + RCC_PCLK_OUT(); //PA03输出PCLK + while (1) + { + ; + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/readme.txt new file mode 100644 index 0000000..e3a2042 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/rcc/rcc_pclkout/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 利用PCLK时钟输出功能将PCLK时钟从PA03引脚输出。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟2分频，24MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=24MHz + +演示说明： + 采用默认时钟配置，并设置PCLK时钟输出，用示波器观测PA03引脚的波形，默认程序为24MHz。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开rcc_pclkout.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/readme.txt new file mode 100644 index 0000000..12860ff --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/readme.txt @@ -0,0 +1,3 @@ +cleanup.bat说明： + +1. 清除编译、链接等中间过程中生成的文件 diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/EWARM/Project.ewd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/EWARM/Project.ewd new file mode 100644 index 0000000..c9f817b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/EWARM/Project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + debug + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + 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0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/EWARM/Project.ewp b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/EWARM/Project.ewp new file mode 100644 index 0000000..c96128b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/EWARM/Project.ewp @@ -0,0 +1,2154 @@ + + + 3 + + Release + + ARM + + 0 + + General + 3 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/MDK/systick_delay.uvoptx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/MDK/systick_delay.uvoptx new file mode 100644 index 0000000..96e8c22 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/MDK/systick_delay.uvoptx @@ -0,0 +1,326 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + systick_delay + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_systick.c + cw32f030_systick.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/MDK/systick_delay.uvprojx b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/MDK/systick_delay.uvprojx new file mode 100644 index 0000000..a36d480 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/MDK/systick_delay.uvprojx @@ -0,0 +1,456 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + systick_delay + 0x4 + ARM-ADS + 6190000::V6.19::ARMCLANG + 1 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0P$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + systick_delay + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4098 + + 0 + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 5 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32f030.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32f030.s + + + system_cw32f030.c + 1 + ..\..\..\..\Libraries\src\system_cw32f030.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32f030.c + 1 + ..\USER\src\interrupts_cw32f030.c + + + + + Driver + + + cw32f030_systick.c + 1 + ..\..\..\..\Libraries\src\cw32f030_systick.c + + + cw32f030_rcc.c + 1 + ..\..\..\..\Libraries\src\cw32f030_rcc.c + + + cw32f030_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32f030_gpio.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/USER/inc/interrupts_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/USER/inc/interrupts_cw32f030.h new file mode 100644 index 0000000..456739a --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/USER/inc/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/USER/inc/main.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/USER/inc/main.h new file mode 100644 index 0000000..2f6160d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/USER/src/interrupts_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/USER/src/interrupts_cw32f030.c new file mode 100644 index 0000000..b94a0b4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/USER/src/interrupts_cw32f030.c @@ -0,0 +1,407 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/USER/src/main.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/USER/src/main.c new file mode 100644 index 0000000..1130268 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/USER/src/main.c @@ -0,0 +1,125 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-25 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "cw32f030_systick.h" +#include "cw32f030_rcc.h" +#include "cw32f030_gpio.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** GPIOA00每100mS翻转一次 + ** + ******************************************************************************/ +int32_t main(void) +{ + uint32_t cnt; + RCC_HSI_Enable(RCC_HSIOSC_DIV2); //24M + InitTick(24000000); //初始化SysTick + //PB8/PB9 推挽输出 + CW_SYSCTRL->AHBEN_f.GPIOB = 1; + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + PB08_SETLOW(); + PB09_SETLOW(); + cnt = GetTick(); + while (1) + { + if ((GetTick() - cnt) > 100) + { + cnt = GetTick(); + PB08_TOG(); + PB09_TOG(); + } + } +} +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn */ + uwTick += uwTickFreq; + /* USER CODE END SysTick_IRQn */ +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/readme.txt new file mode 100644 index 0000000..ed9d26f --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Examples/systick/systick_delay/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 利用systick定时器完成100mS定时。 + +硬件资源： + 1. CW32F030C8T6 StartKit 或者CW32F030CxT6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟2分频，24MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=24MHz + +演示说明： + 采用默认时钟配置，并初始化systick为1mS定时，在systick中对32位的uwTick变量进行持续加1（计满后变为0）。在主程序中通过读取uwTick的差值来定时，本程序中利用systick实现100mS的定时进行LED灯闪烁。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开systick_delay.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/debugger/CW/CW32F030.ddf b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/debugger/CW/CW32F030.ddf new file mode 100644 index 0000000..2a8acaa --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/debugger/CW/CW32F030.ddf @@ -0,0 +1,29 @@ + +;; Architecture extensions +#include weak "..\ARM\ARMv6-M-SYST.ddf" + +;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Used to define address zones within the ARM address space (Memory). +;; +;; Name may be almost anything +;; AdrSpace must be Memory +;; StartAdr start of memory block +;; EndAdr end of memory block +;; AccType type of access, read-only (R), read-write (RW) or SFR (W) + +[Memory] +;; Name AdrSpace StartAdr EndAdr AccType Width +Memory = ROM_Factory Memory 0x00012600 0x0001267F R +Memory = OTP Memory 0x00012780 0x000127FF R +Memory = PeriphAPB Memory 0x40000000 0x40014FFF W +Memory = PeriphAHB Memory 0x40020000 0x480017FF W +Memory = SystemSFR Memory 0xE0000000 0xE00FFFFF W +Memory = Flash Memory 0x00000000 0x0000FFFF R +Memory = RAM Memory 0x20000000 0x20001FFF RW + +TrustedRanges = true +UseSfrFilter = true + +[SfrInclude] +File = CW32F030.svd diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/debugger/CW/CW32F030.svd b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/debugger/CW/CW32F030.svd new file mode 100644 index 0000000..d32ecd7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/debugger/CW/CW32F030.svd @@ -0,0 +1,12858 @@ + + + Wuhan Xinyuan Semiconductor Co.Ltd + WHXY + CW32F030 + CW32F030C8xx,CW32F030F6xx,CW32F030F8xx, CW32F030K8xx + ARMCM0P + 1.2 + + CM0+ + r0p1 + little + false + false + 3 + false + + 8 + 32 + 32 + read-write + 0x0 + 0x0 + + + ADC + desc ADC + 0x40012400 + + ADC + ADC Interrupt + 12 + + ADC + 32 + + 0x0 + 0x8C + registers + + + + CR0 + Control register0 + 0x0 + 32 + read-write + + + BIAS + desc BIAS + 15 + 14 + read-write + + + BUF + desc BUF + 13 + 13 + read-write + + + SAM + desc SAM + 12 + 11 + read-write + + + CLK + desc CLK + 10 + 8 + read-write + + + REF + desc REF + 7 + 6 + read-write + + + TSEN + desc TSEN + 5 + 5 + read-write + + + BGREN + desc BGREN + 4 + 4 + read-write + + + MODE + desc MODE + 3 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + CR1 + Control register1 + 0x4 + 32 + read-write + + + WDTALL + desc WDTALL + 13 + 13 + read-write + + + WDTCH + desc WDTCH + 11 + 8 + read-write + + + DMAEN + desc DMAEN + 7 + 7 + read-write + + + ALIGN + desc ALIGN + 6 + 6 + read-write + + + DISCARD + desc DISCARD + 5 + 5 + read-write + + + CHMUX + desc CHMUX + 3 + 0 + read-write + + + + + START + desc START + 0x8 + 32 + read-write + + + AUTOSTOP + desc AUTOSTOP + 1 + 1 + read-write + + + START + desc START + 0 + 0 + read-write + + + + + SQR + desc SQR + 0xC + 32 + read-write + + + ENS + desc ENS + 17 + 16 + read-write + + + SQR3 + desc SQR3 + 15 + 12 + read-write + + + SQR2 + desc SQR2 + 11 + 8 + read-write + + + SQR1 + desc SQR1 + 7 + 4 + read-write + + + SQR0 + desc SQR0 + 3 + 0 + read-write + + + + + CR2 + Control register2 + 0x10 + 32 + read-write + + + ACCRST + desc ACCRST + 9 + 9 + read-write + + + ACCEN + desc ACCEN + 8 + 8 + read-write + + + CNT + desc CNT + 7 + 0 + read-write + + + + + VTH + desc VTH + 0x14 + 32 + read-write + + + VTH + desc VTH + 11 + 0 + read-write + + + + + VTL + desc VTL + 0x18 + 32 + read-write + + + VTL + desc VTL + 11 + 0 + read-write + + + + + TRIGGER + desc TRIGGER + 0x1C + 32 + read-write + + + DMA + desc DMA + 15 + 15 + read-write + + + I2C2 + desc I2C2 + 14 + 14 + read-write + + + I2C1 + desc I2C1 + 13 + 13 + read-write + + + SPI2 + desc SPI2 + 12 + 12 + read-write + + + SPI1 + desc SPI1 + 11 + 11 + read-write + + + UART3 + desc UART3 + 10 + 10 + read-write + + + UART2 + desc UART2 + 9 + 9 + read-write + + + UART1 + desc UART1 + 8 + 8 + read-write + + + BTIM3 + desc BTIM3 + 7 + 7 + read-write + + + BTIM2 + desc BTIM2 + 6 + 6 + read-write + + + BTIM1 + desc BTIM1 + 5 + 5 + read-write + + + GTIM4 + desc GTIM4 + 4 + 4 + read-write + + + GTIM3 + desc GTIM3 + 3 + 3 + read-write + + + GTIM2 + desc GTIM2 + 2 + 2 + read-write + + + GTIM1 + desc GTIM1 + 1 + 1 + read-write + + + ATIM + desc ATIM + 0 + 0 + read-write + + + + + RESULT0 + desc RESULT0 + 0x20 + 32 + read-only + + + RESULT + desc RESULT + 15 + 0 + read-only + + + + + RESULT1 + desc RESULT1 + 0x24 + 32 + read-only + + + RESULT + desc RESULT + 15 + 0 + read-only + + + + + RESULT2 + desc RESULT2 + 0x28 + 32 + read-only + + + RESULT + desc RESULT + 15 + 0 + read-only + + + + + RESULT3 + desc RESULT3 + 0x2C + 32 + read-only + + + RESULT + desc RESULT + 15 + 0 + read-only + + + + + RESULTACC + desc RESULTACC + 0x30 + 32 + read-only + + + RESULT + desc RESULT + 23 + 0 + read-only + + + + + IER + Interrupt enable register + 0x34 + 32 + read-write + + + OVW + desc OVW + 6 + 6 + read-write + + + WDTR + desc WDTR + 5 + 5 + read-write + + + WDTH + desc WDTH + 4 + 4 + read-write + + + WDTL + desc WDTL + 3 + 3 + read-write + + + EOA + desc EOA + 2 + 2 + read-write + + + EOS + desc EOS + 1 + 1 + read-write + + + EOC + desc EOC + 0 + 0 + read-write + + + + + ICR + Interrupt flag clear register + 0x38 + 32 + read-write + + + OVW + desc OVW + 6 + 6 + read-write + + + WDTR + desc WDTR + 5 + 5 + read-write + + + WDTH + desc WDTH + 4 + 4 + read-write + + + WDTL + desc WDTL + 3 + 3 + read-write + + + EOA + desc EOA + 2 + 2 + read-write + + + EOS + desc EOS + 1 + 1 + read-write + + + EOC + desc EOC + 0 + 0 + read-write + + + + + ISR + Interrupt status register + 0x3C + 32 + read-only + + + READY + desc READY + 7 + 7 + read-only + + + OVW + desc OVW + 6 + 6 + read-only + + + WDTR + desc WDTR + 5 + 5 + read-only + + + WDTH + desc WDTH + 4 + 4 + read-only + + + WDTL + desc WDTL + 3 + 3 + read-only + + + EOA + desc EOA + 2 + 2 + read-only + + + EOS + desc EOS + 1 + 1 + read-only + + + EOC + desc EOC + 0 + 0 + read-only + + + + + + + ATIM + desc ATIM + 0x40012C00 + + ATIM + Advanced Timer Interrupt + 13 + + ATIM + 32 + + 0x0 + 0x5C + registers + + + + ARR + desc ARR + 0x0 + 32 + read-write + + + ARR + desc ARR + 15 + 0 + read-write + + + + + CNT + desc CNT + 0x4 + 32 + read-write + + + CNT + desc CNT + 15 + 0 + read-write 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read-write + + + TIF + desc TIF + 15 + 15 + read-write + + + BIF + desc BIF + 14 + 14 + read-write + + + C3BE + desc C3BE + 13 + 13 + read-write + + + C2BE + desc C2BE + 12 + 12 + read-write + + + C1BE + desc C1BE + 11 + 11 + read-write + + + C3AE + desc C3AE + 10 + 10 + read-write + + + C2AE + desc C2AE + 9 + 9 + read-write + + + C1AE + desc C1AE + 8 + 8 + read-write + + + C3BF + desc C3BF + 7 + 7 + read-write + + + C2BF + desc C2BF + 6 + 6 + read-write + + + C1BF + desc C1BF + 5 + 5 + read-write + + + C3AF + desc C3AF + 4 + 4 + read-write + + + C2AF + desc C2AF + 3 + 3 + read-write + + + C1AF + desc C1AF + 2 + 2 + read-write + + + UIF + desc UIF + 0 + 0 + read-write + + + + + MSCR + desc MSCR + 0x18 + 32 + read-write + + + IB1S + desc IB1S + 12 + 12 + read-write + + + IA1S + desc IA1S + 11 + 11 + read-write + + + SMS + desc SMS + 10 + 8 + read-write + + + TS + desc TS + 7 + 5 + read-write + + + CCDS + desc CCDS + 3 + 3 + read-write + + + MMS + desc MMS + 2 + 0 + read-write + + + + + FLTR + desc FLTR + 0x1C + 32 + read-write + + + ETP + desc ETP + 31 + 31 + read-write + + + FLTET + desc FLTET + 30 + 28 + read-write + + + BKP + desc BKP + 27 + 27 + read-write + + + FLTBK + desc FLTBK + 26 + 24 + read-write + + + CCP3B + desc CCP3B + 23 + 23 + read-write + + + OCM3BFLT3B + desc OCM3BFLT3B + 22 + 20 + read-write + + + CCP3A + desc CCP3A + 19 + 19 + read-write + + + OCM3AFLT3A + desc OCM3AFLT3A + 18 + 16 + read-write + + + CCP2B + desc CCP2B + 15 + 15 + read-write + + + OCM2BFLT2B + desc OCM2BFLT2B + 14 + 12 + read-write + + + CCP2A + desc CCP2A + 11 + 11 + read-write + + + OCM2AFLT2A + desc OCM2AFLT2A + 10 + 8 + read-write + + + CCP1B + desc CCP1B + 7 + 7 + read-write + + + OCM1BFLT1B + desc OCM1BFLT1B + 6 + 4 + read-write + + + CCP1A + desc CCP1A + 3 + 3 + read-write + + + OCM1AFLT1A + desc OCM1AFLT1A + 2 + 0 + read-write + + + + + TRIG + desc TRIG + 0x20 + 32 + read-write + + + ADTE + desc ADTE + 7 + 7 + read-write + + + CM3BE + desc CM3BE + 6 + 6 + read-write + + + CM2BE + desc CM2BE + 5 + 5 + read-write + + + CM1BE + desc CM1BE + 4 + 4 + read-write + + + CM3AE + desc CM3AE + 3 + 3 + read-write + + + CM2AE + desc CM2AE + 2 + 2 + read-write + + + CM1AE + desc CM1AE + 1 + 1 + read-write + + + UEVE + desc UEVE + 0 + 0 + read-write + + + + + CH1CR + desc CH1CR + 0x24 + 32 + read-write + + + CCGB + desc CCGB + 15 + 15 + read-write + + + CCGA + desc CCGA + 14 + 14 + read-write + + + CISB + desc CISB + 13 + 12 + read-write + + + CDEB + desc CDEB + 11 + 11 + read-write + + + CDEA + desc CDEA + 10 + 10 + read-write + + + CIEB + desc CIEB + 9 + 9 + read-write + + + CIEA + desc CIEA + 8 + 8 + read-write + + + BUFEB + desc BUFEB + 7 + 7 + read-write + + + BUFEA + desc BUFEA + 6 + 6 + read-write + + + CSB + desc CSB + 5 + 5 + read-write + + + CSA + desc CSA + 4 + 4 + read-write + + + BKSB + desc BKSB + 3 + 2 + read-write + + + BKSA + desc BKSA + 1 + 0 + read-write + + + + + CH2CR + desc CH2CR + 0x28 + 32 + read-write + + + CCGB + desc CCGB + 15 + 15 + read-write + + + CCGA + desc CCGA + 14 + 14 + read-write + + + CISB + desc CISB + 13 + 12 + read-write + + + CDEB + desc CDEB + 11 + 11 + read-write + + + CDEA + desc CDEA + 10 + 10 + read-write + + + CIEB + desc CIEB + 9 + 9 + read-write + + + CIEA + desc CIEA + 8 + 8 + read-write + + + BUFEB + desc BUFEB + 7 + 7 + read-write + + + BUFEA + desc BUFEA + 6 + 6 + read-write + + + CSB + desc CSB + 5 + 5 + read-write + + + CSA + desc CSA + 4 + 4 + read-write + + + BKSB + desc BKSB + 3 + 2 + read-write + + + BKSA + desc BKSA + 1 + 0 + read-write + + + + + CH3CR + desc CH3CR + 0x2C + 32 + read-write + + + CCGB + desc CCGB + 15 + 15 + read-write + + + CCGA + desc CCGA + 14 + 14 + read-write + + + CISB + desc CISB + 13 + 12 + read-write + + + CDEB + desc CDEB + 11 + 11 + read-write + + + CDEA + desc CDEA + 10 + 10 + read-write + + + CIEB + desc CIEB + 9 + 9 + read-write + + + CIEA + desc CIEA + 8 + 8 + read-write + + + BUFEB + desc BUFEB + 7 + 7 + read-write + + + BUFEA + desc BUFEA + 6 + 6 + read-write + + + CSB + desc CSB + 5 + 5 + read-write + + + CSA + desc CSA + 4 + 4 + read-write + + + BKSB + desc BKSB + 3 + 2 + read-write + + + BKSA + desc BKSA + 1 + 0 + read-write + + + + + DTR + desc DTR + 0x30 + 32 + read-write + + + VCE + desc VCE + 14 + 14 + read-write + + + SAFEEN + desc SAFEEN + 13 + 13 + read-write + + + MOE + desc MOE + 12 + 12 + read-write + + + AOE + desc AOE + 11 + 11 + read-write + + + BKE + desc BKE + 10 + 10 + read-write + + + DTEN + desc DTEN + 9 + 9 + read-write + + + DTR + desc DTR + 7 + 0 + read-write + + + + + RCR + desc RCR + 0x34 + 32 + read-write + + + UD + desc UD + 9 + 9 + read-write + + + OV + desc OV + 8 + 8 + read-write + + + RCR + desc RCR + 7 + 0 + read-write + + + + + CH1CCRA + desc CH1CCRA + 0x3C + 32 + read-write + + + CCR1A + desc CCR1A + 15 + 0 + read-write + + + + + CH1CCRB + desc CH1CCRB + 0x40 + 32 + read-write + + + CCR1B + desc CCR1B + 15 + 0 + read-write + + + + + CH2CCRA + desc CH2CCRA + 0x44 + 32 + read-write + + + CCR2A + desc CCR2A + 15 + 0 + read-write + + + + + CH2CCRB + desc CH2CCRB + 0x48 + 32 + read-write + + + CCR2B + desc CCR2B + 15 + 0 + read-write + + + + + CH3CCRA + desc CH3CCRA + 0x4C + 32 + read-write + + + CCR3A + desc CCR3A + 15 + 0 + read-write + + + + + CH3CCRB + desc CH3CCRB + 0x50 + 32 + read-write + + + CCR3B + desc CCR3B + 15 + 0 + read-write + + + + + CH4CCR + desc CH4CCR + 0x54 + 32 + read-write + + + CCR4 + desc CCR4 + 15 + 0 + read-write + + + + + CH4CR + desc CH4CR + 0x58 + 32 + read-write + + + C4EN + desc C4EN + 5 + 5 + read-write + + + CIS + desc CIS + 4 + 3 + read-write + + + CDE + desc CDE + 2 + 2 + read-write + + + CIE + desc CIE + 1 + 1 + read-write + + + BUFE + desc BUFE + 0 + 0 + read-write + + + + + + + AWT + desc AWT + 0x40014C00 + + AWT + Auto Wakeup Timer Interrupt + 30 + + AWT + 32 + + 0x0 + 0x20 + registers + + + + CR + Control register + 0x0 + 32 + read-write + + + SRC + desc SRC + 10 + 8 + read-write + + + PRS + desc PRS + 7 + 4 + read-write + + + MD + desc MD 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ETRFLT + 6 + 4 + read-write + + + + + BCR + Base Control register + 0x10 + 32 + read-write + + + PRSSTATUS + desc PRSSTATUS + 14 + 11 + read-only + + + PRS + desc PRS + 10 + 7 + read-write + + + TOGEN + desc TOGEN + 6 + 6 + read-write + + + ONESHOT + desc ONESHOT + 5 + 5 + read-write + + + POL + desc POL + 4 + 4 + read-write + + + TRS + desc TRS + 3 + 3 + read-write + + + MODE + desc MODE + 2 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + IER + Interrupt enable register + 0x14 + 32 + read-write + + + TOP + desc TOP + 2 + 2 + read-write + + + TI + desc TI + 1 + 1 + read-write + + + OV + desc OV + 0 + 0 + read-write + + + + + ISR + Interrupt status register + 0x18 + 32 + read-only + + + TOP + desc TOP + 2 + 2 + read-only + + + TI + desc TI + 1 + 1 + read-only + + + OV + desc OV + 0 + 0 + read-only + + + + + ICR + Interrupt flag clear register + 0x1C + 32 + read-write + + + TOP + desc TOP + 2 + 2 + read-write + + + TI + desc TI + 1 + 1 + read-write + + + OV + desc OV + 0 + 0 + read-write + + + + + DMA + DMA control register + 0x20 + 32 + read-write + + + TRS + desc TRS + 1 + 1 + read-write + + + OV + desc OV + 0 + 0 + read-write + + + + + + + BTIM2 + Base Timer 2 + 0x40014900 + + BTIM2 + Base Timer2 Interrupt + 21 + + + + BTIM3 + Base Timer 3 + 0x40014A00 + + BTIM3 + Base Timer3 Interrupt + 22 + + + + CRC + desc CRC + 0x40023000 + CRC + 32 + + 0x0 + 0x10 + registers + + + + CR + Control register + 0x0 + 32 + read-write + + + MODE + desc MODE + 3 + 0 + read-write + + + + + DR32 + Data register + 0x8 + 32 + read-write + + + DR32 + desc DR32 + 31 + 0 + read-write + + + + + DR16 + Data register + DR32 + 0x8 + 16 + read-write + + + DR16 + desc DR16 + 15 + 0 + read-write + + + + + DR8 + Data register + DR32 + 0x8 + 8 + read-write + + + DR8 + desc DR8 + 7 + 0 + read-write + + + + + RESULT32 + Result register + 0xC + 32 + read-only + + + RESULT32 + desc RESULT32 + 31 + 0 + read-only + + + + + RESULT16 + Result register + RESULT32 + 0xC + 16 + read-only + + + RESULT16 + desc RESULT16 + 15 + 0 + read-only + + + + + + + DMA + desc DMA + 0x40020000 + + DMACH1 + DMA Channel 1 Interrupt + 9 + + DMA + DMA + 32 + + 0x0 + 0xB4 + registers + + + + ISR + Interrupt status register + 0x0 + 32 + read-only + + + TE5 + desc TE5 + 17 + 17 + read-only + + + TC5 + desc TC5 + 16 + 16 + read-only + + + TE4 + desc TE4 + 13 + 13 + read-only + + + TC4 + desc TC4 + 12 + 12 + read-only + + + TE3 + desc TE3 + 9 + 9 + read-only + + + TC3 + desc TC3 + 8 + 8 + read-only + + + TE2 + desc TE2 + 5 + 5 + read-only + + + TC2 + desc TC2 + 4 + 4 + read-only + + + TE1 + desc TE1 + 1 + 1 + read-only + + + TC1 + desc TC1 + 0 + 0 + read-only + + + + + ICR + Interrupt flag clear register + 0x4 + 32 + read-write + + + TE5 + desc TE5 + 17 + 17 + read-write + + + TC5 + desc TC5 + 16 + 16 + read-write + + + TE4 + desc TE4 + 13 + 13 + read-write + + + TC4 + desc TC4 + 12 + 12 + read-write + + + TE3 + desc TE3 + 9 + 9 + read-write + + + TC3 + desc TC3 + 8 + 8 + read-write + + + TE2 + desc TE2 + 5 + 5 + read-write + + + TC2 + desc TC2 + 4 + 4 + read-write + + + TE1 + desc TE1 + 1 + 1 + read-write + + + TC1 + desc TC1 + 0 + 0 + read-write + + + + + CSR1 + Channel1 control and status register + 0x20 + 32 + read-write + + + STATUS + desc STATUS + 10 + 8 + read-only + + + SIZE + desc SIZE + 7 + 6 + read-write + + + DSTINC + desc DSTINC + 5 + 5 + read-write + + + SRCINC + desc SRCINC + 4 + 4 + read-write + + + TRANS + desc TRANS + 3 + 3 + read-write + + + TEIE + desc TEIE + 2 + 2 + read-write + + + TCIE + desc TCIE + 1 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + CNT1 + Channel1 counter register + 0x24 + 32 + read-write + + + REPEAT + desc REPEAT + 19 + 16 + read-write + + + CNT + desc CNT + 15 + 0 + read-write + + + + + SRCADDR1 + Channel1 source address register + 0x28 + 32 + read-write + + + SRCADDR + desc SRCADDR + 31 + 0 + read-write + + + + + DSTADDR1 + Channel1 destination address register + 0x2C + 32 + read-write + + + DSTADDR + desc DSTADDR + 31 + 0 + read-write + + + + + TRIG1 + Channel1 trigger register + 0x30 + 32 + read-write + + + HARDSRC + desc HARDSRC + 7 + 2 + read-write + + + SOFTSRC + desc SOFTSRC + 1 + 1 + read-write + + + TYPE + desc TYPE + 0 + 0 + read-write + + + + + CSR2 + Channel2 control and status register + 0x40 + 32 + read-write + + + STATUS + desc STATUS + 10 + 8 + read-only + + + SIZE + desc SIZE + 7 + 6 + read-write + + + DSTINC + desc DSTINC + 5 + 5 + read-write + + + SRCINC + desc SRCINC + 4 + 4 + read-write + + + TRANS + desc TRANS + 3 + 3 + read-write + + + TEIE + desc TEIE + 2 + 2 + read-write + + + TCIE + desc TCIE + 1 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + CNT2 + Channel2 counter register + 0x44 + 32 + read-write + + + REPEAT + desc REPEAT + 19 + 16 + read-write + + + CNT + desc CNT + 15 + 0 + read-write + + + + + SRCADDR2 + Channel2 source address register + 0x48 + 32 + read-write + + + SRCADDR + desc SRCADDR + 31 + 0 + read-write + + + + + DSTADDR2 + Channel2 destination address register + 0x4C + 32 + read-write + + + DSTADDR + desc DSTADDR + 31 + 0 + read-write + + + + + TRIG2 + Channel2 trigger register + 0x50 + 32 + read-write + + + HARDSRC + desc HARDSRC + 7 + 2 + read-write + + + SOFTSRC + desc SOFTSRC + 1 + 1 + read-write + + + TYPE + desc TYPE + 0 + 0 + read-write + + + + + CSR3 + Channel3 control and status register + 0x60 + 32 + read-write + + + STATUS + desc STATUS + 10 + 8 + read-only + + + SIZE + desc SIZE + 7 + 6 + read-write + + + DSTINC + desc DSTINC + 5 + 5 + read-write + + + SRCINC + desc SRCINC + 4 + 4 + read-write + + + TRANS + desc TRANS + 3 + 3 + read-write + + + TEIE + desc TEIE + 2 + 2 + read-write + + + TCIE + desc TCIE + 1 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + CNT3 + Channel3 counter register + 0x64 + 32 + read-write + + + REPEAT + desc REPEAT + 19 + 16 + read-write + + + CNT + desc CNT + 15 + 0 + read-write + + + + + SRCADDR3 + Channel3 source address register + 0x68 + 32 + read-write + + + SRCADDR + desc SRCADDR + 31 + 0 + read-write + + + + + DSTADDR3 + Channel3 destination address register + 0x6C + 32 + read-write + + + DSTADDR + desc DSTADDR + 31 + 0 + read-write + + + + + TRIG3 + Channel3 trigger register + 0x70 + 32 + read-write + + + HARDSRC + desc HARDSRC + 7 + 2 + read-write + + + SOFTSRC + desc SOFTSRC + 1 + 1 + read-write + + + TYPE + desc TYPE + 0 + 0 + read-write + + + + + CSR4 + Channel4 control and status register + 0x80 + 32 + read-write + + + STATUS + desc STATUS + 10 + 8 + read-only + + + SIZE + desc SIZE + 7 + 6 + read-write + + + DSTINC + desc DSTINC + 5 + 5 + read-write + + + SRCINC + desc SRCINC + 4 + 4 + read-write + + + TRANS + desc TRANS + 3 + 3 + read-write + + + TEIE + desc TEIE + 2 + 2 + read-write + + + TCIE + desc TCIE + 1 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + CNT4 + Channel4 counter register + 0x84 + 32 + read-write + + + REPEAT + desc REPEAT + 19 + 16 + read-write + + + CNT + desc CNT + 15 + 0 + read-write + + + + + SRCADDR4 + Channel4 source address register + 0x88 + 32 + read-write + + + SRCADDR + desc SRCADDR + 31 + 0 + read-write + + + + + DSTADDR4 + Channel4 destination address register + 0x8C + 32 + read-write + + + DSTADDR + desc DSTADDR + 31 + 0 + read-write + + + + + TRIG4 + Channel4 trigger register + 0x90 + 32 + read-write + + + HARDSRC + desc HARDSRC + 7 + 2 + read-write + + + SOFTSRC + desc SOFTSRC + 1 + 1 + read-write + + + TYPE + desc TYPE + 0 + 0 + read-write + + + + + CSR5 + Channel5 control and status register + 0xA0 + 32 + read-write + + + STATUS + desc STATUS + 10 + 8 + read-only + + + SIZE + desc SIZE + 7 + 6 + read-write + + + DSTINC + desc DSTINC + 5 + 5 + read-write + + + SRCINC + desc SRCINC + 4 + 4 + read-write + + + TRANS + desc TRANS + 3 + 3 + read-write + + + TEIE + desc TEIE + 2 + 2 + read-write + + + TCIE + desc TCIE + 1 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + CNT5 + Channel5 counter register + 0xA4 + 32 + read-write + + + REPEAT + desc REPEAT + 19 + 16 + read-write + + + CNT + desc CNT + 15 + 0 + read-write + + + + + SRCADDR5 + Channel5 source address register + 0xA8 + 32 + read-write + + + SRCADDR + desc SRCADDR + 31 + 0 + read-write + + + + + DSTADDR5 + Channel5 destination address register + 0xAC + 32 + read-write + + + DSTADDR + desc DSTADDR + 31 + 0 + read-write + + + + + TRIG5 + Channel5 trigger register + 0xB0 + 32 + read-write + + + HARDSRC + desc HARDSRC + 7 + 2 + read-write + + + SOFTSRC + desc SOFTSRC + 1 + 1 + read-write + + + TYPE + desc TYPE + 0 + 0 + read-write + + + + + + + DMACHANNEL1 + DMA Channel 1 + 0x40020020 + DMA + + DMACH1 + DMA Channel 1 Interrupt + 9 + + DMA + DMACHANNEL + 32 + + 0x0 + 0x14 + registers + + + + CSR + Channel.y control and status register + 0x0 + 32 + read-write + + + STATUS + desc STATUS + 10 + 8 + read-only + + + SIZE + desc SIZE + 7 + 6 + read-write + + + DSTINC + desc DSTINC + 5 + 5 + read-write + + + SRCINC + desc SRCINC + 4 + 4 + read-write + + + TRANS + desc TRANS + 3 + 3 + read-write + + + TEIE + desc TEIE + 2 + 2 + read-write + + + TCIE + desc TCIE + 1 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + CNT + Channel.y counter register + 0x4 + 32 + read-write + + + REPEAT + desc REPEAT + 19 + 16 + read-write + + + CNT + desc CNT + 15 + 0 + read-write + + + + + SRCADDR + Channel.y source address register + 0x8 + 32 + read-write + + + SRCADDR + desc SRCADDR + 31 + 0 + read-write + + + + + DSTADDR + Channel.y destination address register + 0xC + 32 + read-write + + + DSTADDR + desc DSTADDR + 31 + 0 + read-write + + + + + TRIG + Channel.y trigger register + 0x10 + 32 + read-write + + + HARDSRC + desc HARDSRC + 7 + 2 + read-write + + + SOFTSRC + desc SOFTSRC + 1 + 1 + read-write + + + TYPE + desc TYPE + 0 + 0 + read-write + + + + + + + DMACHANNEL2 + DMA Channel 2 + 0x40020040 + DMA + + DMACH23 + DMA Channel 2/3 Interrupt + 10 + + + + DMACHANNEL3 + DMA Channel 3 + 0x40020060 + DMA + + DMACH23 + DMA Channel 2/3 Interrupt + 10 + + + + DMACHANNEL4 + DMA Channel 4 + 0x40020080 + DMA + + DMACH45 + DMA Channel 2/3 Interrupt + 11 + + + + DMACHANNEL5 + DMA Channel 5 + 0x400200A0 + DMA + + DMACH45 + DMA Channel 2/3 Interrupt + 11 + + + + FLASH + desc FLASH + 0x40022000 + + FLASHRAM + Flash/RAM Interrupt + 3 + + FLASH + 32 + + 0x0 + 0x2C + registers + + + + CR1 + Control register1 + 0x0 + 32 + read-write + + + KEY + desc KEY + 31 + 16 + write-only + + + SECURITY + desc SECURITY + 7 + 6 + read-only + + + BUSY + desc BUSY + 5 + 5 + read-only + + + STANDBY + desc STANDBY + 4 + 4 + read-write + + + MODE + desc MODE + 1 + 0 + read-write + + + + + CR2 + Control register2 + 0x4 + 32 + read-write + + + KEY + desc KEY + 31 + 16 + write-only + + + CACHE + desc CACHE + 4 + 4 + read-write + + + FETCH + desc FETCH + 3 + 3 + read-write + + + WAIT + desc WAIT + 2 + 0 + read-write + + + + + PAGELOCK + Page Write Erase Lock + 0x8 + 32 + read-write + + + KEY + desc KEY + 31 + 16 + write-only + + + LOCK15 + Page120 - 127 + 15 + 15 + read-write + + + LOCK14 + Page112 - 119 + 14 + 14 + read-write + + + LOCK13 + Page104 - 111 + 13 + 13 + read-write + + + LOCK12 + Page96 - 103 + 12 + 12 + read-write + + + LOCK11 + Page88 - 95 + 11 + 11 + read-write + + + LOCK10 + Page80 - 87 + 10 + 10 + read-write + + + LOCK9 + Page72 - 79 + 9 + 9 + read-write + + + LOCK8 + Page64 - 71 + 8 + 8 + read-write + + + LOCK7 + Page56 - 63 + 7 + 7 + read-write + + + LOCK6 + Page48 - 55 + 6 + 6 + read-write + + + LOCK5 + Page40 - 47 + 5 + 5 + read-write + + + LOCK4 + Page32 - 39 + 4 + 4 + read-write + + + LOCK3 + Page24 - 31 + 3 + 3 + read-write + + + LOCK2 + Page16 - 23 + 2 + 2 + read-write + + + LOCK1 + Page8 - 15 + 1 + 1 + read-write + + + LOCK0 + Page0 - 7 + 0 + 0 + read-write + + + + + IER + Interrupt enable register + 0x20 + 32 + read-write + + + PROG + desc PROG + 4 + 4 + read-write + + + PAGELOCK + desc PAGELOCK + 1 + 1 + read-write + + + PC + desc PC + 0 + 0 + read-write + + + + + ISR + Interrupt status register + 0x24 + 32 + read-only + + + PROG + desc PROG + 4 + 4 + read-only + + + PAGELOCK + desc PAGELOCK + 1 + 1 + read-only + + + PC + desc PC + 0 + 0 + read-only + + + + + ICR + Interrupt flag clear register + 0x28 + 32 + read-write + + + PROG + desc PROG + 4 + 4 + read-write + + + PAGELOCK + desc PAGELOCK + 1 + 1 + read-write + + + PC + desc PC + 0 + 0 + read-write + + + + + + + GPIOA + desc GPIOA + 0x48000000 + + GPIOA + GPIOA Interrupt + 5 + + GPIO + GPIO + 32 + + 0x0 + 0x64 + registers + + + + DIR + desc DIR + 0x0 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + OPENDRAIN + desc OPENDRAIN + 0x4 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + SPEED + desc SPEED + 0x8 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + PDR + desc PDR + 0xC + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + PUR + desc PUR + 0x10 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + AFRH + desc AFRH + 0x14 + 32 + read-write + + + AFR15 + desc AFR15 + 31 + 28 + read-write + + + AFR14 + desc AFR14 + 27 + 24 + read-write + + + AFR13 + desc AFR13 + 23 + 20 + read-write + + + AFR12 + desc AFR12 + 19 + 16 + read-write + + + AFR11 + desc AFR11 + 15 + 12 + read-write + + + AFR10 + desc AFR10 + 11 + 8 + read-write + + + AFR9 + desc AFR9 + 7 + 4 + read-write + + + AFR8 + desc AFR8 + 3 + 0 + read-write + + + + + AFRL + desc AFRL + 0x18 + 32 + read-write + + + AFR7 + desc AFR7 + 31 + 28 + read-write + + + AFR6 + desc AFR6 + 27 + 24 + read-write + + + AFR5 + desc AFR5 + 23 + 20 + read-write + + + AFR4 + desc AFR4 + 19 + 16 + read-write + + + AFR3 + desc AFR3 + 15 + 12 + read-write + + + AFR2 + desc AFR2 + 11 + 8 + read-write + + + AFR1 + desc AFR1 + 7 + 4 + read-write + + + AFR0 + desc AFR0 + 3 + 0 + read-write + + + + + ANALOG + desc ANALOG + 0x1C + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + DRIVER + desc DRIVER + 0x20 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + RISEIE + Interrupt enable register + 0x24 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + FALLIE + Interrupt enable register + 0x28 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + HIGHIE + Interrupt enable register + 0x2C + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + LOWIE + Interrupt enable register + 0x30 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + ISR + Interrupt status register + 0x34 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + ICR + Interrupt flag clear register + 0x38 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + LOCK + desc LOCK + 0x3C + 32 + read-write + + + KEY + KEY = 0x5A5A + 31 + 16 + write-only + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + FILTER + desc FILTER + 0x40 + 32 + read-write + + + FLTCLK + desc FLTCLK + 18 + 16 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + IDR + desc IDR + 0x50 + 32 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN9 + desc PIN9 + 9 + 9 + read-only + + + PIN8 + desc PIN8 + 8 + 8 + read-only + + + PIN7 + desc PIN7 + 7 + 7 + read-only + + + PIN6 + desc PIN6 + 6 + 6 + read-only + + + PIN5 + desc PIN5 + 5 + 5 + read-only + + + PIN4 + desc PIN4 + 4 + 4 + read-only + + + PIN3 + desc PIN3 + 3 + 3 + read-only + + + PIN2 + desc PIN2 + 2 + 2 + read-only + + + PIN1 + desc PIN1 + 1 + 1 + read-only + + + PIN0 + desc PIN0 + 0 + 0 + read-only + + + + + ODR + desc ODR + 0x54 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + ODRLOWBYTE + desc ODRLOWBYTE + ODR + 0x54 + 8 + read-write + + + LOWBYTE + desc LOWBYTE + 7 + 0 + read-write + + + + + ODRHIGHBYTE + desc ODRHIGHBYTE + ODR + 0x55 + 8 + read-write + + + HIGHBYTE + desc HIGHBYTE + 7 + 0 + read-write + + + + + BRR + desc BRR + 0x58 + 32 + read-write + + + BRR15 + desc BRR15 + 15 + 15 + read-write + + + BRR14 + desc BRR14 + 14 + 14 + read-write + + + BRR13 + desc BRR13 + 13 + 13 + read-write + + + BRR12 + desc BRR12 + 12 + 12 + read-write + + + BRR11 + desc BRR11 + 11 + 11 + read-write + + + BRR10 + desc BRR10 + 10 + 10 + read-write + + + BRR9 + desc BRR9 + 9 + 9 + read-write + + + BRR8 + desc BRR8 + 8 + 8 + read-write + + + BRR7 + desc BRR7 + 7 + 7 + read-write + + + BRR6 + desc BRR6 + 6 + 6 + read-write + + + BRR5 + desc BRR5 + 5 + 5 + read-write + + + BRR4 + desc BRR4 + 4 + 4 + read-write + + + BRR3 + desc BRR3 + 3 + 3 + read-write + + + BRR2 + desc BRR2 + 2 + 2 + read-write + + + BRR1 + desc BRR1 + 1 + 1 + read-write + + + BRR0 + desc BRR0 + 0 + 0 + read-write + + + + + BSRR + desc BSRR + 0x5C + 32 + read-write + + + BRR15 + desc BRR15 + 31 + 31 + read-write + + + BRR14 + desc BRR14 + 30 + 30 + read-write + + + BRR13 + desc BRR13 + 29 + 29 + read-write + + + BRR12 + desc BRR12 + 28 + 28 + read-write + + + BRR11 + desc BRR11 + 27 + 27 + read-write + + + BRR10 + desc BRR10 + 26 + 26 + read-write + + + BRR9 + desc BRR9 + 25 + 25 + read-write + + + BRR8 + desc BRR8 + 24 + 24 + read-write + + + BRR7 + desc BRR7 + 23 + 23 + read-write + + + BRR6 + desc BRR6 + 22 + 22 + read-write + + + BRR5 + desc BRR5 + 21 + 21 + read-write + + + BRR4 + desc BRR4 + 20 + 20 + read-write + + + BRR3 + desc BRR3 + 19 + 19 + read-write + + + BRR2 + desc BRR2 + 18 + 18 + read-write + + + BRR1 + desc BRR1 + 17 + 17 + read-write + + + BRR0 + desc BRR0 + 16 + 16 + read-write + + + BSS15 + desc BSS15 + 15 + 15 + read-write + + + BSS14 + desc BSS14 + 14 + 14 + read-write + + + BSS13 + desc BSS13 + 13 + 13 + read-write + + + BSS12 + desc BSS12 + 12 + 12 + read-write + + + BSS11 + desc BSS11 + 11 + 11 + read-write + + + BSS10 + desc BSS10 + 10 + 10 + read-write + + + BSS9 + desc BSS9 + 9 + 9 + read-write + + + BSS8 + desc BSS8 + 8 + 8 + read-write + + + BSS7 + desc BSS7 + 7 + 7 + read-write + + + BSS6 + desc BSS6 + 6 + 6 + read-write + + + BSS5 + desc BSS5 + 5 + 5 + read-write + + + BSS4 + desc BSS4 + 4 + 4 + read-write + + + BSS3 + desc BSS3 + 3 + 3 + read-write + + + BSS2 + desc BSS2 + 2 + 2 + read-write + + + BSS1 + desc BSS1 + 1 + 1 + read-write + + + BSS0 + desc BSS0 + 0 + 0 + read-write + + + + + TOG + desc TOG + 0x60 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + + + GPIOB + desc GPIOB + 0x48000400 + + GPIOB + GPIOB Interrupt + 6 + + + + GPIOC + desc GPIOC + 0x48000800 + + GPIOC + GPIOC Interrupt + 7 + + GPIO + GPIOC + 32 + + 0x0 + 0x64 + registers + + + + DIR + desc DIR + 0x0 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + OPENDRAIN + desc OPENDRAIN + 0x4 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + SPEED + desc SPEED + 0x8 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + PDR + desc PDR + 0xC + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + PUR + desc PUR + 0x10 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + AFRH + desc AFRH + 0x14 + 32 + read-write + + + AFR15 + desc AFR15 + 31 + 28 + read-write + + + AFR14 + desc AFR14 + 27 + 24 + read-write + + + AFR13 + desc AFR13 + 23 + 20 + read-write + + + + + ANALOG + desc ANALOG + 0x1C + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + DRIVER + desc DRIVER + 0x20 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + RISEIE + Interrupt enable register + 0x24 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + FALLIE + Interrupt enable register + 0x28 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + HIGHIE + Interrupt enable register + 0x2C + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + LOWIE + Interrupt enable register + 0x30 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + ISR + Interrupt status register + 0x34 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + ICR + Interrupt flag clear register + 0x38 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + LOCK + desc LOCK + 0x3C + 32 + read-write + + + KEY + KEY = 0x5A5A + 31 + 16 + write-only + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + FILTER + desc FILTER + 0x40 + 32 + read-write + + + FLTCLK + desc FLTCLK + 18 + 16 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + IDR + desc IDR + 0x50 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + ODR + desc ODR + 0x54 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + ODRLOWBYTE + desc ODRLOWBYTE + ODR + 0x54 + 8 + read-write + + + LOWBYTE + desc LOWBYTE + 7 + 0 + read-write + + + + + ODRHIGHBYTE + desc ODRHIGHBYTE + ODR + 0x55 + 8 + read-write + + + HIGHBYTE + desc HIGHBYTE + 7 + 0 + read-write + + + + + BRR + desc BRR + 0x58 + 32 + read-write + + + BRR15 + desc BRR15 + 15 + 15 + read-write + + + BRR14 + desc BRR14 + 14 + 14 + read-write + + + BRR13 + desc BRR13 + 13 + 13 + read-write + + + + + BSRR + desc BSRR + 0x5C + 32 + read-write + + + BRR15 + desc BRR15 + 31 + 31 + read-write + + + BRR14 + desc BRR14 + 30 + 30 + read-write + + + BRR13 + desc BRR13 + 29 + 29 + read-write + + + BSS15 + desc BSS15 + 15 + 15 + read-write + + + BSS14 + desc BSS14 + 14 + 14 + read-write + + + BSS13 + desc BSS13 + 13 + 13 + read-write + + + + + TOG + desc TOG + 0x60 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + + + + + GPIOF + desc GPIOF + 0x48001400 + + GPIOF + GPIOF Interrupt + 8 + + GPIO + GPIOF + 32 + + 0x0 + 0x64 + registers + + + + DIR + desc DIR + 0x0 + 32 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + OPENDRAIN + desc OPENDRAIN + 0x4 + 32 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + SPEED + desc SPEED + 0x8 + 32 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + PDR + desc PDR + 0xC + 32 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + PUR + desc PUR + 0x10 + 32 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + AFRL + desc AFRL + 0x18 + 32 + read-write + + + AFR7 + desc AFR7 + 31 + 28 + read-write + + + AFR6 + desc AFR6 + 27 + 24 + read-write + + + AFR3 + desc AFR3 + 15 + 12 + read-write + + + AFR1 + desc AFR1 + 7 + 4 + read-write + + + AFR0 + desc AFR0 + 3 + 0 + read-write + + + + + ANALOG + desc ANALOG + 0x1C + 32 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + DRIVER + desc DRIVER + 0x20 + 32 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + RISEIE + Interrupt enable register + 0x24 + 32 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + FALLIE + Interrupt enable register + 0x28 + 32 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + HIGHIE + Interrupt enable register + 0x2C + 32 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + LOWIE + Interrupt enable register + 0x30 + 32 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + ISR + Interrupt status register + 0x34 + 32 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + ICR + Interrupt flag clear register + 0x38 + 32 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + LOCK + desc LOCK + 0x3C + 32 + read-write + + + KEY + KEY = 0x5A5A + 31 + 16 + write-only + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + FILTER + desc FILTER + 0x40 + 32 + read-write + + + FLTCLK + desc FLTCLK + 18 + 16 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + IDR + desc IDR + 0x50 + 32 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + ODR + desc ODR + 0x54 + 32 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + ODRLOWBYTE + desc ODRLOWBYTE + ODR + 0x54 + 8 + read-write + + + LOWBYTE + desc LOWBYTE + 7 + 0 + read-write + + + + + BRR + desc BRR + 0x58 + 32 + read-write + + + BRR7 + desc BRR7 + 7 + 7 + read-write + + + BRR6 + desc BRR6 + 6 + 6 + read-write + + + BRR3 + desc BRR3 + 3 + 3 + read-write + + + BRR1 + desc BRR1 + 1 + 1 + read-write + + + BRR0 + desc BRR0 + 0 + 0 + read-write + + + + + BSRR + desc BSRR + 0x5C + 32 + read-write + + + BSS7 + desc BSS7 + 7 + 7 + read-write + + + BSS6 + desc BSS6 + 6 + 6 + read-write + + + BSS3 + desc BSS3 + 3 + 3 + read-write + + + BSS1 + desc BSS1 + 1 + 1 + read-write + + + BSS0 + desc BSS0 + 0 + 0 + read-write + + + + + TOG + desc TOG + 0x60 + 32 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + + + GTIM1 + General Timer 1 + 0x40000400 + + GTIM1 + General Timer1 Interrupt + 16 + + GTIM + GTIM + 32 + + 0x0 + 0x344 + registers + + + + ARR + Auto Reload Register + 0x300 + 32 + read-write + + + ARR + desc ARR + 15 + 0 + read-write + + + + + CNT + Counter Register + 0x304 + 32 + read-write + + + CNT + desc CNT + 15 + 0 + read-write + + + + + CMMR + Capture compare control Register + 0x308 + 32 + read-write + + + CC4M + desc CC4M + 15 + 12 + read-write + + + CC3M + desc CC3M + 11 + 8 + read-write + + + CC2M + desc CC2M + 7 + 4 + read-write + + + CC1M + desc CC1M + 3 + 0 + read-write + + + + + ETR + ETR Control register + 0x30C + 32 + read-write + + + ETRFLT + desc ETRFLT + 6 + 4 + read-write + + + + + CR0 + Control register0 + 0x310 + 32 + read-write + + + ENCRELOAD + desc ENCRELOAD + 20 + 19 + read-write + + + ENCRESET + desc ENCRESET + 18 + 17 + read-write + + + ENCMODE + desc ENCMODE + 16 + 15 + read-write + + + PRSSTATUS + desc PRSSTATUS + 14 + 11 + read-only + + + PRS + desc PRS + 10 + 7 + read-write + + + TOGEN + desc TOGEN + 6 + 6 + read-write + + + ONESHOT + desc ONESHOT + 5 + 5 + read-write + + + POL + desc POL + 4 + 4 + read-write + + + TRS + desc TRS + 3 + 3 + read-write + + + MODE + desc MODE + 2 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + IER + Interrupt enable register + 0x314 + 32 + read-write + + + DIRCHANGE + desc DIRCHANGE + 9 + 9 + read-write + + + CC4 + desc CC4 + 6 + 6 + read-write + + + CC3 + desc CC3 + 5 + 5 + read-write + + + CC2 + desc CC2 + 4 + 4 + read-write + + + CC1 + desc CC1 + 3 + 3 + read-write + + + UD + desc UD + 2 + 2 + read-write + + + TI + desc TI + 1 + 1 + read-write + + + OV + desc OV + 0 + 0 + read-write + + + + + ISR + Interrupt status register + 0x318 + 32 + read-write + + + DIR + desc DIR + 10 + 10 + read-only + + + DIRCHANGE + desc DIRCHANGE + 9 + 9 + read-only + + + CC4 + desc CC4 + 6 + 6 + read-only + + + CC3 + desc CC3 + 5 + 5 + read-only + + + CC2 + desc CC2 + 4 + 4 + read-only + + + CC1 + desc CC1 + 3 + 3 + read-only + + + UD + desc UD + 2 + 2 + read-only + + + TI + desc TI + 1 + 1 + read-only + + + OV + desc OV + 0 + 0 + read-only + + + + + ICR + Interrupt flag clear register + 0x31C + 32 + read-write + + + DIRCHANGE + desc DIRCHANGE + 9 + 9 + read-write + + + CC4 + desc CC4 + 6 + 6 + read-write + + + CC3 + desc CC3 + 5 + 5 + read-write + + + CC2 + desc CC2 + 4 + 4 + read-write + + + CC1 + desc CC1 + 3 + 3 + read-write + + + UD + desc UD + 2 + 2 + read-write + + + TI + desc TI + 1 + 1 + read-write + + + OV + desc OV + 0 + 0 + read-write + + + + + CCR1 + capture compare register + 0x320 + 32 + read-write + + + CCR + desc CCR + 15 + 0 + read-write + + + + + CCR2 + capture compare register + 0x324 + 32 + read-write + + + CCR + desc CCR + 15 + 0 + read-write + + + + + CCR3 + capture compare register + 0x328 + 32 + read-write + + + CCR + desc CCR + 15 + 0 + read-write + + + + + CCR4 + capture compare register + 0x32C + 32 + read-write + + + CCR + desc CCR + 15 + 0 + read-write + + + + + CR1 + Control register1 + 0x330 + 32 + read-write + + + CH4POL + desc CH4POL + 15 + 15 + read-write + + + CH4FLT + desc CH4FLT + 14 + 12 + read-write + + + CH3POL + desc CH3POL + 11 + 11 + read-write + + + CH3FLT + desc CH3FLT + 10 + 8 + read-write + + + CH2POL + desc CH2POL + 7 + 7 + read-write + + + CH2FLT + desc CH2FLT + 6 + 4 + read-write + + + CH1POL + desc CH1POL + 3 + 3 + read-write + + + CH1FLT + desc CH1FLT + 2 + 0 + read-write + + + + + DMA + DMA Control register + 0x340 + 32 + read-write + + + CC4 + desc CC4 + 5 + 5 + read-write + + + CC3 + desc CC3 + 4 + 4 + read-write + + + CC2 + desc CC2 + 3 + 3 + read-write + + + CC1 + desc CC1 + 2 + 2 + read-write + + + TRS + desc TRS + 1 + 1 + read-write + + + OV + desc OV + 0 + 0 + read-write + + + + + + + GTIM2 + General Timer 2 + 0x40001000 + + GTIM2 + General Timer2 Interrupt + 17 + + + + GTIM3 + General Timer 3 + 0x40014000 + + GTIM3 + General Timer3 Interrupt + 18 + + + + GTIM4 + General Timer 4 + 0x40014400 + + GTIM4 + General Timer4 Interrupt + 19 + + + + I2C1 + desc I2C1 + 0x40005400 + + I2C1 + I2C1 Interrupt + 23 + + I2C + I2C + 32 + + 0x0 + 0x2C + registers + + + + BRREN + desc BRREN + 0x0 + 32 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + BRR + desc BRR + 0x4 + 32 + read-write + + + BRR + fSCL = fPCLK / 8 / (BRR+1) + 7 + 0 + read-write + + + + + CR + Control register + 0x8 + 32 + read-write + + + EN + desc EN + 6 + 6 + read-write + + + STA + desc STA + 5 + 5 + read-write + + + STO + desc STO + 4 + 4 + read-write + + + SI + desc SI + 3 + 3 + read-write + + + AA + desc AA + 2 + 2 + read-write + + + FLT + desc FLT + 0 + 0 + read-write + + + + + DR + Data register + 0xC + 32 + read-write + + + DR + desc DR + 7 + 0 + read-write + + + + + ADDR0 + Slave Addrress0 + 0x10 + 32 + read-write + + + ADDR0 + desc ADDR0 + 7 + 1 + read-write + + + GC + desc GC + 0 + 0 + read-write + + + + + STAT + Status register + 0x14 + 32 + read-only + + + STAT + desc STAT + 7 + 0 + read-only + + + + + ADDR1 + Slave Addrress1 + 0x20 + 32 + read-write + + + ADDR1 + desc ADDR1 + 7 + 1 + read-write + + + + + ADDR2 + Slave Addrress2 + 0x24 + 32 + read-write + + + ADDR2 + desc ADDR2 + 7 + 1 + read-write + + + + + MATCH + Slave Addrress match flag + 0x28 + 32 + read-only + + + ADDR2 + desc ADDR2 + 2 + 2 + read-only + + + ADDR1 + desc ADDR1 + 1 + 1 + read-only + + + ADDR0 + desc ADDR0 + 0 + 0 + read-only + + + + + + + I2C2 + desc I2C2 + 0x40005800 + + I2C2 + I2C2 Interrput + 24 + + + + IWDT + desc IWDT + 0x40003000 + + WDT + Watch Dog Timer Interrupt + 0 + + WDT + IWDT + 32 + + 0x0 + 0x28 + registers + + + + KR + Key register + 0x0 + 32 + write-only + + + KR + desc KR + 15 + 0 + write-only + + + + + CR + Control register + 0x4 + 32 + read-write + + + PAUSE + desc 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desc GPIOC + 6 + 6 + read-write + + + GPIOB + desc GPIOB + 5 + 5 + read-write + + + GPIOA + desc GPIOA + 4 + 4 + read-write + + + CRC + desc CRC + 2 + 2 + read-write + + + FLASH + desc FLASH + 1 + 1 + read-write + + + DMA + desc DMA + 0 + 0 + read-write + + + + + APBEN2 + APB Clock Control Reg2 + 0x34 + 32 + read-write + + + AWT + desc AWT + 13 + 13 + read-write + + + BTIM + desc BTIM + 12 + 12 + read-write + + + GTIM4 + desc GTIM4 + 11 + 11 + read-write + + + GTIM3 + desc GTIM3 + 10 + 10 + read-write + + + UART1 + desc UART1 + 9 + 9 + read-write + + + SPI1 + desc SPI1 + 8 + 8 + read-write + + + ATIM + desc ATIM + 7 + 7 + read-write + + + VC + desc VC + 4 + 4 + read-write + + + ADC + desc ADC + 2 + 2 + read-write + + + + + APBEN1 + APB Clock Control Reg1 + 0x38 + 32 + read-write + + + I2C2 + desc I2C2 + 12 + 12 + read-write + + + I2C1 + desc I2C1 + 11 + 11 + read-write + + + UART3 + desc UART3 + 8 + 8 + read-write + + + UART2 + desc UART2 + 7 + 7 + read-write + + + SPI2 + desc SPI2 + 6 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+ + + GTIM1CAP + GTIM1 CAP Control Reg + 0x50 + 32 + read-write + + + CH4 + desc CH4 + 14 + 12 + read-write + + + CH3 + desc CH3 + 10 + 8 + read-write + + + CH2 + desc CH2 + 6 + 4 + read-write + + + CH1 + desc CH1 + 2 + 0 + read-write + + + + + GTIM2CAP + GTIM2 CAP Control Reg + 0x54 + 32 + read-write + + + CH4 + desc CH4 + 14 + 12 + read-write + + + CH3 + desc CH3 + 10 + 8 + read-write + + + CH2 + desc CH2 + 6 + 4 + read-write + + + CH1 + desc CH1 + 2 + 0 + read-write + + + + + GTIM3CAP + GTIM3 CAP Control Reg + 0x58 + 32 + read-write + + + CH4 + desc CH4 + 14 + 12 + read-write + + + CH3 + desc CH3 + 10 + 8 + read-write + + + CH2 + desc CH2 + 6 + 4 + read-write + + + CH1 + desc CH1 + 2 + 0 + read-write + + + + + GTIM4CAP + GTIM4 CAP Control Reg + 0x5C + 32 + read-write + + + CH4 + desc CH4 + 14 + 12 + read-write + + + CH3 + desc CH3 + 10 + 8 + read-write + + + CH2 + desc CH2 + 6 + 4 + read-write + + + CH1 + desc CH1 + 2 + 0 + read-write + + + + + ATIMETR + ATIM ETR Control Reg + 0x60 + 32 + read-write + + + ATIMETR + desc ATIMETR + 2 + 0 + read-write + + + + + GTIMETR + GTIM1-4 ETR Control Reg + 0x64 + 32 + read-write + + + GTIM4ETR + desc GTIM4ETR + 14 + 12 + read-write + + + GTIM3ETR + desc GTIM3ETR + 10 + 8 + read-write + + + GTIM2ETR + desc GTIM2ETR + 6 + 4 + read-write + + + GTIM1ETR + desc GTIM1ETR + 2 + 0 + read-write + + + + + TIMITR + BTIMx GTIMx ATIM ITR Control Reg + 0x6C + 32 + read-write + + + BTIM3ITR + desc BTIM3ITR + 23 + 21 + read-write + + + BTIM2ITR + desc BTIM2ITR + 20 + 18 + read-write + + + BTIM1ITR + desc BTIM1ITR + 17 + 15 + read-write + + + GTIM4ITR + desc GTIM4ITR + 14 + 12 + read-write + + + GTIM3ITR + desc GTIM3ITR + 11 + 9 + read-write + + + GTIM2ITR + desc GTIM2ITR + 8 + 6 + read-write + + + GTIM1ITR + desc GTIM1ITR + 5 + 3 + read-write + + + ATIMITR + desc ATIMITR + 2 + 0 + read-write + + + + + MCO + Master Clock Output Control Reg + 0x70 + 32 + read-write + + + DIV + desc DIV + 6 + 4 + read-write + + + SOURCE + desc SOURCE + 3 + 0 + read-write + + + + + IRMOD + IR MOD Control Reg + 0x74 + 32 + read-write + + + MOD + desc MOD + 3 + 0 + read-write + + + + + + + UART1 + desc UART1 + 0x40013800 + + UART1 + UART1 Interrupt + 27 + + UART + UART + 32 + + 0x0 + 0x38 + registers + + + + CR1 + Control register1 + 0x0 + 32 + read-write + + + OVER + desc OVER + 10 + 9 + read-write + + + START + desc START + 8 + 8 + read-write + + + SYNC + desc SYNC + 6 + 6 + read-write + + + STOP + desc STOP + 5 + 4 + read-write + + + PARITY + desc PARITY + 3 + 2 + read-write + + + RXEN + desc RXEN + 1 + 1 + read-write + + + TXEN + desc TXEN + 0 + 0 + read-write + + + + + CR2 + Control register2 + 0x4 + 32 + read-write + + + SOURCE + desc SOURCE + 9 + 8 + read-write + + + DMATX + desc DMATX + 7 + 7 + read-write + + + DMARX + desc DMARX + 6 + 6 + read-write + + + TXINV + desc TXINV + 5 + 5 + read-write + + + RXINV + desc RXINV + 4 + 4 + read-write + + + RTSEN + desc RTSEN + 3 + 3 + read-write + + + CTSEN + desc CTSEN + 2 + 2 + read-write + + + SIGNAL + desc SIGNAL + 1 + 1 + read-write + + + ADDREN + desc ADDREN + 0 + 0 + read-write + + + + + IER + Interrupt enable register + 0x8 + 32 + read-write + + + CTS + CTS change + 6 + 6 + read-write + + + PE + Parity error + 4 + 4 + read-write + + + FE + Frame error + 3 + 3 + read-write + + + RC + Receive complete + 2 + 2 + read-write + + + TC + Transmit complete + 1 + 1 + read-write + + + TXE + TxBuf empty + 0 + 0 + read-write + + + + + BRRI + desc BRRI + 0xC + 32 + read-write + + + BRRI + desc BRRI + 15 + 0 + read-write + + + + + BRRF + desc BRRF + 0x10 + 32 + read-write + + + BRRF + desc BRRF + 3 + 0 + read-write + + + + + ISR + Interrupt status register + 0x1C + 32 + read-only + + + TXBUSY + desc TXBUSY + 8 + 8 + read-only + + + CTSLV + CTS PIN level + 7 + 7 + read-only + + + CTS + CTS change + 6 + 6 + read-only + + + MATCH + Slave addr match + 5 + 5 + read-only + + + PE + Parity error + 4 + 4 + read-only + + + FE + Frame error + 3 + 3 + read-only + + + RC + Receive complete + 2 + 2 + read-only + + + TC + Transmit complete + 1 + 1 + read-only + + + TXE + TxBuf empty + 0 + 0 + read-only + + + + + ICR + Interrupt flag clear register + 0x20 + 32 + read-write + + + CTS + CTS change + 6 + 6 + read-write + + + PE + Parity error + 4 + 4 + read-write + + + FE + Frame error + 3 + 3 + read-write + + + RC + Receive complete + 2 + 2 + read-write + + + TC + Transmit complete + 1 + 1 + read-write + + + + + RDR + Data reg for read + 0x24 + 32 + read-only + + + RDR + desc RDR + 8 + 0 + read-only + + + + + TDR + Data reg for write + 0x28 + 32 + write-only + + + TDR + desc TDR + 8 + 0 + write-only + + + + + ADDR + Slave addr + 0x30 + 32 + read-write + + + ADDR + desc ADDR + 7 + 0 + read-write + + + + + MASK + Slave addr mask + 0x34 + 32 + read-write + + + MASK + desc MASK + 7 + 0 + read-write + + + + + + + UART2 + desc UART2 + 0x40004400 + + UART2 + UART2 Interrupt + 28 + + + + UART3 + desc UART3 + 0x40004800 + + UART3 + UART3 Interrupt + 29 + + + + VC1 + desc VC1 + 0x40012A00 + + VC1 + Voltage Comparator 1 Interrupt + 14 + + VC + VC + 32 + + 0x0 + 0x10 + registers + + + + DIV + desc DIV + 0x0 + 32 + read-write + + + VIN + desc VIN + 7 + 7 + read-write + + + EN + desc EN + 6 + 6 + read-write + + + DIV + desc DIV + 5 + 0 + read-write + + + + + CR0 + Control register0 + 0x4 + 32 + read-write + + + INN + desc INN + 15 + 12 + read-write + + + INP + desc INP + 11 + 8 + read-write + + + WINDOW + desc WINDOW + 7 + 7 + read-write + + + POL + desc POL + 6 + 6 + read-write + + + IE + desc IE + 5 + 5 + read-write + + + HYS + desc HYS + 4 + 3 + read-write + + + RESP + desc RESP + 2 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + CR1 + Control register1 + 0x8 + 32 + read-write + + + BLANKFLT + desc BLANKFLT + 15 + 13 + read-write + + + BLANKCH3B + desc BLANKCH3B + 12 + 12 + read-write + + + BLANKCH2B + desc BLANKCH2B + 11 + 11 + read-write + + + BLANKCH1B + desc BLANKCH1B + 10 + 10 + read-write + + + ATIMBK + desc ATIMBK + 9 + 9 + read-write + + + ATIMCLR + desc ATIMCLR + 8 + 8 + read-write + + + HIGHIE + desc HIGHIE + 7 + 7 + read-write + + + RISEIE + desc RISEIE + 6 + 6 + read-write + + + FALLIE + desc FALLIE + 5 + 5 + read-write + + + FLTCLK + desc FLTCLK + 4 + 4 + read-write + + + FLTTIME + desc FLTTIME + 3 + 1 + read-write + + + FLTEN + desc FLTEN + 0 + 0 + read-write + + + + + SR + Status register + 0xC + 32 + read-write + + + READY + desc READY + 2 + 2 + read-only + + + FLTV + desc FLTV + 1 + 1 + read-only + + + INTF + desc INTF + 0 + 0 + read-write + + + + + + + VC2 + desc VC2 + 0x40012A10 + + VC2 + Voltage Comparator 2 Interrupt + 15 + + + + WWDT + desc WWDT + 0x40002C00 + + WDT + Watch Dog Timer Interrupt + 0 + + WDT + WWDT + 32 + + 0x0 + 0xC + registers + + + + CR0 + Control register1 + 0x0 + 32 + read-write + + + EN + desc EN + 7 + 7 + read-write + + + WCNT + desc WCNT + 6 + 0 + read-write + + + + + CR1 + Control register2 + 0x4 + 32 + read-write + + + IE + desc IE + 10 + 10 + read-write + + + PRS + desc PRS + 9 + 7 + read-write + + + WINR + desc WINR + 6 + 0 + read-write + + + + + SR + Status register + 0x8 + 32 + read-write + + + POV + desc POV + 0 + 0 + read-write + + + + + + + \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashCW32F030_RAM4K.out b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashCW32F030_RAM4K.out new file mode 100644 index 0000000..aed8e06 Binary files /dev/null and b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashCW32F030_RAM4K.out differ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashCW32F030_RAM6K.out b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashCW32F030_RAM6K.out new file mode 100644 index 0000000..e0a4ab8 Binary files /dev/null and b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashCW32F030_RAM6K.out differ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashCW32F030_RAM8K.out b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashCW32F030_RAM8K.out new file mode 100644 index 0000000..c506cb4 Binary files /dev/null and b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashCW32F030_RAM8K.out differ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashLoader_CW030.mac b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashLoader_CW030.mac new file mode 100644 index 0000000..b321dac --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashLoader_CW030.mac @@ -0,0 +1,23 @@ +setup() +{ + __message "----- setup hardware for Flashloader -----\n"; + /*Wait*/ + __delay(5); + __emulatorSpeed(0); + + /*Vectors at RAM*/ + __writeMemory32(0x20000000, 0xE000ED08, "Memory"); +} + +execUserPreload() +{ + __message "----- execUserPreload -----\n"; + setup(); +} + +execUserFlashInit() // Called by debugger before loading flash loader in RAM. +{ + __message "----- execUserFlashInit -----\n"; + setup(); +} + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashLoader_CW32F030x6.board b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashLoader_CW32F030x6.board new file mode 100644 index 0000000..5da1a8b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashLoader_CW32F030x6.board @@ -0,0 +1,7 @@ + + + + $TOOLKIT_DIR$\config\flashloader\CW\FlashLoader_CW32F030x6.flash + CODE 0x0 0x7fff + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashLoader_CW32F030x6.flash b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashLoader_CW32F030x6.flash new file mode 100644 index 0000000..ca0fd4f --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashLoader_CW32F030x6.flash @@ -0,0 +1,10 @@ + + + + $TOOLKIT_DIR$\config\flashloader\CW\FlashCW32F030_RAM6K.out + 1 + 64 0x200 + 0x00000000 + $TOOLKIT_DIR$\config\flashloader\CW\FlashLoader_CW030.mac + 0 + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashLoader_CW32F030x8.board b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashLoader_CW32F030x8.board new file mode 100644 index 0000000..fa56c49 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashLoader_CW32F030x8.board @@ -0,0 +1,7 @@ + + + + $TOOLKIT_DIR$\config\flashloader\CW\FlashLoader_CW32F030x8.flash + CODE 0x0 0xffff + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashLoader_CW32F030x8.flash b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashLoader_CW32F030x8.flash new file mode 100644 index 0000000..1062628 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/flashloader/CW/FlashLoader_CW32F030x8.flash @@ -0,0 +1,10 @@ + + + + $TOOLKIT_DIR$\config\flashloader\CW\FlashCW32F030_RAM8K.out + 1 + 128 0x200 + 0x00000000 + $TOOLKIT_DIR$\config\flashloader\CW\FlashLoader_CW030.mac + 0 + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/linker/CW/CW32F030.icf b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/linker/CW/CW32F030.icf new file mode 100644 index 0000000..0acdb62 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/arm/config/linker/CW/CW32F030.icf @@ -0,0 +1,29 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/readme.txt new file mode 100644 index 0000000..626b5be --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/readme.txt @@ -0,0 +1,10 @@ +用于EWARM工具的单片机Flash烧写配置文件，请将该文件下的arm文件加拷贝到EWARM的安装目录下。 + +1. 拷贝arm文件到EWARM的安装路径： + 如EWARM安装路径为D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2 + 则将arm文件夹拷贝到D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\目录下，覆盖同名的arm文件夹。 + +2. 使用： + 1) EWARM界面->"Project"->"Options..."->"Linker"->"Config"->在显示的标签栏中选择“Override default"，点击"..."在弹出的对话框中选择"CW32F030.icf"->点击"打开" + 2)EWARM界面->"Project"->"Options..."->"Debugger"->"Download"->在显示的标签栏中选择“Override default .board file"，点击"..."在弹出的对话框中选择"CW"文件夹下的"FlashLoader_CW030.board"->点击"打开" + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/startup_cw32f030.s b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/startup_cw32f030.s new file mode 100644 index 0000000..16b7d4b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/EWARM/startup_cw32f030.s @@ -0,0 +1,312 @@ + +;/*****************************************************************************/ +;/* Startup for IAR */ +;/* Version V1.0 */ +;/* Date 2021-02-24 */ +;/* Target-mcu M0+ Device */ +;/*****************************************************************************/ + + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + SECTION .intvec:CODE:ROOT(8) + DATA +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset + DCD NMI_Handler ; NMI + DCD HardFault_Handler ; Hard Fault + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV + DCD SysTick_Handler ; SysTick + +; Numbered IRQ handler vectors + +; Note: renaming to device dependent ISR function names are done in + + DCD WDT_IRQHandler + DCD LVD_IRQHandler + DCD RTC_IRQHandler + DCD FLASHRAM_IRQHandler + DCD RCC_IRQHandler + DCD GPIOA_IRQHandler + DCD GPIOB_IRQHandler + DCD GPIOC_IRQHandler + DCD GPIOF_IRQHandler + DCD DMACH1_IRQHandler + DCD DMACH23_IRQHandler + DCD DMACH45_IRQHandler + DCD ADC_IRQHandler + DCD ATIM_IRQHandler + DCD VC1_IRQHandler + DCD VC2_IRQHandler + DCD GTIM1_IRQHandler + DCD GTIM2_IRQHandler + DCD GTIM3_IRQHandler + DCD GTIM4_IRQHandler + DCD BTIM1_IRQHandler + DCD BTIM2_IRQHandler + DCD BTIM3_IRQHandler + DCD I2C1_IRQHandler + DCD I2C2_IRQHandler + DCD SPI1_IRQHandler + DCD SPI2_IRQHandler + DCD UART1_IRQHandler + DCD UART2_IRQHandler + DCD UART3_IRQHandler + DCD AWT_IRQHandler + DCD FAULT_IRQHandler + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R1, =0x0 + LDR R0, [R1] + MOV SP, R0 + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WDT_IRQHandler + B WDT_IRQHandler + + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK FLASHRAM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASHRAM_IRQHandler + B FLASHRAM_IRQHandler + + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + + PUBWEAK GPIOA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOA_IRQHandler + B GPIOA_IRQHandler + + + PUBWEAK GPIOB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOB_IRQHandler + B GPIOB_IRQHandler + + + PUBWEAK GPIOC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOC_IRQHandler + B GPIOC_IRQHandler + + + PUBWEAK GPIOF_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOF_IRQHandler + B GPIOF_IRQHandler + + + PUBWEAK DMACH1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMACH1_IRQHandler + B DMACH1_IRQHandler + + + PUBWEAK DMACH23_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMACH23_IRQHandler + B DMACH23_IRQHandler + + + PUBWEAK DMACH45_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMACH45_IRQHandler + B DMACH45_IRQHandler + + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + + PUBWEAK ATIM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ATIM_IRQHandler + B ATIM_IRQHandler + + + PUBWEAK VC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +VC1_IRQHandler + B VC1_IRQHandler + + + PUBWEAK VC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +VC2_IRQHandler + B VC2_IRQHandler + + + PUBWEAK GTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GTIM1_IRQHandler + B GTIM1_IRQHandler + + + PUBWEAK GTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GTIM2_IRQHandler + B GTIM2_IRQHandler + + + PUBWEAK GTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GTIM3_IRQHandler + B GTIM3_IRQHandler + + + PUBWEAK GTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GTIM4_IRQHandler + B GTIM4_IRQHandler + + + PUBWEAK BTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BTIM1_IRQHandler + B BTIM1_IRQHandler + + + PUBWEAK BTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BTIM2_IRQHandler + B BTIM2_IRQHandler + + + PUBWEAK BTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BTIM3_IRQHandler + B BTIM3_IRQHandler + + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK AWT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +AWT_IRQHandler + B AWT_IRQHandler + + + PUBWEAK FAULT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FAULT_IRQHandler + B FAULT_IRQHandler + + + + + + END diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/MDK/WHXY.CW32F030_DFP.1.0.5.pack b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/MDK/WHXY.CW32F030_DFP.1.0.5.pack new file mode 100644 index 0000000..c093c5d Binary files /dev/null and b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/MDK/WHXY.CW32F030_DFP.1.0.5.pack differ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/MDK/startup_cw32f030.s b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/MDK/startup_cw32f030.s new file mode 100644 index 0000000..dbd70ea --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/IdeSupport/MDK/startup_cw32f030.s @@ -0,0 +1,246 @@ + +;/*****************************************************************************/ +;/* Startup for ARM */ +;/* Version V1.0 */ +;/* Date 2021-03-12 */ +;/* Target-mcu {MCU_PN_H} */ +;/*****************************************************************************/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors + DCD __initial_sp ; Top of Stack + DCD Reset_Handler ;< -15 Reset Vector, invoked on Power up and warm reset + DCD NMI_Handler ;< -14 Non maskable Interrupt, cannot be stopped or preempted + DCD HardFault_Handler ;< -13 Hard Fault, all classes of Fault + DCD 0 ;< -12 Reserved + DCD 0 ;< -11 Reserved + DCD 0 ;< -10 Reserved + DCD 0 ;< -9 Reserved + DCD 0 ;< -8 Reserved + DCD 0 ;< -7 Reserved + DCD 0 ;< -6 Reserved + DCD SVC_Handler ;< -5 System Service Call via SVC instruction + DCD 0 ;< -4 Reserved + DCD 0 ;< -3 Reserved + DCD PendSV_Handler ;< -2 Pendable request for system service + DCD SysTick_Handler ;< -1 System Tick Timer + + DCD WDT_IRQHandler ;< 0 Watch Dog Timer Interrupt Handler + DCD LVD_IRQHandler ;< 1 Low Voltage Detect Interrupt Handler + DCD RTC_IRQHandler ;< 2 Real Time Clock Interrupt Handler + DCD FLASHRAM_IRQHandler ;< 3 Flash/RAM Interrupt Handler + DCD RCC_IRQHandler ;< 4 RCC Interupt Handler + DCD GPIOA_IRQHandler ;< 5 GPIOA Interrupt Handler + DCD GPIOB_IRQHandler ;< 6 GPIOB Interrupt Handler + DCD GPIOC_IRQHandler ;< 7 GPIOC Interrupt Handler + DCD GPIOF_IRQHandler ;< 8 GPIOF Interrupt Handler + DCD DMACH1_IRQHandler ;< 9 DMA Channel 1 Interrupt Handler + DCD DMACH23_IRQHandler ;< 10 DMA Channel 2/3 Interrupt Handler + DCD DMACH45_IRQHandler ;< 11 DMA Channel 4/5 Interrupt Handler + DCD ADC_IRQHandler ;< 12 ADC Interrupt Handler + DCD ATIM_IRQHandler ;< 13 Advanced Timer Interrupt Handler + DCD VC1_IRQHandler ;< 14 Voltage Comparator 1 Interrupt Handler + DCD VC2_IRQHandler ;< 15 Voltage Comparator 2 Interrupt Handler + DCD GTIM1_IRQHandler ;< 16 General Timer1 Interrupt Handler + DCD GTIM2_IRQHandler ;< 17 General Timer2 Interrupt Handler + DCD GTIM3_IRQHandler ;< 18 General Timer3 Interrupt Handler + DCD GTIM4_IRQHandler ;< 19 General Timer4 Interrupt Handler + DCD BTIM1_IRQHandler ;< 20 Base Timer1 Interrupt Handler + DCD BTIM2_IRQHandler ;< 21 Base Timer2 Interrupt Handler + DCD BTIM3_IRQHandler ;< 22 Base Timer3 Interrupt Handler + DCD I2C1_IRQHandler ;< 23 I2C1 Interrupt Handler + DCD I2C2_IRQHandler ;< 24 I2C2 Interrupt Handler + DCD SPI1_IRQHandler ;< 25 SPI1 Interrupt Handler + DCD SPI2_IRQHandler ;< 26 SPI2 Interrupt Handler + DCD UART1_IRQHandler ;< 27 UART1 Interrupt Handler + DCD UART2_IRQHandler ;< 28 UART2 Interrupt Handler + DCD UART3_IRQHandler ;< 29 UART3 Interrupt Handler + DCD AWT_IRQHandler ;< 30 Auto Wakeup Timer Handler + DCD FAULT_IRQHandler ;< 31 FAULT Interrupt Handler + + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R1, =0x0 + LDR R0, [R1] + MOV SP, R0 + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + + +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT WDT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASHRAM_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT GPIOA_IRQHandler [WEAK] + EXPORT GPIOB_IRQHandler [WEAK] + EXPORT GPIOC_IRQHandler [WEAK] + EXPORT GPIOF_IRQHandler [WEAK] + EXPORT DMACH1_IRQHandler [WEAK] + EXPORT DMACH23_IRQHandler [WEAK] + EXPORT DMACH45_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT ATIM_IRQHandler [WEAK] + EXPORT VC1_IRQHandler [WEAK] + EXPORT VC2_IRQHandler [WEAK] + EXPORT GTIM1_IRQHandler [WEAK] + EXPORT GTIM2_IRQHandler [WEAK] + EXPORT GTIM3_IRQHandler [WEAK] + EXPORT GTIM4_IRQHandler [WEAK] + EXPORT BTIM1_IRQHandler [WEAK] + EXPORT BTIM2_IRQHandler [WEAK] + EXPORT BTIM3_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT AWT_IRQHandler [WEAK] + EXPORT FAULT_IRQHandler [WEAK] + +WDT_IRQHandler +LVD_IRQHandler +RTC_IRQHandler +FLASHRAM_IRQHandler +RCC_IRQHandler +GPIOA_IRQHandler +GPIOB_IRQHandler +GPIOC_IRQHandler +GPIOF_IRQHandler +DMACH1_IRQHandler +DMACH23_IRQHandler +DMACH45_IRQHandler +ADC_IRQHandler +ATIM_IRQHandler +VC1_IRQHandler +VC2_IRQHandler +GTIM1_IRQHandler +GTIM2_IRQHandler +GTIM3_IRQHandler +GTIM4_IRQHandler +BTIM1_IRQHandler +BTIM2_IRQHandler +BTIM3_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +AWT_IRQHandler +FAULT_IRQHandler + + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/base_types.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/base_types.h new file mode 100644 index 0000000..5b17e12 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/base_types.h @@ -0,0 +1,145 @@ + +#ifndef __BASE_TYPES_H +#define __BASE_TYPES_H + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include +#include +#include + + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +#ifndef TRUE + /** Value is true (boolean_t type) */ + #define TRUE ((boolean_t) 1u) +#endif + +#ifndef FALSE + /** Value is false (boolean_t type) */ + #define FALSE ((boolean_t) 0u) +#endif + +/** Returns the minimum value out of two values */ +#define MINIMUM(X, Y) ((X) < (Y) ? (X) : (Y)) + +/** Returns the maximum value out of two values */ +#define MAXIMUM(X, Y) ((X) > (Y) ? (X) : (Y)) + +/** Returns the dimension of an array */ +#define ARRAY_SZ(X) (sizeof(X) / sizeof((X)[0])) + +#ifdef __DEBUG_ASSERT + #define ASSERT(x) do{ assert((x)> 0u) ; }while(0); +#else + #define ASSERT(x) {} +#endif +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** logical datatype (only values are TRUE and FALSE) */ +typedef uint8_t boolean_t; + +/** single precision floating point number (4 byte) */ +typedef float float32_t; + +/** double precision floating point number (8 byte) */ +typedef double float64_t; + +/** ASCII character for string generation (8 bit) */ +typedef char char_t; + +/** function pointer type to void/void function */ +typedef void (*func_ptr_t)(void); + +/** function pointer type to void/uint8_t function */ +typedef void (*func_ptr_arg1_t)(uint8_t u8Param); + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + + + +#define bv(n) ((uint32_t)1u << (n)) + +#define bv0 (((uint32_t)1u) << 0) +#define bv1 (((uint32_t)1u) << 1) +#define bv2 (((uint32_t)1u) << 2) +#define bv3 (((uint32_t)1u) << 3) +#define bv4 (((uint32_t)1u) << 4) +#define bv5 (((uint32_t)1u) << 5) +#define bv6 (((uint32_t)1u) << 6) +#define bv7 (((uint32_t)1u) << 7) +#define bv8 (((uint32_t)1u) << 8) +#define bv9 (((uint32_t)1u) << 9) +#define bv10 (((uint32_t)1u) << 10) +#define bv11 (((uint32_t)1u) << 11) +#define bv12 (((uint32_t)1u) << 12) +#define bv13 (((uint32_t)1u) << 13) +#define bv14 (((uint32_t)1u) << 14) +#define bv15 (((uint32_t)1u) << 15) +#define bv16 (((uint32_t)1u) << 16) +#define bv17 (((uint32_t)1u) << 17) +#define bv18 (((uint32_t)1u) << 18) +#define bv19 (((uint32_t)1u) << 19) +#define bv20 (((uint32_t)1u) << 20) +#define bv21 (((uint32_t)1u) << 21) +#define bv22 (((uint32_t)1u) << 22) +#define bv23 (((uint32_t)1u) << 23) +#define bv24 (((uint32_t)1u) << 24) +#define bv25 (((uint32_t)1u) << 25) +#define bv26 (((uint32_t)1u) << 26) +#define bv27 (((uint32_t)1u) << 27) +#define bv28 (((uint32_t)1u) << 28) +#define bv29 (((uint32_t)1u) << 29) +#define bv30 (((uint32_t)1u) << 30) +#define bv31 (((uint32_t)1u) << 31) + +#define REGBITS_SET(Reg, Mask) ((Reg) |= (Mask)) +#define REGBITS_CLR(Reg, Mask) ((Reg) &= (~((uint32_t)(Mask)))) +#define REGBITS_GET(Reg, Mask) ((Reg) & (Mask) ) +#define REGBITS_MODIFY(Reg, Mask, Value) ((Reg) = ((Reg) & (~(uint32_t)(Mask))) | (Value)) + +/* Exported macro ------------------------------------------------------------*/ +#define USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT + /** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) + /* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +#endif /* __BASE_TYPES_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030.h new file mode 100644 index 0000000..a3ffba5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030.h @@ -0,0 +1,7870 @@ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * @file cw32f030.h + * @brief CMSIS HeaderFile + * @version 1.2 + * @date 22. July 2021 + * @note Generated by SVDConv V3.3.25 on Thursday, 22.07.2021 14:07:41 + * from File 'cw32f030.svd', + * last modified on Thursday, 22.07.2021 06:07:37 + */ + + + +/** @addtogroup CW Co.Ltd + * @{ + */ + + +/** @addtogroup cw32f030 + * @{ + */ + + +#ifndef CW32F030_H +#define CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ + /* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* ========================================== cw32f030 Specific Interrupt Numbers ========================================== */ + WDT_IRQn = 0, /*!< 0 Watch Dog Timer Interrupt */ + LVD_IRQn = 1, /*!< 1 Low Voltage Detect Interrupt */ + RTC_IRQn = 2, /*!< 2 Real Time Clock Interrupt */ + FLASHRAM_IRQn = 3, /*!< 3 Flash/RAM Interrupt */ + RCC_IRQn = 4, /*!< 4 RCC Interupt */ + GPIOA_IRQn = 5, /*!< 5 GPIOA Interrupt */ + GPIOB_IRQn = 6, /*!< 6 GPIOB Interrupt */ + GPIOC_IRQn = 7, /*!< 7 GPIOC Interrupt */ + GPIOF_IRQn = 8, /*!< 8 GPIOF Interrupt */ + DMACH1_IRQn = 9, /*!< 9 DMA Channel 1 Interrupt */ + DMACH23_IRQn = 10, /*!< 10 DMA Channel 2/3 Interrupt */ + DMACH45_IRQn = 11, /*!< 11 DMA Channel 2/3 Interrupt */ + ADC_IRQn = 12, /*!< 12 ADC Interrupt */ + ATIM_IRQn = 13, /*!< 13 Advanced Timer Interrupt */ + VC1_IRQn = 14, /*!< 14 Voltage Comparator 1 Interrupt */ + VC2_IRQn = 15, /*!< 15 Voltage Comparator 2 Interrupt */ + GTIM1_IRQn = 16, /*!< 16 General Timer1 Interrupt */ + GTIM2_IRQn = 17, /*!< 17 General Timer2 Interrupt */ + GTIM3_IRQn = 18, /*!< 18 General Timer3 Interrupt */ + GTIM4_IRQn = 19, /*!< 19 General Timer4 Interrupt */ + BTIM1_IRQn = 20, /*!< 20 Base Timer1 Interrupt */ + BTIM2_IRQn = 21, /*!< 21 Base Timer2 Interrupt */ + BTIM3_IRQn = 22, /*!< 22 Base Timer3 Interrupt */ + I2C1_IRQn = 23, /*!< 23 I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< 24 I2C2 Interrput */ + SPI1_IRQn = 25, /*!< 25 SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< 26 SPI2 Interrupt */ + UART1_IRQn = 27, /*!< 27 UART1 Interrupt */ + UART2_IRQn = 28, /*!< 28 UART2 Interrupt */ + UART3_IRQn = 29, /*!< 29 UART3 Interrupt */ + AWT_IRQn = 30, /*!< 30 Auto Wakeup Timer Interrupt */ + FAULT_IRQn = 31 /*!< 31 FAULT Interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 0 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ +#include "system_cw32f030.h" /*!< cw32f030 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ +#define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ +#define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ +#define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined (__ICCARM__) +#pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#pragma clang diagnostic ignored "-Wgnu-anonymous-struct" +#pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined (__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning 586 +#elif defined (__CSMC__) +/* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc ADC (ADC) + */ + +typedef struct /*!< (@ 0x40012400) ADC Structure */ +{ + + union + { + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control register0 */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t MODE : 3; /*!< [3..1] desc MODE */ + __IOM uint32_t BGREN : 1; /*!< [4..4] desc BGREN */ + __IOM uint32_t TSEN : 1; /*!< [5..5] desc TSEN */ + __IOM uint32_t REF : 2; /*!< [7..6] desc REF */ + __IOM uint32_t CLK : 3; /*!< [10..8] desc CLK */ + __IOM uint32_t SAM : 2; /*!< [12..11] desc SAM */ + __IOM uint32_t BUF : 1; /*!< [13..13] desc BUF */ + __IOM uint32_t BIAS : 2; /*!< [15..14] desc BIAS */ + } CR0_f; + } ; + + union + { + __IOM uint32_t CR1; /*!< (@ 0x00000004) Control register1 */ + + struct + { + __IOM uint32_t CHMUX : 4; /*!< [3..0] desc CHMUX */ + __IM uint32_t : 1; + __IOM uint32_t DISCARD : 1; /*!< [5..5] desc DISCARD */ + __IOM uint32_t ALIGN : 1; /*!< [6..6] desc ALIGN */ + __IOM uint32_t DMAEN : 1; /*!< [7..7] desc DMAEN */ + __IOM uint32_t WDTCH : 4; /*!< [11..8] desc WDTCH */ + __IM uint32_t : 1; + __IOM uint32_t WDTALL : 1; /*!< [13..13] desc WDTALL */ + } CR1_f; + } ; + + union + { + __IOM uint32_t START; /*!< (@ 0x00000008) desc START */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] desc START */ + __IOM uint32_t AUTOSTOP : 1; /*!< [1..1] desc AUTOSTOP */ + } START_f; + } ; + + union + { + __IOM uint32_t SQR; /*!< (@ 0x0000000C) desc SQR */ + + struct + { + __IOM uint32_t SQR0 : 4; /*!< [3..0] desc SQR0 */ + __IOM uint32_t SQR1 : 4; /*!< [7..4] desc SQR1 */ + __IOM uint32_t SQR2 : 4; /*!< [11..8] desc SQR2 */ + __IOM uint32_t SQR3 : 4; /*!< [15..12] desc SQR3 */ + __IOM uint32_t ENS : 2; /*!< [17..16] desc ENS */ + } SQR_f; + } ; + + union + { + __IOM uint32_t CR2; /*!< (@ 0x00000010) Control register2 */ + + struct + { + __IOM uint32_t CNT : 8; /*!< [7..0] desc CNT */ + __IOM uint32_t ACCEN : 1; /*!< [8..8] desc ACCEN */ + __IOM uint32_t ACCRST : 1; /*!< [9..9] desc ACCRST */ + } CR2_f; + } ; + + union + { + __IOM uint32_t VTH; /*!< (@ 0x00000014) desc VTH */ + + struct + { + __IOM uint32_t VTH : 12; /*!< [11..0] desc VTH */ + } VTH_f; + } ; + + union + { + __IOM uint32_t VTL; /*!< (@ 0x00000018) desc VTL */ + + struct + { + __IOM uint32_t VTL : 12; /*!< [11..0] desc VTL */ + } VTL_f; + } ; + + union + { + __IOM uint32_t TRIGGER; /*!< (@ 0x0000001C) desc TRIGGER */ + + struct + { + __IOM uint32_t ATIM : 1; /*!< [0..0] desc ATIM */ + __IOM uint32_t GTIM1 : 1; /*!< [1..1] desc GTIM1 */ + __IOM uint32_t GTIM2 : 1; /*!< [2..2] desc GTIM2 */ + __IOM uint32_t GTIM3 : 1; /*!< [3..3] desc GTIM3 */ + __IOM uint32_t GTIM4 : 1; /*!< [4..4] desc GTIM4 */ + __IOM uint32_t BTIM1 : 1; /*!< [5..5] desc BTIM1 */ + __IOM uint32_t BTIM2 : 1; /*!< [6..6] desc BTIM2 */ + __IOM uint32_t BTIM3 : 1; /*!< [7..7] desc BTIM3 */ + __IOM uint32_t UART1 : 1; /*!< [8..8] desc UART1 */ + __IOM uint32_t UART2 : 1; /*!< [9..9] desc UART2 */ + __IOM uint32_t UART3 : 1; /*!< [10..10] desc UART3 */ + __IOM uint32_t SPI1 : 1; /*!< [11..11] desc SPI1 */ + __IOM uint32_t SPI2 : 1; /*!< [12..12] desc SPI2 */ + __IOM uint32_t I2C1 : 1; /*!< [13..13] desc I2C1 */ + __IOM uint32_t I2C2 : 1; /*!< [14..14] desc I2C2 */ + __IOM uint32_t DMA : 1; /*!< [15..15] desc DMA */ + } TRIGGER_f; + } ; + + union + { + __IM uint32_t RESULT0; /*!< (@ 0x00000020) desc RESULT0 */ + + struct + { + __IM uint32_t RESULT : 16; /*!< [15..0] desc RESULT */ + } RESULT0_f; + } ; + + union + { + __IM uint32_t RESULT1; /*!< (@ 0x00000024) desc RESULT1 */ + + struct + { + __IM uint32_t RESULT : 16; /*!< [15..0] desc RESULT */ + } RESULT1_f; + } ; + + union + { + __IM uint32_t RESULT2; /*!< (@ 0x00000028) desc RESULT2 */ + + struct + { + __IM uint32_t RESULT : 16; /*!< [15..0] desc RESULT */ + } RESULT2_f; + } ; + + union + { + __IM uint32_t RESULT3; /*!< (@ 0x0000002C) desc RESULT3 */ + + struct + { + __IM uint32_t RESULT : 16; /*!< [15..0] desc RESULT */ + } RESULT3_f; + } ; + + union + { + __IM uint32_t RESULTACC; /*!< (@ 0x00000030) desc RESULTACC */ + + struct + { + __IM uint32_t RESULT : 24; /*!< [23..0] desc RESULT */ + } RESULTACC_f; + } ; + + union + { + __IOM uint32_t IER; /*!< (@ 0x00000034) Interrupt enable register */ + + struct + { + __IOM uint32_t EOC : 1; /*!< [0..0] desc EOC */ + __IOM uint32_t EOS : 1; /*!< [1..1] desc EOS */ + __IOM uint32_t EOA : 1; /*!< [2..2] desc EOA */ + __IOM uint32_t WDTL : 1; /*!< [3..3] desc WDTL */ + __IOM uint32_t WDTH : 1; /*!< [4..4] desc WDTH */ + __IOM uint32_t WDTR : 1; /*!< [5..5] desc WDTR */ + __IOM uint32_t OVW : 1; /*!< [6..6] desc OVW */ + } IER_f; + } ; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000038) Interrupt flag clear register */ + + struct + { + __IOM uint32_t EOC : 1; /*!< [0..0] desc EOC */ + __IOM uint32_t EOS : 1; /*!< [1..1] desc EOS */ + __IOM uint32_t EOA : 1; /*!< [2..2] desc EOA */ + __IOM uint32_t WDTL : 1; /*!< [3..3] desc WDTL */ + __IOM uint32_t WDTH : 1; /*!< [4..4] desc WDTH */ + __IOM uint32_t WDTR : 1; /*!< [5..5] desc WDTR */ + __IOM uint32_t OVW : 1; /*!< [6..6] desc OVW */ + } ICR_f; + } ; + + union + { + __IM uint32_t ISR; /*!< (@ 0x0000003C) Interrupt status register */ + + struct + { + __IM uint32_t EOC : 1; /*!< [0..0] desc EOC */ + __IM uint32_t EOS : 1; /*!< [1..1] desc EOS */ + __IM uint32_t EOA : 1; /*!< [2..2] desc EOA */ + __IM uint32_t WDTL : 1; /*!< [3..3] desc WDTL */ + __IM uint32_t WDTH : 1; /*!< [4..4] desc WDTH */ + __IM uint32_t WDTR : 1; /*!< [5..5] desc WDTR */ + __IM uint32_t OVW : 1; /*!< [6..6] desc OVW */ + __IM uint32_t READY : 1; /*!< [7..7] desc READY */ + } ISR_f; + } ; + +} ADC_TypeDef; /*!< Size = 140 (0x8c) */ + + + +/* =========================================================================================================================== */ +/* ================ ATIM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc ATIM (ATIM) + */ + +typedef struct /*!< (@ 0x40012C00) ATIM Structure */ +{ + + union + { + __IOM uint32_t ARR; /*!< (@ 0x00000000) desc ARR */ + + struct + { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } ARR_f; + } ; + + union + { + __IOM uint32_t CNT; /*!< (@ 0x00000004) desc CNT */ + + struct + { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + } CNT_f; + } ; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CR; /*!< (@ 0x0000000C) desc CR */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t COMP : 1; /*!< [1..1] desc COMP */ + __IOM uint32_t CT : 1; /*!< [2..2] desc CT */ + __IOM uint32_t PWM2S : 1; /*!< [3..3] desc PWM2S */ + __IOM uint32_t PRS : 3; /*!< [6..4] desc PRS */ + __IOM uint32_t BUFPEN : 1; /*!< [7..7] desc BUFPEN */ + __IM uint32_t : 2; + __IOM uint32_t UIE : 1; /*!< [10..10] desc UIE */ + __IM uint32_t : 1; + __IOM uint32_t MODE : 2; /*!< [13..12] Please keep 10/11 */ + __IOM uint32_t ONESHOT : 1; /*!< [14..14] desc ONESHOT */ + __IM uint32_t : 1; + __IOM uint32_t OCCS : 1; /*!< [16..16] desc OCCS */ + __IOM uint32_t URS : 1; /*!< [17..17] desc URS */ + __IM uint32_t : 1; + __IOM uint32_t TIE : 1; /*!< [19..19] desc TIE */ + __IOM uint32_t BIE : 1; /*!< [20..20] desc BIE */ + __IOM uint32_t CISA : 2; /*!< [22..21] desc CISA */ + __IOM uint32_t OCCE : 1; /*!< [23..23] desc OCCE */ + __IOM uint32_t TG : 1; /*!< [24..24] desc TG */ + __IOM uint32_t UG : 1; /*!< [25..25] desc UG */ + __IOM uint32_t BG : 1; /*!< [26..26] desc BG */ + __IOM uint32_t DIR : 1; /*!< [27..27] desc DIR */ + __IOM uint32_t OVE : 1; /*!< [28..28] desc OVE */ + __IOM uint32_t UNDE : 1; /*!< [29..29] desc UNDE */ + } CR_f; + } ; + + union + { + __IM uint32_t ISR; /*!< (@ 0x00000010) desc ISR */ + + struct + { + __IM uint32_t UIF : 1; /*!< [0..0] desc UIF */ + __IM uint32_t : 1; + __IM uint32_t C1AF : 1; /*!< [2..2] desc C1AF */ + __IM uint32_t C2AF : 1; /*!< [3..3] desc C2AF */ + __IM uint32_t C3AF : 1; /*!< [4..4] desc C3AF */ + __IM uint32_t C1BF : 1; /*!< [5..5] desc C1BF */ + __IM uint32_t C2BF : 1; /*!< [6..6] desc C2BF */ + __IM uint32_t C3BF : 1; /*!< [7..7] desc C3BF */ + __IM uint32_t C1AE : 1; /*!< [8..8] desc C1AE */ + __IM uint32_t C2AE : 1; /*!< [9..9] desc C2AE */ + __IM uint32_t C3AE : 1; /*!< [10..10] desc C3AE */ + __IM uint32_t C1BE : 1; /*!< [11..11] desc C1BE */ + __IM uint32_t C2BE : 1; /*!< [12..12] desc C2BE */ + __IM uint32_t C3BE : 1; /*!< [13..13] desc C3BE */ + __IM uint32_t BIF : 1; /*!< [14..14] desc BIF */ + __IM uint32_t TIF : 1; /*!< [15..15] desc TIF */ + __IM uint32_t OVF : 1; /*!< [16..16] desc OVF */ + __IM uint32_t UNDF : 1; /*!< [17..17] desc UNDF */ + __IM uint32_t C4AF : 1; /*!< [18..18] desc C4AF */ + } ISR_f; + } ; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000014) desc ICR */ + + struct + { + __IOM uint32_t UIF : 1; /*!< [0..0] desc UIF */ + __IM uint32_t : 1; + __IOM uint32_t C1AF : 1; /*!< [2..2] desc C1AF */ + __IOM uint32_t C2AF : 1; /*!< [3..3] desc C2AF */ + __IOM uint32_t C3AF : 1; /*!< [4..4] desc C3AF */ + __IOM uint32_t C1BF : 1; /*!< [5..5] desc C1BF */ + __IOM uint32_t C2BF : 1; /*!< [6..6] desc C2BF */ + __IOM uint32_t C3BF : 1; /*!< [7..7] desc C3BF */ + __IOM uint32_t C1AE : 1; /*!< [8..8] desc C1AE */ + __IOM uint32_t C2AE : 1; /*!< [9..9] desc C2AE */ + __IOM uint32_t C3AE : 1; /*!< [10..10] desc C3AE */ + __IOM uint32_t C1BE : 1; /*!< [11..11] desc C1BE */ + __IOM uint32_t C2BE : 1; /*!< [12..12] desc C2BE */ + __IOM uint32_t C3BE : 1; /*!< [13..13] desc C3BE */ + __IOM uint32_t BIF : 1; /*!< [14..14] desc BIF */ + __IOM uint32_t TIF : 1; /*!< [15..15] desc TIF */ + __IOM uint32_t OVF : 1; /*!< [16..16] desc OVF */ + __IOM uint32_t UNDF : 1; /*!< [17..17] desc UNDF */ + __IOM uint32_t C4AF : 1; /*!< [18..18] desc C4AF */ + } ICR_f; + } ; + + union + { + __IOM uint32_t MSCR; /*!< (@ 0x00000018) desc MSCR */ + + struct + { + __IOM uint32_t MMS : 3; /*!< [2..0] desc MMS */ + __IOM uint32_t CCDS : 1; /*!< [3..3] desc CCDS */ + __IM uint32_t : 1; + __IOM uint32_t TS : 3; /*!< [7..5] desc TS */ + __IOM uint32_t SMS : 3; /*!< [10..8] desc SMS */ + __IOM uint32_t IA1S : 1; /*!< [11..11] desc IA1S */ + __IOM uint32_t IB1S : 1; /*!< [12..12] desc IB1S */ + } MSCR_f; + } ; + + union + { + __IOM uint32_t FLTR; /*!< (@ 0x0000001C) desc FLTR */ + + struct + { + __IOM uint32_t OCM1AFLT1A : 3; /*!< [2..0] desc OCM1AFLT1A */ + __IOM uint32_t CCP1A : 1; /*!< [3..3] desc CCP1A */ + __IOM uint32_t OCM1BFLT1B : 3; /*!< [6..4] desc OCM1BFLT1B */ + __IOM uint32_t CCP1B : 1; /*!< [7..7] desc CCP1B */ + __IOM uint32_t OCM2AFLT2A : 3; /*!< [10..8] desc OCM2AFLT2A */ + __IOM uint32_t CCP2A : 1; /*!< [11..11] desc CCP2A */ + __IOM uint32_t OCM2BFLT2B : 3; /*!< [14..12] desc OCM2BFLT2B */ + __IOM uint32_t CCP2B : 1; /*!< [15..15] desc CCP2B */ + __IOM uint32_t OCM3AFLT3A : 3; /*!< [18..16] desc OCM3AFLT3A */ + __IOM uint32_t CCP3A : 1; /*!< [19..19] desc CCP3A */ + __IOM uint32_t OCM3BFLT3B : 3; /*!< [22..20] desc OCM3BFLT3B */ + __IOM uint32_t CCP3B : 1; /*!< [23..23] desc CCP3B */ + __IOM uint32_t FLTBK : 3; /*!< [26..24] desc FLTBK */ + __IOM uint32_t BKP : 1; /*!< [27..27] desc BKP */ + __IOM uint32_t FLTET : 3; /*!< [30..28] desc FLTET */ + __IOM uint32_t ETP : 1; /*!< [31..31] desc ETP */ + } FLTR_f; + } ; + + union + { + __IOM uint32_t TRIG; /*!< (@ 0x00000020) desc TRIG */ + + struct + { + __IOM uint32_t UEVE : 1; /*!< [0..0] desc UEVE */ + __IOM uint32_t CM1AE : 1; /*!< [1..1] desc CM1AE */ + __IOM uint32_t CM2AE : 1; /*!< [2..2] desc CM2AE */ + __IOM uint32_t CM3AE : 1; /*!< [3..3] desc CM3AE */ + __IOM uint32_t CM1BE : 1; /*!< [4..4] desc CM1BE */ + __IOM uint32_t CM2BE : 1; /*!< [5..5] desc CM2BE */ + __IOM uint32_t CM3BE : 1; /*!< [6..6] desc CM3BE */ + __IOM uint32_t ADTE : 1; /*!< [7..7] desc ADTE */ + } TRIG_f; + } ; + + union + { + __IOM uint32_t CH1CR; /*!< (@ 0x00000024) desc CH1CR */ + + struct + { + __IOM uint32_t BKSA : 2; /*!< [1..0] desc BKSA */ + __IOM uint32_t BKSB : 2; /*!< [3..2] desc BKSB */ + __IOM uint32_t CSA : 1; /*!< [4..4] desc CSA */ + __IOM uint32_t CSB : 1; /*!< [5..5] desc CSB */ + __IOM uint32_t BUFEA : 1; /*!< [6..6] desc BUFEA */ + __IOM uint32_t BUFEB : 1; /*!< [7..7] desc BUFEB */ + __IOM uint32_t CIEA : 1; /*!< [8..8] desc CIEA */ + __IOM uint32_t CIEB : 1; /*!< [9..9] desc CIEB */ + __IOM uint32_t CDEA : 1; /*!< [10..10] desc CDEA */ + __IOM uint32_t CDEB : 1; /*!< [11..11] desc CDEB */ + __IOM uint32_t CISB : 2; /*!< [13..12] desc CISB */ + __IOM uint32_t CCGA : 1; /*!< [14..14] desc CCGA */ + __IOM uint32_t CCGB : 1; /*!< [15..15] desc CCGB */ + } CH1CR_f; + } ; + + union + { + __IOM uint32_t CH2CR; /*!< (@ 0x00000028) desc CH2CR */ + + struct + { + __IOM uint32_t BKSA : 2; /*!< [1..0] desc BKSA */ + __IOM uint32_t BKSB : 2; /*!< [3..2] desc BKSB */ + __IOM uint32_t CSA : 1; /*!< [4..4] desc CSA */ + __IOM uint32_t CSB : 1; /*!< [5..5] desc CSB */ + __IOM uint32_t BUFEA : 1; /*!< [6..6] desc BUFEA */ + __IOM uint32_t BUFEB : 1; /*!< [7..7] desc BUFEB */ + __IOM uint32_t CIEA : 1; /*!< [8..8] desc CIEA */ + __IOM uint32_t CIEB : 1; /*!< [9..9] desc CIEB */ + __IOM uint32_t CDEA : 1; /*!< [10..10] desc CDEA */ + __IOM uint32_t CDEB : 1; /*!< [11..11] desc CDEB */ + __IOM uint32_t CISB : 2; /*!< [13..12] desc CISB */ + __IOM uint32_t CCGA : 1; /*!< [14..14] desc CCGA */ + __IOM uint32_t CCGB : 1; /*!< [15..15] desc CCGB */ + } CH2CR_f; + } ; + + union + { + __IOM uint32_t CH3CR; /*!< (@ 0x0000002C) desc CH3CR */ + + struct + { + __IOM uint32_t BKSA : 2; /*!< [1..0] desc BKSA */ + __IOM uint32_t BKSB : 2; /*!< [3..2] desc BKSB */ + __IOM uint32_t CSA : 1; /*!< [4..4] desc CSA */ + __IOM uint32_t CSB : 1; /*!< [5..5] desc CSB */ + __IOM uint32_t BUFEA : 1; /*!< [6..6] desc BUFEA */ + __IOM uint32_t BUFEB : 1; /*!< [7..7] desc BUFEB */ + __IOM uint32_t CIEA : 1; /*!< [8..8] desc CIEA */ + __IOM uint32_t CIEB : 1; /*!< [9..9] desc CIEB */ + __IOM uint32_t CDEA : 1; /*!< [10..10] desc CDEA */ + __IOM uint32_t CDEB : 1; /*!< [11..11] desc CDEB */ + __IOM uint32_t CISB : 2; /*!< [13..12] desc CISB */ + __IOM uint32_t CCGA : 1; /*!< [14..14] desc CCGA */ + __IOM uint32_t CCGB : 1; /*!< [15..15] desc CCGB */ + } CH3CR_f; + } ; + + union + { + __IOM uint32_t DTR; /*!< (@ 0x00000030) desc DTR */ + + struct + { + __IOM uint32_t DTR : 8; /*!< [7..0] desc DTR */ + __IM uint32_t : 1; + __IOM uint32_t DTEN : 1; /*!< [9..9] desc DTEN */ + __IOM uint32_t BKE : 1; /*!< [10..10] desc BKE */ + __IOM uint32_t AOE : 1; /*!< [11..11] desc AOE */ + __IOM uint32_t MOE : 1; /*!< [12..12] desc MOE */ + __IOM uint32_t SAFEEN : 1; /*!< [13..13] desc SAFEEN */ + __IOM uint32_t VCE : 1; /*!< [14..14] desc VCE */ + } DTR_f; + } ; + + union + { + __IOM uint32_t RCR; /*!< (@ 0x00000034) desc RCR */ + + struct + { + __IOM uint32_t RCR : 8; /*!< [7..0] desc RCR */ + __IOM uint32_t OV : 1; /*!< [8..8] desc OV */ + __IOM uint32_t UD : 1; /*!< [9..9] desc UD */ + } RCR_f; + } ; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t CH1CCRA; /*!< (@ 0x0000003C) desc CH1CCRA */ + + struct + { + __IOM uint32_t CCR1A : 16; /*!< [15..0] desc CCR1A */ + } CH1CCRA_f; + } ; + + union + { + __IOM uint32_t CH1CCRB; /*!< (@ 0x00000040) desc CH1CCRB */ + + struct + { + __IOM uint32_t CCR1B : 16; /*!< [15..0] desc CCR1B */ + } CH1CCRB_f; + } ; + + union + { + __IOM uint32_t CH2CCRA; /*!< (@ 0x00000044) desc CH2CCRA */ + + struct + { + __IOM uint32_t CCR2A : 16; /*!< [15..0] desc CCR2A */ + } CH2CCRA_f; + } ; + + union + { + __IOM uint32_t CH2CCRB; /*!< (@ 0x00000048) desc CH2CCRB */ + + struct + { + __IOM uint32_t CCR2B : 16; /*!< [15..0] desc CCR2B */ + } CH2CCRB_f; + } ; + + union + { + __IOM uint32_t CH3CCRA; /*!< (@ 0x0000004C) desc CH3CCRA */ + + struct + { + __IOM uint32_t CCR3A : 16; /*!< [15..0] desc CCR3A */ + } CH3CCRA_f; + } ; + + union + { + __IOM uint32_t CH3CCRB; /*!< (@ 0x00000050) desc CH3CCRB */ + + struct + { + __IOM uint32_t CCR3B : 16; /*!< [15..0] desc CCR3B */ + } CH3CCRB_f; + } ; + + union + { + __IOM uint32_t CH4CCR; /*!< (@ 0x00000054) desc CH4CCR */ + + struct + { + __IOM uint32_t CCR4 : 16; /*!< [15..0] desc CCR4 */ + } CH4CCR_f; + } ; + + union + { + __IOM uint32_t CH4CR; /*!< (@ 0x00000058) desc CH4CR */ + + struct + { + __IOM uint32_t BUFE : 1; /*!< [0..0] desc BUFE */ + __IOM uint32_t CIE : 1; /*!< [1..1] desc CIE */ + __IOM uint32_t CDE : 1; /*!< [2..2] desc CDE */ + __IOM uint32_t CIS : 2; /*!< [4..3] desc CIS */ + __IOM uint32_t C4EN : 1; /*!< [5..5] desc C4EN */ + } CH4CR_f; + } ; +} ATIM_TypeDef; /*!< Size = 92 (0x5c) */ + + + +/* =========================================================================================================================== */ +/* ================ AWT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc AWT (AWT) + */ + +typedef struct /*!< (@ 0x40014C00) AWT Structure */ +{ + + union + { + __IOM uint32_t CR; /*!< (@ 0x00000000) Control register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t MD : 2; /*!< [2..1] desc MD */ + __IM uint32_t : 1; + __IOM uint32_t PRS : 4; /*!< [7..4] desc PRS */ + __IOM uint32_t SRC : 3; /*!< [10..8] desc SRC */ + } CR_f; + } ; + + union + { + __IOM uint32_t ARR; /*!< (@ 0x00000004) Auto reload register */ + + struct + { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } ARR_f; + } ; + + union + { + __IM uint32_t CNT; /*!< (@ 0x00000008) counter */ + + struct + { + __IM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + } CNT_f; + } ; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t IER; /*!< (@ 0x00000010) Interrupt enable register */ + + struct + { + __IM uint32_t : 3; + __IOM uint32_t UD : 1; /*!< [3..3] desc UD */ + } IER_f; + } ; + + union + { + __IM uint32_t ISR; /*!< (@ 0x00000014) Interrupt status register */ + + struct + { + __IM uint32_t : 3; + __IM uint32_t UD : 1; /*!< [3..3] desc UD */ + } ISR_f; + } ; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x0000001C) Interrupt flag clear register */ + + struct + { + __IM uint32_t : 3; + __IOM uint32_t UD : 1; /*!< [3..3] desc UD */ + } ICR_f; + } ; +} AWT_TypeDef; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ BTIM1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Base Timer 1 (BTIM1) + */ + +typedef struct /*!< (@ 0x40014800) BTIM1 Structure */ +{ + + union + { + __IOM uint32_t ARR; /*!< (@ 0x00000000) Auto Reload Register */ + + struct + { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } ARR_f; + } ; + + union + { + __IOM uint32_t CNT; /*!< (@ 0x00000004) Counter Register */ + + struct + { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + } CNT_f; + } ; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t ACR; /*!< (@ 0x0000000C) Advanced Control register */ + + struct + { + __IM uint32_t : 4; + __IOM uint32_t ETRFLT : 3; /*!< [6..4] desc ETRFLT */ + } ACR_f; + } ; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000010) Base Control register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t MODE : 2; /*!< [2..1] desc MODE */ + __IOM uint32_t TRS : 1; /*!< [3..3] desc TRS */ + __IOM uint32_t POL : 1; /*!< [4..4] desc POL */ + __IOM uint32_t ONESHOT : 1; /*!< [5..5] desc ONESHOT */ + __IOM uint32_t TOGEN : 1; /*!< [6..6] desc TOGEN */ + __IOM uint32_t PRS : 4; /*!< [10..7] desc PRS */ + __IM uint32_t PRSSTATUS : 4; /*!< [14..11] desc PRSSTATUS */ + } BCR_f; + } ; + + union + { + __IOM uint32_t IER; /*!< (@ 0x00000014) Interrupt enable register */ + + struct + { + __IOM uint32_t OV : 1; /*!< [0..0] desc OV */ + __IOM uint32_t TI : 1; /*!< [1..1] desc TI */ + __IOM uint32_t TOP : 1; /*!< [2..2] desc TOP */ + } IER_f; + } ; + + union + { + __IM uint32_t ISR; /*!< (@ 0x00000018) Interrupt status register */ + + struct + { + __IM uint32_t OV : 1; /*!< [0..0] desc OV */ + __IM uint32_t TI : 1; /*!< [1..1] desc TI */ + __IM uint32_t TOP : 1; /*!< [2..2] desc TOP */ + } ISR_f; + } ; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x0000001C) Interrupt flag clear register */ + + struct + { + __IOM uint32_t OV : 1; /*!< [0..0] desc OV */ + __IOM uint32_t TI : 1; /*!< [1..1] desc TI */ + __IOM uint32_t TOP : 1; /*!< [2..2] desc TOP */ + } ICR_f; + } ; + + union + { + __IOM uint32_t DMA; /*!< (@ 0x00000020) DMA control register */ + + struct + { + __IOM uint32_t OV : 1; /*!< [0..0] desc OV */ + __IOM uint32_t TRS : 1; /*!< [1..1] desc TRS */ + } DMA_f; + } ; +} BTIM_TypeDef; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ CRC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc CRC (CRC) + */ + +typedef struct /*!< (@ 0x40023000) CRC Structure */ +{ + + union + { + __IOM uint32_t CR; /*!< (@ 0x00000000) Control register */ + + struct + { + __IOM uint32_t MODE : 4; /*!< [3..0] desc MODE */ + } CR_f; + } ; + __IM uint32_t RESERVED; + + union + { + union + { + __IOM uint32_t DR32; /*!< (@ 0x00000008) Data register */ + + struct + { + __IOM uint32_t DR32 : 32; /*!< [31..0] desc DR32 */ + } DR32_f; + } ; + + union + { + __IOM uint16_t DR16; /*!< (@ 0x00000008) Data register */ + + struct + { + __IOM uint16_t DR16 : 16; /*!< [15..0] desc DR16 */ + } DR16_f; + } ; + + union + { + __IOM uint8_t DR8; /*!< (@ 0x00000008) Data register */ + __IOM uint8_t DR; + struct + { + __IOM uint8_t DR8 : 8; /*!< [7..0] desc DR8 */ + } DR8_f; + } ; + }; + + union + { + union + { + __IM uint32_t RESULT32; /*!< (@ 0x0000000C) Result register */ + + struct + { + __IM uint32_t RESULT32 : 32; /*!< [31..0] desc RESULT32 */ + } RESULT32_f; + } ; + + union + { + __IM uint16_t RESULT16; /*!< (@ 0x0000000C) Result register */ + __IM uint16_t RESULT; + + struct + { + __IM uint16_t RESULT16 : 16; /*!< [15..0] desc RESULT16 */ + } RESULT16_f; + } ; + }; +} CRC_TypeDef; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc DMA (DMA) + */ + +typedef struct /*!< (@ 0x40020000) DMA Structure */ +{ + + union + { + __IM uint32_t ISR; /*!< (@ 0x00000000) Interrupt status register */ + + struct + { + __IM uint32_t TC1 : 1; /*!< [0..0] desc TC1 */ + __IM uint32_t TE1 : 1; /*!< [1..1] desc TE1 */ + __IM uint32_t : 2; + __IM uint32_t TC2 : 1; /*!< [4..4] desc TC2 */ + __IM uint32_t TE2 : 1; /*!< [5..5] desc TE2 */ + __IM uint32_t : 2; + __IM uint32_t TC3 : 1; /*!< [8..8] desc TC3 */ + __IM uint32_t TE3 : 1; /*!< [9..9] desc TE3 */ + __IM uint32_t : 2; + __IM uint32_t TC4 : 1; /*!< [12..12] desc TC4 */ + __IM uint32_t TE4 : 1; /*!< [13..13] desc TE4 */ + __IM uint32_t : 2; + __IM uint32_t TC5 : 1; /*!< [16..16] desc TC5 */ + __IM uint32_t TE5 : 1; /*!< [17..17] desc TE5 */ + } ISR_f; + } ; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000004) Interrupt flag clear register */ + + struct + { + __IOM uint32_t TC1 : 1; /*!< [0..0] desc TC1 */ + __IOM uint32_t TE1 : 1; /*!< [1..1] desc TE1 */ + __IM uint32_t : 2; + __IOM uint32_t TC2 : 1; /*!< [4..4] desc TC2 */ + __IOM uint32_t TE2 : 1; /*!< [5..5] desc TE2 */ + __IM uint32_t : 2; + __IOM uint32_t TC3 : 1; /*!< [8..8] desc TC3 */ + __IOM uint32_t TE3 : 1; /*!< [9..9] desc TE3 */ + __IM uint32_t : 2; + __IOM uint32_t TC4 : 1; /*!< [12..12] desc TC4 */ + __IOM uint32_t TE4 : 1; /*!< [13..13] desc TE4 */ + __IM uint32_t : 2; + __IOM uint32_t TC5 : 1; /*!< [16..16] desc TC5 */ + __IOM uint32_t TE5 : 1; /*!< [17..17] desc TE5 */ + } ICR_f; + } ; + __IM uint32_t RESERVED[6]; + + union + { + __IOM uint32_t CSR1; /*!< (@ 0x00000020) Channel1 control and status register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + } CSR1_f; + } ; + + union + { + __IOM uint32_t CNT1; /*!< (@ 0x00000024) Channel1 counter register */ + + struct + { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT1_f; + } ; + + union + { + __IOM uint32_t SRCADDR1; /*!< (@ 0x00000028) Channel1 source address register */ + + struct + { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR1_f; + } ; + + union + { + __IOM uint32_t DSTADDR1; /*!< (@ 0x0000002C) Channel1 destination address register */ + + struct + { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR1_f; + } ; + + union + { + __IOM uint32_t TRIG1; /*!< (@ 0x00000030) Channel1 trigger register */ + + struct + { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG1_f; + } ; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CSR2; /*!< (@ 0x00000040) Channel2 control and status register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + } CSR2_f; + } ; + + union + { + __IOM uint32_t CNT2; /*!< (@ 0x00000044) Channel2 counter register */ + + struct + { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT2_f; + } ; + + union + { + __IOM uint32_t SRCADDR2; /*!< (@ 0x00000048) Channel2 source address register */ + + struct + { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR2_f; + } ; + + union + { + __IOM uint32_t DSTADDR2; /*!< (@ 0x0000004C) Channel2 destination address register */ + + struct + { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR2_f; + } ; + + union + { + __IOM uint32_t TRIG2; /*!< (@ 0x00000050) Channel2 trigger register */ + + struct + { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG2_f; + } ; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t CSR3; /*!< (@ 0x00000060) Channel3 control and status register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + } CSR3_f; + } ; + + union + { + __IOM uint32_t CNT3; /*!< (@ 0x00000064) Channel3 counter register */ + + struct + { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT3_f; + } ; + + union + { + __IOM uint32_t SRCADDR3; /*!< (@ 0x00000068) Channel3 source address register */ + + struct + { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR3_f; + } ; + + union + { + __IOM uint32_t DSTADDR3; /*!< (@ 0x0000006C) Channel3 destination address register */ + + struct + { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR3_f; + } ; + + union + { + __IOM uint32_t TRIG3; /*!< (@ 0x00000070) Channel3 trigger register */ + + struct + { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG3_f; + } ; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t CSR4; /*!< (@ 0x00000080) Channel4 control and status register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + } CSR4_f; + } ; + + union + { + __IOM uint32_t CNT4; /*!< (@ 0x00000084) Channel4 counter register */ + + struct + { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT4_f; + } ; + + union + { + __IOM uint32_t SRCADDR4; /*!< (@ 0x00000088) Channel4 source address register */ + + struct + { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR4_f; + } ; + + union + { + __IOM uint32_t DSTADDR4; /*!< (@ 0x0000008C) Channel4 destination address register */ + + struct + { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR4_f; + } ; + + union + { + __IOM uint32_t TRIG4; /*!< (@ 0x00000090) Channel4 trigger register */ + + struct + { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG4_f; + } ; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t CSR5; /*!< (@ 0x000000A0) Channel5 control and status register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + } CSR5_f; + } ; + + union + { + __IOM uint32_t CNT5; /*!< (@ 0x000000A4) Channel5 counter register */ + + struct + { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT5_f; + } ; + + union + { + __IOM uint32_t SRCADDR5; /*!< (@ 0x000000A8) Channel5 source address register */ + + struct + { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR5_f; + } ; + + union + { + __IOM uint32_t DSTADDR5; /*!< (@ 0x000000AC) Channel5 destination address register */ + + struct + { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR5_f; + } ; + + union + { + __IOM uint32_t TRIG5; /*!< (@ 0x000000B0) Channel5 trigger register */ + + struct + { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG5_f; + } ; +} DMA_TypeDef; /*!< Size = 180 (0xb4) */ + + + +/* =========================================================================================================================== */ +/* ================ DMACHANNEL1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DMA Channel 1 (DMACHANNEL1) + */ + +typedef struct /*!< (@ 0x40020020) DMACHANNEL1 Structure */ +{ + + union + { + __IOM uint32_t CSR; /*!< (@ 0x00000000) Channel.y control and status register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + } CSR_f; + } ; + + union + { + __IOM uint32_t CNT; /*!< (@ 0x00000004) Channel.y counter register */ + + struct + { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT_f; + } ; + + union + { + __IOM uint32_t SRCADDR; /*!< (@ 0x00000008) Channel.y source address register */ + + struct + { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR_f; + } ; + + union + { + __IOM uint32_t DSTADDR; /*!< (@ 0x0000000C) Channel.y destination address register */ + + struct + { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR_f; + } ; + + union + { + __IOM uint32_t TRIG; /*!< (@ 0x00000010) Channel.y trigger register */ + + struct + { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG_f; + } ; +} DMACHANNEL_TypeDef; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ FLASH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc FLASH (FLASH) + */ + +typedef struct /*!< (@ 0x40022000) FLASH Structure */ +{ + + union + { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control register1 */ + + struct + { + __IOM uint32_t MODE : 2; /*!< [1..0] desc MODE */ + __IM uint32_t : 2; + __IOM uint32_t STANDBY : 1; /*!< [4..4] desc STANDBY */ + __IM uint32_t BUSY : 1; /*!< [5..5] desc BUSY */ + __IM uint32_t SECURITY : 2; /*!< [7..6] desc SECURITY */ + __IM uint32_t : 8; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR1_f; + } ; + + union + { + __IOM uint32_t CR2; /*!< (@ 0x00000004) Control register2 */ + + struct + { + __IOM uint32_t WAIT : 3; /*!< [2..0] desc WAIT */ + __IOM uint32_t FETCH : 1; /*!< [3..3] desc FETCH */ + __IOM uint32_t CACHE : 1; /*!< [4..4] desc CACHE */ + __IM uint32_t : 11; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR2_f; + } ; + + union + { + __IOM uint32_t PAGELOCK; /*!< (@ 0x00000008) Page Write Erase Lock */ + + struct + { + __IOM uint32_t LOCK0 : 1; /*!< [0..0] Page0 - 7 */ + __IOM uint32_t LOCK1 : 1; /*!< [1..1] Page8 - 15 */ + __IOM uint32_t LOCK2 : 1; /*!< [2..2] Page16 - 23 */ + __IOM uint32_t LOCK3 : 1; /*!< [3..3] Page24 - 31 */ + __IOM uint32_t LOCK4 : 1; /*!< [4..4] Page32 - 39 */ + __IOM uint32_t LOCK5 : 1; /*!< [5..5] Page40 - 47 */ + __IOM uint32_t LOCK6 : 1; /*!< [6..6] Page48 - 55 */ + __IOM uint32_t LOCK7 : 1; /*!< [7..7] Page56 - 63 */ + __IOM uint32_t LOCK8 : 1; /*!< [8..8] Page64 - 71 */ + __IOM uint32_t LOCK9 : 1; /*!< [9..9] Page72 - 79 */ + __IOM uint32_t LOCK10 : 1; /*!< [10..10] Page80 - 87 */ + __IOM uint32_t LOCK11 : 1; /*!< [11..11] Page88 - 95 */ + __IOM uint32_t LOCK12 : 1; /*!< [12..12] Page96 - 103 */ + __IOM uint32_t LOCK13 : 1; /*!< [13..13] Page104 - 111 */ + __IOM uint32_t LOCK14 : 1; /*!< [14..14] Page112 - 119 */ + __IOM uint32_t LOCK15 : 1; /*!< [15..15] Page120 - 127 */ + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } PAGELOCK_f; + } ; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t IER; /*!< (@ 0x00000020) Interrupt enable register */ + + struct + { + __IOM uint32_t PC : 1; /*!< [0..0] desc PC */ + __IOM uint32_t PAGELOCK : 1; /*!< [1..1] desc PAGELOCK */ + __IM uint32_t : 2; + __IOM uint32_t PROG : 1; /*!< [4..4] desc PROG */ + } IER_f; + } ; + + union + { + __IM uint32_t ISR; /*!< (@ 0x00000024) Interrupt status register */ + + struct + { + __IM uint32_t PC : 1; /*!< [0..0] desc PC */ + __IM uint32_t PAGELOCK : 1; /*!< [1..1] desc PAGELOCK */ + __IM uint32_t : 2; + __IM uint32_t PROG : 1; /*!< [4..4] desc PROG */ + } ISR_f; + } ; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000028) Interrupt flag clear register */ + + struct + { + __IOM uint32_t PC : 1; /*!< [0..0] desc PC */ + __IOM uint32_t PAGELOCK : 1; /*!< [1..1] desc PAGELOCK */ + __IM uint32_t : 2; + __IOM uint32_t PROG : 1; /*!< [4..4] desc PROG */ + } ICR_f; + } ; +} FLASH_TypeDef; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc GPIOA (GPIOA) + */ + +typedef struct /*!< (@ 0x48000000) GPIOA Structure */ +{ + + union + { + __IOM uint32_t DIR; /*!< (@ 0x00000000) desc DIR */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } DIR_f; + } ; + + union + { + __IOM uint32_t OPENDRAIN; /*!< (@ 0x00000004) desc OPENDRAIN */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } OPENDRAIN_f; + } ; + + union + { + __IOM uint32_t SPEED; /*!< (@ 0x00000008) desc SPEED */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } SPEED_f; + } ; + + union + { + __IOM uint32_t PDR; /*!< (@ 0x0000000C) desc PDR */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } PDR_f; + } ; + + union + { + __IOM uint32_t PUR; /*!< (@ 0x00000010) desc PUR */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } PUR_f; + } ; + + union + { + __IOM uint32_t AFRH; /*!< (@ 0x00000014) desc AFRH */ + + struct + { + __IOM uint32_t AFR8 : 4; /*!< [3..0] desc AFR8 */ + __IOM uint32_t AFR9 : 4; /*!< [7..4] desc AFR9 */ + __IOM uint32_t AFR10 : 4; /*!< [11..8] desc AFR10 */ + __IOM uint32_t AFR11 : 4; /*!< [15..12] desc AFR11 */ + __IOM uint32_t AFR12 : 4; /*!< [19..16] desc AFR12 */ + __IOM uint32_t AFR13 : 4; /*!< [23..20] desc AFR13 */ + __IOM uint32_t AFR14 : 4; /*!< [27..24] desc AFR14 */ + __IOM uint32_t AFR15 : 4; /*!< [31..28] desc AFR15 */ + } AFRH_f; + } ; + + union + { + __IOM uint32_t AFRL; /*!< (@ 0x00000018) desc AFRL */ + + struct + { + __IOM uint32_t AFR0 : 4; /*!< [3..0] desc AFR0 */ + __IOM uint32_t AFR1 : 4; /*!< [7..4] desc AFR1 */ + __IOM uint32_t AFR2 : 4; /*!< [11..8] desc AFR2 */ + __IOM uint32_t AFR3 : 4; /*!< [15..12] desc AFR3 */ + __IOM uint32_t AFR4 : 4; /*!< [19..16] desc AFR4 */ + __IOM uint32_t AFR5 : 4; /*!< [23..20] desc AFR5 */ + __IOM uint32_t AFR6 : 4; /*!< [27..24] desc AFR6 */ + __IOM uint32_t AFR7 : 4; /*!< [31..28] desc AFR7 */ + } AFRL_f; + } ; + + union + { + __IOM uint32_t ANALOG; /*!< (@ 0x0000001C) desc ANALOG */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ANALOG_f; + } ; + + union + { + __IOM uint32_t DRIVER; /*!< (@ 0x00000020) desc DRIVER */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } DRIVER_f; + } ; + + union + { + __IOM uint32_t RISEIE; /*!< (@ 0x00000024) Interrupt enable register */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } RISEIE_f; + } ; + + union + { + __IOM uint32_t FALLIE; /*!< (@ 0x00000028) Interrupt enable register */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } FALLIE_f; + } ; + + union + { + __IOM uint32_t HIGHIE; /*!< (@ 0x0000002C) Interrupt enable register */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } HIGHIE_f; + } ; + + union + { + __IOM uint32_t LOWIE; /*!< (@ 0x00000030) Interrupt enable register */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } LOWIE_f; + } ; + + union + { + __IOM uint32_t ISR; /*!< (@ 0x00000034) Interrupt status register */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ISR_f; + } ; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000038) Interrupt flag clear register */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ICR_f; + } ; + + union + { + __IOM uint32_t LOCK; /*!< (@ 0x0000003C) desc LOCK */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + __OM uint32_t KEY : 16; /*!< [31..16] KEY = 0x5A5A */ + } LOCK_f; + } ; + + union + { + __IOM uint32_t FILTER; /*!< (@ 0x00000040) desc FILTER */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + __IOM uint32_t FLTCLK : 3; /*!< [18..16] desc FLTCLK */ + } FILTER_f; + } ; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t IDR; /*!< (@ 0x00000050) desc IDR */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } IDR_f; + } ; + + union + { + union + { + __IOM uint32_t ODR; /*!< (@ 0x00000054) desc ODR */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ODR_f; + } ; + + struct + { + union + { + __IOM uint8_t ODRLOWBYTE; /*!< (@ 0x00000054) desc ODRLOWBYTE */ + + struct + { + __IOM uint8_t LOWBYTE : 8; /*!< [7..0] desc LOWBYTE */ + } ODRLOWBYTE_f; + } ; + + union + { + __IOM uint8_t ODRHIGHBYTE; /*!< (@ 0x00000055) desc ODRHIGHBYTE */ + + struct + { + __IOM uint8_t HIGHBYTE : 8; /*!< [7..0] desc HIGHBYTE */ + } ODRHIGHBYTE_f; + } ; + }; + }; + + union + { + __IOM uint32_t BRR; /*!< (@ 0x00000058) desc BRR */ + + struct + { + __IOM uint32_t BRR0 : 1; /*!< [0..0] desc BRR0 */ + __IOM uint32_t BRR1 : 1; /*!< [1..1] desc BRR1 */ + __IOM uint32_t BRR2 : 1; /*!< [2..2] desc BRR2 */ + __IOM uint32_t BRR3 : 1; /*!< [3..3] desc BRR3 */ + __IOM uint32_t BRR4 : 1; /*!< [4..4] desc BRR4 */ + __IOM uint32_t BRR5 : 1; /*!< [5..5] desc BRR5 */ + __IOM uint32_t BRR6 : 1; /*!< [6..6] desc BRR6 */ + __IOM uint32_t BRR7 : 1; /*!< [7..7] desc BRR7 */ + __IOM uint32_t BRR8 : 1; /*!< [8..8] desc BRR8 */ + __IOM uint32_t BRR9 : 1; /*!< [9..9] desc BRR9 */ + __IOM uint32_t BRR10 : 1; /*!< [10..10] desc BRR10 */ + __IOM uint32_t BRR11 : 1; /*!< [11..11] desc BRR11 */ + __IOM uint32_t BRR12 : 1; /*!< [12..12] desc BRR12 */ + __IOM uint32_t BRR13 : 1; /*!< [13..13] desc BRR13 */ + __IOM uint32_t BRR14 : 1; /*!< [14..14] desc BRR14 */ + __IOM uint32_t BRR15 : 1; /*!< [15..15] desc BRR15 */ + } BRR_f; + } ; + + union + { + __IOM uint32_t BSRR; /*!< (@ 0x0000005C) desc BSRR */ + + struct + { + __IOM uint32_t BSS0 : 1; /*!< [0..0] desc BSS0 */ + __IOM uint32_t BSS1 : 1; /*!< [1..1] desc BSS1 */ + __IOM uint32_t BSS2 : 1; /*!< [2..2] desc BSS2 */ + __IOM uint32_t BSS3 : 1; /*!< [3..3] desc BSS3 */ + __IOM uint32_t BSS4 : 1; /*!< [4..4] desc BSS4 */ + __IOM uint32_t BSS5 : 1; /*!< [5..5] desc BSS5 */ + __IOM uint32_t BSS6 : 1; /*!< [6..6] desc BSS6 */ + __IOM uint32_t BSS7 : 1; /*!< [7..7] desc BSS7 */ + __IOM uint32_t BSS8 : 1; /*!< [8..8] desc BSS8 */ + __IOM uint32_t BSS9 : 1; /*!< [9..9] desc BSS9 */ + __IOM uint32_t BSS10 : 1; /*!< [10..10] desc BSS10 */ + __IOM uint32_t BSS11 : 1; /*!< [11..11] desc BSS11 */ + __IOM uint32_t BSS12 : 1; /*!< [12..12] desc BSS12 */ + __IOM uint32_t BSS13 : 1; /*!< [13..13] desc BSS13 */ + __IOM uint32_t BSS14 : 1; /*!< [14..14] desc BSS14 */ + __IOM uint32_t BSS15 : 1; /*!< [15..15] desc BSS15 */ + __IOM uint32_t BRR0 : 1; /*!< [16..16] desc BRR0 */ + __IOM uint32_t BRR1 : 1; /*!< [17..17] desc BRR1 */ + __IOM uint32_t BRR2 : 1; /*!< [18..18] desc BRR2 */ + __IOM uint32_t BRR3 : 1; /*!< [19..19] desc BRR3 */ + __IOM uint32_t BRR4 : 1; /*!< [20..20] desc BRR4 */ + __IOM uint32_t BRR5 : 1; /*!< [21..21] desc BRR5 */ + __IOM uint32_t BRR6 : 1; /*!< [22..22] desc BRR6 */ + __IOM uint32_t BRR7 : 1; /*!< [23..23] desc BRR7 */ + __IOM uint32_t BRR8 : 1; /*!< [24..24] desc BRR8 */ + __IOM uint32_t BRR9 : 1; /*!< [25..25] desc BRR9 */ + __IOM uint32_t BRR10 : 1; /*!< [26..26] desc BRR10 */ + __IOM uint32_t BRR11 : 1; /*!< [27..27] desc BRR11 */ + __IOM uint32_t BRR12 : 1; /*!< [28..28] desc BRR12 */ + __IOM uint32_t BRR13 : 1; /*!< [29..29] desc BRR13 */ + __IOM uint32_t BRR14 : 1; /*!< [30..30] desc BRR14 */ + __IOM uint32_t BRR15 : 1; /*!< [31..31] desc BRR15 */ + } BSRR_f; + } ; + + union + { + __IOM uint32_t TOG; /*!< (@ 0x00000060) desc TOG */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } TOG_f; + } ; +} GPIO_TypeDef; /*!< Size = 100 (0x64) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc GPIOC (GPIOC) + */ + +typedef struct /*!< (@ 0x48000800) GPIOC Structure */ +{ + + union + { + __IOM uint32_t DIR; /*!< (@ 0x00000000) desc DIR */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } DIR_f; + } ; + + union + { + __IOM uint32_t OPENDRAIN; /*!< (@ 0x00000004) desc OPENDRAIN */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } OPENDRAIN_f; + } ; + + union + { + __IOM uint32_t SPEED; /*!< (@ 0x00000008) desc SPEED */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } SPEED_f; + } ; + + union + { + __IOM uint32_t PDR; /*!< (@ 0x0000000C) desc PDR */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } PDR_f; + } ; + + union + { + __IOM uint32_t PUR; /*!< (@ 0x00000010) desc PUR */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } PUR_f; + } ; + + union + { + __IOM uint32_t AFRH; /*!< (@ 0x00000014) desc AFRH */ + + struct + { + __IM uint32_t : 20; + __IOM uint32_t AFR13 : 4; /*!< [23..20] desc AFR13 */ + __IOM uint32_t AFR14 : 4; /*!< [27..24] desc AFR14 */ + __IOM uint32_t AFR15 : 4; /*!< [31..28] desc AFR15 */ + } AFRH_f; + } ; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t ANALOG; /*!< (@ 0x0000001C) desc ANALOG */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ANALOG_f; + } ; + + union + { + __IOM uint32_t DRIVER; /*!< (@ 0x00000020) desc DRIVER */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } DRIVER_f; + } ; + + union + { + __IOM uint32_t RISEIE; /*!< (@ 0x00000024) Interrupt enable register */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } RISEIE_f; + } ; + + union + { + __IOM uint32_t FALLIE; /*!< (@ 0x00000028) Interrupt enable register */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } FALLIE_f; + } ; + + union + { + __IOM uint32_t HIGHIE; /*!< (@ 0x0000002C) Interrupt enable register */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } HIGHIE_f; + } ; + + union + { + __IOM uint32_t LOWIE; /*!< (@ 0x00000030) Interrupt enable register */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } LOWIE_f; + } ; + + union + { + __IOM uint32_t ISR; /*!< (@ 0x00000034) Interrupt status register */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ISR_f; + } ; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000038) Interrupt flag clear register */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ICR_f; + } ; + + union + { + __IOM uint32_t LOCK; /*!< (@ 0x0000003C) desc LOCK */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + __OM uint32_t KEY : 16; /*!< [31..16] KEY = 0x5A5A */ + } LOCK_f; + } ; + + union + { + __IOM uint32_t FILTER; /*!< (@ 0x00000040) desc FILTER */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + __IOM uint32_t FLTCLK : 3; /*!< [18..16] desc FLTCLK */ + } FILTER_f; + } ; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t IDR; /*!< (@ 0x00000050) desc IDR */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } IDR_f; + } ; + + union + { + union + { + __IOM uint32_t ODR; /*!< (@ 0x00000054) desc ODR */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ODR_f; + } ; + + struct + { + union + { + __IOM uint8_t ODRLOWBYTE; /*!< (@ 0x00000054) desc ODRLOWBYTE */ + + struct + { + __IOM uint8_t LOWBYTE : 8; /*!< [7..0] desc LOWBYTE */ + } ODRLOWBYTE_f; + } ; + + union + { + __IOM uint8_t ODRHIGHBYTE; /*!< (@ 0x00000055) desc ODRHIGHBYTE */ + + struct + { + __IOM uint8_t HIGHBYTE : 8; /*!< [7..0] desc HIGHBYTE */ + } ODRHIGHBYTE_f; + } ; + }; + }; + + union + { + __IOM uint32_t BRR; /*!< (@ 0x00000058) desc BRR */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t BRR13 : 1; /*!< [13..13] desc BRR13 */ + __IOM uint32_t BRR14 : 1; /*!< [14..14] desc BRR14 */ + __IOM uint32_t BRR15 : 1; /*!< [15..15] desc BRR15 */ + } BRR_f; + } ; + + union + { + __IOM uint32_t BSRR; /*!< (@ 0x0000005C) desc BSRR */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t BSS13 : 1; /*!< [13..13] desc BSS13 */ + __IOM uint32_t BSS14 : 1; /*!< [14..14] desc BSS14 */ + __IOM uint32_t BSS15 : 1; /*!< [15..15] desc BSS15 */ + __IM uint32_t : 13; + __IOM uint32_t BRR13 : 1; /*!< [29..29] desc BRR13 */ + __IOM uint32_t BRR14 : 1; /*!< [30..30] desc BRR14 */ + __IOM uint32_t BRR15 : 1; /*!< [31..31] desc BRR15 */ + } BSRR_f; + } ; + + union + { + __IOM uint32_t TOG; /*!< (@ 0x00000060) desc TOG */ + + struct + { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } TOG_f; + } ; +} GPIOC_TypeDef; /*!< Size = 100 (0x64) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOF ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc GPIOF (GPIOF) + */ + +typedef struct /*!< (@ 0x48001400) GPIOF Structure */ +{ + + union + { + __IOM uint32_t DIR; /*!< (@ 0x00000000) desc DIR */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } DIR_f; + } ; + + union + { + __IOM uint32_t OPENDRAIN; /*!< (@ 0x00000004) desc OPENDRAIN */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } OPENDRAIN_f; + } ; + + union + { + __IOM uint32_t SPEED; /*!< (@ 0x00000008) desc SPEED */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } SPEED_f; + } ; + + union + { + __IOM uint32_t PDR; /*!< (@ 0x0000000C) desc PDR */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } PDR_f; + } ; + + union + { + __IOM uint32_t PUR; /*!< (@ 0x00000010) desc PUR */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } PUR_f; + } ; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t AFRL; /*!< (@ 0x00000018) desc AFRL */ + + struct + { + __IOM uint32_t AFR0 : 4; /*!< [3..0] desc AFR0 */ + __IOM uint32_t AFR1 : 4; /*!< [7..4] desc AFR1 */ + __IM uint32_t : 4; + __IOM uint32_t AFR3 : 4; /*!< [15..12] desc AFR3 */ + __IM uint32_t : 8; + __IOM uint32_t AFR6 : 4; /*!< [27..24] desc AFR6 */ + __IOM uint32_t AFR7 : 4; /*!< [31..28] desc AFR7 */ + } AFRL_f; + } ; + + union + { + __IOM uint32_t ANALOG; /*!< (@ 0x0000001C) desc ANALOG */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } ANALOG_f; + } ; + + union + { + __IOM uint32_t DRIVER; /*!< (@ 0x00000020) desc DRIVER */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } DRIVER_f; + } ; + + union + { + __IOM uint32_t RISEIE; /*!< (@ 0x00000024) Interrupt enable register */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } RISEIE_f; + } ; + + union + { + __IOM uint32_t FALLIE; /*!< (@ 0x00000028) Interrupt enable register */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } FALLIE_f; + } ; + + union + { + __IOM uint32_t HIGHIE; /*!< (@ 0x0000002C) Interrupt enable register */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } HIGHIE_f; + } ; + + union + { + __IOM uint32_t LOWIE; /*!< (@ 0x00000030) Interrupt enable register */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } LOWIE_f; + } ; + + union + { + __IOM uint32_t ISR; /*!< (@ 0x00000034) Interrupt status register */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } ISR_f; + } ; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000038) Interrupt flag clear register */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } ICR_f; + } ; + + union + { + __IOM uint32_t LOCK; /*!< (@ 0x0000003C) desc LOCK */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IM uint32_t : 8; + __OM uint32_t KEY : 16; /*!< [31..16] KEY = 0x5A5A */ + } LOCK_f; + } ; + + union + { + __IOM uint32_t FILTER; /*!< (@ 0x00000040) desc FILTER */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IM uint32_t : 8; + __IOM uint32_t FLTCLK : 3; /*!< [18..16] desc FLTCLK */ + } FILTER_f; + } ; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t IDR; /*!< (@ 0x00000050) desc IDR */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } IDR_f; + } ; + + union + { + union + { + __IOM uint32_t ODR; /*!< (@ 0x00000054) desc ODR */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } ODR_f; + } ; + + union + { + __IOM uint8_t ODRLOWBYTE; /*!< (@ 0x00000054) desc ODRLOWBYTE */ + + struct + { + __IOM uint8_t LOWBYTE : 8; /*!< [7..0] desc LOWBYTE */ + } ODRLOWBYTE_f; + } ; + }; + + union + { + __IOM uint32_t BRR; /*!< (@ 0x00000058) desc BRR */ + + struct + { + __IOM uint32_t BRR0 : 1; /*!< [0..0] desc BRR0 */ + __IOM uint32_t BRR1 : 1; /*!< [1..1] desc BRR1 */ + __IM uint32_t : 1; + __IOM uint32_t BRR3 : 1; /*!< [3..3] desc BRR3 */ + __IM uint32_t : 2; + __IOM uint32_t BRR6 : 1; /*!< [6..6] desc BRR6 */ + __IOM uint32_t BRR7 : 1; /*!< [7..7] desc BRR7 */ + } BRR_f; + } ; + + union + { + __IOM uint32_t BSRR; /*!< (@ 0x0000005C) desc BSRR */ + + struct + { + __IOM uint32_t BSS0 : 1; /*!< [0..0] desc BSS0 */ + __IOM uint32_t BSS1 : 1; /*!< [1..1] desc BSS1 */ + __IM uint32_t : 1; + __IOM uint32_t BSS3 : 1; /*!< [3..3] desc BSS3 */ + __IM uint32_t : 2; + __IOM uint32_t BSS6 : 1; /*!< [6..6] desc BSS6 */ + __IOM uint32_t BSS7 : 1; /*!< [7..7] desc BSS7 */ + } BSRR_f; + } ; + + union + { + __IOM uint32_t TOG; /*!< (@ 0x00000060) desc TOG */ + + struct + { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } TOG_f; + } ; +} GPIOF_TypeDef; /*!< Size = 100 (0x64) */ + + + +/* =========================================================================================================================== */ +/* ================ GTIM1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Timer 1 (GTIM1) + */ + +typedef struct /*!< (@ 0x40000400) GTIM1 Structure */ +{ + __IM uint32_t RESERVED[192]; + + union + { + __IOM uint32_t ARR; /*!< (@ 0x00000300) Auto Reload Register */ + + struct + { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } ARR_f; + } ; + + union + { + __IOM uint32_t CNT; /*!< (@ 0x00000304) Counter Register */ + + struct + { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + } CNT_f; + } ; + + union + { + __IOM uint32_t CMMR; /*!< (@ 0x00000308) Capture compare control Register */ + + struct + { + __IOM uint32_t CC1M : 4; /*!< [3..0] desc CC1M */ + __IOM uint32_t CC2M : 4; /*!< [7..4] desc CC2M */ + __IOM uint32_t CC3M : 4; /*!< [11..8] desc CC3M */ + __IOM uint32_t CC4M : 4; /*!< [15..12] desc CC4M */ + } CMMR_f; + } ; + + union + { + __IOM uint32_t ETR; /*!< (@ 0x0000030C) ETR Control register */ + + struct + { + __IM uint32_t : 4; + __IOM uint32_t ETRFLT : 3; /*!< [6..4] desc ETRFLT */ + } ETR_f; + } ; + + union + { + __IOM uint32_t CR0; /*!< (@ 0x00000310) Control register0 */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t MODE : 2; /*!< [2..1] desc MODE */ + __IOM uint32_t TRS : 1; /*!< [3..3] desc TRS */ + __IOM uint32_t POL : 1; /*!< [4..4] desc POL */ + __IOM uint32_t ONESHOT : 1; /*!< [5..5] desc ONESHOT */ + __IOM uint32_t TOGEN : 1; /*!< [6..6] desc TOGEN */ + __IOM uint32_t PRS : 4; /*!< [10..7] desc PRS */ + __IM uint32_t PRSSTATUS : 4; /*!< [14..11] desc PRSSTATUS */ + __IOM uint32_t ENCMODE : 2; /*!< [16..15] desc ENCMODE */ + __IOM uint32_t ENCRESET : 2; /*!< [18..17] desc ENCRESET */ + __IOM uint32_t ENCRELOAD : 2; /*!< [20..19] desc ENCRELOAD */ + } CR0_f; + } ; + + union + { + __IOM uint32_t IER; /*!< (@ 0x00000314) Interrupt enable register */ + + struct + { + __IOM uint32_t OV : 1; /*!< [0..0] desc OV */ + __IOM uint32_t TI : 1; /*!< [1..1] desc TI */ + __IOM uint32_t UD : 1; /*!< [2..2] desc UD */ + __IOM uint32_t CC1 : 1; /*!< [3..3] desc CC1 */ + __IOM uint32_t CC2 : 1; /*!< [4..4] desc CC2 */ + __IOM uint32_t CC3 : 1; /*!< [5..5] desc CC3 */ + __IOM uint32_t CC4 : 1; /*!< [6..6] desc CC4 */ + __IM uint32_t : 2; + __IOM uint32_t DIRCHANGE : 1; /*!< [9..9] desc DIRCHANGE */ + } IER_f; + } ; + + union + { + __IOM uint32_t ISR; /*!< (@ 0x00000318) Interrupt status register */ + + struct + { + __IOM uint32_t OV : 1; /*!< [0..0] desc OV */ + __IOM uint32_t TI : 1; /*!< [1..1] desc TI */ + __IOM uint32_t UD : 1; /*!< [2..2] desc UD */ + __IM uint32_t CC1 : 1; /*!< [3..3] desc CC1 */ + __IM uint32_t CC2 : 1; /*!< [4..4] desc CC2 */ + __IM uint32_t CC3 : 1; /*!< [5..5] desc CC3 */ + __IM uint32_t CC4 : 1; /*!< [6..6] desc CC4 */ + __IM uint32_t : 2; + __IM uint32_t DIRCHANGE : 1; /*!< [9..9] desc DIRCHANGE */ + __IM uint32_t DIR : 1; /*!< [10..10] desc DIR */ + } ISR_f; + } ; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x0000031C) Interrupt flag clear register */ + + struct + { + __IOM uint32_t OV : 1; /*!< [0..0] desc OV */ + __IOM uint32_t TI : 1; /*!< [1..1] desc TI */ + __IOM uint32_t UD : 1; /*!< [2..2] desc UD */ + __IOM uint32_t CC1 : 1; /*!< [3..3] desc CC1 */ + __IOM uint32_t CC2 : 1; /*!< [4..4] desc CC2 */ + __IOM uint32_t CC3 : 1; /*!< [5..5] desc CC3 */ + __IOM uint32_t CC4 : 1; /*!< [6..6] desc CC4 */ + __IM uint32_t : 2; + __IOM uint32_t DIRCHANGE : 1; /*!< [9..9] desc DIRCHANGE */ + } ICR_f; + } ; + + union + { + __IOM uint32_t CCR1; /*!< (@ 0x00000320) capture compare register */ + + struct + { + __IOM uint32_t CCR : 16; /*!< [15..0] desc CCR */ + } CCR1_f; + } ; + + union + { + __IOM uint32_t CCR2; /*!< (@ 0x00000324) capture compare register */ + + struct + { + __IOM uint32_t CCR : 16; /*!< [15..0] desc CCR */ + } CCR2_f; + } ; + + union + { + __IOM uint32_t CCR3; /*!< (@ 0x00000328) capture compare register */ + + struct + { + __IOM uint32_t CCR : 16; /*!< [15..0] desc CCR */ + } CCR3_f; + } ; + + union + { + __IOM uint32_t CCR4; /*!< (@ 0x0000032C) capture compare register */ + + struct + { + __IOM uint32_t CCR : 16; /*!< [15..0] desc CCR */ + } CCR4_f; + } ; + + union + { + __IOM uint32_t CR1; /*!< (@ 0x00000330) Control register1 */ + + struct + { + __IOM uint32_t CH1FLT : 3; /*!< [2..0] desc CH1FLT */ + __IOM uint32_t CH1POL : 1; /*!< [3..3] desc CH1POL */ + __IOM uint32_t CH2FLT : 3; /*!< [6..4] desc CH2FLT */ + __IOM uint32_t CH2POL : 1; /*!< [7..7] desc CH2POL */ + __IOM uint32_t CH3FLT : 3; /*!< [10..8] desc CH3FLT */ + __IOM uint32_t CH3POL : 1; /*!< [11..11] desc CH3POL */ + __IOM uint32_t CH4FLT : 3; /*!< [14..12] desc CH4FLT */ + __IOM uint32_t CH4POL : 1; /*!< [15..15] desc CH4POL */ + } CR1_f; + } ; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t DMA; /*!< (@ 0x00000340) DMA Control register */ + + struct + { + __IOM uint32_t OV : 1; /*!< [0..0] desc OV */ + __IOM uint32_t TRS : 1; /*!< [1..1] desc TRS */ + __IOM uint32_t CC1 : 1; /*!< [2..2] desc CC1 */ + __IOM uint32_t CC2 : 1; /*!< [3..3] desc CC2 */ + __IOM uint32_t CC3 : 1; /*!< [4..4] desc CC3 */ + __IOM uint32_t CC4 : 1; /*!< [5..5] desc CC4 */ + } DMA_f; + } ; +} GTIM_TypeDef; /*!< Size = 836 (0x344) */ + + + +/* =========================================================================================================================== */ +/* ================ I2C1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc I2C1 (I2C1) + */ + +typedef struct /*!< (@ 0x40005400) I2C1 Structure */ +{ + + union + { + __IOM uint32_t BRREN; /*!< (@ 0x00000000) desc BRREN */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + } BRREN_f; + } ; + + union + { + __IOM uint32_t BRR; /*!< (@ 0x00000004) desc BRR */ + + struct + { + __IOM uint32_t BRR : 8; /*!< [7..0] fSCL = fPCLK / 8 / (BRR+1) */ + } BRR_f; + } ; + + union + { + __IOM uint32_t CR; /*!< (@ 0x00000008) Control register */ + + struct + { + __IOM uint32_t FLT : 1; /*!< [0..0] desc FLT */ + __IM uint32_t : 1; + __IOM uint32_t AA : 1; /*!< [2..2] desc AA */ + __IOM uint32_t SI : 1; /*!< [3..3] desc SI */ + __IOM uint32_t STO : 1; /*!< [4..4] desc STO */ + __IOM uint32_t STA : 1; /*!< [5..5] desc STA */ + __IOM uint32_t EN : 1; /*!< [6..6] desc EN */ + } CR_f; + } ; + + union + { + __IOM uint32_t DR; /*!< (@ 0x0000000C) Data register */ + + struct + { + __IOM uint32_t DR : 8; /*!< [7..0] desc DR */ + } DR_f; + } ; + + union + { + __IOM uint32_t ADDR0; /*!< (@ 0x00000010) Slave Addrress0 */ + + struct + { + __IOM uint32_t GC : 1; /*!< [0..0] desc GC */ + __IOM uint32_t ADDR0 : 7; /*!< [7..1] desc ADDR0 */ + } ADDR0_f; + } ; + + union + { + __IM uint32_t STAT; /*!< (@ 0x00000014) Status register */ + + struct + { + __IM uint32_t STAT : 8; /*!< [7..0] desc STAT */ + } STAT_f; + } ; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t ADDR1; /*!< (@ 0x00000020) Slave Addrress1 */ + + struct + { + __IM uint32_t : 1; + __IOM uint32_t ADDR1 : 7; /*!< [7..1] desc ADDR1 */ + } ADDR1_f; + } ; + + union + { + __IOM uint32_t ADDR2; /*!< (@ 0x00000024) Slave Addrress2 */ + + struct + { + __IM uint32_t : 1; + __IOM uint32_t ADDR2 : 7; /*!< [7..1] desc ADDR2 */ + } ADDR2_f; + } ; + + union + { + __IM uint32_t MATCH; /*!< (@ 0x00000028) Slave Addrress match flag */ + + struct + { + __IM uint32_t ADDR0 : 1; /*!< [0..0] desc ADDR0 */ + __IM uint32_t ADDR1 : 1; /*!< [1..1] desc ADDR1 */ + __IM uint32_t ADDR2 : 1; /*!< [2..2] desc ADDR2 */ + } MATCH_f; + } ; +} I2C_TypeDef; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ IWDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc IWDT (IWDT) + */ + +typedef struct /*!< (@ 0x40003000) IWDT Structure */ +{ + + union + { + __OM uint32_t KR; /*!< (@ 0x00000000) Key register */ + + struct + { + __OM uint32_t KR : 16; /*!< [15..0] desc KR */ + } KR_f; + } ; + + union + { + __IOM uint32_t CR; /*!< (@ 0x00000004) Control register */ + + struct + { + __IOM uint32_t PRS : 3; /*!< [2..0] desc PRS */ + __IOM uint32_t ACTION : 1; /*!< [3..3] desc ACTION */ + __IOM uint32_t IE : 1; /*!< [4..4] desc IE */ + __IOM uint32_t PAUSE : 1; /*!< [5..5] desc PAUSE */ + } CR_f; + } ; + + union + { + __IOM uint32_t ARR; /*!< (@ 0x00000008) Auto reload register */ + + struct + { + __IOM uint32_t ARR : 12; /*!< [11..0] desc ARR */ + } ARR_f; + } ; + + union + { + __IOM uint32_t SR; /*!< (@ 0x0000000C) Status register */ + + struct + { + __IM uint32_t CRF : 1; /*!< [0..0] desc CRF */ + __IM uint32_t ARRF : 1; /*!< [1..1] desc ARRF */ + __IM uint32_t WINRF : 1; /*!< [2..2] desc WINRF */ + __IOM uint32_t OV : 1; /*!< [3..3] desc OV */ + __IM uint32_t RUN : 1; /*!< [4..4] desc RUN */ + __IM uint32_t RELOAD : 1; /*!< [5..5] desc RELOAD */ + } SR_f; + } ; + + union + { + __IOM uint32_t WINR; /*!< (@ 0x00000010) Window register */ + + struct + { + __IOM uint32_t WINR : 12; /*!< [11..0] desc WINR */ + } WINR_f; + } ; + __IM uint32_t RESERVED[4]; + + union + { + __IM uint32_t CNT; /*!< (@ 0x00000024) counter */ + + struct + { + __IM uint32_t CNT : 12; /*!< [11..0] desc CNT */ + } CNT_f; + } ; +} IWDT_TypeDef; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ LVD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc LVD (LVD) + */ + +typedef struct /*!< (@ 0x40012A80) LVD Structure */ +{ + + union + { + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control register0 */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t ACTION : 1; /*!< [1..1] desc ACTION */ + __IOM uint32_t SOURCE : 2; /*!< [3..2] desc SOURCE */ + __IOM uint32_t VTH : 4; /*!< [7..4] desc VTH */ + __IM uint32_t : 1; + __IOM uint32_t IE : 1; /*!< [9..9] desc IE */ + } CR0_f; + } ; + + union + { + __IOM uint32_t CR1; /*!< (@ 0x00000004) Control register1 */ + + struct + { + __IOM uint32_t FLTEN : 1; /*!< [0..0] desc FLTEN */ + __IOM uint32_t FLTTIME : 3; /*!< [3..1] desc FLTTIME */ + __IOM uint32_t FLTCLK : 1; /*!< [4..4] desc FLTCLK */ + __IOM uint32_t RISE : 1; /*!< [5..5] desc RISE */ + __IOM uint32_t FALL : 1; /*!< [6..6] desc FALL */ + __IOM uint32_t LEVEL : 1; /*!< [7..7] desc LEVEL */ + } CR1_f; + } ; + + union + { + __IOM uint32_t SR; /*!< (@ 0x00000008) status register */ + + struct + { + __IOM uint32_t INTF : 1; /*!< [0..0] desc INTF */ + __IM uint32_t FLTV : 1; /*!< [1..1] desc FLTV */ + } SR_f; + } ; +} LVD_TypeDef; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ RAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc RAM (RAM) + */ + +typedef struct /*!< (@ 0x40022400) RAM Structure */ +{ + + union + { + __IOM uint32_t IER; /*!< (@ 0x00000000) Interrupt enable register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t PARITY : 1; /*!< [1..1] desc PARITY */ + } IER_f; + } ; + + union + { + __IM uint32_t ADDR; /*!< (@ 0x00000004) Parity check error addr register */ + + struct + { + __IM uint32_t ADDR : 32; /*!< [31..0] desc ADDR */ + } ADDR_f; + } ; + + union + { + __IM uint32_t ISR; /*!< (@ 0x00000008) Interrupt flag register */ + + struct + { + __IM uint32_t PARITY : 1; /*!< [0..0] desc PARITY */ + } ISR_f; + } ; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x0000000C) Interrupt flag clear register */ + + struct + { + __IOM uint32_t PARITY : 1; /*!< [0..0] desc PARITY */ + } ICR_f; + } ; +} RAM_TypeDef; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc RTC (RTC) + */ + +typedef struct /*!< (@ 0x40002800) RTC Structure */ +{ + + union + { + __OM uint32_t KEY; /*!< (@ 0x00000000) desc KEY */ + + struct + { + __OM uint32_t KEY : 8; /*!< [7..0] Key = 0xCA - 0x53 */ + } KEY_f; + } ; + + union + { + __IOM uint32_t CR0; /*!< (@ 0x00000004) Control register0 */ + + struct + { + __IOM uint32_t INTERVAL : 3; /*!< [2..0] desc INTERVAL */ + __IOM uint32_t H24 : 1; /*!< [3..3] desc H24 */ + __IM uint32_t : 1; + __IOM uint32_t RTC1HZ : 2; /*!< [6..5] desc RTC1HZ */ + __IOM uint32_t START : 1; /*!< [7..7] desc START */ + } CR0_f; + } ; + + union + { + __IOM uint32_t CR1; /*!< (@ 0x00000008) Control register1 */ + + struct + { + __IOM uint32_t ACCESS : 1; /*!< [0..0] desc ACCESS */ + __IM uint32_t WINDOW : 1; /*!< [1..1] desc WINDOW */ + __IM uint32_t : 6; + __IOM uint32_t SOURCE : 3; /*!< [10..8] desc SOURCE */ + } CR1_f; + } ; + + union + { + __IOM uint32_t CR2; /*!< (@ 0x0000000C) Control register2 */ + + struct + { + __IOM uint32_t AWTSRC : 3; /*!< [2..0] desc AWTSRC */ + __IOM uint32_t TAMPEDGE : 1; /*!< [3..3] desc TAMPEDGE */ + __IOM uint32_t RTCOUT : 2; /*!< [5..4] desc RTCOUT */ + __IOM uint32_t TAMPEN : 1; /*!< [6..6] desc TAMPEN */ + __IOM uint32_t AWTEN : 1; /*!< [7..7] desc AWTEN */ + __IM uint32_t : 1; + __IOM uint32_t ALARMAEN : 1; /*!< [9..9] desc ALARMAEN */ + __IOM uint32_t ALARMBEN : 1; /*!< [10..10] desc ALARMBEN */ + } CR2_f; + } ; + + union + { + __IOM uint32_t COMPEN; /*!< (@ 0x00000010) Compen register */ + + struct + { + __IOM uint32_t COMP : 12; /*!< [11..0] desc COMP */ + __IOM uint32_t STEP : 2; /*!< [13..12] desc STEP */ + __IOM uint32_t SIGN : 1; /*!< [14..14] desc SIGN */ + __IOM uint32_t EN : 1; /*!< [15..15] desc EN */ + __IOM uint32_t FREQ : 4; /*!< [19..16] desc FREQ */ + } COMPEN_f; + } ; + + union + { + __IOM uint32_t DATE; /*!< (@ 0x00000014) Time.Second register */ + + struct + { + __IOM uint32_t DAY : 8; /*!< [7..0] desc DAY */ + __IOM uint32_t MONTH : 8; /*!< [15..8] desc MONTH */ + __IOM uint32_t YEAR : 8; /*!< [23..16] desc YEAR */ + __IOM uint32_t WEEK : 3; /*!< [26..24] desc WEEK */ + } DATE_f; + } ; + + union + { + __IOM uint32_t TIME; /*!< (@ 0x00000018) Time.Second register */ + + struct + { + __IOM uint32_t SECOND : 7; /*!< [6..0] desc SECOND */ + __IM uint32_t : 1; + __IOM uint32_t MINUTE : 7; /*!< [14..8] desc MINUTE */ + __IM uint32_t : 1; + __IOM uint32_t HOUR : 6; /*!< [21..16] desc HOUR */ + } TIME_f; + } ; + + union + { + __IOM uint32_t ALARMA; /*!< (@ 0x0000001C) Alarm - A */ + + struct + { + __IOM uint32_t SECOND : 7; /*!< [6..0] desc SECOND */ + __IOM uint32_t SECONDEN : 1; /*!< [7..7] desc SECONDRN */ + __IOM uint32_t MINUTE : 7; /*!< [14..8] desc MINUTE */ + __IOM uint32_t MINUTEEN : 1; /*!< [15..15] desc MINUTEEM */ + __IOM uint32_t HOUR : 6; /*!< [21..16] desc HOUR */ + __IM uint32_t : 1; + __IOM uint32_t HOURRN : 1; /*!< [23..23] desc HOURMEN */ + __IOM uint32_t WEEKMASK : 7; /*!< [30..24] desc WEEKMASK */ + } ALARMA_f; + } ; + + union + { + __IOM uint32_t ALARMB; /*!< (@ 0x00000020) Alarm - B */ + + struct + { + __IOM uint32_t SECOND : 7; /*!< [6..0] desc SECOND */ + __IOM uint32_t SECONDEN : 1; /*!< [7..7] desc SECONDEN */ + __IOM uint32_t MINUTE : 7; /*!< [14..8] desc MINUTE */ + __IOM uint32_t MINUTEEN : 1; /*!< [15..15] desc MINUTEEN */ + __IOM uint32_t HOUR : 6; /*!< [21..16] desc HOUR */ + __IM uint32_t : 1; + __IOM uint32_t HOUREN : 1; /*!< [23..23] desc HOUREN */ + __IOM uint32_t WEEKMASK : 7; /*!< [30..24] desc WEEKMASK */ + } ALARMB_f; + } ; + + union + { + __IOM uint32_t TAMPDATE; /*!< (@ 0x00000024) desc TAMPDATE */ + + struct + { + __IOM uint32_t DAY : 6; /*!< [5..0] desc DAY */ + __IM uint32_t : 2; + __IOM uint32_t MONTH : 5; /*!< [12..8] desc MONTH */ + __IOM uint32_t WEEK : 3; /*!< [15..13] desc WEEK */ + } TAMPDATE_f; + } ; + + union + { + __IOM uint32_t TAMPTIME; /*!< (@ 0x00000028) desc TAMPTIME */ + + struct + { + __IOM uint32_t SECOND : 7; /*!< [6..0] desc SECOND */ + __IM uint32_t : 1; + __IOM uint32_t MINUTE : 7; /*!< [14..8] desc MINUTE */ + __IM uint32_t : 1; + __IOM uint32_t HOUR : 6; /*!< [21..16] desc HOUR */ + } TAMPTIME_f; + } ; + + union + { + __IOM uint32_t AWTARR; /*!< (@ 0x0000002C) Auto Wakeup Timer Auto Reload Register */ + + struct + { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } AWTARR_f; + } ; + + union + { + __IOM uint32_t IER; /*!< (@ 0x00000030) Interrupt enable register */ + + struct + { + __IOM uint32_t ALARMA : 1; /*!< [0..0] desc ALARMA */ + __IOM uint32_t ALARMB : 1; /*!< [1..1] desc ALARMB */ + __IOM uint32_t AWTIMER : 1; /*!< [2..2] desc AWTIMER */ + __IOM uint32_t TAMP : 1; /*!< [3..3] desc TAMP */ + __IOM uint32_t TAMPOV : 1; /*!< [4..4] desc TAMPOV */ + __IM uint32_t : 1; + __IOM uint32_t INTERVAL : 1; /*!< [6..6] desc INTERVAL */ + } IER_f; + } ; + + union + { + __IM uint32_t ISR; /*!< (@ 0x00000034) Interrupt status register */ + + struct + { + __IM uint32_t ALARMA : 1; /*!< [0..0] desc ALARMA */ + __IM uint32_t ALARMB : 1; /*!< [1..1] desc ALARMB */ + __IM uint32_t AWTIMER : 1; /*!< [2..2] desc AWTIMER */ + __IM uint32_t TAMP : 1; /*!< [3..3] desc TAMP */ + __IM uint32_t TAMPOV : 1; /*!< [4..4] desc TAMPOV */ + __IM uint32_t : 1; + __IM uint32_t INTERVAL : 1; /*!< [6..6] desc INTERVAL */ + } ISR_f; + } ; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000038) Interrupt flag clear register */ + + struct + { + __IOM uint32_t ALARMA : 1; /*!< [0..0] desc ALARMA */ + __IOM uint32_t ALARMB : 1; /*!< [1..1] desc ALARMB */ + __IOM uint32_t AWTIMER : 1; /*!< [2..2] desc AWTIMER */ + __IOM uint32_t TAMP : 1; /*!< [3..3] desc TAMP */ + __IOM uint32_t TAMPOV : 1; /*!< [4..4] desc TAMPOV */ + __IM uint32_t : 1; + __IOM uint32_t INTERVAL : 1; /*!< [6..6] desc INTERVAL */ + } ICR_f; + } ; +} RTC_TypeDef; /*!< Size = 60 (0x3c) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc SPI1 (SPI1) + */ + +typedef struct /*!< (@ 0x40013000) SPI1 Structure */ +{ + + union + { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control register1 */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] desc CPHA */ + __IOM uint32_t CPOL : 1; /*!< [1..1] desc CPOL */ + __IOM uint32_t MSTR : 1; /*!< [2..2] desc MSTR */ + __IOM uint32_t BR : 3; /*!< [5..3] desc BR */ + __IOM uint32_t EN : 1; /*!< [6..6] desc EN */ + __IOM uint32_t LSBF : 1; /*!< [7..7] desc LSBF */ + __IOM uint32_t SMP : 1; /*!< [8..8] desc SMP */ + __IOM uint32_t SSM : 1; /*!< [9..9] desc SSM */ + __IOM uint32_t WIDTH : 4; /*!< [13..10] desc WIDTH */ + __IOM uint32_t MODE : 2; /*!< [15..14] desc MODE */ + __IOM uint32_t DMARX : 1; /*!< [16..16] desc DMARX */ + __IOM uint32_t DMATX : 1; /*!< [17..17] desc DMATX */ + __IOM uint32_t MISOHD : 1; /*!< [18..18] desc MISOHD */ + } CR1_f; + } ; + + union + { + __IOM uint32_t IER; /*!< (@ 0x00000004) Interrupt enable register */ + + struct + { + __IOM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IOM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IOM uint32_t SSF : 1; /*!< [2..2] desc SSF */ + __IOM uint32_t SSR : 1; /*!< [3..3] desc SSR */ + __IOM uint32_t UD : 1; /*!< [4..4] desc UD */ + __IOM uint32_t OV : 1; /*!< [5..5] desc OV */ + __IOM uint32_t SSERR : 1; /*!< [6..6] desc SSERR */ + __IOM uint32_t MODF : 1; /*!< [7..7] desc MODF */ + } IER_f; + } ; + + union + { + __IOM uint32_t CR2; /*!< (@ 0x00000008) Control register2 */ + + struct + { + __IOM uint32_t HDOE : 1; /*!< [0..0] desc HDOE */ + } CR2_f; + } ; + + union + { + __IOM uint32_t SSI; /*!< (@ 0x0000000C) Slave slect register */ + + struct + { + __IOM uint32_t SSI : 1; /*!< [0..0] desc SSI */ + } SSI_f; + } ; + + union + { + __IM uint32_t ISR; /*!< (@ 0x00000010) Interrupt status register */ + + struct + { + __IM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IM uint32_t SSF : 1; /*!< [2..2] desc SSF */ + __IM uint32_t SSR : 1; /*!< [3..3] desc SSR */ + __IM uint32_t UD : 1; /*!< [4..4] desc UD */ + __IM uint32_t OV : 1; /*!< [5..5] desc OV */ + __IM uint32_t SSERR : 1; /*!< [6..6] desc SSERR */ + __IM uint32_t MODF : 1; /*!< [7..7] desc MODF */ + __IM uint32_t BUSY : 1; /*!< [8..8] desc BUSY */ + __IM uint32_t SSLVL : 1; /*!< [9..9] desc SSLVL */ + } ISR_f; + } ; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000014) Interrupt flag clear register */ + + struct + { + __IOM uint32_t FLUSH : 1; /*!< [0..0] desc FLUSH */ + __IOM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IOM uint32_t SSF : 1; /*!< [2..2] desc SSF */ + __IOM uint32_t SSR : 1; /*!< [3..3] desc SSR */ + __IOM uint32_t UD : 1; /*!< [4..4] desc UD */ + __IOM uint32_t OV : 1; /*!< [5..5] desc OV */ + __IOM uint32_t SSERR : 1; /*!< [6..6] desc SSERR */ + __IOM uint32_t MODF : 1; /*!< [7..7] desc MODF */ + } ICR_f; + } ; + + union + { + __IOM uint32_t DR; /*!< (@ 0x00000018) Data register */ + + struct + { + __IOM uint32_t DR : 16; /*!< [15..0] desc DR */ + } DR_f; + } ; +} SPI_TypeDef; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Ctrl (SYSCTRL) + */ + +typedef struct /*!< (@ 0x40010000) SYSCTRL Structure */ +{ + + union + { + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control Reg0 */ + + struct + { + __IOM uint32_t SYSCLK : 3; /*!< [2..0] desc SYSCLK */ + __IOM uint32_t PCLKPRS : 2; /*!< [4..3] desc PCLKPRS */ + __IOM uint32_t HCLKPRS : 3; /*!< [7..5] desc HCLKPRS */ + __IM uint32_t : 8; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR0_f; + } ; + + union + { + __IOM uint32_t CR1; /*!< (@ 0x00000004) Control Reg1 */ + + struct + { + __IOM uint32_t HSIEN : 1; /*!< [0..0] desc HSIEN */ + __IOM uint32_t HSEEN : 1; /*!< [1..1] desc HSEEN */ + __IOM uint32_t PLLEN : 1; /*!< [2..2] desc PLLEN */ + __IOM uint32_t LSIEN : 1; /*!< [3..3] desc LSIEN */ + __IOM uint32_t LSEEN : 1; /*!< [4..4] desc LSEEN */ + __IOM uint32_t LSELOCK : 1; /*!< [5..5] desc LSELOCK */ + __IOM uint32_t LSECCS : 1; /*!< [6..6] desc LSECCS */ + __IOM uint32_t HSECCS : 1; /*!< [7..7] desc HSECCS */ + __IOM uint32_t CLKCCS : 1; /*!< [8..8] desc CLKCCS */ + __IM uint32_t : 7; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR1_f; + } ; + + union + { + __IOM uint32_t CR2; /*!< (@ 0x00000008) Control Reg2 */ + + struct + { + __IM uint32_t : 1; + __IOM uint32_t SWDIO : 1; /*!< [1..1] desc SWDIO */ + __IOM uint32_t LOCKUP : 1; /*!< [2..2] desc LOCKUP */ + __IOM uint32_t WAKEUPCLK : 1; /*!< [3..3] desc WAKEUPCLK */ + __IM uint32_t : 12; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR2_f; + } ; + + union + { + __IOM uint32_t IER; /*!< (@ 0x0000000C) Interupt Enable Reg */ + + struct + { + __IOM uint32_t HSIRDY : 1; /*!< [0..0] desc HSIRDY */ + __IOM uint32_t HSERDY : 1; /*!< [1..1] desc HSERDY */ + __IOM uint32_t PLLRDY : 1; /*!< [2..2] desc PLLRDY */ + __IOM uint32_t LSIRDY : 1; /*!< [3..3] desc LSIRDY */ + __IOM uint32_t LSERDY : 1; /*!< [4..4] desc LSERDY */ + __IOM uint32_t LSEFAIL : 1; /*!< [5..5] desc LSEFAIL */ + __IOM uint32_t HSEFAIL : 1; /*!< [6..6] desc HSEFAIL */ + __IOM uint32_t LSEFAULT : 1; /*!< [7..7] desc LSEFAULT */ + __IOM uint32_t HSEFAULT : 1; /*!< [8..8] desc HSEFAULT */ + __IM uint32_t : 7; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } IER_f; + } ; + + union + { + __IM uint32_t ISR; /*!< (@ 0x00000010) Interupt Status Reg */ + + struct + { + __IM uint32_t HSIRDY : 1; /*!< [0..0] desc HSIRDY */ + __IM uint32_t HSERDY : 1; /*!< [1..1] desc HSERDY */ + __IM uint32_t PLLRDY : 1; /*!< [2..2] desc PLLRDY */ + __IM uint32_t LSIRDY : 1; /*!< [3..3] desc LSIRDY */ + __IM uint32_t LSERDY : 1; /*!< [4..4] desc LSERDY */ + __IM uint32_t LSEFAIL : 1; /*!< [5..5] desc LSEFAIL */ + __IM uint32_t HSEFAIL : 1; /*!< [6..6] desc HSEFAIL */ + __IM uint32_t LSEFAULT : 1; /*!< [7..7] desc LSEFAULT */ + __IM uint32_t HSEFAULT : 1; /*!< [8..8] desc HSEFAULT */ + __IM uint32_t : 2; + __IM uint32_t HSISTABLE : 1; /*!< [11..11] desc HSISTABLE */ + __IM uint32_t HSESTABLE : 1; /*!< [12..12] desc HSESTABLE */ + __IM uint32_t PLLSTABLE : 1; /*!< [13..13] desc PLLSTABLE */ + __IM uint32_t LSISTABLE : 1; /*!< [14..14] desc LSISTABLE */ + __IM uint32_t LSESTABLE : 1; /*!< [15..15] desc LSESTABLE */ + } ISR_f; + } ; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000014) Interupt Clear Reg */ + + struct + { + __IOM uint32_t HSIRDY : 1; /*!< [0..0] desc HSIRDY */ + __IOM uint32_t HSERDY : 1; /*!< [1..1] desc HSERDY */ + __IOM uint32_t PLLRDY : 1; /*!< [2..2] desc PLLRDY */ + __IOM uint32_t LSIRDY : 1; /*!< [3..3] desc LSIRDY */ + __IOM uint32_t LSERDY : 1; /*!< [4..4] desc LSERDY */ + __IOM uint32_t LSEFAIL : 1; /*!< [5..5] desc LSEFAIL */ + __IOM uint32_t HSEFAIL : 1; /*!< [6..6] desc HSEFAIL */ + __IOM uint32_t LSEFAULT : 1; /*!< [7..7] desc LSEFAULT */ + __IOM uint32_t HSEFAULT : 1; /*!< [8..8] desc HSEFAULT */ + } ICR_f; + } ; + + union + { + __IOM uint32_t HSI; /*!< (@ 0x00000018) HSI Control Reg */ + + struct + { + __IOM uint32_t TRIM : 11; /*!< [10..0] desc TRIM */ + __IOM uint32_t DIV : 4; /*!< [14..11] desc DIV */ + __IM uint32_t STABLE : 1; /*!< [15..15] desc STABLE */ + } HSI_f; + } ; + + union + { + __IOM uint32_t HSE; /*!< (@ 0x0000001C) HSE Control Reg */ + + struct + { + __IOM uint32_t DRIVER : 2; /*!< [1..0] desc DRIVER */ + __IOM uint32_t FREQRANGE : 2; /*!< [3..2] desc FREQRANGE */ + __IOM uint32_t WAITCYCLE : 2; /*!< [5..4] desc WAITCYCLE */ + __IOM uint32_t MODE : 1; /*!< [6..6] desc MODE */ + __IOM uint32_t FLT : 1; /*!< [7..7] desc FLT */ + __IOM uint32_t DETCNT : 11; /*!< [18..8] desc DETCNT */ + __IM uint32_t STABLE : 1; /*!< [19..19] desc STABLE */ + } HSE_f; + } ; + + union + { + __IOM uint32_t LSI; /*!< (@ 0x00000020) LSI Control Reg */ + + struct + { + __IOM uint32_t TRIM : 10; /*!< [9..0] desc TRIM */ + __IOM uint32_t WAITCYCLE : 2; /*!< [11..10] desc WAITCYCLE */ + __IM uint32_t : 3; + __IM uint32_t STABLE : 1; /*!< [15..15] desc STABLE */ + } LSI_f; + } ; + + union + { + __IOM uint32_t LSE; /*!< (@ 0x00000024) LSE Control Reg */ + + struct + { + __IOM uint32_t DRIVER : 2; /*!< [1..0] desc DRIVER */ + __IOM uint32_t AMP : 2; /*!< [3..2] desc AMP */ + __IOM uint32_t WAITCYCLE : 2; /*!< [5..4] desc WAITCYCLE */ + __IOM uint32_t MODE : 1; /*!< [6..6] desc MODE */ + __IM uint32_t : 8; + __IM uint32_t STABLE : 1; /*!< [15..15] desc STABLE */ + } LSE_f; + } ; + + union + { + __IOM uint32_t PLL; /*!< (@ 0x00000028) PLL Control Reg */ + + struct + { + __IOM uint32_t SOURCE : 2; /*!< [1..0] desc SOURCE */ + __IOM uint32_t FREQIN : 2; /*!< [3..2] desc FREQIN */ + __IOM uint32_t MUL : 5; /*!< [8..4] desc MUL */ + __IOM uint32_t FREQOUT : 3; /*!< [11..9] desc FREQOUT */ + __IOM uint32_t WAITCYCLE : 3; /*!< [14..12] desc WAITCYCLE */ + __IM uint32_t STABLE : 1; /*!< [15..15] desc STABLE */ + } PLL_f; + } ; + + union + { + __IOM uint32_t DEBUG; /*!< (@ 0x0000002C) Debug Control Reg */ + + struct + { + __IOM uint32_t ATIM : 1; /*!< [0..0] desc ATIM */ + __IOM uint32_t GTIM1 : 1; /*!< [1..1] desc GTIM1 */ + __IOM uint32_t GTIM2 : 1; /*!< [2..2] desc GTIM2 */ + __IOM uint32_t GTIM3 : 1; /*!< [3..3] desc GTIM3 */ + __IOM uint32_t GTIM4 : 1; /*!< [4..4] desc GTIM4 */ + __IOM uint32_t BTIM123 : 1; /*!< [5..5] desc BTIM123 */ + __IOM uint32_t AWT : 1; /*!< [6..6] desc AWT */ + __IM uint32_t : 1; + __IOM uint32_t RTC : 1; /*!< [8..8] desc RTC */ + __IOM uint32_t IWDT : 1; /*!< [9..9] desc IWDT */ + __IOM uint32_t WWDT : 1; /*!< [10..10] desc WWDT */ + } DEBUG_f; + } ; + + union + { + __IOM uint32_t AHBEN; /*!< (@ 0x00000030) AHB Clock Control Reg */ + + struct + { + __IOM uint32_t DMA : 1; /*!< [0..0] desc DMA */ + __IOM uint32_t FLASH : 1; /*!< [1..1] desc FLASH */ + __IOM uint32_t CRC : 1; /*!< [2..2] desc CRC */ + __IM uint32_t : 1; + __IOM uint32_t GPIOA : 1; /*!< [4..4] desc GPIOA */ + __IOM uint32_t GPIOB : 1; /*!< [5..5] desc GPIOB */ + __IOM uint32_t GPIOC : 1; /*!< [6..6] desc GPIOC */ + __IM uint32_t : 2; + __IOM uint32_t GPIOF : 1; /*!< [9..9] desc GPIOF */ + } AHBEN_f; + } ; + + union + { + __IOM uint32_t APBEN2; /*!< (@ 0x00000034) APB Clock Control Reg2 */ + + struct + { + __IM uint32_t : 2; + __IOM uint32_t ADC : 1; /*!< [2..2] desc ADC */ + __IM uint32_t : 1; + __IOM uint32_t VC : 1; /*!< [4..4] desc VC */ + __IM uint32_t : 2; + __IOM uint32_t ATIM : 1; /*!< [7..7] desc ATIM */ + __IOM uint32_t SPI1 : 1; /*!< [8..8] desc SPI1 */ + __IOM uint32_t UART1 : 1; /*!< [9..9] desc UART1 */ + __IOM uint32_t GTIM3 : 1; /*!< [10..10] desc GTIM3 */ + __IOM uint32_t GTIM4 : 1; /*!< [11..11] desc GTIM4 */ + __IOM uint32_t BTIM : 1; /*!< [12..12] desc BTIM */ + __IOM uint32_t AWT : 1; /*!< [13..13] desc AWT */ + } APBEN2_f; + } ; + + union + { + __IOM uint32_t APBEN1; /*!< (@ 0x00000038) APB Clock Control Reg1 */ + + struct + { + __IM uint32_t : 1; + __IOM uint32_t GTIM1 : 1; /*!< [1..1] desc GTIM1 */ + __IOM uint32_t GTIM2 : 1; /*!< [2..2] desc GTIM2 */ + __IOM uint32_t RTC : 1; /*!< [3..3] desc RTC */ + __IOM uint32_t WWDT : 1; /*!< [4..4] desc WWDT */ + __IOM uint32_t IWDT : 1; /*!< [5..5] desc IWDT */ + __IOM uint32_t SPI2 : 1; /*!< [6..6] desc SPI2 */ + __IOM uint32_t UART2 : 1; /*!< [7..7] desc UART2 */ + __IOM uint32_t UART3 : 1; /*!< [8..8] desc UART3 */ + __IM uint32_t : 2; + __IOM uint32_t I2C1 : 1; /*!< [11..11] desc I2C1 */ + __IOM uint32_t I2C2 : 1; /*!< [12..12] desc I2C2 */ + } APBEN1_f; + } ; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t AHBRST; /*!< (@ 0x00000040) AHB Reset Control Reg */ + + struct + { + __IOM uint32_t DMA : 1; /*!< [0..0] desc DMA */ + __IOM uint32_t FLASH : 1; /*!< [1..1] desc FLASH */ + __IOM uint32_t CRC : 1; /*!< [2..2] desc CRC */ + __IM uint32_t : 1; + __IOM uint32_t GPIOA : 1; /*!< [4..4] desc GPIOA */ + __IOM uint32_t GPIOB : 1; /*!< [5..5] desc GPIOB */ + __IOM uint32_t GPIOC : 1; /*!< [6..6] desc GPIOC */ + __IM uint32_t : 2; + __IOM uint32_t GPIOF : 1; /*!< [9..9] desc GPIOF */ + } AHBRST_f; + } ; + + union + { + __IOM uint32_t APBRST2; /*!< (@ 0x00000044) APB Reset Control Reg2 */ + + struct + { + __IM uint32_t : 2; + __IOM uint32_t ADC : 1; /*!< [2..2] desc ADC */ + __IM uint32_t : 1; + __IOM uint32_t VC : 1; /*!< [4..4] desc VC */ + __IM uint32_t : 2; + __IOM uint32_t ATIM : 1; /*!< [7..7] desc ATIM */ + __IOM uint32_t SPI1 : 1; /*!< [8..8] desc SPI1 */ + __IOM uint32_t UART1 : 1; /*!< [9..9] desc UART1 */ + __IOM uint32_t GTIM3 : 1; /*!< [10..10] desc GTIM3 */ + __IOM uint32_t GTIM4 : 1; /*!< [11..11] desc GTIM4 */ + __IOM uint32_t BTIM : 1; /*!< [12..12] desc BTIM */ + __IOM uint32_t AWT : 1; /*!< [13..13] desc AWT */ + } APBRST2_f; + } ; + + union + { + __IOM uint32_t APBRST1; /*!< (@ 0x00000048) APB Reset Control Reg1 */ + + struct + { + __IM uint32_t : 1; + __IOM uint32_t GTIM1 : 1; /*!< [1..1] desc GTIM1 */ + __IOM uint32_t GTIM2 : 1; /*!< [2..2] desc GTIM2 */ + __IOM uint32_t RTC : 1; /*!< [3..3] desc RTC */ + __IOM uint32_t WWDT : 1; /*!< [4..4] desc WWDT */ + __IOM uint32_t IWDT : 1; /*!< [5..5] desc IWDT */ + __IOM uint32_t SPI2 : 1; /*!< [6..6] desc SPI2 */ + __IOM uint32_t UART2 : 1; /*!< [7..7] desc UART2 */ + __IOM uint32_t UART3 : 1; /*!< [8..8] desc UART3 */ + __IM uint32_t : 2; + __IOM uint32_t I2C1 : 1; /*!< [11..11] desc I2C1 */ + __IOM uint32_t I2C2 : 1; /*!< [12..12] desc I2C2 */ + } APBRST1_f; + } ; + + union + { + __IOM uint32_t RESETFLAG; /*!< (@ 0x0000004C) Reset Status Reg */ + + struct + { + __IOM uint32_t POR : 1; /*!< [0..0] desc POR */ + __IM uint32_t : 2; + __IOM uint32_t LVD : 1; /*!< [3..3] desc LVD */ + __IOM uint32_t IWDT : 1; /*!< [4..4] desc IWDT */ + __IOM uint32_t WWDT : 1; /*!< [5..5] desc WWDT */ + __IOM uint32_t RSTB : 1; /*!< [6..6] desc RSTB */ + __IM uint32_t : 1; + __IOM uint32_t LOCKUP : 1; /*!< [8..8] desc LOCKUP */ + __IOM uint32_t SYSRESETREQ : 1; /*!< [9..9] desc SYSRESETREQ */ + } RESETFLAG_f; + } ; + + union + { + __IOM uint32_t GTIM1CAP; /*!< (@ 0x00000050) GTIM1 CAP Control Reg */ + + struct + { + __IOM uint32_t CH1 : 3; /*!< [2..0] desc CH1 */ + __IM uint32_t : 1; + __IOM uint32_t CH2 : 3; /*!< [6..4] desc CH2 */ + __IM uint32_t : 1; + __IOM uint32_t CH3 : 3; /*!< [10..8] desc CH3 */ + __IM uint32_t : 1; + __IOM uint32_t CH4 : 3; /*!< [14..12] desc CH4 */ + } GTIM1CAP_f; + } ; + + union + { + __IOM uint32_t GTIM2CAP; /*!< (@ 0x00000054) GTIM2 CAP Control Reg */ + + struct + { + __IOM uint32_t CH1 : 3; /*!< [2..0] desc CH1 */ + __IM uint32_t : 1; + __IOM uint32_t CH2 : 3; /*!< [6..4] desc CH2 */ + __IM uint32_t : 1; + __IOM uint32_t CH3 : 3; /*!< [10..8] desc CH3 */ + __IM uint32_t : 1; + __IOM uint32_t CH4 : 3; /*!< [14..12] desc CH4 */ + } GTIM2CAP_f; + } ; + + union + { + __IOM uint32_t GTIM3CAP; /*!< (@ 0x00000058) GTIM3 CAP Control Reg */ + + struct + { + __IOM uint32_t CH1 : 3; /*!< [2..0] desc CH1 */ + __IM uint32_t : 1; + __IOM uint32_t CH2 : 3; /*!< [6..4] desc CH2 */ + __IM uint32_t : 1; + __IOM uint32_t CH3 : 3; /*!< [10..8] desc CH3 */ + __IM uint32_t : 1; + __IOM uint32_t CH4 : 3; /*!< [14..12] desc CH4 */ + } GTIM3CAP_f; + } ; + + union + { + __IOM uint32_t GTIM4CAP; /*!< (@ 0x0000005C) GTIM4 CAP Control Reg */ + + struct + { + __IOM uint32_t CH1 : 3; /*!< [2..0] desc CH1 */ + __IM uint32_t : 1; + __IOM uint32_t CH2 : 3; /*!< [6..4] desc CH2 */ + __IM uint32_t : 1; + __IOM uint32_t CH3 : 3; /*!< [10..8] desc CH3 */ + __IM uint32_t : 1; + __IOM uint32_t CH4 : 3; /*!< [14..12] desc CH4 */ + } GTIM4CAP_f; + } ; + + union + { + __IOM uint32_t ATIMETR; /*!< (@ 0x00000060) ATIM ETR Control Reg */ + + struct + { + __IOM uint32_t ATIMETR : 3; /*!< [2..0] desc ATIMETR */ + } ATIMETR_f; + } ; + + union + { + __IOM uint32_t GTIMETR; /*!< (@ 0x00000064) GTIM1-4 ETR Control Reg */ + + struct + { + __IOM uint32_t GTIM1ETR : 3; /*!< [2..0] desc GTIM1ETR */ + __IM uint32_t : 1; + __IOM uint32_t GTIM2ETR : 3; /*!< [6..4] desc GTIM2ETR */ + __IM uint32_t : 1; + __IOM uint32_t GTIM3ETR : 3; /*!< [10..8] desc GTIM3ETR */ + __IM uint32_t : 1; + __IOM uint32_t GTIM4ETR : 3; /*!< [14..12] desc GTIM4ETR */ + } GTIMETR_f; + } ; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t TIMITR; /*!< (@ 0x0000006C) BTIMx GTIMx ATIM ITR Control Reg */ + + struct + { + __IOM uint32_t ATIMITR : 3; /*!< [2..0] desc ATIMITR */ + __IOM uint32_t GTIM1ITR : 3; /*!< [5..3] desc GTIM1ITR */ + __IOM uint32_t GTIM2ITR : 3; /*!< [8..6] desc GTIM2ITR */ + __IOM uint32_t GTIM3ITR : 3; /*!< [11..9] desc GTIM3ITR */ + __IOM uint32_t GTIM4ITR : 3; /*!< [14..12] desc GTIM4ITR */ + __IOM uint32_t BTIM1ITR : 3; /*!< [17..15] desc BTIM1ITR */ + __IOM uint32_t BTIM2ITR : 3; /*!< [20..18] desc BTIM2ITR */ + __IOM uint32_t BTIM3ITR : 3; /*!< [23..21] desc BTIM3ITR */ + } TIMITR_f; + } ; + + union + { + __IOM uint32_t MCO; /*!< (@ 0x00000070) Master Clock Output Control Reg */ + + struct + { + __IOM uint32_t SOURCE : 4; /*!< [3..0] desc SOURCE */ + __IOM uint32_t DIV : 3; /*!< [6..4] desc DIV */ + } MCO_f; + } ; + + union + { + __IOM uint32_t IRMOD; /*!< (@ 0x00000074) IR MOD Control Reg */ + + struct + { + __IOM uint32_t MOD : 4; /*!< [3..0] desc MOD */ + } IRMOD_f; + } ; +} SYSCTRL_TypeDef; /*!< Size = 120 (0x78) */ + + + +/* =========================================================================================================================== */ +/* ================ UART1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc UART1 (UART1) + */ + +typedef struct /*!< (@ 0x40013800) UART1 Structure */ +{ + + union + { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control register1 */ + + struct + { + __IOM uint32_t TXEN : 1; /*!< [0..0] desc TXEN */ + __IOM uint32_t RXEN : 1; /*!< [1..1] desc RXEN */ + __IOM uint32_t PARITY : 2; /*!< [3..2] desc PARITY */ + __IOM uint32_t STOP : 2; /*!< [5..4] desc STOP */ + __IOM uint32_t SYNC : 1; /*!< [6..6] desc SYNC */ + __IM uint32_t : 1; + __IOM uint32_t START : 1; /*!< [8..8] desc START */ + __IOM uint32_t OVER : 2; /*!< [10..9] desc OVER */ + } CR1_f; + } ; + + union + { + __IOM uint32_t CR2; /*!< (@ 0x00000004) Control register2 */ + + struct + { + __IOM uint32_t ADDREN : 1; /*!< [0..0] desc ADDREN */ + __IOM uint32_t SIGNAL : 1; /*!< [1..1] desc SIGNAL */ + __IOM uint32_t CTSEN : 1; /*!< [2..2] desc CTSEN */ + __IOM uint32_t RTSEN : 1; /*!< [3..3] desc RTSEN */ + __IOM uint32_t RXINV : 1; /*!< [4..4] desc RXINV */ + __IOM uint32_t TXINV : 1; /*!< [5..5] desc TXINV */ + __IOM uint32_t DMARX : 1; /*!< [6..6] desc DMARX */ + __IOM uint32_t DMATX : 1; /*!< [7..7] desc DMATX */ + __IOM uint32_t SOURCE : 2; /*!< [9..8] desc SOURCE */ + } CR2_f; + } ; + + union + { + __IOM uint32_t IER; /*!< (@ 0x00000008) Interrupt enable register */ + + struct + { + __IOM uint32_t TXE : 1; /*!< [0..0] TxBuf empty */ + __IOM uint32_t TC : 1; /*!< [1..1] Transmit complete */ + __IOM uint32_t RC : 1; /*!< [2..2] Receive complete */ + __IOM uint32_t FE : 1; /*!< [3..3] Frame error */ + __IOM uint32_t PE : 1; /*!< [4..4] Parity error */ + __IM uint32_t : 1; + __IOM uint32_t CTS : 1; /*!< [6..6] CTS change */ + } IER_f; + } ; + + union + { + __IOM uint32_t BRRI; /*!< (@ 0x0000000C) desc BRRI */ + + struct + { + __IOM uint32_t BRRI : 16; /*!< [15..0] desc BRRI */ + } BRRI_f; + } ; + + union + { + __IOM uint32_t BRRF; /*!< (@ 0x00000010) desc BRRF */ + + struct + { + __IOM uint32_t BRRF : 4; /*!< [3..0] desc BRRF */ + } BRRF_f; + } ; + __IM uint32_t RESERVED[2]; + + union + { + __IM uint32_t ISR; /*!< (@ 0x0000001C) Interrupt status register */ + + struct + { + __IM uint32_t TXE : 1; /*!< [0..0] TxBuf empty */ + __IM uint32_t TC : 1; /*!< [1..1] Transmit complete */ + __IM uint32_t RC : 1; /*!< [2..2] Receive complete */ + __IM uint32_t FE : 1; /*!< [3..3] Frame error */ + __IM uint32_t PE : 1; /*!< [4..4] Parity error */ + __IM uint32_t MATCH : 1; /*!< [5..5] Slave addr match */ + __IM uint32_t CTS : 1; /*!< [6..6] CTS change */ + __IM uint32_t CTSLV : 1; /*!< [7..7] CTS PIN level */ + __IM uint32_t TXBUSY : 1; /*!< [8..8] desc TXBUSY */ + } ISR_f; + } ; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000020) Interrupt flag clear register */ + + struct + { + __IM uint32_t : 1; + __IOM uint32_t TC : 1; /*!< [1..1] Transmit complete */ + __IOM uint32_t RC : 1; /*!< [2..2] Receive complete */ + __IOM uint32_t FE : 1; /*!< [3..3] Frame error */ + __IOM uint32_t PE : 1; /*!< [4..4] Parity error */ + __IM uint32_t : 1; + __IOM uint32_t CTS : 1; /*!< [6..6] CTS change */ + } ICR_f; + } ; + + union + { + __IM uint32_t RDR; /*!< (@ 0x00000024) Data reg for read */ + + struct + { + __IM uint32_t RDR : 9; /*!< [8..0] desc RDR */ + } RDR_f; + } ; + + union + { + __OM uint32_t TDR; /*!< (@ 0x00000028) Data reg for write */ + + struct + { + __OM uint32_t TDR : 9; /*!< [8..0] desc TDR */ + } TDR_f; + } ; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t ADDR; /*!< (@ 0x00000030) Slave addr */ + + struct + { + __IOM uint32_t ADDR : 8; /*!< [7..0] desc ADDR */ + } ADDR_f; + } ; + + union + { + __IOM uint32_t MASK; /*!< (@ 0x00000034) Slave addr mask */ + + struct + { + __IOM uint32_t MASK : 8; /*!< [7..0] desc MASK */ + } MASK_f; + } ; +} UART_TypeDef; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ VC1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc VC1 (VC1) + */ + +typedef struct /*!< (@ 0x40012A00) VC1 Structure */ +{ + + union + { + __IOM uint32_t DIV; /*!< (@ 0x00000000) desc DIV */ + + struct + { + __IOM uint32_t DIV : 6; /*!< [5..0] desc DIV */ + __IOM uint32_t EN : 1; /*!< [6..6] desc EN */ + __IOM uint32_t VIN : 1; /*!< [7..7] desc VIN */ + } DIV_f; + } ; + + union + { + __IOM uint32_t CR0; /*!< (@ 0x00000004) Control register0 */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t RESP : 2; /*!< [2..1] desc RESP */ + __IOM uint32_t HYS : 2; /*!< [4..3] desc HYS */ + __IOM uint32_t IE : 1; /*!< [5..5] desc IE */ + __IOM uint32_t POL : 1; /*!< [6..6] desc POL */ + __IOM uint32_t WINDOW : 1; /*!< [7..7] desc WINDOW */ + __IOM uint32_t INP : 4; /*!< [11..8] desc INP */ + __IOM uint32_t INN : 4; /*!< [15..12] desc INN */ + } CR0_f; + } ; + + union + { + __IOM uint32_t CR1; /*!< (@ 0x00000008) Control register1 */ + + struct + { + __IOM uint32_t FLTEN : 1; /*!< [0..0] desc FLTEN */ + __IOM uint32_t FLTTIME : 3; /*!< [3..1] desc FLTTIME */ + __IOM uint32_t FLTCLK : 1; /*!< [4..4] desc FLTCLK */ + __IOM uint32_t FALLIE : 1; /*!< [5..5] desc FALLIE */ + __IOM uint32_t RISEIE : 1; /*!< [6..6] desc RISEIE */ + __IOM uint32_t HIGHIE : 1; /*!< [7..7] desc HIGHIE */ + __IOM uint32_t ATIMCLR : 1; /*!< [8..8] desc ATIMCLR */ + __IOM uint32_t ATIMBK : 1; /*!< [9..9] desc ATIMBK */ + __IOM uint32_t BLANKCH1B : 1; /*!< [10..10] desc BLANKCH1B */ + __IOM uint32_t BLANKCH2B : 1; /*!< [11..11] desc BLANKCH2B */ + __IOM uint32_t BLANKCH3B : 1; /*!< [12..12] desc BLANKCH3B */ + __IOM uint32_t BLANKFLT : 3; /*!< [15..13] desc BLANKFLT */ + } CR1_f; + } ; + + union + { + __IOM uint32_t SR; /*!< (@ 0x0000000C) Status register */ + + struct + { + __IOM uint32_t INTF : 1; /*!< [0..0] desc INTF */ + __IM uint32_t FLTV : 1; /*!< [1..1] desc FLTV */ + __IM uint32_t READY : 1; /*!< [2..2] desc READY */ + } SR_f; + } ; +} VC_TypeDef; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ WWDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc WWDT (WWDT) + */ + +typedef struct /*!< (@ 0x40002C00) WWDT Structure */ +{ + + union + { + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control register1 */ + + struct + { + __IOM uint32_t WCNT : 7; /*!< [6..0] desc WCNT */ + __IOM uint32_t EN : 1; /*!< [7..7] desc EN */ + } CR0_f; + } ; + + union + { + __IOM uint32_t CR1; /*!< (@ 0x00000004) Control register2 */ + + struct + { + __IOM uint32_t WINR : 7; /*!< [6..0] desc WINR */ + __IOM uint32_t PRS : 3; /*!< [9..7] desc PRS */ + __IOM uint32_t IE : 1; /*!< [10..10] desc IE */ + } CR1_f; + } ; + + union + { + __IOM uint32_t SR; /*!< (@ 0x00000008) Status register */ + + struct + { + __IOM uint32_t POV : 1; /*!< [0..0] desc POV */ + } SR_f; + } ; +} WWDT_TypeDef; /*!< Size = 12 (0xc) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define ADC_BASE 0x40012400UL +#define ATIM_BASE 0x40012C00UL +#define AWT_BASE 0x40014C00UL +#define BTIM1_BASE 0x40014800UL +#define BTIM2_BASE 0x40014900UL +#define BTIM3_BASE 0x40014A00UL +#define CRC_BASE 0x40023000UL +#define DMA_BASE 0x40020000UL +#define DMACHANNEL1_BASE 0x40020020UL +#define DMACHANNEL2_BASE 0x40020040UL +#define DMACHANNEL3_BASE 0x40020060UL +#define DMACHANNEL4_BASE 0x40020080UL +#define DMACHANNEL5_BASE 0x400200A0UL +#define FLASH_BASE 0x40022000UL +#define GPIOA_BASE 0x48000000UL +#define GPIOB_BASE 0x48000400UL +#define GPIOC_BASE 0x48000800UL +#define GPIOF_BASE 0x48001400UL +#define GTIM1_BASE 0x40000400UL +#define GTIM2_BASE 0x40001000UL +#define GTIM3_BASE 0x40014000UL +#define GTIM4_BASE 0x40014400UL +#define I2C1_BASE 0x40005400UL +#define I2C2_BASE 0x40005800UL +#define IWDT_BASE 0x40003000UL +#define LVD_BASE 0x40012A80UL +#define RAM_BASE 0x40022400UL +#define RTC_BASE 0x40002800UL +#define SPI1_BASE 0x40013000UL +#define SPI2_BASE 0x40003800UL +#define SYSCTRL_BASE 0x40010000UL +#define UART1_BASE 0x40013800UL +#define UART2_BASE 0x40004400UL +#define UART3_BASE 0x40004800UL +#define VC1_BASE 0x40012A00UL +#define VC2_BASE 0x40012A10UL +#define WWDT_BASE 0x40002C00UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ +#define CW_ADC ((ADC_TypeDef*) ADC_BASE) +#define CW_ATIM ((ATIM_TypeDef*) ATIM_BASE) +#define CW_AWT ((AWT_TypeDef*) AWT_BASE) +#define CW_BTIM1 ((BTIM_TypeDef*) BTIM1_BASE) +#define CW_BTIM2 ((BTIM_TypeDef*) BTIM2_BASE) +#define CW_BTIM3 ((BTIM_TypeDef*) BTIM3_BASE) +#define CW_CRC ((CRC_TypeDef*) CRC_BASE) +#define CW_DMA ((DMA_TypeDef*) DMA_BASE) +#define CW_DMACHANNEL1 ((DMACHANNEL_TypeDef*) DMACHANNEL1_BASE) +#define CW_DMACHANNEL2 ((DMACHANNEL_TypeDef*) DMACHANNEL2_BASE) +#define CW_DMACHANNEL3 ((DMACHANNEL_TypeDef*) DMACHANNEL3_BASE) +#define CW_DMACHANNEL4 ((DMACHANNEL_TypeDef*) DMACHANNEL4_BASE) +#define CW_DMACHANNEL5 ((DMACHANNEL_TypeDef*) DMACHANNEL5_BASE) +#define CW_FLASH ((FLASH_TypeDef*) FLASH_BASE) +#define CW_GPIOA ((GPIO_TypeDef*) GPIOA_BASE) +#define CW_GPIOB ((GPIO_TypeDef*) GPIOB_BASE) +#define CW_GPIOC ((GPIO_TypeDef*) GPIOC_BASE) +#define CW_GPIOF ((GPIO_TypeDef*) GPIOF_BASE) +#define CW_GTIM1 ((GTIM_TypeDef*) GTIM1_BASE) +#define CW_GTIM2 ((GTIM_TypeDef*) GTIM2_BASE) +#define CW_GTIM3 ((GTIM_TypeDef*) GTIM3_BASE) +#define CW_GTIM4 ((GTIM_TypeDef*) GTIM4_BASE) +#define CW_I2C1 ((I2C_TypeDef*) I2C1_BASE) +#define CW_I2C2 ((I2C_TypeDef*) I2C2_BASE) +#define CW_IWDT ((IWDT_TypeDef*) IWDT_BASE) +#define CW_LVD ((LVD_TypeDef*) LVD_BASE) +#define CW_RAM ((RAM_TypeDef*) RAM_BASE) +#define CW_RTC ((RTC_TypeDef*) RTC_BASE) +#define CW_SPI1 ((SPI_TypeDef*) SPI1_BASE) +#define CW_SPI2 ((SPI_TypeDef*) SPI2_BASE) +#define CW_SYSCTRL ((SYSCTRL_TypeDef*) SYSCTRL_BASE) +#define CW_UART1 ((UART_TypeDef*) UART1_BASE) +#define CW_UART2 ((UART_TypeDef*) UART2_BASE) +#define CW_UART3 ((UART_TypeDef*) UART3_BASE) +#define CW_VC1 ((VC_TypeDef*) VC1_BASE) +#define CW_VC2 ((VC_TypeDef*) VC2_BASE) +#define CW_WWDT ((WWDT_TypeDef*) WWDT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) +#pragma pop +#elif defined (__ICCARM__) +/* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#elif defined (__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined (__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning restore +#elif defined (__CSMC__) +/* anonymous unions are enabled by default */ +#endif + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define ADC_CR0_BIAS_Pos (14UL) /*!< BIAS (Bit 14) */ +#define ADC_CR0_BIAS_Msk (0xc000UL) /*!< BIAS (Bitfield-Mask: 0x03) */ +#define ADC_CR0_BUF_Pos (13UL) /*!< BUF (Bit 13) */ +#define ADC_CR0_BUF_Msk (0x2000UL) /*!< BUF (Bitfield-Mask: 0x01) */ +#define ADC_CR0_SAM_Pos (11UL) /*!< SAM (Bit 11) */ +#define ADC_CR0_SAM_Msk (0x1800UL) /*!< SAM (Bitfield-Mask: 0x03) */ +#define ADC_CR0_CLK_Pos (8UL) /*!< CLK (Bit 8) */ +#define ADC_CR0_CLK_Msk (0x700UL) /*!< CLK (Bitfield-Mask: 0x07) */ +#define ADC_CR0_REF_Pos (6UL) /*!< REF (Bit 6) */ +#define ADC_CR0_REF_Msk (0xc0UL) /*!< REF (Bitfield-Mask: 0x03) */ +#define ADC_CR0_TSEN_Pos (5UL) /*!< TSEN (Bit 5) */ +#define ADC_CR0_TSEN_Msk (0x20UL) /*!< TSEN (Bitfield-Mask: 0x01) */ +#define ADC_CR0_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ +#define ADC_CR0_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +#define ADC_CR0_MODE_Pos (1UL) /*!< MODE (Bit 1) */ +#define ADC_CR0_MODE_Msk (0xeUL) /*!< MODE (Bitfield-Mask: 0x07) */ +#define ADC_CR0_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define ADC_CR0_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ +#define ADC_CR1_WDTALL_Pos (13UL) /*!< WDTALL (Bit 13) */ +#define ADC_CR1_WDTALL_Msk (0x2000UL) /*!< WDTALL (Bitfield-Mask: 0x01) */ +#define ADC_CR1_WDTCH_Pos (8UL) /*!< WDTCH (Bit 8) */ +#define ADC_CR1_WDTCH_Msk (0xf00UL) /*!< WDTCH (Bitfield-Mask: 0x0f) */ +#define ADC_CR1_DMAEN_Pos (7UL) /*!< DMAEN (Bit 7) */ +#define ADC_CR1_DMAEN_Msk (0x80UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +#define ADC_CR1_ALIGN_Pos (6UL) /*!< ALIGN (Bit 6) */ +#define ADC_CR1_ALIGN_Msk (0x40UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ +#define ADC_CR1_DISCARD_Pos (5UL) /*!< DISCARD (Bit 5) */ +#define ADC_CR1_DISCARD_Msk (0x20UL) /*!< DISCARD (Bitfield-Mask: 0x01) */ +#define ADC_CR1_CHMUX_Pos (0UL) /*!< CHMUX (Bit 0) */ +#define ADC_CR1_CHMUX_Msk (0xfUL) /*!< CHMUX (Bitfield-Mask: 0x0f) */ +/* ========================================================= START ========================================================= */ +#define ADC_START_AUTOSTOP_Pos (1UL) /*!< AUTOSTOP (Bit 1) */ +#define ADC_START_AUTOSTOP_Msk (0x2UL) /*!< AUTOSTOP (Bitfield-Mask: 0x01) */ +#define ADC_START_START_Pos (0UL) /*!< START (Bit 0) */ +#define ADC_START_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================== SQR ========================================================== */ +#define ADC_SQR_ENS_Pos (16UL) /*!< ENS (Bit 16) */ +#define ADC_SQR_ENS_Msk (0x30000UL) /*!< ENS (Bitfield-Mask: 0x03) */ +#define ADC_SQR_SQR3_Pos (12UL) /*!< SQR3 (Bit 12) */ +#define ADC_SQR_SQR3_Msk (0xf000UL) /*!< SQR3 (Bitfield-Mask: 0x0f) */ +#define ADC_SQR_SQR2_Pos (8UL) /*!< SQR2 (Bit 8) */ +#define ADC_SQR_SQR2_Msk (0xf00UL) /*!< SQR2 (Bitfield-Mask: 0x0f) */ +#define ADC_SQR_SQR1_Pos (4UL) /*!< SQR1 (Bit 4) */ +#define ADC_SQR_SQR1_Msk (0xf0UL) /*!< SQR1 (Bitfield-Mask: 0x0f) */ +#define ADC_SQR_SQR0_Pos (0UL) /*!< SQR0 (Bit 0) */ +#define ADC_SQR_SQR0_Msk (0xfUL) /*!< SQR0 (Bitfield-Mask: 0x0f) */ +/* ========================================================== CR2 ========================================================== */ +#define ADC_CR2_ACCRST_Pos (9UL) /*!< ACCRST (Bit 9) */ +#define ADC_CR2_ACCRST_Msk (0x200UL) /*!< ACCRST (Bitfield-Mask: 0x01) */ +#define ADC_CR2_ACCEN_Pos (8UL) /*!< ACCEN (Bit 8) */ +#define ADC_CR2_ACCEN_Msk (0x100UL) /*!< ACCEN (Bitfield-Mask: 0x01) */ +#define ADC_CR2_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define ADC_CR2_CNT_Msk (0xffUL) /*!< CNT (Bitfield-Mask: 0xff) */ +/* ========================================================== VTH ========================================================== */ +#define ADC_VTH_VTH_Pos (0UL) /*!< VTH (Bit 0) */ +#define ADC_VTH_VTH_Msk (0xfffUL) /*!< VTH (Bitfield-Mask: 0xfff) */ +/* ========================================================== VTL ========================================================== */ +#define ADC_VTL_VTL_Pos (0UL) /*!< VTL (Bit 0) */ +#define ADC_VTL_VTL_Msk (0xfffUL) /*!< VTL (Bitfield-Mask: 0xfff) */ +/* ======================================================== TRIGGER ======================================================== */ +#define ADC_TRIGGER_DMA_Pos (15UL) /*!< DMA (Bit 15) */ +#define ADC_TRIGGER_DMA_Msk (0x8000UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_I2C2_Pos (14UL) /*!< I2C2 (Bit 14) */ +#define ADC_TRIGGER_I2C2_Msk (0x4000UL) /*!< I2C2 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_I2C1_Pos (13UL) /*!< I2C1 (Bit 13) */ +#define ADC_TRIGGER_I2C1_Msk (0x2000UL) /*!< I2C1 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_SPI2_Pos (12UL) /*!< SPI2 (Bit 12) */ +#define ADC_TRIGGER_SPI2_Msk (0x1000UL) /*!< SPI2 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_SPI1_Pos (11UL) /*!< SPI1 (Bit 11) */ +#define ADC_TRIGGER_SPI1_Msk (0x800UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_UART3_Pos (10UL) /*!< UART3 (Bit 10) */ +#define ADC_TRIGGER_UART3_Msk (0x400UL) /*!< UART3 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_UART2_Pos (9UL) /*!< UART2 (Bit 9) */ +#define ADC_TRIGGER_UART2_Msk (0x200UL) /*!< UART2 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_UART1_Pos (8UL) /*!< UART1 (Bit 8) */ +#define ADC_TRIGGER_UART1_Msk (0x100UL) /*!< UART1 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_BTIM3_Pos (7UL) /*!< BTIM3 (Bit 7) */ +#define ADC_TRIGGER_BTIM3_Msk (0x80UL) /*!< BTIM3 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_BTIM2_Pos (6UL) /*!< BTIM2 (Bit 6) */ +#define ADC_TRIGGER_BTIM2_Msk (0x40UL) /*!< BTIM2 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_BTIM1_Pos (5UL) /*!< BTIM1 (Bit 5) */ +#define ADC_TRIGGER_BTIM1_Msk (0x20UL) /*!< BTIM1 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_GTIM4_Pos (4UL) /*!< GTIM4 (Bit 4) */ +#define ADC_TRIGGER_GTIM4_Msk (0x10UL) /*!< GTIM4 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_GTIM3_Pos (3UL) /*!< GTIM3 (Bit 3) */ +#define ADC_TRIGGER_GTIM3_Msk (0x8UL) /*!< GTIM3 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_GTIM2_Pos (2UL) /*!< GTIM2 (Bit 2) */ +#define ADC_TRIGGER_GTIM2_Msk (0x4UL) /*!< GTIM2 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_GTIM1_Pos (1UL) /*!< GTIM1 (Bit 1) */ +#define ADC_TRIGGER_GTIM1_Msk (0x2UL) /*!< GTIM1 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_ATIM_Pos (0UL) /*!< ATIM (Bit 0) */ +#define ADC_TRIGGER_ATIM_Msk (0x1UL) /*!< ATIM (Bitfield-Mask: 0x01) */ +/* ======================================================== RESULT0 ======================================================== */ +#define ADC_RESULT0_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADC_RESULT0_RESULT_Msk (0xffffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT1 ======================================================== */ +#define ADC_RESULT1_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADC_RESULT1_RESULT_Msk (0xffffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT2 ======================================================== */ +#define ADC_RESULT2_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADC_RESULT2_RESULT_Msk (0xffffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT3 ======================================================== */ +#define ADC_RESULT3_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADC_RESULT3_RESULT_Msk (0xffffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================= RESULTACC ======================================================= */ +#define ADC_RESULTACC_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADC_RESULTACC_RESULT_Msk (0xffffffUL) /*!< RESULT (Bitfield-Mask: 0xffffff) */ +/* ========================================================== IER ========================================================== */ +#define ADC_IER_OVW_Pos (6UL) /*!< OVW (Bit 6) */ +#define ADC_IER_OVW_Msk (0x40UL) /*!< OVW (Bitfield-Mask: 0x01) */ +#define ADC_IER_WDTR_Pos (5UL) /*!< WDTR (Bit 5) */ +#define ADC_IER_WDTR_Msk (0x20UL) /*!< WDTR (Bitfield-Mask: 0x01) */ +#define ADC_IER_WDTH_Pos (4UL) /*!< WDTH (Bit 4) */ +#define ADC_IER_WDTH_Msk (0x10UL) /*!< WDTH (Bitfield-Mask: 0x01) */ +#define ADC_IER_WDTL_Pos (3UL) /*!< WDTL (Bit 3) */ +#define ADC_IER_WDTL_Msk (0x8UL) /*!< WDTL (Bitfield-Mask: 0x01) */ +#define ADC_IER_EOA_Pos (2UL) /*!< EOA (Bit 2) */ +#define ADC_IER_EOA_Msk (0x4UL) /*!< EOA (Bitfield-Mask: 0x01) */ +#define ADC_IER_EOS_Pos (1UL) /*!< EOS (Bit 1) */ +#define ADC_IER_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */ +#define ADC_IER_EOC_Pos (0UL) /*!< EOC (Bit 0) */ +#define ADC_IER_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define ADC_ISR_READY_Pos (7UL) /*!< READY (Bit 7) */ +#define ADC_ISR_READY_Msk (0x80UL) /*!< READY (Bitfield-Mask: 0x01) */ +#define ADC_ISR_OVW_Pos (6UL) /*!< OVW (Bit 6) */ +#define ADC_ISR_OVW_Msk (0x40UL) /*!< OVW (Bitfield-Mask: 0x01) */ +#define ADC_ISR_WDTR_Pos (5UL) /*!< WDTR (Bit 5) */ +#define ADC_ISR_WDTR_Msk (0x20UL) /*!< WDTR (Bitfield-Mask: 0x01) */ +#define ADC_ISR_WDTH_Pos (4UL) /*!< WDTH (Bit 4) */ +#define ADC_ISR_WDTH_Msk (0x10UL) /*!< WDTH (Bitfield-Mask: 0x01) */ +#define ADC_ISR_WDTL_Pos (3UL) /*!< WDTL (Bit 3) */ +#define ADC_ISR_WDTL_Msk (0x8UL) /*!< WDTL (Bitfield-Mask: 0x01) */ +#define ADC_ISR_EOA_Pos (2UL) /*!< EOA (Bit 2) */ +#define ADC_ISR_EOA_Msk (0x4UL) /*!< EOA (Bitfield-Mask: 0x01) */ +#define ADC_ISR_EOS_Pos (1UL) /*!< EOS (Bit 1) */ +#define ADC_ISR_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */ +#define ADC_ISR_EOC_Pos (0UL) /*!< EOC (Bit 0) */ +#define ADC_ISR_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define ADC_ICR_OVW_Pos (6UL) /*!< OVW (Bit 6) */ +#define ADC_ICR_OVW_Msk (0x40UL) /*!< OVW (Bitfield-Mask: 0x01) */ +#define ADC_ICR_WDTR_Pos (5UL) /*!< WDTR (Bit 5) */ +#define ADC_ICR_WDTR_Msk (0x20UL) /*!< WDTR (Bitfield-Mask: 0x01) */ +#define ADC_ICR_WDTH_Pos (4UL) /*!< WDTH (Bit 4) */ +#define ADC_ICR_WDTH_Msk (0x10UL) /*!< WDTH (Bitfield-Mask: 0x01) */ +#define ADC_ICR_WDTL_Pos (3UL) /*!< WDTL (Bit 3) */ +#define ADC_ICR_WDTL_Msk (0x8UL) /*!< WDTL (Bitfield-Mask: 0x01) */ +#define ADC_ICR_EOA_Pos (2UL) /*!< EOA (Bit 2) */ +#define ADC_ICR_EOA_Msk (0x4UL) /*!< EOA (Bitfield-Mask: 0x01) */ +#define ADC_ICR_EOS_Pos (1UL) /*!< EOS (Bit 1) */ +#define ADC_ICR_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */ +#define ADC_ICR_EOC_Pos (0UL) /*!< EOC (Bit 0) */ +#define ADC_ICR_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ATIM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ARR ========================================================== */ +#define ATIM_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define ATIM_ARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ========================================================== CNT ========================================================== */ +#define ATIM_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define ATIM_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== CR =========================================================== */ +#define ATIM_CR_UNDE_Pos (29UL) /*!< UNDE (Bit 29) */ +#define ATIM_CR_UNDE_Msk (0x20000000UL) /*!< UNDE (Bitfield-Mask: 0x01) */ +#define ATIM_CR_OVE_Pos (28UL) /*!< OVE (Bit 28) */ +#define ATIM_CR_OVE_Msk (0x10000000UL) /*!< OVE (Bitfield-Mask: 0x01) */ +#define ATIM_CR_DIR_Pos (27UL) /*!< DIR (Bit 27) */ +#define ATIM_CR_DIR_Msk (0x8000000UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define ATIM_CR_BG_Pos (26UL) /*!< BG (Bit 26) */ +#define ATIM_CR_BG_Msk (0x4000000UL) /*!< BG (Bitfield-Mask: 0x01) */ +#define ATIM_CR_UG_Pos (25UL) /*!< UG (Bit 25) */ +#define ATIM_CR_UG_Msk (0x2000000UL) /*!< UG (Bitfield-Mask: 0x01) */ +#define ATIM_CR_TG_Pos (24UL) /*!< TG (Bit 24) */ +#define ATIM_CR_TG_Msk (0x1000000UL) /*!< TG (Bitfield-Mask: 0x01) */ +#define ATIM_CR_OCCE_Pos (23UL) /*!< OCCE (Bit 23) */ +#define ATIM_CR_OCCE_Msk (0x800000UL) /*!< OCCE (Bitfield-Mask: 0x01) */ +#define ATIM_CR_CISA_Pos (21UL) /*!< CISA (Bit 21) */ +#define ATIM_CR_CISA_Msk (0x600000UL) /*!< CISA (Bitfield-Mask: 0x03) */ +#define ATIM_CR_BIE_Pos (20UL) /*!< BIE (Bit 20) */ +#define ATIM_CR_BIE_Msk (0x100000UL) /*!< BIE (Bitfield-Mask: 0x01) */ +#define ATIM_CR_TIE_Pos (19UL) /*!< TIE (Bit 19) */ +#define ATIM_CR_TIE_Msk (0x80000UL) /*!< TIE (Bitfield-Mask: 0x01) */ +#define ATIM_CR_URS_Pos (17UL) /*!< URS (Bit 17) */ +#define ATIM_CR_URS_Msk (0x20000UL) /*!< URS (Bitfield-Mask: 0x01) */ +#define ATIM_CR_OCCS_Pos (16UL) /*!< OCCS (Bit 16) */ +#define ATIM_CR_OCCS_Msk (0x10000UL) /*!< OCCS (Bitfield-Mask: 0x01) */ +#define ATIM_CR_ONESHOT_Pos (14UL) /*!< ONESHOT (Bit 14) */ +#define ATIM_CR_ONESHOT_Msk (0x4000UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ +#define ATIM_CR_MODE_Pos (12UL) /*!< MODE (Bit 12) */ +#define ATIM_CR_MODE_Msk (0x3000UL) /*!< MODE (Bitfield-Mask: 0x03) */ +#define ATIM_CR_UIE_Pos (10UL) /*!< UIE (Bit 10) */ +#define ATIM_CR_UIE_Msk (0x400UL) /*!< UIE (Bitfield-Mask: 0x01) */ +#define ATIM_CR_BUFPEN_Pos (7UL) /*!< BUFPEN (Bit 7) */ +#define ATIM_CR_BUFPEN_Msk (0x80UL) /*!< BUFPEN (Bitfield-Mask: 0x01) */ +#define ATIM_CR_PRS_Pos (4UL) /*!< PRS (Bit 4) */ +#define ATIM_CR_PRS_Msk (0x70UL) /*!< PRS (Bitfield-Mask: 0x07) */ +#define ATIM_CR_PWM2S_Pos (3UL) /*!< PWM2S (Bit 3) */ +#define ATIM_CR_PWM2S_Msk (0x8UL) /*!< PWM2S (Bitfield-Mask: 0x01) */ +#define ATIM_CR_CT_Pos (2UL) /*!< CT (Bit 2) */ +#define ATIM_CR_CT_Msk (0x4UL) /*!< CT (Bitfield-Mask: 0x01) */ +#define ATIM_CR_COMP_Pos (1UL) /*!< COMP (Bit 1) */ +#define ATIM_CR_COMP_Msk (0x2UL) /*!< COMP (Bitfield-Mask: 0x01) */ +#define ATIM_CR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define ATIM_CR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define ATIM_ISR_C4AF_Pos (18UL) /*!< C4AF (Bit 18) */ +#define ATIM_ISR_C4AF_Msk (0x40000UL) /*!< C4AF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_UNDF_Pos (17UL) /*!< UNDF (Bit 17) */ +#define ATIM_ISR_UNDF_Msk (0x20000UL) /*!< UNDF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_OVF_Pos (16UL) /*!< OVF (Bit 16) */ +#define ATIM_ISR_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_TIF_Pos (15UL) /*!< TIF (Bit 15) */ +#define ATIM_ISR_TIF_Msk (0x8000UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_BIF_Pos (14UL) /*!< BIF (Bit 14) */ +#define ATIM_ISR_BIF_Msk (0x4000UL) /*!< BIF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C3BE_Pos (13UL) /*!< C3BE (Bit 13) */ +#define ATIM_ISR_C3BE_Msk (0x2000UL) /*!< C3BE (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C2BE_Pos (12UL) /*!< C2BE (Bit 12) */ +#define ATIM_ISR_C2BE_Msk (0x1000UL) /*!< C2BE (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C1BE_Pos (11UL) /*!< C1BE (Bit 11) */ +#define ATIM_ISR_C1BE_Msk (0x800UL) /*!< C1BE (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C3AE_Pos (10UL) /*!< C3AE (Bit 10) */ +#define ATIM_ISR_C3AE_Msk (0x400UL) /*!< C3AE (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C2AE_Pos (9UL) /*!< C2AE (Bit 9) */ +#define ATIM_ISR_C2AE_Msk (0x200UL) /*!< C2AE (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C1AE_Pos (8UL) /*!< C1AE (Bit 8) */ +#define ATIM_ISR_C1AE_Msk (0x100UL) /*!< C1AE (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C3BF_Pos (7UL) /*!< C3BF (Bit 7) */ +#define ATIM_ISR_C3BF_Msk (0x80UL) /*!< C3BF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C2BF_Pos (6UL) /*!< C2BF (Bit 6) */ +#define ATIM_ISR_C2BF_Msk (0x40UL) /*!< C2BF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C1BF_Pos (5UL) /*!< C1BF (Bit 5) */ +#define ATIM_ISR_C1BF_Msk (0x20UL) /*!< C1BF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C3AF_Pos (4UL) /*!< C3AF (Bit 4) */ +#define ATIM_ISR_C3AF_Msk (0x10UL) /*!< C3AF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C2AF_Pos (3UL) /*!< C2AF (Bit 3) */ +#define ATIM_ISR_C2AF_Msk (0x8UL) /*!< C2AF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C1AF_Pos (2UL) /*!< C1AF (Bit 2) */ +#define ATIM_ISR_C1AF_Msk (0x4UL) /*!< C1AF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_UIF_Pos (0UL) /*!< UIF (Bit 0) */ +#define ATIM_ISR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define ATIM_ICR_C4AF_Pos (18UL) /*!< C4AF (Bit 18) */ +#define ATIM_ICR_C4AF_Msk (0x40000UL) /*!< C4AF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_UNDF_Pos (17UL) /*!< UNDF (Bit 17) */ +#define ATIM_ICR_UNDF_Msk (0x20000UL) /*!< UNDF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_OVF_Pos (16UL) /*!< OVF (Bit 16) */ +#define ATIM_ICR_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_TIF_Pos (15UL) /*!< TIF (Bit 15) */ +#define ATIM_ICR_TIF_Msk (0x8000UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_BIF_Pos (14UL) /*!< BIF (Bit 14) */ +#define ATIM_ICR_BIF_Msk (0x4000UL) /*!< BIF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C3BE_Pos (13UL) /*!< C3BE (Bit 13) */ +#define ATIM_ICR_C3BE_Msk (0x2000UL) /*!< C3BE (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C2BE_Pos (12UL) /*!< C2BE (Bit 12) */ +#define ATIM_ICR_C2BE_Msk (0x1000UL) /*!< C2BE (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C1BE_Pos (11UL) /*!< C1BE (Bit 11) */ +#define ATIM_ICR_C1BE_Msk (0x800UL) /*!< C1BE (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C3AE_Pos (10UL) /*!< C3AE (Bit 10) */ +#define ATIM_ICR_C3AE_Msk (0x400UL) /*!< C3AE (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C2AE_Pos (9UL) /*!< C2AE (Bit 9) */ +#define ATIM_ICR_C2AE_Msk (0x200UL) /*!< C2AE (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C1AE_Pos (8UL) /*!< C1AE (Bit 8) */ +#define ATIM_ICR_C1AE_Msk (0x100UL) /*!< C1AE (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C3BF_Pos (7UL) /*!< C3BF (Bit 7) */ +#define ATIM_ICR_C3BF_Msk (0x80UL) /*!< C3BF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C2BF_Pos (6UL) /*!< C2BF (Bit 6) */ +#define ATIM_ICR_C2BF_Msk (0x40UL) /*!< C2BF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C1BF_Pos (5UL) /*!< C1BF (Bit 5) */ +#define ATIM_ICR_C1BF_Msk (0x20UL) /*!< C1BF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C3AF_Pos (4UL) /*!< C3AF (Bit 4) */ +#define ATIM_ICR_C3AF_Msk (0x10UL) /*!< C3AF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C2AF_Pos (3UL) /*!< C2AF (Bit 3) */ +#define ATIM_ICR_C2AF_Msk (0x8UL) /*!< C2AF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C1AF_Pos (2UL) /*!< C1AF (Bit 2) */ +#define ATIM_ICR_C1AF_Msk (0x4UL) /*!< C1AF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_UIF_Pos (0UL) /*!< UIF (Bit 0) */ +#define ATIM_ICR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */ +/* ========================================================= MSCR ========================================================== */ +#define ATIM_MSCR_IB1S_Pos (12UL) /*!< IB1S (Bit 12) */ +#define ATIM_MSCR_IB1S_Msk (0x1000UL) /*!< IB1S (Bitfield-Mask: 0x01) */ +#define ATIM_MSCR_IA1S_Pos (11UL) /*!< IA1S (Bit 11) */ +#define ATIM_MSCR_IA1S_Msk (0x800UL) /*!< IA1S (Bitfield-Mask: 0x01) */ +#define ATIM_MSCR_SMS_Pos (8UL) /*!< SMS (Bit 8) */ +#define ATIM_MSCR_SMS_Msk (0x700UL) /*!< SMS (Bitfield-Mask: 0x07) */ +#define ATIM_MSCR_TS_Pos (5UL) /*!< TS (Bit 5) */ +#define ATIM_MSCR_TS_Msk (0xe0UL) /*!< TS (Bitfield-Mask: 0x07) */ +#define ATIM_MSCR_CCDS_Pos (3UL) /*!< CCDS (Bit 3) */ +#define ATIM_MSCR_CCDS_Msk (0x8UL) /*!< CCDS (Bitfield-Mask: 0x01) */ +#define ATIM_MSCR_MMS_Pos (0UL) /*!< MMS (Bit 0) */ +#define ATIM_MSCR_MMS_Msk (0x7UL) /*!< MMS (Bitfield-Mask: 0x07) */ +/* ========================================================= FLTR ========================================================== */ +#define ATIM_FLTR_ETP_Pos (31UL) /*!< ETP (Bit 31) */ +#define ATIM_FLTR_ETP_Msk (0x80000000UL) /*!< ETP (Bitfield-Mask: 0x01) */ +#define ATIM_FLTR_FLTET_Pos (28UL) /*!< FLTET (Bit 28) */ +#define ATIM_FLTR_FLTET_Msk (0x70000000UL) /*!< FLTET (Bitfield-Mask: 0x07) */ +#define ATIM_FLTR_BKP_Pos (27UL) /*!< BKP (Bit 27) */ +#define ATIM_FLTR_BKP_Msk (0x8000000UL) /*!< BKP (Bitfield-Mask: 0x01) */ +#define ATIM_FLTR_FLTBK_Pos (24UL) /*!< FLTBK (Bit 24) */ +#define ATIM_FLTR_FLTBK_Msk (0x7000000UL) /*!< FLTBK (Bitfield-Mask: 0x07) */ +#define ATIM_FLTR_CCP3B_Pos (23UL) /*!< CCP3B (Bit 23) */ +#define ATIM_FLTR_CCP3B_Msk (0x800000UL) /*!< CCP3B (Bitfield-Mask: 0x01) */ +#define ATIM_FLTR_OCM3BFLT3B_Pos (20UL) /*!< OCM3BFLT3B (Bit 20) */ +#define ATIM_FLTR_OCM3BFLT3B_Msk (0x700000UL) /*!< OCM3BFLT3B (Bitfield-Mask: 0x07) */ +#define ATIM_FLTR_CCP3A_Pos (19UL) /*!< CCP3A (Bit 19) */ +#define ATIM_FLTR_CCP3A_Msk (0x80000UL) /*!< CCP3A (Bitfield-Mask: 0x01) */ +#define ATIM_FLTR_OCM3AFLT3A_Pos (16UL) /*!< OCM3AFLT3A (Bit 16) */ +#define ATIM_FLTR_OCM3AFLT3A_Msk (0x70000UL) /*!< OCM3AFLT3A (Bitfield-Mask: 0x07) */ +#define ATIM_FLTR_CCP2B_Pos (15UL) /*!< CCP2B (Bit 15) */ +#define ATIM_FLTR_CCP2B_Msk (0x8000UL) /*!< CCP2B (Bitfield-Mask: 0x01) */ +#define ATIM_FLTR_OCM2BFLT2B_Pos (12UL) /*!< OCM2BFLT2B (Bit 12) */ +#define ATIM_FLTR_OCM2BFLT2B_Msk (0x7000UL) /*!< OCM2BFLT2B (Bitfield-Mask: 0x07) */ +#define ATIM_FLTR_CCP2A_Pos (11UL) /*!< CCP2A (Bit 11) */ +#define ATIM_FLTR_CCP2A_Msk (0x800UL) /*!< CCP2A (Bitfield-Mask: 0x01) */ +#define ATIM_FLTR_OCM2AFLT2A_Pos (8UL) /*!< OCM2AFLT2A (Bit 8) */ +#define ATIM_FLTR_OCM2AFLT2A_Msk (0x700UL) /*!< OCM2AFLT2A (Bitfield-Mask: 0x07) */ +#define ATIM_FLTR_CCP1B_Pos (7UL) /*!< CCP1B (Bit 7) */ +#define ATIM_FLTR_CCP1B_Msk (0x80UL) /*!< CCP1B (Bitfield-Mask: 0x01) */ +#define ATIM_FLTR_OCM1BFLT1B_Pos (4UL) /*!< OCM1BFLT1B (Bit 4) */ +#define ATIM_FLTR_OCM1BFLT1B_Msk (0x70UL) /*!< OCM1BFLT1B (Bitfield-Mask: 0x07) */ +#define ATIM_FLTR_CCP1A_Pos (3UL) /*!< CCP1A (Bit 3) */ +#define ATIM_FLTR_CCP1A_Msk (0x8UL) /*!< CCP1A (Bitfield-Mask: 0x01) */ +#define ATIM_FLTR_OCM1AFLT1A_Pos (0UL) /*!< OCM1AFLT1A (Bit 0) */ +#define ATIM_FLTR_OCM1AFLT1A_Msk (0x7UL) /*!< OCM1AFLT1A (Bitfield-Mask: 0x07) */ +/* ========================================================= TRIG ========================================================== */ +#define ATIM_TRIG_ADTE_Pos (7UL) /*!< ADTE (Bit 7) */ +#define ATIM_TRIG_ADTE_Msk (0x80UL) /*!< ADTE (Bitfield-Mask: 0x01) */ +#define ATIM_TRIG_CM3BE_Pos (6UL) /*!< CM3BE (Bit 6) */ +#define ATIM_TRIG_CM3BE_Msk (0x40UL) /*!< CM3BE (Bitfield-Mask: 0x01) */ +#define ATIM_TRIG_CM2BE_Pos (5UL) /*!< CM2BE (Bit 5) */ +#define ATIM_TRIG_CM2BE_Msk (0x20UL) /*!< CM2BE (Bitfield-Mask: 0x01) */ +#define ATIM_TRIG_CM1BE_Pos (4UL) /*!< CM1BE (Bit 4) */ +#define ATIM_TRIG_CM1BE_Msk (0x10UL) /*!< CM1BE (Bitfield-Mask: 0x01) */ +#define ATIM_TRIG_CM3AE_Pos (3UL) /*!< CM3AE (Bit 3) */ +#define ATIM_TRIG_CM3AE_Msk (0x8UL) /*!< CM3AE (Bitfield-Mask: 0x01) */ +#define ATIM_TRIG_CM2AE_Pos (2UL) /*!< CM2AE (Bit 2) */ +#define ATIM_TRIG_CM2AE_Msk (0x4UL) /*!< CM2AE (Bitfield-Mask: 0x01) */ +#define ATIM_TRIG_CM1AE_Pos (1UL) /*!< CM1AE (Bit 1) */ +#define ATIM_TRIG_CM1AE_Msk (0x2UL) /*!< CM1AE (Bitfield-Mask: 0x01) */ +#define ATIM_TRIG_UEVE_Pos (0UL) /*!< UEVE (Bit 0) */ +#define ATIM_TRIG_UEVE_Msk (0x1UL) /*!< UEVE (Bitfield-Mask: 0x01) */ +/* ========================================================= CH1CR ========================================================= */ +#define ATIM_CH1CR_CCGB_Pos (15UL) /*!< CCGB (Bit 15) */ +#define ATIM_CH1CR_CCGB_Msk (0x8000UL) /*!< CCGB (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_CCGA_Pos (14UL) /*!< CCGA (Bit 14) */ +#define ATIM_CH1CR_CCGA_Msk (0x4000UL) /*!< CCGA (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_CISB_Pos (12UL) /*!< CISB (Bit 12) */ +#define ATIM_CH1CR_CISB_Msk (0x3000UL) /*!< CISB (Bitfield-Mask: 0x03) */ +#define ATIM_CH1CR_CDEB_Pos (11UL) /*!< CDEB (Bit 11) */ +#define ATIM_CH1CR_CDEB_Msk (0x800UL) /*!< CDEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_CDEA_Pos (10UL) /*!< CDEA (Bit 10) */ +#define ATIM_CH1CR_CDEA_Msk (0x400UL) /*!< CDEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_CIEB_Pos (9UL) /*!< CIEB (Bit 9) */ +#define ATIM_CH1CR_CIEB_Msk (0x200UL) /*!< CIEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_CIEA_Pos (8UL) /*!< CIEA (Bit 8) */ +#define ATIM_CH1CR_CIEA_Msk (0x100UL) /*!< CIEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_BUFEB_Pos (7UL) /*!< BUFEB (Bit 7) */ +#define ATIM_CH1CR_BUFEB_Msk (0x80UL) /*!< BUFEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_BUFEA_Pos (6UL) /*!< BUFEA (Bit 6) */ +#define ATIM_CH1CR_BUFEA_Msk (0x40UL) /*!< BUFEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_CSB_Pos (5UL) /*!< CSB (Bit 5) */ +#define ATIM_CH1CR_CSB_Msk (0x20UL) /*!< CSB (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_CSA_Pos (4UL) /*!< CSA (Bit 4) */ +#define ATIM_CH1CR_CSA_Msk (0x10UL) /*!< CSA (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_BKSB_Pos (2UL) /*!< BKSB (Bit 2) */ +#define ATIM_CH1CR_BKSB_Msk (0xcUL) /*!< BKSB (Bitfield-Mask: 0x03) */ +#define ATIM_CH1CR_BKSA_Pos (0UL) /*!< BKSA (Bit 0) */ +#define ATIM_CH1CR_BKSA_Msk (0x3UL) /*!< BKSA (Bitfield-Mask: 0x03) */ +/* ========================================================= CH2CR ========================================================= */ +#define ATIM_CH2CR_CCGB_Pos (15UL) /*!< CCGB (Bit 15) */ +#define ATIM_CH2CR_CCGB_Msk (0x8000UL) /*!< CCGB (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_CCGA_Pos (14UL) /*!< CCGA (Bit 14) */ +#define ATIM_CH2CR_CCGA_Msk (0x4000UL) /*!< CCGA (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_CISB_Pos (12UL) /*!< CISB (Bit 12) */ +#define ATIM_CH2CR_CISB_Msk (0x3000UL) /*!< CISB (Bitfield-Mask: 0x03) */ +#define ATIM_CH2CR_CDEB_Pos (11UL) /*!< CDEB (Bit 11) */ +#define ATIM_CH2CR_CDEB_Msk (0x800UL) /*!< CDEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_CDEA_Pos (10UL) /*!< CDEA (Bit 10) */ +#define ATIM_CH2CR_CDEA_Msk (0x400UL) /*!< CDEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_CIEB_Pos (9UL) /*!< CIEB (Bit 9) */ +#define ATIM_CH2CR_CIEB_Msk (0x200UL) /*!< CIEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_CIEA_Pos (8UL) /*!< CIEA (Bit 8) */ +#define ATIM_CH2CR_CIEA_Msk (0x100UL) /*!< CIEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_BUFEB_Pos (7UL) /*!< BUFEB (Bit 7) */ +#define ATIM_CH2CR_BUFEB_Msk (0x80UL) /*!< BUFEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_BUFEA_Pos (6UL) /*!< BUFEA (Bit 6) */ +#define ATIM_CH2CR_BUFEA_Msk (0x40UL) /*!< BUFEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_CSB_Pos (5UL) /*!< CSB (Bit 5) */ +#define ATIM_CH2CR_CSB_Msk (0x20UL) /*!< CSB (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_CSA_Pos (4UL) /*!< CSA (Bit 4) */ +#define ATIM_CH2CR_CSA_Msk (0x10UL) /*!< CSA (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_BKSB_Pos (2UL) /*!< BKSB (Bit 2) */ +#define ATIM_CH2CR_BKSB_Msk (0xcUL) /*!< BKSB (Bitfield-Mask: 0x03) */ +#define ATIM_CH2CR_BKSA_Pos (0UL) /*!< BKSA (Bit 0) */ +#define ATIM_CH2CR_BKSA_Msk (0x3UL) /*!< BKSA (Bitfield-Mask: 0x03) */ +/* ========================================================= CH3CR ========================================================= */ +#define ATIM_CH3CR_CCGB_Pos (15UL) /*!< CCGB (Bit 15) */ +#define ATIM_CH3CR_CCGB_Msk (0x8000UL) /*!< CCGB (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_CCGA_Pos (14UL) /*!< CCGA (Bit 14) */ +#define ATIM_CH3CR_CCGA_Msk (0x4000UL) /*!< CCGA (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_CISB_Pos (12UL) /*!< CISB (Bit 12) */ +#define ATIM_CH3CR_CISB_Msk (0x3000UL) /*!< CISB (Bitfield-Mask: 0x03) */ +#define ATIM_CH3CR_CDEB_Pos (11UL) /*!< CDEB (Bit 11) */ +#define ATIM_CH3CR_CDEB_Msk (0x800UL) /*!< CDEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_CDEA_Pos (10UL) /*!< CDEA (Bit 10) */ +#define ATIM_CH3CR_CDEA_Msk (0x400UL) /*!< CDEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_CIEB_Pos (9UL) /*!< CIEB (Bit 9) */ +#define ATIM_CH3CR_CIEB_Msk (0x200UL) /*!< CIEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_CIEA_Pos (8UL) /*!< CIEA (Bit 8) */ +#define ATIM_CH3CR_CIEA_Msk (0x100UL) /*!< CIEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_BUFEB_Pos (7UL) /*!< BUFEB (Bit 7) */ +#define ATIM_CH3CR_BUFEB_Msk (0x80UL) /*!< BUFEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_BUFEA_Pos (6UL) /*!< BUFEA (Bit 6) */ +#define ATIM_CH3CR_BUFEA_Msk (0x40UL) /*!< BUFEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_CSB_Pos (5UL) /*!< CSB (Bit 5) */ +#define ATIM_CH3CR_CSB_Msk (0x20UL) /*!< CSB (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_CSA_Pos (4UL) /*!< CSA (Bit 4) */ +#define ATIM_CH3CR_CSA_Msk (0x10UL) /*!< CSA (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_BKSB_Pos (2UL) /*!< BKSB (Bit 2) */ +#define ATIM_CH3CR_BKSB_Msk (0xcUL) /*!< BKSB (Bitfield-Mask: 0x03) */ +#define ATIM_CH3CR_BKSA_Pos (0UL) /*!< BKSA (Bit 0) */ +#define ATIM_CH3CR_BKSA_Msk (0x3UL) /*!< BKSA (Bitfield-Mask: 0x03) */ +/* ========================================================= CH4CR ========================================================= */ +#define ATIM_CH4CR_C4EN_Pos (5UL) /*!< C4EN (Bit 5) */ +#define ATIM_CH4CR_C4EN_Msk (0x20UL) /*!< C4EN (Bitfield-Mask: 0x01) */ +#define ATIM_CH4CR_CIS_Pos (3UL) /*!< CIS (Bit 3) */ +#define ATIM_CH4CR_CIS_Msk (0x18UL) /*!< CIS (Bitfield-Mask: 0x03) */ +#define ATIM_CH4CR_CDE_Pos (2UL) /*!< CDE (Bit 2) */ +#define ATIM_CH4CR_CDE_Msk (0x4UL) /*!< CDE (Bitfield-Mask: 0x01) */ +#define ATIM_CH4CR_CIE_Pos (1UL) /*!< CIE (Bit 1) */ +#define ATIM_CH4CR_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ +#define ATIM_CH4CR_BUFE_Pos (0UL) /*!< BUFE (Bit 0) */ +#define ATIM_CH4CR_BUFE_Msk (0x1UL) /*!< BUFE (Bitfield-Mask: 0x01) */ +/* ========================================================== DTR ========================================================== */ +#define ATIM_DTR_VCE_Pos (14UL) /*!< VCE (Bit 14) */ +#define ATIM_DTR_VCE_Msk (0x4000UL) /*!< VCE (Bitfield-Mask: 0x01) */ +#define ATIM_DTR_SAFEEN_Pos (13UL) /*!< SAFEEN (Bit 13) */ +#define ATIM_DTR_SAFEEN_Msk (0x2000UL) /*!< SAFEEN (Bitfield-Mask: 0x01) */ +#define ATIM_DTR_MOE_Pos (12UL) /*!< MOE (Bit 12) */ +#define ATIM_DTR_MOE_Msk (0x1000UL) /*!< MOE (Bitfield-Mask: 0x01) */ +#define ATIM_DTR_AOE_Pos (11UL) /*!< AOE (Bit 11) */ +#define ATIM_DTR_AOE_Msk (0x800UL) /*!< AOE (Bitfield-Mask: 0x01) */ +#define ATIM_DTR_BKE_Pos (10UL) /*!< BKE (Bit 10) */ +#define ATIM_DTR_BKE_Msk (0x400UL) /*!< BKE (Bitfield-Mask: 0x01) */ +#define ATIM_DTR_DTEN_Pos (9UL) /*!< DTEN (Bit 9) */ +#define ATIM_DTR_DTEN_Msk (0x200UL) /*!< DTEN (Bitfield-Mask: 0x01) */ +#define ATIM_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */ +#define ATIM_DTR_DTR_Msk (0xffUL) /*!< DTR (Bitfield-Mask: 0xff) */ +/* ========================================================== RCR ========================================================== */ +#define ATIM_RCR_UD_Pos (9UL) /*!< UD (Bit 9) */ +#define ATIM_RCR_UD_Msk (0x200UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define ATIM_RCR_OV_Pos (8UL) /*!< OV (Bit 8) */ +#define ATIM_RCR_OV_Msk (0x100UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define ATIM_RCR_RCR_Pos (0UL) /*!< RCR (Bit 0) */ +#define ATIM_RCR_RCR_Msk (0xffUL) /*!< RCR (Bitfield-Mask: 0xff) */ +/* ======================================================== CH1CCRA ======================================================== */ +#define ATIM_CH1CCRA_CCR1A_Pos (0UL) /*!< CCR1A (Bit 0) */ +#define ATIM_CH1CCRA_CCR1A_Msk (0xffffUL) /*!< CCR1A (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH1CCRB ======================================================== */ +#define ATIM_CH1CCRB_CCR1B_Pos (0UL) /*!< CCR1B (Bit 0) */ +#define ATIM_CH1CCRB_CCR1B_Msk (0xffffUL) /*!< CCR1B (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH2CCRA ======================================================== */ +#define ATIM_CH2CCRA_CCR2A_Pos (0UL) /*!< CCR2A (Bit 0) */ +#define ATIM_CH2CCRA_CCR2A_Msk (0xffffUL) /*!< CCR2A (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH2CCRB ======================================================== */ +#define ATIM_CH2CCRB_CCR2B_Pos (0UL) /*!< CCR2B (Bit 0) */ +#define ATIM_CH2CCRB_CCR2B_Msk (0xffffUL) /*!< CCR2B (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH3CCRA ======================================================== */ +#define ATIM_CH3CCRA_CCR3A_Pos (0UL) /*!< CCR3A (Bit 0) */ +#define ATIM_CH3CCRA_CCR3A_Msk (0xffffUL) /*!< CCR3A (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH3CCRB ======================================================== */ +#define ATIM_CH3CCRB_CCR3B_Pos (0UL) /*!< CCR3B (Bit 0) */ +#define ATIM_CH3CCRB_CCR3B_Msk (0xffffUL) /*!< CCR3B (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH4CCR ========================================================= */ +#define ATIM_CH4CCR_CCR4_Pos (0UL) /*!< CCR4 (Bit 0) */ +#define ATIM_CH4CCR_CCR4_Msk (0xffffUL) /*!< CCR4 (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ AWT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define AWT_CR_SRC_Pos (8UL) /*!< SRC (Bit 8) */ +#define AWT_CR_SRC_Msk (0x700UL) /*!< SRC (Bitfield-Mask: 0x07) */ +#define AWT_CR_PRS_Pos (4UL) /*!< PRS (Bit 4) */ +#define AWT_CR_PRS_Msk (0xf0UL) /*!< PRS (Bitfield-Mask: 0x0f) */ +#define AWT_CR_MD_Pos (1UL) /*!< MD (Bit 1) */ +#define AWT_CR_MD_Msk (0x6UL) /*!< MD (Bitfield-Mask: 0x03) */ +#define AWT_CR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define AWT_CR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== ARR ========================================================== */ +#define AWT_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define AWT_ARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ========================================================== CNT ========================================================== */ +#define AWT_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define AWT_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== IER ========================================================== */ +#define AWT_IER_UD_Pos (3UL) /*!< UD (Bit 3) */ +#define AWT_IER_UD_Msk (0x8UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define AWT_ISR_UD_Pos (3UL) /*!< UD (Bit 3) */ +#define AWT_ISR_UD_Msk (0x8UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define AWT_ICR_UD_Pos (3UL) /*!< UD (Bit 3) */ +#define AWT_ICR_UD_Msk (0x8UL) /*!< UD (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ BTIM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ARR ========================================================== */ +#define BTIMx_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define BTIMx_ARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ========================================================== CNT ========================================================== */ +#define BTIMx_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define BTIMx_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== ACR ========================================================== */ +#define BTIMx_ACR_ETRFLT_Pos (4UL) /*!< ETRFLT (Bit 4) */ +#define BTIMx_ACR_ETRFLT_Msk (0x70UL) /*!< ETRFLT (Bitfield-Mask: 0x07) */ +/* ========================================================== BCR ========================================================== */ +#define BTIMx_BCR_PRSSTATUS_Pos (11UL) /*!< PRSSTATUS (Bit 11) */ +#define BTIMx_BCR_PRSSTATUS_Msk (0x7800UL) /*!< PRSSTATUS (Bitfield-Mask: 0x0f) */ +#define BTIMx_BCR_PRS_Pos (7UL) /*!< PRS (Bit 7) */ +#define BTIMx_BCR_PRS_Msk (0x780UL) /*!< PRS (Bitfield-Mask: 0x0f) */ +#define BTIMx_BCR_TOGEN_Pos (6UL) /*!< TOGEN (Bit 6) */ +#define BTIMx_BCR_TOGEN_Msk (0x40UL) /*!< TOGEN (Bitfield-Mask: 0x01) */ +#define BTIMx_BCR_ONESHOT_Pos (5UL) /*!< ONESHOT (Bit 5) */ +#define BTIMx_BCR_ONESHOT_Msk (0x20UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ +#define BTIMx_BCR_POL_Pos (4UL) /*!< POL (Bit 4) */ +#define BTIMx_BCR_POL_Msk (0x10UL) /*!< POL (Bitfield-Mask: 0x01) */ +#define BTIMx_BCR_TRS_Pos (3UL) /*!< TRS (Bit 3) */ +#define BTIMx_BCR_TRS_Msk (0x8UL) /*!< TRS (Bitfield-Mask: 0x01) */ +#define BTIMx_BCR_MODE_Pos (1UL) /*!< MODE (Bit 1) */ +#define BTIMx_BCR_MODE_Msk (0x6UL) /*!< MODE (Bitfield-Mask: 0x03) */ +#define BTIMx_BCR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define BTIMx_BCR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define BTIMx_IER_TOP_Pos (2UL) /*!< TOP (Bit 2) */ +#define BTIMx_IER_TOP_Msk (0x4UL) /*!< TOP (Bitfield-Mask: 0x01) */ +#define BTIMx_IER_TI_Pos (1UL) /*!< TI (Bit 1) */ +#define BTIMx_IER_TI_Msk (0x2UL) /*!< TI (Bitfield-Mask: 0x01) */ +#define BTIMx_IER_OV_Pos (0UL) /*!< OV (Bit 0) */ +#define BTIMx_IER_OV_Msk (0x1UL) /*!< OV (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define BTIMx_ISR_TOP_Pos (2UL) /*!< TOP (Bit 2) */ +#define BTIMx_ISR_TOP_Msk (0x4UL) /*!< TOP (Bitfield-Mask: 0x01) */ +#define BTIMx_ISR_TI_Pos (1UL) /*!< TI (Bit 1) */ +#define BTIMx_ISR_TI_Msk (0x2UL) /*!< TI (Bitfield-Mask: 0x01) */ +#define BTIMx_ISR_OV_Pos (0UL) /*!< OV (Bit 0) */ +#define BTIMx_ISR_OV_Msk (0x1UL) /*!< OV (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define BTIMx_ICR_TOP_Pos (2UL) /*!< TOP (Bit 2) */ +#define BTIMx_ICR_TOP_Msk (0x4UL) /*!< TOP (Bitfield-Mask: 0x01) */ +#define BTIMx_ICR_TI_Pos (1UL) /*!< TI (Bit 1) */ +#define BTIMx_ICR_TI_Msk (0x2UL) /*!< TI (Bitfield-Mask: 0x01) */ +#define BTIMx_ICR_OV_Pos (0UL) /*!< OV (Bit 0) */ +#define BTIMx_ICR_OV_Msk (0x1UL) /*!< OV (Bitfield-Mask: 0x01) */ +/* ========================================================== DMA ========================================================== */ +#define BTIMx_DMA_TRS_Pos (1UL) /*!< TRS (Bit 1) */ +#define BTIMx_DMA_TRS_Msk (0x2UL) /*!< TRS (Bitfield-Mask: 0x01) */ +#define BTIMx_DMA_OV_Pos (0UL) /*!< OV (Bit 0) */ +#define BTIMx_DMA_OV_Msk (0x1UL) /*!< OV (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ CRC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define CRC_CR_MODE_Pos (0UL) /*!< MODE (Bit 0) */ +#define CRC_CR_MODE_Msk (0xfUL) /*!< MODE (Bitfield-Mask: 0x0f) */ +/* ========================================================= DR32 ========================================================== */ +#define CRC_DR32_DR32_Pos (0UL) /*!< DR32 (Bit 0) */ +#define CRC_DR32_DR32_Msk (0xffffffffUL) /*!< DR32 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DR16 ========================================================== */ +#define CRC_DR16_DR16_Pos (0UL) /*!< DR16 (Bit 0) */ +#define CRC_DR16_DR16_Msk (0xffffUL) /*!< DR16 (Bitfield-Mask: 0xffff) */ +/* ========================================================== DR8 ========================================================== */ +#define CRC_DR8_DR8_Pos (0UL) /*!< DR8 (Bit 0) */ +#define CRC_DR8_DR8_Msk (0xffUL) /*!< DR8 (Bitfield-Mask: 0xff) */ +/* ======================================================= RESULT32 ======================================================== */ +#define CRC_RESULT32_RESULT32_Pos (0UL) /*!< RESULT32 (Bit 0) */ +#define CRC_RESULT32_RESULT32_Msk (0xffffffffUL) /*!< RESULT32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= RESULT16 ======================================================== */ +#define CRC_RESULT16_RESULT16_Pos (0UL) /*!< RESULT16 (Bit 0) */ +#define CRC_RESULT16_RESULT16_Msk (0xffffUL) /*!< RESULT16 (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ISR ========================================================== */ +#define DMA_ISR_TE5_Pos (17UL) /*!< TE5 (Bit 17) */ +#define DMA_ISR_TE5_Msk (0x20000UL) /*!< TE5 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC5_Pos (16UL) /*!< TC5 (Bit 16) */ +#define DMA_ISR_TC5_Msk (0x10000UL) /*!< TC5 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TE4_Pos (13UL) /*!< TE4 (Bit 13) */ +#define DMA_ISR_TE4_Msk (0x2000UL) /*!< TE4 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC4_Pos (12UL) /*!< TC4 (Bit 12) */ +#define DMA_ISR_TC4_Msk (0x1000UL) /*!< TC4 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TE3_Pos (9UL) /*!< TE3 (Bit 9) */ +#define DMA_ISR_TE3_Msk (0x200UL) /*!< TE3 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC3_Pos (8UL) /*!< TC3 (Bit 8) */ +#define DMA_ISR_TC3_Msk (0x100UL) /*!< TC3 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TE2_Pos (5UL) /*!< TE2 (Bit 5) */ +#define DMA_ISR_TE2_Msk (0x20UL) /*!< TE2 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC2_Pos (4UL) /*!< TC2 (Bit 4) */ +#define DMA_ISR_TC2_Msk (0x10UL) /*!< TC2 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TE1_Pos (1UL) /*!< TE1 (Bit 1) */ +#define DMA_ISR_TE1_Msk (0x2UL) /*!< TE1 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC1_Pos (0UL) /*!< TC1 (Bit 0) */ +#define DMA_ISR_TC1_Msk (0x1UL) /*!< TC1 (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define DMA_ICR_TE5_Pos (17UL) /*!< TE5 (Bit 17) */ +#define DMA_ICR_TE5_Msk (0x20000UL) /*!< TE5 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC5_Pos (16UL) /*!< TC5 (Bit 16) */ +#define DMA_ICR_TC5_Msk (0x10000UL) /*!< TC5 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TE4_Pos (13UL) /*!< TE4 (Bit 13) */ +#define DMA_ICR_TE4_Msk (0x2000UL) /*!< TE4 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC4_Pos (12UL) /*!< TC4 (Bit 12) */ +#define DMA_ICR_TC4_Msk (0x1000UL) /*!< TC4 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TE3_Pos (9UL) /*!< TE3 (Bit 9) */ +#define DMA_ICR_TE3_Msk (0x200UL) /*!< TE3 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC3_Pos (8UL) /*!< TC3 (Bit 8) */ +#define DMA_ICR_TC3_Msk (0x100UL) /*!< TC3 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TE2_Pos (5UL) /*!< TE2 (Bit 5) */ +#define DMA_ICR_TE2_Msk (0x20UL) /*!< TE2 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC2_Pos (4UL) /*!< TC2 (Bit 4) */ +#define DMA_ICR_TC2_Msk (0x10UL) /*!< TC2 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TE1_Pos (1UL) /*!< TE1 (Bit 1) */ +#define DMA_ICR_TE1_Msk (0x2UL) /*!< TE1 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC1_Pos (0UL) /*!< TC1 (Bit 0) */ +#define DMA_ICR_TC1_Msk (0x1UL) /*!< TC1 (Bitfield-Mask: 0x01) */ +/* ========================================================= CSR1 ========================================================== */ +#define DMA_CSR1_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR1_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR1_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR1_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR1_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR1_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR1_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR1_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR1_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR1_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR1_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT1 ========================================================== */ +#define DMA_CNT1_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT1_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT1_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT1_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR1 ======================================================== */ +#define DMA_SRCADDR1_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR1_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR1 ======================================================== */ +#define DMA_DSTADDR1_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR1_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG1 ========================================================= */ +#define DMA_TRIG1_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG1_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG1_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG1_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG1_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG1_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CSR2 ========================================================== */ +#define DMA_CSR2_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR2_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR2_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR2_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR2_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR2_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR2_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR2_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR2_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR2_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR2_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT2 ========================================================== */ +#define DMA_CNT2_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT2_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT2_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT2_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR2 ======================================================== */ +#define DMA_SRCADDR2_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR2_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR2 ======================================================== */ +#define DMA_DSTADDR2_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR2_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG2 ========================================================= */ +#define DMA_TRIG2_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG2_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG2_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG2_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG2_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG2_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CSR3 ========================================================== */ +#define DMA_CSR3_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR3_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR3_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR3_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR3_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR3_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR3_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR3_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR3_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR3_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR3_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT3 ========================================================== */ +#define DMA_CNT3_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT3_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT3_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT3_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR3 ======================================================== */ +#define DMA_SRCADDR3_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR3_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR3 ======================================================== */ +#define DMA_DSTADDR3_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR3_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG3 ========================================================= */ +#define DMA_TRIG3_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG3_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG3_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG3_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG3_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG3_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CSR4 ========================================================== */ +#define DMA_CSR4_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR4_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR4_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR4_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR4_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR4_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR4_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR4_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR4_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR4_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR4_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT4 ========================================================== */ +#define DMA_CNT4_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT4_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT4_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT4_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR4 ======================================================== */ +#define DMA_SRCADDR4_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR4_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR4 ======================================================== */ +#define DMA_DSTADDR4_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR4_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG4 ========================================================= */ +#define DMA_TRIG4_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG4_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG4_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG4_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG4_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG4_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CSR5 ========================================================== */ +#define DMA_CSR5_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR5_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR5_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR5_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR5_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR5_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR5_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR5_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR5_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR5_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR5_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR5_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR5_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR5_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR5_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR5_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT5 ========================================================== */ +#define DMA_CNT5_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT5_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT5_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT5_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR5 ======================================================== */ +#define DMA_SRCADDR5_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR5_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR5 ======================================================== */ +#define DMA_DSTADDR5_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR5_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG5 ========================================================= */ +#define DMA_TRIG5_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG5_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG5_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG5_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG5_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG5_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ DMACHANNEL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CSR ========================================================== */ +#define DMACHx_CSR_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMACHx_CSR_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMACHx_CSR_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMACHx_CSR_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMACHx_CSR_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMACHx_CSR_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMACHx_CSR_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMACHx_CSR_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMACHx_CSR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMACHx_CSR_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMACHx_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +#define DMACHx_CNT_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMACHx_CNT_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMACHx_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMACHx_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================== SRCADDR ======================================================== */ +#define DMACHx_SRCADDR_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMACHx_SRCADDR_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DSTADDR ======================================================== */ +#define DMACHx_DSTADDR_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMACHx_DSTADDR_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG ========================================================== */ +#define DMACHx_TRIG_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMACHx_TRIG_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMACHx_TRIG_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMACHx_TRIG_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMACHx_TRIG_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMACHx_TRIG_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ FLASH ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define FLASH_CR1_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define FLASH_CR1_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define FLASH_CR1_SECURITY_Pos (6UL) /*!< SECURITY (Bit 6) */ +#define FLASH_CR1_SECURITY_Msk (0xc0UL) /*!< SECURITY (Bitfield-Mask: 0x03) */ +#define FLASH_CR1_BUSY_Pos (5UL) /*!< BUSY (Bit 5) */ +#define FLASH_CR1_BUSY_Msk (0x20UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define FLASH_CR1_STANDBY_Pos (4UL) /*!< STANDBY (Bit 4) */ +#define FLASH_CR1_STANDBY_Msk (0x10UL) /*!< STANDBY (Bitfield-Mask: 0x01) */ +#define FLASH_CR1_MODE_Pos (0UL) /*!< MODE (Bit 0) */ +#define FLASH_CR1_MODE_Msk (0x3UL) /*!< MODE (Bitfield-Mask: 0x03) */ +/* ========================================================== CR2 ========================================================== */ +#define FLASH_CR2_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define FLASH_CR2_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define FLASH_CR2_CACHE_Pos (4UL) /*!< CACHE (Bit 4) */ +#define FLASH_CR2_CACHE_Msk (0x10UL) /*!< CACHE (Bitfield-Mask: 0x01) */ +#define FLASH_CR2_FETCH_Pos (3UL) /*!< FETCH (Bit 3) */ +#define FLASH_CR2_FETCH_Msk (0x8UL) /*!< FETCH (Bitfield-Mask: 0x01) */ +#define FLASH_CR2_WAIT_Pos (0UL) /*!< WAIT (Bit 0) */ +#define FLASH_CR2_WAIT_Msk (0x7UL) /*!< WAIT (Bitfield-Mask: 0x07) */ +/* ======================================================= PAGELOCK ======================================================== */ +#define FLASH_PAGELOCK_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define FLASH_PAGELOCK_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define FLASH_PAGELOCK_LOCK15_Pos (15UL) /*!< LOCK15 (Bit 15) */ +#define FLASH_PAGELOCK_LOCK15_Msk (0x8000UL) /*!< LOCK15 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK14_Pos (14UL) /*!< LOCK14 (Bit 14) */ +#define FLASH_PAGELOCK_LOCK14_Msk (0x4000UL) /*!< LOCK14 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK13_Pos (13UL) /*!< LOCK13 (Bit 13) */ +#define FLASH_PAGELOCK_LOCK13_Msk (0x2000UL) /*!< LOCK13 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK12_Pos (12UL) /*!< LOCK12 (Bit 12) */ +#define FLASH_PAGELOCK_LOCK12_Msk (0x1000UL) /*!< LOCK12 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK11_Pos (11UL) /*!< LOCK11 (Bit 11) */ +#define FLASH_PAGELOCK_LOCK11_Msk (0x800UL) /*!< LOCK11 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK10_Pos (10UL) /*!< LOCK10 (Bit 10) */ +#define FLASH_PAGELOCK_LOCK10_Msk (0x400UL) /*!< LOCK10 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK9_Pos (9UL) /*!< LOCK9 (Bit 9) */ +#define FLASH_PAGELOCK_LOCK9_Msk (0x200UL) /*!< LOCK9 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK8_Pos (8UL) /*!< LOCK8 (Bit 8) */ +#define FLASH_PAGELOCK_LOCK8_Msk (0x100UL) /*!< LOCK8 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK7_Pos (7UL) /*!< LOCK7 (Bit 7) */ +#define FLASH_PAGELOCK_LOCK7_Msk (0x80UL) /*!< LOCK7 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK6_Pos (6UL) /*!< LOCK6 (Bit 6) */ +#define FLASH_PAGELOCK_LOCK6_Msk (0x40UL) /*!< LOCK6 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK5_Pos (5UL) /*!< LOCK5 (Bit 5) */ +#define FLASH_PAGELOCK_LOCK5_Msk (0x20UL) /*!< LOCK5 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK4_Pos (4UL) /*!< LOCK4 (Bit 4) */ +#define FLASH_PAGELOCK_LOCK4_Msk (0x10UL) /*!< LOCK4 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK3_Pos (3UL) /*!< LOCK3 (Bit 3) */ +#define FLASH_PAGELOCK_LOCK3_Msk (0x8UL) /*!< LOCK3 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK2_Pos (2UL) /*!< LOCK2 (Bit 2) */ +#define FLASH_PAGELOCK_LOCK2_Msk (0x4UL) /*!< LOCK2 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK1_Pos (1UL) /*!< LOCK1 (Bit 1) */ +#define FLASH_PAGELOCK_LOCK1_Msk (0x2UL) /*!< LOCK1 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK0_Pos (0UL) /*!< LOCK0 (Bit 0) */ +#define FLASH_PAGELOCK_LOCK0_Msk (0x1UL) /*!< LOCK0 (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define FLASH_IER_PROG_Pos (4UL) /*!< PROG (Bit 4) */ +#define FLASH_IER_PROG_Msk (0x10UL) /*!< PROG (Bitfield-Mask: 0x01) */ +#define FLASH_IER_PAGELOCK_Pos (1UL) /*!< PAGELOCK (Bit 1) */ +#define FLASH_IER_PAGELOCK_Msk (0x2UL) /*!< PAGELOCK (Bitfield-Mask: 0x01) */ +#define FLASH_IER_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define FLASH_IER_PC_Msk (0x1UL) /*!< PC (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define FLASH_ISR_PROG_Pos (4UL) /*!< PROG (Bit 4) */ +#define FLASH_ISR_PROG_Msk (0x10UL) /*!< PROG (Bitfield-Mask: 0x01) */ +#define FLASH_ISR_PAGELOCK_Pos (1UL) /*!< PAGELOCK (Bit 1) */ +#define FLASH_ISR_PAGELOCK_Msk (0x2UL) /*!< PAGELOCK (Bitfield-Mask: 0x01) */ +#define FLASH_ISR_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define FLASH_ISR_PC_Msk (0x1UL) /*!< PC (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define FLASH_ICR_PROG_Pos (4UL) /*!< PROG (Bit 4) */ +#define FLASH_ICR_PROG_Msk (0x10UL) /*!< PROG (Bitfield-Mask: 0x01) */ +#define FLASH_ICR_PAGELOCK_Pos (1UL) /*!< PAGELOCK (Bit 1) */ +#define FLASH_ICR_PAGELOCK_Msk (0x2UL) /*!< PAGELOCK (Bitfield-Mask: 0x01) */ +#define FLASH_ICR_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define FLASH_ICR_PC_Msk (0x1UL) /*!< PC (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DIR ========================================================== */ +#define GPIOx_DIR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_DIR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_DIR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_DIR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_DIR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_DIR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_DIR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_DIR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_DIR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_DIR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_DIR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_DIR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_DIR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_DIR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_DIR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_DIR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_DIR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================= OPENDRAIN ======================================================= */ +#define GPIOx_OPENDRAIN_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_OPENDRAIN_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_OPENDRAIN_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_OPENDRAIN_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_OPENDRAIN_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_OPENDRAIN_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_OPENDRAIN_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_OPENDRAIN_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_OPENDRAIN_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_OPENDRAIN_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_OPENDRAIN_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_OPENDRAIN_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_OPENDRAIN_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_OPENDRAIN_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_OPENDRAIN_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_OPENDRAIN_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_OPENDRAIN_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SPEED ========================================================= */ +#define GPIOx_SPEED_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_SPEED_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_SPEED_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_SPEED_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_SPEED_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_SPEED_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_SPEED_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_SPEED_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_SPEED_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_SPEED_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_SPEED_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_SPEED_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_SPEED_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_SPEED_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_SPEED_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_SPEED_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_SPEED_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ +#define GPIOx_PDR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_PDR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_PDR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_PDR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_PDR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_PDR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_PDR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_PDR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_PDR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_PDR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_PDR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_PDR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_PDR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_PDR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_PDR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_PDR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_PDR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== PUR ========================================================== */ +#define GPIOx_PUR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_PUR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_PUR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_PUR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_PUR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_PUR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_PUR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_PUR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_PUR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_PUR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_PUR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_PUR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_PUR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_PUR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_PUR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_PUR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_PUR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= AFRH ========================================================== */ +#define GPIOx_AFRH_AFR15_Pos (28UL) /*!< AFR15 (Bit 28) */ +#define GPIOx_AFRH_AFR15_Msk (0xf0000000UL) /*!< AFR15 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_AFR14_Pos (24UL) /*!< AFR14 (Bit 24) */ +#define GPIOx_AFRH_AFR14_Msk (0xf000000UL) /*!< AFR14 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_AFR13_Pos (20UL) /*!< AFR13 (Bit 20) */ +#define GPIOx_AFRH_AFR13_Msk (0xf00000UL) /*!< AFR13 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_AFR12_Pos (16UL) /*!< AFR12 (Bit 16) */ +#define GPIOx_AFRH_AFR12_Msk (0xf0000UL) /*!< AFR12 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_AFR11_Pos (12UL) /*!< AFR11 (Bit 12) */ +#define GPIOx_AFRH_AFR11_Msk (0xf000UL) /*!< AFR11 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_AFR10_Pos (8UL) /*!< AFR10 (Bit 8) */ +#define GPIOx_AFRH_AFR10_Msk (0xf00UL) /*!< AFR10 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_AFR9_Pos (4UL) /*!< AFR9 (Bit 4) */ +#define GPIOx_AFRH_AFR9_Msk (0xf0UL) /*!< AFR9 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_AFR8_Pos (0UL) /*!< AFR8 (Bit 0) */ +#define GPIOx_AFRH_AFR8_Msk (0xfUL) /*!< AFR8 (Bitfield-Mask: 0x0f) */ +/* ========================================================= AFRL ========================================================== */ +#define GPIOx_AFRL_AFR7_Pos (28UL) /*!< AFR7 (Bit 28) */ +#define GPIOx_AFRL_AFR7_Msk (0xf0000000UL) /*!< AFR7 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_AFR6_Pos (24UL) /*!< AFR6 (Bit 24) */ +#define GPIOx_AFRL_AFR6_Msk (0xf000000UL) /*!< AFR6 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_AFR5_Pos (20UL) /*!< AFR5 (Bit 20) */ +#define GPIOx_AFRL_AFR5_Msk (0xf00000UL) /*!< AFR5 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_AFR4_Pos (16UL) /*!< AFR4 (Bit 16) */ +#define GPIOx_AFRL_AFR4_Msk (0xf0000UL) /*!< AFR4 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_AFR3_Pos (12UL) /*!< AFR3 (Bit 12) */ +#define GPIOx_AFRL_AFR3_Msk (0xf000UL) /*!< AFR3 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_AFR2_Pos (8UL) /*!< AFR2 (Bit 8) */ +#define GPIOx_AFRL_AFR2_Msk (0xf00UL) /*!< AFR2 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_AFR1_Pos (4UL) /*!< AFR1 (Bit 4) */ +#define GPIOx_AFRL_AFR1_Msk (0xf0UL) /*!< AFR1 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_AFR0_Pos (0UL) /*!< AFR0 (Bit 0) */ +#define GPIOx_AFRL_AFR0_Msk (0xfUL) /*!< AFR0 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ANALOG ========================================================= */ +#define GPIOx_ANALOG_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_ANALOG_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_ANALOG_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_ANALOG_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_ANALOG_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_ANALOG_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_ANALOG_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_ANALOG_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_ANALOG_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_ANALOG_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_ANALOG_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_ANALOG_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_ANALOG_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_ANALOG_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_ANALOG_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_ANALOG_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_ANALOG_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DRIVER ========================================================= */ +#define GPIOx_DRIVER_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_DRIVER_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_DRIVER_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_DRIVER_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_DRIVER_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_DRIVER_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_DRIVER_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_DRIVER_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_DRIVER_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_DRIVER_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_DRIVER_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_DRIVER_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_DRIVER_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_DRIVER_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_DRIVER_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_DRIVER_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_DRIVER_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== RISEIE ========================================================= */ +#define GPIOx_RISEIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_RISEIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_RISEIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_RISEIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_RISEIE_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_RISEIE_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_RISEIE_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_RISEIE_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_RISEIE_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_RISEIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_RISEIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_RISEIE_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_RISEIE_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_RISEIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_RISEIE_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_RISEIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_RISEIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FALLIE ========================================================= */ +#define GPIOx_FALLIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_FALLIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_FALLIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_FALLIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_FALLIE_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_FALLIE_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_FALLIE_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_FALLIE_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_FALLIE_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_FALLIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_FALLIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_FALLIE_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_FALLIE_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_FALLIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_FALLIE_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_FALLIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_FALLIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== HIGHIE ========================================================= */ +#define GPIOx_HIGHIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_HIGHIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_HIGHIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_HIGHIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_HIGHIE_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_HIGHIE_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_HIGHIE_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_HIGHIE_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_HIGHIE_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_HIGHIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_HIGHIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_HIGHIE_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_HIGHIE_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_HIGHIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_HIGHIE_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_HIGHIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_HIGHIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= LOWIE ========================================================= */ +#define GPIOx_LOWIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_LOWIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_LOWIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_LOWIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_LOWIE_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_LOWIE_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_LOWIE_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_LOWIE_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_LOWIE_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_LOWIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_LOWIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_LOWIE_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_LOWIE_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_LOWIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_LOWIE_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_LOWIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_LOWIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define GPIOx_ISR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_ISR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_ISR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_ISR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_ISR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_ISR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_ISR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_ISR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_ISR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_ISR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_ISR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_ISR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_ISR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_ISR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_ISR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_ISR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_ISR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define GPIOx_ICR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_ICR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_ICR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_ICR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_ICR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_ICR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_ICR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_ICR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_ICR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_ICR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_ICR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_ICR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_ICR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_ICR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_ICR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_ICR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_ICR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= LOCK ========================================================== */ +#define GPIOx_LOCK_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define GPIOx_LOCK_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define GPIOx_LOCK_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_LOCK_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_LOCK_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_LOCK_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_LOCK_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_LOCK_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_LOCK_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_LOCK_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_LOCK_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_LOCK_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_LOCK_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_LOCK_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_LOCK_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_LOCK_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_LOCK_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_LOCK_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_LOCK_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FILTER ========================================================= */ +#define GPIOx_FILTER_FLTCLK_Pos (16UL) /*!< FLTCLK (Bit 16) */ +#define GPIOx_FILTER_FLTCLK_Msk (0x70000UL) /*!< FLTCLK (Bitfield-Mask: 0x07) */ +#define GPIOx_FILTER_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_FILTER_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_FILTER_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_FILTER_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_FILTER_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_FILTER_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_FILTER_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_FILTER_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_FILTER_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_FILTER_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_FILTER_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_FILTER_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_FILTER_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_FILTER_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_FILTER_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_FILTER_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_FILTER_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== IDR ========================================================== */ +#define GPIOx_IDR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_IDR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_IDR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_IDR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_IDR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_IDR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_IDR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_IDR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_IDR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_IDR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_IDR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_IDR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_IDR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_IDR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_IDR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_IDR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_IDR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ODR ========================================================== */ +#define GPIOx_ODR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_ODR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_ODR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_ODR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_ODR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_ODR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_ODR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_ODR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_ODR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_ODR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_ODR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_ODR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_ODR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_ODR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_ODR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_ODR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_ODR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ====================================================== ODRLOWBYTE ======================================================= */ +#define GPIOx_ODRLOWBYTE_LOWBYTE_Pos (0UL) /*!< LOWBYTE (Bit 0) */ +#define GPIOx_ODRLOWBYTE_LOWBYTE_Msk (0xffUL) /*!< LOWBYTE (Bitfield-Mask: 0xff) */ +/* ====================================================== ODRHIGHBYTE ====================================================== */ +#define GPIOx_ODRHIGHBYTE_HIGHBYTE_Pos (0UL) /*!< HIGHBYTE (Bit 0) */ +#define GPIOx_ODRHIGHBYTE_HIGHBYTE_Msk (0xffUL) /*!< HIGHBYTE (Bitfield-Mask: 0xff) */ +/* ========================================================== BRR ========================================================== */ +#define GPIOx_BRR_BRR15_Pos (15UL) /*!< BRR15 (Bit 15) */ +#define GPIOx_BRR_BRR15_Msk (0x8000UL) /*!< BRR15 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR14_Pos (14UL) /*!< BRR14 (Bit 14) */ +#define GPIOx_BRR_BRR14_Msk (0x4000UL) /*!< BRR14 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR13_Pos (13UL) /*!< BRR13 (Bit 13) */ +#define GPIOx_BRR_BRR13_Msk (0x2000UL) /*!< BRR13 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR12_Pos (12UL) /*!< BRR12 (Bit 12) */ +#define GPIOx_BRR_BRR12_Msk (0x1000UL) /*!< BRR12 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR11_Pos (11UL) /*!< BRR11 (Bit 11) */ +#define GPIOx_BRR_BRR11_Msk (0x800UL) /*!< BRR11 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR10_Pos (10UL) /*!< BRR10 (Bit 10) */ +#define GPIOx_BRR_BRR10_Msk (0x400UL) /*!< BRR10 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR9_Pos (9UL) /*!< BRR9 (Bit 9) */ +#define GPIOx_BRR_BRR9_Msk (0x200UL) /*!< BRR9 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR8_Pos (8UL) /*!< BRR8 (Bit 8) */ +#define GPIOx_BRR_BRR8_Msk (0x100UL) /*!< BRR8 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR7_Pos (7UL) /*!< BRR7 (Bit 7) */ +#define GPIOx_BRR_BRR7_Msk (0x80UL) /*!< BRR7 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR6_Pos (6UL) /*!< BRR6 (Bit 6) */ +#define GPIOx_BRR_BRR6_Msk (0x40UL) /*!< BRR6 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR5_Pos (5UL) /*!< BRR5 (Bit 5) */ +#define GPIOx_BRR_BRR5_Msk (0x20UL) /*!< BRR5 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR4_Pos (4UL) /*!< BRR4 (Bit 4) */ +#define GPIOx_BRR_BRR4_Msk (0x10UL) /*!< BRR4 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR3_Pos (3UL) /*!< BRR3 (Bit 3) */ +#define GPIOx_BRR_BRR3_Msk (0x8UL) /*!< BRR3 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR2_Pos (2UL) /*!< BRR2 (Bit 2) */ +#define GPIOx_BRR_BRR2_Msk (0x4UL) /*!< BRR2 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR1_Pos (1UL) /*!< BRR1 (Bit 1) */ +#define GPIOx_BRR_BRR1_Msk (0x2UL) /*!< BRR1 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR0_Pos (0UL) /*!< BRR0 (Bit 0) */ +#define GPIOx_BRR_BRR0_Msk (0x1UL) /*!< BRR0 (Bitfield-Mask: 0x01) */ +/* ========================================================= BSRR ========================================================== */ +#define GPIOx_BSRR_BRR15_Pos (31UL) /*!< BRR15 (Bit 31) */ +#define GPIOx_BSRR_BRR15_Msk (0x80000000UL) /*!< BRR15 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR14_Pos (30UL) /*!< BRR14 (Bit 30) */ +#define GPIOx_BSRR_BRR14_Msk (0x40000000UL) /*!< BRR14 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR13_Pos (29UL) /*!< BRR13 (Bit 29) */ +#define GPIOx_BSRR_BRR13_Msk (0x20000000UL) /*!< BRR13 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR12_Pos (28UL) /*!< BRR12 (Bit 28) */ +#define GPIOx_BSRR_BRR12_Msk (0x10000000UL) /*!< BRR12 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR11_Pos (27UL) /*!< BRR11 (Bit 27) */ +#define GPIOx_BSRR_BRR11_Msk (0x8000000UL) /*!< BRR11 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR10_Pos (26UL) /*!< BRR10 (Bit 26) */ +#define GPIOx_BSRR_BRR10_Msk (0x4000000UL) /*!< BRR10 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR9_Pos (25UL) /*!< BRR9 (Bit 25) */ +#define GPIOx_BSRR_BRR9_Msk (0x2000000UL) /*!< BRR9 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR8_Pos (24UL) /*!< BRR8 (Bit 24) */ +#define GPIOx_BSRR_BRR8_Msk (0x1000000UL) /*!< BRR8 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR7_Pos (23UL) /*!< BRR7 (Bit 23) */ +#define GPIOx_BSRR_BRR7_Msk (0x800000UL) /*!< BRR7 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR6_Pos (22UL) /*!< BRR6 (Bit 22) */ +#define GPIOx_BSRR_BRR6_Msk (0x400000UL) /*!< BRR6 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR5_Pos (21UL) /*!< BRR5 (Bit 21) */ +#define GPIOx_BSRR_BRR5_Msk (0x200000UL) /*!< BRR5 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR4_Pos (20UL) /*!< BRR4 (Bit 20) */ +#define GPIOx_BSRR_BRR4_Msk (0x100000UL) /*!< BRR4 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR3_Pos (19UL) /*!< BRR3 (Bit 19) */ +#define GPIOx_BSRR_BRR3_Msk (0x80000UL) /*!< BRR3 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR2_Pos (18UL) /*!< BRR2 (Bit 18) */ +#define GPIOx_BSRR_BRR2_Msk (0x40000UL) /*!< BRR2 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR1_Pos (17UL) /*!< BRR1 (Bit 17) */ +#define GPIOx_BSRR_BRR1_Msk (0x20000UL) /*!< BRR1 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR0_Pos (16UL) /*!< BRR0 (Bit 16) */ +#define GPIOx_BSRR_BRR0_Msk (0x10000UL) /*!< BRR0 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS15_Pos (15UL) /*!< BSS15 (Bit 15) */ +#define GPIOx_BSRR_BSS15_Msk (0x8000UL) /*!< BSS15 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS14_Pos (14UL) /*!< BSS14 (Bit 14) */ +#define GPIOx_BSRR_BSS14_Msk (0x4000UL) /*!< BSS14 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS13_Pos (13UL) /*!< BSS13 (Bit 13) */ +#define GPIOx_BSRR_BSS13_Msk (0x2000UL) /*!< BSS13 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS12_Pos (12UL) /*!< BSS12 (Bit 12) */ +#define GPIOx_BSRR_BSS12_Msk (0x1000UL) /*!< BSS12 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS11_Pos (11UL) /*!< BSS11 (Bit 11) */ +#define GPIOx_BSRR_BSS11_Msk (0x800UL) /*!< BSS11 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS10_Pos (10UL) /*!< BSS10 (Bit 10) */ +#define GPIOx_BSRR_BSS10_Msk (0x400UL) /*!< BSS10 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS9_Pos (9UL) /*!< BSS9 (Bit 9) */ +#define GPIOx_BSRR_BSS9_Msk (0x200UL) /*!< BSS9 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS8_Pos (8UL) /*!< BSS8 (Bit 8) */ +#define GPIOx_BSRR_BSS8_Msk (0x100UL) /*!< BSS8 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS7_Pos (7UL) /*!< BSS7 (Bit 7) */ +#define GPIOx_BSRR_BSS7_Msk (0x80UL) /*!< BSS7 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS6_Pos (6UL) /*!< BSS6 (Bit 6) */ +#define GPIOx_BSRR_BSS6_Msk (0x40UL) /*!< BSS6 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS5_Pos (5UL) /*!< BSS5 (Bit 5) */ +#define GPIOx_BSRR_BSS5_Msk (0x20UL) /*!< BSS5 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS4_Pos (4UL) /*!< BSS4 (Bit 4) */ +#define GPIOx_BSRR_BSS4_Msk (0x10UL) /*!< BSS4 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS3_Pos (3UL) /*!< BSS3 (Bit 3) */ +#define GPIOx_BSRR_BSS3_Msk (0x8UL) /*!< BSS3 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS2_Pos (2UL) /*!< BSS2 (Bit 2) */ +#define GPIOx_BSRR_BSS2_Msk (0x4UL) /*!< BSS2 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS1_Pos (1UL) /*!< BSS1 (Bit 1) */ +#define GPIOx_BSRR_BSS1_Msk (0x2UL) /*!< BSS1 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS0_Pos (0UL) /*!< BSS0 (Bit 0) */ +#define GPIOx_BSRR_BSS0_Msk (0x1UL) /*!< BSS0 (Bitfield-Mask: 0x01) */ +/* ========================================================== TOG ========================================================== */ +#define GPIOx_TOG_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_TOG_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_TOG_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_TOG_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_TOG_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_TOG_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_TOG_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_TOG_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_TOG_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_TOG_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_TOG_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_TOG_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_TOG_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_TOG_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_TOG_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_TOG_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_TOG_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GPIOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DIR ========================================================== */ +#define GPIOC_DIR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_DIR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_DIR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_DIR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_DIR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_DIR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ======================================================= OPENDRAIN ======================================================= */ +#define GPIOC_OPENDRAIN_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_OPENDRAIN_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_OPENDRAIN_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_OPENDRAIN_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_OPENDRAIN_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_OPENDRAIN_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================= SPEED ========================================================= */ +#define GPIOC_SPEED_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_SPEED_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_SPEED_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_SPEED_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_SPEED_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_SPEED_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ +#define GPIOC_PDR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_PDR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_PDR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_PDR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_PDR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_PDR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================== PUR ========================================================== */ +#define GPIOC_PUR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_PUR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_PUR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_PUR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_PUR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_PUR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================= AFRH ========================================================== */ +#define GPIOC_AFRH_AFR15_Pos (28UL) /*!< AFR15 (Bit 28) */ +#define GPIOC_AFRH_AFR15_Msk (0xf0000000UL) /*!< AFR15 (Bitfield-Mask: 0x0f) */ +#define GPIOC_AFRH_AFR14_Pos (24UL) /*!< AFR14 (Bit 24) */ +#define GPIOC_AFRH_AFR14_Msk (0xf000000UL) /*!< AFR14 (Bitfield-Mask: 0x0f) */ +#define GPIOC_AFRH_AFR13_Pos (20UL) /*!< AFR13 (Bit 20) */ +#define GPIOC_AFRH_AFR13_Msk (0xf00000UL) /*!< AFR13 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ANALOG ========================================================= */ +#define GPIOC_ANALOG_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_ANALOG_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_ANALOG_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_ANALOG_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_ANALOG_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_ANALOG_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ======================================================== DRIVER ========================================================= */ +#define GPIOC_DRIVER_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_DRIVER_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_DRIVER_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_DRIVER_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_DRIVER_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_DRIVER_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ======================================================== RISEIE ========================================================= */ +#define GPIOC_RISEIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_RISEIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_RISEIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_RISEIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_RISEIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_RISEIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ======================================================== FALLIE ========================================================= */ +#define GPIOC_FALLIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_FALLIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_FALLIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_FALLIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_FALLIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_FALLIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ======================================================== HIGHIE ========================================================= */ +#define GPIOC_HIGHIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_HIGHIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_HIGHIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_HIGHIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_HIGHIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_HIGHIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================= LOWIE ========================================================= */ +#define GPIOC_LOWIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_LOWIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_LOWIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_LOWIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_LOWIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_LOWIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define GPIOC_ISR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_ISR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_ISR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_ISR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_ISR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_ISR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define GPIOC_ICR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_ICR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_ICR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_ICR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_ICR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_ICR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================= LOCK ========================================================== */ +#define GPIOC_LOCK_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define GPIOC_LOCK_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define GPIOC_LOCK_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_LOCK_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_LOCK_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_LOCK_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_LOCK_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_LOCK_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ======================================================== FILTER ========================================================= */ +#define GPIOC_FILTER_FLTCLK_Pos (16UL) /*!< FLTCLK (Bit 16) */ +#define GPIOC_FILTER_FLTCLK_Msk (0x70000UL) /*!< FLTCLK (Bitfield-Mask: 0x07) */ +#define GPIOC_FILTER_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_FILTER_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_FILTER_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_FILTER_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_FILTER_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_FILTER_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================== IDR ========================================================== */ +#define GPIOC_IDR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_IDR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_IDR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_IDR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_IDR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_IDR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================== ODR ========================================================== */ +#define GPIOC_ODR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_ODR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_ODR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_ODR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_ODR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_ODR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ====================================================== ODRLOWBYTE ======================================================= */ +#define GPIOC_ODRLOWBYTE_LOWBYTE_Pos (0UL) /*!< LOWBYTE (Bit 0) */ +#define GPIOC_ODRLOWBYTE_LOWBYTE_Msk (0xffUL) /*!< LOWBYTE (Bitfield-Mask: 0xff) */ +/* ====================================================== ODRHIGHBYTE ====================================================== */ +#define GPIOC_ODRHIGHBYTE_HIGHBYTE_Pos (0UL) /*!< HIGHBYTE (Bit 0) */ +#define GPIOC_ODRHIGHBYTE_HIGHBYTE_Msk (0xffUL) /*!< HIGHBYTE (Bitfield-Mask: 0xff) */ +/* ========================================================== BRR ========================================================== */ +#define GPIOC_BRR_BRR15_Pos (15UL) /*!< BRR15 (Bit 15) */ +#define GPIOC_BRR_BRR15_Msk (0x8000UL) /*!< BRR15 (Bitfield-Mask: 0x01) */ +#define GPIOC_BRR_BRR14_Pos (14UL) /*!< BRR14 (Bit 14) */ +#define GPIOC_BRR_BRR14_Msk (0x4000UL) /*!< BRR14 (Bitfield-Mask: 0x01) */ +#define GPIOC_BRR_BRR13_Pos (13UL) /*!< BRR13 (Bit 13) */ +#define GPIOC_BRR_BRR13_Msk (0x2000UL) /*!< BRR13 (Bitfield-Mask: 0x01) */ +/* ========================================================= BSRR ========================================================== */ +#define GPIOC_BSRR_BRR15_Pos (31UL) /*!< BRR15 (Bit 31) */ +#define GPIOC_BSRR_BRR15_Msk (0x80000000UL) /*!< BRR15 (Bitfield-Mask: 0x01) */ +#define GPIOC_BSRR_BRR14_Pos (30UL) /*!< BRR14 (Bit 30) */ +#define GPIOC_BSRR_BRR14_Msk (0x40000000UL) /*!< BRR14 (Bitfield-Mask: 0x01) */ +#define GPIOC_BSRR_BRR13_Pos (29UL) /*!< BRR13 (Bit 29) */ +#define GPIOC_BSRR_BRR13_Msk (0x20000000UL) /*!< BRR13 (Bitfield-Mask: 0x01) */ +#define GPIOC_BSRR_BSS15_Pos (15UL) /*!< BSS15 (Bit 15) */ +#define GPIOC_BSRR_BSS15_Msk (0x8000UL) /*!< BSS15 (Bitfield-Mask: 0x01) */ +#define GPIOC_BSRR_BSS14_Pos (14UL) /*!< BSS14 (Bit 14) */ +#define GPIOC_BSRR_BSS14_Msk (0x4000UL) /*!< BSS14 (Bitfield-Mask: 0x01) */ +#define GPIOC_BSRR_BSS13_Pos (13UL) /*!< BSS13 (Bit 13) */ +#define GPIOC_BSRR_BSS13_Msk (0x2000UL) /*!< BSS13 (Bitfield-Mask: 0x01) */ +/* ========================================================== TOG ========================================================== */ +#define GPIOC_TOG_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_TOG_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_TOG_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_TOG_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_TOG_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_TOG_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GPIOF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DIR ========================================================== */ +#define GPIOF_DIR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_DIR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_DIR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_DIR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_DIR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_DIR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_DIR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_DIR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_DIR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_DIR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================= OPENDRAIN ======================================================= */ +#define GPIOF_OPENDRAIN_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_OPENDRAIN_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_OPENDRAIN_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_OPENDRAIN_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_OPENDRAIN_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_OPENDRAIN_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_OPENDRAIN_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_OPENDRAIN_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_OPENDRAIN_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_OPENDRAIN_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SPEED ========================================================= */ +#define GPIOF_SPEED_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_SPEED_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_SPEED_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_SPEED_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_SPEED_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_SPEED_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_SPEED_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_SPEED_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_SPEED_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_SPEED_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ +#define GPIOF_PDR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_PDR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_PDR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_PDR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_PDR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_PDR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_PDR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_PDR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_PDR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_PDR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== PUR ========================================================== */ +#define GPIOF_PUR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_PUR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_PUR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_PUR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_PUR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_PUR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_PUR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_PUR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_PUR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_PUR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= AFRL ========================================================== */ +#define GPIOF_AFRL_AFR7_Pos (28UL) /*!< AFR7 (Bit 28) */ +#define GPIOF_AFRL_AFR7_Msk (0xf0000000UL) /*!< AFR7 (Bitfield-Mask: 0x0f) */ +#define GPIOF_AFRL_AFR6_Pos (24UL) /*!< AFR6 (Bit 24) */ +#define GPIOF_AFRL_AFR6_Msk (0xf000000UL) /*!< AFR6 (Bitfield-Mask: 0x0f) */ +#define GPIOF_AFRL_AFR3_Pos (12UL) /*!< AFR3 (Bit 12) */ +#define GPIOF_AFRL_AFR3_Msk (0xf000UL) /*!< AFR3 (Bitfield-Mask: 0x0f) */ +#define GPIOF_AFRL_AFR1_Pos (4UL) /*!< AFR1 (Bit 4) */ +#define GPIOF_AFRL_AFR1_Msk (0xf0UL) /*!< AFR1 (Bitfield-Mask: 0x0f) */ +#define GPIOF_AFRL_AFR0_Pos (0UL) /*!< AFR0 (Bit 0) */ +#define GPIOF_AFRL_AFR0_Msk (0xfUL) /*!< AFR0 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ANALOG ========================================================= */ +#define GPIOF_ANALOG_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_ANALOG_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_ANALOG_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_ANALOG_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_ANALOG_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_ANALOG_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_ANALOG_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_ANALOG_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_ANALOG_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_ANALOG_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DRIVER ========================================================= */ +#define GPIOF_DRIVER_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_DRIVER_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_DRIVER_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_DRIVER_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_DRIVER_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_DRIVER_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_DRIVER_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_DRIVER_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_DRIVER_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_DRIVER_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== RISEIE ========================================================= */ +#define GPIOF_RISEIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_RISEIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_RISEIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_RISEIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_RISEIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_RISEIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_RISEIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_RISEIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_RISEIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_RISEIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FALLIE ========================================================= */ +#define GPIOF_FALLIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_FALLIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_FALLIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_FALLIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_FALLIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_FALLIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_FALLIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_FALLIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_FALLIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_FALLIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== HIGHIE ========================================================= */ +#define GPIOF_HIGHIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_HIGHIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_HIGHIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_HIGHIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_HIGHIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_HIGHIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_HIGHIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_HIGHIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_HIGHIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_HIGHIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= LOWIE ========================================================= */ +#define GPIOF_LOWIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_LOWIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_LOWIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_LOWIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_LOWIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_LOWIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_LOWIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_LOWIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_LOWIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_LOWIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define GPIOF_ISR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_ISR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_ISR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_ISR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_ISR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_ISR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_ISR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_ISR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_ISR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_ISR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define GPIOF_ICR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_ICR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_ICR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_ICR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_ICR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_ICR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_ICR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_ICR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_ICR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_ICR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= LOCK ========================================================== */ +#define GPIOF_LOCK_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define GPIOF_LOCK_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define GPIOF_LOCK_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_LOCK_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_LOCK_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_LOCK_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_LOCK_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_LOCK_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_LOCK_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_LOCK_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_LOCK_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_LOCK_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FILTER ========================================================= */ +#define GPIOF_FILTER_FLTCLK_Pos (16UL) /*!< FLTCLK (Bit 16) */ +#define GPIOF_FILTER_FLTCLK_Msk (0x70000UL) /*!< FLTCLK (Bitfield-Mask: 0x07) */ +#define GPIOF_FILTER_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_FILTER_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_FILTER_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_FILTER_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_FILTER_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_FILTER_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_FILTER_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_FILTER_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_FILTER_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_FILTER_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== IDR ========================================================== */ +#define GPIOF_IDR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_IDR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_IDR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_IDR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_IDR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_IDR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_IDR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_IDR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_IDR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_IDR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ODR ========================================================== */ +#define GPIOF_ODR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_ODR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_ODR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_ODR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_ODR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_ODR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_ODR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_ODR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_ODR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_ODR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ====================================================== ODRLOWBYTE ======================================================= */ +#define GPIOF_ODRLOWBYTE_LOWBYTE_Pos (0UL) /*!< LOWBYTE (Bit 0) */ +#define GPIOF_ODRLOWBYTE_LOWBYTE_Msk (0xffUL) /*!< LOWBYTE (Bitfield-Mask: 0xff) */ +/* ========================================================== BRR ========================================================== */ +#define GPIOF_BRR_BRR7_Pos (7UL) /*!< BRR7 (Bit 7) */ +#define GPIOF_BRR_BRR7_Msk (0x80UL) /*!< BRR7 (Bitfield-Mask: 0x01) */ +#define GPIOF_BRR_BRR6_Pos (6UL) /*!< BRR6 (Bit 6) */ +#define GPIOF_BRR_BRR6_Msk (0x40UL) /*!< BRR6 (Bitfield-Mask: 0x01) */ +#define GPIOF_BRR_BRR3_Pos (3UL) /*!< BRR3 (Bit 3) */ +#define GPIOF_BRR_BRR3_Msk (0x8UL) /*!< BRR3 (Bitfield-Mask: 0x01) */ +#define GPIOF_BRR_BRR1_Pos (1UL) /*!< BRR1 (Bit 1) */ +#define GPIOF_BRR_BRR1_Msk (0x2UL) /*!< BRR1 (Bitfield-Mask: 0x01) */ +#define GPIOF_BRR_BRR0_Pos (0UL) /*!< BRR0 (Bit 0) */ +#define GPIOF_BRR_BRR0_Msk (0x1UL) /*!< BRR0 (Bitfield-Mask: 0x01) */ +/* ========================================================= BSRR ========================================================== */ +#define GPIOF_BSRR_BSS7_Pos (7UL) /*!< BSS7 (Bit 7) */ +#define GPIOF_BSRR_BSS7_Msk (0x80UL) /*!< BSS7 (Bitfield-Mask: 0x01) */ +#define GPIOF_BSRR_BSS6_Pos (6UL) /*!< BSS6 (Bit 6) */ +#define GPIOF_BSRR_BSS6_Msk (0x40UL) /*!< BSS6 (Bitfield-Mask: 0x01) */ +#define GPIOF_BSRR_BSS3_Pos (3UL) /*!< BSS3 (Bit 3) */ +#define GPIOF_BSRR_BSS3_Msk (0x8UL) /*!< BSS3 (Bitfield-Mask: 0x01) */ +#define GPIOF_BSRR_BSS1_Pos (1UL) /*!< BSS1 (Bit 1) */ +#define GPIOF_BSRR_BSS1_Msk (0x2UL) /*!< BSS1 (Bitfield-Mask: 0x01) */ +#define GPIOF_BSRR_BSS0_Pos (0UL) /*!< BSS0 (Bit 0) */ +#define GPIOF_BSRR_BSS0_Msk (0x1UL) /*!< BSS0 (Bitfield-Mask: 0x01) */ +/* ========================================================== TOG ========================================================== */ +#define GPIOF_TOG_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_TOG_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_TOG_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_TOG_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_TOG_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_TOG_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_TOG_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_TOG_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_TOG_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_TOG_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GTIM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ARR ========================================================== */ +#define GTIMx_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define GTIMx_ARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ========================================================== CNT ========================================================== */ +#define GTIMx_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define GTIMx_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================= CMMR ========================================================== */ +#define GTIMx_CMMR_CC4M_Pos (12UL) /*!< CC4M (Bit 12) */ +#define GTIMx_CMMR_CC4M_Msk (0xf000UL) /*!< CC4M (Bitfield-Mask: 0x0f) */ +#define GTIMx_CMMR_CC3M_Pos (8UL) /*!< CC3M (Bit 8) */ +#define GTIMx_CMMR_CC3M_Msk (0xf00UL) /*!< CC3M (Bitfield-Mask: 0x0f) */ +#define GTIMx_CMMR_CC2M_Pos (4UL) /*!< CC2M (Bit 4) */ +#define GTIMx_CMMR_CC2M_Msk (0xf0UL) /*!< CC2M (Bitfield-Mask: 0x0f) */ +#define GTIMx_CMMR_CC1M_Pos (0UL) /*!< CC1M (Bit 0) */ +#define GTIMx_CMMR_CC1M_Msk (0xfUL) /*!< CC1M (Bitfield-Mask: 0x0f) */ +/* ========================================================== ETR ========================================================== */ +#define GTIMx_ETR_ETRFLT_Pos (4UL) /*!< ETRFLT (Bit 4) */ +#define GTIMx_ETR_ETRFLT_Msk (0x70UL) /*!< ETRFLT (Bitfield-Mask: 0x07) */ +/* ========================================================== CR0 ========================================================== */ +#define GTIMx_CR0_ENCRELOAD_Pos (19UL) /*!< ENCRELOAD (Bit 19) */ +#define GTIMx_CR0_ENCRELOAD_Msk (0x180000UL) /*!< ENCRELOAD (Bitfield-Mask: 0x03) */ +#define GTIMx_CR0_ENCRESET_Pos (17UL) /*!< ENCRESET (Bit 17) */ +#define GTIMx_CR0_ENCRESET_Msk (0x60000UL) /*!< ENCRESET (Bitfield-Mask: 0x03) */ +#define GTIMx_CR0_ENCMODE_Pos (15UL) /*!< ENCMODE (Bit 15) */ +#define GTIMx_CR0_ENCMODE_Msk (0x18000UL) /*!< ENCMODE (Bitfield-Mask: 0x03) */ +#define GTIMx_CR0_PRSSTATUS_Pos (11UL) /*!< PRSSTATUS (Bit 11) */ +#define GTIMx_CR0_PRSSTATUS_Msk (0x7800UL) /*!< PRSSTATUS (Bitfield-Mask: 0x0f) */ +#define GTIMx_CR0_PRS_Pos (7UL) /*!< PRS (Bit 7) */ +#define GTIMx_CR0_PRS_Msk (0x780UL) /*!< PRS (Bitfield-Mask: 0x0f) */ +#define GTIMx_CR0_TOGEN_Pos (6UL) /*!< TOGEN (Bit 6) */ +#define GTIMx_CR0_TOGEN_Msk (0x40UL) /*!< TOGEN (Bitfield-Mask: 0x01) */ +#define GTIMx_CR0_ONESHOT_Pos (5UL) /*!< ONESHOT (Bit 5) */ +#define GTIMx_CR0_ONESHOT_Msk (0x20UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ +#define GTIMx_CR0_POL_Pos (4UL) /*!< POL (Bit 4) */ +#define GTIMx_CR0_POL_Msk (0x10UL) /*!< POL (Bitfield-Mask: 0x01) */ +#define GTIMx_CR0_TRS_Pos (3UL) /*!< TRS (Bit 3) */ +#define GTIMx_CR0_TRS_Msk (0x8UL) /*!< TRS (Bitfield-Mask: 0x01) */ +#define GTIMx_CR0_MODE_Pos (1UL) /*!< MODE (Bit 1) */ +#define GTIMx_CR0_MODE_Msk (0x6UL) /*!< MODE (Bitfield-Mask: 0x03) */ +#define GTIMx_CR0_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define GTIMx_CR0_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define GTIMx_IER_DIRCHANGE_Pos (9UL) /*!< DIRCHANGE (Bit 9) */ +#define GTIMx_IER_DIRCHANGE_Msk (0x200UL) /*!< DIRCHANGE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC4_Pos (6UL) /*!< CC4 (Bit 6) */ +#define GTIMx_IER_CC4_Msk (0x40UL) /*!< CC4 (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC3_Pos (5UL) /*!< CC3 (Bit 5) */ +#define GTIMx_IER_CC3_Msk (0x20UL) /*!< CC3 (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC2_Pos (4UL) /*!< CC2 (Bit 4) */ +#define GTIMx_IER_CC2_Msk (0x10UL) /*!< CC2 (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC1_Pos (3UL) /*!< CC1 (Bit 3) */ +#define GTIMx_IER_CC1_Msk (0x8UL) /*!< CC1 (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_UD_Pos (2UL) /*!< UD (Bit 2) */ +#define GTIMx_IER_UD_Msk (0x4UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_TI_Pos (1UL) /*!< TI (Bit 1) */ +#define GTIMx_IER_TI_Msk (0x2UL) /*!< TI (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_OV_Pos (0UL) /*!< OV (Bit 0) */ +#define GTIMx_IER_OV_Msk (0x1UL) /*!< OV (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define GTIMx_ISR_DIR_Pos (10UL) /*!< DIR (Bit 10) */ +#define GTIMx_ISR_DIR_Msk (0x400UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_DIRCHANGE_Pos (9UL) /*!< DIRCHANGE (Bit 9) */ +#define GTIMx_ISR_DIRCHANGE_Msk (0x200UL) /*!< DIRCHANGE (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC4_Pos (6UL) /*!< CC4 (Bit 6) */ +#define GTIMx_ISR_CC4_Msk (0x40UL) /*!< CC4 (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC3_Pos (5UL) /*!< CC3 (Bit 5) */ +#define GTIMx_ISR_CC3_Msk (0x20UL) /*!< CC3 (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC2_Pos (4UL) /*!< CC2 (Bit 4) */ +#define GTIMx_ISR_CC2_Msk (0x10UL) /*!< CC2 (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC1_Pos (3UL) /*!< CC1 (Bit 3) */ +#define GTIMx_ISR_CC1_Msk (0x8UL) /*!< CC1 (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_UD_Pos (2UL) /*!< UD (Bit 2) */ +#define GTIMx_ISR_UD_Msk (0x4UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_TI_Pos (1UL) /*!< TI (Bit 1) */ +#define GTIMx_ISR_TI_Msk (0x2UL) /*!< TI (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_OV_Pos (0UL) /*!< OV (Bit 0) */ +#define GTIMx_ISR_OV_Msk (0x1UL) /*!< OV (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define GTIMx_ICR_DIRCHANGE_Pos (9UL) /*!< DIRCHANGE (Bit 9) */ +#define GTIMx_ICR_DIRCHANGE_Msk (0x200UL) /*!< DIRCHANGE (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC4_Pos (6UL) /*!< CC4 (Bit 6) */ +#define GTIMx_ICR_CC4_Msk (0x40UL) /*!< CC4 (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC3_Pos (5UL) /*!< CC3 (Bit 5) */ +#define GTIMx_ICR_CC3_Msk (0x20UL) /*!< CC3 (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC2_Pos (4UL) /*!< CC2 (Bit 4) */ +#define GTIMx_ICR_CC2_Msk (0x10UL) /*!< CC2 (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC1_Pos (3UL) /*!< CC1 (Bit 3) */ +#define GTIMx_ICR_CC1_Msk (0x8UL) /*!< CC1 (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_UD_Pos (2UL) /*!< UD (Bit 2) */ +#define GTIMx_ICR_UD_Msk (0x4UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_TI_Pos (1UL) /*!< TI (Bit 1) */ +#define GTIMx_ICR_TI_Msk (0x2UL) /*!< TI (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_OV_Pos (0UL) /*!< OV (Bit 0) */ +#define GTIMx_ICR_OV_Msk (0x1UL) /*!< OV (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR1 ========================================================== */ +#define GTIMx_CCR1_CCR_Pos (0UL) /*!< CCR (Bit 0) */ +#define GTIMx_CCR1_CCR_Msk (0xffffUL) /*!< CCR (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR2 ========================================================== */ +#define GTIMx_CCR2_CCR_Pos (0UL) /*!< CCR (Bit 0) */ +#define GTIMx_CCR2_CCR_Msk (0xffffUL) /*!< CCR (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR3 ========================================================== */ +#define GTIMx_CCR3_CCR_Pos (0UL) /*!< CCR (Bit 0) */ +#define GTIMx_CCR3_CCR_Msk (0xffffUL) /*!< CCR (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR4 ========================================================== */ +#define GTIMx_CCR4_CCR_Pos (0UL) /*!< CCR (Bit 0) */ +#define GTIMx_CCR4_CCR_Msk (0xffffUL) /*!< CCR (Bitfield-Mask: 0xffff) */ +/* ========================================================== CR1 ========================================================== */ +#define GTIMx_CR1_CH4POL_Pos (15UL) /*!< CH4POL (Bit 15) */ +#define GTIMx_CR1_CH4POL_Msk (0x8000UL) /*!< CH4POL (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_CH4FLT_Pos (12UL) /*!< CH4FLT (Bit 12) */ +#define GTIMx_CR1_CH4FLT_Msk (0x7000UL) /*!< CH4FLT (Bitfield-Mask: 0x07) */ +#define GTIMx_CR1_CH3POL_Pos (11UL) /*!< CH3POL (Bit 11) */ +#define GTIMx_CR1_CH3POL_Msk (0x800UL) /*!< CH3POL (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_CH3FLT_Pos (8UL) /*!< CH3FLT (Bit 8) */ +#define GTIMx_CR1_CH3FLT_Msk (0x700UL) /*!< CH3FLT (Bitfield-Mask: 0x07) */ +#define GTIMx_CR1_CH2POL_Pos (7UL) /*!< CH2POL (Bit 7) */ +#define GTIMx_CR1_CH2POL_Msk (0x80UL) /*!< CH2POL (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_CH2FLT_Pos (4UL) /*!< CH2FLT (Bit 4) */ +#define GTIMx_CR1_CH2FLT_Msk (0x70UL) /*!< CH2FLT (Bitfield-Mask: 0x07) */ +#define GTIMx_CR1_CH1POL_Pos (3UL) /*!< CH1POL (Bit 3) */ +#define GTIMx_CR1_CH1POL_Msk (0x8UL) /*!< CH1POL (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_CH1FLT_Pos (0UL) /*!< CH1FLT (Bit 0) */ +#define GTIMx_CR1_CH1FLT_Msk (0x7UL) /*!< CH1FLT (Bitfield-Mask: 0x07) */ +/* ========================================================== DMA ========================================================== */ +#define GTIMx_DMA_CC4_Pos (5UL) /*!< CC4 (Bit 5) */ +#define GTIMx_DMA_CC4_Msk (0x20UL) /*!< CC4 (Bitfield-Mask: 0x01) */ +#define GTIMx_DMA_CC3_Pos (4UL) /*!< CC3 (Bit 4) */ +#define GTIMx_DMA_CC3_Msk (0x10UL) /*!< CC3 (Bitfield-Mask: 0x01) */ +#define GTIMx_DMA_CC2_Pos (3UL) /*!< CC2 (Bit 3) */ +#define GTIMx_DMA_CC2_Msk (0x8UL) /*!< CC2 (Bitfield-Mask: 0x01) */ +#define GTIMx_DMA_CC1_Pos (2UL) /*!< CC1 (Bit 2) */ +#define GTIMx_DMA_CC1_Msk (0x4UL) /*!< CC1 (Bitfield-Mask: 0x01) */ +#define GTIMx_DMA_TRS_Pos (1UL) /*!< TRS (Bit 1) */ +#define GTIMx_DMA_TRS_Msk (0x2UL) /*!< TRS (Bitfield-Mask: 0x01) */ +#define GTIMx_DMA_OV_Pos (0UL) /*!< OV (Bit 0) */ +#define GTIMx_DMA_OV_Msk (0x1UL) /*!< OV (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ I2C ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= BRREN ========================================================= */ +#define I2Cx_BRREN_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define I2Cx_BRREN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== BRR ========================================================== */ +#define I2Cx_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ +#define I2Cx_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== CR =========================================================== */ +#define I2Cx_CR_EN_Pos (6UL) /*!< EN (Bit 6) */ +#define I2Cx_CR_EN_Msk (0x40UL) /*!< EN (Bitfield-Mask: 0x01) */ +#define I2Cx_CR_STA_Pos (5UL) /*!< STA (Bit 5) */ +#define I2Cx_CR_STA_Msk (0x20UL) /*!< STA (Bitfield-Mask: 0x01) */ +#define I2Cx_CR_STO_Pos (4UL) /*!< STO (Bit 4) */ +#define I2Cx_CR_STO_Msk (0x10UL) /*!< STO (Bitfield-Mask: 0x01) */ +#define I2Cx_CR_SI_Pos (3UL) /*!< SI (Bit 3) */ +#define I2Cx_CR_SI_Msk (0x8UL) /*!< SI (Bitfield-Mask: 0x01) */ +#define I2Cx_CR_AA_Pos (2UL) /*!< AA (Bit 2) */ +#define I2Cx_CR_AA_Msk (0x4UL) /*!< AA (Bitfield-Mask: 0x01) */ +#define I2Cx_CR_FLT_Pos (0UL) /*!< FLT (Bit 0) */ +#define I2Cx_CR_FLT_Msk (0x1UL) /*!< FLT (Bitfield-Mask: 0x01) */ +/* ========================================================== DR =========================================================== */ +#define I2Cx_DR_DR_Pos (0UL) /*!< DR (Bit 0) */ +#define I2Cx_DR_DR_Msk (0xffUL) /*!< DR (Bitfield-Mask: 0xff) */ +/* ========================================================= ADDR0 ========================================================= */ +#define I2Cx_ADDR0_ADDR0_Pos (1UL) /*!< ADDR0 (Bit 1) */ +#define I2Cx_ADDR0_ADDR0_Msk (0xfeUL) /*!< ADDR0 (Bitfield-Mask: 0x7f) */ +#define I2Cx_ADDR0_GC_Pos (0UL) /*!< GC (Bit 0) */ +#define I2Cx_ADDR0_GC_Msk (0x1UL) /*!< GC (Bitfield-Mask: 0x01) */ +/* ========================================================= STAT ========================================================== */ +#define I2Cx_STAT_STAT_Pos (0UL) /*!< STAT (Bit 0) */ +#define I2Cx_STAT_STAT_Msk (0xffUL) /*!< STAT (Bitfield-Mask: 0xff) */ +/* ========================================================= ADDR1 ========================================================= */ +#define I2Cx_ADDR1_ADDR1_Pos (1UL) /*!< ADDR1 (Bit 1) */ +#define I2Cx_ADDR1_ADDR1_Msk (0xfeUL) /*!< ADDR1 (Bitfield-Mask: 0x7f) */ +/* ========================================================= ADDR2 ========================================================= */ +#define I2Cx_ADDR2_ADDR2_Pos (1UL) /*!< ADDR2 (Bit 1) */ +#define I2Cx_ADDR2_ADDR2_Msk (0xfeUL) /*!< ADDR2 (Bitfield-Mask: 0x7f) */ +/* ========================================================= MATCH ========================================================= */ +#define I2Cx_MATCH_ADDR2_Pos (2UL) /*!< ADDR2 (Bit 2) */ +#define I2Cx_MATCH_ADDR2_Msk (0x4UL) /*!< ADDR2 (Bitfield-Mask: 0x01) */ +#define I2Cx_MATCH_ADDR1_Pos (1UL) /*!< ADDR1 (Bit 1) */ +#define I2Cx_MATCH_ADDR1_Msk (0x2UL) /*!< ADDR1 (Bitfield-Mask: 0x01) */ +#define I2Cx_MATCH_ADDR0_Pos (0UL) /*!< ADDR0 (Bit 0) */ +#define I2Cx_MATCH_ADDR0_Msk (0x1UL) /*!< ADDR0 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ IWDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== KR =========================================================== */ +#define IWDT_KR_KR_Pos (0UL) /*!< KR (Bit 0) */ +#define IWDT_KR_KR_Msk (0xffffUL) /*!< KR (Bitfield-Mask: 0xffff) */ +/* ========================================================== CR =========================================================== */ +#define IWDT_CR_PAUSE_Pos (5UL) /*!< PAUSE (Bit 5) */ +#define IWDT_CR_PAUSE_Msk (0x20UL) /*!< PAUSE (Bitfield-Mask: 0x01) */ +#define IWDT_CR_IE_Pos (4UL) /*!< IE (Bit 4) */ +#define IWDT_CR_IE_Msk (0x10UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define IWDT_CR_ACTION_Pos (3UL) /*!< ACTION (Bit 3) */ +#define IWDT_CR_ACTION_Msk (0x8UL) /*!< ACTION (Bitfield-Mask: 0x01) */ +#define IWDT_CR_PRS_Pos (0UL) /*!< PRS (Bit 0) */ +#define IWDT_CR_PRS_Msk (0x7UL) /*!< PRS (Bitfield-Mask: 0x07) */ +/* ========================================================== ARR ========================================================== */ +#define IWDT_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define IWDT_ARR_ARR_Msk (0xfffUL) /*!< ARR (Bitfield-Mask: 0xfff) */ +/* ========================================================== SR =========================================================== */ +#define IWDT_SR_RELOAD_Pos (5UL) /*!< RELOAD (Bit 5) */ +#define IWDT_SR_RELOAD_Msk (0x20UL) /*!< RELOAD (Bitfield-Mask: 0x01) */ +#define IWDT_SR_RUN_Pos (4UL) /*!< RUN (Bit 4) */ +#define IWDT_SR_RUN_Msk (0x10UL) /*!< RUN (Bitfield-Mask: 0x01) */ +#define IWDT_SR_OV_Pos (3UL) /*!< OV (Bit 3) */ +#define IWDT_SR_OV_Msk (0x8UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define IWDT_SR_WINRF_Pos (2UL) /*!< WINRF (Bit 2) */ +#define IWDT_SR_WINRF_Msk (0x4UL) /*!< WINRF (Bitfield-Mask: 0x01) */ +#define IWDT_SR_ARRF_Pos (1UL) /*!< ARRF (Bit 1) */ +#define IWDT_SR_ARRF_Msk (0x2UL) /*!< ARRF (Bitfield-Mask: 0x01) */ +#define IWDT_SR_CRF_Pos (0UL) /*!< CRF (Bit 0) */ +#define IWDT_SR_CRF_Msk (0x1UL) /*!< CRF (Bitfield-Mask: 0x01) */ +/* ========================================================= WINR ========================================================== */ +#define IWDT_WINR_WINR_Pos (0UL) /*!< WINR (Bit 0) */ +#define IWDT_WINR_WINR_Msk (0xfffUL) /*!< WINR (Bitfield-Mask: 0xfff) */ +/* ========================================================== CNT ========================================================== */ +#define IWDT_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define IWDT_CNT_CNT_Msk (0xfffUL) /*!< CNT (Bitfield-Mask: 0xfff) */ + + +/* =========================================================================================================================== */ +/* ================ LVD ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define LVD_CR0_IE_Pos (9UL) /*!< IE (Bit 9) */ +#define LVD_CR0_IE_Msk (0x200UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define LVD_CR0_VTH_Pos (4UL) /*!< VTH (Bit 4) */ +#define LVD_CR0_VTH_Msk (0xf0UL) /*!< VTH (Bitfield-Mask: 0x0f) */ +#define LVD_CR0_SOURCE_Pos (2UL) /*!< SOURCE (Bit 2) */ +#define LVD_CR0_SOURCE_Msk (0xcUL) /*!< SOURCE (Bitfield-Mask: 0x03) */ +#define LVD_CR0_ACTION_Pos (1UL) /*!< ACTION (Bit 1) */ +#define LVD_CR0_ACTION_Msk (0x2UL) /*!< ACTION (Bitfield-Mask: 0x01) */ +#define LVD_CR0_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define LVD_CR0_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ +#define LVD_CR1_LEVEL_Pos (7UL) /*!< LEVEL (Bit 7) */ +#define LVD_CR1_LEVEL_Msk (0x80UL) /*!< LEVEL (Bitfield-Mask: 0x01) */ +#define LVD_CR1_FALL_Pos (6UL) /*!< FALL (Bit 6) */ +#define LVD_CR1_FALL_Msk (0x40UL) /*!< FALL (Bitfield-Mask: 0x01) */ +#define LVD_CR1_RISE_Pos (5UL) /*!< RISE (Bit 5) */ +#define LVD_CR1_RISE_Msk (0x20UL) /*!< RISE (Bitfield-Mask: 0x01) */ +#define LVD_CR1_FLTCLK_Pos (4UL) /*!< FLTCLK (Bit 4) */ +#define LVD_CR1_FLTCLK_Msk (0x10UL) /*!< FLTCLK (Bitfield-Mask: 0x01) */ +#define LVD_CR1_FLTTIME_Pos (1UL) /*!< FLTTIME (Bit 1) */ +#define LVD_CR1_FLTTIME_Msk (0xeUL) /*!< FLTTIME (Bitfield-Mask: 0x07) */ +#define LVD_CR1_FLTEN_Pos (0UL) /*!< FLTEN (Bit 0) */ +#define LVD_CR1_FLTEN_Msk (0x1UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ +/* ========================================================== SR =========================================================== */ +#define LVD_SR_FLTV_Pos (1UL) /*!< FLTV (Bit 1) */ +#define LVD_SR_FLTV_Msk (0x2UL) /*!< FLTV (Bitfield-Mask: 0x01) */ +#define LVD_SR_INTF_Pos (0UL) /*!< INTF (Bit 0) */ +#define LVD_SR_INTF_Msk (0x1UL) /*!< INTF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ RAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== IER ========================================================== */ +#define RAM_IER_PARITY_Pos (1UL) /*!< PARITY (Bit 1) */ +#define RAM_IER_PARITY_Msk (0x2UL) /*!< PARITY (Bitfield-Mask: 0x01) */ +#define RAM_IER_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define RAM_IER_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADDR ========================================================== */ +#define RAM_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define RAM_ADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== ISR ========================================================== */ +#define RAM_ISR_PARITY_Pos (0UL) /*!< PARITY (Bit 0) */ +#define RAM_ISR_PARITY_Msk (0x1UL) /*!< PARITY (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define RAM_ICR_PARITY_Pos (0UL) /*!< PARITY (Bit 0) */ +#define RAM_ICR_PARITY_Msk (0x1UL) /*!< PARITY (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== KEY ========================================================== */ +#define RTC_KEY_KEY_Pos (0UL) /*!< KEY (Bit 0) */ +#define RTC_KEY_KEY_Msk (0xffUL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================== CR0 ========================================================== */ +#define RTC_CR0_START_Pos (7UL) /*!< START (Bit 7) */ +#define RTC_CR0_START_Msk (0x80UL) /*!< START (Bitfield-Mask: 0x01) */ +#define RTC_CR0_RTC1HZ_Pos (5UL) /*!< RTC1HZ (Bit 5) */ +#define RTC_CR0_RTC1HZ_Msk (0x60UL) /*!< RTC1HZ (Bitfield-Mask: 0x03) */ +#define RTC_CR0_H24_Pos (3UL) /*!< H24 (Bit 3) */ +#define RTC_CR0_H24_Msk (0x8UL) /*!< H24 (Bitfield-Mask: 0x01) */ +#define RTC_CR0_INTERVAL_Pos (0UL) /*!< INTERVAL (Bit 0) */ +#define RTC_CR0_INTERVAL_Msk (0x7UL) /*!< INTERVAL (Bitfield-Mask: 0x07) */ +/* ========================================================== CR1 ========================================================== */ +#define RTC_CR1_SOURCE_Pos (8UL) /*!< SOURCE (Bit 8) */ +#define RTC_CR1_SOURCE_Msk (0x700UL) /*!< SOURCE (Bitfield-Mask: 0x07) */ +#define RTC_CR1_WINDOW_Pos (1UL) /*!< WINDOW (Bit 1) */ +#define RTC_CR1_WINDOW_Msk (0x2UL) /*!< WINDOW (Bitfield-Mask: 0x01) */ +#define RTC_CR1_ACCESS_Pos (0UL) /*!< ACCESS (Bit 0) */ +#define RTC_CR1_ACCESS_Msk (0x1UL) /*!< ACCESS (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define RTC_CR2_ALARMBEN_Pos (10UL) /*!< ALARMBEN (Bit 10) */ +#define RTC_CR2_ALARMBEN_Msk (0x400UL) /*!< ALARMBEN (Bitfield-Mask: 0x01) */ +#define RTC_CR2_ALARMAEN_Pos (9UL) /*!< ALARMAEN (Bit 9) */ +#define RTC_CR2_ALARMAEN_Msk (0x200UL) /*!< ALARMAEN (Bitfield-Mask: 0x01) */ +#define RTC_CR2_AWTEN_Pos (7UL) /*!< AWTEN (Bit 7) */ +#define RTC_CR2_AWTEN_Msk (0x80UL) /*!< AWTEN (Bitfield-Mask: 0x01) */ +#define RTC_CR2_TAMPEN_Pos (6UL) /*!< TAMPEN (Bit 6) */ +#define RTC_CR2_TAMPEN_Msk (0x40UL) /*!< TAMPEN (Bitfield-Mask: 0x01) */ +#define RTC_CR2_RTCOUT_Pos (4UL) /*!< RTCOUT (Bit 4) */ +#define RTC_CR2_RTCOUT_Msk (0x30UL) /*!< RTCOUT (Bitfield-Mask: 0x03) */ +#define RTC_CR2_TAMPEDGE_Pos (3UL) /*!< TAMPEDGE (Bit 3) */ +#define RTC_CR2_TAMPEDGE_Msk (0x8UL) /*!< TAMPEDGE (Bitfield-Mask: 0x01) */ +#define RTC_CR2_AWTSRC_Pos (0UL) /*!< AWTSRC (Bit 0) */ +#define RTC_CR2_AWTSRC_Msk (0x7UL) /*!< AWTSRC (Bitfield-Mask: 0x07) */ +/* ======================================================== COMPEN ========================================================= */ +#define RTC_COMPEN_FREQ_Pos (16UL) /*!< FREQ (Bit 16) */ +#define RTC_COMPEN_FREQ_Msk (0xf0000UL) /*!< FREQ (Bitfield-Mask: 0x0f) */ +#define RTC_COMPEN_EN_Pos (15UL) /*!< EN (Bit 15) */ +#define RTC_COMPEN_EN_Msk (0x8000UL) /*!< EN (Bitfield-Mask: 0x01) */ +#define RTC_COMPEN_SIGN_Pos (14UL) /*!< SIGN (Bit 14) */ +#define RTC_COMPEN_SIGN_Msk (0x4000UL) /*!< SIGN (Bitfield-Mask: 0x01) */ +#define RTC_COMPEN_STEP_Pos (12UL) /*!< STEP (Bit 12) */ +#define RTC_COMPEN_STEP_Msk (0x3000UL) /*!< STEP (Bitfield-Mask: 0x03) */ +#define RTC_COMPEN_COMP_Pos (0UL) /*!< COMP (Bit 0) */ +#define RTC_COMPEN_COMP_Msk (0xfffUL) /*!< COMP (Bitfield-Mask: 0xfff) */ +/* ========================================================= DATE ========================================================== */ +#define RTC_DATE_WEEK_Pos (24UL) /*!< WEEK (Bit 24) */ +#define RTC_DATE_WEEK_Msk (0x7000000UL) /*!< WEEK (Bitfield-Mask: 0x07) */ +#define RTC_DATE_YEAR_Pos (16UL) /*!< YEAR (Bit 16) */ +#define RTC_DATE_YEAR_Msk (0xff0000UL) /*!< YEAR (Bitfield-Mask: 0xff) */ +#define RTC_DATE_MONTH_Pos (8UL) /*!< MONTH (Bit 8) */ +#define RTC_DATE_MONTH_Msk (0xff00UL) /*!< MONTH (Bitfield-Mask: 0xff) */ +#define RTC_DATE_DAY_Pos (0UL) /*!< DAY (Bit 0) */ +#define RTC_DATE_DAY_Msk (0xffUL) /*!< DAY (Bitfield-Mask: 0xff) */ +/* ========================================================= TIME ========================================================== */ +#define RTC_TIME_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */ +#define RTC_TIME_HOUR_Msk (0x3f0000UL) /*!< HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_TIME_MINUTE_Pos (8UL) /*!< MINUTE (Bit 8) */ +#define RTC_TIME_MINUTE_Msk (0x7f00UL) /*!< MINUTE (Bitfield-Mask: 0x7f) */ +#define RTC_TIME_SECOND_Pos (0UL) /*!< SECOND (Bit 0) */ +#define RTC_TIME_SECOND_Msk (0x7fUL) /*!< SECOND (Bitfield-Mask: 0x7f) */ +/* ======================================================== ALARMA ========================================================= */ +#define RTC_ALARMA_WEEKMASK_Pos (24UL) /*!< WEEKMASK (Bit 24) */ +#define RTC_ALARMA_WEEKMASK_Msk (0x7f000000UL) /*!< WEEKMASK (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMA_HOUREN_Pos (23UL) /*!< HOUREN (Bit 23) */ +#define RTC_ALARMA_HOUREN_Msk (0x800000UL) /*!< HOUREN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMA_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */ +#define RTC_ALARMA_HOUR_Msk (0x3f0000UL) /*!< HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_ALARMA_MINUTEEN_Pos (15UL) /*!< MINUTEEN (Bit 15) */ +#define RTC_ALARMA_MINUTEEN_Msk (0x8000UL) /*!< MINUTEEN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMA_MINUTE_Pos (8UL) /*!< MINUTE (Bit 8) */ +#define RTC_ALARMA_MINUTE_Msk (0x7f00UL) /*!< MINUTE (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMA_SECONDEN_Pos (7UL) /*!< SECONDEN (Bit 7) */ +#define RTC_ALARMA_SECONDEN_Msk (0x80UL) /*!< SECONDEN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMA_SECOND_Pos (0UL) /*!< SECOND (Bit 0) */ +#define RTC_ALARMA_SECOND_Msk (0x7fUL) /*!< SECOND (Bitfield-Mask: 0x7f) */ +/* ======================================================== ALARMB ========================================================= */ +#define RTC_ALARMB_WEEKMASK_Pos (24UL) /*!< WEEKMASK (Bit 24) */ +#define RTC_ALARMB_WEEKMASK_Msk (0x7f000000UL) /*!< WEEKMASK (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMB_HOUREN_Pos (23UL) /*!< HOUREN (Bit 23) */ +#define RTC_ALARMB_HOUREN_Msk (0x800000UL) /*!< HOUREN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMB_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */ +#define RTC_ALARMB_HOUR_Msk (0x3f0000UL) /*!< HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_ALARMB_MINUTEEN_Pos (15UL) /*!< MINUTEEN (Bit 15) */ +#define RTC_ALARMB_MINUTEEN_Msk (0x8000UL) /*!< MINUTEEN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMB_MINUTE_Pos (8UL) /*!< MINUTE (Bit 8) */ +#define RTC_ALARMB_MINUTE_Msk (0x7f00UL) /*!< MINUTE (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMB_SECONDEN_Pos (7UL) /*!< SECONDEN (Bit 7) */ +#define RTC_ALARMB_SECONDEN_Msk (0x80UL) /*!< SECONDEN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMB_SECOND_Pos (0UL) /*!< SECOND (Bit 0) */ +#define RTC_ALARMB_SECOND_Msk (0x7fUL) /*!< SECOND (Bitfield-Mask: 0x7f) */ +/* ======================================================= TAMPDATE ======================================================== */ +#define RTC_TAMPDATE_WEEK_Pos (13UL) /*!< WEEK (Bit 13) */ +#define RTC_TAMPDATE_WEEK_Msk (0xe000UL) /*!< WEEK (Bitfield-Mask: 0x07) */ +#define RTC_TAMPDATE_MONTH_Pos (8UL) /*!< MONTH (Bit 8) */ +#define RTC_TAMPDATE_MONTH_Msk (0x1f00UL) /*!< MONTH (Bitfield-Mask: 0x1f) */ +#define RTC_TAMPDATE_DAY_Pos (0UL) /*!< DAY (Bit 0) */ +#define RTC_TAMPDATE_DAY_Msk (0x3fUL) /*!< DAY (Bitfield-Mask: 0x3f) */ +/* ======================================================= TAMPTIME ======================================================== */ +#define RTC_TAMPTIME_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */ +#define RTC_TAMPTIME_HOUR_Msk (0x3f0000UL) /*!< HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_TAMPTIME_MINUTE_Pos (8UL) /*!< MINUTE (Bit 8) */ +#define RTC_TAMPTIME_MINUTE_Msk (0x7f00UL) /*!< MINUTE (Bitfield-Mask: 0x7f) */ +#define RTC_TAMPTIME_SECOND_Pos (0UL) /*!< SECOND (Bit 0) */ +#define RTC_TAMPTIME_SECOND_Msk (0x7fUL) /*!< SECOND (Bitfield-Mask: 0x7f) */ +/* ======================================================== AWTARR ========================================================= */ +#define RTC_AWTARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define RTC_AWTARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ========================================================== IER ========================================================== */ +#define RTC_IER_INTERVAL_Pos (6UL) /*!< INTERVAL (Bit 6) */ +#define RTC_IER_INTERVAL_Msk (0x40UL) /*!< INTERVAL (Bitfield-Mask: 0x01) */ +#define RTC_IER_TAMPOV_Pos (4UL) /*!< TAMPOV (Bit 4) */ +#define RTC_IER_TAMPOV_Msk (0x10UL) /*!< TAMPOV (Bitfield-Mask: 0x01) */ +#define RTC_IER_TAMP_Pos (3UL) /*!< TAMP (Bit 3) */ +#define RTC_IER_TAMP_Msk (0x8UL) /*!< TAMP (Bitfield-Mask: 0x01) */ +#define RTC_IER_AWTIMER_Pos (2UL) /*!< AWTIMER (Bit 2) */ +#define RTC_IER_AWTIMER_Msk (0x4UL) /*!< AWTIMER (Bitfield-Mask: 0x01) */ +#define RTC_IER_ALARMB_Pos (1UL) /*!< ALARMB (Bit 1) */ +#define RTC_IER_ALARMB_Msk (0x2UL) /*!< ALARMB (Bitfield-Mask: 0x01) */ +#define RTC_IER_ALARMA_Pos (0UL) /*!< ALARMA (Bit 0) */ +#define RTC_IER_ALARMA_Msk (0x1UL) /*!< ALARMA (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define RTC_ISR_INTERVAL_Pos (6UL) /*!< INTERVAL (Bit 6) */ +#define RTC_ISR_INTERVAL_Msk (0x40UL) /*!< INTERVAL (Bitfield-Mask: 0x01) */ +#define RTC_ISR_TAMPOV_Pos (4UL) /*!< TAMPOV (Bit 4) */ +#define RTC_ISR_TAMPOV_Msk (0x10UL) /*!< TAMPOV (Bitfield-Mask: 0x01) */ +#define RTC_ISR_TAMP_Pos (3UL) /*!< TAMP (Bit 3) */ +#define RTC_ISR_TAMP_Msk (0x8UL) /*!< TAMP (Bitfield-Mask: 0x01) */ +#define RTC_ISR_AWTIMER_Pos (2UL) /*!< AWTIMER (Bit 2) */ +#define RTC_ISR_AWTIMER_Msk (0x4UL) /*!< AWTIMER (Bitfield-Mask: 0x01) */ +#define RTC_ISR_ALARMB_Pos (1UL) /*!< ALARMB (Bit 1) */ +#define RTC_ISR_ALARMB_Msk (0x2UL) /*!< ALARMB (Bitfield-Mask: 0x01) */ +#define RTC_ISR_ALARMA_Pos (0UL) /*!< ALARMA (Bit 0) */ +#define RTC_ISR_ALARMA_Msk (0x1UL) /*!< ALARMA (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define RTC_ICR_INTERVAL_Pos (6UL) /*!< INTERVAL (Bit 6) */ +#define RTC_ICR_INTERVAL_Msk (0x40UL) /*!< INTERVAL (Bitfield-Mask: 0x01) */ +#define RTC_ICR_TAMPOV_Pos (4UL) /*!< TAMPOV (Bit 4) */ +#define RTC_ICR_TAMPOV_Msk (0x10UL) /*!< TAMPOV (Bitfield-Mask: 0x01) */ +#define RTC_ICR_TAMP_Pos (3UL) /*!< TAMP (Bit 3) */ +#define RTC_ICR_TAMP_Msk (0x8UL) /*!< TAMP (Bitfield-Mask: 0x01) */ +#define RTC_ICR_AWTIMER_Pos (2UL) /*!< AWTIMER (Bit 2) */ +#define RTC_ICR_AWTIMER_Msk (0x4UL) /*!< AWTIMER (Bitfield-Mask: 0x01) */ +#define RTC_ICR_ALARMB_Pos (1UL) /*!< ALARMB (Bit 1) */ +#define RTC_ICR_ALARMB_Msk (0x2UL) /*!< ALARMB (Bitfield-Mask: 0x01) */ +#define RTC_ICR_ALARMA_Pos (0UL) /*!< ALARMA (Bit 0) */ +#define RTC_ICR_ALARMA_Msk (0x1UL) /*!< ALARMA (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define SPIx_CR1_MISOHD_Pos (18UL) /*!< MISOHD (Bit 18) */ +#define SPIx_CR1_MISOHD_Msk (0x40000UL) /*!< MISOHD (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_DMATX_Pos (17UL) /*!< DMATX (Bit 17) */ +#define SPIx_CR1_DMATX_Msk (0x20000UL) /*!< DMATX (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_DMARX_Pos (16UL) /*!< DMARX (Bit 16) */ +#define SPIx_CR1_DMARX_Msk (0x10000UL) /*!< DMARX (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_MODE_Pos (14UL) /*!< MODE (Bit 14) */ +#define SPIx_CR1_MODE_Msk (0xc000UL) /*!< MODE (Bitfield-Mask: 0x03) */ +#define SPIx_CR1_WIDTH_Pos (10UL) /*!< WIDTH (Bit 10) */ +#define SPIx_CR1_WIDTH_Msk (0x3c00UL) /*!< WIDTH (Bitfield-Mask: 0x0f) */ +#define SPIx_CR1_SSM_Pos (9UL) /*!< SSM (Bit 9) */ +#define SPIx_CR1_SSM_Msk (0x200UL) /*!< SSM (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_SMP_Pos (8UL) /*!< SMP (Bit 8) */ +#define SPIx_CR1_SMP_Msk (0x100UL) /*!< SMP (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_LSBF_Pos (7UL) /*!< LSBF (Bit 7) */ +#define SPIx_CR1_LSBF_Msk (0x80UL) /*!< LSBF (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_EN_Pos (6UL) /*!< EN (Bit 6) */ +#define SPIx_CR1_EN_Msk (0x40UL) /*!< EN (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_BR_Pos (3UL) /*!< BR (Bit 3) */ +#define SPIx_CR1_BR_Msk (0x38UL) /*!< BR (Bitfield-Mask: 0x07) */ +#define SPIx_CR1_MSTR_Pos (2UL) /*!< MSTR (Bit 2) */ +#define SPIx_CR1_MSTR_Msk (0x4UL) /*!< MSTR (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ +#define SPIx_CR1_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ +#define SPIx_CR1_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define SPIx_IER_MODF_Pos (7UL) /*!< MODF (Bit 7) */ +#define SPIx_IER_MODF_Msk (0x80UL) /*!< MODF (Bitfield-Mask: 0x01) */ +#define SPIx_IER_SSERR_Pos (6UL) /*!< SSERR (Bit 6) */ +#define SPIx_IER_SSERR_Msk (0x40UL) /*!< SSERR (Bitfield-Mask: 0x01) */ +#define SPIx_IER_OV_Pos (5UL) /*!< OV (Bit 5) */ +#define SPIx_IER_OV_Msk (0x20UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define SPIx_IER_UD_Pos (4UL) /*!< UD (Bit 4) */ +#define SPIx_IER_UD_Msk (0x10UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define SPIx_IER_SSR_Pos (3UL) /*!< SSR (Bit 3) */ +#define SPIx_IER_SSR_Msk (0x8UL) /*!< SSR (Bitfield-Mask: 0x01) */ +#define SPIx_IER_SSF_Pos (2UL) /*!< SSF (Bit 2) */ +#define SPIx_IER_SSF_Msk (0x4UL) /*!< SSF (Bitfield-Mask: 0x01) */ +#define SPIx_IER_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define SPIx_IER_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define SPIx_IER_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define SPIx_IER_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define SPIx_CR2_HDOE_Pos (0UL) /*!< HDOE (Bit 0) */ +#define SPIx_CR2_HDOE_Msk (0x1UL) /*!< HDOE (Bitfield-Mask: 0x01) */ +/* ========================================================== SSI ========================================================== */ +#define SPIx_SSI_SSI_Pos (0UL) /*!< SSI (Bit 0) */ +#define SPIx_SSI_SSI_Msk (0x1UL) /*!< SSI (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define SPIx_ISR_SSLVL_Pos (9UL) /*!< SSLVL (Bit 9) */ +#define SPIx_ISR_SSLVL_Msk (0x200UL) /*!< SSLVL (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_BUSY_Pos (8UL) /*!< BUSY (Bit 8) */ +#define SPIx_ISR_BUSY_Msk (0x100UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_MODF_Pos (7UL) /*!< MODF (Bit 7) */ +#define SPIx_ISR_MODF_Msk (0x80UL) /*!< MODF (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_SSERR_Pos (6UL) /*!< SSERR (Bit 6) */ +#define SPIx_ISR_SSERR_Msk (0x40UL) /*!< SSERR (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_OV_Pos (5UL) /*!< OV (Bit 5) */ +#define SPIx_ISR_OV_Msk (0x20UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_UD_Pos (4UL) /*!< UD (Bit 4) */ +#define SPIx_ISR_UD_Msk (0x10UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_SSR_Pos (3UL) /*!< SSR (Bit 3) */ +#define SPIx_ISR_SSR_Msk (0x8UL) /*!< SSR (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_SSF_Pos (2UL) /*!< SSF (Bit 2) */ +#define SPIx_ISR_SSF_Msk (0x4UL) /*!< SSF (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define SPIx_ISR_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define SPIx_ISR_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define SPIx_ICR_MODF_Pos (7UL) /*!< MODF (Bit 7) */ +#define SPIx_ICR_MODF_Msk (0x80UL) /*!< MODF (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_SSERR_Pos (6UL) /*!< SSERR (Bit 6) */ +#define SPIx_ICR_SSERR_Msk (0x40UL) /*!< SSERR (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_OV_Pos (5UL) /*!< OV (Bit 5) */ +#define SPIx_ICR_OV_Msk (0x20UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_UD_Pos (4UL) /*!< UD (Bit 4) */ +#define SPIx_ICR_UD_Msk (0x10UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_SSR_Pos (3UL) /*!< SSR (Bit 3) */ +#define SPIx_ICR_SSR_Msk (0x8UL) /*!< SSR (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_SSF_Pos (2UL) /*!< SSF (Bit 2) */ +#define SPIx_ICR_SSF_Msk (0x4UL) /*!< SSF (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define SPIx_ICR_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_FLUSH_Pos (0UL) /*!< FLUSH (Bit 0) */ +#define SPIx_ICR_FLUSH_Msk (0x1UL) /*!< FLUSH (Bitfield-Mask: 0x01) */ +/* ========================================================== DR =========================================================== */ +#define SPIx_DR_DR_Pos (0UL) /*!< DR (Bit 0) */ +#define SPIx_DR_DR_Msk (0xffffUL) /*!< DR (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ SYSCTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define SYSCTRL_CR0_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_CR0_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_CR0_HCLKPRS_Pos (5UL) /*!< HCLKPRS (Bit 5) */ +#define SYSCTRL_CR0_HCLKPRS_Msk (0xe0UL) /*!< HCLKPRS (Bitfield-Mask: 0x07) */ +#define SYSCTRL_CR0_PCLKPRS_Pos (3UL) /*!< PCLKPRS (Bit 3) */ +#define SYSCTRL_CR0_PCLKPRS_Msk (0x18UL) /*!< PCLKPRS (Bitfield-Mask: 0x03) */ +#define SYSCTRL_CR0_SYSCLK_Pos (0UL) /*!< SYSCLK (Bit 0) */ +#define SYSCTRL_CR0_SYSCLK_Msk (0x7UL) /*!< SYSCLK (Bitfield-Mask: 0x07) */ +/* ========================================================== CR1 ========================================================== */ +#define SYSCTRL_CR1_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_CR1_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_CR1_CLKCCS_Pos (8UL) /*!< CLKCCS (Bit 8) */ +#define SYSCTRL_CR1_CLKCCS_Msk (0x100UL) /*!< CLKCCS (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_HSECCS_Pos (7UL) /*!< HSECCS (Bit 7) */ +#define SYSCTRL_CR1_HSECCS_Msk (0x80UL) /*!< HSECCS (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_LSECCS_Pos (6UL) /*!< LSECCS (Bit 6) */ +#define SYSCTRL_CR1_LSECCS_Msk (0x40UL) /*!< LSECCS (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_LSELOCK_Pos (5UL) /*!< LSELOCK (Bit 5) */ +#define SYSCTRL_CR1_LSELOCK_Msk (0x20UL) /*!< LSELOCK (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_LSEEN_Pos (4UL) /*!< LSEEN (Bit 4) */ +#define SYSCTRL_CR1_LSEEN_Msk (0x10UL) /*!< LSEEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_LSIEN_Pos (3UL) /*!< LSIEN (Bit 3) */ +#define SYSCTRL_CR1_LSIEN_Msk (0x8UL) /*!< LSIEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_PLLEN_Pos (2UL) /*!< PLLEN (Bit 2) */ +#define SYSCTRL_CR1_PLLEN_Msk (0x4UL) /*!< PLLEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_HSEEN_Pos (1UL) /*!< HSEEN (Bit 1) */ +#define SYSCTRL_CR1_HSEEN_Msk (0x2UL) /*!< HSEEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_HSIEN_Pos (0UL) /*!< HSIEN (Bit 0) */ +#define SYSCTRL_CR1_HSIEN_Msk (0x1UL) /*!< HSIEN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define SYSCTRL_CR2_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_CR2_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_CR2_WAKEUPCLK_Pos (3UL) /*!< WAKEUPCLK (Bit 3) */ +#define SYSCTRL_CR2_WAKEUPCLK_Msk (0x8UL) /*!< WAKEUPCLK (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_LOCKUP_Pos (2UL) /*!< LOCKUP (Bit 2) */ +#define SYSCTRL_CR2_LOCKUP_Msk (0x4UL) /*!< LOCKUP (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_SWDIO_Pos (1UL) /*!< SWDIO (Bit 1) */ +#define SYSCTRL_CR2_SWDIO_Msk (0x2UL) /*!< SWDIO (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define SYSCTRL_IER_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_IER_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_IER_HSEFAULT_Pos (8UL) /*!< HSEFAULT (Bit 8) */ +#define SYSCTRL_IER_HSEFAULT_Msk (0x100UL) /*!< HSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_LSEFAULT_Pos (7UL) /*!< LSEFAULT (Bit 7) */ +#define SYSCTRL_IER_LSEFAULT_Msk (0x80UL) /*!< LSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_HSEFAIL_Pos (6UL) /*!< HSEFAIL (Bit 6) */ +#define SYSCTRL_IER_HSEFAIL_Msk (0x40UL) /*!< HSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_LSEFAIL_Pos (5UL) /*!< LSEFAIL (Bit 5) */ +#define SYSCTRL_IER_LSEFAIL_Msk (0x20UL) /*!< LSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_LSERDY_Pos (4UL) /*!< LSERDY (Bit 4) */ +#define SYSCTRL_IER_LSERDY_Msk (0x10UL) /*!< LSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_LSIRDY_Pos (3UL) /*!< LSIRDY (Bit 3) */ +#define SYSCTRL_IER_LSIRDY_Msk (0x8UL) /*!< LSIRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_PLLRDY_Pos (2UL) /*!< PLLRDY (Bit 2) */ +#define SYSCTRL_IER_PLLRDY_Msk (0x4UL) /*!< PLLRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_HSERDY_Pos (1UL) /*!< HSERDY (Bit 1) */ +#define SYSCTRL_IER_HSERDY_Msk (0x2UL) /*!< HSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_HSIRDY_Pos (0UL) /*!< HSIRDY (Bit 0) */ +#define SYSCTRL_IER_HSIRDY_Msk (0x1UL) /*!< HSIRDY (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define SYSCTRL_ISR_LSESTABLE_Pos (15UL) /*!< LSESTABLE (Bit 15) */ +#define SYSCTRL_ISR_LSESTABLE_Msk (0x8000UL) /*!< LSESTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSISTABLE_Pos (14UL) /*!< LSISTABLE (Bit 14) */ +#define SYSCTRL_ISR_LSISTABLE_Msk (0x4000UL) /*!< LSISTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_PLLSTABLE_Pos (13UL) /*!< PLLSTABLE (Bit 13) */ +#define SYSCTRL_ISR_PLLSTABLE_Msk (0x2000UL) /*!< PLLSTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSESTABLE_Pos (12UL) /*!< HSESTABLE (Bit 12) */ +#define SYSCTRL_ISR_HSESTABLE_Msk (0x1000UL) /*!< HSESTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSISTABLE_Pos (11UL) /*!< HSISTABLE (Bit 11) */ +#define SYSCTRL_ISR_HSISTABLE_Msk (0x800UL) /*!< HSISTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSEFAULT_Pos (8UL) /*!< HSEFAULT (Bit 8) */ +#define SYSCTRL_ISR_HSEFAULT_Msk (0x100UL) /*!< HSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSEFAULT_Pos (7UL) /*!< LSEFAULT (Bit 7) */ +#define SYSCTRL_ISR_LSEFAULT_Msk (0x80UL) /*!< LSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSEFAIL_Pos (6UL) /*!< HSEFAIL (Bit 6) */ +#define SYSCTRL_ISR_HSEFAIL_Msk (0x40UL) /*!< HSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSEFAIL_Pos (5UL) /*!< LSEFAIL (Bit 5) */ +#define SYSCTRL_ISR_LSEFAIL_Msk (0x20UL) /*!< LSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSERDY_Pos (4UL) /*!< LSERDY (Bit 4) */ +#define SYSCTRL_ISR_LSERDY_Msk (0x10UL) /*!< LSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSIRDY_Pos (3UL) /*!< LSIRDY (Bit 3) */ +#define SYSCTRL_ISR_LSIRDY_Msk (0x8UL) /*!< LSIRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_PLLRDY_Pos (2UL) /*!< PLLRDY (Bit 2) */ +#define SYSCTRL_ISR_PLLRDY_Msk (0x4UL) /*!< PLLRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSERDY_Pos (1UL) /*!< HSERDY (Bit 1) */ +#define SYSCTRL_ISR_HSERDY_Msk (0x2UL) /*!< HSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSIRDY_Pos (0UL) /*!< HSIRDY (Bit 0) */ +#define SYSCTRL_ISR_HSIRDY_Msk (0x1UL) /*!< HSIRDY (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define SYSCTRL_ICR_HSEFAULT_Pos (8UL) /*!< HSEFAULT (Bit 8) */ +#define SYSCTRL_ICR_HSEFAULT_Msk (0x100UL) /*!< HSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_LSEFAULT_Pos (7UL) /*!< LSEFAULT (Bit 7) */ +#define SYSCTRL_ICR_LSEFAULT_Msk (0x80UL) /*!< LSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_HSEFAIL_Pos (6UL) /*!< HSEFAIL (Bit 6) */ +#define SYSCTRL_ICR_HSEFAIL_Msk (0x40UL) /*!< HSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_LSEFAIL_Pos (5UL) /*!< LSEFAIL (Bit 5) */ +#define SYSCTRL_ICR_LSEFAIL_Msk (0x20UL) /*!< LSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_LSERDY_Pos (4UL) /*!< LSERDY (Bit 4) */ +#define SYSCTRL_ICR_LSERDY_Msk (0x10UL) /*!< LSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_LSIRDY_Pos (3UL) /*!< LSIRDY (Bit 3) */ +#define SYSCTRL_ICR_LSIRDY_Msk (0x8UL) /*!< LSIRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_PLLRDY_Pos (2UL) /*!< PLLRDY (Bit 2) */ +#define SYSCTRL_ICR_PLLRDY_Msk (0x4UL) /*!< PLLRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_HSERDY_Pos (1UL) /*!< HSERDY (Bit 1) */ +#define SYSCTRL_ICR_HSERDY_Msk (0x2UL) /*!< HSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_HSIRDY_Pos (0UL) /*!< HSIRDY (Bit 0) */ +#define SYSCTRL_ICR_HSIRDY_Msk (0x1UL) /*!< HSIRDY (Bitfield-Mask: 0x01) */ +/* ========================================================== HSI ========================================================== */ +#define SYSCTRL_HSI_STABLE_Pos (15UL) /*!< STABLE (Bit 15) */ +#define SYSCTRL_HSI_STABLE_Msk (0x8000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSI_DIV_Pos (11UL) /*!< DIV (Bit 11) */ +#define SYSCTRL_HSI_DIV_Msk (0x7800UL) /*!< DIV (Bitfield-Mask: 0x0f) */ +#define SYSCTRL_HSI_TRIM_Pos (0UL) /*!< TRIM (Bit 0) */ +#define SYSCTRL_HSI_TRIM_Msk (0x7ffUL) /*!< TRIM (Bitfield-Mask: 0x7ff) */ +/* ========================================================== HSE ========================================================== */ +#define SYSCTRL_HSE_STABLE_Pos (19UL) /*!< STABLE (Bit 19) */ +#define SYSCTRL_HSE_STABLE_Msk (0x80000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSE_DETCNT_Pos (8UL) /*!< DETCNT (Bit 8) */ +#define SYSCTRL_HSE_DETCNT_Msk (0x7ff00UL) /*!< DETCNT (Bitfield-Mask: 0x7ff) */ +#define SYSCTRL_HSE_FLT_Pos (7UL) /*!< FLT (Bit 7) */ +#define SYSCTRL_HSE_FLT_Msk (0x80UL) /*!< FLT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSE_MODE_Pos (6UL) /*!< MODE (Bit 6) */ +#define SYSCTRL_HSE_MODE_Msk (0x40UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSE_WAITCYCLE_Pos (4UL) /*!< WAITCYCLE (Bit 4) */ +#define SYSCTRL_HSE_WAITCYCLE_Msk (0x30UL) /*!< WAITCYCLE (Bitfield-Mask: 0x03) */ +#define SYSCTRL_HSE_FREQRANGE_Pos (2UL) /*!< FREQRANGE (Bit 2) */ +#define SYSCTRL_HSE_FREQRANGE_Msk (0xcUL) /*!< FREQRANGE (Bitfield-Mask: 0x03) */ +#define SYSCTRL_HSE_DRIVER_Pos (0UL) /*!< DRIVER (Bit 0) */ +#define SYSCTRL_HSE_DRIVER_Msk (0x3UL) /*!< DRIVER (Bitfield-Mask: 0x03) */ +/* ========================================================== LSI ========================================================== */ +#define SYSCTRL_LSI_STABLE_Pos (15UL) /*!< STABLE (Bit 15) */ +#define SYSCTRL_LSI_STABLE_Msk (0x8000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_LSI_WAITCYCLE_Pos (10UL) /*!< WAITCYCLE (Bit 10) */ +#define SYSCTRL_LSI_WAITCYCLE_Msk (0xc00UL) /*!< WAITCYCLE (Bitfield-Mask: 0x03) */ +#define SYSCTRL_LSI_TRIM_Pos (0UL) /*!< TRIM (Bit 0) */ +#define SYSCTRL_LSI_TRIM_Msk (0x3ffUL) /*!< TRIM (Bitfield-Mask: 0x3ff) */ +/* ========================================================== LSE ========================================================== */ +#define SYSCTRL_LSE_STABLE_Pos (15UL) /*!< STABLE (Bit 15) */ +#define SYSCTRL_LSE_STABLE_Msk (0x8000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_LSE_MODE_Pos (6UL) /*!< MODE (Bit 6) */ +#define SYSCTRL_LSE_MODE_Msk (0x40UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_LSE_WAITCYCLE_Pos (4UL) /*!< WAITCYCLE (Bit 4) */ +#define SYSCTRL_LSE_WAITCYCLE_Msk (0x30UL) /*!< WAITCYCLE (Bitfield-Mask: 0x03) */ +#define SYSCTRL_LSE_AMP_Pos (2UL) /*!< AMP (Bit 2) */ +#define SYSCTRL_LSE_AMP_Msk (0xcUL) /*!< AMP (Bitfield-Mask: 0x03) */ +#define SYSCTRL_LSE_DRIVER_Pos (0UL) /*!< DRIVER (Bit 0) */ +#define SYSCTRL_LSE_DRIVER_Msk (0x3UL) /*!< DRIVER (Bitfield-Mask: 0x03) */ +/* ========================================================== PLL ========================================================== */ +#define SYSCTRL_PLL_STABLE_Pos (15UL) /*!< STABLE (Bit 15) */ +#define SYSCTRL_PLL_STABLE_Msk (0x8000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_PLL_WAITCYCLE_Pos (12UL) /*!< WAITCYCLE (Bit 12) */ +#define SYSCTRL_PLL_WAITCYCLE_Msk (0x7000UL) /*!< WAITCYCLE (Bitfield-Mask: 0x07) */ +#define SYSCTRL_PLL_FREQOUT_Pos (9UL) /*!< FREQOUT (Bit 9) */ +#define SYSCTRL_PLL_FREQOUT_Msk (0xe00UL) /*!< FREQOUT (Bitfield-Mask: 0x07) */ +#define SYSCTRL_PLL_MUL_Pos (4UL) /*!< MUL (Bit 4) */ +#define SYSCTRL_PLL_MUL_Msk (0x1f0UL) /*!< MUL (Bitfield-Mask: 0x1f) */ +#define SYSCTRL_PLL_FREQIN_Pos (2UL) /*!< FREQIN (Bit 2) */ +#define SYSCTRL_PLL_FREQIN_Msk (0xcUL) /*!< FREQIN (Bitfield-Mask: 0x03) */ +#define SYSCTRL_PLL_SOURCE_Pos (0UL) /*!< SOURCE (Bit 0) */ +#define SYSCTRL_PLL_SOURCE_Msk (0x3UL) /*!< SOURCE (Bitfield-Mask: 0x03) */ +/* ========================================================= DEBUG ========================================================= */ +#define SYSCTRL_DEBUG_WWDT_Pos (10UL) /*!< WWDT (Bit 10) */ +#define SYSCTRL_DEBUG_WWDT_Msk (0x400UL) /*!< WWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_IWDT_Pos (9UL) /*!< IWDT (Bit 9) */ +#define SYSCTRL_DEBUG_IWDT_Msk (0x200UL) /*!< IWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_RTC_Pos (8UL) /*!< RTC (Bit 8) */ +#define SYSCTRL_DEBUG_RTC_Msk (0x100UL) /*!< RTC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_AWT_Pos (6UL) /*!< AWT (Bit 6) */ +#define SYSCTRL_DEBUG_AWT_Msk (0x40UL) /*!< AWT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_BTIM123_Pos (5UL) /*!< BTIM123 (Bit 5) */ +#define SYSCTRL_DEBUG_BTIM123_Msk (0x20UL) /*!< BTIM123 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_GTIM4_Pos (4UL) /*!< GTIM4 (Bit 4) */ +#define SYSCTRL_DEBUG_GTIM4_Msk (0x10UL) /*!< GTIM4 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_GTIM3_Pos (3UL) /*!< GTIM3 (Bit 3) */ +#define SYSCTRL_DEBUG_GTIM3_Msk (0x8UL) /*!< GTIM3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_GTIM2_Pos (2UL) /*!< GTIM2 (Bit 2) */ +#define SYSCTRL_DEBUG_GTIM2_Msk (0x4UL) /*!< GTIM2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_GTIM1_Pos (1UL) /*!< GTIM1 (Bit 1) */ +#define SYSCTRL_DEBUG_GTIM1_Msk (0x2UL) /*!< GTIM1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_ATIM_Pos (0UL) /*!< ATIM (Bit 0) */ +#define SYSCTRL_DEBUG_ATIM_Msk (0x1UL) /*!< ATIM (Bitfield-Mask: 0x01) */ +/* ========================================================= AHBEN ========================================================= */ +#define SYSCTRL_AHBEN_GPIOF_Pos (9UL) /*!< GPIOF (Bit 9) */ +#define SYSCTRL_AHBEN_GPIOF_Msk (0x200UL) /*!< GPIOF (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_GPIOC_Pos (6UL) /*!< GPIOC (Bit 6) */ +#define SYSCTRL_AHBEN_GPIOC_Msk (0x40UL) /*!< GPIOC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_GPIOB_Pos (5UL) /*!< GPIOB (Bit 5) */ +#define SYSCTRL_AHBEN_GPIOB_Msk (0x20UL) /*!< GPIOB (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_GPIOA_Pos (4UL) /*!< GPIOA (Bit 4) */ +#define SYSCTRL_AHBEN_GPIOA_Msk (0x10UL) /*!< GPIOA (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_CRC_Pos (2UL) /*!< CRC (Bit 2) */ +#define SYSCTRL_AHBEN_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_FLASH_Pos (1UL) /*!< FLASH (Bit 1) */ +#define SYSCTRL_AHBEN_FLASH_Msk (0x2UL) /*!< FLASH (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_DMA_Pos (0UL) /*!< DMA (Bit 0) */ +#define SYSCTRL_AHBEN_DMA_Msk (0x1UL) /*!< DMA (Bitfield-Mask: 0x01) */ +/* ======================================================== APBEN2 ========================================================= */ +#define SYSCTRL_APBEN2_AWT_Pos (13UL) /*!< AWT (Bit 13) */ +#define SYSCTRL_APBEN2_AWT_Msk (0x2000UL) /*!< AWT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_BTIM_Pos (12UL) /*!< BTIM (Bit 12) */ +#define SYSCTRL_APBEN2_BTIM_Msk (0x1000UL) /*!< BTIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_GTIM4_Pos (11UL) /*!< GTIM4 (Bit 11) */ +#define SYSCTRL_APBEN2_GTIM4_Msk (0x800UL) /*!< GTIM4 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_GTIM3_Pos (10UL) /*!< GTIM3 (Bit 10) */ +#define SYSCTRL_APBEN2_GTIM3_Msk (0x400UL) /*!< GTIM3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_UART1_Pos (9UL) /*!< UART1 (Bit 9) */ +#define SYSCTRL_APBEN2_UART1_Msk (0x200UL) /*!< UART1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_SPI1_Pos (8UL) /*!< SPI1 (Bit 8) */ +#define SYSCTRL_APBEN2_SPI1_Msk (0x100UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_ATIM_Pos (7UL) /*!< ATIM (Bit 7) */ +#define SYSCTRL_APBEN2_ATIM_Msk (0x80UL) /*!< ATIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_VC_Pos (4UL) /*!< VC (Bit 4) */ +#define SYSCTRL_APBEN2_VC_Msk (0x10UL) /*!< VC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_ADC_Pos (2UL) /*!< ADC (Bit 2) */ +#define SYSCTRL_APBEN2_ADC_Msk (0x4UL) /*!< ADC (Bitfield-Mask: 0x01) */ +/* ======================================================== APBEN1 ========================================================= */ +#define SYSCTRL_APBEN1_I2C2_Pos (12UL) /*!< I2C2 (Bit 12) */ +#define SYSCTRL_APBEN1_I2C2_Msk (0x1000UL) /*!< I2C2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_I2C1_Pos (11UL) /*!< I2C1 (Bit 11) */ +#define SYSCTRL_APBEN1_I2C1_Msk (0x800UL) /*!< I2C1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_UART3_Pos (8UL) /*!< UART3 (Bit 8) */ +#define SYSCTRL_APBEN1_UART3_Msk (0x100UL) /*!< UART3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_UART2_Pos (7UL) /*!< UART2 (Bit 7) */ +#define SYSCTRL_APBEN1_UART2_Msk (0x80UL) /*!< UART2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_SPI2_Pos (6UL) /*!< SPI2 (Bit 6) */ +#define SYSCTRL_APBEN1_SPI2_Msk (0x40UL) /*!< SPI2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_IWDT_Pos (5UL) /*!< IWDT (Bit 5) */ +#define SYSCTRL_APBEN1_IWDT_Msk (0x20UL) /*!< IWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_WWDT_Pos (4UL) /*!< WWDT (Bit 4) */ +#define SYSCTRL_APBEN1_WWDT_Msk (0x10UL) /*!< WWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_RTC_Pos (3UL) /*!< RTC (Bit 3) */ +#define SYSCTRL_APBEN1_RTC_Msk (0x8UL) /*!< RTC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_GTIM2_Pos (2UL) /*!< GTIM2 (Bit 2) */ +#define SYSCTRL_APBEN1_GTIM2_Msk (0x4UL) /*!< GTIM2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_GTIM1_Pos (1UL) /*!< GTIM1 (Bit 1) */ +#define SYSCTRL_APBEN1_GTIM1_Msk (0x2UL) /*!< GTIM1 (Bitfield-Mask: 0x01) */ +/* ======================================================== AHBRST ========================================================= */ +#define SYSCTRL_AHBRST_GPIOF_Pos (9UL) /*!< GPIOF (Bit 9) */ +#define SYSCTRL_AHBRST_GPIOF_Msk (0x200UL) /*!< GPIOF (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_GPIOC_Pos (6UL) /*!< GPIOC (Bit 6) */ +#define SYSCTRL_AHBRST_GPIOC_Msk (0x40UL) /*!< GPIOC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_GPIOB_Pos (5UL) /*!< GPIOB (Bit 5) */ +#define SYSCTRL_AHBRST_GPIOB_Msk (0x20UL) /*!< GPIOB (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_GPIOA_Pos (4UL) /*!< GPIOA (Bit 4) */ +#define SYSCTRL_AHBRST_GPIOA_Msk (0x10UL) /*!< GPIOA (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_CRC_Pos (2UL) /*!< CRC (Bit 2) */ +#define SYSCTRL_AHBRST_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_FLASH_Pos (1UL) /*!< FLASH (Bit 1) */ +#define SYSCTRL_AHBRST_FLASH_Msk (0x2UL) /*!< FLASH (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_DMA_Pos (0UL) /*!< DMA (Bit 0) */ +#define SYSCTRL_AHBRST_DMA_Msk (0x1UL) /*!< DMA (Bitfield-Mask: 0x01) */ +/* ======================================================== APBRST2 ======================================================== */ +#define SYSCTRL_APBRST2_AWT_Pos (13UL) /*!< AWT (Bit 13) */ +#define SYSCTRL_APBRST2_AWT_Msk (0x2000UL) /*!< AWT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_BTIM_Pos (12UL) /*!< BTIM (Bit 12) */ +#define SYSCTRL_APBRST2_BTIM_Msk (0x1000UL) /*!< BTIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_GTIM4_Pos (11UL) /*!< GTIM4 (Bit 11) */ +#define SYSCTRL_APBRST2_GTIM4_Msk (0x800UL) /*!< GTIM4 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_GTIM3_Pos (10UL) /*!< GTIM3 (Bit 10) */ +#define SYSCTRL_APBRST2_GTIM3_Msk (0x400UL) /*!< GTIM3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_UART1_Pos (9UL) /*!< UART1 (Bit 9) */ +#define SYSCTRL_APBRST2_UART1_Msk (0x200UL) /*!< UART1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_SPI1_Pos (8UL) /*!< SPI1 (Bit 8) */ +#define SYSCTRL_APBRST2_SPI1_Msk (0x100UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_ATIM_Pos (7UL) /*!< ATIM (Bit 7) */ +#define SYSCTRL_APBRST2_ATIM_Msk (0x80UL) /*!< ATIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_VC_Pos (4UL) /*!< VC (Bit 4) */ +#define SYSCTRL_APBRST2_VC_Msk (0x10UL) /*!< VC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_ADC_Pos (2UL) /*!< ADC (Bit 2) */ +#define SYSCTRL_APBRST2_ADC_Msk (0x4UL) /*!< ADC (Bitfield-Mask: 0x01) */ +/* ======================================================== APBRST1 ======================================================== */ +#define SYSCTRL_APBRST1_I2C2_Pos (12UL) /*!< I2C2 (Bit 12) */ +#define SYSCTRL_APBRST1_I2C2_Msk (0x1000UL) /*!< I2C2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_I2C1_Pos (11UL) /*!< I2C1 (Bit 11) */ +#define SYSCTRL_APBRST1_I2C1_Msk (0x800UL) /*!< I2C1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_UART3_Pos (8UL) /*!< UART3 (Bit 8) */ +#define SYSCTRL_APBRST1_UART3_Msk (0x100UL) /*!< UART3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_UART2_Pos (7UL) /*!< UART2 (Bit 7) */ +#define SYSCTRL_APBRST1_UART2_Msk (0x80UL) /*!< UART2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_SPI2_Pos (6UL) /*!< SPI2 (Bit 6) */ +#define SYSCTRL_APBRST1_SPI2_Msk (0x40UL) /*!< SPI2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_IWDT_Pos (5UL) /*!< IWDT (Bit 5) */ +#define SYSCTRL_APBRST1_IWDT_Msk (0x20UL) /*!< IWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_WWDT_Pos (4UL) /*!< WWDT (Bit 4) */ +#define SYSCTRL_APBRST1_WWDT_Msk (0x10UL) /*!< WWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_RTC_Pos (3UL) /*!< RTC (Bit 3) */ +#define SYSCTRL_APBRST1_RTC_Msk (0x8UL) /*!< RTC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_GTIM2_Pos (2UL) /*!< GTIM2 (Bit 2) */ +#define SYSCTRL_APBRST1_GTIM2_Msk (0x4UL) /*!< GTIM2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_GTIM1_Pos (1UL) /*!< GTIM1 (Bit 1) */ +#define SYSCTRL_APBRST1_GTIM1_Msk (0x2UL) /*!< GTIM1 (Bitfield-Mask: 0x01) */ +/* ======================================================= RESETFLAG ======================================================= */ +#define SYSCTRL_RESETFLAG_SYSRESETREQ_Pos (9UL) /*!< SYSRESETREQ (Bit 9) */ +#define SYSCTRL_RESETFLAG_SYSRESETREQ_Msk (0x200UL) /*!< SYSRESETREQ (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_LOCKUP_Pos (8UL) /*!< LOCKUP (Bit 8) */ +#define SYSCTRL_RESETFLAG_LOCKUP_Msk (0x100UL) /*!< LOCKUP (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_RSTB_Pos (6UL) /*!< RSTB (Bit 6) */ +#define SYSCTRL_RESETFLAG_RSTB_Msk (0x40UL) /*!< RSTB (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_WWDT_Pos (5UL) /*!< WWDT (Bit 5) */ +#define SYSCTRL_RESETFLAG_WWDT_Msk (0x20UL) /*!< WWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_IWDT_Pos (4UL) /*!< IWDT (Bit 4) */ +#define SYSCTRL_RESETFLAG_IWDT_Msk (0x10UL) /*!< IWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_LVD_Pos (3UL) /*!< LVD (Bit 3) */ +#define SYSCTRL_RESETFLAG_LVD_Msk (0x8UL) /*!< LVD (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_POR_Pos (0UL) /*!< POR (Bit 0) */ +#define SYSCTRL_RESETFLAG_POR_Msk (0x1UL) /*!< POR (Bitfield-Mask: 0x01) */ +/* ======================================================= GTIM1CAP ======================================================== */ +#define SYSCTRL_GTIM1CAP_CH4_Pos (12UL) /*!< CH4 (Bit 12) */ +#define SYSCTRL_GTIM1CAP_CH4_Msk (0x7000UL) /*!< CH4 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM1CAP_CH3_Pos (8UL) /*!< CH3 (Bit 8) */ +#define SYSCTRL_GTIM1CAP_CH3_Msk (0x700UL) /*!< CH3 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM1CAP_CH2_Pos (4UL) /*!< CH2 (Bit 4) */ +#define SYSCTRL_GTIM1CAP_CH2_Msk (0x70UL) /*!< CH2 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM1CAP_CH1_Pos (0UL) /*!< CH1 (Bit 0) */ +#define SYSCTRL_GTIM1CAP_CH1_Msk (0x7UL) /*!< CH1 (Bitfield-Mask: 0x07) */ +/* ======================================================= GTIM2CAP ======================================================== */ +#define SYSCTRL_GTIM2CAP_CH4_Pos (12UL) /*!< CH4 (Bit 12) */ +#define SYSCTRL_GTIM2CAP_CH4_Msk (0x7000UL) /*!< CH4 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM2CAP_CH3_Pos (8UL) /*!< CH3 (Bit 8) */ +#define SYSCTRL_GTIM2CAP_CH3_Msk (0x700UL) /*!< CH3 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM2CAP_CH2_Pos (4UL) /*!< CH2 (Bit 4) */ +#define SYSCTRL_GTIM2CAP_CH2_Msk (0x70UL) /*!< CH2 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM2CAP_CH1_Pos (0UL) /*!< CH1 (Bit 0) */ +#define SYSCTRL_GTIM2CAP_CH1_Msk (0x7UL) /*!< CH1 (Bitfield-Mask: 0x07) */ +/* ======================================================= GTIM3CAP ======================================================== */ +#define SYSCTRL_GTIM3CAP_CH4_Pos (12UL) /*!< CH4 (Bit 12) */ +#define SYSCTRL_GTIM3CAP_CH4_Msk (0x7000UL) /*!< CH4 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM3CAP_CH3_Pos (8UL) /*!< CH3 (Bit 8) */ +#define SYSCTRL_GTIM3CAP_CH3_Msk (0x700UL) /*!< CH3 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM3CAP_CH2_Pos (4UL) /*!< CH2 (Bit 4) */ +#define SYSCTRL_GTIM3CAP_CH2_Msk (0x70UL) /*!< CH2 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM3CAP_CH1_Pos (0UL) /*!< CH1 (Bit 0) */ +#define SYSCTRL_GTIM3CAP_CH1_Msk (0x7UL) /*!< CH1 (Bitfield-Mask: 0x07) */ +/* ======================================================= GTIM4CAP ======================================================== */ +#define SYSCTRL_GTIM4CAP_CH4_Pos (12UL) /*!< CH4 (Bit 12) */ +#define SYSCTRL_GTIM4CAP_CH4_Msk (0x7000UL) /*!< CH4 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM4CAP_CH3_Pos (8UL) /*!< CH3 (Bit 8) */ +#define SYSCTRL_GTIM4CAP_CH3_Msk (0x700UL) /*!< CH3 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM4CAP_CH2_Pos (4UL) /*!< CH2 (Bit 4) */ +#define SYSCTRL_GTIM4CAP_CH2_Msk (0x70UL) /*!< CH2 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM4CAP_CH1_Pos (0UL) /*!< CH1 (Bit 0) */ +#define SYSCTRL_GTIM4CAP_CH1_Msk (0x7UL) /*!< CH1 (Bitfield-Mask: 0x07) */ +/* ======================================================== ATIMETR ======================================================== */ +#define SYSCTRL_ATIMETR_ATIMETR_Pos (0UL) /*!< ATIMETR (Bit 0) */ +#define SYSCTRL_ATIMETR_ATIMETR_Msk (0x7UL) /*!< ATIMETR (Bitfield-Mask: 0x07) */ +/* ======================================================== GTIMETR ======================================================== */ +#define SYSCTRL_GTIMETR_GTIM4ETR_Pos (12UL) /*!< GTIM4ETR (Bit 12) */ +#define SYSCTRL_GTIMETR_GTIM4ETR_Msk (0x7000UL) /*!< GTIM4ETR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIMETR_GTIM3ETR_Pos (8UL) /*!< GTIM3ETR (Bit 8) */ +#define SYSCTRL_GTIMETR_GTIM3ETR_Msk (0x700UL) /*!< GTIM3ETR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIMETR_GTIM2ETR_Pos (4UL) /*!< GTIM2ETR (Bit 4) */ +#define SYSCTRL_GTIMETR_GTIM2ETR_Msk (0x70UL) /*!< GTIM2ETR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIMETR_GTIM1ETR_Pos (0UL) /*!< GTIM1ETR (Bit 0) */ +#define SYSCTRL_GTIMETR_GTIM1ETR_Msk (0x7UL) /*!< GTIM1ETR (Bitfield-Mask: 0x07) */ +/* ======================================================== TIMITR ========================================================= */ +#define SYSCTRL_TIMITR_BTIM3ITR_Pos (21UL) /*!< BTIM3ITR (Bit 21) */ +#define SYSCTRL_TIMITR_BTIM3ITR_Msk (0xe00000UL) /*!< BTIM3ITR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_TIMITR_BTIM2ITR_Pos (18UL) /*!< BTIM2ITR (Bit 18) */ +#define SYSCTRL_TIMITR_BTIM2ITR_Msk (0x1c0000UL) /*!< BTIM2ITR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_TIMITR_BTIM1ITR_Pos (15UL) /*!< BTIM1ITR (Bit 15) */ +#define SYSCTRL_TIMITR_BTIM1ITR_Msk (0x38000UL) /*!< BTIM1ITR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_TIMITR_GTIM4ITR_Pos (12UL) /*!< GTIM4ITR (Bit 12) */ +#define SYSCTRL_TIMITR_GTIM4ITR_Msk (0x7000UL) /*!< GTIM4ITR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_TIMITR_GTIM3ITR_Pos (9UL) /*!< GTIM3ITR (Bit 9) */ +#define SYSCTRL_TIMITR_GTIM3ITR_Msk (0xe00UL) /*!< GTIM3ITR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_TIMITR_GTIM2ITR_Pos (6UL) /*!< GTIM2ITR (Bit 6) */ +#define SYSCTRL_TIMITR_GTIM2ITR_Msk (0x1c0UL) /*!< GTIM2ITR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_TIMITR_GTIM1ITR_Pos (3UL) /*!< GTIM1ITR (Bit 3) */ +#define SYSCTRL_TIMITR_GTIM1ITR_Msk (0x38UL) /*!< GTIM1ITR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_TIMITR_ATIMITR_Pos (0UL) /*!< ATIMITR (Bit 0) */ +#define SYSCTRL_TIMITR_ATIMITR_Msk (0x7UL) /*!< ATIMITR (Bitfield-Mask: 0x07) */ +/* ========================================================== MCO ========================================================== */ +#define SYSCTRL_MCO_DIV_Pos (4UL) /*!< DIV (Bit 4) */ +#define SYSCTRL_MCO_DIV_Msk (0x70UL) /*!< DIV (Bitfield-Mask: 0x07) */ +#define SYSCTRL_MCO_SOURCE_Pos (0UL) /*!< SOURCE (Bit 0) */ +#define SYSCTRL_MCO_SOURCE_Msk (0xfUL) /*!< SOURCE (Bitfield-Mask: 0x0f) */ +/* ========================================================= IRMOD ========================================================= */ +#define SYSCTRL_IRMOD_MOD_Pos (0UL) /*!< MOD (Bit 0) */ +#define SYSCTRL_IRMOD_MOD_Msk (0xfUL) /*!< MOD (Bitfield-Mask: 0x0f) */ + + +/* =========================================================================================================================== */ +/* ================ UART ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define UARTx_CR1_OVER_Pos (9UL) /*!< OVER (Bit 9) */ +#define UARTx_CR1_OVER_Msk (0x600UL) /*!< OVER (Bitfield-Mask: 0x03) */ +#define UARTx_CR1_START_Pos (8UL) /*!< START (Bit 8) */ +#define UARTx_CR1_START_Msk (0x100UL) /*!< START (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_SYNC_Pos (6UL) /*!< SYNC (Bit 6) */ +#define UARTx_CR1_SYNC_Msk (0x40UL) /*!< SYNC (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_STOP_Pos (4UL) /*!< STOP (Bit 4) */ +#define UARTx_CR1_STOP_Msk (0x30UL) /*!< STOP (Bitfield-Mask: 0x03) */ +#define UARTx_CR1_PARITY_Pos (2UL) /*!< PARITY (Bit 2) */ +#define UARTx_CR1_PARITY_Msk (0xcUL) /*!< PARITY (Bitfield-Mask: 0x03) */ +#define UARTx_CR1_RXEN_Pos (1UL) /*!< RXEN (Bit 1) */ +#define UARTx_CR1_RXEN_Msk (0x2UL) /*!< RXEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_TXEN_Pos (0UL) /*!< TXEN (Bit 0) */ +#define UARTx_CR1_TXEN_Msk (0x1UL) /*!< TXEN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define UARTx_CR2_SOURCE_Pos (8UL) /*!< SOURCE (Bit 8) */ +#define UARTx_CR2_SOURCE_Msk (0x300UL) /*!< SOURCE (Bitfield-Mask: 0x03) */ +#define UARTx_CR2_DMATX_Pos (7UL) /*!< DMATX (Bit 7) */ +#define UARTx_CR2_DMATX_Msk (0x80UL) /*!< DMATX (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_DMARX_Pos (6UL) /*!< DMARX (Bit 6) */ +#define UARTx_CR2_DMARX_Msk (0x40UL) /*!< DMARX (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_TXINV_Pos (5UL) /*!< TXINV (Bit 5) */ +#define UARTx_CR2_TXINV_Msk (0x20UL) /*!< TXINV (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_RXINV_Pos (4UL) /*!< RXINV (Bit 4) */ +#define UARTx_CR2_RXINV_Msk (0x10UL) /*!< RXINV (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_RTSEN_Pos (3UL) /*!< RTSEN (Bit 3) */ +#define UARTx_CR2_RTSEN_Msk (0x8UL) /*!< RTSEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_CTSEN_Pos (2UL) /*!< CTSEN (Bit 2) */ +#define UARTx_CR2_CTSEN_Msk (0x4UL) /*!< CTSEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_SIGNAL_Pos (1UL) /*!< SIGNAL (Bit 1) */ +#define UARTx_CR2_SIGNAL_Msk (0x2UL) /*!< SIGNAL (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_ADDREN_Pos (0UL) /*!< ADDREN (Bit 0) */ +#define UARTx_CR2_ADDREN_Msk (0x1UL) /*!< ADDREN (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define UARTx_IER_CTS_Pos (6UL) /*!< CTS (Bit 6) */ +#define UARTx_IER_CTS_Msk (0x40UL) /*!< CTS (Bitfield-Mask: 0x01) */ +#define UARTx_IER_PE_Pos (4UL) /*!< PE (Bit 4) */ +#define UARTx_IER_PE_Msk (0x10UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UARTx_IER_FE_Pos (3UL) /*!< FE (Bit 3) */ +#define UARTx_IER_FE_Msk (0x8UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UARTx_IER_RC_Pos (2UL) /*!< RC (Bit 2) */ +#define UARTx_IER_RC_Msk (0x4UL) /*!< RC (Bitfield-Mask: 0x01) */ +#define UARTx_IER_TC_Pos (1UL) /*!< TC (Bit 1) */ +#define UARTx_IER_TC_Msk (0x2UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define UARTx_IER_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define UARTx_IER_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define UARTx_ISR_TXBUSY_Pos (8UL) /*!< TXBUSY (Bit 8) */ +#define UARTx_ISR_TXBUSY_Msk (0x100UL) /*!< TXBUSY (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_CTSLV_Pos (7UL) /*!< CTSLV (Bit 7) */ +#define UARTx_ISR_CTSLV_Msk (0x80UL) /*!< CTSLV (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_CTS_Pos (6UL) /*!< CTS (Bit 6) */ +#define UARTx_ISR_CTS_Msk (0x40UL) /*!< CTS (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_MATCH_Pos (5UL) /*!< MATCH (Bit 5) */ +#define UARTx_ISR_MATCH_Msk (0x20UL) /*!< MATCH (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_PE_Pos (4UL) /*!< PE (Bit 4) */ +#define UARTx_ISR_PE_Msk (0x10UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_FE_Pos (3UL) /*!< FE (Bit 3) */ +#define UARTx_ISR_FE_Msk (0x8UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_RC_Pos (2UL) /*!< RC (Bit 2) */ +#define UARTx_ISR_RC_Msk (0x4UL) /*!< RC (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_TC_Pos (1UL) /*!< TC (Bit 1) */ +#define UARTx_ISR_TC_Msk (0x2UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define UARTx_ISR_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define UARTx_ICR_CTS_Pos (6UL) /*!< CTS (Bit 6) */ +#define UARTx_ICR_CTS_Msk (0x40UL) /*!< CTS (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_PE_Pos (4UL) /*!< PE (Bit 4) */ +#define UARTx_ICR_PE_Msk (0x10UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_FE_Pos (3UL) /*!< FE (Bit 3) */ +#define UARTx_ICR_FE_Msk (0x8UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_RC_Pos (2UL) /*!< RC (Bit 2) */ +#define UARTx_ICR_RC_Msk (0x4UL) /*!< RC (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_TC_Pos (1UL) /*!< TC (Bit 1) */ +#define UARTx_ICR_TC_Msk (0x2UL) /*!< TC (Bitfield-Mask: 0x01) */ +/* ========================================================= BRRI ========================================================== */ +#define UARTx_BRRI_BRRI_Pos (0UL) /*!< BRRI (Bit 0) */ +#define UARTx_BRRI_BRRI_Msk (0xffffUL) /*!< BRRI (Bitfield-Mask: 0xffff) */ +/* ========================================================= BRRF ========================================================== */ +#define UARTx_BRRF_BRRF_Pos (0UL) /*!< BRRF (Bit 0) */ +#define UARTx_BRRF_BRRF_Msk (0xfUL) /*!< BRRF (Bitfield-Mask: 0x0f) */ +/* ========================================================== RDR ========================================================== */ +#define UARTx_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ +#define UARTx_RDR_RDR_Msk (0x1ffUL) /*!< RDR (Bitfield-Mask: 0x1ff) */ +/* ========================================================== TDR ========================================================== */ +#define UARTx_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ +#define UARTx_TDR_TDR_Msk (0x1ffUL) /*!< TDR (Bitfield-Mask: 0x1ff) */ +/* ========================================================= ADDR ========================================================== */ +#define UARTx_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define UARTx_ADDR_ADDR_Msk (0xffUL) /*!< ADDR (Bitfield-Mask: 0xff) */ +/* ========================================================= MASK ========================================================== */ +#define UARTx_MASK_MASK_Pos (0UL) /*!< MASK (Bit 0) */ +#define UARTx_MASK_MASK_Msk (0xffUL) /*!< MASK (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ VC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DIV ========================================================== */ +#define VCx_DIV_VIN_Pos (7UL) /*!< VIN (Bit 7) */ +#define VCx_DIV_VIN_Msk (0x80UL) /*!< VIN (Bitfield-Mask: 0x01) */ +#define VCx_DIV_EN_Pos (6UL) /*!< EN (Bit 6) */ +#define VCx_DIV_EN_Msk (0x40UL) /*!< EN (Bitfield-Mask: 0x01) */ +#define VCx_DIV_DIV_Pos (0UL) /*!< DIV (Bit 0) */ +#define VCx_DIV_DIV_Msk (0x3fUL) /*!< DIV (Bitfield-Mask: 0x3f) */ +/* ========================================================== CR0 ========================================================== */ +#define VCx_CR0_INN_Pos (12UL) /*!< INN (Bit 12) */ +#define VCx_CR0_INN_Msk (0xf000UL) /*!< INN (Bitfield-Mask: 0x0f) */ +#define VCx_CR0_INP_Pos (8UL) /*!< INP (Bit 8) */ +#define VCx_CR0_INP_Msk (0xf00UL) /*!< INP (Bitfield-Mask: 0x0f) */ +#define VCx_CR0_WINDOW_Pos (7UL) /*!< WINDOW (Bit 7) */ +#define VCx_CR0_WINDOW_Msk (0x80UL) /*!< WINDOW (Bitfield-Mask: 0x01) */ +#define VCx_CR0_POL_Pos (6UL) /*!< POL (Bit 6) */ +#define VCx_CR0_POL_Msk (0x40UL) /*!< POL (Bitfield-Mask: 0x01) */ +#define VCx_CR0_IE_Pos (5UL) /*!< IE (Bit 5) */ +#define VCx_CR0_IE_Msk (0x20UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define VCx_CR0_HYS_Pos (3UL) /*!< HYS (Bit 3) */ +#define VCx_CR0_HYS_Msk (0x18UL) /*!< HYS (Bitfield-Mask: 0x03) */ +#define VCx_CR0_RESP_Pos (1UL) /*!< RESP (Bit 1) */ +#define VCx_CR0_RESP_Msk (0x6UL) /*!< RESP (Bitfield-Mask: 0x03) */ +#define VCx_CR0_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define VCx_CR0_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ +#define VCx_CR1_BLANKFLT_Pos (13UL) /*!< BLANKFLT (Bit 13) */ +#define VCx_CR1_BLANKFLT_Msk (0xe000UL) /*!< BLANKFLT (Bitfield-Mask: 0x07) */ +#define VCx_CR1_BLANKCH3B_Pos (12UL) /*!< BLANKCH3B (Bit 12) */ +#define VCx_CR1_BLANKCH3B_Msk (0x1000UL) /*!< BLANKCH3B (Bitfield-Mask: 0x01) */ +#define VCx_CR1_BLANKCH2B_Pos (11UL) /*!< BLANKCH2B (Bit 11) */ +#define VCx_CR1_BLANKCH2B_Msk (0x800UL) /*!< BLANKCH2B (Bitfield-Mask: 0x01) */ +#define VCx_CR1_BLANKCH1B_Pos (10UL) /*!< BLANKCH1B (Bit 10) */ +#define VCx_CR1_BLANKCH1B_Msk (0x400UL) /*!< BLANKCH1B (Bitfield-Mask: 0x01) */ +#define VCx_CR1_ATIMBK_Pos (9UL) /*!< ATIMBK (Bit 9) */ +#define VCx_CR1_ATIMBK_Msk (0x200UL) /*!< ATIMBK (Bitfield-Mask: 0x01) */ +#define VCx_CR1_ATIMCLR_Pos (8UL) /*!< ATIMCLR (Bit 8) */ +#define VCx_CR1_ATIMCLR_Msk (0x100UL) /*!< ATIMCLR (Bitfield-Mask: 0x01) */ +#define VCx_CR1_HIGHIE_Pos (7UL) /*!< HIGHIE (Bit 7) */ +#define VCx_CR1_HIGHIE_Msk (0x80UL) /*!< HIGHIE (Bitfield-Mask: 0x01) */ +#define VCx_CR1_RISEIE_Pos (6UL) /*!< RISEIE (Bit 6) */ +#define VCx_CR1_RISEIE_Msk (0x40UL) /*!< RISEIE (Bitfield-Mask: 0x01) */ +#define VCx_CR1_FALLIE_Pos (5UL) /*!< FALLIE (Bit 5) */ +#define VCx_CR1_FALLIE_Msk (0x20UL) /*!< FALLIE (Bitfield-Mask: 0x01) */ +#define VCx_CR1_FLTCLK_Pos (4UL) /*!< FLTCLK (Bit 4) */ +#define VCx_CR1_FLTCLK_Msk (0x10UL) /*!< FLTCLK (Bitfield-Mask: 0x01) */ +#define VCx_CR1_FLTTIME_Pos (1UL) /*!< FLTTIME (Bit 1) */ +#define VCx_CR1_FLTTIME_Msk (0xeUL) /*!< FLTTIME (Bitfield-Mask: 0x07) */ +#define VCx_CR1_FLTEN_Pos (0UL) /*!< FLTEN (Bit 0) */ +#define VCx_CR1_FLTEN_Msk (0x1UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ +/* ========================================================== SR =========================================================== */ +#define VCx_SR_READY_Pos (2UL) /*!< READY (Bit 2) */ +#define VCx_SR_READY_Msk (0x4UL) /*!< READY (Bitfield-Mask: 0x01) */ +#define VCx_SR_FLTV_Pos (1UL) /*!< FLTV (Bit 1) */ +#define VCx_SR_FLTV_Msk (0x2UL) /*!< FLTV (Bitfield-Mask: 0x01) */ +#define VCx_SR_INTF_Pos (0UL) /*!< INTF (Bit 0) */ +#define VCx_SR_INTF_Msk (0x1UL) /*!< INTF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ WWDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define WWDT_CR0_EN_Pos (7UL) /*!< EN (Bit 7) */ +#define WWDT_CR0_EN_Msk (0x80UL) /*!< EN (Bitfield-Mask: 0x01) */ +#define WWDT_CR0_WCNT_Pos (0UL) /*!< WCNT (Bit 0) */ +#define WWDT_CR0_WCNT_Msk (0x7fUL) /*!< WCNT (Bitfield-Mask: 0x7f) */ +/* ========================================================== CR1 ========================================================== */ +#define WWDT_CR1_IE_Pos (10UL) /*!< IE (Bit 10) */ +#define WWDT_CR1_IE_Msk (0x400UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define WWDT_CR1_PRS_Pos (7UL) /*!< PRS (Bit 7) */ +#define WWDT_CR1_PRS_Msk (0x380UL) /*!< PRS (Bitfield-Mask: 0x07) */ +#define WWDT_CR1_WINR_Pos (0UL) /*!< WINR (Bit 0) */ +#define WWDT_CR1_WINR_Msk (0x7fUL) /*!< WINR (Bitfield-Mask: 0x7f) */ +/* ========================================================== SR =========================================================== */ +#define WWDT_SR_POV_Pos (0UL) /*!< POV (Bit 0) */ +#define WWDT_SR_POV_Msk (0x1UL) /*!< POV (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + +#ifdef __cplusplus +} +#endif + +#endif /* CW32F030_H */ + + +/** @} */ /* End of group cw32f030 */ + +/** @} */ /* End of group CW Co.Ltd */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_adc.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_adc.h new file mode 100644 index 0000000..82a07a9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_adc.h @@ -0,0 +1,806 @@ +/** +* @file cw32f030_lvd.h +* @author WHXY +* @brief +* @version 0.1 +* @date 2021-07-01 +* +* @copyright Copyright (c) 2021 +* +*/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +#ifndef __CW32F030_ADC_H +#define __CW32F030_ADC_H + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "base_types.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup AdcGroup AD Converter (ADC) + ** + ******************************************************************************/ + +//@{ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define ADC_INT_PRIORITY ((uint32_t)3) /*ADC interrupt priority (lowest by default) */ + +#define COEFF_TS (0.0924f) +#define ADDR_TRIM_1P5 (0x0001260A) +#define ADDR_TRIM_2P5 (0x0001260C) +#define ADDR_T0 (0x00012609) +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition + * @{ + */ +#define ADC_IT_READY ((uint16_t)0x0080) +#define ADC_IT_OVW ((uint16_t)0x0040) +#define ADC_IT_WDTR ((uint16_t)0x0020) +#define ADC_IT_WDTH ((uint16_t)0x0010) +#define ADC_IT_WDTL ((uint16_t)0x0008) +#define ADC_IT_EOA ((uint16_t)0x0004) +#define ADC_IT_EOS ((uint16_t)0x0002) +#define ADC_IT_EOC ((uint16_t)0x0001) + +#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x00) && ((IT) != 0x00)) +#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_READY) || \ + ((IT) == ADC_IT_OVW) || \ + ((IT) == ADC_IT_WDTR) || \ + ((IT) == ADC_IT_WDTH) || \ + ((IT) == ADC_IT_WDTL) || \ + ((IT) == ADC_IT_EOA) || \ + ((IT) == ADC_IT_EOS) || \ + ((IT) == ADC_IT_EOC)) + + +/** @defgroup ADC external interrupts_definition + * @{ + */ +#define ADC_TRIG_DMA ((uint16_t)0x8000) +#define ADC_TRIG_I2C2 ((uint16_t)0x4000) +#define ADC_TRIG_I2C1 ((uint16_t)0x2000) +#define ADC_TRIG_SPI2 ((uint16_t)0x1000) +#define ADC_TRIG_SPI1 ((uint16_t)0x0800) +#define ADC_TRIG_UART3 ((uint16_t)0x0400) +#define ADC_TRIG_UART2 ((uint16_t)0x0200) +#define ADC_TRIG_UART1 ((uint16_t)0x0100) +#define ADC_TRIG_BTIM3 ((uint16_t)0x0080) +#define ADC_TRIG_BTIM2 ((uint16_t)0x0040) +#define ADC_TRIG_BTIM1 ((uint16_t)0x0020) +#define ADC_TRIG_GTIM4 ((uint16_t)0x0010) +#define ADC_TRIG_GTIM3 ((uint16_t)0x0008) +#define ADC_TRIG_GTIM2 ((uint16_t)0x0004) +#define ADC_TRIG_GTIM1 ((uint16_t)0x0002) +#define ADC_TRIG_ATIM ((uint16_t)0x0001) + +#define IS_ADC_TRIG(TRIG) ((((TRIG) & (uint16_t)0x0000) == 0x00) && ((TRIG) != 0x00)) +#define IS_ADC_GET_TRIG(TRIG) (((TRIG) == ADC_TRIG_DMA)|| \ + ((TRIG) == ADC_TRIG_I2C2) || \ + ((TRIG) == ADC_TRIG_I2C1) || \ + ((TRIG) == ADC_TRIG_SPI2) || \ + ((TRIG) == ADC_TRIG_SPI1) || \ + ((TRIG) == ADC_TRIG_UART3) || \ + ((TRIG) == ADC_TRIG_UART2) || \ + ((TRIG) == ADC_TRIG_UART1) || \ + ((TRIG) == ADC_TRIG_BTIM3) || \ + ((TRIG) == ADC_TRIG_BTIM2) || \ + ((TRIG) == ADC_TRIG_BTIM1) || \ + ((TRIG) == ADC_TRIG_GTIM4) || \ + ((TRIG) == ADC_TRIG_GTIM3) || \ + ((TRIG) == ADC_TRIG_GTIM2) || \ + ((TRIG) == ADC_TRIG_GTIM1) || \ + ((TRIG) == ADC_TRIG_ATIM)) + + +/****************************************************************************** + ** Global type definitions + *****************************************************************************/ + +/** @defgroup ADC_OpMode + * @{ + */ +#define ADC_SingleChOneMode ((uint32_t)0x00000000) +#define ADC_SingleChMoreMode ((uint32_t)0x00000002) +#define ADC_SingleChContinuousMode ((uint32_t)0x00000004) +#define ADC_SerialChContinuousMode ((uint32_t)0x00000006) +#define ADC_SerialChScanMode ((uint32_t)0x00000008) +#define ADC_SerialChMoreMode ((uint32_t)0x0000000A) +#define ADC_SerialChBreakMode ((uint32_t)0x0000000C) + + +#define IS_ADC_OP_MODE(OP_MODE) (((OP_MODE) == ADC_SingleChOneMode) || \ + ((OP_MODE) == ADC_SingleChMoreMode) || \ + ((OP_MODE) == ADC_SingleChContinuousMode) || \ + ((OP_MODE) == ADC_SerialChContinuousMode) || \ + ((OP_MODE) == ADC_SerialChScanMode) || \ + ((OP_MODE) == ADC_SerialChMoreMode) || \ + ((OP_MODE) == ADC_SerialChBreakMode)) + + +/** @defgroup ADC_ClkDiv + * @{ + */ +#define ADC_Clk_Div1 ((uint32_t)0x00000000) +#define ADC_Clk_Div2 ((uint32_t)0x00000100) +#define ADC_Clk_Div4 ((uint32_t)0x00000200) +#define ADC_Clk_Div8 ((uint32_t)0x00000300) +#define ADC_Clk_Div16 ((uint32_t)0x00000400) +#define ADC_Clk_Div32 ((uint32_t)0x00000500) +#define ADC_Clk_Div64 ((uint32_t)0x00000600) +#define ADC_Clk_Div128 ((uint32_t)0x00000700) + +#define IS_ADC_CLK_DIV(CLK_DIV) (((CLK_DIV) == ADC_Clk_Div1) || \ + ((CLK_DIV) == ADC_Clk_Div2) || \ + ((CLK_DIV) == ADC_Clk_Div4) || \ + ((CLK_DIV) == ADC_Clk_Div8) || \ + ((CLK_DIV) == ADC_Clk_Div16) || \ + ((CLK_DIV) == ADC_Clk_Div32) || \ + ((CLK_DIV) == ADC_Clk_Div64) || \ + ((CLK_DIV) == ADC_Clk_Div128)) + +/** @defgroup ADC_VrefSel + * @{ + */ +#define ADC_Vref_BGR1p5 ((uint32_t)0x00000000) +#define ADC_Vref_BGR2p5 ((uint32_t)0x00000040) +#define ADC_Vref_Extern1 ((uint32_t)0x00000080) +#define ADC_Vref_VDDA ((uint32_t)0x000000C0) + +#define IS_ADC_VREF_SEL(VREF_SEL) (((VREF_SEL) == ADC_Vref_BGR1p5) || \ + ((VREF_SEL) == ADC_Vref_BGR2p5) || \ + ((VREF_SEL) == ADC_Vref_Extern1) || \ + ((VREF_SEL) == ADC_Vref_VDDA)) + +/** @defgroup ADC_ChSel + * @{ + * 通道0输入PA00 + * 通道1输入PA01 + * 通道2输入PA02 + * 通道3输入PA03 + * 通道4输入PA04 + * 通道5输入PA05 + * 通道6输入PA06 + * 通道7输入PA07 + * 通道8输入PB00 + * 通道9输入PB01 + * 通道10输入PB02 + * 通道11输入PB10 + * 通道12输入PB11 + * 1/3 VDDA(必须使用输入增益) + * BGR_TS(必须使用输入增益) + * Vref1P2(必须使用输入增益) + */ +#define ADC_ExInputCH0 ((uint32_t)0x00000000) +#define ADC_ExInputCH1 ((uint32_t)0x00000001) +#define ADC_ExInputCH2 ((uint32_t)0x00000002) +#define ADC_ExInputCH3 ((uint32_t)0x00000003) +#define ADC_ExInputCH4 ((uint32_t)0x00000004) +#define ADC_ExInputCH5 ((uint32_t)0x00000005) +#define ADC_ExInputCH6 ((uint32_t)0x00000006) +#define ADC_ExInputCH7 ((uint32_t)0x00000007) +#define ADC_ExInputCH8 ((uint32_t)0x00000008) +#define ADC_ExInputCH9 ((uint32_t)0x00000009) +#define ADC_ExInputCH10 ((uint32_t)0x0000000A) +#define ADC_ExInputCH11 ((uint32_t)0x0000000B) +#define ADC_ExInputCH12 ((uint32_t)0x0000000C) +#define ADC_VddaDiV3Input ((uint32_t)0x0000000D) +#define ADC_TsInput ((uint32_t)0x0000000E) +#define ADC_Vref1P2Input ((uint32_t)0x0000000F) + +#define IS_ADC_CH_SEL(CH_SEL) (((CH_SEL) == ADC_ExInputCH0) || \ + ((CH_SEL) == ADC_ExInputCH1) || \ + ((CH_SEL) == ADC_ExInputCH2) || \ + ((CH_SEL) == ADC_ExInputCH3) || \ + ((CH_SEL) == ADC_ExInputCH4) || \ + ((CH_SEL) == ADC_ExInputCH5) || \ + ((CH_SEL) == ADC_ExInputCH6) || \ + ((CH_SEL) == ADC_ExInputCH7) || \ + ((CH_SEL) == ADC_ExInputCH8) || \ + ((CH_SEL) == ADC_ExInputCH9) || \ + ((CH_SEL) == ADC_ExInputCH10) || \ + ((CH_SEL) == ADC_ExInputCH11) || \ + ((CH_SEL) == ADC_ExInputCH12) || \ + ((CH_SEL) == ADC_VddaDiV3Input) || \ + ((CH_SEL) == ADC_TsInput) || \ + ((CH_SEL) == ADC_Vref1P2Input)) + +/** @defgroup ADC_SampleTime + * @{ + */ +#define ADC_SampTime5Clk ((uint32_t)0x00000000) +#define ADC_SampTime6Clk ((uint32_t)0x00000800) +#define ADC_SampTime8Clk ((uint32_t)0x00001000) +#define ADC_SampTime10Clk ((uint32_t)0x00001800) + +#define IS_ADC_SAMPLE_TIME(SAMPLE_TIME) (((SAMPLE_TIME) == ADC_SampTime5Clk) || \ + ((SAMPLE_TIME) == ADC_SampTime6Clk) || \ + ((SAMPLE_TIME) == ADC_SampTime8Clk) || \ + ((SAMPLE_TIME) == ADC_SampTime10Clk)) + + + +/** @defgroup ADC_TrigSel + * @{ + */ +#define ADC_TrigATimerDisable ((uint32_t)0x00000000) +#define ADC_TrigATimerEnable ((uint32_t)0x00000001) + +#define ADC_TrigGTimer1Disable ((uint32_t)0x00000000) +#define ADC_TrigGTimer1Enable ((uint32_t)0x00000002) + +#define ADC_TrigGTimer2Disable ((uint32_t)0x00000000) +#define ADC_TrigGTimer2Enable ((uint32_t)0x00000004) + +#define ADC_TrigGTimer3Disable ((uint32_t)0x00000000) +#define ADC_TrigGTimer3Enable ((uint32_t)0x00000008) + +#define ADC_TrigGTimer4Disable ((uint32_t)0x00000000) +#define ADC_TrigGTimer4Enable ((uint32_t)0x00000010) + +#define ADC_TrigBTimer1Disable ((uint32_t)0x00000000) +#define ADC_TrigBTimer1Enable ((uint32_t)0x00000020) + +#define ADC_TrigBTimer2Disable ((uint32_t)0x00000000) +#define ADC_TrigBTimer2Enable ((uint32_t)0x00000040) + +#define ADC_TrigBTimer3Disable ((uint32_t)0x00000000) +#define ADC_TrigBTimer3Enable ((uint32_t)0x00000080) + +#define ADC_TrigUart1Disable ((uint32_t)0x00000000) +#define ADC_TrigUart1Enable ((uint32_t)0x00000100) + +#define ADC_TrigUart2Disable ((uint32_t)0x00000000) +#define ADC_TrigUart2Enable ((uint32_t)0x00000200) + +#define ADC_TrigUart3Disable ((uint32_t)0x00000000) +#define ADC_TrigUart3Enable ((uint32_t)0x00000400) + +#define ADC_TrigSPI1Disable ((uint32_t)0x00000000) +#define ADC_TrigSPI1Enable ((uint32_t)0x00000800) + +#define ADC_TrigSPI2Disable ((uint32_t)0x00000000) +#define ADC_TrigSPI2Enable ((uint32_t)0x00001000) + +#define ADC_TrigI2C1Disable ((uint32_t)0x00000000) +#define ADC_TrigI2C1Enable ((uint32_t)0x00002000) + +#define ADC_TrigI2C2Disable ((uint32_t)0x00000000) +#define ADC_TrigI2C2Enable ((uint32_t)0x00004000) + +#define ADC_TrigDMADisable ((uint32_t)0x00000000) +#define ADC_TrigDMAEnable ((uint32_t)0x00008000) + +#define IS_ADC_TRIG_SEL(TRIG_SEL) (((TRIG_SEL) == ADC_TrigATimerDisable) || \ + ((TRIG_SEL) == ADC_TrigATimerEnable) || \ + ((TRIG_SEL) == ADC_TrigGTimer1Disable) || \ + ((TRIG_SEL) == ADC_TrigGTimer1Enable) || \ + ((TRIG_SEL) == ADC_TrigGTimer2Disable) || \ + ((TRIG_SEL) == ADC_TrigGTimer2Enable) || \ + ((TRIG_SEL) == ADC_TrigGTimer3Disable) || \ + ((TRIG_SEL) == ADC_TrigGTimer3Enable) || \ + ((TRIG_SEL) == ADC_TrigGTimer4Disable) || \ + ((TRIG_SEL) == ADC_TrigGTimer4Enable) || \ + ((TRIG_SEL) == ADC_TrigBTimer1Disable) || \ + ((TRIG_SEL) == ADC_TrigBTimer1Enable) || \ + ((TRIG_SEL) == ADC_TrigBTimer2Disable) || \ + ((TRIG_SEL) == ADC_TrigBTimer2Enable) || \ + ((TRIG_SEL) == ADC_TrigBTimer3Disable) || \ + ((TRIG_SEL) == ADC_TrigBTimer3Enable) || \ + ((TRIG_SEL) == ADC_TrigUart1Disable) || \ + ((TRIG_SEL) == ADC_TrigUart1Enable) || \ + ((TRIG_SEL) == ADC_TrigUart2Disable) || \ + ((TRIG_SEL) == ADC_TrigUart2Enable) || \ + ((TRIG_SEL) == ADC_TrigUart3Disable) || \ + ((TRIG_SEL) == ADC_TrigUart3Enable) || \ + ((TRIG_SEL) == ADC_TrigSPI1Disable) || \ + ((TRIG_SEL) == ADC_TrigSPI1Enable) || \ + ((TRIG_SEL) == ADC_TrigSPI2Disable) || \ + ((TRIG_SEL) == ADC_TrigSPI2Enable) || \ + ((TRIG_SEL) == ADC_TrigI2C1Disable) || \ + ((TRIG_SEL) == ADC_TrigI2C1Enable) || \ + ((TRIG_SEL) == ADC_TrigI2C2Disable) || \ + ((TRIG_SEL) == ADC_TrigI2C2Enable) || \ + ((TRIG_SEL) == ADC_TrigDMADisable) || \ + ((TRIG_SEL) == ADC_TrigDMAEnable)) + + + +/** @defgroup ADC_SqrEns + * @{ + */ +#define ADC_SqrEns0 ((uint32_t)0x00000000) +#define ADC_SqrEns01 ((uint32_t)0x00010000) +#define ADC_SqrEns02 ((uint32_t)0x00020000) +#define ADC_SqrEns03 ((uint32_t)0x00030000) + +#define IS_ADC_SQR_ENS(SQR_ENS) (((SQR_ENS) == ADC_SqrEns0) || \ + ((SQR_ENS) == ADC_SqrEns01) || \ + ((SQR_ENS) == ADC_SqrEns02) || \ + ((SQR_ENS) == ADC_SqrEns03)) + + + +/** @defgroup ADC_SqrChmux + * @{ + * 通道0输入PA00 + * 通道1输入PA01 + * 通道2输入PA02 + * 通道3输入PA03 + * 通道4输入PA04 + * 通道5输入PA05 + * 通道6输入PA06 + * 通道7输入PA07 + * 通道8输入PB00 + * 通道9输入PB01 + * 通道10输入PB02 + * 通道11输入PB10 + * 通道12输入PB11 + * 1/3 VDDA(必须使用输入增益) + * BGR_TS(必须使用输入增益) + * Vref1P2(必须使用输入增益) + */ +#define ADC_SqrCh0 ((uint32_t)0x00000000) +#define ADC_SqrCh1 ((uint32_t)0x00000001) +#define ADC_SqrCh2 ((uint32_t)0x00000002) +#define ADC_SqrCh3 ((uint32_t)0x00000003) +#define ADC_SqrCh4 ((uint32_t)0x00000004) +#define ADC_SqrCh5 ((uint32_t)0x00000005) +#define ADC_SqrCh6 ((uint32_t)0x00000006) +#define ADC_SqrCh7 ((uint32_t)0x00000007) +#define ADC_SqrCh8 ((uint32_t)0x00000008) +#define ADC_SqrCh9 ((uint32_t)0x00000009) +#define ADC_SqrCh10 ((uint32_t)0x0000000A) +#define ADC_SqrCh11 ((uint32_t)0x0000000B) +#define ADC_SqrCh12 ((uint32_t)0x0000000C) +#define ADC_SqrVddaDiV3 ((uint32_t)0x0000000D) +#define ADC_SqrTs ((uint32_t)0x0000000E) +#define ADC_SqrVref1P2 ((uint32_t)0x0000000F) + +#define IS_ADC_SQR_CH(SQR_CH) (((SQR_CH) == ADC_SqrCh0) || \ + ((SQR_CH) == ADC_SqrCh1) || \ + ((SQR_CH) == ADC_SqrCh2) || \ + ((SQR_CH) == ADC_SqrCh3) || \ + ((SQR_CH) == ADC_SqrCh4) || \ + ((SQR_CH) == ADC_SqrCh5) || \ + ((SQR_CH) == ADC_SqrCh6) || \ + ((SQR_CH) == ADC_SqrCh7) || \ + ((SQR_CH) == ADC_SqrCh8) || \ + ((SQR_CH) == ADC_SqrCh9) || \ + ((SQR_CH) == ADC_SqrCh10) || \ + ((SQR_CH) == ADC_SqrCh11) || \ + ((SQR_CH) == ADC_SqrCh12) || \ + ((SQR_CH) == ADC_SqrVddaDiV3) || \ + ((SQR_CH) == ADC_SqrTs) || \ + ((SQR_CH) == ADC_SqrVref1P2)) + + + +/** @defgroup ADC_WdtChmux + * @{ + * 通道0输入PA00 + * 通道1输入PA01 + * 通道2输入PA02 + * 通道3输入PA03 + * 通道4输入PA04 + * 通道5输入PA05 + * 通道6输入PA06 + * 通道7输入PA07 + * 通道8输入PB00 + * 通道9输入PB01 + * 通道10输入PB02 + * 通道11输入PB10 + * 通道12输入PB11 + * 1/3 VDDA(必须使用输入增益) + * BGR_TS(必须使用输入增益) + * Vref1P2(必须使用输入增益) + */ +#define ADC_WdtCh0 ((uint32_t)0x00000000) +#define ADC_WdtCh1 ((uint32_t)0x00000100) +#define ADC_WdtCh2 ((uint32_t)0x00000200) +#define ADC_WdtCh3 ((uint32_t)0x00000300) +#define ADC_WdtCh4 ((uint32_t)0x00000400) +#define ADC_WdtCh5 ((uint32_t)0x00000500) +#define ADC_WdtCh6 ((uint32_t)0x00000600) +#define ADC_WdtCh7 ((uint32_t)0x00000700) +#define ADC_WdtCh8 ((uint32_t)0x00000800) +#define ADC_WdtCh9 ((uint32_t)0x00000900) +#define ADC_WdtCh10 ((uint32_t)0x00000A00) +#define ADC_WdtCh11 ((uint32_t)0x00000B00) +#define ADC_WdtCh12 ((uint32_t)0x00000C00) +#define ADC_WdtVddaDiV3 ((uint32_t)0x00000D00) +#define ADC_WdtTs ((uint32_t)0x00000E00) +#define ADC_WdtVref1P2 ((uint32_t)0x00000F00) + +#define IS_ADC_WDT_CH(WDT_CH) (((WDT_CH) == ADC_WdtCh0) || \ + ((WDT_CH) == ADC_WdtCh1) || \ + ((WDT_CH) == ADC_WdtCh2) || \ + ((WDT_CH) == ADC_WdtCh3) || \ + ((WDT_CH) == ADC_WdtCh4) || \ + ((WDT_CH) == ADC_WdtCh5) || \ + ((WDT_CH) == ADC_WdtCh6) || \ + ((WDT_CH) == ADC_WdtCh7) || \ + ((WDT_CH) == ADC_WdtCh8) || \ + ((WDT_CH) == ADC_WdtCh9) || \ + ((WDT_CH) == ADC_WdtCh10) || \ + ((WDT_CH) == ADC_WdtCh11) || \ + ((WDT_CH) == ADC_WdtCh12) || \ + ((WDT_CH) == ADC_WdtVddaDiV3) || \ + ((WDT_CH) == ADC_WdtTs) || \ + ((WDT_CH) == ADC_WdtVref1P2)) + + +/** @defgroup ADC_WdtAll + * @{ + */ +#define ADC_WdtDisable ((uint32_t)0x00000000) +#define ADC_WdtEnable ((uint32_t)0x00002000) + +#define IS_ADC_WDT_EN(WDT_EN) (((WDT_EN) == ADC_WdtDisable) || \ + ((WDT_EN) == ADC_WdtEnable)) + +/** @defgroup ADC_WdtrIrq + * @{ + */ +#define ADC_WdtrDisable ((uint32_t)0x00000000) +#define ADC_WdtrEnable ((uint32_t)0x00000020) + +#define IS_ADC_WDTR_EN(WDTR_EN) (((WDTR_EN) == ADC_WdtrDisable) || \ + ((WDTR_EN) == ADC_WdtrEnable)) + +/** @defghoup ADC_WdthIrq + * @{ + */ +#define ADC_WdthDisable ((uint32_t)0x00000000) +#define ADC_WdthEnable ((uint32_t)0x00000010) + +#define IS_ADC_WDTH_EN(WDTH_EN) (((WDTH_EN) == ADC_WdthDisable) || \ + ((WDTH_EN) == ADC_WdthEnable)) + +/** @defgloup ADC_WdtlIrq + * @{ + */ +#define ADC_WdtlDisable ((uint32_t)0x00000000) +#define ADC_WdtlEnable ((uint32_t)0x00000008) + +#define IS_ADC_WDTL_EN(WDTL_EN) (((WDTL_EN) == ADC_WdtlDisable) || \ + ((WDTL_EN) == ADC_WdtlEnable)) + + + +/** @defgroup ADC_Align + * @{ + */ +#define ADC_AlignRight ((uint32_t)0x00000000) +#define ADC_AlignLeft ((uint32_t)0x00000040) + +#define IS_ADC_DATA_ALIGN(DATA_ALIGN) (((DATA_ALIGN) == ADC_AlignRight)|| \ + ((DATA_ALIGN) == ADC_AlignLeft)) + + + +/** @defgroup ADC_DataDiscard + * @{ + */ +#define ADC_DiscardNull ((uint32_t)0x00000000) +#define ADC_DiscardEnable ((uint32_t)0x00000020) + +#define IS_ADC_DATA_DISCARD(DATA_DISCARD) (((DATA_DISCARD) == ADC_DiscardNull) || \ + ((DATA_DISCARD) == ADC_DiscardEnable)) + + + +/** @defgroup ADC_TsEn + * @{ + */ +#define ADC_TsDisable ((uint32_t)0x00000000) +#define ADC_TsEnable ((uint32_t)0x00000020) + +#define IS_ADC_TS_ENABLE(TS_ENABLE) (((TS_ENABLE) == ADC_TsDisable) || \ + ((TS_ENABLE) == ADC_TsEnable)) + +/** @defgroup ADC_InBufEn + * @{ + */ +#define ADC_BufDisable ((uint32_t)0x00000000) +#define ADC_BufEnable ((uint32_t)0x00002000) + +#define IS_ADC_BUF_ENABLE(BUF_ENABLE) (((BUF_ENABLE) == ADC_BufDisable) || \ + ((BUF_ENABLE) == ADC_BufEnable)) + +/** @defgroup ADC_DMAEn + * @{ + */ +#define ADC_DmaDisable ((uint32_t)0x00000000) +#define ADC_DmaEnable ((uint32_t)0x00000080) + +#define IS_ADC_DMA_ENABLE(DMA_ENABLE) (((DMA_ENABLE) == ADC_DmaDisable) || \ + ((DMA_ENABLE) == ADC_DmaEnable)) + +/** @defgroup ADC_AccEn + * @{ + */ +#define ADC_AccDisable ((uint32_t)0x00000000) +#define ADC_AccEnable ((uint32_t)0x00000100) + +#define IS_ADC_ACC_ENABLE(ACC_ENABLE) (((ACC_ENABLE) == ADC_AccDisable) || \ + ((ACC_ENABLE) == ADC_AccEnable)) + + + +/** @defgroup ADC_AutoStop + * @{ + */ +#define ADC_AutoStopDisable ((uint32_t)0x00000000) +#define ADC_AutoStopEnable ((uint32_t)0x00000002) + +#define IS_ADC_AUTO_STOP(AUTO_STOP) (((AUTO_STOP) == ADC_AutoStopDisable) || \ + ((AUTO_STOP) == ADC_AutoStopEnable)) + +/****************************************************************************** + * Extern type definitions ('typedef') * + ******************************************************************************/ + +/** + ****************************************************************************** + ** @brief ADC配置 + *****************************************************************************/ +typedef struct +{ + uint32_t ADC_OpMode; /*ADC操作模式*/ + + uint32_t ADC_ClkDiv; /*ADC时钟选择*/ + + uint32_t ADC_SampleTime; /*ADC采样时间*/ + + uint32_t ADC_VrefSel; /*ADC参考电压*/ + + uint32_t ADC_InBufEn; /*ADC输入增益使能*/ + + uint32_t ADC_TsEn; /*内置温度传感器使能*/ + + uint32_t ADC_DMAEn; /*ADC转换完成触发DMA使能*/ + + uint32_t ADC_Align; /*ADC转换结果对齐方式*/ + + uint32_t ADC_AccEn; /*转换结果累加使能*/ +} ADC_InitTypeDef; + +/** + ****************************************************************************** + ** @brief ADC模拟看门狗配置 + *****************************************************************************/ +typedef struct +{ + uint32_t ADC_WdtCh; /*ADC模拟看门狗通道*/ + + uint32_t ADC_WdtAll; /*ADC模拟看门狗使能*/ + + uint32_t ADC_WdtrIrq; /*ADC区间模拟看门狗使能*/ + + uint32_t ADC_WdthIrq; /*ADC上超出模拟看门狗使能*/ + + uint32_t ADC_WdtlIrq; /*ADC下超出模拟看门狗使能*/ + + uint32_t ADC_Vth; /*ADC模拟看门狗上阈值*/ + + uint32_t ADC_Vtl; /*ADC模拟看门狗下阈值*/ +} ADC_WdtTypeDef; + +/** + ****************************************************************************** + ** @brief ADC单通道配置 + *****************************************************************************/ +typedef struct +{ + uint32_t ADC_Chmux; /*ADC单通道转换模式待转换通道*/ + + uint32_t ADC_DiscardEn; /*单通道ADC转换结果保存策略配置*/ + + ADC_InitTypeDef ADC_InitStruct; /*ADC初始化*/ + + ADC_WdtTypeDef ADC_WdtStruct; /*ADC模拟看门狗配置*/ +} ADC_SingleChTypeDef; + +/** + ****************************************************************************** + ** @brief ADC序列配置 + *****************************************************************************/ +typedef struct +{ + uint32_t ADC_SqrEns; /*ADC序列转换的序列配置*/ + + uint32_t ADC_Sqr3Chmux; /*ADC序列3待转换通道*/ + + uint32_t ADC_Sqr2Chmux; /*ADC序列2待转换通道*/ + + uint32_t ADC_Sqr1Chmux; /*ADC序列1待转换通道*/ + + uint32_t ADC_Sqr0Chmux; /*ADC序列0待转换通道*/ + + ADC_InitTypeDef ADC_InitStruct; /*ADC初始化*/ +} ADC_SerialChTypeDef; + + +/** + ****************************************************************************** + ** @brief ADC中断配置 + *****************************************************************************/ +typedef struct +{ + boolean_t ADC_ReadyFlag; /*ADC初始化完成标志*/ + + boolean_t ADC_OvwIrq; /*ADC转换结果溢出中断*/ + + boolean_t ADC_WdtrIrq; /*ADC模拟看门狗区间中断*/ + + boolean_t ADC_WdthIrq; /*ADC模拟看门狗上阈值中断*/ + + boolean_t ADC_WdtlIrq; /*ADC模拟看门狗下阈值中断*/ + + boolean_t ADC_EoaIrq; /*ADC多次转换完成中断*/ + + boolean_t ADC_EosIrq; /*ADC序列转换完成中断*/ + + boolean_t ADC_EocIrq; /*ADC单次转换完成中断*/ +} ADC_IrqTypeDef; + + + + + +/****************************************************************************** + * Global variable definitions ('extern') + ******************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + ******************************************************************************/ +//ADC去初始化 +void ADC_DeInit(void); +//ADC初始化 +void ADC_Init(ADC_InitTypeDef *ADC_InitStruct); +//ADC默认值初始化 +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); +//ADC模拟看门狗默认值初始化 +void ADC_WdtInit(ADC_WdtTypeDef *ADC_WdtStruct); +//ADC使能 +void ADC_Enable(void); +//ADC禁用 +void ADC_Disable(void); + +//触发DMA读取命令 +void ADC_DMACmd(FunctionalState NewState); +//触发DMA读取使能 +void ADC_DMAEnable(void); +//触发DMA读取禁止 +void ADC_DMADisable(void); + +//ADC转换软件启动命令 +void ADC_SoftwareStartConvCmd(FunctionalState NewState); +//ADC外部中断触发源配置 +void ADC_ExtTrigCfg(uint16_t ADC_TRIG, FunctionalState NewState); + +//单通道转换模式公共配置 +void ADC_SingleChCommon(ADC_SingleChTypeDef *ADC_SingleChStruct); +//ADC单通道单次转换模式配置 +void ADC_SingleChOneModeCfg(ADC_SingleChTypeDef *ADC_SingleChStruct); +//ADC单通道多次转换模式配置 +void ADC_SingleChMoreModeCfg(ADC_SingleChTypeDef *ADC_SingleChStruct, uint8_t cntAdcSample); +//ADC单通道连续转换模式配置 +void ADC_SingleChContinuousModeCfg(ADC_SingleChTypeDef *ADC_SingleChStruct); +//ADC序列转换模式公共配置 +void ADC_SerialChCommon(ADC_SerialChTypeDef *ADC_SerialChStruct); +//ADC序列连续转换模式配置 +void ADC_SerialChContinuousModeCfg(ADC_SerialChTypeDef *ADC_SerialChStruct); +//ADC序列扫描转换模式配置 +void ADC_SerialChScanModeCfg(ADC_SerialChTypeDef *ADC_SerialChStruct); +//ADC序列多次转换模式配置 +void ADC_SerialChMoreModeCfg(ADC_SerialChTypeDef *ADC_SerialChStruct, uint8_t cntAdcSample); +//ADC序列断续转换模式配置 +void ADC_SerialChBreakModeCfg(ADC_SerialChTypeDef *ADC_SerialChStruct); + +//序列SQR0转换通道配置 +void ADC_Sqr0ChannelCfg(ADC_SerialChTypeDef *ADC_SerialChStruct); +//序列SQR0/SQR1转换通道配置 +void ADC_Sqr01ChannelCfg(ADC_SerialChTypeDef *ADC_SerialChStruct); +//序列SQR0~SQR2转换通道配置 +void ADC_Sqr02ChannelCfg(ADC_SerialChTypeDef *ADC_SerialChStruct); +//序列SQR0~SQR3转换通道配置 +void ADC_Sqr03ChannelCfg(ADC_SerialChTypeDef *ADC_SerialChStruct); + +//单通道模式的内置跟随器使能 +void ADC_BufEnSingleCh(uint32_t enAdcSampCh); +//序列模式的内置跟随器使能 +void ADC_BufEnSerialCh(uint32_t enAdcSampCh); + +//ADC模拟看门狗配置 +void ADC_WdtConfig(ADC_WdtTypeDef *ADC_WdtStruct); + +//ADC中断配置 +void ADC_ITConfig(uint16_t ADC_IT, FunctionalState NewState); +//ADC中断使能 +void ADC_EnableIrq(uint8_t intPriority); +//ADC中断禁止 +void ADC_DisableIrq(void); +//使能NVIC中ADC中断 +void ADC_EnableNvic(uint8_t intPriority); +//禁用NVIC中ADC中断 +void ADC_DisableNvic(void); +//获取ADC所有中断状态 +void ADC_GetITStatusAll(volatile uint8_t *pFlagAdcIrq); +//获取ADC指定的中断状态 +ITStatus ADC_GetITStatus(uint16_t ADC_IT); +//清除ADC所有中断状态 +void ADC_ClearITPendingAll(void); +//清除ADC指定的中断状态 +void ADC_ClearITPendingBit(uint16_t ADC_IT); + +//获取单次转换采样值 +uint16_t ADC_GetConversionValue(void); +//获取SQR0通道采样值 +void ADC_GetSqr0Result(uint16_t *pAdcResult); +//获取SQR1通道采样值 +void ADC_GetSqr1Result(uint16_t *pAdcResult); +//获取SQR2通道采样值 +void ADC_GetSqr2Result(uint16_t *pAdcResult); +//获取SQR3通道采样值 +void ADC_GetSqr3Result(uint16_t *pAdcResult); +//获取累加采样值 +void ADC_GetAccResult(uint32_t *pAdcAccResult); +//清零累加采样值 +void ADC_ClrAccResult(void); + +//设置参考电压 +void ADC_SetVref(uint32_t ADC_VrefSel); +//设置结果对齐方式 +void ADC_SetAlign(uint32_t enAlign); +//设置单通道ADC转换结果溢出保存策略 +void ADC_SetDiscard(uint32_t enDiscard); +//设置内置温度传感器使能控制 +void ADC_SetTs(uint32_t enTs); +//读取ADC参考电压1.5V时的温度传感器的测量温度 +void ADC_GetTsVref1V5(float *fAdcTsDegree); +//读取ADC参考电压2.5V时的温度传感器的测量温度 +void ADC_GetTsVref2V5(float *fAdcTsDegree); +//设置ADC转换结束自动停止 +void ADC_AutoStop(uint32_t enAutoStop); +//@} +#ifdef __cplusplus +} +#endif + +#endif /* __CW32F030_ADC_H */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_atim.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_atim.h new file mode 100644 index 0000000..3a455fd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_atim.h @@ -0,0 +1,356 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_ATIM_H +#define __CW32F030_ATIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" + +/****************************************************************************** + * type definitions ('typedef') + ******************************************************************************/ +typedef struct +{ + uint32_t CounterDirection; /*!< 计数方向 */ + + uint32_t CounterOPMode; /*!< 运行模式：单次或重复 */ + + uint32_t CounterAlignedMode; /*!< 计数对齐模式: 边沿或中央 */ + + FunctionalState BufferState; /*!< ARR缓存使能 */ + + uint32_t Prescaler; /*!< 预分频系数 */ + + uint32_t ClockSelect; /*!< 计数时钟选择 */ + + uint32_t ReloadValue; /*!< ARR赋值，取值范围0x0000~0xFFFF */ + + uint32_t RepetitionCounter; /*!< 重复周期计数值，RCR寄存器 */ + + FunctionalState UnderFlowMask; /*!< 下溢出屏蔽使能 */ + + FunctionalState OverFlowMask; /*!< 上溢出屏蔽使能 */ + +} ATIM_InitTypeDef; + +typedef struct +{ + uint32_t ICPolarity; /*!< 输入捕获极性：上升、下降、双沿 */ + + uint32_t ICFilter; /*!< 输入滤波配置 */ +} ATIM_ICInitTypeDef; + +typedef struct +{ + uint32_t OCPolarity; /*!< 端口极性选择：正向、反向 */ + + uint32_t OCMode; /*!< 比较模式配置 */ + + uint32_t OCInterruptSelect; /*!< 比较中断模式 */ + + FunctionalState OCDMAState; /*!< 比较匹配触发DMA使能状态 */ + + FunctionalState OCInterruptState; /*!< 比较匹配触发中断使能状态 */ + + FunctionalState BufferState; /*!< 比较缓存使能状态 */ +} ATIM_OCInitTypeDef; +/****************************************************************************** + * pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define ATIM_COUNTING_UP (0UL) +#define ATIM_COUNTING_DOWN (1UL << 27) +#define IS_ATIM_COUNTING_DIRECTION(DIR) (((DIR) == ATIM_COUNTING_UP) || \ + ((DIR) == ATIM_COUNTING_DOWN)) + +#define ATIM_OP_MODE_SINGLE (1UL << 14) +#define ATIM_OP_MODE_REPETITIVE (0UL) +#define IS_ATIM_OP_MODE(MODE) (((MODE) == ATIM_OP_MODE_SINGLE) || \ + ((MODE) == ATIM_OP_MODE_REPETITIVE)) + + +#define ATIM_COUNT_MODE_EDGE_ALIGN (2UL << 12) +#define ATIM_COUNT_MODE_CENTER_ALIGN (3UL << 12) +#define IS_ATIM_COUNT_MODE(MODE) (((MODE) == ATIM_COUNT_MODE_EDGE_ALIGN) || \ + ((MODE) == ATIM_COUNT_MODE_CENTER_ALIGN)) + +#define ATIM_CR_IT_UNDE (1UL << 29) +#define ATIM_CR_IT_OVE (1UL << 28) +#define ATIM_CR_IT_BIE (1UL << 20) +#define ATIM_CR_IT_TIE (1UL << 19) +#define ATIM_CR_IT_UIE (1UL << 10) + +#define ATIM_BUFFER_ENABLE (1UL << 7) +#define ATIM_BUFFER_DISABLE (0UL) + +#define ATIM_Prescaler_DIV1 (0UL) +#define ATIM_Prescaler_DIV2 (1UL << 4) +#define ATIM_Prescaler_DIV4 (2UL << 4) +#define ATIM_Prescaler_DIV8 (3UL << 4) +#define ATIM_Prescaler_DIV16 (4UL << 4) +#define ATIM_Prescaler_DIV32 (5UL << 4) +#define ATIM_Prescaler_DIV64 (6UL << 4) +#define ATIM_Prescaler_DIV256 (7UL << 4) +#define IS_ATIM_PRESCALER(PRESCALER) (((PRESCALER) == ATIM_Prescaler_DIV1) ||\ + ((PRESCALER) == ATIM_Prescaler_DIV2) ||\ + ((PRESCALER) == ATIM_Prescaler_DIV4) ||\ + ((PRESCALER) == ATIM_Prescaler_DIV8) ||\ + ((PRESCALER) == ATIM_Prescaler_DIV16) ||\ + ((PRESCALER) == ATIM_Prescaler_DIV64) ||\ + ((PRESCALER) == ATIM_Prescaler_DIV256)) + +#define ATIM_CLOCK_PCLK (0UL) +#define ATIM_CLOCK_ETR (1UL << 2) +#define IS_ATIM_CLOCK(CLK) (((CLK) == ATIM_CLOCK_PCLK) || \ + ((CLK) == ATIM_CLOCK_ETR)) + +#define ATIM_IT_UIF (1UL) +#define ATIM_IT_C1AF (1UL << 2) +#define ATIM_IT_C2AF (1UL << 3) +#define ATIM_IT_C3AF (1UL << 4) +#define ATIM_IT_C1BF (1UL << 5) +#define ATIM_IT_C2BF (1UL << 6) +#define ATIM_IT_C3BF (1UL << 7) +#define ATIM_IT_C1AE (1UL << 8) +#define ATIM_IT_C2AE (1UL << 9) +#define ATIM_IT_C3AE (1UL << 10) +#define ATIM_IT_C1BE (1UL << 11) +#define ATIM_IT_C2BE (1UL << 12) +#define ATIM_IT_C3BE (1UL << 13) +#define ATIM_IT_BIF (1UL << 14) +#define ATIM_IT_TIF (1UL << 15) +#define ATIM_IT_OVF (1UL << 16) +#define ATIM_IT_UNDF (1UL << 17) +#define ATIM_IT_C4AF (1UL << 18) + +#define ATIM_CH_A_IC (1UL << 4) +#define ATIM_CH_A_OC (0UL) + +#define ATIM_CH_B_IC (1UL << 5) +#define ATIM_CH_B_OC (0UL) + +#define ATIM_CHxA_BUFF (1UL << 6) +#define ATIM_CHxA_CIE (1UL << 8) +#define ATIM_CHxA_CDE (1UL << 10) +#define ATIM_CHxB_BUFF (1UL << 7) +#define ATIM_CHxB_CIE (1UL << 9) +#define ATIM_CHxB_CDE (1UL << 11) + +#define ATIM_CH4_BUFF (1UL) +#define ATIM_CH4_CIE (1UL << 1) +#define ATIM_CH4_CDE (1UL << 2) + +#define ATIM_ICPOLOARITY_DISABLE (0UL) +#define ATIM_ICPOLARITY_RISING (1UL) +#define ATIM_ICPOLARITY_FALLING (2UL) +#define ATIM_ICPOLARITY_BOTHEDGE (3UL) +#define IS_ATIM_IC_POLARITY(POLARITY) (((POLARITY) == ATIM_ICPOLOARITY_DISABLE) || \ + ((POLARITY) == ATIM_ICPOLARITY_RISING) || \ + ((POLARITY) == ATIM_ICPOLARITY_FALLING)|| \ + ((POLARITY) == ATIM_ICPOLARITY_BOTHEDGE)) + +#define ATIM_ICFILTER_NONE (0UL) +#define ATIM_ICFILTER_PCLK_N3 (4UL) +#define ATIM_ICFILTER_PCLKDIV4_N3 (5UL) +#define ATIM_ICFILTER_PCLKDIV16_N3 (6UL) +#define ATIM_ICFILTER_PCLKDIV64_N3 (7UL) +#define IS_ATIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 7UL) + +#define ATIM_OCPOLARITY_NONINVERT (0UL) +#define ATIM_OCPOLARITY_INVERT (1UL) +#define IS_ATIM_OC_POLARITY(POLARITY) (((POLARITY) == ATIM_OCPOLARITY_NONINVERT) || \ + ((POLARITY) == ATIM_OCPOLARITY_INVERT)) + +#define ATIM_OCMODE_FORCED_INACTIVE (0UL) +#define ATIM_OCMODE_FORCED_ACTIVE (1UL) +#define ATIM_OCMODE_INACTIVE (2UL) +#define ATIM_OCMODE_ACTIVE (3UL) +#define ATIM_OCMODE_TOGGLE (4UL) +#define ATIM_OCMODE_ONE_PLUSE (5UL) +#define ATIM_OCMODE_PWM1 (6UL) +#define ATIM_OCMODE_PWM2 (7UL) +#define IS_ATIM_OC_MODE(MODE) ((MODE) <= 7UL) + +#define ATIM_OC_IT_NONE (0UL) +#define ATIM_OC_IT_UP_COUNTER (1UL) +#define ATIM_OC_IT_DOWN_COUNTER (2UL) +#define ATIM_OC_IT_BOTH_COUNTER (3UL) +#define IS_ATIM_OC_IT(SELECT) ((SELECT) <= 3UL) + +#define ATIM_ETR_POLARITY_NONINVERT (0UL) +#define ATIM_ETR_POLARITY_INVERT (1UL << 31) +#define IS_ATIM_ETR_POLARITY(POLARITY) (((POLARITY) == ATIM_ETR_POLARITY_INVERT) || \ + ((POLARITY) == ATIM_ETR_POLARITY_NONINVERT)) + +#define ATIM_ETR_FILTER_NONE (0UL) +#define ATIM_ETR_FILTER_PCLK_N3 (4UL << 28) +#define ATIM_ETR_FILTER_PCLKDIV4_N3 (5UL << 28) +#define ATIM_ETR_FILTER_PCLKDIV16_N3 (6UL << 28) +#define ATIM_ETR_FILTER_PCLKDIV64_N3 (7UL << 28) +#define IS_ATIM_ETR_FILTER(FILTER) (((FILTER) == ATIM_ETR_FILTER_NONE) ||\ + ((FILTER) == ATIM_ETR_FILTER_PCLK_N3) || \ + ((FILTER) == ATIM_ETR_FILTER_PCLKDIV4_N3) || \ + ((FILTER) == ATIM_ETR_FILTER_PCLKDIV16_N3) || \ + ((FILTER) == ATIM_ETR_FILTER_PCLKDIV64_N3)) + +#define ATIM_BRAKE_POLARITY_NONINVERT (0UL) +#define ATIM_BRAKE_POLARITY_INVERT (1UL << 27) +#define IS_ATIM_BRAKE_POLARITY(POLARITY) (((POLARITY) == ATIM_BRAKE_POLARITY_INVERT) || \ + ((POLARITY) == ATIM_BRAKE_POLARITY_NONINVERT)) + +#define ATIM_BRAKE_FILTER_NONE (0UL) +#define ATIM_BRAKE_FILTER_PCLK_N3 (4UL << 24) +#define ATIM_BRAKE_FILTER_PCLKDIV4_N3 (5UL << 24) +#define ATIM_BRAKE_FILTER_PCLKDIV16_N3 (6UL << 24) +#define ATIM_BRAKE_FILTER_PCLKDIV64_N3 (7UL << 24) +#define IS_ATIM_BRAKE_FILTER(FILTER) (((FILTER) == ATIM_BRAKE_FILTER_NONE) ||\ + ((FILTER) == ATIM_BRAKE_FILTER_PCLK_N3) || \ + ((FILTER) == ATIM_BRAKE_FILTER_PCLKDIV4_N3) || \ + ((FILTER) == ATIM_BRAKE_FILTER_PCLKDIV16_N3) || \ + ((FILTER) == ATIM_BRAKE_FILTER_PCLKDIV64_N3)) + +#define ATIM_ADC_TRIGGER_GLOBAL (1UL << 7) +#define ATIM_ADC_TRIGGER_CH3B (1UL << 6) +#define ATIM_ADC_TRIGGER_CH2B (1UL << 5) +#define ATIM_ADC_TRIGGER_CH1B (1UL << 4) +#define ATIM_ADC_TRIGGER_CH3A (1UL << 3) +#define ATIM_ADC_TRIGGER_CH2A (1UL << 2) +#define ATIM_ADC_TRIGGER_CH1A (1UL << 1) +#define ATIM_ADC_TRIGGER_UPDATA_EVENT (1UL) +#define IS_ATIM_ADC_TRIGGER(SOURCE) ((SOURCE) <= 0x000000FF) + +#define OCREFA_TYPE_DOUBLE (0UL) +#define OCREFA_TYPE_SINGLE (1UL << 3) +#define IS_ATIM_OCREFA_TYPE(TYPE) ((TYPE) == OCREFA_TYPE_DOUBLE || (TYPE) == OCREFA_TYPE_SINGLE) +#define OUTPUT_TYPE_ALONE (0UL) +#define OUTPUT_TYPE_COMP (1UL << 1) +#define IS_ATIM_OUTPUT_TYPE(TYPE) ((TYPE) == OUTPUT_TYPE_ALONE || (TYPE) == OUTPUT_TYPE_COMP) +#define IS_ATIM_DEADTIME(VAL) ((VAL)<= 0xFF) + +#define ATIM_MASTER_OUTPUT_UG 0x00 // 软件更新UG +#define ATIM_MASTER_OUTPUT_CTEN 0x01 // 定时器使能CTEN +#define ATIM_MASTER_OUTPUT_UEV 0x02 // 定时器时间更新UEV +#define ATIM_MASTER_OUTPUT_CMPSO 0x03 // 比较匹配选择输出CMPSO +#define ATIM_MASTER_OUTPUT_OCREF1A 0x04 // 定时器比较输出OCREF1A +#define ATIM_MASTER_OUTPUT_OCREF2A 0x05 // 定时器比较输出OCREF2A +#define ATIM_MASTER_OUTPUT_OCREF3A 0x06 // 定时器比较输出OCREF3A +#define ATIM_MASTER_OUTPUT_OCREF1B 0x07 // 定时器比较输出OCREF1B +#define IS_ATIM_MASTER_OUTPUT(OUTPUT) ((OUTPUT) <= 0x07) + +#define ATIM_SLAVER_TYPE_PCLK 0x00 // 内部时钟 +#define ATIM_SLAVER_TYPE_RESET 0x01 // 复位功能 +#define ATIM_SLAVER_TYPE_TRIGGER 0x02 // 触发模式 +#define ATIM_SLAVER_TYPE_EXT 0x03 // 外部时钟 +#define ATIM_SLAVER_TYPE_ENCODE1 0x04 // 正交编码计数模式1 +#define ATIM_SLAVER_TYPE_ENCODE2 0x05 // 正交编码计数模式2 +#define ATIM_SLAVER_TYPE_ENCODE3 0x06 // 正交编码计数模式3 +#define ATIM_SLAVER_TYPE_GATE 0x07 // 门控功能 +#define IS_ATIM_SLAVER_TYPE(TYPE) ((TYPE) <= 0x07) + +#define ATIM_TRIGGER_SOURCE_ETFP 0x00 // 端口ETR的滤波相位选择后的信号ETFP +#define ATIM_TRIGGER_SOURCE_ITR 0x01 // 内部互联信号ITR +#define ATIM_TRIGGER_SOURCE_CH1A 0x05 // 端口CH1A的边沿信号 +#define ATIM_TRIGGER_SOURCE_IAFP 0x06 // 端口CH1A的滤波相位选择后的信号IAFP +#define ATIM_TRIGGER_SOURCE_IBFP 0x07 // 端口CH1B的滤波相位选择后的信号IBFP +#define IS_ATIM_TRIGGER_SOURCE(SRC) ((SRC) == ATIM_TRIGGER_SOURCE_ETFP || \ + (SRC) == ATIM_TRIGGER_SOURCE_ITR || \ + (SRC) == ATIM_TRIGGER_SOURCE_CH1A || \ + (SRC) == ATIM_TRIGGER_SOURCE_IAFP || \ + (SRC) == ATIM_TRIGGER_SOURCE_IBFP) + +#define ATIM_UPDATE_EVENT_NORMAL 0x01 // 上溢出/下溢出 +#define ATIM_UPDATE_EVENT_EXTENSION 0x00 // 上溢出/下溢出/软件更新/从模式复位 +#define IS_ATIM_UPDATE_EVENT(EVENT) ((EVENT) == ATIM_UPDATE_EVENT_NORMAL || \ + (EVENT) == ATIM_UPDATE_EVENT_EXTENSION) +/****************************************************************************** +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ + +/****************************************************************************** +* Global function prototypes +******************************************************************************/ +void ATIM_DeInit(void); + +void ATIM_Init(ATIM_InitTypeDef *ATIM_InitStruct); +void ATIM_Cmd(FunctionalState NewState); + +void ATIM_ITConfig(uint32_t ATIM_IT, FunctionalState NewState); +ITStatus ATIM_GetITStatus(uint32_t ATIM_IT); +void ATIM_ClearITPendingBit(uint32_t ATIM_IT); +void ATIM_SetReloadValue(uint32_t Value); + +void ATIM_CH1Config(uint32_t Function, FunctionalState NewState); +void ATIM_CH2Config(uint32_t Function, FunctionalState NewState); +void ATIM_CH3Config(uint32_t Function, FunctionalState NewState); +void ATIM_CH4Config(uint32_t Function, FunctionalState NewState); + +void ATIM_IC1AInit(ATIM_ICInitTypeDef *TIM_ICInitStruct); +void ATIM_IC1BInit(ATIM_ICInitTypeDef *TIM_ICInitStruct); +void ATIM_IC2AInit(ATIM_ICInitTypeDef *TIM_ICInitStruct); +void ATIM_IC2BInit(ATIM_ICInitTypeDef *TIM_ICInitStruct); +void ATIM_IC3AInit(ATIM_ICInitTypeDef *TIM_ICInitStruct); +void ATIM_IC3BInit(ATIM_ICInitTypeDef *TIM_ICInitStruct); + +void ATIM_OC1AInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct); +void ATIM_OC2AInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct); +void ATIM_OC3AInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct); +void ATIM_OC1BInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct); +void ATIM_OC2BInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct); +void ATIM_OC3BInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct); + +void ATIM_OC4Init(FunctionalState NewState, uint32_t ITSelect, FunctionalState DMAState, + FunctionalState ITState, FunctionalState BufferState); +void ATIM_PWMOutputConfig(uint32_t OCREFAType, uint32_t OutputType, int16_t Deadtime); +void ATIM_CtrlPWMOutputs(FunctionalState NewState); +void ATIM_ETRConfig(uint32_t ATIM_ETRPolarity, uint32_t ATIM_ETRFilter); +void ATIM_BrakeConfig(uint32_t ATIM_BrakePolarity, uint32_t ATIM_BrakeFilter); + +void ATIM_ADCTriggerConfig(uint32_t ATIM_ADCTriggerSource, FunctionalState NewState); + +uint16_t ATIM_GetCapture1A(void); +uint16_t ATIM_GetCapture2A(void); +uint16_t ATIM_GetCapture3A(void); +uint16_t ATIM_GetCapture1B(void); +uint16_t ATIM_GetCapture2B(void); +uint16_t ATIM_GetCapture3B(void); +uint16_t ATIM_GetCapture4(void); + +void ATIM_SetCompare1A(uint16_t Compare); +void ATIM_SetCompare2A(uint16_t Compare); +void ATIM_SetCompare3A(uint16_t Compare); +void ATIM_SetCompare1B(uint16_t Compare); +void ATIM_SetCompare2B(uint16_t Compare); +void ATIM_SetCompare3B(uint16_t Compare); +void ATIM_SetCompare4(uint16_t Compare); + +void ATIM_MasterModeConfig(uint8_t ATIM_MasterOutput); +void ATIM_SlaverModeConfig(uint8_t ATIM_SlaverType); +void ATIM_TriggerSelect(uint8_t ATIM_TriggerSource); +void ATIM_UpdateEventSelect(uint8_t ATIM_UpdateEvent); + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32F030_ATIM_H */ +/** + * @} + */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_awt.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_awt.h new file mode 100644 index 0000000..8760a49 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_awt.h @@ -0,0 +1,120 @@ +/** + * @file cw32f030_awt.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-18 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_AWT_H +#define __CW32F030_AWT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" + +typedef struct +{ + uint32_t AWT_ClkSource; /* 时钟源选择，设置值0 - 4 */ + uint32_t AWT_Prescaler; /* 预分配系数，设置值1 - 15，对应取值范围2的n次幂，n=1,2…15 */ + uint32_t AWT_Period; /* 计数重载周期，低16位有效，取值范围0x0000 到 0xFFFF. */ + uint32_t AWT_Mode; /* AWT工作模式，固定为11 */ +} AWT_TimeCntInitTypeDef; + +#define AWT_CLKSOURCE_HSIOSC ( uint32_t )(0x00UL << 8) +#define AWT_CLKSOURCE_LSI ( uint32_t )(0x01UL << 8) +#define AWT_CLKSOURCE_HSE ( uint32_t )(0x02UL << 8) +#define AWT_CLKSOURCE_LSE ( uint32_t )(0x03UL << 8) +#define AWT_CLKSOURCE_ETR ( uint32_t )(0x04UL << 8) +#define IS_AWT_CLKSOURCE(SOURCE) (((SOURCE) == AWT_CLKSOURCE_HSIOSC) || \ + ((SOURCE) == AWT_CLKSOURCE_LSI) || \ + ((SOURCE) == AWT_CLKSOURCE_HSE) || \ + ((SOURCE) == AWT_CLKSOURCE_LSE) || \ + ((SOURCE) == AWT_CLKSOURCE_ETR)) + +#define AWT_PRS_DIV2 ( uint32_t )(0x01UL << 4) +#define AWT_PRS_DIV4 ( uint32_t )(0x02UL << 4) +#define AWT_PRS_DIV8 ( uint32_t )(0x03UL << 4) +#define AWT_PRS_DIV16 ( uint32_t )(0x04UL << 4) +#define AWT_PRS_DIV32 ( uint32_t )(0x05UL << 4) +#define AWT_PRS_DIV64 ( uint32_t )(0x06UL << 4) +#define AWT_PRS_DIV128 ( uint32_t )(0x07UL << 4) +#define AWT_PRS_DIV256 ( uint32_t )(0x08UL << 4) +#define AWT_PRS_DIV512 ( uint32_t )(0x09UL << 4) +#define AWT_PRS_DIV1024 ( uint32_t )(0x0AUL << 4) +#define AWT_PRS_DIV2048 ( uint32_t )(0x0BUL << 4) +#define AWT_PRS_DIV4096 ( uint32_t )(0x0CUL << 4) +#define AWT_PRS_DIV8192 ( uint32_t )(0x0DUL << 4) +#define AWT_PRS_DIV16384 ( uint32_t )(0x0EUL << 4) +#define AWT_PRS_DIV32768 ( uint32_t )(0x0FUL << 4) +#define IS_AWT_PRS_DIV(DIV) (((DIV) == AWT_PRS_DIV2) || \ + ((DIV) == AWT_PRS_DIV4) || \ + ((DIV) == AWT_PRS_DIV8) || \ + ((DIV) == AWT_PRS_DIV16) || \ + ((DIV) == AWT_PRS_DIV32) || \ + ((DIV) == AWT_PRS_DIV64) || \ + ((DIV) == AWT_PRS_DIV128) || \ + ((DIV) == AWT_PRS_DIV256) || \ + ((DIV) == AWT_PRS_DIV512) || \ + ((DIV) == AWT_PRS_DIV1024) || \ + ((DIV) == AWT_PRS_DIV2048) || \ + ((DIV) == AWT_PRS_DIV4096) || \ + ((DIV) == AWT_PRS_DIV8192) || \ + ((DIV) == AWT_PRS_DIV16384) || \ + ((DIV) == AWT_PRS_DIV32768)) + +#define AWT_MODE_TIMECNT ( uint32_t )(0x03UL << 1) +#define IS_AWT_MODE(MODE) ((MODE) == AWT_MODE_TIMECNT) +#define AWT_CR_EN bv0 + +#define IS_AWT_ARR(ARR) ((ARR) <= 65535) + +#define AWT_IT_UD ((uint32_t)0x08) +#define IS_AWT_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF7) == 0x0000) && ((IT) != 0x0000)) +#define IS_AWT_GET_IT(IT) ((IT) == AWT_IT_UD) + + +void AWT_DeInit(void); +void AWT_TimeCntInit(AWT_TimeCntInitTypeDef *AWT_TimeCntInitStruct); +void AWT_TimeCntStructInit(AWT_TimeCntInitTypeDef *AWT_TimeCntInitStruct); +void AWT_Cmd(FunctionalState NewState); +void AWT_ITConfig(uint32_t AWT_IT, FunctionalState NewState); +ITStatus AWT_GetITStatus(uint32_t AWT_IT); +void AWT_ClearITPendingBit(uint32_t AWT_IT); +void AWT_ClkSourceConfig(uint32_t AWT_ClkSource); +void AWT_PrescalerConfig(uint32_t AWT_Prescaler); +uint16_t AWT_GetCounter(void); +uint16_t AWT_GetAutoreload(void); +uint32_t AWT_GetClkSource(void); +uint32_t AWT_GetPrescaler(void); + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_btim.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_btim.h new file mode 100644 index 0000000..a87f3b8 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_btim.h @@ -0,0 +1,270 @@ +/** + * @file cw32f030_btim.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-27 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_BTIM_H +#define __CW32F030_BTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" + + +/** @addtogroup BTIM + * @{ + */ + +/** @defgroup BTIM_Exported_Types + * @{ + */ + +/** + * @brief BTIM Time Base Init structure definition + * @note This structure is used with all BTIMx except for BTIM6 and BTIM7. + */ + +typedef struct +{ + uint16_t BTIM_Prescaler; /* 预分配系数，取值范围2的n次幂，n=0,1,2…15 */ + + uint16_t BTIM_Mode; /* 工作模式，00：定时器模式 + 01：计数器模式 + 10：触发计数模式 + 11：门控计数模式 */ + + uint16_t BTIM_Period; /* 计数重载周期，取值范围0x0000 到 0xFFFF. */ + + uint16_t BTIM_OPMode; /* 单次和连续模式控制 */ + +} BTIM_TimeBaseInitTypeDef; + +/** @defgroup BTIM_Exported_constants + * @{ + */ + +#define IS_BTIM_ALL_PERIPH(PERIPH) (((PERIPH) == CW_BTIM1) || \ + ((PERIPH) == CW_BTIM2) || \ + ((PERIPH) == CW_BTIM3)) + +/** + * @} + */ + +/** @defgroup BTIM_One_Pulse_Mode + * @{ + */ + +#define BTIM_OPMode_Single ((uint16_t)0x0020) +#define BTIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_BTIM_OPM_MODE(MODE) (((MODE) == BTIM_OPMode_Single) || \ + ((MODE) == BTIM_OPMode_Repetitive)) +/** + * @} + */ + + + +/** @defgroup BTIM_Prescaler_Division + * @{ + */ + +#define BTIM_PRS_DIV1 ((uint16_t)0x0000) +#define BTIM_PRS_DIV2 ((uint16_t)0x0080) +#define BTIM_PRS_DIV4 ((uint16_t)0x0100) +#define BTIM_PRS_DIV8 ((uint16_t)0x0180) +#define BTIM_PRS_DIV16 ((uint16_t)0x0200) +#define BTIM_PRS_DIV32 ((uint16_t)0x0280) +#define BTIM_PRS_DIV64 ((uint16_t)0x0300) +#define BTIM_PRS_DIV128 ((uint16_t)0x0380) +#define BTIM_PRS_DIV256 ((uint16_t)0x0400) +#define BTIM_PRS_DIV512 ((uint16_t)0x0480) +#define BTIM_PRS_DIV1024 ((uint16_t)0x0500) +#define BTIM_PRS_DIV2048 ((uint16_t)0x0580) +#define BTIM_PRS_DIV4096 ((uint16_t)0x0600) +#define BTIM_PRS_DIV8192 ((uint16_t)0x0680) +#define BTIM_PRS_DIV16384 ((uint16_t)0x0700) +#define BTIM_PRS_DIV32768 ((uint16_t)0x0780) +#define IS_BTIM_PRS_DIV(DIV) (((DIV) == BTIM_PRS_DIV1) || \ + ((DIV) == BTIM_PRS_DIV2) || \ + ((DIV) == BTIM_PRS_DIV4) || \ + ((DIV) == BTIM_PRS_DIV8) || \ + ((DIV) == BTIM_PRS_DIV16) || \ + ((DIV) == BTIM_PRS_DIV32) || \ + ((DIV) == BTIM_PRS_DIV64) || \ + ((DIV) == BTIM_PRS_DIV128) || \ + ((DIV) == BTIM_PRS_DIV256) || \ + ((DIV) == BTIM_PRS_DIV512) || \ + ((DIV) == BTIM_PRS_DIV1024) || \ + ((DIV) == BTIM_PRS_DIV2048) || \ + ((DIV) == BTIM_PRS_DIV4096) || \ + ((DIV) == BTIM_PRS_DIV8192) || \ + ((DIV) == BTIM_PRS_DIV16384) || \ + ((DIV) == BTIM_PRS_DIV32768)) +/** + * @} + */ + +/** @defgroup BTIM_Mode + * @{ + */ + +#define BTIM_Mode_TIMER ((uint16_t)0x0000) +#define BTIM_Mode_COUNTER ((uint16_t)0x0002) +#define BTIM_Mode_TRIGGER ((uint16_t)0x00004) +#define BTIM_Mode_GATE ((uint16_t)0x0006) +#define IS_BTIM_MODE(MODE) (((MODE) == BTIM_Mode_TIMER) || \ + ((MODE) == BTIM_Mode_COUNTER) || \ + ((MODE) == BTIM_Mode_TRIGGER) || \ + ((MODE) == BTIM_Mode_GATE)) + + + +/** @defgroup BTIM_interrupt_sources + * @{ + */ + +#define BTIM_IT_OV ((uint16_t)0x0001) +#define BTIM_IT_TI ((uint16_t)0x0002) +#define BTIM_IT_TOP ((uint16_t)0x0004) +#define IS_BTIM_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x0000) && ((IT) != 0x0000)) + +#define IS_BTIM_GET_IT(IT) (((IT) == BTIM_IT_OV) || \ + ((IT) == BTIM_IT_TI) || \ + ((IT) == BTIM_IT_TOP)) +/** + * @} + */ + +/** @defgroup BTIM_DMA_sources + * @{ + */ + +#define BTIM_DMA_OV ((uint16_t)0x0001) +#define BTIM_DMA_TRS ((uint16_t)0x0002) +#define IS_BTIM_DMA_SOURCE(SOURCE) (((SOURCE) == BTIM_DMA_OV) ||\ + ((SOURCE) == BTIM_DMA_TRS)) + +/** + * @} + */ + + +/** @defgroup BTIM_Internal_Trigger_Selection + * @{ + */ + +#define BTIM_TS_ITR ((uint16_t)0x0008) +#define BTIM_TS_ETR ((uint16_t)0x0000) +#define IS_BTIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == BTIM_TS_ITR) || \ + ((SELECTION) == BTIM_TS_ETR)) + +/** + * @} + */ + +/** @defgroup BTIM_ETR_Polarity + * @{ + */ + +#define BTIM_ETR_Polarity_Positive ((uint16_t)0x0000) +#define BTIM_ETR_Polarity_Negative ((uint16_t)0x0010) +#define IS_BTIM_ETR_POLARITY(MODE) (((MODE) == BTIM_ETR_Polarity_Positive) || \ + ((MODE) == BTIM_ETR_Polarity_Negative)) +/** + * @} + */ + +/** @defgroup BTIM_Prescaler_Reload_Mode + * @{ + */ + +#define BTIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define BTIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_BTIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == BTIM_PSCReloadMode_Update) || \ + ((RELOAD) == BTIM_PSCReloadMode_Immediate)) +/** + * @} + */ + + +/** @defgroup BTIM_External_Trigger_Filter + * @{ + */ +#define BTIM_EXT_FILTER_NONE 0x0000 +#define BTIM_EXT_FILTER_PCLK_N2 0x0010 +#define BTIM_EXT_FILTER_PCLK_N4 0x0020 +#define BTIM_EXT_FILTER_PCLK_N6 0x0030 +#define BTIM_EXT_FILTER_PCLKDIV4_N4 0x0040 +#define BTIM_EXT_FILTER_PCLKDIV4_N6 0x0050 +#define BTIM_EXT_FILTER_PCLKDIV16_N4 0x0060 +#define BTIM_EXT_FILTER_PCLKDIV16_N6 0x0070 +#define IS_BTIM_EXT_FILTER(EXTFILTER) (((EXTFILTER) == BTIM_EXT_FILTER_NONE) || \ + ((EXTFILTER) == BTIM_EXT_FILTER_PCLK_N2) || \ + ((EXTFILTER) == BTIM_EXT_FILTER_PCLK_N4) || \ + ((EXTFILTER) == BTIM_EXT_FILTER_PCLK_N6) || \ + ((EXTFILTER) == BTIM_EXT_FILTER_PCLKDIV4_N4) || \ + ((EXTFILTER) == BTIM_EXT_FILTER_PCLKDIV4_N6) || \ + ((EXTFILTER) == BTIM_EXT_FILTER_PCLKDIV16_N4) || \ + ((EXTFILTER) == BTIM_EXT_FILTER_PCLKDIV16_N6)) +/** + * @} + */ + + +/** @defgroup BTIM_Exported_Functions + * @{ + */ + +void BTIM_DeInit(BTIM_TypeDef *BTIMx); +void BTIM_TimeBaseInit(BTIM_TypeDef *BTIMx, BTIM_TimeBaseInitTypeDef *BTIM_TimeBaseInitStruct); +void BTIM_TimeBaseStructInit(BTIM_TimeBaseInitTypeDef *BTIM_TimeBaseInitStruct); +void BTIM_Cmd(BTIM_TypeDef *BTIMx, FunctionalState NewState); +void BTIM_ITConfig(BTIM_TypeDef *BTIMx, uint16_t BTIM_IT, FunctionalState NewState); +void BTIM_DMACmd(BTIM_TypeDef *BTIMx, uint16_t BTIM_DMASource, FunctionalState NewState); +void BTIM_PrescalerConfig(BTIM_TypeDef *BTIMx, uint16_t Prescaler, uint16_t BTIM_PSCReloadMode); +void BTIM_ModeConfig(BTIM_TypeDef *BTIMx, uint16_t BTIM_Mode); +void BTIM_SelectInputTrigger(BTIM_TypeDef *BTIMx, uint16_t BTIM_InputTriggerSource); +void BTIM_SelectOnePulseMode(BTIM_TypeDef *BTIMx, uint16_t BTIM_OPMode); +void BTIM_OutputToggleCmd(BTIM_TypeDef *BTIMx, FunctionalState NewState); +void BTIM_ETRConfig(BTIM_TypeDef *BTIMx, uint16_t BTIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void BTIM_SetCounter(BTIM_TypeDef *BTIMx, uint16_t Counter); +void BTIM_SetAutoreload(BTIM_TypeDef *BTIMx, uint16_t Autoreload); +uint16_t BTIM_GetCounter(BTIM_TypeDef *BTIMx); +uint16_t BTIM_GetAutoreload(BTIM_TypeDef *BTIMx); +uint16_t BTIM_GetPrescaler(BTIM_TypeDef *BTIMx); +void BTIM_ClearFlag(BTIM_TypeDef *BTIMx, uint16_t BTIM_FLAG); +ITStatus BTIM_GetITStatus(BTIM_TypeDef *BTIMx, uint16_t BTIM_IT); +void BTIM_ClearITPendingBit(BTIM_TypeDef *BTIMx, uint16_t BTIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_crc.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_crc.h new file mode 100644 index 0000000..a565ba6 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_crc.h @@ -0,0 +1,91 @@ +/** + * @file cw32f030_crc.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-13 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F03x_CRC_H__ +#define __CW32F03x_CRC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#include "base_types.h" +#include "cw32f030.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +//============================================================ + + +uint16_t CRC16_Calc_8bit(uint8_t CrcMode, uint8_t *pByteBuf, uint16_t ByteCnt); +uint16_t CRC16_Calc_16bit(uint8_t CrcMode, uint16_t *pHWBuf, uint16_t HalfWordCnt); +uint16_t CRC16_Calc_32bit(uint8_t CrcMode, uint32_t *pWBuf, uint16_t WordCnt); + +uint32_t CRC32_Calc_8bit(uint8_t CrcMode, uint8_t *pByteBuf, uint16_t ByteCnt); +uint32_t CRC32_Calc_16bit(uint8_t CrcMode, uint16_t *pHWBuf, uint16_t HalfWordCnt); +uint32_t CRC32_Calc_32bit(uint8_t CrcMode, uint32_t *pWBuf, uint16_t WordCnt); + + +//============================================================ + +#define CRC16_IBM 0x00UL +#define CRC16_MAXIM 0x01UL +#define CRC16_USB 0x02UL +#define CRC16_MODBUS 0x03UL +#define CRC16_CCITT 0x04UL +#define CRC16_CCITTFALSE 0x05UL +#define CRC16_X25 0x06UL +#define CRC16_XMODEM 0x07UL +#define CRC32_DEFAULT 0x08UL +#define CRC32_MPEG2 0x09UL + + +#define IS_CRC_CRC16_MODE(MODE) (((MODE) == CRC16_IBM) || \ + ((MODE) == CRC16_MAXIM) || \ + ((MODE) == CRC16_USB) || \ + ((MODE) == CRC16_MODBUS) || \ + ((MODE) == CRC16_CCITT) || \ + ((MODE) == CRC16_CCITTFALSE) || \ + ((MODE) == CRC16_X25) || \ + ((MODE) == CRC16_XMODEM)) +#define IS_CRC_CRC32_MODE(MODE) (((MODE) == CRC32_DEFAULT) || \ + ((MODE) == CRC32_MPEG2)) + +//============================================================ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_debug.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_debug.h new file mode 100644 index 0000000..c9bd05d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_debug.h @@ -0,0 +1,71 @@ +/** + * @file cw32f030_debug.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-13 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F03x_DEBUG_H__ +#define __CW32F03x_DEBUG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#include "base_types.h" +#include "cw32f030.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +//============================================================ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); + + +#define DBGMCU_ATIM_STOP ((uint32_t)0x00000001) +#define DBGMCU_GTIM1_STOP ((uint32_t)0x00000002) +#define DBGMCU_GTIM2_STOP ((uint32_t)0x00000004) +#define DBGMCU_GTIM3_STOP ((uint32_t)0x00000008) +#define DBGMCU_GTIM4_STOP ((uint32_t)0x00000010) +#define DBGMCU_BTIM123_STOP ((uint32_t)0x00000020) +#define DBGMCU_AWT_STOP ((uint32_t)0x00000040) +#define DBGMCU_RTC_STOP ((uint32_t)0x00000100) +#define DBGMCU_IWDT_STOP ((uint32_t)0x00000200) +#define DBGMCU_WWDT_STOP ((uint32_t)0x00000400) +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFF880) == 0x00) && ((PERIPH) != 0x00)) + + +//============================================================ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_digitalsign.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_digitalsign.h new file mode 100644 index 0000000..75764f5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_digitalsign.h @@ -0,0 +1,79 @@ +/** + * @file cw32f030_digitalsign.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-14 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F03x_DIGITALSIGN_H__ +#define __CW32F03x_DIGITALSIGN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "base_types.h" +#include "cw32f030.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +//============================================================ + +#define DIGITALSIGN_BASE 0x00012610UL + +#define CHIP_TYPE_BASE 0x00012610UL +#define PIN_COUNT_BASE 0x00012626UL +#define FLASH_SIZE_BASE 0x00012628UL +#define RAM_SIZE_BASE 0x0001262CUL + +#define CHIP_UID_BASE 0x00012660UL + +#define CHIP_TYPE_LENGTH 22 +#define CHIP_UID_LENGTH 10 +//============================================================ + +//获取芯片型号// +void DIGITALSIGN_GetChipType(uint8_t *pChipType); +//获取管脚数量// +uint16_t DIGITALSIGN_GetPinCount(void); +//获取FLASH容量// +uint32_t DIGITALSIGN_GetFlashSize(void); +//获取RAM容量// +uint32_t DIGITALSIGN_GetRamSize(void); +//获取芯片UID// +void DIGITALSIGN_GetChipUid(uint8_t *pChipUid); + +//============================================================ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_dma.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_dma.h new file mode 100644 index 0000000..0972c52 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_dma.h @@ -0,0 +1,257 @@ +/** + * @file cw32f030_dma.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-17 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F03x_DMA_H__ +#define __CW32F03x_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +//============================================================ +typedef struct +{ + uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of */ + uint32_t DMA_TransferWidth; ///transfer data width + uint32_t DMA_SrcInc; /*!< Specifies whether the SRC address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + uint32_t DMA_DstInc; /*!< Specifies whether the DST address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + uint32_t TrigMode ; + + uint32_t HardTrigSource ; + + uint32_t DMA_TransferCnt; ///< Transfer counter + + uint32_t DMA_SrcAddress; ///< Source address> + + uint32_t DMA_DstAddress; ///< Dest address> + +} DMA_InitTypeDef; + + +#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == CW_DMACHANNEL1) || \ + ((PERIPH) == CW_DMACHANNEL2) || \ + ((PERIPH) == CW_DMACHANNEL3) || \ + ((PERIPH) == CW_DMACHANNEL4) || \ + ((PERIPH) == CW_DMACHANNEL5)) + +#define DMA_MODE_BULK 0x00UL +#define DMA_MODE_BLOCK 0x08UL +#define IS_DMA_MODE(MODE) (((MODE) == DMA_MODE_BULK) || \ + ((MODE) == DMA_MODE_BLOCK)) + +#define DMA_SrcAddress_Fix 0x00UL +#define DMA_SrcAddress_Increase 0x10UL +#define IS_DMA_SRCADDRESS_INC(INSTRANCE) (((INSTRANCE) == DMA_SrcAddress_Increase) || \ + ((INSTRANCE) == DMA_SrcAddress_Fix)) + +#define DMA_DstAddress_Fix 0x00UL +#define DMA_DstAddress_Increase 0x20UL +#define IS_DMA_DSTADDRESS_INC(INSTRANCE) (((INSTRANCE) == DMA_DstAddress_Increase) || \ + ((INSTRANCE) == DMA_DstAddress_Fix)) + +#define DMA_TRANSFER_WIDTH_8BIT 0x00UL +#define DMA_TRANSFER_WIDTH_16BIT 0x40UL +#define DMA_TRANSFER_WIDTH_32BIT 0x80UL +#define IS_DMA_TRANSFER_WIDTH(INSTRANCE) (((INSTRANCE) == DMA_TRANSFER_WIDTH_8BIT) || \ + ((INSTRANCE) == DMA_TRANSFER_WIDTH_16BIT) || \ + ((INSTRANCE) == DMA_TRANSFER_WIDTH_32BIT)) + +#define IS_DMA_TRANSFERCNT(CNT) (((CNT)>= 1) && ((CNT)<= 65535)) + +#define DMA_SWTrig 0x00UL +#define DMA_HardTrig 0x01UL +#define IS_DMA_TRIG(TRIG) (((TRIG) == DMA_SWTrig) || \ + ((TRIG) == DMA_HardTrig)) + +#define DMA_HardTrig_UART1_RXBufferNE (uint32_t)(0x00UL << 2) +#define DMA_HardTrig_UART1_TXBufferE (uint32_t)(0x01UL << 2) +#define DMA_HardTrig_UART2_RXBufferNE (uint32_t)(0x02UL << 2) +#define DMA_HardTrig_UART2_TXBufferE (uint32_t)(0x03UL << 2) +#define DMA_HardTrig_UART3_RXBufferNE (uint32_t)(0x04UL << 2) +#define DMA_HardTrig_UART3_TXBufferE (uint32_t)(0x05UL << 2) + +#define DMA_HardTrig_SPI1_RXBufferNE (uint32_t)(0x06UL << 2) +#define DMA_HardTrig_SPI1_TXBufferE (uint32_t)(0x07UL << 2) +#define DMA_HardTrig_SPI2_RXBufferNE (uint32_t)(0x08UL << 2) +#define DMA_HardTrig_SPI2_TXBufferE (uint32_t)(0x09UL << 2) + +#define DMA_HardTrig_ADC_TRANSCOMPLETE (uint32_t)(0x0AUL << 2) + +#define DMA_HardTrig_BTIM1_OVERINT (uint32_t)(0x0BUL << 2) +#define DMA_HardTrig_BTIM1_TRIGINT (uint32_t)(0x0CUL << 2) +#define DMA_HardTrig_BTIM2_OVERINT (uint32_t)(0x0DUL << 2) +#define DMA_HardTrig_BTIM2_TRIGINT (uint32_t)(0x0EUL << 2) +#define DMA_HardTrig_BTIM3_OVERINT (uint32_t)(0x0FUL << 2) +#define DMA_HardTrig_BTIM3_TRIGINT (uint32_t)(0x10UL << 2) + +#define DMA_HardTrig_ATIM_CH1A2A3A4 (uint32_t)(0x11UL << 2) +#define DMA_HardTrig_ATIM_CH1B2B3B (uint32_t)(0x12UL << 2) + +#define DMA_HardTrig_GTIM1_OVERINT (uint32_t)(0x13UL << 2) +#define DMA_HardTrig_GTIM1_TRIGINT (uint32_t)(0x14UL << 2) +#define DMA_HardTrig_GTIM1_CH1COMINT (uint32_t)(0x15UL << 2) +#define DMA_HardTrig_GTIM1_CH2COMINT (uint32_t)(0x16UL << 2) +#define DMA_HardTrig_GTIM1_CH3COMINT (uint32_t)(0x17UL << 2) +#define DMA_HardTrig_GTIM1_CH4COMINT (uint32_t)(0x18UL << 2) + +#define DMA_HardTrig_GTIM2_OVERINT (uint32_t)(0x19UL << 2) +#define DMA_HardTrig_GTIM2_TRIGINT (uint32_t)(0x1AUL << 2) +#define DMA_HardTrig_GTIM2_CH1COMINT (uint32_t)(0x1BUL << 2) +#define DMA_HardTrig_GTIM2_CH2COMINT (uint32_t)(0x1CUL << 2) +#define DMA_HardTrig_GTIM2_CH3COMINT (uint32_t)(0x1DUL << 2) +#define DMA_HardTrig_GTIM2_CH4COMINT (uint32_t)(0x1EUL << 2) + +#define DMA_HardTrig_GTIM3_OVERINT (uint32_t)(0x1FUL << 2) +#define DMA_HardTrig_GTIM3_TRIGINT (uint32_t)(0x20UL << 2) +#define DMA_HardTrig_GTIM3_CH1COMINT (uint32_t)(0x21UL << 2) +#define DMA_HardTrig_GTIM3_CH2COMINT (uint32_t)(0x22UL << 2) +#define DMA_HardTrig_GTIM3_CH3COMINT (uint32_t)(0x23UL << 2) +#define DMA_HardTrig_GTIM3_CH4COMINT (uint32_t)(0x24UL << 2) + +#define DMA_HardTrig_GTIM4_OVERINT (uint32_t)(0x25UL << 2) +#define DMA_HardTrig_GTIM4_TRIGINT (uint32_t)(0x26UL << 2) +#define DMA_HardTrig_GTIM4_CH1COMINT (uint32_t)(0x27UL << 2) +#define DMA_HardTrig_GTIM4_CH2COMINT (uint32_t)(0x28UL << 2) +#define DMA_HardTrig_GTIM4_CH3COMINT (uint32_t)(0x29UL << 2) +#define DMA_HardTrig_GTIM4_CH4COMINT (uint32_t)(0x2AUL << 2) + +#define IS_DMA_HARD_TRIGSRC(TRIGSRC) (((TRIGSRC) == DMA_HardTrig_UART1_RXBufferNE) || \ + ((TRIGSRC) == DMA_HardTrig_UART1_TXBufferE) || \ + ((TRIGSRC) == DMA_HardTrig_UART2_RXBufferNE) || \ + ((TRIGSRC) == DMA_HardTrig_UART2_TXBufferE) || \ + ((TRIGSRC) == DMA_HardTrig_UART3_RXBufferNE) || \ + ((TRIGSRC) == DMA_HardTrig_UART3_TXBufferE) || \ + ((TRIGSRC) == DMA_HardTrig_SPI1_RXBufferNE) || \ + ((TRIGSRC) == DMA_HardTrig_SPI1_TXBufferE) || \ + ((TRIGSRC) == DMA_HardTrig_SPI2_RXBufferNE) || \ + ((TRIGSRC) == DMA_HardTrig_SPI2_TXBufferE) || \ + ((TRIGSRC) == DMA_HardTrig_ADC_TRANSCOMPLETE)|| \ + ((TRIGSRC) == DMA_HardTrig_BTIM1_OVERINT) || \ + ((TRIGSRC) == DMA_HardTrig_BTIM1_TRIGINT) || \ + ((TRIGSRC) == DMA_HardTrig_BTIM2_OVERINT) || \ + ((TRIGSRC) == DMA_HardTrig_BTIM2_TRIGINT) || \ + ((TRIGSRC) == DMA_HardTrig_BTIM3_OVERINT) || \ + ((TRIGSRC) == DMA_HardTrig_BTIM3_TRIGINT) || \ + ((TRIGSRC) == DMA_HardTrig_ATIM_CH1A2A3A4) || \ + ((TRIGSRC) == DMA_HardTrig_ATIM_CH1B2B3B) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM1_OVERINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM1_TRIGINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM1_CH1COMINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM1_CH2COMINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM1_CH3COMINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM1_CH4COMINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM2_OVERINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM2_TRIGINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM2_CH1COMINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM2_CH2COMINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM2_CH3COMINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM2_CH4COMINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM3_OVERINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM3_TRIGINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM3_CH1COMINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM3_CH2COMINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM3_CH3COMINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM3_CH4COMINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM4_OVERINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM4_TRIGINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM4_CH1COMINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM4_CH2COMINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM4_CH3COMINT) || \ + ((TRIGSRC) == DMA_HardTrig_GTIM4_CH4COMINT)) + + +#define DMA_CHANNEL_EN bv0 //DMA CHANNEL ENABLE +#define DMA_SOFTTRIG_EN bv1 //Soft Trig Trans Start Now +#define CSR_CLEAR_Mask (uint32_t)0xFFFFFF07 +#define TRIG_CLEAR_Mask (uint32_t)0xFFFFFF00 +#define CNT_CLEAR_Mask (uint32_t)0xFFFF0000 + +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_TE ((uint32_t)0x00000004) +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF9) == 0x00) && ((IT) != 0x00)) + +#define DMA_IT_TC1 ((uint32_t)0x00000001) +#define DMA_IT_TE1 ((uint32_t)0x00000002) +#define DMA_IT_TC2 ((uint32_t)0x00000010) +#define DMA_IT_TE2 ((uint32_t)0x00000020) +#define DMA_IT_TC3 ((uint32_t)0x00000100) +#define DMA_IT_TE3 ((uint32_t)0x00000200) +#define DMA_IT_TC4 ((uint32_t)0x00001000) +#define DMA_IT_TE4 ((uint32_t)0x00002000) +#define DMA_IT_TC5 ((uint32_t)0x00010000) +#define DMA_IT_TE5 ((uint32_t)0x00020000) +#define DMA_IT_ALL ((uint32_t)0x00033333) + +#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xFFFCCCCC) == 0x00) && ((IT) != 0x00)) +#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TC1) || ((IT) == DMA_IT_TE1) || \ + ((IT) == DMA_IT_TC2) || ((IT) == DMA_IT_TE2) || \ + ((IT) == DMA_IT_TC3) || ((IT) == DMA_IT_TE3) || \ + ((IT) == DMA_IT_TC4) || ((IT) == DMA_IT_TE4) || \ + ((IT) == DMA_IT_TC5) || ((IT) == DMA_IT_TE5)) + + +#define DMA_CHANNEL_STATUS_INIT ((uint8_t)0x00) +#define DMA_CHANNEL_STATUS_ADDRESSOUTRANGE ((uint8_t)0x01) +#define DMA_CHANNEL_STATUS_STOPREQ ((uint8_t)0x02) +#define DMA_CHANNEL_STATUS_SRCADDERR ((uint8_t)0x03) +#define DMA_CHANNEL_STATUS_DSTADDERR ((uint8_t)0x04) +#define DMA_CHANNEL_STATUS_TRANSCOMPLETE ((uint8_t)0x05) + +//============================================================ + +void DMA_DeInit(DMACHANNEL_TypeDef *DMAy_Channelx); +void DMA_Init(DMACHANNEL_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); +void DMA_Cmd(DMACHANNEL_TypeDef *DMAy_Channelx, FunctionalState NewState); +void DMA_SWTrigCmd(DMACHANNEL_TypeDef *DMAy_Channelx); +void DMA_ITConfig(DMACHANNEL_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); +uint8_t DMA_GetFlagStatus(DMACHANNEL_TypeDef *DMAy_Channelx); + +//============================================================ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_flash.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_flash.h new file mode 100644 index 0000000..e90f225 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_flash.h @@ -0,0 +1,166 @@ +/** + * @file cw32f030_flash.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-13 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F03x_FLASH_H__ +#define __CW32F03x_FLASH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "base_types.h" +#include "cw32f030.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +//============================================================ + +/** @defgroup FLASH状态 + * @{ + */ +#define FLASH_FLAG_OK (0UL) +#define FLASH_FLAG_BSY (bv5) /*!< FLASH Busy flag */ +#define FLASH_FLAG_PGERR (bv4) /*!< FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR (bv1) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PCERR (bv0) /*!< FLASH PC error flag */ +#define FLASH_ERROR_ADDR 0x80 + +/** @defgroup 读访问周期延时 + * @{ + */ +#define FLASH_Latency_1 ((uint32_t)0x00000000) /*!< FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000001) /*!< FLASH Two Latency cycles */ +#define FLASH_Latency_3 ((uint32_t)0x00000002) /*!< FLASH THREE Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2) || \ + ((LATENCY) == FLASH_Latency_3)) + +/** @defgroup FETCH开关 + * @{ + */ +#define FLASH_Prefetch_Enable ((uint32_t)0x00000008) /*!< FLASH Prefetch Enable */ +#define FLASH_Prefetch_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Disable */ +#define IS_FLASH_PREFETCH_STATE(STATE) (((STATE) == FLASH_Prefetch_Enable) || \ + ((STATE) == FLASH_Prefetch_Disable)) + +/** @defgroup CACHE开关 + * @{ + */ +#define FLASH_Cache_Enable ((uint32_t)0x00000010) /*!< FLASH Buffer Enable */ +#define FLASH_Cache_Disable ((uint32_t)0x00000000) /*!< FLASH Buffer Disable */ +#define IS_FLASH_CACHE_STATE(STATE) (((STATE) == FLASH_Cache_Enable) || \ + ((STATE) == FLASH_Cache_Disable)) + +/** @defgroup 读保护等级 + * @{ + */ +#define FLASH_RDLEVEL0 ((uint16_t)0x00) +#define FLASH_RDLEVEL1 ((uint16_t)0x01) +#define FLASH_RDLEVEL2 ((uint16_t)0x02) +#define FLASH_RDLEVEL3 ((uint16_t)0x03) +#define IS_FLASH_RDLEVEL(LEVEL) (((LEVEL) == FLASH_RDLEVEL0) || \ + ((LEVEL) == FLASH_RDLEVEL1) || \ + ((LEVEL) == FLASH_RDLEVEL2) || \ + ((LEVEL) == FLASH_RDLEVEL3)) + +/** @defgroup 中断标志位 + * @{ + */ +#define FLASH_IT_PROG (bv4) +#define FLASH_IT_PAGELOCK (bv1) +#define FLASH_IT_PC (bv0) +#define IS_FLASH_IT(IT) ((((IT) & 0xFFFFFFEC) == 0x0UL) && ((IT) != 0x0UL)) +#define IS_FLASH_GET_IT(IT) (((IT) == FLASH_IT_PROG) || \ + ((IT) == FLASH_IT_PAGELOCK) || \ + ((IT) == FLASH_IT_PC)) + +/** @defgroup FLASH页 + * @{ + */ +#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Pages */ +#define IS_FLASH_PAGE_Number(PAGENUMBER) ((PAGENUMBER) <= 127) +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x00000000) && ((ADDRESS) < 0x00010000)) + +//============================================================ +//设置FLASH读访问周期 +void FLASH_SetLatency(uint32_t FLASH_Latency); +//设置预取使能 +void FLASH_PrefetchCmd(uint32_t FLASH_Prefetch); +//设置BUFFER使能 +void FLASH_CacheCmd(uint32_t FLASH_Buffer); +//获取FLASH的Fetch状态 +FlagStatus FLASH_GetPrefetchStatus(void); +//获取FLASH的Cache状态 +FlagStatus FLASH_GetCacheStatus(void); +//获取FLASH的读保护等级 +uint8_t FLASH_GetReadOutLevel(void); +//设置FLASH的读保护等级 +void FLASH_SetReadOutLevel(uint16_t RdLevel); +//解锁FLASH所有页面 +void FLASH_UnlockAllPages(void); +//锁定FLASH所有页面 +void FLASH_LockAllPages(void); +//解锁FLASH指定页面：按照页面号解锁，0~127 +uint8_t FLASH_UnlockPage(uint8_t Page_Number); +//解锁FLASH指定页面：按照起始和终止地址解锁 +uint8_t FLASH_UnlockPages(uint32_t StartAddr, uint32_t EndAddr); +//擦除FLASH指定页面：按照页面号擦除，0~127 +uint8_t FLASH_ErasePage(uint8_t Page_Number); +//擦除FLASH指定页面：按照起始和终止地址擦除 +uint8_t FLASH_ErasePages(uint32_t StartAddr, uint32_t EndAddr); +//指定地址开始写一定长度的数据，按照字节写 +uint8_t FLASH_WriteBytes(uint32_t WriteAddr, uint8_t *pWrBuf, uint16_t WrByteCnt); +//指定地址开始写一定长度的数据，按照半字写 +uint8_t FLASH_WriteHalfWords(uint32_t WriteAddr, uint16_t *pWrBuf, uint16_t WrByteCnt); +//指定地址开始写一定长度的数据，按照字写 +uint8_t FLASH_WriteWords(uint32_t WriteAddr, uint32_t *pWrBuf, uint16_t WrByteCnt); +//锁定FLASH指定页面：按照页面号锁定，0~127 +uint8_t FLASH_LockPage(uint8_t Page_Number); +//锁定FLASH指定页面：按照起始和终止地址锁定 +uint8_t FLASH_LockPages(uint32_t StartAddr, uint32_t EndAddr); +//FLASH指定中断使能配置 +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +//获取指定FLASH中断标志位 +ITStatus FLASH_GetITStatus(uint32_t FLASH_IT); +//清除指定FLASH中断标志位 +void FLASH_ClearITPendingBit(uint32_t FLASH_IT); +//获取FLASH模块当前状态// +uint32_t FLASH_GetStatus(void); + +//============================================================ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_gpio.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_gpio.h new file mode 100644 index 0000000..86dadaa --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_gpio.h @@ -0,0 +1,1084 @@ +#ifndef __CW32F03x_GPIO_H__ +#define __CW32F03x_GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#include "base_types.h" +#include "cw32f030.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +typedef struct +{ + uint32_t Pins; + uint32_t Mode; + uint32_t IT; + uint32_t Speed; +} GPIO_InitTypeDef; + +typedef enum +{ + GPIO_Pin_RESET = 0, + GPIO_Pin_SET +} GPIO_PinState; + +//============================================================ + +void GPIO_SWD2GPIO(void); +void GPIO_GPIO2SWD(void); +void GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pins); +void GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pins); +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void GPIO_ConfigFilter(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pins, uint32_t FltClk); +void GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pins, GPIO_PinState PinState); +void GPIO_HighByte_Write(GPIO_TypeDef *GPIOx, uint8_t Value); +void GPIO_LowByte_Write(GPIO_TypeDef *GPIOx, uint8_t Value); +void GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pins); +GPIO_PinState GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); + +//============================================================ + +#define GPIO_MODE_ANALOG (0X00) +#define GPIO_MODE_INPUT (0x10) +#define GPIO_MODE_INPUT_PULLUP (0x11) +#define GPIO_MODE_INPUT_PULLDOWN (0x12) +#define GPIO_MODE_OUTPUT_PP (0x20) +#define GPIO_MODE_OUTPUT_OD (0x21) + +#define GPIO_IT_NONE (0x80) +#define GPIO_IT_RISING (0x81) +#define GPIO_IT_FALLING (0x82) +#define GPIO_IT_HIGH (0x84) +#define GPIO_IT_LOW (0x88) + +#define GPIO_SPEED_LOW (0x0000) +#define GPIO_SPEED_HIGH (0xFFFF) + +//============================================================ + +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +//============================================================ +//端口滤波定义 +#define GPIO_FLTCLK_HCLK2 (((uint32_t)0) << 16) +#define GPIO_FLTCLK_HCLK4 (((uint32_t)1) << 16) +#define GPIO_FLTCLK_HCLK8 (((uint32_t)2) << 16) +#define GPIO_FLTCLK_BTIM1OV (((uint32_t)3) << 16) +#define GPIO_FLTCLK_RC150K (((uint32_t)4) << 16) +#define GPIO_FLTCLK_LSI (((uint32_t)5) << 16) +#define GPIO_FLTCLK_RC10K (((uint32_t)6) << 16) + +//============================================================ +//清除CW_GPIO中断标志 +#define GPIOA_INTFLAG_CLR(Mask) ((CW_GPIOA->ICR) = (~((uint32_t)(Mask)))) +#define GPIOB_INTFLAG_CLR(Mask) ((CW_GPIOB->ICR) = (~((uint32_t)(Mask)))) +#define GPIOC_INTFLAG_CLR(Mask) ((CW_GPIOC->ICR) = (~((uint32_t)(Mask)))) +#define GPIOF_INTFLAG_CLR(Mask) ((CW_GPIOF->ICR) = (~((uint32_t)(Mask)))) + +//============================================================ +//ANALOG OR DIGTAL +#define PA00_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN0 = 0) +#define PA00_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN0 = 1) +#define PA01_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN1 = 0) +#define PA01_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN1 = 1) +#define PA02_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN2 = 0) +#define PA02_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN2 = 1) +#define PA03_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN3 = 0) +#define PA03_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN3 = 1) +#define PA04_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN4 = 0) +#define PA04_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN4 = 1) +#define PA05_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN5 = 0) +#define PA05_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN5 = 1) +#define PA06_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN6 = 0) +#define PA06_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN6 = 1) +#define PA07_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN7 = 0) +#define PA07_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN7 = 1) +#define PA08_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN8 = 0) +#define PA08_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN8 = 1) +#define PA09_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN9 = 0) +#define PA09_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN9 = 1) +#define PA10_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN10 = 0) +#define PA10_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN10 = 1) +#define PA11_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN11 = 0) +#define PA11_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN11 = 1) +#define PA12_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN12 = 0) +#define PA12_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN12 = 1) +#define PA13_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN13 = 0) +#define PA13_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN13 = 1) +#define PA14_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN14 = 0) +#define PA14_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN14 = 1) +#define PA15_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN15 = 0) +#define PA15_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN15 = 1) +#define PB00_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN0 = 0) +#define PB00_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN0 = 1) +#define PB01_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN1 = 0) +#define PB01_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN1 = 1) +#define PB02_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN2 = 0) +#define PB02_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN2 = 1) +#define PB03_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN3 = 0) +#define PB03_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN3 = 1) +#define PB04_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN4 = 0) +#define PB04_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN4 = 1) +#define PB05_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN5 = 0) +#define PB05_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN5 = 1) +#define PB06_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN6 = 0) +#define PB06_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN6 = 1) +#define PB07_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN7 = 0) +#define PB07_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN7 = 1) +#define PB08_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN8 = 0) +#define PB08_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN8 = 1) +#define PB09_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN9 = 0) +#define PB09_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN9 = 1) +#define PB10_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN10 = 0) +#define PB10_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN10 = 1) +#define PB11_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN11 = 0) +#define PB11_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN11 = 1) +#define PB12_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN12 = 0) +#define PB12_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN12 = 1) +#define PB13_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN13 = 0) +#define PB13_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN13 = 1) +#define PB14_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN14 = 0) +#define PB14_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN14 = 1) +#define PB15_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN15 = 0) +#define PB15_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN15 = 1) +#define PC13_DIGTAL_ENABLE() (CW_GPIOC->ANALOG_f.PIN13 = 0) +#define PC13_ANALOG_ENABLE() (CW_GPIOC->ANALOG_f.PIN13 = 1) +#define PC14_DIGTAL_ENABLE() (CW_GPIOC->ANALOG_f.PIN14 = 0) +#define PC14_ANALOG_ENABLE() (CW_GPIOC->ANALOG_f.PIN14 = 1) +#define PC15_DIGTAL_ENABLE() (CW_GPIOC->ANALOG_f.PIN15 = 0) +#define PC15_ANALOG_ENABLE() (CW_GPIOC->ANALOG_f.PIN15 = 1) +#define PF00_DIGTAL_ENABLE() (CW_GPIOF->ANALOG_f.PIN0 = 0) +#define PF00_ANALOG_ENABLE() (CW_GPIOF->ANALOG_f.PIN0 = 1) +#define PF01_DIGTAL_ENABLE() (CW_GPIOF->ANALOG_f.PIN1 = 0) +#define PF01_ANALOG_ENABLE() (CW_GPIOF->ANALOG_f.PIN1 = 1) +#define PF06_DIGTAL_ENABLE() (CW_GPIOF->ANALOG_f.PIN6 = 0) +#define PF06_ANALOG_ENABLE() (CW_GPIOF->ANALOG_f.PIN6 = 1) +#define PF07_DIGTAL_ENABLE() (CW_GPIOF->ANALOG_f.PIN7 = 0) +#define PF07_ANALOG_ENABLE() (CW_GPIOF->ANALOG_f.PIN7 = 1) +#define PF03_DIGTAL_ENABLE() (CW_GPIOF->ANALOG_f.PIN3 = 0) +#define PF03_ANALOG_ENABLE() (CW_GPIOF->ANALOG_f.PIN3 = 1) + +//============================================================ +// INPUTAND OUTPUT +#define PA00_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN0 = 0) +#define PA00_DIR_INPUT() (CW_GPIOA->DIR_f.PIN0 = 1) +#define PA01_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN1 = 0) +#define PA01_DIR_INPUT() (CW_GPIOA->DIR_f.PIN1 = 1) +#define PA02_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN2 = 0) +#define PA02_DIR_INPUT() (CW_GPIOA->DIR_f.PIN2 = 1) +#define PA03_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN3 = 0) +#define PA03_DIR_INPUT() (CW_GPIOA->DIR_f.PIN3 = 1) +#define PA04_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN4 = 0) +#define PA04_DIR_INPUT() (CW_GPIOA->DIR_f.PIN4 = 1) +#define PA05_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN5 = 0) +#define PA05_DIR_INPUT() (CW_GPIOA->DIR_f.PIN5 = 1) +#define PA06_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN6 = 0) +#define PA06_DIR_INPUT() (CW_GPIOA->DIR_f.PIN6 = 1) +#define PA07_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN7 = 0) +#define PA07_DIR_INPUT() (CW_GPIOA->DIR_f.PIN7 = 1) +#define PA08_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN8 = 0) +#define PA08_DIR_INPUT() (CW_GPIOA->DIR_f.PIN8 = 1) +#define PA09_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN9 = 0) +#define PA09_DIR_INPUT() (CW_GPIOA->DIR_f.PIN9 = 1) +#define PA10_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN10 = 0) +#define PA10_DIR_INPUT() (CW_GPIOA->DIR_f.PIN10 = 1) +#define PA11_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN11 = 0) +#define PA11_DIR_INPUT() (CW_GPIOA->DIR_f.PIN11 = 1) +#define PA12_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN12 = 0) +#define PA12_DIR_INPUT() (CW_GPIOA->DIR_f.PIN12 = 1) +#define PA13_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN13 = 0) +#define PA13_DIR_INPUT() (CW_GPIOA->DIR_f.PIN13 = 1) +#define PA14_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN14 = 0) +#define PA14_DIR_INPUT() (CW_GPIOA->DIR_f.PIN14 = 1) +#define PA15_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN15 = 0) +#define PA15_DIR_INPUT() (CW_GPIOA->DIR_f.PIN15 = 1) +#define PB00_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN0 = 0) +#define PB00_DIR_INPUT() (CW_GPIOB->DIR_f.PIN0 = 1) +#define PB01_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN1 = 0) +#define PB01_DIR_INPUT() (CW_GPIOB->DIR_f.PIN1 = 1) +#define PB02_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN2 = 0) +#define PB02_DIR_INPUT() (CW_GPIOB->DIR_f.PIN2 = 1) +#define PB03_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN3 = 0) +#define PB03_DIR_INPUT() (CW_GPIOB->DIR_f.PIN3 = 1) +#define PB04_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN4 = 0) +#define PB04_DIR_INPUT() (CW_GPIOB->DIR_f.PIN4 = 1) +#define PB05_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN5 = 0) +#define PB05_DIR_INPUT() (CW_GPIOB->DIR_f.PIN5 = 1) +#define PB06_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN6 = 0) +#define PB06_DIR_INPUT() (CW_GPIOB->DIR_f.PIN6 = 1) +#define PB07_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN7 = 0) +#define PB07_DIR_INPUT() (CW_GPIOB->DIR_f.PIN7 = 1) +#define PB08_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN8 = 0) +#define PB08_DIR_INPUT() (CW_GPIOB->DIR_f.PIN8 = 1) +#define PB09_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN9 = 0) +#define PB09_DIR_INPUT() (CW_GPIOB->DIR_f.PIN9 = 1) +#define PB10_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN10 = 0) +#define PB10_DIR_INPUT() (CW_GPIOB->DIR_f.PIN10 = 1) +#define PB11_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN11 = 0) +#define PB11_DIR_INPUT() (CW_GPIOB->DIR_f.PIN11 = 1) +#define PB12_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN12 = 0) +#define PB12_DIR_INPUT() (CW_GPIOB->DIR_f.PIN12 = 1) +#define PB13_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN13 = 0) +#define PB13_DIR_INPUT() (CW_GPIOB->DIR_f.PIN13 = 1) +#define PB14_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN14 = 0) +#define PB14_DIR_INPUT() (CW_GPIOB->DIR_f.PIN14 = 1) +#define PB15_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN15 = 0) +#define PB15_DIR_INPUT() (CW_GPIOB->DIR_f.PIN15 = 1) +#define PC13_DIR_OUTPUT() (CW_GPIOC->DIR_f.PIN13 = 0) +#define PC13_DIR_INPUT() (CW_GPIOC->DIR_f.PIN13 = 1) +#define PC14_DIR_OUTPUT() (CW_GPIOC->DIR_f.PIN14 = 0) +#define PC14_DIR_INPUT() (CW_GPIOC->DIR_f.PIN14 = 1) +#define PC15_DIR_OUTPUT() (CW_GPIOC->DIR_f.PIN15 = 0) +#define PC15_DIR_INPUT() (CW_GPIOC->DIR_f.PIN15 = 1) +#define PF00_DIR_OUTPUT() (CW_GPIOF->DIR_f.PIN0 = 0) +#define PF00_DIR_INPUT() (CW_GPIOF->DIR_f.PIN0 = 1) +#define PF01_DIR_OUTPUT() (CW_GPIOF->DIR_f.PIN1 = 0) +#define PF01_DIR_INPUT() (CW_GPIOF->DIR_f.PIN1 = 1) +#define PF06_DIR_OUTPUT() (CW_GPIOF->DIR_f.PIN6 = 0) +#define PF06_DIR_INPUT() (CW_GPIOF->DIR_f.PIN6 = 1) +#define PF07_DIR_OUTPUT() (CW_GPIOF->DIR_f.PIN7 = 0) +#define PF07_DIR_INPUT() (CW_GPIOF->DIR_f.PIN7 = 1) +#define PF03_DIR_OUTPUT() (CW_GPIOF->DIR_f.PIN3 = 0) +#define PF03_DIR_INPUT() (CW_GPIOF->DIR_f.PIN3 = 1) + +//============================================================ +//push-pull or opendrain +#define PA00_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN0 = 0) +#define PA00_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN0 = 1) +#define PA01_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN1 = 0) +#define PA01_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN1 = 1) +#define PA02_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN2 = 0) +#define PA02_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN2 = 1) +#define PA03_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN3 = 0) +#define PA03_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN3 = 1) +#define PA04_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN4 = 0) +#define PA04_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN4 = 1) +#define PA05_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN5 = 0) +#define PA05_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN5 = 1) +#define PA06_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN6 = 0) +#define PA06_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN6 = 1) +#define PA07_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN7 = 0) +#define PA07_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN7 = 1) +#define PA08_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN8 = 0) +#define PA08_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN8 = 1) +#define PA09_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN9 = 0) +#define PA09_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN9 = 1) +#define PA10_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN10 = 0) +#define PA10_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN10 = 1) +#define PA11_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN11 = 0) +#define PA11_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN11 = 1) +#define PA12_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN12 = 0) +#define PA12_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN12 = 1) +#define PA13_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN13 = 0) +#define PA13_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN13 = 1) +#define PA14_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN14 = 0) +#define PA14_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN14 = 1) +#define PA15_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN15 = 0) +#define PA15_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN15 = 1) +#define PB00_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN0 = 0) +#define PB00_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN0 = 1) +#define PB01_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN1 = 0) +#define PB01_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN1 = 1) +#define PB02_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN2 = 0) +#define PB02_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN2 = 1) +#define PB03_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN3 = 0) +#define PB03_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN3 = 1) +#define PB04_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN4 = 0) +#define PB04_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN4 = 1) +#define PB05_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN5 = 0) +#define PB05_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN5 = 1) +#define PB06_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN6 = 0) +#define PB06_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN6 = 1) +#define PB07_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN7 = 0) +#define PB07_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN7 = 1) +#define PB08_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN8 = 0) +#define PB08_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN8 = 1) +#define PB09_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN9 = 0) +#define PB09_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN9 = 1) +#define PB10_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN10 = 0) +#define PB10_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN10 = 1) +#define PB11_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN11 = 0) +#define PB11_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN11 = 1) +#define PB12_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN12 = 0) +#define PB12_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN12 = 1) +#define PB13_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN13 = 0) +#define PB13_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN13 = 1) +#define PB14_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN14 = 0) +#define PB14_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN14 = 1) +#define PB15_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN15 = 0) +#define PB15_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN15 = 1) +#define PC13_PUSHPULL_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN13 = 0) +#define PC13_OPENDRAIN_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN13 = 1) +#define PC14_PUSHPULL_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN14 = 0) +#define PC14_OPENDRAIN_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN14 = 1) +#define PC15_PUSHPULL_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN15 = 0) +#define PC15_OPENDRAIN_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN15 = 1) +#define PF00_PUSHPULL_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN0 = 0) +#define PF00_OPENDRAIN_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN0 = 1) +#define PF01_PUSHPULL_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN1 = 0) +#define PF01_OPENDRAIN_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN1 = 1) +#define PF06_PUSHPULL_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN6 = 0) +#define PF06_OPENDRAIN_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN6 = 1) +#define PF07_PUSHPULL_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN7 = 0) +#define PF07_OPENDRAIN_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN7 = 1) +#define PF03_PUSHPULL_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN3 = 0) +#define PF03_OPENDRAIN_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN3 = 1) + +//============================================================ +// SPEED +#define PA00_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN0 = 0) +#define PA00_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN0 = 1) +#define PA01_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN1 = 0) +#define PA01_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN1 = 1) +#define PA02_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN2 = 0) +#define PA02_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN2 = 1) +#define PA03_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN3 = 0) +#define PA03_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN3 = 1) +#define PA04_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN4 = 0) +#define PA04_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN4 = 1) +#define PA05_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN5 = 0) +#define PA05_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN5 = 1) +#define PA06_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN6 = 0) +#define PA06_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN6 = 1) +#define PA07_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN7 = 0) +#define PA07_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN7 = 1) +#define PA08_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN8 = 0) +#define PA08_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN8 = 1) +#define PA09_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN9 = 0) +#define PA09_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN9 = 1) +#define PA10_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN10 = 0) +#define PA10_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN10 = 1) +#define PA11_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN11 = 0) +#define PA11_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN11 = 1) +#define PA12_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN12 = 0) +#define PA12_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN12 = 1) +#define PA13_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN13 = 0) +#define PA13_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN13 = 1) +#define PA14_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN14 = 0) +#define PA14_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN14 = 1) +#define PA15_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN15 = 0) +#define PA15_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN15 = 1) +#define PB00_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN0 = 0) +#define PB00_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN0 = 1) +#define PB01_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN1 = 0) +#define PB01_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN1 = 1) +#define PB02_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN2 = 0) +#define PB02_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN2 = 1) +#define PB03_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN3 = 0) +#define PB03_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN3 = 1) +#define PB04_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN4 = 0) +#define PB04_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN4 = 1) +#define PB05_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN5 = 0) +#define PB05_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN5 = 1) +#define PB06_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN6 = 0) +#define PB06_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN6 = 1) +#define PB07_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN7 = 0) +#define PB07_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN7 = 1) +#define PB08_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN8 = 0) +#define PB08_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN8 = 1) +#define PB09_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN9 = 0) +#define PB09_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN9 = 1) +#define PB10_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN10 = 0) +#define PB10_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN10 = 1) +#define PB11_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN11 = 0) +#define PB11_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN11 = 1) +#define PB12_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN12 = 0) +#define PB12_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN12 = 1) +#define PB13_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN13 = 0) +#define PB13_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN13 = 1) +#define PB14_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN14 = 0) +#define PB14_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN14 = 1) +#define PB15_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN15 = 0) +#define PB15_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN15 = 1) +#define PC13_SPEED_LOW() (CW_GPIOC->SPEED_f.PIN13 = 0) +#define PC13_SPEED_HIGH() (CW_GPIOC->SPEED_f.PIN13 = 1) +#define PC14_SPEED_LOW() (CW_GPIOC->SPEED_f.PIN14 = 0) +#define PC14_SPEED_HIGH() (CW_GPIOC->SPEED_f.PIN14 = 1) +#define PC15_SPEED_LOW() (CW_GPIOC->SPEED_f.PIN15 = 0) +#define PC15_SPEED_HIGH() (CW_GPIOC->SPEED_f.PIN15 = 1) +#define PF00_SPEED_LOW() (CW_GPIOF->SPEED_f.PIN0 = 0) +#define PF00_SPEED_HIGH() (CW_GPIOF->SPEED_f.PIN0 = 1) +#define PF01_SPEED_LOW() (CW_GPIOF->SPEED_f.PIN1 = 0) +#define PF01_SPEED_HIGH() (CW_GPIOF->SPEED_f.PIN1 = 1) +#define PF06_SPEED_LOW() (CW_GPIOF->SPEED_f.PIN6 = 0) +#define PF06_SPEED_HIGH() (CW_GPIOF->SPEED_f.PIN6 = 1) +#define PF07_SPEED_LOW() (CW_GPIOF->SPEED_f.PIN7 = 0) +#define PF07_SPEED_HIGH() (CW_GPIOF->SPEED_f.PIN7 = 1) +#define PF03_SPEED_LOW() (CW_GPIOF->SPEED_f.PIN3 = 0) +#define PF03_SPEED_HIGH() (CW_GPIOF->SPEED_f.PIN3 = 1) +//============================================================ +//PUR +#define PA00_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN0 = 1) +#define PA00_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN0 = 0) +#define PA01_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN1 = 1) +#define PA01_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN1 = 0) +#define PA02_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN2 = 1) +#define PA02_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN2 = 0) +#define PA03_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN3 = 1) +#define PA03_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN3 = 0) +#define PA04_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN4 = 1) +#define PA04_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN4 = 0) +#define PA05_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN5 = 1) +#define PA05_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN5 = 0) +#define PA06_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN6 = 1) +#define PA06_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN6 = 0) +#define PA07_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN7 = 1) +#define PA07_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN7 = 0) +#define PA08_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN8 = 1) +#define PA08_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN8 = 0) +#define PA09_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN9 = 1) +#define PA09_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN9 = 0) +#define PA10_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN10 = 1) +#define PA10_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN10 = 0) +#define PA11_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN11 = 1) +#define PA11_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN11 = 0) +#define PA12_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN12 = 1) +#define PA12_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN12 = 0) +#define PA13_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN13 = 1) +#define PA13_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN13 = 0) +#define PA14_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN14 = 1) +#define PA14_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN14 = 0) +#define PA15_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN15 = 1) +#define PA15_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN15 = 0) +#define PB00_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN0 = 1) +#define PB00_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN0 = 0) +#define PB01_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN1 = 1) +#define PB01_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN1 = 0) +#define PB02_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN2 = 1) +#define PB02_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN2 = 0) +#define PB03_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN3 = 1) +#define PB03_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN3 = 0) +#define PB04_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN4 = 1) +#define PB04_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN4 = 0) +#define PB05_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN5 = 1) +#define PB05_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN5 = 0) +#define PB06_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN6 = 1) +#define PB06_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN6 = 0) +#define PB07_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN7 = 1) +#define PB07_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN7 = 0) +#define PB08_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN8 = 1) +#define PB08_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN8 = 0) +#define PB09_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN9 = 1) +#define PB09_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN9 = 0) +#define PB10_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN10 = 1) +#define PB10_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN10 = 0) +#define PB11_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN11 = 1) +#define PB11_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN11 = 0) +#define PB12_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN12 = 1) +#define PB12_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN12 = 0) +#define PB13_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN13 = 1) +#define PB13_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN13 = 0) +#define PB14_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN14 = 1) +#define PB14_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN14 = 0) +#define PB15_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN15 = 1) +#define PB15_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN15 = 0) +#define PC13_PUR_ENABLE() (CW_GPIOC->PUR_f.PIN13 = 1) +#define PC13_PUR_DISABLE() (CW_GPIOC->PUR_f.PIN13 = 0) +#define PC14_PUR_ENABLE() (CW_GPIOC->PUR_f.PIN14 = 1) +#define PC14_PUR_DISABLE() (CW_GPIOC->PUR_f.PIN14 = 0) +#define PC15_PUR_ENABLE() (CW_GPIOC->PUR_f.PIN15 = 1) +#define PC15_PUR_DISABLE() (CW_GPIOC->PUR_f.PIN15 = 0) +#define PF00_PUR_ENABLE() (CW_GPIOF->PUR_f.PIN0 = 1) +#define PF00_PUR_DISABLE() (CW_GPIOF->PUR_f.PIN0 = 0) +#define PF01_PUR_ENABLE() (CW_GPIOF->PUR_f.PIN1 = 1) +#define PF01_PUR_DISABLE() (CW_GPIOF->PUR_f.PIN1 = 0) +#define PF06_PUR_ENABLE() (CW_GPIOF->PUR_f.PIN6 = 1) +#define PF06_PUR_DISABLE() (CW_GPIOF->PUR_f.PIN6 = 0) +#define PF07_PUR_ENABLE() (CW_GPIOF->PUR_f.PIN7 = 1) +#define PF07_PUR_DISABLE() (CW_GPIOF->PUR_f.PIN7 = 0) +#define PF03_PUR_ENABLE() (CW_GPIOF->PUR_f.PIN3 = 1) +#define PF03_PUR_DISABLE() (CW_GPIOF->PUR_f.PIN3 = 0) + +//============================================================ +//PDR +#define PA00_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN0 = 1) +#define PA00_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN0 = 0) +#define PA01_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN1 = 1) +#define PA01_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN1 = 0) +#define PA02_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN2 = 1) +#define PA02_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN2 = 0) +#define PA03_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN3 = 1) +#define PA03_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN3 = 0) +#define PA04_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN4 = 1) +#define PA04_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN4 = 0) +#define PA05_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN5 = 1) +#define PA05_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN5 = 0) +#define PA06_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN6 = 1) +#define PA06_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN6 = 0) +#define PA07_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN7 = 1) +#define PA07_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN7 = 0) +#define PA08_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN8 = 1) +#define PA08_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN8 = 0) +#define PA09_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN9 = 1) +#define PA09_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN9 = 0) +#define PA10_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN10 = 1) +#define PA10_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN10 = 0) +#define PA11_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN11 = 1) +#define PA11_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN11 = 0) +#define PA12_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN12 = 1) +#define PA12_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN12 = 0) +#define PA13_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN13 = 1) +#define PA13_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN13 = 0) +#define PA14_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN14 = 1) +#define PA14_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN14 = 0) +#define PA15_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN15 = 1) +#define PA15_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN15 = 0) +#define PB00_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN0 = 1) +#define PB00_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN0 = 0) +#define PB01_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN1 = 1) +#define PB01_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN1 = 0) +#define PB02_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN2 = 1) +#define PB02_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN2 = 0) +#define PB03_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN3 = 1) +#define PB03_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN3 = 0) +#define PB04_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN4 = 1) +#define PB04_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN4 = 0) +#define PB05_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN5 = 1) +#define PB05_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN5 = 0) +#define PB06_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN6 = 1) +#define PB06_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN6 = 0) +#define PB07_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN7 = 1) +#define PB07_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN7 = 0) +#define PB08_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN8 = 1) +#define PB08_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN8 = 0) +#define PB09_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN9 = 1) +#define PB09_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN9 = 0) +#define PB10_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN10 = 1) +#define PB10_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN10 = 0) +#define PB11_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN11 = 1) +#define PB11_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN11 = 0) +#define PB12_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN12 = 1) +#define PB12_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN12 = 0) +#define PB13_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN13 = 1) +#define PB13_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN13 = 0) +#define PB14_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN14 = 1) +#define PB14_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN14 = 0) +#define PB15_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN15 = 1) +#define PB15_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN15 = 0) +#define PC13_PDR_ENABLE() (CW_GPIOC->PDR_f.PIN13 = 1) +#define PC13_PDR_DISABLE() (CW_GPIOC->PDR_f.PIN13 = 0) +#define PC14_PDR_ENABLE() (CW_GPIOC->PDR_f.PIN14 = 1) +#define PC14_PDR_DISABLE() (CW_GPIOC->PDR_f.PIN14 = 0) +#define PC15_PDR_ENABLE() (CW_GPIOC->PDR_f.PIN15 = 1) +#define PC15_PDR_DISABLE() (CW_GPIOC->PDR_f.PIN15 = 0) +#define PF00_PDR_ENABLE() (CW_GPIOF->PDR_f.PIN0 = 1) +#define PF00_PDR_DISABLE() (CW_GPIOF->PDR_f.PIN0 = 0) +#define PF01_PDR_ENABLE() (CW_GPIOF->PDR_f.PIN1 = 1) +#define PF01_PDR_DISABLE() (CW_GPIOF->PDR_f.PIN1 = 0) +#define PF06_PDR_ENABLE() (CW_GPIOF->PDR_f.PIN6 = 1) +#define PF06_PDR_DISABLE() (CW_GPIOF->PDR_f.PIN6 = 0) +#define PF07_PDR_ENABLE() (CW_GPIOF->PDR_f.PIN7 = 1) +#define PF07_PDR_DISABLE() (CW_GPIOF->PDR_f.PIN7 = 0) +#define PF03_PDR_ENABLE() (CW_GPIOF->PDR_f.PIN3 = 1) +#define PF03_PDR_DISABLE() (CW_GPIOF->PDR_f.PIN3 = 0) + +//============================================================ +// GETVALUE +#define PA00_GETVALUE() (CW_GPIOA->IDR & bv0) +#define PA01_GETVALUE() (CW_GPIOA->IDR & bv1) +#define PA02_GETVALUE() (CW_GPIOA->IDR & bv2) +#define PA03_GETVALUE() (CW_GPIOA->IDR & bv3) +#define PA04_GETVALUE() (CW_GPIOA->IDR & bv4) +#define PA05_GETVALUE() (CW_GPIOA->IDR & bv5) +#define PA06_GETVALUE() (CW_GPIOA->IDR & bv6) +#define PA07_GETVALUE() (CW_GPIOA->IDR & bv7) +#define PA08_GETVALUE() (CW_GPIOA->IDR & bv8) +#define PA09_GETVALUE() (CW_GPIOA->IDR & bv9) +#define PA10_GETVALUE() (CW_GPIOA->IDR & bv10) +#define PA11_GETVALUE() (CW_GPIOA->IDR & bv11) +#define PA12_GETVALUE() (CW_GPIOA->IDR & bv12) +#define PA13_GETVALUE() (CW_GPIOA->IDR & bv13) +#define PA14_GETVALUE() (CW_GPIOA->IDR & bv14) +#define PA15_GETVALUE() (CW_GPIOA->IDR & bv15) +#define PB00_GETVALUE() (CW_GPIOB->IDR & bv0) +#define PB01_GETVALUE() (CW_GPIOB->IDR & bv1) +#define PB02_GETVALUE() (CW_GPIOB->IDR & bv2) +#define PB03_GETVALUE() (CW_GPIOB->IDR & bv3) +#define PB04_GETVALUE() (CW_GPIOB->IDR & bv4) +#define PB05_GETVALUE() (CW_GPIOB->IDR & bv5) +#define PB06_GETVALUE() (CW_GPIOB->IDR & bv6) +#define PB07_GETVALUE() (CW_GPIOB->IDR & bv7) +#define PB08_GETVALUE() (CW_GPIOB->IDR & bv8) +#define PB09_GETVALUE() (CW_GPIOB->IDR & bv9) +#define PB10_GETVALUE() (CW_GPIOB->IDR & bv10) +#define PB11_GETVALUE() (CW_GPIOB->IDR & bv11) +#define PB12_GETVALUE() (CW_GPIOB->IDR & bv12) +#define PB13_GETVALUE() (CW_GPIOB->IDR & bv13) +#define PB14_GETVALUE() (CW_GPIOB->IDR & bv14) +#define PB15_GETVALUE() (CW_GPIOB->IDR & bv15) +#define PC13_GETVALUE() (CW_GPIOC->IDR & bv13) +#define PC14_GETVALUE() (CW_GPIOC->IDR & bv14) +#define PC15_GETVALUE() (CW_GPIOC->IDR & bv15) +#define PF00_GETVALUE() (CW_GPIOF->IDR & bv0) +#define PF01_GETVALUE() (CW_GPIOF->IDR & bv1) +#define PF06_GETVALUE() (CW_GPIOF->IDR & bv6) +#define PF07_GETVALUE() (CW_GPIOF->IDR & bv7) +#define PF03_GETVALUE() (CW_GPIOF->IDR & bv3) + +//============================================================ +// SET HIGH AND LOW +#define PA00_SETHIGH() (CW_GPIOA->BSRR = bv0) +#define PA00_SETLOW() (CW_GPIOA->BRR = bv0) +#define PA01_SETHIGH() (CW_GPIOA->BSRR = bv1) +#define PA01_SETLOW() (CW_GPIOA->BRR = bv1) +#define PA02_SETHIGH() (CW_GPIOA->BSRR = bv2) +#define PA02_SETLOW() (CW_GPIOA->BRR = bv2) +#define PA03_SETHIGH() (CW_GPIOA->BSRR = bv3) +#define PA03_SETLOW() (CW_GPIOA->BRR = bv3) +#define PA04_SETHIGH() (CW_GPIOA->BSRR = bv4) +#define PA04_SETLOW() (CW_GPIOA->BRR = bv4) +#define PA05_SETHIGH() (CW_GPIOA->BSRR = bv5) +#define PA05_SETLOW() (CW_GPIOA->BRR = bv5) +#define PA06_SETHIGH() (CW_GPIOA->BSRR = bv6) +#define PA06_SETLOW() (CW_GPIOA->BRR = bv6) +#define PA07_SETHIGH() (CW_GPIOA->BSRR = bv7) +#define PA07_SETLOW() (CW_GPIOA->BRR = bv7) +#define PA08_SETHIGH() (CW_GPIOA->BSRR = bv8) +#define PA08_SETLOW() (CW_GPIOA->BRR = bv8) +#define PA09_SETHIGH() (CW_GPIOA->BSRR = bv9) +#define PA09_SETLOW() (CW_GPIOA->BRR = bv9) +#define PA10_SETHIGH() (CW_GPIOA->BSRR = bv10) +#define PA10_SETLOW() (CW_GPIOA->BRR = bv10) +#define PA11_SETHIGH() (CW_GPIOA->BSRR = bv11) +#define PA11_SETLOW() (CW_GPIOA->BRR = bv11) +#define PA12_SETHIGH() (CW_GPIOA->BSRR = bv12) +#define PA12_SETLOW() (CW_GPIOA->BRR = bv12) +#define PA13_SETHIGH() (CW_GPIOA->BSRR = bv13) +#define PA13_SETLOW() (CW_GPIOA->BRR = bv13) +#define PA14_SETHIGH() (CW_GPIOA->BSRR = bv14) +#define PA14_SETLOW() (CW_GPIOA->BRR = bv14) +#define PA15_SETHIGH() (CW_GPIOA->BSRR = bv15) +#define PA15_SETLOW() (CW_GPIOA->BRR = bv15) +#define PB00_SETHIGH() (CW_GPIOB->BSRR = bv0) +#define PB00_SETLOW() (CW_GPIOB->BRR = bv0) +#define PB01_SETHIGH() (CW_GPIOB->BSRR = bv1) +#define PB01_SETLOW() (CW_GPIOB->BRR = bv1) +#define PB02_SETHIGH() (CW_GPIOB->BSRR = bv2) +#define PB02_SETLOW() (CW_GPIOB->BRR = bv2) +#define PB03_SETHIGH() (CW_GPIOB->BSRR = bv3) +#define PB03_SETLOW() (CW_GPIOB->BRR = bv3) +#define PB04_SETHIGH() (CW_GPIOB->BSRR = bv4) +#define PB04_SETLOW() (CW_GPIOB->BRR = bv4) +#define PB05_SETHIGH() (CW_GPIOB->BSRR = bv5) +#define PB05_SETLOW() (CW_GPIOB->BRR = bv5) +#define PB06_SETHIGH() (CW_GPIOB->BSRR = bv6) +#define PB06_SETLOW() (CW_GPIOB->BRR = bv6) +#define PB07_SETHIGH() (CW_GPIOB->BSRR = bv7) +#define PB07_SETLOW() (CW_GPIOB->BRR = bv7) +#define PB08_SETHIGH() (CW_GPIOB->BSRR = bv8) +#define PB08_SETLOW() (CW_GPIOB->BRR = bv8) +#define PB09_SETHIGH() (CW_GPIOB->BSRR = bv9) +#define PB09_SETLOW() (CW_GPIOB->BRR = bv9) +#define PB10_SETHIGH() (CW_GPIOB->BSRR = bv10) +#define PB10_SETLOW() (CW_GPIOB->BRR = bv10) +#define PB11_SETHIGH() (CW_GPIOB->BSRR = bv11) +#define PB11_SETLOW() (CW_GPIOB->BRR = bv11) +#define PB12_SETHIGH() (CW_GPIOB->BSRR = bv12) +#define PB12_SETLOW() (CW_GPIOB->BRR = bv12) +#define PB13_SETHIGH() (CW_GPIOB->BSRR = bv13) +#define PB13_SETLOW() (CW_GPIOB->BRR = bv13) +#define PB14_SETHIGH() (CW_GPIOB->BSRR = bv14) +#define PB14_SETLOW() (CW_GPIOB->BRR = bv14) +#define PB15_SETHIGH() (CW_GPIOB->BSRR = bv15) +#define PB15_SETLOW() (CW_GPIOB->BRR = bv15) +#define PC13_SETHIGH() (CW_GPIOC->BSRR = bv13) +#define PC13_SETLOW() (CW_GPIOC->BRR = bv13) +#define PC14_SETHIGH() (CW_GPIOC->BSRR = bv14) +#define PC14_SETLOW() (CW_GPIOC->BRR = bv14) +#define PC15_SETHIGH() (CW_GPIOC->BSRR = bv15) +#define PC15_SETLOW() (CW_GPIOC->BRR = bv15) +#define PF00_SETHIGH() (CW_GPIOF->BSRR = bv0) +#define PF00_SETLOW() (CW_GPIOF->BRR = bv0) +#define PF01_SETHIGH() (CW_GPIOF->BSRR = bv1) +#define PF01_SETLOW() (CW_GPIOF->BRR = bv1) +#define PF06_SETHIGH() (CW_GPIOF->BSRR = bv6) +#define PF06_SETLOW() (CW_GPIOF->BRR = bv6) +#define PF07_SETHIGH() (CW_GPIOF->BSRR = bv7) +#define PF07_SETLOW() (CW_GPIOF->BRR = bv7) +#define PF03_SETHIGH() (CW_GPIOF->BSRR = bv3) +#define PF03_SETLOW() (CW_GPIOF->BRR = bv3) + +//============================================================ +// TOG +#define PA00_TOG() (CW_GPIOA->TOG = bv0) +#define PA01_TOG() (CW_GPIOA->TOG = bv1) +#define PA02_TOG() (CW_GPIOA->TOG = bv2) +#define PA03_TOG() (CW_GPIOA->TOG = bv3) +#define PA04_TOG() (CW_GPIOA->TOG = bv4) +#define PA05_TOG() (CW_GPIOA->TOG = bv5) +#define PA06_TOG() (CW_GPIOA->TOG = bv6) +#define PA07_TOG() (CW_GPIOA->TOG = bv7) +#define PA08_TOG() (CW_GPIOA->TOG = bv8) +#define PA09_TOG() (CW_GPIOA->TOG = bv9) +#define PA10_TOG() (CW_GPIOA->TOG = bv10) +#define PA11_TOG() (CW_GPIOA->TOG = bv11) +#define PA12_TOG() (CW_GPIOA->TOG = bv12) +#define PA13_TOG() (CW_GPIOA->TOG = bv13) +#define PA14_TOG() (CW_GPIOA->TOG = bv14) +#define PA15_TOG() (CW_GPIOA->TOG = bv15) +#define PB00_TOG() (CW_GPIOB->TOG = bv0) +#define PB01_TOG() (CW_GPIOB->TOG = bv1) +#define PB02_TOG() (CW_GPIOB->TOG = bv2) +#define PB03_TOG() (CW_GPIOB->TOG = bv3) +#define PB04_TOG() (CW_GPIOB->TOG = bv4) +#define PB05_TOG() (CW_GPIOB->TOG = bv5) +#define PB06_TOG() (CW_GPIOB->TOG = bv6) +#define PB07_TOG() (CW_GPIOB->TOG = bv7) +#define PB08_TOG() (CW_GPIOB->TOG = bv8) +#define PB09_TOG() (CW_GPIOB->TOG = bv9) +#define PB10_TOG() (CW_GPIOB->TOG = bv10) +#define PB11_TOG() (CW_GPIOB->TOG = bv11) +#define PB12_TOG() (CW_GPIOB->TOG = bv12) +#define PB13_TOG() (CW_GPIOB->TOG = bv13) +#define PB14_TOG() (CW_GPIOB->TOG = bv14) +#define PB15_TOG() (CW_GPIOB->TOG = bv15) +#define PC13_TOG() (CW_GPIOC->TOG = bv13) +#define PC14_TOG() (CW_GPIOC->TOG = bv14) +#define PC15_TOG() (CW_GPIOC->TOG = bv15) +#define PF00_TOG() (CW_GPIOF->TOG = bv0) +#define PF01_TOG() (CW_GPIOF->TOG = bv1) +#define PF06_TOG() (CW_GPIOF->TOG = bv6) +#define PF07_TOG() (CW_GPIOF->TOG = bv7) +#define PF03_TOG() (CW_GPIOF->TOG = bv3) + +//============================================================ +// AF0 - AF7 +#define PA00_AFx_GPIO() (CW_GPIOA->AFRL_f.AFR0 = 0) +#define PA00_AFx_UART3CTS() (CW_GPIOA->AFRL_f.AFR0 = 1) +#define PA00_AFx_UART2CTS() (CW_GPIOA->AFRL_f.AFR0 = 2) +#define PA00_AFx_RTCTAMP() (CW_GPIOA->AFRL_f.AFR0 = 3) +#define PA00_AFx_VC1OUT() (CW_GPIOA->AFRL_f.AFR0 = 4) +#define PA00_AFx_SPI2MISO() (CW_GPIOA->AFRL_f.AFR0 = 5) +#define PA00_AFx_GTIM2CH1() (CW_GPIOA->AFRL_f.AFR0 = 6) +#define PA00_AFx_GTIM2ETR() (CW_GPIOA->AFRL_f.AFR0 = 7) +#define PA01_AFx_GPIO() (CW_GPIOA->AFRL_f.AFR1 = 0) +#define PA01_AFx_UART3RTS() (CW_GPIOA->AFRL_f.AFR1 = 1) +#define PA01_AFx_UART2RTS() (CW_GPIOA->AFRL_f.AFR1 = 2) +#define PA01_AFx_I2C2SCL() (CW_GPIOA->AFRL_f.AFR1 = 3) +#define PA01_AFx_LVDOUT() (CW_GPIOA->AFRL_f.AFR1 = 4) +#define PA01_AFx_SPI2MOSI() (CW_GPIOA->AFRL_f.AFR1 = 5) +#define PA01_AFx_GTIM2CH2() (CW_GPIOA->AFRL_f.AFR1 = 6) +#define PA01_AFx_RTCTAMP() (CW_GPIOA->AFRL_f.AFR1 = 7) +#define PA02_AFx_GPIO() (CW_GPIOA->AFRL_f.AFR2 = 0) +#define PA02_AFx_UART3TXD() (CW_GPIOA->AFRL_f.AFR2 = 1) +#define PA02_AFx_UART2TXD() (CW_GPIOA->AFRL_f.AFR2 = 2) +#define PA02_AFx_I2C2SDA() (CW_GPIOA->AFRL_f.AFR2 = 3) +#define PA02_AFx_VC2OUT() (CW_GPIOA->AFRL_f.AFR2 = 4) +#define PA02_AFx_SPI2SCK() (CW_GPIOA->AFRL_f.AFR2 = 5) +#define PA02_AFx_GTIM2CH3() (CW_GPIOA->AFRL_f.AFR2 = 6) +#define PA02_AFx_AWTETR() (CW_GPIOA->AFRL_f.AFR2 = 7) +#define PA03_AFx_GPIO() (CW_GPIOA->AFRL_f.AFR3 = 0) +#define PA03_AFx_UART3RXD() (CW_GPIOA->AFRL_f.AFR3 = 1) +#define PA03_AFx_UART2RXD() (CW_GPIOA->AFRL_f.AFR3 = 2) +#define PA03_AFx_GTIM2CH2() (CW_GPIOA->AFRL_f.AFR3 = 3) +#define PA03_AFx_PCLKOUT() (CW_GPIOA->AFRL_f.AFR3 = 4) +#define PA03_AFx_SPI2CS() (CW_GPIOA->AFRL_f.AFR3 = 5) +#define PA03_AFx_GTIM2CH4() (CW_GPIOA->AFRL_f.AFR3 = 6) +#define PA03_AFx_ATIMCH3A() (CW_GPIOA->AFRL_f.AFR3 = 7) +#define PA04_AFx_GPIO() (CW_GPIOA->AFRL_f.AFR4 = 0) +#define PA04_AFx_UART2CTS() (CW_GPIOA->AFRL_f.AFR4 = 2) +#define PA04_AFx_I2C2SCL() (CW_GPIOA->AFRL_f.AFR4 = 3) +#define PA04_AFx_HCLKOUT() (CW_GPIOA->AFRL_f.AFR4 = 4) +#define PA04_AFx_SPI1CS() (CW_GPIOA->AFRL_f.AFR4 = 5) +#define PA04_AFx_GTIM2ETR() (CW_GPIOA->AFRL_f.AFR4 = 6) +#define PA04_AFx_ATIMCH2A() (CW_GPIOA->AFRL_f.AFR4 = 7) +#define PA05_AFx_GPIO() (CW_GPIOA->AFRL_f.AFR5 = 0) +#define PA05_AFx_GTIM2ETR() (CW_GPIOA->AFRL_f.AFR5 = 1) +#define PA05_AFx_UART2RTS() (CW_GPIOA->AFRL_f.AFR5 = 2) +#define PA05_AFx_I2C2SDA() (CW_GPIOA->AFRL_f.AFR5 = 3) +#define PA05_AFx_BTIM2TOGP() (CW_GPIOA->AFRL_f.AFR5 = 4) +#define PA05_AFx_SPI1SCK() (CW_GPIOA->AFRL_f.AFR5 = 5) +#define PA05_AFx_GTIM2CH1() (CW_GPIOA->AFRL_f.AFR5 = 6) +#define PA05_AFx_ATIMCH1A() (CW_GPIOA->AFRL_f.AFR5 = 7) +#define PA06_AFx_GPIO() (CW_GPIOA->AFRL_f.AFR6 = 0) +#define PA06_AFx_GTIM3CH1() (CW_GPIOA->AFRL_f.AFR6 = 1) +#define PA06_AFx_UART2TXD() (CW_GPIOA->AFRL_f.AFR6 = 2) +#define PA06_AFx_VC1OUT() (CW_GPIOA->AFRL_f.AFR6 = 3) +#define PA06_AFx_BTIM2TOGN() (CW_GPIOA->AFRL_f.AFR6 = 4) +#define PA06_AFx_SPI1MISO() (CW_GPIOA->AFRL_f.AFR6 = 5) +#define PA06_AFx_GTIM1CH1() (CW_GPIOA->AFRL_f.AFR6 = 6) +#define PA06_AFx_ATIMBK() (CW_GPIOA->AFRL_f.AFR6 = 7) +#define PA07_AFx_GPIO() (CW_GPIOA->AFRL_f.AFR7 = 0) +#define PA07_AFx_GTIM4CH1() (CW_GPIOA->AFRL_f.AFR7 = 1) +#define PA07_AFx_UART2RXD() (CW_GPIOA->AFRL_f.AFR7 = 2) +#define PA07_AFx_VC2OUT() (CW_GPIOA->AFRL_f.AFR7 = 3) +#define PA07_AFx_BTIM1TOGP() (CW_GPIOA->AFRL_f.AFR7 = 4) +#define PA07_AFx_SPI1MOSI() (CW_GPIOA->AFRL_f.AFR7 = 5) +#define PA07_AFx_GTIM1CH2() (CW_GPIOA->AFRL_f.AFR7 = 6) +#define PA07_AFx_ATIMCH1B() (CW_GPIOA->AFRL_f.AFR7 = 7) +#define PA08_AFx_GPIO() (CW_GPIOA->AFRH_f.AFR8 = 0) +#define PA08_AFx_UART1TXD() (CW_GPIOA->AFRH_f.AFR8 = 2) +#define PA08_AFx_BTIM2TOGN() (CW_GPIOA->AFRH_f.AFR8 = 3) +#define PA08_AFx_MCO() (CW_GPIOA->AFRH_f.AFR8 = 4) +#define PA08_AFx_LVDOUT() (CW_GPIOA->AFRH_f.AFR8 = 5) +#define PA08_AFx_GTIM3ETR() (CW_GPIOA->AFRH_f.AFR8 = 6) +#define PA08_AFx_ATIMCH1A() (CW_GPIOA->AFRH_f.AFR8 = 7) +#define PA09_AFx_GPIO() (CW_GPIOA->AFRH_f.AFR9 = 0) +#define PA09_AFx_UART3TXD() (CW_GPIOA->AFRH_f.AFR9 = 1) +#define PA09_AFx_UART1RXD() (CW_GPIOA->AFRH_f.AFR9 = 2) +#define PA09_AFx_I2C1SCL() (CW_GPIOA->AFRH_f.AFR9 = 3) +#define PA09_AFx_BTIM1TOGP() (CW_GPIOA->AFRH_f.AFR9 = 4) +#define PA09_AFx_SPI1CS() (CW_GPIOA->AFRH_f.AFR9 = 5) +#define PA09_AFx_GTIM3CH1() (CW_GPIOA->AFRH_f.AFR9 = 6) +#define PA09_AFx_ATIMCH2A() (CW_GPIOA->AFRH_f.AFR9 = 7) +#define PA10_AFx_GPIO() (CW_GPIOA->AFRH_f.AFR10 = 0) +#define PA10_AFx_UART3RXD() (CW_GPIOA->AFRH_f.AFR10 = 1) +#define PA10_AFx_UART1CTS() (CW_GPIOA->AFRH_f.AFR10 = 2) +#define PA10_AFx_I2C1SDA() (CW_GPIOA->AFRH_f.AFR10 = 3) +#define PA10_AFx_BTIM1TOGN() (CW_GPIOA->AFRH_f.AFR10 = 4) +#define PA10_AFx_SPI1SCK() (CW_GPIOA->AFRH_f.AFR10 = 5) +#define PA10_AFx_GTIM3CH2() (CW_GPIOA->AFRH_f.AFR10 = 6) +#define PA10_AFx_ATIMCH3A() (CW_GPIOA->AFRH_f.AFR10 = 7) +#define PA11_AFx_GPIO() (CW_GPIOA->AFRH_f.AFR11 = 0) +#define PA11_AFx_UART3CTS() (CW_GPIOA->AFRH_f.AFR11 = 1) +#define PA11_AFx_UART1RTS() (CW_GPIOA->AFRH_f.AFR11 = 2) +#define PA11_AFx_I2C2SCL() (CW_GPIOA->AFRH_f.AFR11 = 3) +#define PA11_AFx_VC1OUT() (CW_GPIOA->AFRH_f.AFR11 = 4) +#define PA11_AFx_SPI1MISO() (CW_GPIOA->AFRH_f.AFR11 = 5) +#define PA11_AFx_GTIM3CH3() (CW_GPIOA->AFRH_f.AFR11 = 6) +#define PA11_AFx_ATIMGATE() (CW_GPIOA->AFRH_f.AFR11 = 7) +#define PA12_AFx_GPIO() (CW_GPIOA->AFRH_f.AFR12 = 0) +#define PA12_AFx_UART3RTS() (CW_GPIOA->AFRH_f.AFR12 = 1) +#define PA12_AFx_BTIMETR() (CW_GPIOA->AFRH_f.AFR12 = 2) +#define PA12_AFx_I2C2SDA() (CW_GPIOA->AFRH_f.AFR12 = 3) +#define PA12_AFx_VC2OUT() (CW_GPIOA->AFRH_f.AFR12 = 4) +#define PA12_AFx_SPI1MOSI() (CW_GPIOA->AFRH_f.AFR12 = 5) +#define PA12_AFx_GTIM3CH4() (CW_GPIOA->AFRH_f.AFR12 = 6) +#define PA12_AFx_ATIMETR() (CW_GPIOA->AFRH_f.AFR12 = 7) +#define PA13_AFx_GPIO() (CW_GPIOA->AFRH_f.AFR13 = 0) +#define PA13_AFx_I2C1SDA() (CW_GPIOA->AFRH_f.AFR13 = 2) +#define PA13_AFx_UART1RXD() (CW_GPIOA->AFRH_f.AFR13 = 3) +#define PA13_AFx_UART2RXD() (CW_GPIOA->AFRH_f.AFR13 = 4) +#define PA13_AFx_I2C2SCL() (CW_GPIOA->AFRH_f.AFR13 = 5) +#define PA13_AFx_IROUT() (CW_GPIOA->AFRH_f.AFR13 = 6) +#define PA14_AFx_GPIO() (CW_GPIOA->AFRH_f.AFR14 = 0) +#define PA14_AFx_UART3TXD() (CW_GPIOA->AFRH_f.AFR14 = 1) +#define PA14_AFx_I2C1SCL() (CW_GPIOA->AFRH_f.AFR14 = 2) +#define PA14_AFx_UART1TXD() (CW_GPIOA->AFRH_f.AFR14 = 3) +#define PA14_AFx_UART2TXD() (CW_GPIOA->AFRH_f.AFR14 = 4) +#define PA14_AFx_I2C2SDA() (CW_GPIOA->AFRH_f.AFR14 = 5) +#define PA15_AFx_GPIO() (CW_GPIOA->AFRH_f.AFR15 = 0) +#define PA15_AFx_UART3RXD() (CW_GPIOA->AFRH_f.AFR15 = 1) +#define PA15_AFx_GTIM2CH1() (CW_GPIOA->AFRH_f.AFR15 = 2) +#define PA15_AFx_UART1RXD() (CW_GPIOA->AFRH_f.AFR15 = 3) +#define PA15_AFx_UART2RXD() (CW_GPIOA->AFRH_f.AFR15 = 4) +#define PA15_AFx_SPI1CS() (CW_GPIOA->AFRH_f.AFR15 = 5) +#define PA15_AFx_GTIM2ETR() (CW_GPIOA->AFRH_f.AFR15 = 6) +#define PA15_AFx_ATIMCH1B() (CW_GPIOA->AFRH_f.AFR15 = 7) +#define PB00_AFx_GPIO() (CW_GPIOB->AFRL_f.AFR0 = 0) +#define PB00_AFx_UART2RXD() (CW_GPIOB->AFRL_f.AFR0 = 1) +#define PB00_AFx_UART1CTS() (CW_GPIOB->AFRL_f.AFR0 = 2) +#define PB00_AFx_I2C2SCL() (CW_GPIOB->AFRL_f.AFR0 = 3) +#define PB00_AFx_BTIM1TOGN() (CW_GPIOB->AFRL_f.AFR0 = 4) +#define PB00_AFx_HSIOUT() (CW_GPIOB->AFRL_f.AFR0 = 5) +#define PB00_AFx_GTIM1CH3() (CW_GPIOB->AFRL_f.AFR0 = 6) +#define PB00_AFx_ATIMCH2B() (CW_GPIOB->AFRL_f.AFR0 = 7) +#define PB01_AFx_GPIO() (CW_GPIOB->AFRL_f.AFR1 = 0) +#define PB01_AFx_UART2TXD() (CW_GPIOB->AFRL_f.AFR1 = 1) +#define PB01_AFx_UART1RTS() (CW_GPIOB->AFRL_f.AFR1 = 2) +#define PB01_AFx_I2C2SDA() (CW_GPIOB->AFRL_f.AFR1 = 3) +#define PB01_AFx_GTIM4TOGN() (CW_GPIOB->AFRL_f.AFR1 = 4) +#define PB01_AFx_BTIM3TOGP() (CW_GPIOB->AFRL_f.AFR1 = 5) +#define PB01_AFx_GTIM1CH4() (CW_GPIOB->AFRL_f.AFR1 = 6) +#define PB01_AFx_ATIMCH3B() (CW_GPIOB->AFRL_f.AFR1 = 7) +#define PB02_AFx_GPIO() (CW_GPIOB->AFRL_f.AFR2 = 0) +#define PB02_AFx_UART2CTS() (CW_GPIOB->AFRL_f.AFR2 = 1) +#define PB02_AFx_UART1TXD() (CW_GPIOB->AFRL_f.AFR2 = 2) +#define PB02_AFx_HSEOUT() (CW_GPIOB->AFRL_f.AFR2 = 3) +#define PB02_AFx_GTIM4TOGP() (CW_GPIOB->AFRL_f.AFR2 = 4) +#define PB02_AFx_BTIM3TOGN() (CW_GPIOB->AFRL_f.AFR2 = 5) +#define PB02_AFx_GTIM1ETR() (CW_GPIOB->AFRL_f.AFR2 = 6) +#define PB02_AFx_ATIMCH1A() (CW_GPIOB->AFRL_f.AFR2 = 7) +#define PB03_AFx_GPIO() (CW_GPIOB->AFRL_f.AFR3 = 0) +#define PB03_AFx_UART3RTS() (CW_GPIOB->AFRL_f.AFR3 = 1) +#define PB03_AFx_GTIM2CH2() (CW_GPIOB->AFRL_f.AFR3 = 2) +#define PB03_AFx_UART1CTS() (CW_GPIOB->AFRL_f.AFR3 = 3) +#define PB03_AFx_UART2TXD() (CW_GPIOB->AFRL_f.AFR3 = 4) +#define PB03_AFx_SPI1SCK() (CW_GPIOB->AFRL_f.AFR3 = 5) +#define PB03_AFx_GTIM1ETR() (CW_GPIOB->AFRL_f.AFR3 = 6) +#define PB03_AFx_ATIMCH2B() (CW_GPIOB->AFRL_f.AFR3 = 7) +#define PB04_AFx_GPIO() (CW_GPIOB->AFRL_f.AFR4 = 0) +#define PB04_AFx_UART3CTS() (CW_GPIOB->AFRL_f.AFR4 = 1) +#define PB04_AFx_GTIM4ETR() (CW_GPIOB->AFRL_f.AFR4 = 2) +#define PB04_AFx_UART1RTS() (CW_GPIOB->AFRL_f.AFR4 = 3) +#define PB04_AFx_UART2CTS() (CW_GPIOB->AFRL_f.AFR4 = 4) +#define PB04_AFx_SPI1MISO() (CW_GPIOB->AFRL_f.AFR4 = 5) +#define PB04_AFx_GTIM1CH1() (CW_GPIOB->AFRL_f.AFR4 = 6) +#define PB04_AFx_ATIMCH3B() (CW_GPIOB->AFRL_f.AFR4 = 7) +#define PB05_AFx_GPIO() (CW_GPIOB->AFRL_f.AFR5 = 0) +#define PB05_AFx_GTIM3CH4() (CW_GPIOB->AFRL_f.AFR5 = 2) +#define PB05_AFx_AWTETR() (CW_GPIOB->AFRL_f.AFR5 = 3) +#define PB05_AFx_UART2RTS() (CW_GPIOB->AFRL_f.AFR5 = 4) +#define PB05_AFx_SPI1MOSI() (CW_GPIOB->AFRL_f.AFR5 = 5) +#define PB05_AFx_GTIM1CH2() (CW_GPIOB->AFRL_f.AFR5 = 6) +#define PB05_AFx_ATIMCH1A() (CW_GPIOB->AFRL_f.AFR5 = 7) +#define PB06_AFx_GPIO() (CW_GPIOB->AFRL_f.AFR6 = 0) +#define PB06_AFx_UART3TXD() (CW_GPIOB->AFRL_f.AFR6 = 1) +#define PB06_AFx_GTIM3CH3() (CW_GPIOB->AFRL_f.AFR6 = 2) +#define PB06_AFx_I2C1SCL() (CW_GPIOB->AFRL_f.AFR6 = 3) +#define PB06_AFx_GTIM4CH4() (CW_GPIOB->AFRL_f.AFR6 = 4) +#define PB06_AFx_SPI2MOSI() (CW_GPIOB->AFRL_f.AFR6 = 5) +#define PB06_AFx_GTIM1TOGN() (CW_GPIOB->AFRL_f.AFR6 = 6) +#define PB06_AFx_ATIMCH2A() (CW_GPIOB->AFRL_f.AFR6 = 7) +#define PB07_AFx_GPIO() (CW_GPIOB->AFRL_f.AFR7 = 0) +#define PB07_AFx_UART3RXD() (CW_GPIOB->AFRL_f.AFR7 = 1) +#define PB07_AFx_GTIM3CH2() (CW_GPIOB->AFRL_f.AFR7 = 2) +#define PB07_AFx_I2C1SDA() (CW_GPIOB->AFRL_f.AFR7 = 3) +#define PB07_AFx_GTIM4CH3() (CW_GPIOB->AFRL_f.AFR7 = 4) +#define PB07_AFx_SPI2MISO() (CW_GPIOB->AFRL_f.AFR7 = 5) +#define PB07_AFx_GTIM1TOGP() (CW_GPIOB->AFRL_f.AFR7 = 6) +#define PB07_AFx_ATIMCH3A() (CW_GPIOB->AFRL_f.AFR7 = 7) +#define PB08_AFx_GPIO() (CW_GPIOB->AFRH_f.AFR8 = 0) +#define PB08_AFx_I2C1SCL() (CW_GPIOB->AFRH_f.AFR8 = 1) +#define PB08_AFx_GTIM3CH1() (CW_GPIOB->AFRH_f.AFR8 = 2) +#define PB08_AFx_UART1TXD() (CW_GPIOB->AFRH_f.AFR8 = 3) +#define PB08_AFx_GTIM4CH2() (CW_GPIOB->AFRH_f.AFR8 = 4) +#define PB08_AFx_SPI2SCK() (CW_GPIOB->AFRH_f.AFR8 = 5) +#define PB08_AFx_GTIM1CH3() (CW_GPIOB->AFRH_f.AFR8 = 6) +#define PB08_AFx_ATIMETR() (CW_GPIOB->AFRH_f.AFR8 = 7) +#define PB09_AFx_GPIO() (CW_GPIOB->AFRH_f.AFR9 = 0) +#define PB09_AFx_I2C1SDA() (CW_GPIOB->AFRH_f.AFR9 = 1) +#define PB09_AFx_GTIM4CH1() (CW_GPIOB->AFRH_f.AFR9 = 2) +#define PB09_AFx_UART1RXD() (CW_GPIOB->AFRH_f.AFR9 = 3) +#define PB09_AFx_IROUT() (CW_GPIOB->AFRH_f.AFR9 = 4) +#define PB09_AFx_SPI2CS() (CW_GPIOB->AFRH_f.AFR9 = 5) +#define PB09_AFx_GTIM1CH4() (CW_GPIOB->AFRH_f.AFR9 = 6) +#define PB09_AFx_ATIMBK() (CW_GPIOB->AFRH_f.AFR9 = 7) +#define PB10_AFx_GPIO() (CW_GPIOB->AFRH_f.AFR10 = 0) +#define PB10_AFx_UART2RTS() (CW_GPIOB->AFRH_f.AFR10 = 1) +#define PB10_AFx_UART1RXD() (CW_GPIOB->AFRH_f.AFR10 = 2) +#define PB10_AFx_I2C1SCL() (CW_GPIOB->AFRH_f.AFR10 = 3) +#define PB10_AFx_I2C2SCL() (CW_GPIOB->AFRH_f.AFR10 = 4) +#define PB10_AFx_SPI2SCK() (CW_GPIOB->AFRH_f.AFR10 = 5) +#define PB10_AFx_GTIM2CH3() (CW_GPIOB->AFRH_f.AFR10 = 6) +#define PB10_AFx_ATIMCH2A() (CW_GPIOB->AFRH_f.AFR10 = 7) +#define PB11_AFx_GPIO() (CW_GPIOB->AFRH_f.AFR11 = 0) +#define PB11_AFx_LSIOUT() (CW_GPIOB->AFRH_f.AFR11 = 1) +#define PB11_AFx_GTIM4ETR() (CW_GPIOB->AFRH_f.AFR11 = 2) +#define PB11_AFx_I2C1SDA() (CW_GPIOB->AFRH_f.AFR11 = 3) +#define PB11_AFx_I2C2SDA() (CW_GPIOB->AFRH_f.AFR11 = 4) +#define PB11_AFx_BTIMETR() (CW_GPIOB->AFRH_f.AFR11 = 5) +#define PB11_AFx_GTIM2CH4() (CW_GPIOB->AFRH_f.AFR11 = 6) +#define PB11_AFx_ATIMCH3A() (CW_GPIOB->AFRH_f.AFR11 = 7) +#define PB12_AFx_GPIO() (CW_GPIOB->AFRH_f.AFR12 = 0) +#define PB12_AFx_GTIM2TOGN() (CW_GPIOB->AFRH_f.AFR12 = 1) +#define PB12_AFx_GTIM4CH4() (CW_GPIOB->AFRH_f.AFR12 = 2) +#define PB12_AFx_LSEOUT() (CW_GPIOB->AFRH_f.AFR12 = 3) +#define PB12_AFx_SPI2CS() (CW_GPIOB->AFRH_f.AFR12 = 4) +#define PB12_AFx_SPI1CS() (CW_GPIOB->AFRH_f.AFR12 = 5) +#define PB12_AFx_GTIM1TOGN() (CW_GPIOB->AFRH_f.AFR12 = 6) +#define PB12_AFx_ATIMBK() (CW_GPIOB->AFRH_f.AFR12 = 7) +#define PB13_AFx_GPIO() (CW_GPIOB->AFRH_f.AFR13 = 0) +#define PB13_AFx_GTIM2TOGP() (CW_GPIOB->AFRH_f.AFR13 = 1) +#define PB13_AFx_GTIM4CH3() (CW_GPIOB->AFRH_f.AFR13 = 2) +#define PB13_AFx_I2C2SCL() (CW_GPIOB->AFRH_f.AFR13 = 3) +#define PB13_AFx_SPI2SCK() (CW_GPIOB->AFRH_f.AFR13 = 4) +#define PB13_AFx_SPI1SCK() (CW_GPIOB->AFRH_f.AFR13 = 5) +#define PB13_AFx_GTIM1TOGP() (CW_GPIOB->AFRH_f.AFR13 = 6) +#define PB13_AFx_ATIMCH1B() (CW_GPIOB->AFRH_f.AFR13 = 7) +#define PB14_AFx_GPIO() (CW_GPIOB->AFRH_f.AFR14 = 0) +#define PB14_AFx_GTIM2CH1() (CW_GPIOB->AFRH_f.AFR14 = 1) +#define PB14_AFx_GTIM4CH2() (CW_GPIOB->AFRH_f.AFR14 = 2) +#define PB14_AFx_I2C2SDA() (CW_GPIOB->AFRH_f.AFR14 = 3) +#define PB14_AFx_SPI2MISO() (CW_GPIOB->AFRH_f.AFR14 = 4) +#define PB14_AFx_SPI1MISO() (CW_GPIOB->AFRH_f.AFR14 = 5) +#define PB14_AFx_RTCOUT() (CW_GPIOB->AFRH_f.AFR14 = 6) +#define PB14_AFx_ATIMCH2B() (CW_GPIOB->AFRH_f.AFR14 = 7) +#define PB15_AFx_GPIO() (CW_GPIOB->AFRH_f.AFR15 = 0) +#define PB15_AFx_GTIM2CH2() (CW_GPIOB->AFRH_f.AFR15 = 1) +#define PB15_AFx_GTIM4CH1() (CW_GPIOB->AFRH_f.AFR15 = 2) +#define PB15_AFx_BTIM2TOGP() (CW_GPIOB->AFRH_f.AFR15 = 3) +#define PB15_AFx_SPI2MOSI() (CW_GPIOB->AFRH_f.AFR15 = 4) +#define PB15_AFx_SPI1MOSI() (CW_GPIOB->AFRH_f.AFR15 = 5) +#define PB15_AFx_RTC1Hz() (CW_GPIOB->AFRH_f.AFR15 = 6) +#define PB15_AFx_ATIMCH3B() (CW_GPIOB->AFRH_f.AFR15 = 7) +#define PC13_AFx_GPIO() (CW_GPIOC->AFRH_f.AFR13 = 0) +#define PC13_AFx_PLLOUT() (CW_GPIOC->AFRH_f.AFR13 = 1) +#define PC13_AFx_RTC1Hz() (CW_GPIOC->AFRH_f.AFR13 = 2) +#define PC13_AFx_UART1CTS() (CW_GPIOC->AFRH_f.AFR13 = 3) +#define PC13_AFx_RTCOUT() (CW_GPIOC->AFRH_f.AFR13 = 4) +#define PC13_AFx_BTIMETR() (CW_GPIOC->AFRH_f.AFR13 = 5) +#define PC13_AFx_GTIM3ETR() (CW_GPIOC->AFRH_f.AFR13 = 6) +#define PC13_AFx_RTCTAMP() (CW_GPIOC->AFRH_f.AFR13 = 7) +#define PC14_AFx_GPIO() (CW_GPIOC->AFRH_f.AFR14 = 0) +#define PC14_AFx_AWTETR() (CW_GPIOC->AFRH_f.AFR14 = 1) +#define PC14_AFx_GTIM4CH4() (CW_GPIOC->AFRH_f.AFR14 = 2) +#define PC14_AFx_UART1RTS() (CW_GPIOC->AFRH_f.AFR14 = 3) +#define PC14_AFx_BTIM2TOGP() (CW_GPIOC->AFRH_f.AFR14 = 4) +#define PC14_AFx_SPI2MISO() (CW_GPIOC->AFRH_f.AFR14 = 5) +#define PC14_AFx_GTIM3TOGN() (CW_GPIOC->AFRH_f.AFR14 = 6) +#define PC14_AFx_GTIM3CH1() (CW_GPIOC->AFRH_f.AFR14 = 7) +#define PC15_AFx_GPIO() (CW_GPIOC->AFRH_f.AFR15 = 0) +#define PC15_AFx_HSEOUT() (CW_GPIOC->AFRH_f.AFR15 = 1) +#define PC15_AFx_GTIM4CH3() (CW_GPIOC->AFRH_f.AFR15 = 2) +#define PC15_AFx_GTIM4ETR() (CW_GPIOC->AFRH_f.AFR15 = 3) +#define PC15_AFx_BTIM2TOGN() (CW_GPIOC->AFRH_f.AFR15 = 4) +#define PC15_AFx_SPI2MOSI() (CW_GPIOC->AFRH_f.AFR15 = 5) +#define PC15_AFx_GTIM3TOGP() (CW_GPIOC->AFRH_f.AFR15 = 6) +#define PC15_AFx_GTIM3CH2() (CW_GPIOC->AFRH_f.AFR15 = 7) +#define PF00_AFx_GPIO() (CW_GPIOF->AFRL_f.AFR0 = 0) +#define PF00_AFx_AWTETR() (CW_GPIOF->AFRL_f.AFR0 = 1) +#define PF00_AFx_GTIM4CH2() (CW_GPIOF->AFRL_f.AFR0 = 2) +#define PF00_AFx_I2C1SDA() (CW_GPIOF->AFRL_f.AFR0 = 3) +#define PF00_AFx_BTIM1TOGP() (CW_GPIOF->AFRL_f.AFR0 = 4) +#define PF00_AFx_SPI2SCK() (CW_GPIOF->AFRL_f.AFR0 = 5) +#define PF00_AFx_GTIM2TOGN() (CW_GPIOF->AFRL_f.AFR0 = 6) +#define PF00_AFx_GTIM3CH3() (CW_GPIOF->AFRL_f.AFR0 = 7) +#define PF01_AFx_GPIO() (CW_GPIOF->AFRL_f.AFR1 = 0) +#define PF01_AFx_LSEOUT() (CW_GPIOF->AFRL_f.AFR1 = 1) +#define PF01_AFx_GTIM4CH1() (CW_GPIOF->AFRL_f.AFR1 = 2) +#define PF01_AFx_I2C1SCL() (CW_GPIOF->AFRL_f.AFR1 = 3) +#define PF01_AFx_BTIM1TOGN() (CW_GPIOF->AFRL_f.AFR1 = 4) +#define PF01_AFx_SPI2CS() (CW_GPIOF->AFRL_f.AFR1 = 5) +#define PF01_AFx_GTIM2TOGP() (CW_GPIOF->AFRL_f.AFR1 = 6) +#define PF01_AFx_GTIM3CH4() (CW_GPIOF->AFRL_f.AFR1 = 7) +#define PF06_AFx_GPIO() (CW_GPIOF->AFRL_f.AFR6 = 0) +#define PF06_AFx_UART3CTS() (CW_GPIOF->AFRL_f.AFR6 = 1) +#define PF06_AFx_I2C1SCL() (CW_GPIOF->AFRL_f.AFR6 = 2) +#define PF06_AFx_GTIM4TOGN() (CW_GPIOF->AFRL_f.AFR6 = 3) +#define PF06_AFx_UART2CTS() (CW_GPIOF->AFRL_f.AFR6 = 4) +#define PF06_AFx_I2C2SCL() (CW_GPIOF->AFRL_f.AFR6 = 5) +#define PF06_AFx_GTIM3TOGN() (CW_GPIOF->AFRL_f.AFR6 = 6) +#define PF06_AFx_BTIM3TOGP() (CW_GPIOF->AFRL_f.AFR6 = 7) +#define PF07_AFx_GPIO() (CW_GPIOF->AFRL_f.AFR7 = 0) +#define PF07_AFx_UART3RTS() (CW_GPIOF->AFRL_f.AFR7 = 1) +#define PF07_AFx_I2C1SDA() (CW_GPIOF->AFRL_f.AFR7 = 2) +#define PF07_AFx_GTIM4TOGP() (CW_GPIOF->AFRL_f.AFR7 = 3) +#define PF07_AFx_UART2RTS() (CW_GPIOF->AFRL_f.AFR7 = 4) +#define PF07_AFx_I2C2SDA() (CW_GPIOF->AFRL_f.AFR7 = 5) +#define PF07_AFx_GTIM3TOGP() (CW_GPIOF->AFRL_f.AFR7 = 6) +#define PF07_AFx_BTIM3TOGN() (CW_GPIOF->AFRL_f.AFR7 = 7) +#define PF03_AFx_GPIO() (CW_GPIOF->AFRL_f.AFR3 = 0) + +//============================================================ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_gtim.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_gtim.h new file mode 100644 index 0000000..a3dbe34 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_gtim.h @@ -0,0 +1,333 @@ +/** + * @file cw32f030_gtim.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-04-26 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_GTIM_H +#define __CW32F030_GTIM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" + +/****************************************************************************** + * type definitions ('typedef') + ******************************************************************************/ + +/** + * @brief GTIM 基础初始化参数 + */ +typedef struct +{ + uint32_t Mode; /*!< GTIM的模式选择。 */ + uint32_t OneShotMode; /*!< GTIM的单次/连续计数模式选择。 */ + FunctionalState ToggleOutState; /*!< GTIM的翻转输出使能选择。 */ + uint32_t Prescaler; /*!< GTIM的预分频系数。 */ + uint32_t ReloadValue; /*!< GTIM的重载值。 */ +} GTIM_InitTypeDef; + +/** + * @brief GTIM 编码器模式下的初始化参数 + */ + +typedef struct +{ + uint32_t EncodeMode; + uint32_t EncodeResetMode; + uint32_t EncodeReloadMode; + uint32_t CH1Filter; + uint32_t CH2Filter; + uint32_t CH3Filter; + uint32_t CH1Invert; + uint32_t CH2Invert; + uint32_t CH3Invert; +} GTIM_EncodeInitTypeDef; + +/** + * @brief GTIM 输入捕获的配置参数 + */ +typedef struct +{ + uint32_t CHx; + uint32_t ICPolarity; + uint32_t ICFilter; + uint32_t ICInvert; +} GTIM_ICInitTypeDef; + +/****************************************************************************** + * pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_GTIM_DEFINE(GTIMx) (((GTIMx) == CW_GTIM1) || \ + ((GTIMx) == CW_GTIM2) || \ + ((GTIMx) == CW_GTIM3) || \ + ((GTIMx) == CW_GTIM4)) + + +#define GTIM_MODE_TIME (0UL) +#define GTIM_MODE_COUNTER (1UL << 1) +#define GTIM_MODE_TRIGGER (2UL << 1) +#define GTIM_MODE_GATE (3UL << 1) +#define IS_GTIM_MODE(MODE) (((MODE) == GTIM_MODE_TIME) || \ + ((MODE) == GTIM_MODE_COUNTER) || \ + ((MODE) == GTIM_MODE_TRIGGER) || \ + ((MODE) == GTIM_MODE_GATE)) + +#define GTIM_TRIGGER_ETR (0UL) +#define GTIM_TRIGGER_ITR (1UL <<3) +#define IS_GTIM_TRS(MODE) (((MODE) == GTIM_TRIGGER_ETR) || \ + ((MODE) == GTIM_TRIGGER_ITR)) + +#define ITR_SOURCE_BTIM1 (0UL) +#define ITR_SOURCE_BTIM2 (1UL) +#define ITR_SOURCE_BTIM3 (2UL) +#define ITR_SOURCE_GTIM1 (3UL) +#define ITR_SOURCE_GTIM2 (4UL) +#define ITR_SOURCE_GTIM3 (5UL) +#define ITR_SOURCE_GTIM4 (6UL) +#define ITR_SOURCE_ATIM (7UL) +#define IS_ITR_SOURCE(ITR) (((ITR) == ITR_SOURCE_BTIM1) || \ + ((ITR) == ITR_SOURCE_BTIM2) || \ + ((ITR) == ITR_SOURCE_BTIM3) || \ + ((ITR) == ITR_SOURCE_GTIM1) || \ + ((ITR) == ITR_SOURCE_GTIM2) || \ + ((ITR) == ITR_SOURCE_GTIM3) || \ + ((ITR) == ITR_SOURCE_GTIM4) || \ + ((ITR) == ITR_SOURCE_ATIM)) + +#define GTIM_ETR_POL_RISE_HIGH (0UL) +#define GTIM_ETR_POL_FALL_LOW (1UL << 4) +#define IS_GTIM_ETR_POL(MODE) (((MODE) == GTIM_ETR_POL_RISE_HIGH) || \ + ((MODE) == GTIM_ETR_POL_FALL_LOW)) + +#define GTIM_COUNT_CONTINUE (0UL) +#define GTIM_COUNT_ONESHOT (1UL << 5) +#define IS_GTIM_ONESHOT(MODE) (((MODE) == GTIM_COUNT_CONTINUE) || \ + ((MODE) == GTIM_COUNT_ONESHOT)) + +#define GTIM_PRESCALER_DIV1 (0UL) +#define GTIM_PRESCALER_DIV2 (1UL << 7) +#define GTIM_PRESCALER_DIV4 (2UL << 7) +#define GTIM_PRESCALER_DIV8 (3UL << 7) +#define GTIM_PRESCALER_DIV16 (4UL << 7) +#define GTIM_PRESCALER_DIV32 (5UL << 7) +#define GTIM_PRESCALER_DIV64 (6UL << 7) +#define GTIM_PRESCALER_DIV128 (7UL << 7) +#define GTIM_PRESCALER_DIV256 (8UL << 7) +#define GTIM_PRESCALER_DIV512 (9UL << 7) +#define GTIM_PRESCALER_DIV1024 (10UL << 7) +#define GTIM_PRESCALER_DIV2048 (11UL << 7) +#define GTIM_PRESCALER_DIV4096 (12UL << 7) +#define GTIM_PRESCALER_DIV8192 (13UL << 7) +#define GTIM_PRESCALER_DIV16384 (14UL << 7) +#define GTIM_PRESCALER_DIV32768 (15UL << 7) +#define IS_GTIM_PRESCALER(DIV) (((DIV) == GTIM_PRESCALER_DIV1) || \ + ((DIV) == GTIM_PRESCALER_DIV2) || \ + ((DIV) == GTIM_PRESCALER_DIV4) || \ + ((DIV) == GTIM_PRESCALER_DIV8) || \ + ((DIV) == GTIM_PRESCALER_DIV16) || \ + ((DIV) == GTIM_PRESCALER_DIV32) || \ + ((DIV) == GTIM_PRESCALER_DIV64) || \ + ((DIV) == GTIM_PRESCALER_DIV128) || \ + ((DIV) == GTIM_PRESCALER_DIV256) || \ + ((DIV) == GTIM_PRESCALER_DIV512) || \ + ((DIV) == GTIM_PRESCALER_DIV1024) || \ + ((DIV) == GTIM_PRESCALER_DIV2048) || \ + ((DIV) == GTIM_PRESCALER_DIV4096) || \ + ((DIV) == GTIM_PRESCALER_DIV8192) || \ + ((DIV) == GTIM_PRESCALER_DIV16384) || \ + ((DIV) == GTIM_PRESCALER_DIV32768)) + +#define GTIM_ENCODE_MODE0 (0UL) +#define GTIM_ENCODE_MODE1 (1UL << 15) +#define GTIM_ENCODE_MODE2 (2UL << 15) +#define GTIM_ENCODE_MODE3 (3UL << 15) +#define IS_GTIM_ENCODE_MODE(MODE) (((MODE) == GTIM_ENCODE_MODE0) || \ + ((MODE) == GTIM_ENCODE_MODE1) || \ + ((MODE) == GTIM_ENCODE_MODE2) || \ + ((MODE) == GTIM_ENCODE_MODE3)) + +#define GTIM_ENCODE_RESET_NONE (0UL) +#define GTIM_ENCODE_RESET_RISE (1UL << 17) +#define GTIM_ENCODE_RESET_FALL (2UL << 17) +#define IS_GTIM_ENCODE_RESET(MODE) (((MODE) == GTIM_ENCODE_RESET_NONE) || \ + ((MODE) == GTIM_ENCODE_RESET_RISE) || \ + ((MODE) == GTIM_ENCODE_RESET_FALL)) + +#define GTIM_ENCODE_RELOAD_NONE (0UL) +#define GTIM_ENCODE_RELOAD_RISE (1UL << 19) +#define GTIM_ENCODE_RELOAD_FALL (2UL << 19) +#define IS_GTIM_ENCODE_RELOAD(MODE) (((MODE) == GTIM_ENCODE_RELOAD_NONE) || \ + ((MODE) == GTIM_ENCODE_RELOAD_RISE) || \ + ((MODE) == GTIM_ENCODE_RELOAD_FALL)) + +#define GTIM_CHx_FILTER_NONE (0UL) +#define GTIM_CHx_FILTER_PCLK_N2 (1UL) +#define GTIM_CHx_FILTER_PCLK_N4 (2UL) +#define GTIM_CHx_FILTER_PCLK_N6 (3UL) +#define GTIM_CHx_FILTER_PCLKDIV4_N4 (4UL) +#define GTIM_CHx_FILTER_PCLKDIV4_N6 (5UL) +#define GTIM_CHx_FILTER_PCLKDIV8_N4 (6UL) +#define GTIM_CHx_FILTER_PCLKDIV8_N6 (7UL) +#define IS_GTIM_CHx_FILTER(MODE) (((MODE) == GTIM_CHx_FILTER_NONE) || \ + ((MODE) == GTIM_CHx_FILTER_PCLK_N2) || \ + ((MODE) == GTIM_CHx_FILTER_PCLK_N4) || \ + ((MODE) == GTIM_CHx_FILTER_PCLK_N6) || \ + ((MODE) == GTIM_CHx_FILTER_PCLKDIV4_N4) || \ + ((MODE) == GTIM_CHx_FILTER_PCLKDIV4_N6) || \ + ((MODE) == GTIM_CHx_FILTER_PCLKDIV8_N4) || \ + ((MODE) == GTIM_CHx_FILTER_PCLKDIV8_N6)) + +#define GTIM_CHx_INVERT_OFF (1UL) +#define GTIM_CHx_INVERT_ON (0UL) +#define IS_GTIM_CHx_INVERT(VAL) (((VAL) == GTIM_CHx_INVERT_OFF) || \ + ((VAL) == GTIM_CHx_INVERT_ON)) + +#define GTIM_ETR_FILTER_NONE (0UL) +#define GTIM_ETR_FILTER_PCLK_N2 (1UL << 4) +#define GTIM_ETR_FILTER_PCLK_N4 (2UL << 4) +#define GTIM_ETR_FILTER_PCLK_N6 (3UL << 4) +#define GTIM_ETR_FILTER_PCLKDIV4_N4 (4UL << 4) +#define GTIM_ETR_FILTER_PCLKDIV4_N6 (5UL << 4) +#define GTIM_ETR_FILTER_PCLKDIV8_N4 (6UL << 4) +#define GTIM_ETR_FILTER_PCLKDIV8_N6 (7UL << 4) +#define IS_GTIM_ETR_FILTER(MODE) (((MODE) == GTIM_ETR_FILTER_NONE) || \ + ((MODE) == GTIM_ETR_FILTER_PCLK_N2) || \ + ((MODE) == GTIM_ETR_FILTER_PCLK_N4) || \ + ((MODE) == GTIM_ETR_FILTER_PCLK_N6) || \ + ((MODE) == GTIM_ETR_FILTER_PCLKDIV4_N4) || \ + ((MODE) == GTIM_ETR_FILTER_PCLKDIV4_N6) || \ + ((MODE) == GTIM_ETR_FILTER_PCLKDIV8_N4) || \ + ((MODE) == GTIM_ETR_FILTER_PCLKDIV8_N6)) + + +#define GTIM_ICPolarity_Rising (1UL) +#define GTIM_ICPolarity_Falling (2UL) +#define GTIM_ICPolarity_BothEdge (3UL) +#define IS_GTIM_ICPolarity(MODE) (((MODE) == GTIM_ICPolarity_Rising) || \ + ((MODE) == GTIM_ICPolarity_Falling) || \ + ((MODE) == GTIM_ICPolarity_BothEdge)) + +#define GTIM_OC_OUTPUT_FORCE_LOW (8UL) +#define GTIM_OC_OUTPUT_FORCE_HIGH (9UL) +#define GTIM_OC_OUTPUT_MATCH_LOW (10UL) +#define GTIM_OC_OUTPUT_MATCH_HIGH (11UL) +#define GTIM_OC_OUTPUT_MATHC_TOGGLE (13UL) +#define GTIM_OC_OUTPUT_PWM_HIGH (14UL) +#define GTIM_OC_OUTPUT_PWM_LOW (15UL) +#define IS_GTIM_OC_OUTPUT(MODE) (((MODE) == GTIM_OC_OUTPUT_FORCE_LOW) || \ + ((MODE) == GTIM_OC_OUTPUT_FORCE_HIGH) || \ + ((MODE) == GTIM_OC_OUTPUT_MATCH_LOW) || \ + ((MODE) == GTIM_OC_OUTPUT_MATCH_HIGH) || \ + ((MODE) == GTIM_OC_OUTPUT_MATHC_TOGGLE) || \ + ((MODE) == GTIM_OC_OUTPUT_PWM_HIGH) || \ + ((MODE) == GTIM_OC_OUTPUT_PWM_LOW)) + +#define GTIM_CHANNEL1 (0UL) +#define GTIM_CHANNEL2 (4UL) +#define GTIM_CHANNEL3 (8UL) +#define GTIM_CHANNEL4 (12UL) +#define IS_GTIM_CHANNEL(CHANNEL) (((CHANNEL) == GTIM_CHANNEL1) || \ + ((CHANNEL) == GTIM_CHANNEL2) || \ + ((CHANNEL) == GTIM_CHANNEL3) || \ + ((CHANNEL) == GTIM_CHANNEL4)) + +#define GTIM_IT_OV (1UL) +#define GTIM_IT_TI (1UL<<1) +#define GTIM_IT_UD (1UL<<2) +#define GTIM_IT_CC1 (1UL<<3) +#define GTIM_IT_CC2 (1UL<<4) +#define GTIM_IT_CC3 (1UL<<5) +#define GTIM_IT_CC4 (1UL<<6) +#define GTIM_IT_DIRCHANGE (1UL<<9) +#define IS_GTIM_IT(IT) ((((IT) & 0xFFFFFD80) == 0x0UL) && ((IT) != 0x0UL)) +#define IS_GTIM_GET_IT(IT) (((IT) == GTIM_IT_OV) || \ + ((IT) == GTIM_IT_TI) || \ + ((IT) == GTIM_IT_UD) || \ + ((IT) == GTIM_IT_CC1) || \ + ((IT) == GTIM_IT_CC2) || \ + ((IT) == GTIM_IT_CC3) || \ + ((IT) == GTIM_IT_CC4) || \ + ((IT) == GTIM_IT_DIRCHANGE)) + +#define GTIM_DMA_OV (1UL) +#define GTIM_DMA_TRS (1UL<<1) +#define GTIM_DMA_CC1 (1UL<<2) +#define GTIM_DMA_CC2 (1UL<<3) +#define GTIM_DMA_CC3 (1UL<<4) +#define GTIM_DMA_CC4 (1UL<<5) +#define IS_GTIM_DMA(DMA) ((((DMA) & 0xFFFFFFC0) == 0x0UL) && (DMA) != 0x0UL) + + +/****************************************************************************** +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ + + +/****************************************************************************** +* Global function prototypes +******************************************************************************/ +void GTIM1_DeInit(void); +void GTIM2_DeInit(void); +void GTIM3_DeInit(void); +void GTIM4_DeInit(void); +void GTIM_TimeBaseInit(GTIM_TypeDef *GTIMx, GTIM_InitTypeDef *GTIM_InitStruct); + +void GTIM_EncodeInit(GTIM_TypeDef *GTIMx, GTIM_EncodeInitTypeDef *GTIM_EncodeInitStruct); +void GTIM_OCInit(GTIM_TypeDef *GTIMx, uint32_t CHx, uint32_t OCMode); +void GTIM_ICInit(GTIM_TypeDef *GTIMx, GTIM_ICInitTypeDef *GTIM_ICInitStruct); +void GTIM_Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState); + +void GTIM_ETRConfig(GTIM_TypeDef *GTIMx, uint32_t ETRPolarity, uint32_t ETRFilter); +void GTIM_ICChannelConfig(GTIM_TypeDef *GTIMx, uint32_t CHx, uint32_t CHxFilter, uint32_t CHxInvert); +void GTIM_SetPrescaler(GTIM_TypeDef *GTIMx, uint32_t GTIMPrescaler); +void GTIM_SetReloadValue(GTIM_TypeDef *GTIMx, uint32_t ReloadValue); +void GTIM_SetCounterValue(GTIM_TypeDef *GTIMx, uint32_t Value); +void GTIM_SetCompare1(GTIM_TypeDef *GTIMx, uint32_t Value); +void GTIM_SetCompare2(GTIM_TypeDef *GTIMx, uint32_t Value); +void GTIM_SetCompare3(GTIM_TypeDef *GTIMx, uint32_t Value); +void GTIM_SetCompare4(GTIM_TypeDef *GTIMx, uint32_t Value); +uint32_t GTIM_GetCapture1(GTIM_TypeDef *GTIMx); +uint32_t GTIM_GetCapture2(GTIM_TypeDef *GTIMx); +uint32_t GTIM_GetCapture3(GTIM_TypeDef *GTIMx); +uint32_t GTIM_GetCapture4(GTIM_TypeDef *GTIMx); +void GTIM_ITConfig(GTIM_TypeDef *GTIMx, uint32_t GTIM_IT, FunctionalState NewState); +ITStatus GTIM_GetITStatus(GTIM_TypeDef *GTIMx, uint32_t GTIM_IT); +void GTIM_ClearITPendingBit(GTIM_TypeDef *GTIMx, uint32_t GTIM_IT); +void GTIM_DMAConfig(GTIM_TypeDef *GTIMx, uint32_t GTIM_DMA, FunctionalState NewState); +void GTIM1_ITRConfig(uint32_t ITRSouce); +void GTIM2_ITRConfig(uint32_t ITRSouce); +void GTIM3_ITRConfig(uint32_t ITRSouce); +void GTIM4_ITRConfig(uint32_t ITRSouce); + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32F030_GTIM_H */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_i2c.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_i2c.h new file mode 100644 index 0000000..ebc2dd0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_i2c.h @@ -0,0 +1,161 @@ +/** + * @file cw32f030_i2c.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-04-27 + * + * @copyright Copyright (c) 2021 + * x + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F03x_I2C_H +#define __CW32F03x_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "base_types.h" +#include "cw32f030_rcc.h" + +//I2C从设备地址，按照8 BIT设置，最低位0或者1均可。 +#define I2C_SLAVEADDRESS 0xA0 //读EEPROM时设置为0XA0，主从通信时设置为0x60 + +//主从通信时从机地址设置（在从程序中设置） +#define OwnSlaveAddress0 0x60 //按照8位设置，最低位设置为0或者1,写入寄存器之前会自动右移一位，再写入寄存器高7位 +#define OwnSlaveAddress1 0xb0 //按照8位设置，最低位设置为0或者1,写入寄存器之前会自动右移一位，再写入寄存器高7位 +#define OwnSlaveAddress2 0xfe //按照8位设置，最低位设置为0或者1,写入寄存器之前会自动右移一位，再写入寄存器高7位 + + +/** + * @brief I2C通道选择 + * + */ +typedef enum en_i2c_channel +{ + I2C1 = 0,///<通道1 + I2C2 = 1,///<通道2 +} en_i2c_channel_t; + +/** + ****************************************************************************** + ** \brief I2C初始化配置结构 + *****************************************************************************/ +typedef struct +{ + FunctionalState I2C_BaudEn; ///<波特率计数器使能 + uint8_t I2C_Baud; ///<波特率计数器配置 + uint8_t I2C_OwnSlaveAddr0; ///<从机地址0 + FunctionalState I2C_OwnGc; ///<广播响应使能 + uint8_t I2C_OwnSlaveAddr1; ///<从机地址1 + uint8_t I2C_OwnSlaveAddr2; ///<从机地址2 + FunctionalState I2C_FLT; ///KR = IWDT_RUN_KEY) +#define __IWDT_REFRESH() (CW_IWDT->KR = IWDT_REFRESH_KEY) +#define __IWDT_STOP() do{ \ + CW_IWDT->KR = IWDT_STOP_KEY1;\ + CW_IWDT->KR = IWDT_STOP_KEY2;\ + } while(0) +#define __IWDT_UNLOCK() (CW_IWDT->KR = IWDT_UNLOCK_KEY) +#define __IWDT_LOCK() (CW_IWDT->KR = IWDT_LOCK_KEY) + + +/****************************************************************************** +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ + + +/****************************************************************************** +* Global function prototypes +******************************************************************************/ +void IWDT_DeInit(void); +int IWDT_Init(IWDT_InitTypeDef *IWDT_InitStruct); + +void IWDT_Cmd(void); +void IWDT_Refresh(void); + +void IWDT_Unlock(void); +void IWDT_Lock(void); +void IWDT_Stop(void); + +int IWDT_SetPrescaler(uint32_t WWDT_Prescaler); +int IWDT_SetWindowValue(uint32_t WindowValue); +int IWDT_SetReloadValue(uint32_t ReloadValue); +int IWDT_ITConfig(FunctionalState NewState); +FlagStatus IWDT_GetFlagStatus(uint32_t StatusBit); +void IWDT_ClearOVFlag(void); +uint32_t IWDT_GetCounterValue(void); +void IWDT_SetPeriod(uint32_t period); + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32F030_IWDT_H */ +/** + * @} + */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_lvd.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_lvd.h new file mode 100644 index 0000000..21b9255 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_lvd.h @@ -0,0 +1,248 @@ +/** + * @file cw32f030_lvd.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-21 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +#ifndef __CW32F030_LVD_H +#define __CW32F030_LVD_H + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "base_types.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup LvdGroup Low Voltage Detector (LVD) + ** + ******************************************************************************/ +//@{ +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define LVD_INT_PRIORITY ((uint32_t)3) /*VC interrupt priority (lowest by default) */ + +/** + * @} + */ +/** @defgroup LVD_interrupts_definition + * @{ + */ +#define LVD_TRIG_LEVEL ((uint16_t)0x0080) +#define LVD_TRIG_FALL ((uint16_t)0x0040) +#define LVD_TRIG_RISE ((uint16_t)0x0020) + + +#define IS_LVD_TRIG(TRIG) ((((TRIG) & (uint16_t)0xFF00) == 0x00) && ((TRIG) != 0x00)) +#define IS_LVD_GET_TRIG(TRIG) (((TRIG) == LVD_TRIG_LEVEL) || \ + ((TRIG) == LVD_TRIG_FALL) || \ + ((TRIG) == LVD_TRIG_RISE)) + +/** @defgroup LVD_flags_definition + * @{ + */ +#define LVD_FLAG_FLTV ((uint16_t)0x0002) +#define LVD_FLAG_INTF ((uint16_t)0x0001) + +#define IS_LVD_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFF00) == 0x00) && ((FLAG) != 0x00)) +#define IS_LVD_GET_FLAG(FLAG) (((FLAG) == LVD_FLAG_FLTV) || \ + ((FLAG) == LVD_FLAG_INTF)) + + +/** @defgroup LVD_Action + * @{ + */ +#define LVD_Action_Irq ((uint32_t)0x00000000) +#define LVD_Action_Reset ((uint32_t)0x00000002) + +#define IS_LVD_ACTION(ACTION) (((ACTION) == LVD_Action_Irq) || \ + ((ACTION) == LVD_Action_Reset)) + +/** @defgroup LVD_Source + * @{ + */ +#define LVD_Source_VDDA ((uint32_t)0x00000000) +#define LVD_Source_PA00 ((uint32_t)0x00000004) +#define LVD_Source_PB00 ((uint32_t)0x00000008) +#define LVD_Source_PB11 ((uint32_t)0x0000000C) + +#define IS_LVD_SOURCE(SOURCE) (((SOURCE) == LVD_Source_VDDA) || \ + ((SOURCE) == LVD_Source_PA00) || \ + ((SOURCE) == LVD_Source_PB00) || \ + ((SOURCE) == LVD_Source_PB11)) + +/** @defgroup LVD_Threshold + * @{ + */ +#define LVD_Threshold_2p0V ((uint32_t)0x00000000) +#define LVD_Threshold_2p11V ((uint32_t)0x00000010) +#define LVD_Threshold_2p22V ((uint32_t)0x00000020) +#define LVD_Threshold_2p33V ((uint32_t)0x00000030) +#define LVD_Threshold_2p44V ((uint32_t)0x00000040) +#define LVD_Threshold_2p56V ((uint32_t)0x00000050) +#define LVD_Threshold_2p67V ((uint32_t)0x00000060) +#define LVD_Threshold_2p78V ((uint32_t)0x00000070) +#define LVD_Threshold_2p89V ((uint32_t)0x00000080) +#define LVD_Threshold_3p0V ((uint32_t)0x00000090) +#define LVD_Threshold_3p11V ((uint32_t)0x000000A0) +#define LVD_Threshold_3p22V ((uint32_t)0x000000B0) +#define LVD_Threshold_3p33V ((uint32_t)0x000000C0) +#define LVD_Threshold_3p44V ((uint32_t)0x000000D0) +#define LVD_Threshold_3p56V ((uint32_t)0x000000E0) +#define LVD_Threshold_3p67V ((uint32_t)0x000000F0) + +#define IS_LVD_THRESHOLD(THRESHOLD) (((THRESHOLD) == LVD_Threshold_2p0V) || \ + ((THRESHOLD) == LVD_Threshold_2p11V) || \ + ((THRESHOLD) == LVD_Threshold_2p22V) || \ + ((THRESHOLD) == LVD_Threshold_2p33V) || \ + ((THRESHOLD) == LVD_Threshold_2p44V) || \ + ((THRESHOLD) == LVD_Threshold_2p56V) || \ + ((THRESHOLD) == LVD_Threshold_2p67V) || \ + ((THRESHOLD) == LVD_Threshold_2p78V) || \ + ((THRESHOLD) == LVD_Threshold_2p89V) || \ + ((THRESHOLD) == LVD_Threshold_3p0V) || \ + ((THRESHOLD) == LVD_Threshold_3p11V) || \ + ((THRESHOLD) == LVD_Threshold_3p22V) || \ + ((THRESHOLD) == LVD_Threshold_3p33V) || \ + ((THRESHOLD) == LVD_Threshold_3p44V) || \ + ((THRESHOLD) == LVD_Threshold_3p56V) || \ + ((THRESHOLD) == LVD_Threshold_3p67V)) + +/** @defgroup LVD_Filter + * @{ + */ +#define LVD_Filter_Disable ((uint32_t)0x00000000) +#define LVD_Filter_Enable ((uint32_t)0x00000001) + +#define IS_LVD_FILTER(FILTER) (((FILTER) == LVD_Filter_Disable) || \ + ((FILTER) == LVD_Filter_Enable)) + +/** @defgroup LVD_FilterClk + * @{ + */ +#define LVD_FilterClk_RC150K ((uint32_t)0x00000000) +#define LVD_FilterClk_HSI ((uint32_t)0x00000010) + +#define IS_LVD_FILTER_CLK(FILTER_CLK) (((FILTER_CLK) == LVD_FilterClk_RC150K) || \ + ((FILTER_CLK) == LVD_FilterClk_HSI)) + +/** @defgroup LVD_FilterTime + * @{ + */ +#define LVD_FilterTime_1Clk ((uint32_t)0x00000000) +#define LVD_FilterTime_3Clk ((uint32_t)0x00000002) +#define LVD_FilterTime_7Clk ((uint32_t)0x00000004) +#define LVD_FilterTime_15Clk ((uint32_t)0x00000006) +#define LVD_FilterTime_63Clk ((uint32_t)0x00000008) +#define LVD_FilterTime_255Clk ((uint32_t)0x0000000A) +#define LVD_FilterTime_1023Clk ((uint32_t)0x0000000C) +#define LVD_FilterTime_4095Clk ((uint32_t)0x0000000E) + +#define IS_LVD_FILTER_TIME(FILTER_TIME) (((FILTER_TIME) == LVD_FilterTime_1Clk) || \ + ((FILTER_TIME) == LVD_FilterTime_3Clk) || \ + ((FILTER_TIME) == LVD_FilterTime_7Clk) || \ + ((FILTER_TIME) == LVD_FilterTime_15Clk) || \ + ((FILTER_TIME) == LVD_FilterTime_63Clk) || \ + ((FILTER_TIME) == LVD_FilterTime_255Clk) || \ + ((FILTER_TIME) == LVD_FilterTime_1023Clk) || \ + ((FILTER_TIME) == LVD_FilterTime_4095Clk)) + +/** + ****************************************************************************** + ** @brief LVD配置 + ** \note + ******************************************************************************/ +typedef struct +{ + uint32_t LVD_Action; // LVD触发动作 + uint32_t LVD_Source; // LVD输入电压源 + uint32_t LVD_Threshold; // LVD阈值电压 + uint32_t LVD_FilterEn; // 是否使用输出滤波 + uint32_t LVD_FilterClk; // 滤波时钟源 + uint32_t LVD_FilterTime; // 输出滤波时间 +} LVD_InitTypeDef; + +/****************************************************************************** + * Global definitions + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions ('extern') + ******************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + ******************************************************************************/ +//使能NVIC中LVD中断 +void LVD_EnableNvic(uint8_t intPriority); +//禁止NVIC中LVD中断 +void LVD_DisableNvic(void); +//配置LVD中断/系统复位触发方式 +void LVD_TrigConfig(uint16_t LVD_TRIG, FunctionalState NewState); +//使能LVD中断 +void LVD_EnableIrq(uint8_t intPriority); +//禁止LVD中断 +void LVD_DisableIrq(void); + +//清除LVD中断标志 +void LVD_ClearIrq(void); +//获取LVD中断标志 +boolean_t LVD_GetIrqStatus(void); +//获取LVD指定的状态位 +FlagStatus LVD_GetFlagStatus(uint16_t LVD_FLAG); +//获取Filter结果 +boolean_t LVD_GetFilterResult(void); + +//LVD初始化 +void LVD_Init(LVD_InitTypeDef *LVD_InitStruct); +//LVD去初始化 +void LVD_DeInit(void); + +//使能LVD +void LVD_Enable(void); +//停止LVD +void LVD_Disable(void); + +//@} // LvdGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __CW32F030_LVD_H */ +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_pwr.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_pwr.h new file mode 100644 index 0000000..8cafdd9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_pwr.h @@ -0,0 +1,120 @@ +/** + * @file cw32f030_pwr.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-21 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +#ifndef __CW32F030_PWR_H +#define __CW32F030_PWR_H + +/***************************************************************************** + * Include files + *****************************************************************************/ +#include "base_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup LpmGroup Low Power Management (LPM) + ** + ** + ******************************************************************************/ +//@{ + +/****************************************************************************** + ** Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** @defgroup PWR_Sevonpend + * @{ + */ +#define PWR_Sevonpend_Disable ((uint32_t)0x00000000) +#define PWR_Sevonpend_Enable ((uint32_t)0x00000010) + +#define IS_PWR_SEVONPEND(SEVONPEND) (((SEVONPEND) == PWR_Sevonpend_Disable) || \ + ((SEVONPEND) == PWR_Sevonpend_Enable)) + +/** @defgroup PWR_SleepDeep + * @{ + */ +#define PWR_SleepDeep_Disable ((uint32_t)0x00000000) +#define PWR_SleepDeep_Enable ((uint32_t)0x00000004) + +#define IS_PWR_SLEEPDEEP(SLEEPDEEP) (((SLEEPDEEP) == PWR_SleepDeep_Disable) || \ + ((SLEEPDEEP) == PWR_SleepDeep_Enable)) + +/** @defgroup PWR_SleepOnExit + * @{ + */ +#define PWR_SleepOnExit_Disable ((uint32_t)0x00000000) +#define PWR_SleepOnExit_Enable ((uint32_t)0x00000002) + +#define IS_PWR_SLEEPONEXIT(SLEEPONEXIT) (((SLEEPONEXIT) == PWR_SleepOnExit_Disable) || \ + ((SLEEPONEXIT) == PWR_SleepOnExit_Enable)) + +/** + ****************************************************************************** + ** @brief Low Power Mode 配置结构体定义 + *****************************************************************************/ +typedef struct +{ + uint32_t PWR_Sevonpend; // 使能:每次新中断会产生一个事件,如果使用WFE休眠,则可用于唤醒处理器. + uint32_t PWR_SleepDeep; // 使能:执行WFI进入深度休眠;不使能:执行WFI进入休眠. + uint32_t PWR_SleepOnExit; // 使能:退出异常处理并返回时,处理器自动进入休眠模式;不使能:该特性禁止. +} PWR_InitTypeDef; + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + *****************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + *****************************************************************************/ +//功能配置及操作函数 +//低功耗模式配置 +void PWR_Config(PWR_InitTypeDef *PWR_InitStruct); +//进入低功耗模式 +void PWR_GotoLpmMode(void); + +//@} // PWRGroup + +#ifdef __cplusplus +} +#endif + + +#endif /* __CW32F030_PWR_H */ +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_ram.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_ram.h new file mode 100644 index 0000000..c88fb2e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_ram.h @@ -0,0 +1,72 @@ +/** + * @file cw32f030_ram.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-14 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F03x_RAM_H__ +#define __CW32F03x_RAM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "base_types.h" +#include "cw32f030.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +//============================================================ + +/** @defgroup 中断标志位 + * @{ + */ +#define RAM_IT_PARITY (bv1) +#define IS_RAM_IT(IT) ((((IT) & 0xFFFFFFFD) == 0x0UL) && ((IT) != 0x0UL)) +#define IS_RAM_GET_IT(IT) ((IT) == RAM_IT_PARITY) + +//============================================================ + +//RAM PARITY中断使能配置 +void RAM_ITConfig(uint32_t RAM_IT, FunctionalState NewState); +//获取RAM PARITY中断标志位 +ITStatus RAM_GetITStatus(uint32_t RAM_IT); +//清除RAM PARITY断标志位 +void RAM_ClearITPendingBit(uint32_t RAM_IT); +//获取发生奇偶校验错的RAM地址// +uint32_t RAM_GetErrorAddress(void); + +//============================================================ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_rcc.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_rcc.h new file mode 100644 index 0000000..4d12dd8 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_rcc.h @@ -0,0 +1,514 @@ +/** + * @file cw32f030_rcc.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-13 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_RCC_H +#define __CW32F030_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "system_cw32f030.h" + +//================================================================================== +#define HSIOSC_VALUE ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/ +#define HSE_VALUE ((uint32_t)16000000) /*!< Value of the External oscillator in Hz */ + +#define LSI_VALUE ((uint32_t)32800) /*!< Value of the External oscillator in Hz */ +#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz */ +/* SYSCTRL CR0 --------------------------------------------------------*/ +#define SYSCTRL_BYPASS (0x5A5A0000U) +#define SYSCTRL_BYPASS_MASK (0xFFFF0000U) + +#define RCC_HCLK_DIV1 (0x0UL << SYSCTRL_CR0_HCLKPRS_Pos)/*!< SYSCLK not divided */ +#define RCC_HCLK_DIV2 (0x1UL << SYSCTRL_CR0_HCLKPRS_Pos)/*!< SYSCLK divided by 2 */ +#define RCC_HCLK_DIV4 (0x2UL << SYSCTRL_CR0_HCLKPRS_Pos)/*!< SYSCLK divided by 4 */ +#define RCC_HCLK_DIV8 (0x3UL << SYSCTRL_CR0_HCLKPRS_Pos)/*!< SYSCLK divided by 8 */ +#define RCC_HCLK_DIV16 (0x4UL << SYSCTRL_CR0_HCLKPRS_Pos)/*!< SYSCLK divided by 16 */ +#define RCC_HCLK_DIV32 (0x5UL << SYSCTRL_CR0_HCLKPRS_Pos)/*!< SYSCLK divided by 32 */ +#define RCC_HCLK_DIV64 (0x6UL << SYSCTRL_CR0_HCLKPRS_Pos)/*!< SYSCLK divided by 64 */ +#define RCC_HCLK_DIV128 (0x7ul << SYSCTRL_CR0_HCLKPRS_Pos)/*!< SYSCLK divided by 128 */ +#define IS_RCC_HCLKPRS(INSTANCE) (((INSTANCE) == RCC_HCLK_DIV1) ||\ + ((INSTANCE) == RCC_HCLK_DIV2) ||\ + ((INSTANCE) == RCC_HCLK_DIV4) ||\ + ((INSTANCE) == RCC_HCLK_DIV8) ||\ + ((INSTANCE) == RCC_HCLK_DIV16) ||\ + ((INSTANCE) == RCC_HCLK_DIV32) ||\ + ((INSTANCE) == RCC_HCLK_DIV64) ||\ + ((INSTANCE) == RCC_HCLK_DIV128)) + +#define RCC_PCLK_DIV1 (0x0UL << SYSCTRL_CR0_PCLKPRS_Pos) /*!< HCLK not divided */ +#define RCC_PCLK_DIV2 (0x1UL << SYSCTRL_CR0_PCLKPRS_Pos) /*!< HCLK divided by 2 */ +#define RCC_PCLK_DIV4 (0x2UL << SYSCTRL_CR0_PCLKPRS_Pos) /*!< HCLK divided by 4 */ +#define RCC_PCLK_DIV8 (0x3UL << SYSCTRL_CR0_PCLKPRS_Pos) /*!< HCLK divided by 8 */ +#define IS_RCC_PCLKPRS(INSTANCE) (((INSTANCE) == RCC_PCLK_DIV1) ||\ + ((INSTANCE) == RCC_PCLK_DIV2) ||\ + ((INSTANCE) == RCC_PCLK_DIV4) ||\ + ((INSTANCE) == RCC_PCLK_DIV8)) + +#define RCC_SYSCLKSRC_HSI (0x00000000U) /*!< HSI selected as system clock */ +#define RCC_SYSCLKSRC_HSE (0x00000001U) /*!< HSE selected as system clock */ +#define RCC_SYSCLKSRC_PLL (0x00000002U) /*!< PLL selected as system clock */ +#define RCC_SYSCLKSRC_LSI (0x00000003U) /*!< LSI selected as system clock */ +#define RCC_SYSCLKSRC_LSE (0x00000004U) /*!< LSE selected as system clock */ +#define IS_RCC_SYSCLKSRC(INSTANCE) (((INSTANCE) == RCC_SYSCLKSRC_HSI) ||\ + ((INSTANCE) == RCC_SYSCLKSRC_HSE) ||\ + ((INSTANCE) == RCC_SYSCLKSRC_PLL) ||\ + ((INSTANCE) == RCC_SYSCLKSRC_LSI) ||\ + ((INSTANCE) == RCC_SYSCLKSRC_LSE)) + +/* SYSCTRL CR1 --------------------------------------------------------*/ +#define RCC_SYSCTRL_HSIEN bv0 +#define RCC_SYSCTRL_HSEEN bv1 +#define RCC_SYSCTRL_PLLEN bv2 +#define RCC_SYSCTRL_LSIEN bv3 +#define RCC_SYSCTRL_LSEEN bv4 + +#define RCC_SYSCTRL_LSELOCKEN bv5 +#define RCC_SYSCTRL_LSELOCKDIS 0x00UL +#define IS_RCC_LSELOCK_STATUS(INSTANCE) (((INSTANCE) == RCC_SYSCTRL_LSELOCKEN) ||\ + ((INSTANCE) == RCC_SYSCTRL_LSELOCKDIS)) + +#define RCC_SYSCTRL_LSECCS bv6 +#define RCC_SYSCTRL_HSECCS bv7 +#define RCC_SYSCTRL_CLKCCS bv8 +#define IS_RCC_CCS_STATUS(INSTANCE) (((INSTANCE) == RCC_SYSCTRL_LSECCS) ||\ + ((INSTANCE) == RCC_SYSCTRL_HSECCS) ||\ + ((INSTANCE) == RCC_SYSCTRL_CLKCCS)) + +/* SYSCTRL CR2 --------------------------------------------------------*/ +#define RCC_SYSCTRL_SWDIOEN 0x00UL +#define RCC_SYSCTRL_SWDIODIS bv1 +#define IS_RCC_SWDIO_STATUS(INSTANCE) (((INSTANCE) == RCC_SYSCTRL_SWDIOEN) ||\ + ((INSTANCE) == RCC_SYSCTRL_SWDIODIS)) + +#define RCC_SYSCTRL_LOCKUPEN bv2 +#define RCC_SYSCTRL_LOCKUPDIS 0x00UL +#define IS_RCC_LOCKUP_STATUS(INSTANCE) (((INSTANCE) == RCC_SYSCTRL_LOCKUPEN) ||\ + ((INSTANCE) == RCC_SYSCTRL_LOCKUPDIS)) + +#define RCC_SYSCTRL_WAKEUPCLKEN bv3 +#define RCC_SYSCTRL_WAKEUPCLKDIS 0x00UL +#define IS_RCC_WAKEUPCLK_STATUS(INSTANCE) (((INSTANCE) == RCC_SYSCTRL_WAKEUPCLKEN) ||\ + ((INSTANCE) == RCC_SYSCTRL_WAKEUPCLKDIS)) +/* SYSCTRL HSI --------------------------------------------------------*/ +#define RCC_HSI_TRIMCODEADDR (0x00012600U) +#define RCC_HSIOSC_DIV6 (0x5U) +#define RCC_HSIOSC_DIV1 (0x6U) +#define RCC_HSIOSC_DIV2 (0x8U) +#define RCC_HSIOSC_DIV3 (0x7U) +#define RCC_HSIOSC_DIV4 (0x9U) +#define RCC_HSIOSC_DIV8 (0xBU) +#define RCC_HSIOSC_DIV10 (0xCU) +#define RCC_HSIOSC_DIV12 (0xDU) +#define RCC_HSIOSC_DIV14 (0xEU) +#define RCC_HSIOSC_DIV16 (0xFU) + +#define IS_RCC_HSIOSC_DIV(INSTANCE) (((INSTANCE) == RCC_HSIOSC_DIV1) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV2) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV3) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV4) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV6) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV8) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV10) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV12) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV14) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV16)) + +/* SYSCTRL LSI --------------------------------------------------------*/ +#define RCC_LSI_TRIMCODEADDR (0x00012602U) +#define RCC_LSI_WAITCYCLE_6 ((uint32_t)(0x0UL << SYSCTRL_LSI_WAITCYCLE_Pos)) +#define RCC_LSI_WAITCYCLE_18 ((uint32_t)(0x1UL << SYSCTRL_LSI_WAITCYCLE_Pos)) +#define RCC_LSI_WAITCYCLE_66 ((uint32_t)(0x2UL << SYSCTRL_LSI_WAITCYCLE_Pos)) +#define RCC_LSI_WAITCYCLE_258 ((uint32_t)(0x3UL << SYSCTRL_LSI_WAITCYCLE_Pos)) + + +/* SYSCTRL HSE --------------------------------------------------------*/ +#define RCC_HSE_FLT_CLOSE (0x00000000U) +#define RCC_HSE_FLT_OPEN SYSCTRL_HSE_FLT_Msk //(0x80UL) +#define IS_RCC_HSE_FLT(INSTANCE) (((INSTANCE) == RCC_HSE_FLT_CLOSE) ||\ + ((INSTANCE) == RCC_HSE_FLT_OPEN)) + +#define RCC_HSE_MODE_OSC (0x00000000U) +#define RCC_HSE_MODE_CLK SYSCTRL_HSE_MODE_Msk //(0x40UL) +#define IS_RCC_HSE_MODE(INSTANCE) (((INSTANCE) == RCC_HSE_MODE_OSC) ||\ + ((INSTANCE) == RCC_HSE_MODE_CLK)) + +#define RCC_HSE_WAITCYCLE_8192 (0x00000000U) +#define RCC_HSE_WAITCYCLE_32768 ((uint32_t)(0x1UL << SYSCTRL_HSE_WAITCYCLE_Pos)) +#define RCC_HSE_WAITCYCLE_131072 ((uint32_t)(0x2UL << SYSCTRL_HSE_WAITCYCLE_Pos)) +#define RCC_HSE_WAITCYCLE_262144 ((uint32_t)(0x3UL << SYSCTRL_HSE_WAITCYCLE_Pos)) + +#define RCC_HSE_FREQ_GT4M (0x00000000U) +#define RCC_HSE_FREQ_GT8M ((uint32_t)(0x1UL << SYSCTRL_HSE_FREQRANGE_Pos)) +#define RCC_HSE_FREQ_GT16M ((uint32_t)(0x2UL << SYSCTRL_HSE_FREQRANGE_Pos)) +#define RCC_HSE_FREQ_GT24M ((uint32_t)(0x3UL << SYSCTRL_HSE_FREQRANGE_Pos)) +#define IS_RCC_HSE_FREQIN(INSTANCE) (((INSTANCE) >=4000000) && ((INSTANCE) <=32000000)) + +#define RCC_HSE_DRIVER_LEAST 0x00U +#define RCC_HSE_DRIVER_SMALL 0x01U +#define RCC_HSE_DRIVER_NORMAL 0x02U +#define RCC_HSE_DRIVER_LARGER 0x03U +#define IS_RCC_HSE_DRIVER(INSTANCE) (((INSTANCE) == RCC_HSE_DRIVER_LEAST) ||\ + ((INSTANCE) == RCC_HSE_DRIVER_SMALL) ||\ + ((INSTANCE) == RCC_HSE_DRIVER_NORMAL) ||\ + ((INSTANCE) == RCC_HSE_DRIVER_LARGER)) + +/* SYSCTRL LSE --------------------------------------------------------*/ +#define RCC_LSE_MODE_OSC (0x00000000U) +#define RCC_LSE_MODE_CLK SYSCTRL_LSE_MODE_Msk + +#define IS_RCC_LSE_MODE(INSTANCE) (((INSTANCE) == RCC_LSE_MODE_OSC) ||\ + ((INSTANCE) == RCC_LSE_MODE_CLK)) + +#define RCC_LSE_AMP_LEAST (0x00000000U) +#define RCC_LSE_AMP_SMALL ((uint32_t)(0x1UL << SYSCTRL_LSE_AMP_Pos)) +#define RCC_LSE_AMP_NORMAL ((uint32_t)(0x2UL << SYSCTRL_LSE_AMP_Pos)) +#define RCC_LSE_AMP_LARGER ((uint32_t)(0x3UL << SYSCTRL_LSE_AMP_Pos)) +#define IS_RCC_LSE_AMP(AMP) (((AMP) == RCC_LSE_AMP_LEAST) ||\ + ((AMP) == RCC_LSE_AMP_SMALL) ||\ + ((AMP) == RCC_LSE_AMP_NORMAL) ||\ + ((AMP) == RCC_LSE_AMP_LARGER)) + +#define RCC_LSE_DRIVER_LEAST (0x00000000U) +#define RCC_LSE_DRIVER_SMALL (0x00000001U) +#define RCC_LSE_DRIVER_NORMAL (0x00000002U) +#define RCC_LSE_DRIVER_LARGER (0x00000003U) + +#define IS_RCC_LSE_DRIVER(DRIVER) (((DRIVER) == RCC_LSE_DRIVER_LEAST)||\ + ((DRIVER) == RCC_LSE_DRIVER_SMALL) ||\ + ((DRIVER) == RCC_LSE_DRIVER_NORMAL) ||\ + ((DRIVER) == RCC_LSE_DRIVER_LARGER)) + +#define RCC_LSE_WAITCYCLE_256 (0x00000000U) +#define RCC_LSE_WAITCYCLE_1024 ((uint32_t)(0x1UL << SYSCTRL_LSE_WAITCYCLE_Pos)) +#define RCC_LSE_WAITCYCLE_4096 ((uint32_t)(0x2UL << SYSCTRL_LSE_WAITCYCLE_Pos)) +#define RCC_LSE_WAITCYCLE_16384 ((uint32_t)(0x3UL << SYSCTRL_LSE_WAITCYCLE_Pos)) + + + +/* SYSCTRL PLL --------------------------------------------------------*/ +#define RCC_PLLSOURCE_HSEOSC (0x00000000U) /*!< HSE oscillator clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSECLK (0x00000001U) /*!< HSE input clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSI (0x00000003U) /*!< HSI clock selected as PLL entry clock source */ + +#define IS_RCC_PLLSOURCE(INSTANCE) (((INSTANCE) == RCC_PLLSOURCE_HSEOSC) ||\ + ((INSTANCE) == RCC_PLLSOURCE_HSECLK) ||\ + ((INSTANCE) == RCC_PLLSOURCE_HSI)) + +#define RCC_PLL_WAITCYCLE_128 (0x00000000U) +#define RCC_PLL_WAITCYCLE_256 ((uint32_t)(0x1UL << SYSCTRL_PLL_WAITCYCLE_Pos)) +#define RCC_PLL_WAITCYCLE_512 ((uint32_t)(0x2UL << SYSCTRL_PLL_WAITCYCLE_Pos)) +#define RCC_PLL_WAITCYCLE_1024 ((uint32_t)(0x3UL << SYSCTRL_PLL_WAITCYCLE_Pos)) +#define RCC_PLL_WAITCYCLE_2048 ((uint32_t)(0x4UL << SYSCTRL_PLL_WAITCYCLE_Pos)) +#define RCC_PLL_WAITCYCLE_4096 ((uint32_t)(0x5UL << SYSCTRL_PLL_WAITCYCLE_Pos)) +#define RCC_PLL_WAITCYCLE_8192 ((uint32_t)(0x6UL << SYSCTRL_PLL_WAITCYCLE_Pos)) +#define RCC_PLL_WAITCYCLE_16384 ((uint32_t)(0x7UL << SYSCTRL_PLL_WAITCYCLE_Pos)) + +#define RCC_PLL_FREQOUT_GT12M (0x00000000U) +#define RCC_PLL_FREQOUT_GT18M ((uint32_t)(0x1UL << SYSCTRL_PLL_FREQOUT_Pos)) +#define RCC_PLL_FREQOUT_GT24M ((uint32_t)(0x2UL << SYSCTRL_PLL_FREQOUT_Pos)) +#define RCC_PLL_FREQOUT_GT36M ((uint32_t)(0x3UL << SYSCTRL_PLL_FREQOUT_Pos)) +#define RCC_PLL_FREQOUT_GT48M ((uint32_t)(0x4UL << SYSCTRL_PLL_FREQOUT_Pos)) +#define IS_RCC_PLL_FREQIN(INSTANCE) (INSTANCE >=4000000) && (INSTANCE <=24000000) + + +#define RCC_PLL_MUL_2 (0x2U) +#define RCC_PLL_MUL_3 (0x3U) +#define RCC_PLL_MUL_4 (0x4U) +#define RCC_PLL_MUL_5 (0x5U) +#define RCC_PLL_MUL_6 (0x6U) +#define RCC_PLL_MUL_7 (0x7U) +#define RCC_PLL_MUL_8 (0x8U) +#define RCC_PLL_MUL_9 (0x9U) +#define RCC_PLL_MUL_10 (0xAU) +#define RCC_PLL_MUL_11 (0xBU) +#define RCC_PLL_MUL_12 (0xCU) +#define IS_RCC_PLL_MUL(INSTANCE) (((INSTANCE) == RCC_PLL_MUL_2) ||\ + ((INSTANCE) == RCC_PLL_MUL_3) ||\ + ((INSTANCE) == RCC_PLL_MUL_4) ||\ + ((INSTANCE) == RCC_PLL_MUL_5) ||\ + ((INSTANCE) == RCC_PLL_MUL_6) ||\ + ((INSTANCE) == RCC_PLL_MUL_7) ||\ + ((INSTANCE) == RCC_PLL_MUL_8) ||\ + ((INSTANCE) == RCC_PLL_MUL_9) ||\ + ((INSTANCE) == RCC_PLL_MUL_10) ||\ + ((INSTANCE) == RCC_PLL_MUL_11) ||\ + ((INSTANCE) == RCC_PLL_MUL_12)) + + +#define RCC_IT_HSEFAULT (bv8) +#define RCC_IT_LSEFAULT (bv7) +#define RCC_IT_HSEFAIL (bv6) +#define RCC_IT_LSEFAIL (bv5) +#define RCC_IT_LSERDY (bv4) +#define RCC_IT_LSIRDY (bv3) +#define RCC_IT_PLLRDY (bv2) +#define RCC_IT_HSERDY (bv1) +#define RCC_IT_HSIRDY (bv0) +#define IS_RCC_IT(IT) ((((IT) & 0xFFFFFFE0) == 0x0UL) && ((IT) != 0x0UL)) +#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_HSEFAULT) || \ + ((IT) == RCC_IT_LSEFAULT) || \ + ((IT) == RCC_IT_HSEFAIL) || \ + ((IT) == RCC_IT_LSEFAIL) ||\ + ((IT) == RCC_IT_LSERDY) ||\ + ((IT) == RCC_IT_LSIRDY) ||\ + ((IT) == RCC_IT_PLLRDY) ||\ + ((IT) == RCC_IT_HSERDY) ||\ + ((IT) == RCC_IT_HSIRDY)) + + +#define RCC_FLAG_HSISTABLE bv11 +#define RCC_FLAG_HSESTABLE bv12 +#define RCC_FLAG_PLLSTABLE bv13 +#define RCC_FLAG_LSESTABLE bv15 +#define RCC_FLAG_LSISTABLE bv14 +#define IS_RCC_STABLEFLAG(FLAG) (((FLAG) == RCC_FLAG_HSISTABLE) || ((FLAG) == RCC_FLAG_HSESTABLE) ||\ + ((FLAG) == RCC_FLAG_PLLSTABLE) || ((FLAG) == RCC_FLAG_LSESTABLE) ||\ + ((FLAG) == RCC_FLAG_LSISTABLE)) + +#define RCC_FLAG_PINRST bv6 +#define RCC_FLAG_PORRST bv0 +#define RCC_FLAG_LVDRST bv3 +#define RCC_FLAG_LOCKUPRST bv8 +#define RCC_FLAG_IWDTRST bv4 +#define RCC_FLAG_WWDTRST bv5 +#define RCC_FLAG_SYSRESETREQRST bv9 +#define RCC_FLAG_ALLRST ((uint32_t)0x00000379) +#define IS_RCC_RSTFLAG(FLAG) (((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_LVDRST) || ((FLAG) == RCC_FLAG_IWDTRST) || \ + ((FLAG) == RCC_FLAG_WWDTRST) || ((FLAG) == RCC_FLAG_LOCKUPRST) || \ + ((FLAG) == RCC_FLAG_SYSRESETREQRST) || ((FLAG) == RCC_FLAG_ALLRST)) + + +#define RCC_AHB_PERIPH_GPIOF bv9 +#define RCC_AHB_PERIPH_GPIOC bv6 +#define RCC_AHB_PERIPH_GPIOB bv5 +#define RCC_AHB_PERIPH_GPIOA bv4 +#define RCC_AHB_PERIPH_CRC bv2 +#define RCC_AHB_PERIPH_FLASH bv1 +#define RCC_AHB_PERIPH_DMA bv0 +#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFD88 ) == 0x00) && ((PERIPH) != 0x00)) + +#define __RCC_GPIOF_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, RCC_AHB_PERIPH_GPIOF) +#define __RCC_GPIOC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, RCC_AHB_PERIPH_GPIOC) +#define __RCC_GPIOB_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, RCC_AHB_PERIPH_GPIOB) +#define __RCC_GPIOA_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, RCC_AHB_PERIPH_GPIOA) +#define __RCC_CRC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, RCC_AHB_PERIPH_CRC) +#define __RCC_FLASH_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, RCC_AHB_PERIPH_FLASH) +#define __RCC_DMA_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, RCC_AHB_PERIPH_DMA) + +#define __RCC_GPIOF_CLK_DISABLE() (CW_SYSCTRL->AHBEN &= ~(RCC_AHB_PERIPH_GPIOF)) +#define __RCC_GPIOC_CLK_DISABLE() (CW_SYSCTRL->AHBEN &= ~(RCC_AHB_PERIPH_GPIOC)) +#define __RCC_GPIOB_CLK_DISABLE() (CW_SYSCTRL->AHBEN &= ~(RCC_AHB_PERIPH_GPIOB)) +#define __RCC_GPIOA_CLK_DISABLE() (CW_SYSCTRL->AHBEN &= ~(RCC_AHB_PERIPH_GPIOA)) +#define __RCC_CRC_CLK_DISABLE() (CW_SYSCTRL->AHBEN &= ~(RCC_AHB_PERIPH_CRC)) +#define __RCC_FLASH_CLK_DISABLE() (CW_SYSCTRL->AHBEN &= ~(RCC_AHB_PERIPH_FLASH)) +#define __RCC_DMA_CLK_DISABLE() (CW_SYSCTRL->AHBEN &= ~(RCC_AHB_PERIPH_DMA)) + +#define RCC_APB1_PERIPH_I2C2 bv12 +#define RCC_APB1_PERIPH_I2C1 bv11 +#define RCC_APB1_PERIPH_UART3 bv8 +#define RCC_APB1_PERIPH_UART2 bv7 +#define RCC_APB1_PERIPH_SPI2 bv6 +#define RCC_APB1_PERIPH_IWDT bv5 +#define RCC_APB1_PERIPH_WWDT bv4 +#define RCC_APB1_PERIPH_RTC bv3 +#define RCC_APB1_PERIPH_GTIM2 bv2 +#define RCC_APB1_PERIPH_GTIM1 bv1 +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFE601 ) == 0x00) && ((PERIPH) != 0x00)) + +#define __RCC_I2C2_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_I2C2) +#define __RCC_I2C1_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_I2C1) +#define __RCC_UART3_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_UART3) +#define __RCC_UART2_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_UART2) +#define __RCC_SPI2_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_SPI2) +#define __RCC_IWDT_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_IWDT) +#define __RCC_WWDT_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_WWDT) +#define __RCC_RTC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_RTC) +#define __RCC_GTIM2_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_GTIM2) +#define __RCC_GTIM1_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_GTIM1) + +#define __RCC_I2C2_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_I2C2)) +#define __RCC_I2C1_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_I2C1)) +#define __RCC_UART3_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_UART3)) +#define __RCC_UART2_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_UART2)) +#define __RCC_SPI2_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_SPI2)) +#define __RCC_IWDT_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_IWDT)) +#define __RCC_WWDT_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_WWDT)) +#define __RCC_RTC_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_RTC)) +#define __RCC_GTIM2_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_GTIM2)) +#define __RCC_GTIM1_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_GTIM1)) + +#define RCC_APB2_PERIPH_AWT bv13 +#define RCC_APB2_PERIPH_BTIM bv12 +#define RCC_APB2_PERIPH_GTIM4 bv11 +#define RCC_APB2_PERIPH_GTIM3 bv10 +#define RCC_APB2_PERIPH_UART1 bv9 +#define RCC_APB2_PERIPH_SPI1 bv8 +#define RCC_APB2_PERIPH_ATIM bv7 +#define RCC_APB2_PERIPH_VC bv4 +#define RCC_APB2_PERIPH_ADC bv2 +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFC06D ) == 0x00) && ((PERIPH) != 0x00)) + +#define __RCC_AWT_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_AWT) +#define __RCC_BTIM_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_BTIM) +#define __RCC_GTIM4_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_GTIM4) +#define __RCC_GTIM3_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_GTIM3) +#define __RCC_UART1_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_UART1) +#define __RCC_SPI1_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_SPI1) +#define __RCC_ATIM_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_ATIM) +#define __RCC_VC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_VC) +#define __RCC_ADC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_ADC) + + +#define __RCC_AWT_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_AWT)) +#define __RCC_BTIM_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_BTIM)) +#define __RCC_GTIM4_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_GTIM4)) +#define __RCC_GTIM3_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_GTIM3)) +#define __RCC_UART1_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_UART1)) +#define __RCC_SPI1_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_SPI1)) +#define __RCC_ATIM_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_ATIM)) +#define __RCC_VC_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_VC)) +#define __RCC_ADC_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_ADC)) + +#define RCC_MCO_DIV1 (0x00U) +#define RCC_MCO_DIV2 ((uint8_t)(0x01U << SYSCTRL_MCO_DIV_Pos)) +#define RCC_MCO_DIV8 ((uint8_t)(0x02U << SYSCTRL_MCO_DIV_Pos)) +#define RCC_MCO_DIV64 ((uint8_t)(0x03U << SYSCTRL_MCO_DIV_Pos)) +#define RCC_MCO_DIV128 ((uint8_t)(0x04U << SYSCTRL_MCO_DIV_Pos)) +#define RCC_MCO_DIV256 ((uint8_t)(0x05U << SYSCTRL_MCO_DIV_Pos)) +#define RCC_MCO_DIV512 ((uint8_t)(0x06U << SYSCTRL_MCO_DIV_Pos)) +#define RCC_MCO_DIV1024 ((uint8_t)(0x07U << SYSCTRL_MCO_DIV_Pos)) + +#define IS_RCC_MCO_DIV(INSTANCE) (((INSTANCE) == RCC_MCO_DIV1) ||\ + ((INSTANCE) == RCC_MCO_DIV2) ||\ + ((INSTANCE) == RCC_MCO_DIV8) ||\ + ((INSTANCE) == RCC_MCO_DIV64) ||\ + ((INSTANCE) == RCC_MCO_DIV128) ||\ + ((INSTANCE) == RCC_MCO_DIV256) ||\ + ((INSTANCE) == RCC_MCO_DIV512) ||\ + ((INSTANCE) == RCC_MCO_DIV1024)) + +#define RCC_MCO_SRC_NONE (0x00U) +#define RCC_MCO_SRC_HCLK (0x01U) +#define RCC_MCO_SRC_PCLK (0x02U) +#define RCC_MCO_SRC_HSI (0x03U) +#define RCC_MCO_SRC_LSI (0x04U) +#define RCC_MCO_SRC_HSE (0x05U) +#define RCC_MCO_SRC_LSE (0x06U) +#define RCC_MCO_SRC_PLL (0x07U) +#define RCC_MCO_SRC_RC150K (0x08U) +#define RCC_MCO_SRC_RC10K (0x09U) + +#define IS_RCC_MCO_SRC(INSTANCE) (((INSTANCE) == RCC_MCO_SRC_NONE) || \ + ((INSTANCE) == RCC_MCO_SRC_HCLK) || \ + ((INSTANCE) == RCC_MCO_SRC_PCLK) || \ + ((INSTANCE) == RCC_MCO_SRC_HSI) || \ + ((INSTANCE) == RCC_MCO_SRC_LSI) || \ + ((INSTANCE) == RCC_MCO_SRC_HSE) || \ + ((INSTANCE) == RCC_MCO_SRC_LSE) || \ + ((INSTANCE) == RCC_MCO_SRC_PLL) || \ + ((INSTANCE) == RCC_MCO_SRC_RC150K) || \ + ((INSTANCE) == RCC_MCO_SRC_RC10K)) + +#define RCC_TIMITR_BTIM1 (0UL) +#define RCC_TIMITR_BTIM2 (1UL) +#define RCC_TIMITR_BTIM3 (2UL) +#define RCC_TIMITR_GTIM1 (3UL) +#define RCC_TIMITR_GTIM2 (4UL) +#define RCC_TIMITR_GTIM3 (5UL) +#define RCC_TIMITR_GTIM4 (6UL) +#define RCC_TIMITR_ATIM (7UL) + +#define IS_RCC_TIMITR_SOURCE(SRC) ((SRC) < 8) + +//================================================================================== +extern void RCC_HCLKPRS_Config(uint32_t HCLKPRS); +extern void RCC_PCLKPRS_Config(uint32_t PCLKPRS); +extern void RCC_SYSCLKSRC_Config(uint32_t SYSCLKSRC); +extern void RCC_CCS_Config(uint32_t CCS, FunctionalState NewState); +extern void RCC_LSELOCK_Config(uint32_t LSELOCK); +extern void RCC_WAKEUPCLK_Config(uint32_t WAKEUPCLK); +extern void RCC_LOCKUP_Config(uint32_t LOCKUP); +extern void RCC_SWDIO_Config(uint32_t SWDIO); +extern int RCC_DeInit(void); +extern void RCC_SystemCoreClockUpdate(uint32_t NewFreq); +extern int RCC_HSI_Enable(uint32_t HSIDiv); +extern void RCC_HSI_Disable(void); +extern int RCC_LSI_Enable(void); +extern void RCC_LSI_Disable(void); +extern int RCC_HSE_Enable(uint32_t Mode, uint32_t FreqIn, uint8_t Driver, uint32_t Flt); +extern void RCC_HSE_Disable(void); +extern int RCC_LSE_Enable(uint32_t Mode, uint8_t Amp, uint8_t Driver); +extern void RCC_LSE_Disable(void); +extern int RCC_PLL_Enable(uint32_t PLLSource, uint32_t FreqIn, uint32_t PLLMul); +extern void RCC_PLL_Disable(void); +extern uint8_t RCC_SysClk_Switch(uint32_t NewClk); +extern void RCC_ITConfig(uint32_t RCC_IT, FunctionalState NewState); +extern ITStatus RCC_GetITStatus(uint32_t RCC_IT); +extern void RCC_ClearITPendingBit(uint32_t RCC_IT); +extern FlagStatus RCC_GetStableFlag(uint32_t RCC_STABLEFLAG); +extern uint32_t RCC_GetAllStableFlag(void); +extern void RCC_AHBPeriphClk_Enable(uint32_t Periph, FunctionalState NewState); +extern void RCC_APBPeriphClk_Enable1(uint32_t Periph, FunctionalState NewState); +extern void RCC_APBPeriphClk_Enable2(uint32_t Periph, FunctionalState NewState); +extern void RCC_AHBPeriphReset(uint32_t Periph, FunctionalState NewState); +extern void RCC_APBPeriphReset1(uint32_t Periph, FunctionalState NewState); +extern void RCC_APBPeriphReset2(uint32_t Periph, FunctionalState NewState); +extern FlagStatus RCC_GetRstFlag(uint32_t RCC_RSTFLAG); +extern uint32_t RCC_GetAllRstFlag(void); +extern void RCC_ClearRstFlag(uint32_t RCC_RSTFLAG); +extern void RCC_HCLK_OUT(void); +extern void RCC_PCLK_OUT(void); +extern void RCC_HSE_OUT(void); +extern void RCC_HSI_OUT(void); +extern void RCC_LSE_OUT(void); +extern void RCC_LSI_OUT(void); +extern void RCC_PLL_OUT(void); +extern void RCC_MCO_OUT(uint8_t Source, uint8_t Div); + +extern uint32_t RCC_Sysctrl_GetHClkFreq(void); +extern uint32_t RCC_Sysctrl_GetPClkFreq(void); + +void RCC_BTIM3ITRSelect(uint32_t Source); +void RCC_BTIM2ITRSelect(uint32_t Source); +void RCC_BTIM1ITRSelect(uint32_t Source); +void RCC_GTIM1ITRSelect(uint32_t Source); +void RCC_GTIM2ITRSelect(uint32_t Source); +void RCC_GTIM3ITRSelect(uint32_t Source); +void RCC_GTIM4ITRSelect(uint32_t Source); +void RCC_ATIMITRSelect(uint32_t Source); + +#ifdef __cplusplus +} +#endif + +#endif /* __CW32F030_RCC_H */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_rtc.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_rtc.h new file mode 100644 index 0000000..3b21268 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_rtc.h @@ -0,0 +1,529 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_RTC_H +#define __CW32F030_RTC_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" + + +typedef struct +{ + uint8_t Day; + uint8_t Month; + uint8_t Year; + uint8_t Week; +} RTC_DateTypeDef; + +typedef struct +{ + uint8_t Second; + uint8_t Minute; + uint8_t Hour; + uint8_t AMPM; + uint8_t H24; //RTC_HOUR24(1),RTC_HOUR12(0) +} RTC_TimeTypeDef; + +typedef struct +{ + uint32_t RTC_ClockSource; + RTC_TimeTypeDef TimeStruct; + RTC_DateTypeDef DateStruct; + +} RTC_InitTypeDef; + + +typedef struct +{ + RTC_TimeTypeDef RTC_AlarmTime; + uint32_t RTC_AlarmMask; /*!< @ref RTC_AlarmMask_Definitions */ +} RTC_AlarmTypeDef; + +typedef struct +{ + uint8_t AWT_ClockSource; + uint16_t AWT_ARRValue; +} RTC_AWTTypeDef; + +typedef struct +{ + uint32_t Freq; + uint32_t Sign; + uint32_t Step; + uint32_t CompensationValue; +} RTC_CalibTypeDef; + + + + +#define RTC_Alarm_A ((uint32_t)0x00000200) +#define RTC_Alarm_B ((uint32_t)0x00000400) +#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) +#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) + +/** @defgroup RTC_ACCESS_TIMEOUT +* @{ +* RTC寄存器访问最大次数，RTC_CR1->WINDOW位未检测到1，判定访问RTC寄存器失败 +*/ + +#define RTC_ACCESS_MAXTIMES ((uint32_t)200U) + + +/** @defgroup RTC_RTC1HZ_source +* @{ +*/ + +#define RTC_RTC1HZ_NONE (0UL) +#define RTC_RTC1HZ_FROM_LSE (1UL << 5) +#define RTC_RTC1HZ_FROM_PCLK (3UL << 5) + +#define IS_RTC_RTC1HZ_SOURCE(src) (((src) == RTC_RTC1HZ_NONE) ||\ + ((src) == RTC_RTC1HZ_FROM_PCLK) || \ + ((src) == RTC_RTC1HZ_FROM_LSE)) + + +#define RTC_HOUR24 (1UL << 3) +#define RTC_HOUR12 (0UL) +#define IS_RTC_HOUR_FORMAT(fmt) (((fmt) == RTC_HOUR24) || ((fmt) == RTC_HOUR12)) +#define IS_RTC_HOUR12_FORMAT(fmt) ((fmt) == RTC_HOUR12) + + +/** @defgroup RTC_Interval_Value + * @{ + */ + +#define RTC_INTERVAL_NONE (0X00) +#define RTC_INTERVAL_EVERY_0_5S (0x01) +#define RTC_INTERVAL_EVERY_1S (0x02) +#define RTC_INTERVAL_EVERY_1M (0x03) +#define RTC_INTERVAL_EVERY_1H (0x04) +#define RTC_INTERVAL_EVERY_1D (0x05) +#define RTC_INTERVAL_EVERY_1MO (0x06) + +#define IS_RTC_INTERVAL_PERIOD(per) (per < 7) + +/** @defgroup RTC_Clock_source + * 000：外部晶体时钟LSE + * 010：内置低频时钟LSI + * 100：外部晶体时钟HSE / 128 + * 101：外部晶体时钟HSE / 256 + * 110：外部晶体时钟HSE / 512 + * 111：外部晶体时钟HSE / 1024 + * @{ + */ + +#define RTC_RTCCLK_FROM_LSE (0UL) +#define RTC_RTCCLK_FROM_LSI (2UL << 8) +#define RTC_RTCCLK_FROM_HSE_128 (4UL << 8) +#define RTC_RTCCLK_FROM_HSE_256 (5UL << 8) +#define RTC_RTCCLK_FROM_HSE_512 (6UL << 8) +#define RTC_RTCCLK_FROM_HSE_1024 (7UL << 8) + +#define IS_RTC_RTCCLK_SOURCE(src) (((src) == RTC_RTCCLK_FROM_LSE) || \ + ((src) == RTC_RTCCLK_FROM_LSI) || \ + ((src) == RTC_RTCCLK_FROM_HSE_128) || \ + ((src) == RTC_RTCCLK_FROM_HSE_256) || \ + ((src) == RTC_RTCCLK_FROM_HSE_512) || \ + ((src) == RTC_RTCCLK_FROM_HSE_1024)) + +#define RTC_IT_INTERVAL (1UL << 6) +#define RTC_IT_TAMPOV (1UL << 4) +#define RTC_IT_TAMP (1UL << 3) +#define RTC_IT_AWTIMER (1UL << 2) +#define RTC_IT_ALARMB (1UL << 1) +#define RTC_IT_ALARMA (1UL) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_INTERVAL) || \ + ((IT) == RTC_IT_TAMPOV) || \ + ((IT) == RTC_IT_TAMP) || \ + ((IT) == RTC_IT_AWTIMER) || \ + ((IT) == RTC_IT_ALARMB) || \ + ((IT) == RTC_IT_ALARMA)) +#define IS_RTC_CONFIG_IT(IT) ((((uint8_t)(IT) & 0x20) == 0) && \ + ((uint8_t)(IT) < 0x40)) +#define IS_RTC_CLAER_IT(IT) ((((uint8_t)(IT) & 0x20) == 0) && \ + ((uint8_t)(IT) < 0x40)) + +/** @defgroup RTC_AlarmMask_Definitions + * @{ + */ +#define RTC_AlarmMask_None ((uint32_t)0x00000000) +#define RTC_AlarmMask_WeekSAT ((uint32_t)0x40000000) +#define RTC_AlarmMask_WeekFRI ((uint32_t)0x20000000) +#define RTC_AlarmMask_WeekTHU ((uint32_t)0x10000000) +#define RTC_AlarmMask_WeekWED ((uint32_t)0x08000000) +#define RTC_AlarmMask_WeekTUE ((uint32_t)0x04000000) +#define RTC_AlarmMask_WeekMON ((uint32_t)0x02000000) +#define RTC_AlarmMask_WeekSun ((uint32_t)0x01000000) +#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) +#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) +#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) +#define RTC_AlarmMask_All ((uint32_t)0x7F808080) +#define IS_ALARM_MASK(MASK) (((MASK) & 0x807F7F7F) == (uint32_t)RESET) + + +#define RTC_TamperTrigger_RisingEdge (0UL) +#define RTC_TamperTrigger_FallingEdge (1UL) +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_FallingEdge)) + + +/** @defgroup RTC_Compen_step + * @{ + */ +#define RTC_RTCOUT_AS_LOW (0x0) +#define RTC_RTCOUT_AS_ALARM_A (0x1) +#define RTC_RTCOUT_AS_ALARM_B (0x2) +#define RTC_RTCOUT_AS_AWT (0x3) + +#define IS_RTC_RTCOUT_SOURCE(src) (src < 4) +/* +#define IS_RTC_RTCOUT_SOURCE(src) (((src) == RTC_RTCOUT_AS_LOW) || \ + ((src) == RTC_RTCOUT_AS_ALARM_A) || \ + ((src) == RTC_RTCOUT_AS_ALARM_B) || \ + ((src) == RTC_RTCOUT_AS_AWT)) ) +*/ + +/** @defgroup RTC_TimerSrc_Value +* @{ +*/ + +#define RTC_AWTSOURCE_FROM_RTCCLK_2 (0x0) +#define RTC_AWTSOURCE_FROM_RTCCLK_4 (0x1) +#define RTC_AWTSOURCE_FROM_RTCCLK_8 (0x2) +#define RTC_AWTSOURCE_FROM_RTCCLK_16 (0x3) +#define RTC_AWTSOURCE_FROM_RTC1HZ_1 (0x4) +#define RTC_AWTSOURCE_FROM_RTC1HZ_2 (0x5) +#define RTC_AWTSOURCE_FROM_RTC1HZ_4 (0x6) +#define RTC_AWTSOURCE_FROM_RTC1HZ_8 (0x7) + +#define IS_RTC_AWTTIMER_SOURCE(clk) (clk < 8) +/* +#define IS_RTC_AWTTIMER_SOURCE(clk) (((clk) == RTC_AWTSOURCE_FROM_RTCCLK_2) || \ + ((clk) == RTC_AWTSOURCE_FROM_RTCCLK_4) || \ + ((clk) == RTC_AWTSOURCE_FROM_RTCCLK_8) || \ + ((clk) == RTC_AWTSOURCE_FROM_RTCCLK_16) || \ + ((clk) == RTC_AWTSOURCE_FROM_RTC1HZ_1) || \ + ((clk) == RTC_AWTSOURCE_FROM_RTC1HZ_2) || \ + ((clk) == RTC_AWTSOURCE_FROM_RTC1HZ_4) || \ + ((clk) == RTC_AWTSOURCE_FROM_RTC1HZ_8)) +*/ + +/** + * @} + */ + +/** @defgroup RTC_Compen_Freq + * @{ + */ +#define RTC_COMPENFREQ_AS_4MHZ (0x0UL) +#define RTC_COMPENFREQ_AS_6MHZ (0x1UL) +#define RTC_COMPENFREQ_AS_8MHZ (0x2UL) +#define RTC_COMPENFREQ_AS_12MHZ (0x3UL) +#define RTC_COMPENFREQ_AS_16MHZ (0x4UL) +#define RTC_COMPENFREQ_AS_20MHZ (0x5UL) +#define RTC_COMPENFREQ_AS_24MHZ (0x6UL) +#define RTC_COMPENFREQ_AS_30MHZ (0x7UL) +#define RTC_COMPENFREQ_AS_48MHZ (0x8UL) + +#define IS_RTC_COMPEN_FREQ(clk) (clk < 9) + +/** + * @} + */ + +/** @defgroup RTC_Compen_step + * @{ + */ +#define RTC_COMPENSTEP_0_950PPM (0x0UL) +#define RTC_COMPENSTEP_0_238PPM (0x1UL) +#define RTC_COMPENSTEP_0_119PPM (0x2UL) + +#define IS_RTC_COMPEN_STEP(stp) ((stp) < 3) + +/** + * @} + */ + +#define RTC_COMPEN_SIGN_UP (0UL) +#define RTC_COMPEN_SIGN_DOWN (1UL) +#define IS_RTC_COMPEN_SIGN(SIGN) ((SIGN) < 2) + +#define IS_RTC_COMPEN_VALUE(VAL) (((VAL) & 0xFFFFF000) == RESET) + +/** @defgroup RTC_Month_Day_Definitions + * @{ + */ +#define RTC_Month_January ((uint8_t)0x01) +#define RTC_Month_February ((uint8_t)0x02) +#define RTC_Month_March ((uint8_t)0x03) +#define RTC_Month_April ((uint8_t)0x04) +#define RTC_Month_May ((uint8_t)0x05) +#define RTC_Month_June ((uint8_t)0x06) +#define RTC_Month_July ((uint8_t)0x07) +#define RTC_Month_August ((uint8_t)0x08) +#define RTC_Month_September ((uint8_t)0x09) +#define RTC_Month_October ((uint8_t)0x10) +#define RTC_Month_November ((uint8_t)0x11) +#define RTC_Month_December ((uint8_t)0x12) +#define IS_RTC_MONTH(MON) (((MON) >= 1) && ((MON) <= 12)) +#define IS_RTC_DAY(DAY) (((DAY) >= 1) && ((DAY) <= 31)) + +/** @defgroup RTC_WeekDay_Definitions +* @{ +*/ + +#define RTC_Weekday_Sunday ((uint8_t)0x00) +#define RTC_Weekday_Monday ((uint8_t)0x01) +#define RTC_Weekday_Tuesday ((uint8_t)0x02) +#define RTC_Weekday_Wednesday ((uint8_t)0x03) +#define RTC_Weekday_Thursday ((uint8_t)0x04) +#define RTC_Weekday_Friday ((uint8_t)0x05) +#define RTC_Weekday_Saturday ((uint8_t)0x06) + +#define IS_RTC_WEEKDAY(wek) (wek < 7) + +/** @defgroup RTC_Alarm_Definitions + * @{ + */ +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(dat) (((dat) > 0) && ((dat) <= 31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(wek) (((wek) == RTC_Weekday_Monday) || \ + ((wek) == RTC_Weekday_Tuesday) || \ + ((wek) == RTC_Weekday_Wednesday) || \ + ((wek) == RTC_Weekday_Thursday) || \ + ((wek) == RTC_Weekday_Friday) || \ + ((wek) == RTC_Weekday_Saturday) || \ + ((wek) == RTC_Weekday_Sunday)) + + +/** @defgroup RTC_Time_Definitions + * @{ + */ +#define RTC_12_HOUR_CLOCK 0 +#define RTC_24_HOUR_CLOCK 1 +#define IS_RTC_HOUR12(hor) (((hor) >= 1) && ((hor) <= 12)) +#define IS_RTC_HOUR24(hor) ((hor) <= 23) +#define IS_RTC_MINUTES(min) ((min) <= 59) +#define IS_RTC_SECONDS(sec) ((sec) <= 59) + +/** @defgroup RTC_AM_PM_Definitions + * @{ + */ +#define RTC_H12_AM (0UL) +#define RTC_H12_PM (1UL) +#define IS_RTC_H12_AMPM(apm) (((apm) == RTC_H12_AM) || ((apm) == RTC_H12_PM)) + +/** @defgroup RTC_Year_Date_Definitions + * @{ + */ +#define IS_RTC_YEAR(yer) ((yer) <= 99) + +/** @defgroup RTC_KEY_WORD + * @{ + */ +#define RTC_KEY_WORD1 ((uint8_t)0xCA) +#define RTC_KEY_WORD2 ((uint8_t)0x53) + +#define RTC_KEY_LOCKW ((uint8_t)0x55) + +#define IS_RTC_KEYWORD(kwd) (((kwd) == RTC_KEY_WORD1) || ((kwd) == RTC_KEY_WORD2)) + +#define RTC_UNLOCK() do{ CW_RTC->KEY_f.KEY = RTC_KEY_WORD1;\ + CW_RTC->KEY_f.KEY = RTC_KEY_WORD2; }while (0) +#define RTC_LOCK() do{ CW_RTC->KEY_f.KEY = RTC_KEY_WORD1; \ + CW_RTC->KEY_f.KEY = RTC_KEY_WORD1;}while (0) + + +/** + * @} + */ +#define RTC_DATE_RESET_VALUE ((uint32_t) 0x00000000) +#define RTC_TIME_RESET_VALUE ((uint32_t) 0x12000000) +#define RTC_ALARMA_RESET_VALUE ((uint32_t) 0x12000000) +#define RTC_ALARMB_RESET_VALUE ((uint32_t) 0x12000000) +#define RTC_TAMPDATA_RESET_VALUE ((uint32_t) 0x00000000) +#define RTC_TAMPTIME_RESET_VALUE ((uint32_t) 0x00000000) +#define RTC_AWTARR_RESET_VALUE ((uint32_t) 0x0000FFFF) +#define RTC_IER_RESET_VALUE ((uint32_t) 0x00000000) + + +//============================================================ + +//RTC CONTROLLER REGSITER0 +#define RTC_START_ENABLE() (CW_RTC->CR0_f.START = 1) +#define RTC_START_DISABLE() (CW_RTC->CR0_f.START = 0) + +#define RTC_RTC1HZ_PCLK() (CW_RTC->CR0_f.RTC1HZ = RTC_RTC1HZ_FROM_PCLK) +#define RTC_RTC1HZ_LSE() (CW_RTC->CR0_f.RTC1HZ = RTC_RTC1HZ_FROM_LSE) + +#define RTC_AMPM_12HOUR() (CW_RTC->CR0_f.AMPM = 0) +#define RTC_AMPM_24HOUR() (CW_RTC->CR0_f.AMPM = 1) + +#define RTC_INTERVAL_0_5S() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_0_5S) +#define RTC_INTERVAL_1S() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_1S) +#define RTC_INTERVAL_1M() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_1M) +#define RTC_INTERVAL_1H() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_1H) +#define RTC_INTERVAL_1D() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_1D) +#define RTC_INTERVAL_1MO() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_1MO) + +#define IS_RTC_START() (CW_RTC->CR0 & bv7) + +//============================================================ +//RTC CONTROLLER REGSITER1 +#define RTC_RTCCLK_LSE() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_LSE) +#define RTC_RTCCLK_LSI() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_LIE) +#define RTC_RTCCLK_HSE128() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_HSE_128) +#define RTC_RTCCLK_HSE256() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_HSE_256) +#define RTC_RTCCLK_HSE512() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_HSE_512) +#define RTC_RTCCLK_HSE1024() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_HSE_1024) + +#define RTC_WINDOW_GETVALUE() (CW_RTC->CR1_f.WINDOW) +#define RTC_ACCESS_GETVALUE() (CW_RTC->CR1_f.ACCESS) +#define RTC_ACCESS_SET() (CW_RTC->CR1_f.ACCESS = 1) +#define RTC_ACCESS_RESET() (CW_RTC->CR1_f.ACCESS = 0) + +//============================================================ +//RTC CONTROLLER REGSITER2 +#define RTC_ALARM_A_ENABLE() (CW_RTC->CR2_f.ALARMAEN = 1) +#define RTC_ALARM_A_DISABLE() (CW_RTC->CR2_f.ALARMAEN = 0) +#define RTC_ALARM_B_ENABLE() (CW_RTC->CR2_f.ALARMBEN = 1) +#define RTC_ALARM_B_DISABLE() (CW_RTC->CR2_f.ALARMBEN = 0) +#define RTC_AWT_ENABLE() (CW_RTC->CR2_f.AWTEN = 1) +#define RTC_AWT_DISABLE() (CW_RTC->CR2_f.AWTEN = 0) +#define RTC_TAMP_ENABLE() (CW_RTC->CR2_f.TAMPEN = 1) +#define RTC_TAMP_DISABLE() (CW_RTC->CR2_f.TAMPEN = 0) +#define RTC_RTCOUT_LOW() (CW_RTC->CR2_f.RTCOUT = RTC_RTCOUT_AS_LOW) +#define RTC_RTCOUT_ALARM_A() (CW_RTC->CR2_f.RTCOUT = RTC_RTCOUT_AS_ALARM_A) +#define RTC_RTCOUT_ALARM_B() (CW_RTC->CR2_f.RTCOUT = RTC_RTCOUT_AS_ALARM_B) +#define RTC_RTCOUT_AWT() (CW_RTC->CR2_f.RTCOUT = RTC_RTCOUT_AS_AWT) +#define RTC_TAMPEDGE_FALL() (CW_RTC->CR2_f.TAMPEDGE = 1) +#define RTC_TAMPEDGE_RISE() (CW_RTC->CR2_f.TAMPEDGE = 0) +#define RTC_AWTSOURCE_RTCLK_2() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTCCLK_2) +#define RTC_AWTSOURCE_RTCLK_4() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTCCLK_4) +#define RTC_AWTSOURCE_RTCLK_8() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTCCLK_8) +#define RTC_AWTSOURCE_RTCLK_16() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTCCLK_16) +#define RTC_AWTSOURCE_RTC1HZ_1() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTC1HZ_1) +#define RTC_AWTSOURCE_RTC1HZ_2() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTC1HZ_2) +#define RTC_AWTSOURCE_RTC1HZ_4() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTC1HZ_4) +#define RTC_AWTSOURCE_RTC1HZ_8() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTC1HZ_8) + +//============================================================ +//RTC COMPEN REGSITER +#define RTC_COMPEN_ENABLE() (CW_RTC->COMPEN_f.EN = 1) +#define RTC_COMPEN_DISABLE() (CW_RTC->COMPEN_f.EN = 0) + +#define RTC_COMPEN_STEP_0_950PPM() (CW_RTC->COMPEN_f.STEP = RTC_COMPENSTEP_0_950PPM) +#define RTC_COMPEN_STEP_0_238PPM() (CW_RTC->COMPEN_f.STEP = RTC_COMPENSTEP_0_238PPM) +#define RTC_COMPEN_STEP_0_119PPM() (CW_RTC->COMPEN_f.STEP = RTC_COMPENSTEP_0_119PPM) + +//============================================================ +//RTC ALARM A CONTROLLER REGSITER +#define RTC_ALARMA_HOURMASK_ENABLE() (CW_RTC->ALARMA_f.HOURMASK = 1) +#define RTC_ALARMA_HOURMASK_DISABLE() (CW_RTC->ALARMA_f.HOURMASK = 0) + +#define RTC_ALARMA_MINUTEMASK_ENABLE() (CW_RTC->ALARMA_f.MINUTEMASK = 1) +#define RTC_ALARMA_MINUTEMASK_DISABLE() (CW_RTC->ALARMA_f.MINUTEMASK = 0) + +#define RTC_ALARMA_SECONDMASK_ENABLE() (CW_RTC->ALARMA_f.SECONDMASK = 1) +#define RTC_ALARMA_SECONDMASK_DISABLE() (CW_RTC->ALARMA_f.SECONDMASK = 0) + +//============================================================ +//RTC ALARM B CONTROLLER REGSITER +#define RTC_ALARMB_HOURMASK_ENABLE() (CW_RTC->ALARMB_f.HOURMASK = 1) +#define RTC_ALARMB_HOURMASK_DISABLE() (CW_RTC->ALARMB_f.HOURMASK = 0) + +#define RTC_ALARMB_MINUTEMASK_ENABLE() (CW_RTC->ALARMB_f.MINUTEMASK = 1) +#define RTC_ALARMB_MINUTEMASK_DISABLE() (CW_RTC->ALARMB_f.MINUTEMASK = 0) + +#define RTC_ALARMB_SECONDMASK_ENABLE() (CW_RTC->ALARMB_f.SECONDMASK = 1) +#define RTC_ALARMB_SECONDMASK_DISABLE() (CW_RTC->ALARMB_f.SECONDMASK = 0) + +//============================================================ +//RTC INTERRUPT ENABLE REGSITER +#define RTC_IE_INTERVAL_ENABLE() (CW_RTC->IER_f.INTERVAL = 1) +#define RTC_IE_INTERVAL_DISABLE() (CW_RTC->IER_f.INTERVAL = 0) + +#define RTC_IE_TAMPOV_ENABLE() (CW_RTC->IER_f.TAMPOV = 1) +#define RTC_IE_TAMPOV_DISABLE() (CW_RTC->IER_f.TAMPOV = 0) + +#define RTC_IE_TAMP_ENABLE() (CW_RTC->IER_f.TAMP = 1) +#define RTC_IE_TAMP_DISABLE() (CW_RTC->IER_f.TAMP = 0) + +#define RTC_IE_AWTIMER_ENABLE() (CW_RTC->IER_f.AWTIMER = 1) +#define RTC_IE_AWTIMER_DISABLE() (CW_RTC->IER_f.AWTIMER = 0) + +#define RTC_IE_ALARMA_ENABLE() (CW_RTC->IER_f.ALARMA = 1) +#define RTC_IE_ALARMA_DISABLE() (CW_RTC->IER_f.ALARMA = 0) + +#define RTC_IE_ALARMB_ENABLE() (CW_RTC->IER_f.ALARMB = 1) +#define RTC_IE_ALARMB_DISABLE() (CW_RTC->IER_f.ALARMB = 0) + +//============================================================ +//RTC INTERRUPT CLEAR REGSITER +#define RTC_IE_INTERVAL_CLEAR() (CW_RTC->ICR_f.INTERVAL = 0) +#define RTC_IE_TAMPOV_CLEAR() (CW_RTC->ICR_f.TAMPOV = 0) +#define RTC_IE_TAMP_CLEAR() (CW_RTC->ICR_f.TAMP = 0) +#define RTC_IE_AWTIMER_CLEAR() (CW_RTC->ICR_f.AWTIMER = 0) +#define RTC_IE_ALARMA_CLEAR() (CW_RTC->ICR_f.ALARMA = 0) +#define RTC_IE_ALARMB_CLEAR() (CW_RTC->ICR_f.ALARMB = 0) + + + +//============================================================ +// CW32F030 RTC HAL API Function（Total： 14），及所有位域的宏命令 +//============================================================ +void RTC_DeInit(void); +ErrorStatus RTC_Init(RTC_InitTypeDef *RTC_InitStruct); +void RTC_Cmd(FunctionalState NewState); +ITStatus RTC_GetITState(uint32_t RTC_ITState); +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); +void RTC_ClearITPendingBit(uint32_t RTC_IT); +void RTC_SetTime(RTC_TimeTypeDef *RTC_TimeStruct); +void RTC_SetDate(RTC_DateTypeDef *RTC_Date); +void RTC_GetTime(RTC_TimeTypeDef *RTC_TimeStruct); +void RTC_GetDate(RTC_DateTypeDef *RTC_Date); +void RTC_SetAlarm(uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct); +void RTC_GetAlarm(uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct); +void RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); +void RTC_TamperTriggerConfig(uint32_t RTC_TamperTrigger); +void RTC_TamperCmd(FunctionalState NewState); +void RTC_GetTamperDate(RTC_DateTypeDef *RTC_Date); +void RTC_GetTamperTime(RTC_TimeTypeDef *RTC_TimeStruct); +void RTC_OutputConfig(uint8_t RTC_Output); +void RTC_AWTConfig(RTC_AWTTypeDef *RCT_AWTStruct); +void RTC_AWTCmd(FunctionalState NewState); +void RTC_SetInterval(uint8_t Period); +void RTC_SetClockSource(uint32_t RTC_ClockSource); +void RTC_CalibrationConfig(RTC_CalibTypeDef *RTC_CalibStruct); +void RTC_CalibrationCmd(FunctionalState NewState); +uint8_t RTC_BinToBCD(uint8_t Value); +uint8_t RTC_BCDToBin(uint8_t Value); + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32F030_RTC_H */ +/** + * @} + */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_spi.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_spi.h new file mode 100644 index 0000000..178ad68 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_spi.h @@ -0,0 +1,306 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_SPI_H +#define __CW32F030_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" + +/****************************************************************************** + * type definitions ('typedef') + ******************************************************************************/ +typedef struct +{ + uint16_t SPI_Direction; /*!< 数据通信模式：全双工，单工单发，单工单收，单线半双工 + 参数取值 @ref SPI_Data_Direction */ + + uint16_t SPI_Mode; /*!< SPI主从模式 + 参数取值 @ref SPI_Mode */ + + uint16_t SPI_DataSize; /*!< 单帧数据宽度 + 参数取值 @ref SPI_Data_Size */ + + uint16_t SPI_CPOL; /*!< 串行时钟待机极性 + 参数取值 @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /*!< 串行时钟相位配置 + 参数取值 @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /*!< CS管脚配置 + 参数取值 @ref SPI_Slave_Select_Management */ + + uint16_t SPI_BaudRatePrescaler; /*!< 主机模式下SCK波特率配置 + 参数取值 @ref SPI_BaudRate_Prescaler */ + + uint16_t SPI_FirstBit; /*!< 数据帧高低位顺序选择 + 参数取值 @ref SPI_MSB_LSB_Transmission */ + + uint16_t SPI_Speed; /*!< 设置SPI的采样是否延后，高速下延后，慢速下不用延后 + 参数取值 @ref SPI_Speed */ +} SPI_InitTypeDef; + +/****************************************************************************** + * pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** @defgroup SPI_Data_Direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) //双向全双工 +#define SPI_Direction_1Line_TxOnly ((uint16_t)0x4000) //单工单发 +#define SPI_Direction_1Line_RxOnly ((uint16_t)0x8000) //单工单收 +#define SPI_Direction_1Lines_HalfDuplex ((uint16_t)0xC000) //单线半双工 +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_1Lines_HalfDuplex) || \ + ((MODE) == SPI_Direction_1Line_TxOnly) || \ + ((MODE) == SPI_Direction_1Line_RxOnly)) + +/** @defgroup SPI_Mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0004) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) + +/** @defgroup SPI_Data_Size + * @{ + */ + +#define SPI_DataSize_4b ((uint16_t)0x0C00) +#define SPI_DataSize_5b ((uint16_t)0x1000) +#define SPI_DataSize_6b ((uint16_t)0x1400) +#define SPI_DataSize_7b ((uint16_t)0x1800) +#define SPI_DataSize_8b ((uint16_t)0x1C00) +#define SPI_DataSize_9b ((uint16_t)0x2000) +#define SPI_DataSize_10b ((uint16_t)0x2400) +#define SPI_DataSize_11b ((uint16_t)0x2800) +#define SPI_DataSize_12b ((uint16_t)0x2C00) +#define SPI_DataSize_13b ((uint16_t)0x3000) +#define SPI_DataSize_14b ((uint16_t)0x3400) +#define SPI_DataSize_15b ((uint16_t)0x3800) +#define SPI_DataSize_16b ((uint16_t)0x3C00) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_4b) || \ + ((DATASIZE) == SPI_DataSize_5b) || \ + ((DATASIZE) == SPI_DataSize_6b) || \ + ((DATASIZE) == SPI_DataSize_7b) || \ + ((DATASIZE) == SPI_DataSize_8b) || \ + ((DATASIZE) == SPI_DataSize_9b) || \ + ((DATASIZE) == SPI_DataSize_10b) || \ + ((DATASIZE) == SPI_DataSize_11b) || \ + ((DATASIZE) == SPI_DataSize_12b) || \ + ((DATASIZE) == SPI_DataSize_13b) || \ + ((DATASIZE) == SPI_DataSize_14b) || \ + ((DATASIZE) == SPI_DataSize_15b) ||\ + ((DATASIZE) == SPI_DataSize_16b)) + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) + +/** @defgroup SPI_Slave_Select_Management + * @{ + */ + +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) + +/** @defgroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128)) + +/** @defgroup SPI_MSB_LSB_Transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) + +/** @defgroup SPI_Speed + * @{ + */ + +#define SPI_Speed_Low ((uint16_t)0x0000) +#define SPI_Speed_High ((uint16_t)0x0100) +#define IS_SPI_SPEED(SPEED) (((SPEED) == SPI_Speed_Low) || \ + ((SPEED) == SPI_Speed_High)) + +/** @defgroup SPI_Direction_Transmit_Receive + * @{ + */ + +#define SPI_Direction_Tx ((uint8_t)0x01) +#define SPI_Direction_Rx ((uint8_t)0x00) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Tx) || \ + ((DIRECTION) == SPI_Direction_Rx)) + +/** @defgroup SPI_DMA_Requests + * @{ + */ + +#define SPI_DMAReq_Tx ((uint32_t)0x00020000) +#define SPI_DMAReq_Rx ((uint32_t)0x00010000) +#define IS_SPI_DMAREQ(DMAREQ) (((DMAREQ) == SPI_DMAReq_Tx) || \ + ((DMAREQ) == SPI_DMAReq_Rx) || \ + ((DMAREQ) == (SPI_DMAReq_Tx | SPI_DMAReq_Rx))) + +/** @defgroup SPI_NSS_Internal_Software_Management + * @{ + */ + +#define SPI_NSSInternalSoft_Set ((uint8_t)0x01) +#define SPI_NSSInternalSoft_Reset ((uint8_t)0x00) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) + +/** @defgroup SPI_MISO_Output_config + * @{ + */ + +#define SPI_MISOOutput_HD ((uint8_t)0x01) +#define SPI_MISOOutput_CMOS ((uint8_t)0x00) +#define IS_SPI_MISOOUTPUT(MISOOUTPUT) (((MISOOUTPUT) == SPI_MISOOutput_HD) || \ + ((MISOOUTPUT) == SPI_MISOOutput_CMOS)) + +/** @defgroup SPI_Interrupts + * @{ + */ + +#define SPI_IT_MODF ((uint8_t)0x80) +#define SPI_IT_SSERR ((uint8_t)0x40) +#define SPI_IT_OV ((uint8_t)0x20) +#define SPI_IT_UD ((uint8_t)0x10) +#define SPI_IT_SSR ((uint8_t)0x08) +#define SPI_IT_SSF ((uint8_t)0x04) +#define SPI_IT_RXNE ((uint8_t)0x02) +#define SPI_IT_TXE ((uint8_t)0x01) +#define IS_SPI_IT(IT) ((IT) <= 0xFF && ((IT) != (uint8_t)0x00)) +#define IS_SPI_CLEAR_IT(IT) ((((IT) & (uint8_t)0x01) == 0x00) && ((IT) != (uint8_t)0x00)) + +/** @defgroup SPI_Flags + * @{ + */ + +#define SPI_FLAG_SSLVL ((uint16_t)0x0200) +#define SPI_FLAG_BUSY ((uint16_t)0x0100) +#define SPI_FLAG_MODF ((uint16_t)0x0080) +#define SPI_FLAG_SSERR ((uint16_t)0x0040) +#define SPI_FLAG_OV ((uint16_t)0x0020) +#define SPI_FLAG_UD ((uint16_t)0x0010) +#define SPI_FLAG_SSR ((uint16_t)0x0008) +#define SPI_FLAG_SSF ((uint16_t)0x0004) +#define SPI_FLAG_RXNE ((uint16_t)0x0002) +#define SPI_FLAG_TXE ((uint16_t)0x0001) +#define IS_SPI_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC00) == 0x00) && ((FLAG) != (uint16_t)0x00)) +#define IS_SPI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFF01) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == CW_SPI1) || \ + ((PERIPH) == CW_SPI2)) + +/****************************************************************************** +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ + + +/****************************************************************************** +* Global function prototypes +******************************************************************************/ + +/* 数据收发 */ +void SPI_SendData(SPI_TypeDef *SPIx, uint16_t Data); +uint16_t SPI_ReceiveData(SPI_TypeDef *SPIx); + +/* 初始化 */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); +void SPI1_DeInit(void); +void SPI2_DeInit(void); + +/* 使能或禁止SPIx */ +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); + +/* 中断及标志 */ +void SPI_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +ITStatus SPI_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); +void SPI_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); +FlagStatus SPI_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_FLAG); +void SPI_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_FLAG); + +/* 单线半双工数据传输方向配置 */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint8_t SPI_Direction); + +/* DMA */ +void SPI_DMACmd(SPI_TypeDef *SPIx, uint32_t SPI_DMAReq, FunctionalState NewState); + +/* 软件内部配置NSS */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint8_t SPI_NSSInternalSoft); + +/* 设置数据帧的位宽 */ +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); + +/* 从模式MISO输出配置*/ +void SPI_MISOOutputConfig(SPI_TypeDef *SPIx, uint8_t SPI_MISOOutput); + +/* 清空发送缓冲区和移位寄存器 */ +void SPI_FlushSendBuff(SPI_TypeDef *SPIx); + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32F030_SPI_H */ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_systick.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_systick.h new file mode 100644 index 0000000..4b36bdd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_systick.h @@ -0,0 +1,77 @@ +/** + * @file cw32f030_systick.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-13 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_SYSTICK_H +#define __CW32F030_SYSTICK_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" + +/* Exported types ------------------------------------------------------------*/ + +typedef enum +{ + TICK_FREQ_10HZ = 100U, + TICK_FREQ_100HZ = 10U, + TICK_FREQ_1KHZ = 1U, + TICK_FREQ_DEFAULT = TICK_FREQ_1KHZ +} TickFreqTypeDef; + +#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */ +#define MAX_SYSTICK_DELAY 0xFFFFFFFFU +#define IS_TICKFREQ(FREQ) (((FREQ) == TICK_FREQ_10HZ) || \ + ((FREQ) == TICK_FREQ_100HZ) || \ + ((FREQ) == TICK_FREQ_1KHZ)) + +/* Exported functions --------------------------------------------------------*/ +void InitTick(uint32_t HclkFreq); +void SysTickDelay(uint32_t Delay); +uint32_t GetTick(void); +void SuspendTick(void); +void ResumeTick(void); +void SysTick_Handler(void); + +/* Exported variables ---------------------------------------------------------*/ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern TickFreqTypeDef uwTickFreq; + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CW32F030_SYSTICK_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_uart.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_uart.h new file mode 100644 index 0000000..4daab93 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_uart.h @@ -0,0 +1,282 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_UART_H +#define __CW32F030_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" + +/****************************************************************************** + * type definitions ('typedef') + ******************************************************************************/ + +/** + * @brief USART Init Structure definition + */ + +typedef struct +{ + uint32_t USART_BaudRate; /*!< 波特率 + 计算公式: + - USART_Over = 00， BaudRate = UCLK / (16 * BRRI + BRRF) + - USART_Over = 01， BaudRate = UCLK / (8 * BRRI) + - USART_Over = 10， BaudRate = UCLK / (4 * BRRI) + - USART_Over = 11， BaudRate = (256 * UCLK) / BRRI */ + + uint16_t USART_Over; /*!< 采样方式 + 参数取值 @ref USART_Over */ + + uint16_t USART_Source; /*!< 传输时钟源UCLK + 参数取值 @ref USART_Source */ + + uint32_t USART_UclkFreq; /*!< 传输时钟UCLK频率 Hz */ + + uint16_t USART_StartBit; /*!< 起始位判定方式 + 参数取值 @ref USART_Start_Bit */ + + uint16_t USART_StopBits; /*!< 停止位长度 + 参数取值 @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /*!< 校验方式 + 参数取值 @ref USART_Parity + @note 当设置为无校验时，数据字长为8位； + 当设置为有校验时，数据字长自动设置为9位 */ + + uint16_t USART_Mode; /*!< 发送/接收使能 + 参数取值 @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /*!< 硬件流控 + 参数取值 @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + uint16_t USART_Clock; /*!< USART同步模式使能/失能 + 参数取值 @ref USART_Clock */ + + uint16_t USART_Source; /*!< 传输时钟源UCLK + 参数取值 @ref USART_Source */ +} USART_ClockInitTypeDef; + +/****************************************************************************** + * pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** @defgroup USART_Over + * @{ + */ + +#define USART_Over_16 ((uint16_t)0x0000) +#define USART_Over_8 ((uint16_t)0x0200) +#define USART_Over_4 ((uint16_t)0x0400) +#define USART_Over_sp ((uint16_t)0x0600) +#define IS_USART_Over(Over) (((Over) == USART_Over_16) || \ + ((Over) == USART_Over_8) || \ + ((Over) == USART_Over_4) || \ + ((Over) == USART_Over_sp)) + +/** @defgroup USART_Source + * @{ + */ + +#define USART_Source_PCLK ((uint16_t)0x0000) +#define USART_Source_LSE ((uint16_t)0x0200) +#define USART_Source_LSI ((uint16_t)0x0300) +#define IS_USART_Source(Source) (((Source) == USART_Source_PCLK) || \ + ((Source) == USART_Source_LSE) || \ + ((Source) == USART_Source_LSI)) + +/** @defgroup USART_Start_Bit + * @{ + */ + +#define USART_StartBit_FE ((uint16_t)0x0000) //RXD下降沿 +#define USART_StartBit_LL ((uint16_t)0x0100) //RXD低电平 +#define IS_USART_StartBit(StartBit) (((StartBit) == USART_StartBit_FE) || \ + ((StartBit) == USART_StartBit_LL)) + +/** @defgroup USART_Stop_Bits + * @{ + */ + +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_2 ((uint16_t)0x0020) +#define USART_StopBits_1_5 ((uint16_t)0x0010) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) + +/** @defgroup USART_Parity + * @{ + */ + +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0008) +#define USART_Parity_Odd ((uint16_t)0x000C) +#define USART_Parity_User ((uint16_t)0x0004) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No)|| \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd) || \ + ((PARITY) == USART_Parity_User)) + +/** @defgroup USART_Mode + * @{ + */ + +#define USART_Mode_Tx ((uint16_t)0x0001) +#define USART_Mode_Rx ((uint16_t)0x0002) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFFC) == 0x00) && ((MODE) != (uint16_t)0x00)) + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ + +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0008) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0004) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x000C) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) + +/** @defgroup USART_Clock + * @{ + */ + +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0040) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) + +/** @defgroup USART_Inversion_Pins + * @{ + */ + +#define USART_InvPin_Tx ((uint16_t)0x0020) +#define USART_InvPin_Rx ((uint16_t)0x0010) +#define IS_USART_INVERSTION_PIN(INVPIN) ((((INVPIN) & (uint16_t)0xFFCF) == 0x00) && ((INVPIN) != (uint16_t)0x00)) + +/** @defgroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** @defgroup USART_Interrupt + * @{ + */ + +#define USART_IT_CTS ((uint16_t)0x0040) +#define USART_IT_PE ((uint16_t)0x0010) +#define USART_IT_FE ((uint16_t)0x0008) +#define USART_IT_RC ((uint16_t)0x0004) +#define USART_IT_TC ((uint16_t)0x0002) +#define USART_IT_TXE ((uint16_t)0x0001) +#define IS_USART_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x00) && ((IT) != (uint16_t)0x00)) +#define IS_USART_CLEAR_IT(IT) ((((IT) & (uint16_t)0xFFA1) == 0x00) && ((IT) != (uint16_t)0x00)) + +/** @defgroup USART_Flags + * @{ + */ + +#define USART_FLAG_TXBUSY ((uint16_t)0x0100) +#define USART_FLAG_CTSLV ((uint16_t)0x0080) +#define USART_FLAG_CTS ((uint16_t)0x0040) +#define USART_FLAG_MATCH ((uint16_t)0x0020) +#define USART_FLAG_PE ((uint16_t)0x0010) +#define USART_FLAG_FE ((uint16_t)0x0008) +#define USART_FLAG_RC ((uint16_t)0x0004) +#define USART_FLAG_TC ((uint16_t)0x0002) +#define USART_FLAG_TXE ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFE00) == 0x00) && ((FLAG) != (uint16_t)0x00)) +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFA1) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) <= 0x00F42400)) +#define IS_USART_UCLKFREQ(UCLKFREQ) (((UCLKFREQ) > 0) && ((UCLKFREQ) <= 0x03D09000)) +#define IS_USART_DATA_16BIT(DATA) ((DATA) <= 0x1FF) +#define IS_USART_DATA_8BIT(DATA) ((DATA) <= 0xFF) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xFF) +#define IS_USART_ADDRESSMSK(ADDRESSMSK) ((ADDRESSMSK) <= 0xFF) +#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == CW_UART1) || \ + ((PERIPH) == CW_UART2) || \ + ((PERIPH) == CW_UART3)) + +/****************************************************************************** +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ + + +/****************************************************************************** +* Global function prototypes +******************************************************************************/ + +/* 数据收发 */ +void USART_SendData(UART_TypeDef *UARTx, uint16_t Data); +void USART_SendData_8bit(UART_TypeDef *UARTx, uint8_t Data); +uint16_t USART_ReceiveData(UART_TypeDef *USARTx); +uint8_t USART_ReceiveData_8bit(UART_TypeDef *USARTx); + +/* 初始化 */ +void USART_Init(UART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); +void USART_StructInit(USART_InitTypeDef *USART_InitStruct); +void USART_ClockInit(UART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); +void UART1_DeInit(void); +void UART2_DeInit(void); +void UART3_DeInit(void); + +/* 中断及标志 */ +void USART_ITConfig(UART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); +ITStatus USART_GetITStatus(UART_TypeDef *USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(UART_TypeDef *USARTx, uint16_t USART_IT); +FlagStatus USART_GetFlagStatus(UART_TypeDef *USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(UART_TypeDef *USARTx, uint16_t USART_FLAG); + +/* 发送和接收控制 */ +void USART_DirectionModeCmd(UART_TypeDef *USARTx, uint16_t USART_DirectionMode, FunctionalState NewState); +void USART_InvPinCmd(UART_TypeDef *USARTx, uint16_t USART_InvPin, FunctionalState NewState); + +/* 半双工通信 */ +void USART_HalfDuplexCmd(UART_TypeDef *USARTx, FunctionalState NewState); + +/* DMA */ +void USART_DMACmd(UART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); + +/* 多机通信 */ +void USART_SetMultiMode(UART_TypeDef *USARTx, uint8_t USART_Address, uint8_t USART_AddressMsK); + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32F030_UART_H */ +/** + * @} + */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_vc.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_vc.h new file mode 100644 index 0000000..0aef4e8 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_vc.h @@ -0,0 +1,493 @@ +/** + * @file cw32f030_vc.h + * @author WHXY + * @brief + * @version 0.2 + * @date 2021-12-20 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +#ifndef __CW32F030_VC_H +#define __CW32F030_VC_H + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "base_types.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup VcGroup Voltage Comparator (VC) + ** + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +#define VC_INT_PRIORITY ((uint32_t)3) /*VC interrupt priority (lowest by default) */ + +/** @defgroup VC_interrupts_definition + * @{ + */ +#define VC_IT_HIGH ((uint16_t)0x0080) +#define VC_IT_RISE ((uint16_t)0x0040) +#define VC_IT_FALL ((uint16_t)0x0020) + + +#define IS_VC_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x00) && ((IT) != 0x00)) +#define IS_VC_GET_IT(IT) (((IT) == VC_IT_HIGH) || \ + ((IT) == VC_IT_RISE) || \ + ((IT) == VC_IT_FALL)) + +/** @defgroup VC_flags_definition + * @{ + */ +#define VC_FLAG_READY ((uint16_t)0x0004) +#define VC_FLAG_FLTV ((uint16_t)0x0002) +#define VC_FLAG_INTF ((uint16_t)0x0001) + +#define IS_VC_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFF00) == 0x00) && ((FLAG) != 0x00)) +#define IS_VC_GET_FLAG(FLAG) (((FLAG) == VC_FLAG_READY) || \ + ((FLAG) == VC_FLAG_FLTV) || \ + ((FLAG) == VC_FLAG_INTF)) + +/** @defgroup VC_DivEn + * @{ + */ +#define VC_Div_Disable ((uint32_t)0x00000000) +#define VC_Div_Enable ((uint32_t)0x00000040) + +#define IS_VC_DIV_EN(DIV_EN) (((DIV_EN) == VC_Div_Disable) || \ + ((DIV_EN) == VC_Div_Enable)) + +/** @defgroup VC_DivVref + * @{ + */ +#define VC_DivVref_VDDA ((uint32_t)0x00000000) +#define VC_DivVref_ADC ((uint32_t)0x00000080) + +#define IS_VC_DIV_VREF(DIV_VREF) (((DIV_VREF) == VC_DivVref_VDDA) || \ + ((DIV_VREF) == VC_DivVref_ADC)) + +/** @defgroup VC_InputP + * @{ + * VC1 VC2 + * 输入通道0 PA00 输入通道0 PA05 + * 输入通道1 PA01 输入通道1 PA06 + * 输入通道2 PA02 输入通道2 PA07 + * 输入通道3 PA03 输入通道3 PB00 + * 输入通道4 PA04 输入通道4 PB01 + * 输入通道5 PA05 输入通道5 PB02 + * 输入通道6 PA06 输入通道6 PB10 + * 输入通道7 PA07 输入通道7 PB11 + */ +#define VC_InputP_Ch0 ((uint32_t)0x00000000) +#define VC_InputP_Ch1 ((uint32_t)0x00000100) +#define VC_InputP_Ch2 ((uint32_t)0x00000200) +#define VC_InputP_Ch3 ((uint32_t)0x00000300) +#define VC_InputP_Ch4 ((uint32_t)0x00000400) +#define VC_InputP_Ch5 ((uint32_t)0x00000500) +#define VC_InputP_Ch6 ((uint32_t)0x00000600) +#define VC_InputP_Ch7 ((uint32_t)0x00000700) + + +#define IS_VC_INPUT_P(INPUT_P) (((INPUT_P) == VC_InputP_Ch0) || \ + ((INPUT_P) == VC_InputP_Ch1) || \ + ((INPUT_P) == VC_InputP_Ch2) || \ + ((INPUT_P) == VC_InputP_Ch3) || \ + ((INPUT_P) == VC_InputP_Ch4) || \ + ((INPUT_P) == VC_InputP_Ch5) || \ + ((INPUT_P) == VC_InputP_Ch6) || \ + ((INPUT_P) == VC_InputP_Ch7)) + +/** @defgroup VC_InputN + * @{ + * VC1 VC2 + * 输入通道0 PA00 输入通道0 PA05 + * 输入通道1 PA01 输入通道1 PA06 + * 输入通道2 PA02 输入通道2 PA07 + * 输入通道3 PA03 输入通道3 PB00 + * 输入通道4 PA04 输入通道4 PB01 + * 输入通道5 PA05 输入通道5 PB02 + * 输入通道6 PA06 输入通道6 PB10 + * 输入通道7 PA07 输入通道7 PB11 + * VDDA分压 VDDA分压 + * ADC VREF ADC VREF + * BGR 1.2V BGR 1.2V + * 温度传感器 温度传感器 + */ +#define VC_InputN_Ch0 ((uint32_t)0x00000000) +#define VC_InputN_Ch1 ((uint32_t)0x00001000) +#define VC_InputN_Ch2 ((uint32_t)0x00002000) +#define VC_InputN_Ch3 ((uint32_t)0x00003000) +#define VC_InputN_Ch4 ((uint32_t)0x00004000) +#define VC_InputN_Ch5 ((uint32_t)0x00005000) +#define VC_InputN_Ch6 ((uint32_t)0x00006000) +#define VC_InputN_Ch7 ((uint32_t)0x00007000) +#define VC_InputN_DivOut ((uint32_t)0x00008000) +#define VC_InputN_AdcVref ((uint32_t)0x00009000) +#define VC_InputN_Bgr1P2 ((uint32_t)0x0000A000) +#define VC_InputN_Ts ((uint32_t)0x0000B000) + +#define IS_VC_INPUT_N(INPUT_N) (((INPUT_N) == VC_InputN_Ch0) || \ + ((INPUT_N) == VC_InputN_Ch1) || \ + ((INPUT_N) == VC_InputN_Ch2) || \ + ((INPUT_N) == VC_InputN_Ch3) || \ + ((INPUT_N) == VC_InputN_Ch4) || \ + ((INPUT_N) == VC_InputN_Ch5) || \ + ((INPUT_N) == VC_InputN_Ch6) || \ + ((INPUT_N) == VC_InputN_Ch7) || \ + ((INPUT_N) == VC_InputN_DivOut) || \ + ((INPUT_N) == VC_InputN_AdcVref) || \ + ((INPUT_N) == VC_InputN_Bgr1P2) || \ + ((INPUT_N) == VC_InputN_Ts)) + +/** @defgroup VC_Hys + * @{ + */ +#define VC_Hys_Off ((uint32_t)0x00000000) +#define VC_Hys_10mV ((uint32_t)0x00000008) +#define VC_Hys_20mV ((uint32_t)0x00000010) +#define VC_Hys_30mV ((uint32_t)0x00000018) + +#define IS_VC_HYS(HYS) (((HYS) == VC_Hys_Off) || \ + ((HYS) == VC_Hys_10mV) || \ + ((HYS) == VC_Hys_20mV) || \ + ((HYS) == VC_Hys_30mV)) + +/** @defgroup VC_Resp + * @{ + */ +#define VC_Resp_ExtraLow ((uint32_t)0x00000000) +#define VC_Resp_Low ((uint32_t)0x00000002) +#define VC_Resp_Medium ((uint32_t)0x00000004) +#define VC_Resp_High ((uint32_t)0x00000006) + +#define IS_VC_RESP(RESP) (((RESP) == VC_Resp_ExtraLow) || \ + ((RESP) == VC_Resp_Low) || \ + ((RESP) == VC_Resp_Medium) || \ + ((RESP) == VC_Resp_High)) + +/** @defgroup VC_FilterEn + * @{ + */ +#define VC_Filter_Disable ((uint32_t)0x00000000) +#define VC_Filter_Enable ((uint32_t)0x00000001) + +#define IS_VC_FILTER(FILTER) (((FILTER) == VC_Filter_Disable) || \ + ((FILTER) == VC_Filter_Enable)) + +/** @defgroup VC_FilterClk + * @{ + */ +#define VC_FltClk_RC150K ((uint32_t)0x00000000) +#define VC_FltClk_PCLK ((uint32_t)0x00000010) + +#define IS_VC_FLT_CLK(FLT_CLK) (((FLT_CLK) == VC_FltClk_RC150K) || \ + ((FLT_CLK) == VC_FltClk_PCLK)) + +/** @defgroup VC_FilterTime + * @{ + */ +#define VC_FltTime_1Clk ((uint32_t)0x00000000) +#define VC_FltTime_3Clk ((uint32_t)0x00000002) +#define VC_FltTime_7Clk ((uint32_t)0x00000004) +#define VC_FltTime_15Clk ((uint32_t)0x00000006) +#define VC_FltTime_63Clk ((uint32_t)0x00000008) +#define VC_FltTime_255Clk ((uint32_t)0x0000000A) +#define VC_FltTime_1023Clk ((uint32_t)0x0000000C) +#define VC_FltTime_4095Clk ((uint32_t)0x0000000E) + + +#define IS_VC_FLT_TIME(FLT_TIME) (((FLT_TIME) == VC_FltTime_1Clk)|| \ + ((FLT_TIME) == VC_FltTime_3Clk) || \ + ((FLT_TIME) == VC_FltTime_7Clk) || \ + ((FLT_TIME) == VC_FltTime_15Clk) || \ + ((FLT_TIME) == VC_FltTime_63Clk) || \ + ((FLT_TIME) == VC_FltTime_255Clk) || \ + ((FLT_TIME) == VC_FltTime_1023Clk) || \ + ((FLT_TIME) == VC_FltTime_4095Clk)) + +/** @defgroup VC_WindowEn + * @{ + */ +#define VC_Window_Disable ((uint32_t)0x00000000) +#define VC_Window_Enable ((uint32_t)0x00000080) + +#define IS_VC_WINDOW(WINDOW) (((WINDOW) == VC_Window_Disable) || \ + ((WINDOW) == VC_Window_Enable)) + +/** @defgroup VC_Polarity + * @{ + */ +#define VC_Polarity_Low ((uint32_t)0x00000000) +#define VC_Polarity_High ((uint32_t)0x00000040) + +#define IS_VC_POLARITY(POLARITY) (((POLARITY) == VC_Polarity_Low) || \ + ((POLARITY) == VC_Polarity_High)) + +/** @defgroup VC_BlankFlt + * @{ + */ +#define VC_BlankFlt_4Clk ((uint32_t)0x00000000) +#define VC_BlankFlt_8Clk ((uint32_t)0x00002000) +#define VC_BlankFlt_16Clk ((uint32_t)0x00004000) +#define VC_BlankFlt_32Clk ((uint32_t)0x00006000) +#define VC_BlankFlt_64Clk ((uint32_t)0x00008000) +#define VC_BlankFlt_128Clk ((uint32_t)0x0000A000) +#define VC_BlankFlt_256Clk ((uint32_t)0x0000C000) +#define VC_BlankFlt_512Clk ((uint32_t)0x0000E000) + +#define IS_VC_BLANK_FLT(BLANK_FLT) (((BLANK_FLT) == VC_BlankFlt_4Clk)|| \ + ((BLANK_FLT) == VC_BlankFlt_8Clk) || \ + ((BLANK_FLT) == VC_BlankFlt_16Clk) || \ + ((BLANK_FLT) == VC_BlankFlt_32Clk) || \ + ((BLANK_FLT) == VC_BlankFlt_64Clk) || \ + ((BLANK_FLT) == VC_BlankFlt_128Clk) || \ + ((BLANK_FLT) == VC_BlankFlt_256Clk) || \ + ((BLANK_FLT) == VC_BlankFlt_512Clk)) + +/** @defgroup VC_BlankCh3B + * @{ + */ +#define VC_BlankCh3B_Disable ((uint32_t)0x00000000) +#define VC_BlankCh3B_Enable ((uint32_t)0x00001000) + +#define IS_VC_BLANK_CH3B(BLANK_CH3B) (((BLANK_CH3B) == VC_BlankCh3B_Disable) || \ + ((BLANK_CH3B) == VC_BlankCh3B_Enable)) + +/** @defgroup VC_BlankCh2B + * @{ + */ +#define VC_BlankCh2B_Disable ((uint32_t)0x00000000) +#define VC_BlankCh2B_Enable ((uint32_t)0x00000800) + +#define IS_VC_BLANK_CH2B(BLANK_CH2B) (((BLANK_CH2B) == VC_BlankCh2B_Disable) || \ + ((BLANK_CH2B) == VC_BlankCh2B_Enable)) + +/** @defgroup VC_BlankCh1B + * @{ + */ +#define VC_BlankCh1B_Disable ((uint32_t)0x00000000) +#define VC_BlankCh1B_Enable ((uint32_t)0x00000400) + +#define IS_VC_BLANK_CH1B(BLANK_CH1B) (((BLANK_CH1B) == VC_BlankCh1B_Disable) || \ + ((BLANK_CH1B) == VC_BlankCh1B_Enable)) + + +/** @defgroup VC_ATIMBk + * @{ + */ +#define VC_ATIMBk_Disable ((uint32_t)0x00000000) +#define VC_ATIMBk_Enable ((uint32_t)0x00000200) + +#define IS_VC_ATIMBK(ATIMBK) (((ATIMBK) == VC_ATIMBk_Disable) || \ + ((ATIMBK) == VC_ATIMBk_Enable)) + +/** @defgroup VC_ATIMClr + * @{ + */ +#define VC_ATIMClr_Disable ((uint32_t)0x00000000) +#define VC_ATIMClr_Enable ((uint32_t)0x00000100) + +#define IS_VC_ATIMCLR(ATIMCLR) (((ATIMCLR) == VC_ATIMClr_Disable) || \ + ((ATIMCLR) == VC_ATIMClr_Enable)) + + +/** + ****************************************************************************** + ** @brief VC模块配置 + *****************************************************************************/ +typedef struct +{ + uint32_t VC_DivVref; // 6-bit VDDA divider输入参考电压选择 + uint32_t VC_DivEn; // 使能6-bit VDDA divider + uint8_t VC_DivValue; // 6-bit VDDA divider设置值 +} VC_DivTypeDef; + +/** + ****************************************************************************** + ** @brief VC通道配置 + *****************************************************************************/ +typedef struct +{ + uint32_t VC_InputP; // P端输入 + uint32_t VC_InputN; // N端输入 + uint32_t VC_Hys; // VC迟滞 + uint32_t VC_Resp; // VC响应速度 + uint32_t VC_FilterEn; // VC数字滤波使能 + uint32_t VC_FilterClk; // 滤波时钟源 + uint32_t VC_FilterTime; // 输出滤波时间 + uint32_t VC_Window; // VC窗口比较功能使能 + uint32_t VC_Polarity; // VC输出信号极性设置 +} VC_InitTypeDef; + +/** + ****************************************************************************** + ** @brief VC模拟Blank窗口配置 + *****************************************************************************/ +typedef struct +{ + uint32_t VC_BlankFlt; /*Blank窗口持续时间*/ + + uint32_t VC_BlankCh3B; /*ATIM的CH3触发VCx启动Blank窗口*/ + + uint32_t VC_BlankCh2B; /*ATIM的CH2触发VCx启动Blank窗口*/ + + uint32_t VC_BlankCh1B; /*ATIM的CH1触发VCx启动Blank窗口*/ +} VC_BlankTypeDef; + +/** + ****************************************************************************** + ** @brief VC输出连接到ATIM的BK/CLR信号配置 + *****************************************************************************/ +typedef struct +{ + uint32_t VC_ATIMBk; /*VCx输出连接到ATIM的BK信号*/ + + uint32_t VC_OutAtimClr; /*VCx输出连接到ATIM的CLR信号*/ +} VC_OutTypeDef; + +/****************************************************************************** + * Global definitions + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions ('extern') + ******************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + ******************************************************************************/ +//VC1/VC2模块VCx负端输入信号初始化 +void VC1VC2_INNInit(VC_InitTypeDef *VC_InitStruct); + +//VC通道1初始化 +void VC1_ChannelInit(VC_InitTypeDef *VC_InitStruct); +//VC通道2初始化 +void VC2_ChannelInit(VC_InitTypeDef *VC_InitStruct); +//VC通道1去初始化 +void VC1_ChannelDeInit(void); +//VC通道2去初始化 +void VC2_ChannelDeInit(void); +//VC模块去初始化 +void VC_DeInit(void); + +//VC1/VC2模块DIV参考电压初始化 +void VC1VC2_DIVInit(VC_DivTypeDef *VC_DivStruct); +//VC1/VC2模块DIV参考电压去初始化 +void VC1VC2_DIVDeInit(void); + +//VC1通道使能 +void VC1_EnableChannel(void); +//VC2通道使能 +void VC2_EnableChannel(void); +//VC1通道禁用 +void VC1_DisableChannel(void); +//VC2通道禁用 +void VC2_DisableChannel(void); + +//VC1输出滤波使能 +void VC1_EnableFilter(void); +//VC2输出滤波使能 +void VC2_EnableFilter(void); +//VC1输出滤波禁用 +void VC1_DisableFilter(void); +//VC2输出滤波禁用 +void VC2_DisableFilter(void); + +//VC通道1/2 输出连接默认值初始化 +void VC1VC2_OutInit(VC_OutTypeDef *VC_OutStruct); +//VC通道1输出连接配置 +void VC1_OutputCfg(VC_OutTypeDef *VC_OutStruct); +//VC通道2输出连接配置 +void VC2_OutputCfg(VC_OutTypeDef *VC_OutStruct); + +//VC通道1/2 BlanK窗口默认值初始化 +void VC1VC2_BlankInit(VC_BlankTypeDef *VC_BlankStruct); +//VC通道1 BlanK窗口配置 +void VC1_BlankCfg(VC_BlankTypeDef *VC_BlankStruct); +//VC通道2 BlanK窗口配置 +void VC2_BlankCfg(VC_BlankTypeDef *VC_BlankStruct); + +//VC通道1窗口比较功能配置 +void VC1_WindowEnable(boolean_t bWindow); +//VC通道2窗口比较功能配置 +void VC2_WindowEnable(boolean_t bWindow); + +//VC通道1输出信号极性设置 +void VC1_PolarityCfg(boolean_t bPolarity); +//VC通道2输出信号极性设置 +void VC2_PolarityCfg(boolean_t bPolarity); + +//使能NVIC中VCx中断 +void VC_EnableNvic(IRQn_Type enIrqn, uint8_t intPriority); +//禁止NVIC中VC中断 +void VC_DisableNvic(IRQn_Type enIrqn); +//VC通道1中断禁用 +void VC1_DisableIrq(void); +//VC通道2中断禁用 +void VC2_DisableIrq(void); +//VC通道1中断使能 +void VC1_EnableIrq(uint8_t intPriority); +//VC通道2中断使能 +void VC2_EnableIrq(uint8_t intPriority); +//配置VC1中断触发方式 +void VC1_ITConfig(uint16_t VC_IT, FunctionalState NewState); +//配置VC2中断触发方式 +void VC2_ITConfig(uint16_t VC_IT, FunctionalState NewState); + +//清除VC1中断标志 +void VC1_ClearIrq(void); +//清除VC2中断标志 +void VC2_ClearIrq(void); + +//获取VC1状态 +FlagStatus VC1_GetFlagStatus(uint16_t VC_FLAG); +//获取VC2状态 +FlagStatus VC2_GetFlagStatus(uint16_t VC_FLAG); + +//获取VC1的使能控制状态 +FlagStatus VC1_GetEnableStatus(void); +//获取VC2的使能控制状态 +FlagStatus VC2_GetEnableStatus(void); +//@} // VcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __CW32F030_VC_H */ +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_wwdt.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_wwdt.h new file mode 100644 index 0000000..9500b03 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/cw32f030_wwdt.h @@ -0,0 +1,100 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_WWDT_H +#define __CW32F030_WWDT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" + +/****************************************************************************** + * type definitions ('typedef') + ******************************************************************************/ +typedef struct +{ + uint32_t WWDT_Prescaler; /* 预分配系数，取值范围2的n次幂，n=12,13..19 */ + + uint32_t WWDT_WindowValue; /* 看门狗窗口值，取值范围小于0x80*/ + + uint8_t WWDT_CounterValue; /* 看门狗计数器初值，取值范围0x40 到 0x7F. */ + + FunctionalState WWDT_ITState; /* 看门狗中断状态，取值范围ENABLE或DISABLE */ +} WWDT_InitTypeDef; +/****************************************************************************** + * pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define WWDT_Prescaler_DIV4096 ((uint32_t)0x00000000) +#define WWDT_Prescaler_DIV8192 ((uint32_t)0x00000080) +#define WWDT_Prescaler_DIV16384 ((uint32_t)0x00000100) +#define WWDT_Prescaler_DIV32768 ((uint32_t)0x00000180) +#define WWDT_Prescaler_DIV65536 ((uint32_t)0x00000200) +#define WWDT_Prescaler_DIV131072 ((uint32_t)0x00000280) +#define WWDT_Prescaler_DIV262144 ((uint32_t)0x00000300) +#define WWDT_Prescaler_DIV524288 ((uint32_t)0x00000380) +#define IS_WWDT_PRESCALER(PRESCALER) (((PRESCALER) == WWDT_Prescaler_DIV4096) || \ + ((PRESCALER) == WWDT_Prescaler_DIV8192) || \ + ((PRESCALER) == WWDT_Prescaler_DIV16384) || \ + ((PRESCALER) == WWDT_Prescaler_DIV32768) || \ + ((PRESCALER) == WWDT_Prescaler_DIV65536) || \ + ((PRESCALER) == WWDT_Prescaler_DIV131072) || \ + ((PRESCALER) == WWDT_Prescaler_DIV262144) || \ + ((PRESCALER) == WWDT_Prescaler_DIV524288)) +#define IS_WWDT_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDT_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + + +#define WWDT_GET_POV_STATUS(VALUE) {(VALUE) = (FlagStatus)(CW_WWDT->SR);} +#define WWDT_CLR_POV_STATUS() {REGBITS_CLR(CW_WWDT->SR, WWDT_SR_POV_Msk);} +#define WWDT_ENABLE_IT() {REGBITS_SET(CW_WWDT->CR1,WWDT_CR1_IE_Msk);} +#define WWDT_FEED(VALUE) {REGBITS_MODIFY(CW_WWDT->CR0, WWDT_CR0_WCNT_Msk,(VALUE));} + +/****************************************************************************** +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ + + +/****************************************************************************** +* Global function prototypes +******************************************************************************/ +void WWDT_DeInit(void); +void WWDT_Init(WWDT_InitTypeDef *WWDT_InitStruct); +void WWDT_Refresh(uint8_t Counter); + + +void WWDT_Cmd(void); +void WWDT_SetPrescaler(uint32_t WWDT_Prescaler); +void WWDT_SetWindowValue(uint8_t WindowValue); +void WWDT_SetCountValue(uint8_t CountValue); +uint8_t WWDT_GetCounterValue(void); +uint8_t WWDT_GetWindowValue(void); +void WWDT_EnableIT(void); +FlagStatus WWDT_GetFlagStatus(void); +void WWDT_ClearFlag(void); + + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32F030_WWDT_H */ +/** + * @} + */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/system_cw32f030.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/system_cw32f030.h new file mode 100644 index 0000000..eb407a2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/inc/system_cw32f030.h @@ -0,0 +1,71 @@ + + +#ifndef __SYSTEM_CW32F030_H +#define __SYSTEM_CW32F030_H + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "base_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/******************************************************************************/ +#define HWWD_DISABLE (1) + +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u + + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern void SystemInit(void); // Initialize the system +//extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable + +/** + ******************************************************************************* + ** This hook is part of wait loops. + ******************************************************************************/ +extern void delay1ms(uint32_t u32Cnt); +extern void delay100us(uint32_t u32Cnt); +extern void delay10us(uint32_t u32Cnt); +extern void FirmwareDelay(uint32_t DlyCnt); + +extern void memclr(void *pu8Address, uint32_t u32Count); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_PS030 _H__ */ + + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_adc.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_adc.c new file mode 100644 index 0000000..aaa3d32 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_adc.c @@ -0,0 +1,1023 @@ +/** + * @file cw32f030_adc.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-08-09 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* + * + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + * + *******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "cw32f030.h" +#include "cw32f030_adc.h" +#include "cw32f030_gpio.h" + +/** + ****************************************************************************** + ** \addtogroup AdcGroup + ******************************************************************************/ +//@{ +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** + * @brief + * 获取ADC所有中断状态 + * + * @param pFlagAdcIrq + */ +void ADC_GetITStatusAll(volatile uint8_t *pFlagAdcIrq) +{ + *pFlagAdcIrq = (uint8_t)(CW_ADC->ISR); +} + +/** + * @brief + * 获取ADC指定的中断状态 + * + * @param ADC_IT: + * @arg ADC_IT_READY + * @arg ADC_IT_OVW + * @arg ADC_IT_WDTR + * @arg ADC_IT_WDTH + * @arg ADC_IT_WDTL + * @arg ADC_IT_EOA + * @arg ADC_IT_EOS + * @arg ADC_IT_EOC + * + * @return ITStatus: SET or RESET + */ +ITStatus ADC_GetITStatus(uint16_t ADC_IT) +{ + assert_param(IS_ADC_GET_IT(ADC_IT)); + return (REGBITS_GET(CW_ADC->ISR, ADC_IT) ? SET : RESET); +} + +/** + * @brief + * 清除ADC所有中断状态 + */ +void ADC_ClearITPendingAll(void) +{ + REGBITS_CLR(CW_ADC->ICR, + (ADC_ISR_OVW_Msk | ADC_ISR_WDTR_Msk | \ + ADC_ISR_WDTH_Msk | ADC_ISR_WDTL_Msk | ADC_ISR_EOA_Msk | \ + ADC_ISR_EOS_Msk | ADC_ISR_EOC_Msk)); +} + +/** + * @brief + * 清除ADC指定的中断状态 + * + * @param ADC_IT + * @arg ADC_IT_OVW + * @arg ADC_IT_WDTR + * @arg ADC_IT_WDTH + * @arg ADC_IT_WDTL + * @arg ADC_IT_EOA + * @arg ADC_IT_EOS + * @arg ADC_IT_EOC + */ +void ADC_ClearITPendingBit(uint16_t ADC_IT) +{ + assert_param(IS_ADC_GET_IT(ADC_IT)); + REGBITS_CLR(CW_ADC->ICR, ADC_IT); +} + +/** + * @brief + * ADC中断使能 + * + * @param intPriority + */ +void ADC_EnableIrq(uint8_t intPriority) +{ + ADC_EnableNvic(intPriority); +} + +/** + * @brief + * ADC中断禁止 + */ +void ADC_DisableIrq(void) +{ + REGBITS_CLR(CW_ADC->IER, + ADC_IER_OVW_Msk | ADC_IER_WDTR_Msk | ADC_IER_WDTH_Msk | \ + ADC_IER_WDTL_Msk | ADC_IER_EOA_Msk | ADC_IER_EOS_Msk | \ + ADC_IER_EOC_Msk); + ADC_DisableNvic(); +} + +/** + * @brief + * ADC模拟看门狗配置 + * + * @param ADC_WdtStruct + */ +void ADC_WdtConfig(ADC_WdtTypeDef *ADC_WdtStruct) +{ + ASSERT(NULL != ADC_WdtStruct); + assert_param(IS_ADC_WDT_CH(ADC_WdtStruct->ADC_WdtCh)); + assert_param(IS_ADC_WDT_EN(ADC_WdtStruct->ADC_WdtAll)); + assert_param(IS_ADC_WDTR_EN(ADC_WdtStruct->ADC_WdtrIrq)); + assert_param(IS_ADC_WDTH_EN(ADC_WdtStruct->ADC_WdthIrq)); + assert_param(IS_ADC_WDTL_EN(ADC_WdtStruct->ADC_WdtlIrq)); + //所有通道模拟看门狗使能控制 + //阈值比较通道选择 + REGBITS_MODIFY(CW_ADC->CR1, ADC_CR1_WDTALL_Msk | ADC_CR1_WDTCH_Msk, + ADC_WdtStruct->ADC_WdtAll | \ + ADC_WdtStruct->ADC_WdtCh); + REGBITS_MODIFY(CW_ADC->IER, + ADC_IER_WDTR_Msk | ADC_IER_WDTH_Msk | ADC_IER_WDTL_Msk, + ADC_WdtStruct->ADC_WdtrIrq | \ + ADC_WdtStruct->ADC_WdthIrq | \ + ADC_WdtStruct->ADC_WdtlIrq); + CW_ADC->VTH = ADC_WdtStruct->ADC_Vth; //模拟看门狗检测高阈值 + CW_ADC->VTL = ADC_WdtStruct->ADC_Vtl; //模拟看门狗检测低阈值 + if (ADC_WdtStruct->ADC_WdtCh == ADC_WdtVref1P2) + { + REGBITS_SET(CW_ADC->CR0, ADC_CR0_BGREN_Msk); + } +} + +/** + * @brief + * ADC初始化 + * + * @param ADC_InitStruct + */ +void ADC_Init(ADC_InitTypeDef *ADC_InitStruct) +{ + ASSERT(NULL != ADC_InitStruct); + assert_param(IS_ADC_OP_MODE(ADC_InitStruct->ADC_OpMode)); + assert_param(IS_ADC_CLK_DIV(ADC_InitStruct->ADC_ClkDiv)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_InitStruct->ADC_SampleTime)); + assert_param(IS_ADC_VREF_SEL(ADC_InitStruct->ADC_VrefSel)); + assert_param(IS_ADC_BUF_ENABLE(ADC_InitStruct->ADC_InBufEn)); + assert_param(IS_ADC_TS_ENABLE(ADC_InitStruct->ADC_TsEn)); + assert_param(IS_ADC_DMA_ENABLE(ADC_InitStruct->ADC_DMAEn)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_Align)); + assert_param(IS_ADC_ACC_ENABLE(ADC_InitStruct->ADC_AccEn)); + REGBITS_MODIFY(CW_ADC->CR0, + ADC_CR0_BUF_Msk | ADC_CR0_SAM_Msk | ADC_CR0_CLK_Msk | \ + ADC_CR0_REF_Msk | ADC_CR0_TSEN_Msk | ADC_CR0_MODE_Msk, + ADC_InitStruct->ADC_InBufEn | \ + ADC_InitStruct->ADC_SampleTime | \ + ADC_InitStruct->ADC_ClkDiv | \ + ADC_InitStruct->ADC_VrefSel | \ + ADC_InitStruct->ADC_TsEn | \ + ADC_InitStruct->ADC_OpMode); + REGBITS_MODIFY(CW_ADC->CR1, ADC_CR1_DMAEN_Msk | ADC_CR1_ALIGN_Msk, + ADC_InitStruct->ADC_DMAEn | \ + ADC_InitStruct->ADC_Align); + if (ADC_InitStruct->ADC_AccEn) + { + REGBITS_MODIFY(CW_ADC->CR2, ADC_CR2_ACCEN_Msk | ADC_CR2_ACCRST_Msk, + ADC_InitStruct->ADC_AccEn | \ + 1u << ADC_CR2_ACCRST_Pos); + } + if (ADC_InitStruct->ADC_VrefSel == ADC_Vref_Extern1) + { + //初始化ExRef：PB00 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOB_Msk); //打开GPIO时钟 + PB00_ANALOG_ENABLE(); + } +} + +/** + * @brief + * ADC默认值初始化 + * + * @param ADC_InitStruct + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + ADC_InitStruct->ADC_OpMode = ADC_SingleChOneMode; //单通道单次转换模式 + ADC_InitStruct->ADC_ClkDiv = ADC_Clk_Div1; //PCLK + ADC_InitStruct->ADC_SampleTime = ADC_SampTime5Clk; //5个ADC时钟周期 + ADC_InitStruct->ADC_VrefSel = ADC_Vref_BGR2p5; //VDDA参考电压 + ADC_InitStruct->ADC_InBufEn = ADC_BufDisable; //关闭跟随器 + ADC_InitStruct->ADC_TsEn = ADC_TsDisable; //关闭内置温度传感器 + ADC_InitStruct->ADC_DMAEn = ADC_DmaDisable; //不触发DMA + ADC_InitStruct->ADC_Align = ADC_AlignRight; //ADC转换结果右对齐 + ADC_InitStruct->ADC_AccEn = ADC_AccDisable; //转换结果累加不使能 +} + +/** + * @brief + * ADC模拟看门狗默认值初始化 + * + * @param ADC_WdtStruct + */ +void ADC_WdtInit(ADC_WdtTypeDef *ADC_WdtStruct) +{ + ADC_WdtStruct->ADC_WdtCh = ADC_WdtCh0; + ADC_WdtStruct->ADC_WdtAll = ADC_WdtDisable; + ADC_WdtStruct->ADC_WdtrIrq = ADC_WdtrDisable; + ADC_WdtStruct->ADC_WdthIrq = ADC_WdthDisable; + ADC_WdtStruct->ADC_WdtlIrq = ADC_WdtlDisable; + ADC_WdtStruct->ADC_Vth = 0x0FFF; + ADC_WdtStruct->ADC_Vtl = 0x00; +} + +/** + * @brief + * ADC外部中断触发源配置 + * + * @param ADC_TRIG: + * @arg ADC_TRIG_DMA + * @arg ADC_TRIG_I2C2 + * @arg ADC_TRIG_I2C1 + * @arg ADC_TRIG_SPI2 + * @arg ADC_TRIG_SPI1 + * @arg ADC_TRIG_UART3 + * @arg ADC_TRIG_UART2 + * @arg ADC_TRIG_UART1 + * @arg ADC_TRIG_BTIM3 + * @arg ADC_TRIG_BTIM2 + * @arg ADC_TRIG_BTIM1 + * @arg ADC_TRIG_GTIM4 + * @arg ADC_TRIG_GTIM3 + * @arg ADC_TRIG_GTIM2 + * @arg ADC_TRIG_GTIM1 + * @arg ADC_TRIG_ATIM + * @param NewState: + * @arg DISABLE + * @arg ENABLE + */ +void ADC_ExtTrigCfg(uint16_t ADC_TRIG, FunctionalState NewState) +{ + uint16_t trigMask = 0; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_TRIG(ADC_TRIG)); + /* Get the ADC TRIG index */ + trigMask = ADC_TRIG; + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + CW_ADC->TRIGGER |= trigMask; + } + else + { + /* Disable the selected ADC interrupts */ + CW_ADC->TRIGGER &= (~(uint32_t) trigMask); + } +} + +/** + * @brief + * ADC去初始化 + */ +void ADC_DeInit(void) +{ + // Enable ADC reset state + REGBITS_CLR(CW_SYSCTRL->APBRST2, SYSCTRL_APBRST2_ADC_Msk); + // Release ADC from reset state + REGBITS_SET(CW_SYSCTRL->APBRST2, SYSCTRL_APBRST2_ADC_Msk); +} + +/** + * @brief + * ADC转换软件启动命令 + * + * @param NewState + * @arg DISABLE + * @arg ENABLE + */ +void ADC_SoftwareStartConvCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + REGBITS_SET(CW_ADC->START, ADC_START_START_Msk); + } + else + { + REGBITS_CLR(CW_ADC->START, ADC_START_START_Msk); + } +} + +/** + * @brief + * ADC使能 + */ +void ADC_Enable(void) +{ + REGBITS_SET(CW_ADC->CR0, ADC_CR0_EN_Msk); + //等待 ADC 模块启动完成 + while (!ADC_GetITStatus(ADC_IT_READY)); +} + +/** + * @brief + * ADC禁用 + */ +void ADC_Disable(void) +{ + REGBITS_CLR(CW_ADC->CR0, ADC_CR0_EN_Msk); +} + +/** + * @brief + * 单通道转换模式公共配置 + * + * @param ADC_SingleChStruct + */ +void ADC_SingleChCommon(ADC_SingleChTypeDef *ADC_SingleChStruct) +{ + ASSERT(NULL != ADC_SingleChStruct); + assert_param(IS_ADC_CH_SEL(ADC_SingleChStruct->ADC_Chmux)); + assert_param(IS_ADC_DATA_DISCARD(ADC_SingleChStruct->ADC_DiscardEn)); + ADC_Init(&ADC_SingleChStruct->ADC_InitStruct); + ADC_BufEnSingleCh(ADC_SingleChStruct->ADC_Chmux); + if (ADC_SingleChStruct->ADC_WdtStruct.ADC_WdtAll == ADC_WdtEnable) + { + ADC_WdtConfig(&ADC_SingleChStruct->ADC_WdtStruct); + } + REGBITS_MODIFY(CW_ADC->CR1, ADC_CR1_DISCARD_Msk | ADC_CR1_CHMUX_Msk, + ADC_SingleChStruct->ADC_DiscardEn | \ + ADC_SingleChStruct->ADC_Chmux); +} + +/** + * @brief + * ADC单通道单次转换模式配置 + * + * @param ADC_SingleChStruct + */ +void ADC_SingleChOneModeCfg(ADC_SingleChTypeDef *ADC_SingleChStruct) +{ + ADC_SingleChCommon(ADC_SingleChStruct); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_MODE_Msk, ADC_SingleChOneMode); +} + +/** + * @brief + * ADC单通道多次转换模式配置 + * + * @param ADC_SingleChStruct + * @param cntAdcSample: 0 ~ 255 + */ +void ADC_SingleChMoreModeCfg(ADC_SingleChTypeDef *ADC_SingleChStruct, + uint8_t cntAdcSample) +{ + ADC_SingleChStruct->ADC_InitStruct.ADC_AccEn = ADC_AccEnable; //Must be added + ADC_SingleChCommon(ADC_SingleChStruct); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_MODE_Msk, ADC_SingleChMoreMode); + CW_ADC->CR2_f.CNT = cntAdcSample; +} + +/** + * @brief + * ADC单通道连续转换模式配置 + * + * @param ADC_SingleChStruct + */ +void ADC_SingleChContinuousModeCfg(ADC_SingleChTypeDef *ADC_SingleChStruct) +{ + ADC_SingleChCommon(ADC_SingleChStruct); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_MODE_Msk, ADC_SingleChContinuousMode); +} + +/** + * @brief + * ADC序列转换模式公共配置 + * + * @param ADC_SerialChStruct + */ +void ADC_SerialChCommon(ADC_SerialChTypeDef *ADC_SerialChStruct) +{ + if (NULL == ADC_SerialChStruct) + { + return; + } + ADC_Init(&ADC_SerialChStruct->ADC_InitStruct); + switch (ADC_SerialChStruct->ADC_SqrEns) + { + case ADC_SqrEns0: + ADC_Sqr0ChannelCfg(ADC_SerialChStruct); + break; + case ADC_SqrEns01: + ADC_Sqr01ChannelCfg(ADC_SerialChStruct); + break; + case ADC_SqrEns02: + ADC_Sqr02ChannelCfg(ADC_SerialChStruct); + break; + case ADC_SqrEns03: + ADC_Sqr03ChannelCfg(ADC_SerialChStruct); + break; + default: + break; + } +} + +/** + * @brief + * ADC序列连续转换模式配置 + * + * @param ADC_SerialChStruct + */ +void ADC_SerialChContinuousModeCfg(ADC_SerialChTypeDef *ADC_SerialChStruct) +{ + ADC_SerialChCommon(ADC_SerialChStruct); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_MODE_Msk, ADC_SerialChContinuousMode); +} + +/** + * @brief + * ADC序列扫描转换模式配置 + * + * @param ADC_SerialChStruct + */ +void ADC_SerialChScanModeCfg(ADC_SerialChTypeDef *ADC_SerialChStruct) +{ + ADC_SerialChCommon(ADC_SerialChStruct); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_MODE_Msk, ADC_SerialChScanMode); +} + +/** + * @brief + * ADC序列多次转换模式配置 + * + * @param ADC_SerialChStruct + * @param cntAdcSample: 0 ~ 255 + */ +void ADC_SerialChMoreModeCfg(ADC_SerialChTypeDef *ADC_SerialChStruct, + uint8_t cntAdcSample) +{ + ADC_SerialChStruct->ADC_InitStruct.ADC_AccEn = ADC_AccEnable; //Must be added + ADC_SerialChCommon(ADC_SerialChStruct); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_MODE_Msk, ADC_SerialChMoreMode); + CW_ADC->CR2_f.CNT = cntAdcSample; +} + +/** + * @brief + * ADC序列断续转换模式配置 + * + * @param ADC_SerialChStruct + */ +void ADC_SerialChBreakModeCfg(ADC_SerialChTypeDef *ADC_SerialChStruct) +{ + ADC_SerialChCommon(ADC_SerialChStruct); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_MODE_Msk, ADC_SerialChBreakMode); +} + +/** + * @brief + * 单通道模式的内置跟随器使能 + * + * @param enAdcSampCh: + * @arg ADC_ExInputCH0 + * @arg ADC_ExInputCH1 + * @arg ADC_ExInputCH2 + * @arg ADC_ExInputCH3 + * @arg ADC_ExInputCH4 + * @arg ADC_ExInputCH5 + * @arg ADC_ExInputCH6 + * @arg ADC_ExInputCH7 + * @arg ADC_ExInputCH8 + * @arg ADC_ExInputCH9 + * @arg ADC_ExInputCH10 + * @arg ADC_ExInputCH11 + * @arg ADC_ExInputCH12 + * @arg ADC_VddaDiV3Input + * @arg ADC_TsInput + * @arg ADC_Vref1P2Input + */ +void ADC_BufEnSingleCh(uint32_t enAdcSampCh) +{ + if ((enAdcSampCh == ADC_VddaDiV3Input) || (enAdcSampCh == ADC_TsInput) + || (enAdcSampCh == ADC_Vref1P2Input)) + { + REGBITS_SET(CW_ADC->CR0, ADC_CR0_BUF_Msk); + } + if (enAdcSampCh == ADC_Vref1P2Input) + { + REGBITS_SET(CW_ADC->CR0, ADC_CR0_BGREN_Msk); + } + //如果ADC通道选择了内置温度传感器输出电压，则需要使能内置温度传感器 + else if (enAdcSampCh == ADC_TsInput) + { + //使能内置温度传感器 + REGBITS_SET(CW_ADC->CR0, ADC_CR0_TSEN_Msk); + } + else {} +} + +/** + * @brief + * 序列模式的内置跟随器使能 + * + * @param enAdcSampCh: + * @arg ADC_SqrCh0 + * @arg ADC_SqrCh1 + * @arg ADC_SqrCh2 + * @arg ADC_SqrCh3 + * @arg ADC_SqrCh4 + * @arg ADC_SqrCh5 + * @arg ADC_SqrCh6 + * @arg ADC_SqrCh7 + * @arg ADC_SqrCh8 + * @arg ADC_SqrCh9 + * @arg ADC_SqrCh10 + * @arg ADC_SqrCh11 + * @arg ADC_SqrCh12 + * @arg ADC_SqrVddaDiV3 + * @arg ADC_SqrTs + * @arg ADC_SqrVref1P2 + */ +void ADC_BufEnSerialCh(uint32_t enAdcSampCh) +{ + if ((enAdcSampCh == ADC_SqrVddaDiV3) || (enAdcSampCh == ADC_SqrTs) + || (enAdcSampCh == ADC_SqrVref1P2)) + { + REGBITS_SET(CW_ADC->CR0, ADC_CR0_BUF_Msk); + } + if (enAdcSampCh == ADC_SqrVref1P2) + { + REGBITS_SET(CW_ADC->CR0, ADC_CR0_BGREN_Msk); + } + //如果ADC通道选择了内置温度传感器输出电压，则需要使能内置温度传感器 + else if (enAdcSampCh == ADC_SqrTs) + { + //使能内置温度传感器 + REGBITS_SET(CW_ADC->CR0, ADC_CR0_TSEN_Msk); + } + else {} +} + +/** + * @brief + * 序列SQR0转换通道配置 + * + * @param ADC_SerialChStruct + */ +void ADC_Sqr0ChannelCfg(ADC_SerialChTypeDef *ADC_SerialChStruct) +{ + ASSERT(NULL != ADC_SerialChStruct); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr0Chmux)); + assert_param(IS_ADC_SQR_ENS(ADC_SerialChStruct->ADC_SqrEns)); + //ADC_SerialChStruct->ADC_SqrEns = ADC_SqrEns0; + REGBITS_MODIFY(CW_ADC->SQR, ADC_SQR_ENS_Msk | ADC_SQR_SQR0_Msk, + ADC_SerialChStruct->ADC_SqrEns | \ + ADC_SerialChStruct->ADC_Sqr0Chmux); + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr0Chmux); +} + +/** + * @brief + * 序列SQR0/SQR1转换通道配置 + * + * @param ADC_SerialChStruct + */ +void ADC_Sqr01ChannelCfg(ADC_SerialChTypeDef *ADC_SerialChStruct) +{ + ASSERT(NULL != ADC_SerialChStruct); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr0Chmux)); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr1Chmux)); + assert_param(IS_ADC_SQR_ENS(ADC_SerialChStruct->ADC_SqrEns)); + //ADC_SerialChStruct->ADC_SqrEns = ADC_SqrEns01; + REGBITS_MODIFY(CW_ADC->SQR, + ADC_SQR_ENS_Msk | ADC_SQR_SQR0_Msk | ADC_SQR_SQR1_Msk, + ADC_SerialChStruct->ADC_SqrEns | \ + (ADC_SerialChStruct->ADC_Sqr1Chmux << ADC_SQR_SQR1_Pos) | \ + ADC_SerialChStruct->ADC_Sqr0Chmux); + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr0Chmux); + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr1Chmux); +} + +/** + * @brief + * 序列SQR0~SQR2转换通道配置 + * + * @param ADC_SerialChStruct + */ +void ADC_Sqr02ChannelCfg(ADC_SerialChTypeDef *ADC_SerialChStruct) +{ + ASSERT(NULL != ADC_SerialChStruct); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr0Chmux)); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr1Chmux)); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr2Chmux)); + assert_param(IS_ADC_SQR_ENS(ADC_SerialChStruct->ADC_SqrEns)); + //ADC_SerialChStruct->ADC_SqrEns = ADC_SqrEns02; + REGBITS_MODIFY(CW_ADC->SQR, + ADC_SQR_ENS_Msk | ADC_SQR_SQR0_Msk | \ + ADC_SQR_SQR1_Msk | ADC_SQR_SQR2_Msk, + ADC_SerialChStruct->ADC_SqrEns | \ + (ADC_SerialChStruct->ADC_Sqr2Chmux << ADC_SQR_SQR2_Pos) | \ + (ADC_SerialChStruct->ADC_Sqr1Chmux << ADC_SQR_SQR1_Pos) | \ + ADC_SerialChStruct->ADC_Sqr0Chmux); + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr0Chmux); + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr1Chmux); + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr2Chmux); +} + +/** + * @brief + * 序列SQR0~SQR3转换通道配置 + * + * @param ADC_SerialChStruct + */ +void ADC_Sqr03ChannelCfg(ADC_SerialChTypeDef *ADC_SerialChStruct) +{ + ASSERT(NULL != ADC_SerialChStruct); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr0Chmux)); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr1Chmux)); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr2Chmux)); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr3Chmux)); + assert_param(IS_ADC_SQR_ENS(ADC_SerialChStruct->ADC_SqrEns)); + //ADC_SerialChStruct->ADC_SqrEns = ADC_SqrEns03; + REGBITS_MODIFY(CW_ADC->SQR, + ADC_SQR_ENS_Msk | ADC_SQR_SQR0_Msk | \ + ADC_SQR_SQR1_Msk | ADC_SQR_SQR2_Msk | ADC_SQR_SQR3_Msk, + ADC_SerialChStruct->ADC_SqrEns | \ + (ADC_SerialChStruct->ADC_Sqr3Chmux << ADC_SQR_SQR3_Pos) | \ + (ADC_SerialChStruct->ADC_Sqr2Chmux << ADC_SQR_SQR2_Pos) | \ + (ADC_SerialChStruct->ADC_Sqr1Chmux << ADC_SQR_SQR1_Pos) | \ + ADC_SerialChStruct->ADC_Sqr0Chmux); + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr0Chmux); + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr1Chmux); + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr2Chmux); + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr3Chmux); +} + +/** + * @brief + * 触发DMA读取命令 + * + * @param NewState: + * @arg DISABLE + * @arg ENABLE + */ +void ADC_DMACmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + REGBITS_SET(CW_ADC->CR1, ADC_CR1_DMAEN_Msk); + } + else + { + REGBITS_CLR(CW_ADC->CR1, ADC_CR1_DMAEN_Msk); + } +} + +/** + * @brief + * 触发DMA读取使能 + * + */ +void ADC_DMAEnable(void) +{ + REGBITS_SET(CW_ADC->CR1, ADC_CR1_DMAEN_Msk); +} + +/** + * @brief + * 触发DMA读取禁止 + * + */ +void ADC_DMADisable(void) +{ + REGBITS_CLR(CW_ADC->CR1, ADC_CR1_DMAEN_Msk); +} + +/** + * @brief + * 获取单次转换采样值 + * + * @param + * + * @return uint16_t + */ +uint16_t ADC_GetConversionValue(void) +{ + return (uint16_t)(CW_ADC->RESULT0); +} + +/** + * @brief + * 获取SQR0通道采样值 + * + * @param pAdcResult + */ +void ADC_GetSqr0Result(uint16_t *pAdcResult) +{ + if (NULL == pAdcResult) + { + return; + } + *pAdcResult = (uint16_t)(CW_ADC->RESULT0); +} + +/** + * @brief + * 获取SQR1通道采样值 + * + * @param pAdcResult + */ +void ADC_GetSqr1Result(uint16_t *pAdcResult) +{ + if (NULL == pAdcResult) + { + return; + } + *pAdcResult = (uint16_t)(CW_ADC->RESULT1); +} + +/** + * @brief + * 获取SQR2通道采样值 + * + * @param pAdcResult + */ +void ADC_GetSqr2Result(uint16_t *pAdcResult) +{ + if (NULL == pAdcResult) + { + return; + } + *pAdcResult = (uint16_t)(CW_ADC->RESULT2); +} + +/** + * @brief + * 获取SQR3通道采样值 + * + * @param pAdcResult + */ +void ADC_GetSqr3Result(uint16_t *pAdcResult) +{ + if (NULL == pAdcResult) + { + return; + } + *pAdcResult = (uint16_t)(CW_ADC->RESULT3); +} + +/** + * @brief + * 获取累加采样值 + * + * @param pAdcAccResult + */ +void ADC_GetAccResult(uint32_t *pAdcAccResult) +{ + if (NULL == pAdcAccResult) + { + return; + } + *pAdcAccResult = (uint32_t)(CW_ADC->RESULTACC); +} + +/** + * @brief + * 清零累加采样值 + */ +void ADC_ClrAccResult(void) +{ + REGBITS_SET(CW_ADC->CR2, ADC_CR2_ACCRST_Msk); +} + +/** + * @brief + * 设置ADC参考电压 + * + * @param ADC_VrefSel: + * @arg ADC_Vref_BGR1p5 + * @arg ADC_Vref_BGR2p5 + * @arg ADC_Vref_Extern1 + * @arg ADC_Vref_VDDA + */ +void ADC_SetVref(uint32_t ADC_VrefSel) +{ + assert_param(IS_ADC_VREF_SEL(ADC_VrefSel)); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_REF_Msk, + ADC_VrefSel); + if (ADC_VrefSel == ADC_Vref_Extern1) + { + //初始化ExRef：PB00 + REGBITS_SET(CW_SYSCTRL->AHBEN, SYSCTRL_AHBEN_GPIOB_Msk); //打开GPIO时钟 + PB00_ANALOG_ENABLE(); + } +} +/** + * @brief + * 设置ADC结果对齐方式 + * + * @param enAlign: + * @arg ADC_AlignRight + * @arg ADC_AlignLeft + */ +void ADC_SetAlign(uint32_t enAlign) +{ + REGBITS_MODIFY(CW_ADC->CR1, ADC_CR1_ALIGN_Msk, enAlign); +} + +/** + * @brief + * 设置单通道ADC转换结果溢出保存策略 + * + * @param enDiscard: + * @arg ADC_DiscardNull + * @arg ADC_DiscardEnable + */ +void ADC_SetDiscard(uint32_t enDiscard) +{ + assert_param(IS_ADC_DATA_DISCARD(enDiscard)); + REGBITS_MODIFY(CW_ADC->CR1, ADC_CR1_DISCARD_Msk, enDiscard); +} + +/** + * @brief + * 设置内置温度传感器使能控制 + * + * @param enTs: + * @arg ADC_TsDisable + * @arg ADC_TsEnable + */ +void ADC_SetTs(uint32_t enTs) +{ + assert_param(IS_ADC_TS_ENABLE(enTs)); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_TSEN_Msk, enTs); +} + +/** + * @brief + * 读取ADC参考电压1.5V时的温度传感器的测量温度 + * + * @param fAdcTsDegree + */ +void ADC_GetTsVref1V5(float *fAdcTsDegree) +{ + uint16_t u16AdcResult; + uint8_t temp1; + uint16_t temp2; + temp1 = *((uint8_t *)(ADDR_T0)); + temp2 = *((uint16_t *)(ADDR_TRIM_1P5)); + /*Caution: Must select ADC_GetSqr0Result()~ADC_GetSqr3Result() instead of ADC_GetConversionValue() if using ADC_SQR convertion. + * ADC single channel convertion is default. + */ + u16AdcResult = ADC_GetConversionValue(); + //ADC_GetSqr0Result(&u16AdcResult); //Using ADC_SQR0. + //ADC_GetSqr1Result(&u16AdcResult); //Using ADC_SQR1. + //ADC_GetSqr2Result(&u16AdcResult); //Using ADC_SQR2. + //ADC_GetSqr3Result(&u16AdcResult); //Using ADC_SQR3. + *fAdcTsDegree = temp1 * 0.5f + COEFF_TS * 1.5f * (u16AdcResult - temp2); +} + +/** + * @brief + * 读取ADC参考电压2.5V时的温度传感器的测量温度 + * + * @param fAdcTsDegree + */ +void ADC_GetTsVref2V5(float *fAdcTsDegree) +{ + uint16_t u16AdcResult; + uint8_t temp1; + uint16_t temp2; + temp1 = *((uint8_t *)(ADDR_T0)); + temp2 = *((uint16_t *)(ADDR_TRIM_2P5)); + /*Caution: Must select ADC_GetSqr0Result()~ADC_GetSqr3Result() instead of ADC_GetConversionValue() if using ADC_SQR convertion. + * ADC single channel convertion is default. + */ + u16AdcResult = ADC_GetConversionValue(); + //ADC_GetSqr0Result(&u16AdcResult); //Using ADC_SQR0. + //ADC_GetSqr1Result(&u16AdcResult); //Using ADC_SQR1. + //ADC_GetSqr2Result(&u16AdcResult); //Using ADC_SQR2. + //ADC_GetSqr3Result(&u16AdcResult); //Using ADC_SQR3. + *fAdcTsDegree = temp1 * 0.5f + COEFF_TS * 2.5f * (u16AdcResult - temp2); +} + +/** + * @brief + * ADC自动停止配置 + * + * @param enAutoStop: + * @arg ADC_AutoStopDisable + * @arg ADC_AutoStopEnable + */ +void ADC_AutoStop(uint32_t enAutoStop) +{ + REGBITS_MODIFY(CW_ADC->START, ADC_START_AUTOSTOP_Msk, enAutoStop); +} + +/** + * @brief + * ADC中断配置 + * + * @param ADC_IT: + * @arg ADC_IT_READY + * @arg ADC_IT_OVW + * @arg ADC_IT_WDTR + * @arg ADC_IT_WDTH + * @arg ADC_IT_WDTL + * @arg ADC_IT_EOA + * @arg ADC_IT_EOS + * @arg ADC_IT_EOC + * @param NewState: + * @arg DISABLE + * @arg ENABLE + */ +void ADC_ITConfig(uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itMask = 0; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itMask = (uint8_t) ADC_IT; + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + CW_ADC->IER |= itMask; + } + else + { + /* Disable the selected ADC interrupts */ + CW_ADC->IER &= (~(uint32_t) itMask); + } +} + +/** + * @brief + * 使能NVIC中ADC中断 + * + * @param intPriority: + * @arg 0 ~ 3 + */ +void ADC_EnableNvic(uint8_t intPriority) +{ + if (intPriority < (1UL << __NVIC_PRIO_BITS)) + { + NVIC_ClearPendingIRQ(ADC_IRQn); + NVIC_EnableIRQ(ADC_IRQn); + NVIC_SetPriority(ADC_IRQn, intPriority); + } +} + +/** + * @brief + * 禁用NVIC中ADC中断 + * + * @param + * + */ +void ADC_DisableNvic(void) +{ + NVIC_ClearPendingIRQ(ADC_IRQn); + NVIC_DisableIRQ(ADC_IRQn); + NVIC_SetPriority(ADC_IRQn, ADC_INT_PRIORITY); +} +//@} // AdcGroup + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_atim.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_atim.c new file mode 100644 index 0000000..14db6f1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_atim.c @@ -0,0 +1,603 @@ +/** + * @file cw32f030_atim.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-04-29 + * + * @copyright Copyright (c) 2021 + * + */ +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_atim.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ +/** + * @brief ATIM复位，寄存器恢复为默认值 + */ +void ATIM_DeInit(void) +{ + CW_SYSCTRL->APBRST2_f.ATIM = 0; + CW_SYSCTRL->APBRST2_f.ATIM = 1; +} + + +/** + * @brief ATIM 初始化 + * @param ATIM_InitStruct 详见ATIM_InitTypeDef的定义 + */ +void ATIM_Init(ATIM_InitTypeDef *ATIM_InitStruct) +{ + assert_param(IS_ATIM_COUNTING_DIRECTION(ATIM_InitStruct->CounterDirection)); + assert_param(IS_ATIM_OP_MODE(ATIM_InitStruct->CounterOPMode)); + assert_param(IS_ATIM_COUNT_MODE(ATIM_InitStruct->CounterAlignedMode)); + assert_param(IS_ATIM_PRESCALER(ATIM_InitStruct->Prescaler)); + assert_param(IS_ATIM_CLOCK(ATIM_InitStruct->ClockSelect)); + REGBITS_MODIFY(CW_ATIM->CR, ATIM_CR_DIR_Msk | ATIM_CR_ONESHOT_Msk | \ + ATIM_CR_PRS_Msk | ATIM_CR_MODE_Msk | \ + ATIM_CR_BUFPEN_Msk | ATIM_CR_CT_Msk \ + , \ + ATIM_InitStruct->CounterDirection | ATIM_InitStruct->CounterOPMode | + ATIM_InitStruct->Prescaler | ATIM_InitStruct->CounterAlignedMode | + (ATIM_InitStruct->BufferState ? ATIM_BUFFER_ENABLE : ATIM_BUFFER_DISABLE) | + ATIM_InitStruct->ClockSelect); + CW_ATIM->ARR = ATIM_InitStruct->ReloadValue; + CW_ATIM->RCR = ATIM_InitStruct->RepetitionCounter | (ATIM_InitStruct->OverFlowMask ? 1UL << 8 : 0) | \ + (ATIM_InitStruct->UnderFlowMask ? 1UL << 9 : 0); +} + + +/** + * @brief ATIM 启动 + * + * @param NewState ENABLE or DISABLE + */ +void ATIM_Cmd(FunctionalState NewState) +{ + CW_ATIM->CR_f.EN = NewState; +} + +/** + * @brief ATIM中断设置 + * @param ATIM_IT 中断源 + * @param NewState ENABLE 或 DISABLE + */ +void ATIM_ITConfig(uint32_t ATIM_IT, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CW_ATIM->CR |= ATIM_IT; + } + else + { + CW_ATIM->CR &= ~ATIM_IT; + } +} + +/** + * @brief 获取ATIM中断标志位 + * @param ATIM_IT 中断源 + * @return ITStatus + */ +ITStatus ATIM_GetITStatus(uint32_t ATIM_IT) +{ + return (CW_ATIM->ISR & ATIM_IT) ? SET : RESET; +} + +/** + * @brief 清除ATIM中断标志位 + */ +void ATIM_ClearITPendingBit(uint32_t ATIM_IT) +{ + CW_ATIM->ICR = ~ATIM_IT; +} + +/** + * @brief 设置ATIM重载值 + * @param Value + */ +void ATIM_SetReloadValue(uint32_t Value) +{ + CW_ATIM->ARR = Value; +} + +/** + * @brief 设置通道1的功能 + * + * @param Function ATIM_CHxA_BUFF ATIM_CHxA_CIE ATIM_CHxA_CDE + * ATIM_CHxB_BUFF ATIM_CHxB_CIE ATIM_CHxB_CDE + * @param NewState ENABLE 或 DISABLE + */ +void ATIM_CH1Config(uint32_t Function, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CW_ATIM->CH1CR |= Function; + } + else + { + CW_ATIM->CH1CR &= ~(Function); + } +} + +/** + * @brief 设置通道2的功能 + * + * @param Function ATIM_CHxA_BUFF ATIM_CHxA_CIE ATIM_CHxA_CDE + * ATIM_CHxB_BUFF ATIM_CHxB_CIE ATIM_CHxB_CDE + * @param NewState ENABLE 或 DISABLE + */ +void ATIM_CH2Config(uint32_t Function, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CW_ATIM->CH2CR |= Function; + } + else + { + CW_ATIM->CH2CR &= ~(Function); + } +} + +/** + * @brief 设置通道3的功能 + * + * @param Function ATIM_CHxA_BUFF ATIM_CHxA_CIE ATIM_CHxA_CDE + * ATIM_CHxB_BUFF ATIM_CHxB_CIE ATIM_CHxB_CDE + * @param NewState ENABLE 或 DISABLE + */ +void ATIM_CH3Config(uint32_t Function, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CW_ATIM->CH3CR |= Function; + } + else + { + CW_ATIM->CH3CR &= ~(Function); + } +} + +/** + * @brief 设置通道4的功能 + * + * @param Function ATIM_CH4_BUFF ATIM_CH4_CIE ATIM_CH4_CDE * + * @param NewState ENABLE 或 DISABLE + */ +void ATIM_CH4Config(uint32_t Function, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CW_ATIM->CH4CR |= Function; + } + else + { + CW_ATIM->CH4CR &= ~(Function); + } +} + +/** + * @brief 输入捕获通道1A设置 + * @param ATIM_ICInitStruct + */ +void ATIM_IC1AInit(ATIM_ICInitTypeDef *ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + REGBITS_MODIFY(CW_ATIM->CH1CR, (ATIM_CH1CR_BKSA_Msk | ATIM_CH1CR_CSA_Msk), + (ATIM_ICInitStruct->ICPolarity | ATIM_CH_A_IC)); + CW_ATIM->FLTR_f.OCM1AFLT1A = ATIM_ICInitStruct->ICFilter; +} + +/** + * @brief 输入捕获通道1B设置 + * @param ATIM_ICInitStruct + */ +void ATIM_IC1BInit(ATIM_ICInitTypeDef *ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + REGBITS_MODIFY(CW_ATIM->CH1CR, (ATIM_CH1CR_BKSB_Msk | ATIM_CH1CR_CSB_Msk), + (ATIM_ICInitStruct->ICPolarity << 2 | ATIM_CH_B_IC)); + CW_ATIM->FLTR_f.OCM1BFLT1B = ATIM_ICInitStruct->ICFilter; +} + + +/** + * @brief 输入捕获通道2A设置 + * @param ATIM_ICInitStruct + */ +void ATIM_IC2AInit(ATIM_ICInitTypeDef *ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + REGBITS_MODIFY(CW_ATIM->CH2CR, (ATIM_CH2CR_BKSA_Msk | ATIM_CH2CR_CSA_Msk), + (ATIM_ICInitStruct->ICPolarity | ATIM_CH_A_IC)); + CW_ATIM->FLTR_f.OCM2AFLT2A = ATIM_ICInitStruct->ICFilter; +} + +/** + * @brief 输入捕获通道2B设置 + * @param ATIM_ICInitStruct + */ +void ATIM_IC2BInit(ATIM_ICInitTypeDef *ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + REGBITS_MODIFY(CW_ATIM->CH2CR, (ATIM_CH2CR_BKSB_Msk | ATIM_CH2CR_CSB_Msk), + (ATIM_ICInitStruct->ICPolarity << 2 | ATIM_CH_B_IC)); + CW_ATIM->FLTR_f.OCM2BFLT2B = ATIM_ICInitStruct->ICFilter; +} + +/** + * @brief 输入捕获通道3A设置 + * @param ATIM_ICInitStruct + */ +void ATIM_IC3AInit(ATIM_ICInitTypeDef *ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + REGBITS_MODIFY(CW_ATIM->CH3CR, (ATIM_CH3CR_BKSA_Msk | ATIM_CH3CR_CSA_Msk), + (ATIM_ICInitStruct->ICPolarity | ATIM_CH_A_IC)); + CW_ATIM->FLTR_f.OCM3AFLT3A = ATIM_ICInitStruct->ICFilter; +} + +/** + * @brief 输入捕获通道3B设置 + * @param ATIM_ICInitStruct + */ +void ATIM_IC3BInit(ATIM_ICInitTypeDef *ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + REGBITS_MODIFY(CW_ATIM->CH3CR, (ATIM_CH3CR_BKSB_Msk | ATIM_CH3CR_CSB_Msk), + (ATIM_ICInitStruct->ICPolarity << 2 | ATIM_CH_B_IC)); + CW_ATIM->FLTR_f.OCM3BFLT3B = ATIM_ICInitStruct->ICFilter; +} + +/** + * @brief CH1A比较输出设置 + * @param ATIM_OCInitStruct + */ +void ATIM_OC1AInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_MODE(ATIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_POLARITY(ATIM_OCInitStruct->OCPolarity)); + assert_param(IS_ATIM_OC_IT(ATIM_OCInitStruct->OCInterruptSelect)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->BufferState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCDMAState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCInterruptState)); + REGBITS_MODIFY(CW_ATIM->FLTR, ATIM_FLTR_OCM1AFLT1A_Msk | ATIM_FLTR_CCP1A_Msk, + ATIM_OCInitStruct->OCMode | (ATIM_OCInitStruct->OCPolarity << 3)); + CW_ATIM->CR_f.CISA = ATIM_OCInitStruct->OCInterruptSelect; + REGBITS_MODIFY(CW_ATIM->CH1CR, ATIM_CH1CR_BUFEA_Msk | ATIM_CH1CR_CDEA_Msk | ATIM_CH1CR_CIEA_Msk, + (ATIM_OCInitStruct->BufferState ? ATIM_CH1CR_BUFEA_Msk : 0) | \ + (ATIM_OCInitStruct->OCDMAState ? ATIM_CH1CR_CDEA_Msk : 0) | \ + (ATIM_OCInitStruct->OCInterruptState ? ATIM_CH1CR_CIEA_Msk : 0)); +} + +/** + * @brief CH1B比较输出设置 + * @param ATIM_OCInitStruct + */ +void ATIM_OC1BInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_MODE(ATIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_POLARITY(ATIM_OCInitStruct->OCPolarity)); + assert_param(IS_ATIM_OC_IT(ATIM_OCInitStruct->OCInterruptSelect)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->BufferState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCDMAState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCInterruptState)); + REGBITS_MODIFY(CW_ATIM->FLTR, ATIM_FLTR_OCM1BFLT1B_Msk | ATIM_FLTR_CCP1B_Msk, + (ATIM_OCInitStruct->OCMode << 4) | (ATIM_OCInitStruct->OCPolarity << 7)); + REGBITS_MODIFY(CW_ATIM->CH1CR, ATIM_CH1CR_CISB_Msk | ATIM_CH1CR_BUFEB_Msk | ATIM_CH1CR_CDEB_Msk | ATIM_CH1CR_CIEB_Msk, + (ATIM_OCInitStruct->OCInterruptSelect << 12) | \ + (ATIM_OCInitStruct->BufferState ? ATIM_CH1CR_BUFEB_Msk : 0) | \ + (ATIM_OCInitStruct->OCDMAState ? ATIM_CH1CR_CDEB_Msk : 0) | \ + (ATIM_OCInitStruct->OCInterruptState ? ATIM_CH1CR_CIEB_Msk : 0)); +} + +/** + * @brief CH2A比较输出设置 + * @param ATIM_OCInitStruct + */ +void ATIM_OC2AInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_MODE(ATIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_POLARITY(ATIM_OCInitStruct->OCPolarity)); + REGBITS_MODIFY(CW_ATIM->FLTR, ATIM_FLTR_OCM2AFLT2A_Msk | ATIM_FLTR_CCP2A_Msk, + (ATIM_OCInitStruct->OCMode << 8) | (ATIM_OCInitStruct->OCPolarity << 11)); + CW_ATIM->CR_f.CISA = ATIM_OCInitStruct->OCInterruptSelect; + REGBITS_MODIFY(CW_ATIM->CH2CR, ATIM_CH2CR_BUFEA_Msk | ATIM_CH2CR_CDEA_Msk | ATIM_CH2CR_CIEA_Msk, + (ATIM_OCInitStruct->BufferState ? ATIM_CH2CR_BUFEA_Msk : 0) | \ + (ATIM_OCInitStruct->OCDMAState ? ATIM_CH2CR_CDEA_Msk : 0) | \ + (ATIM_OCInitStruct->OCInterruptState ? ATIM_CH2CR_CIEA_Msk : 0)); +} + +/** + * @brief CH2B比较输出设置 + * @param ATIM_OCInitStruct + */ +void ATIM_OC2BInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_MODE(ATIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_POLARITY(ATIM_OCInitStruct->OCPolarity)); + assert_param(IS_ATIM_OC_IT(ATIM_OCInitStruct->OCInterruptSelect)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->BufferState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCDMAState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCInterruptState)); + REGBITS_MODIFY(CW_ATIM->FLTR, ATIM_FLTR_OCM2BFLT2B_Msk | ATIM_FLTR_CCP2B_Msk, + (ATIM_OCInitStruct->OCMode << 12) | (ATIM_OCInitStruct->OCPolarity << 15)); + REGBITS_MODIFY(CW_ATIM->CH2CR, ATIM_CH2CR_CISB_Msk | ATIM_CH2CR_BUFEB_Msk | ATIM_CH2CR_CDEB_Msk | ATIM_CH2CR_CIEB_Msk, + (ATIM_OCInitStruct->OCInterruptSelect << 12) | \ + (ATIM_OCInitStruct->BufferState ? ATIM_CH2CR_BUFEB_Msk : 0) | \ + (ATIM_OCInitStruct->OCDMAState ? ATIM_CH2CR_CDEB_Msk : 0) | \ + (ATIM_OCInitStruct->OCInterruptState ? ATIM_CH2CR_CIEB_Msk : 0)); +} + +/** + * @brief CH3A比较输出设置 + * @param ATIM_OCInitStruct + */ +void ATIM_OC3AInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_MODE(ATIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_POLARITY(ATIM_OCInitStruct->OCPolarity)); + assert_param(IS_ATIM_OC_IT(ATIM_OCInitStruct->OCInterruptSelect)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->BufferState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCDMAState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCInterruptState)); + REGBITS_MODIFY(CW_ATIM->FLTR, ATIM_FLTR_OCM3AFLT3A_Msk | ATIM_FLTR_CCP3A_Msk, + (ATIM_OCInitStruct->OCMode << 16) | (ATIM_OCInitStruct->OCPolarity << 19)); + CW_ATIM->CR_f.CISA = ATIM_OCInitStruct->OCInterruptSelect; + REGBITS_MODIFY(CW_ATIM->CH3CR, ATIM_CH3CR_BUFEA_Msk | ATIM_CH3CR_CDEA_Msk | ATIM_CH3CR_CIEA_Msk, + (ATIM_OCInitStruct->BufferState ? ATIM_CH3CR_BUFEA_Msk : 0) | \ + (ATIM_OCInitStruct->OCDMAState ? ATIM_CH3CR_CDEA_Msk : 0) | \ + (ATIM_OCInitStruct->OCInterruptState ? ATIM_CH3CR_CIEA_Msk : 0)); +} + +/** + * @brief CH3B比较输出设置 + * @param ATIM_OCInitStruct + */ +void ATIM_OC3BInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_MODE(ATIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_POLARITY(ATIM_OCInitStruct->OCPolarity)); + assert_param(IS_ATIM_OC_IT(ATIM_OCInitStruct->OCInterruptSelect)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->BufferState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCDMAState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCInterruptState)); + REGBITS_MODIFY(CW_ATIM->FLTR, ATIM_FLTR_OCM3BFLT3B_Msk | ATIM_FLTR_CCP3B_Msk, + (ATIM_OCInitStruct->OCMode << 20) | (ATIM_OCInitStruct->OCPolarity << 23)); + REGBITS_MODIFY(CW_ATIM->CH3CR, ATIM_CH3CR_CISB_Msk | ATIM_CH3CR_BUFEB_Msk | ATIM_CH3CR_CDEB_Msk | ATIM_CH3CR_CIEB_Msk, + (ATIM_OCInitStruct->OCInterruptSelect << 12) | \ + (ATIM_OCInitStruct->BufferState ? ATIM_CH3CR_BUFEB_Msk : 0) | \ + (ATIM_OCInitStruct->OCDMAState ? ATIM_CH3CR_CDEB_Msk : 0) | \ + (ATIM_OCInitStruct->OCInterruptState ? ATIM_CH3CR_CIEB_Msk : 0)); +} + + +/** + * @brief 通道4的比较设置 + * @param NewState 通道比较使能 + * @param ITSelect 中断产生条件选择，参数为下列参数之一 + * @arg ATIM_OC_IT_NONE + * @arg ATIM_OC_IT_UP_COUNTER + * @arg ATIM_OC_IT_DOWN_COUNTER + * @arg ATIM_OC_IT_BOTH_COUNTER + * @param DMAState 比较触发DMA使能 + * @param ITState 比较触发中断使能 + * @param BufferState 比较缓存使能控制 + */ +void ATIM_OC4Init(FunctionalState NewState, uint32_t ITSelect, FunctionalState DMAState, + FunctionalState ITState, FunctionalState BufferState) +{ + assert_param(IS_ATIM_OC_IT(ITSelect)); + CW_ATIM->CH4CR = (NewState ? 1UL << 5 : 0) | (ITSelect << 3) | (DMAState ? 1UL << 2 : 0) | \ + (ITState ? 1UL << 1 : 0) | (BufferState ? 1 : 0); +} + +/** + * @brief 设置PWM输出的参数 + * + * @param OCREFAType 比较器A单点比较或双点比较 OCREFA_TYPE_SINGLE OCREFA_TYPE_DOUBLE + * @param OutputType PWM输出类型独立或互补 OUTPUT_TYPE_ALONE OUTPUT_TYPE_COMP + * @param Deadtime 死区时间，单位为定时器的计数时隙。-1：禁止， 0~0xFF：插入的死区时隙 + * 取值范围。 + */ +void ATIM_PWMOutputConfig(uint32_t OCREFAType, uint32_t OutputType, int16_t Deadtime) +{ + assert_param(IS_ATIM_OCREFA_TYPE(OCREFAType)); + assert_param(IS_ATIM_OUTPUT_TYPE(OutputType)); + assert_param(IS_ATIM_DEADTIME(Deadtime)); + REGBITS_MODIFY(CW_ATIM->CR, ATIM_CR_COMP_Msk | ATIM_CR_PWM2S_Msk, OCREFAType | OutputType); + if (Deadtime >= 0) + { + CW_ATIM->DTR_f.DTEN = 1; + CW_ATIM->DTR_f.DTR = Deadtime; + } + else + { + CW_ATIM->DTR_f.DTEN = 0; + } +} + +void ATIM_CtrlPWMOutputs(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + CW_ATIM->DTR_f.MOE = NewState; +} + +/** + * @brief 设置外部触发参数 + * @param ATIM_ETRPolarity 外部触发信号有效极性 参数为下列参数之一： + * @arg ATIM_ETR_POLARITY_NONINVERT: 同相 + * @arg ATIM_ETR_POLARITY_INVERT: 反相 + * @param ETRFilter 外部触发通道的滤波设置 参数为下列参数之一： + * @arg ATIM_ETR_FILTER_NONE: 无滤波 + * @arg ATIM_ETR_FILTER_PCLK_N3: PCLK时钟采样，3个连续有效 + * @arg ATIM_ETR_FILTER_PCLKDIV4_N3: PCLK/4时钟采样，3个连续有效 + * @arg ATIM_ETR_FILTER_PCLKDIV16_N3: PCLK/16时钟采样，3个连续有效 + * @arg ATIM_ETR_FILTER_PCLKDIV64_N3: PCLK/64时钟采样，3个连续有效 + */ +void ATIM_ETRConfig(uint32_t ATIM_ETRPolarity, uint32_t ATIM_ETRFilter) +{ + assert_param(IS_ATIM_ETR_POLARITY(ATIM_ETRPolarity)); + assert_param(IS_ATIM_ETR_FILTER(ATIM_ETRFilter)); + REGBITS_MODIFY(CW_ATIM->FLTR, + ATIM_FLTR_ETP_Msk | ATIM_FLTR_FLTET_Msk, + ATIM_ETRPolarity | ATIM_ETRFilter); +} + +/** + * @brief 设置Brake输入信号的参数 + * @param ATIM_BrakePolarity 信号极性，参数为下列参数之一： + * @arg ATIM_BRAKE_POLARITY_NONINVERT: 同相 + * @arg ATIM_BRAKE_POLARITY_INVERT: 反相 + * @param ATIM_BrakeFilter + * @arg ATIM_BRAKE_FILTER_NONE: 无滤波 + * @arg ATIM_BRAKE_FILTER_PCLK_N3: PCLK时钟采样，3个连续有效 + * @arg ATIM_BRAKE_FILTER_PCLKDIV4_N3: PCLK/4时钟采样，3个连续有效 + * @arg ATIM_BRAKE_FILTER_PCLKDIV16_N3: PCLK/16时钟采样，3个连续有效 + * @arg ATIM_BRAKE_FILTER_PCLKDIV64_N3: PCLK/64时钟采样，3个连续有效 + */ +void ATIM_BrakeConfig(uint32_t ATIM_BrakePolarity, uint32_t ATIM_BrakeFilter) +{ + assert_param(IS_ATIM_BRAKE_POLARITY(ATIM_BrakePolarity)); + assert_param(IS_ATIM_BRAKE_FILTER(ATIM_BrakeFilter)); + REGBITS_MODIFY(CW_ATIM->FLTR, + ATIM_FLTR_BKP_Msk | ATIM_FLTR_FLTBK_Msk, + ATIM_BrakePolarity | ATIM_BrakeFilter); +} + +/** + * @brief 设置ATIM触发ADC的采样的触发源 + * @param ATIM_ADCTriggerSource 参数为下列参数之一 + * @arg ATIM_ADC_TRIGGER_CH3B + * @arg ATIM_ADC_TRIGGER_CH2B + * @arg ATIM_ADC_TRIGGER_CH1B + * @arg ATIM_ADC_TRIGGER_CH3A + * @arg ATIM_ADC_TRIGGER_CH2A + * @arg ATIM_ADC_TRIGGER_CH1A + * @arg ATIM_ADC_TRIGGER_UPDATA_EVENT + * @param NewState DISABLE或ENABLE + */ +void ATIM_ADCTriggerConfig(uint32_t ATIM_ADCTriggerSource, FunctionalState NewState) +{ + assert_param(IS_ATIM_ADC_TRIGGER(ATIM_ADCTriggerSource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + CW_ATIM->TRIG |= (ATIM_ADCTriggerSource | ATIM_ADC_TRIGGER_GLOBAL); + } + else + { + CW_ATIM->TRIG &= ~ATIM_ADCTriggerSource; + } +} + +uint16_t ATIM_GetCapture1A(void) +{ + return (uint16_t) CW_ATIM->CH1CCRA; +} + + +uint16_t ATIM_GetCapture2A(void) +{ + return (uint16_t) CW_ATIM->CH2CCRA; +} + + +uint16_t ATIM_GetCapture3A(void) +{ + return (uint16_t) CW_ATIM->CH3CCRA; +} + + +uint16_t ATIM_GetCapture1B(void) +{ + return (uint16_t) CW_ATIM->CH1CCRB; +} + + +uint16_t ATIM_GetCapture2B(void) +{ + return (uint16_t) CW_ATIM->CH2CCRB; +} + + +uint16_t ATIM_GetCapture3B(void) +{ + return (uint16_t) CW_ATIM->CH3CCRB; +} + + +void ATIM_SetCompare1A(uint16_t Compare) +{ + CW_ATIM->CH1CCRA = (uint32_t)Compare; +} + +void ATIM_SetCompare2A(uint16_t Compare) +{ + CW_ATIM->CH2CCRA = (uint32_t)Compare; +} + +void ATIM_SetCompare3A(uint16_t Compare) +{ + CW_ATIM->CH3CCRA = (uint32_t)Compare; +} + +void ATIM_SetCompare1B(uint16_t Compare) +{ + CW_ATIM->CH1CCRB = (uint32_t)Compare; +} + +void ATIM_SetCompare2B(uint16_t Compare) +{ + CW_ATIM->CH2CCRB = (uint32_t)Compare; +} + +void ATIM_SetCompare3B(uint16_t Compare) +{ + CW_ATIM->CH3CCRB = (uint32_t)Compare; +} + +void ATIM_SetCompare4(uint16_t Compare) +{ + CW_ATIM->CH4CCR = (uint32_t) Compare; +} + +void ATIM_MasterModeConfig(uint8_t ATIM_MasterOutput) +{ + assert_param(IS_ATIM_MASTER_OUTPUT(ATIM_MasterOutput)); + CW_ATIM->MSCR_f.MMS = ATIM_MasterOutput; +} + +void ATIM_SlaverModeConfig(uint8_t ATIM_SlaverType) +{ + assert_param(IS_ATIM_SLAVER_TYPE(ATIM_SlaverType)); + CW_ATIM->MSCR_f.SMS = ATIM_SlaverType; +} + +void ATIM_TriggerSelect(uint8_t ATIM_TriggerSource) +{ + assert_param(IS_ATIM_TRIGGER_SOURCE(ATIM_TriggerSource)); + CW_ATIM->MSCR_f.TS = ATIM_TriggerSource; +} + +void ATIM_UpdateEventSelect(uint8_t ATIM_UpdateEvent) +{ + assert_param(IS_ATIM_UPDATE_EVENT(ATIM_UpdateEvent)); + CW_ATIM->CR_f.URS = ATIM_UpdateEvent; +} diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_awt.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_awt.c new file mode 100644 index 0000000..7bbc9a6 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_awt.c @@ -0,0 +1,214 @@ +/** + * @file cw32f030_awt.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-18 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_awt.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief AWT 去初始化 + * + */ +void AWT_DeInit(void) +{ + CW_AWT->CR = 0UL; + CW_AWT->ARR = 0x0000FFFFUL; + CW_AWT->IER = 0UL; + CW_AWT->ICR = 0UL; +} + +/** + * @brief AWT定时器计数初始化 + * + * @param AWT_TimeCntInitStruct + */ +void AWT_TimeCntInit(AWT_TimeCntInitTypeDef *AWT_TimeCntInitStruct) +{ + assert_param(IS_AWT_CLKSOURCE(AWT_TimeCntInitStruct->AWT_ClkSource)); + assert_param(IS_AWT_PRS_DIV(AWT_TimeCntInitStruct->AWT_Prescaler)); + assert_param(IS_AWT_ARR(AWT_TimeCntInitStruct->AWT_Period)); + assert_param(IS_AWT_MODE(AWT_TimeCntInitStruct->AWT_Mode)); + REGBITS_MODIFY(CW_AWT->CR, AWT_CR_SRC_Msk | \ + AWT_CR_PRS_Msk | \ + AWT_CR_MD_Msk + , \ + AWT_TimeCntInitStruct->AWT_ClkSource | \ + AWT_TimeCntInitStruct->AWT_Prescaler | \ + AWT_TimeCntInitStruct->AWT_Mode); + CW_AWT->ARR = AWT_TimeCntInitStruct->AWT_Period; +} + +/** + * @brief 结构体数据AWT_TimeCntInitStruct初始化 + * + * @param AWT_TimeCntInitStruct + */ +void AWT_TimeCntStructInit(AWT_TimeCntInitTypeDef *AWT_TimeCntInitStruct) +{ + AWT_TimeCntInitStruct->AWT_ClkSource = AWT_CLKSOURCE_HSIOSC; + AWT_TimeCntInitStruct->AWT_Prescaler = AWT_PRS_DIV2; + AWT_TimeCntInitStruct->AWT_Mode = AWT_MODE_TIMECNT; + AWT_TimeCntInitStruct->AWT_Period = (uint32_t)0x0000FFFF; +} + +/** + * @brief 使能AWT定时器 + * + * @param NewState + */ +void AWT_Cmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + CW_AWT->CR |= AWT_CR_EN; + } + else + { + CW_AWT->CR &= (~AWT_CR_EN); + } +} + +/** + * @brief 配置AWT的中断 + * + * @param AWT_IT + * @param NewState + */ +void AWT_ITConfig(uint32_t AWT_IT, FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_AWT_IT(AWT_IT)); + if (NewState != DISABLE) + { + CW_AWT->IER |= AWT_IT; + } + else + { + CW_AWT->IER &= (~AWT_IT); + } +} + + +/** + * @brief 获取AWT中断标志 + * + * @param AWT_IT + * @return ITStatus + */ +ITStatus AWT_GetITStatus(uint32_t AWT_IT) +{ + assert_param(IS_AWT_IT(AWT_IT)); + return (CW_AWT->ISR & AWT_IT) ? SET : RESET; +} + +/** + * @brief 清除AWT中断标志 + * + * @param AWT_IT + */ +void AWT_ClearITPendingBit(uint32_t AWT_IT) +{ + assert_param(IS_AWT_IT(AWT_IT)); + CW_AWT->ICR &= (~AWT_IT); +} + +/** + * @brief AWT计数时钟源配置 + * + * @param AWT_ClkSrouce + */ +void AWT_ClkSourceConfig(uint32_t AWT_ClkSource) +{ + assert_param(IS_AWT_CLKSOURCE(AWT_ClkSource)); + REGBITS_MODIFY(CW_AWT->CR, AWT_CR_SRC_Msk, AWT_ClkSource); +} + +/** + * @brief AWT计数时钟分频系数配置 + * + * @param Prescaler + */ +void AWT_PrescalerConfig(uint32_t AWT_Prescaler) +{ + assert_param(IS_AWT_PRS_DIV(AWT_Prescaler)); + REGBITS_MODIFY(CW_AWT->CR, AWT_CR_PRS_Msk, AWT_Prescaler); +} + +/** + * @brief 读取AWT计数器CNT寄存器值 + * + * @return uint16_t + */ +uint16_t AWT_GetCounter(void) +{ + return (uint16_t)(CW_AWT->CNT); +} + +/** + * @brief 读取AWT计数器重载值寄存器ARR值 + * + * @return uint16_t + */ +uint16_t AWT_GetAutoreload(void) +{ + return (uint16_t)(CW_AWT->ARR); +} + +/** + * @brief 读取AWT时钟源 + * + * @return uint32_t + */ +uint32_t AWT_GetClkSource(void) +{ + return (uint32_t)((CW_AWT->CR_f.SRC)); +} + +/** + * @brief 读取AWT时钟分频系数 + * + * @return uint32_t + */ +uint32_t AWT_GetPrescaler(void) +{ + return (uint32_t)((CW_AWT->CR_f.PRS)); +} + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_btim.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_btim.c new file mode 100644 index 0000000..6db0cac --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_btim.c @@ -0,0 +1,338 @@ +/** + * @file cw32f030_btim.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-04-22 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_btim.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/******************************************************************************* +// 说明：去初始化 +// 参数：BTIMx x为1~3 +// 返回值：无 +*******************************************************************************/ + +void BTIM_DeInit(BTIM_TypeDef *BTIMx) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + BTIMx->BCR = 0UL; + BTIMx->ARR = 0x0000FFFF; + BTIMx->CNT = 0UL; + BTIMx->ACR = 0UL; + BTIMx->IER = 0UL; + BTIMx->ICR = 0UL; + BTIMx->DMA = 0UL; +} + +/******************************************************************************* +// 说明：BTIM基本定时器初始化 +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_TimeBaseInitStruct 指向BTIM_TimeBaseInitTypeDef类型结构体的指针 +// 返回值：无 +*******************************************************************************/ +void BTIM_TimeBaseInit(BTIM_TypeDef *BTIMx, BTIM_TimeBaseInitTypeDef *BTIM_TimeBaseInitStruct) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_MODE(BTIM_TimeBaseInitStruct->BTIM_Mode)); + assert_param(IS_BTIM_PRS_DIV(BTIM_TimeBaseInitStruct->BTIM_Prescaler)); + REGBITS_MODIFY(BTIMx->BCR, BTIMx_BCR_MODE_Msk | BTIMx_BCR_PRS_Msk | BTIMx_BCR_ONESHOT_Msk, + BTIM_TimeBaseInitStruct->BTIM_Mode | BTIM_TimeBaseInitStruct->BTIM_Prescaler | + BTIM_TimeBaseInitStruct->BTIM_OPMode); + BTIMx->ARR = BTIM_TimeBaseInitStruct->BTIM_Period; +} + +/******************************************************************************* +// 说明：结构体数据BTIM_TimeBaseInitStruct初始化 +// 参数：BTIM_TimeBaseInitStruct +// 返回值：无 +*******************************************************************************/ + +void BTIM_TimeBaseStructInit(BTIM_TimeBaseInitTypeDef *BTIM_TimeBaseInitStruct) +{ + BTIM_TimeBaseInitStruct->BTIM_Prescaler = BTIM_PRS_DIV1; + BTIM_TimeBaseInitStruct->BTIM_Mode = BTIM_Mode_TIMER; + BTIM_TimeBaseInitStruct->BTIM_Period = 0xFFFF; +} + +/******************************************************************************* +// 说明：使能BTIMx定时器 +// 参数：BTIM_TimeBaseInitStruct +// 返回值：无 +*******************************************************************************/ +void BTIM_Cmd(BTIM_TypeDef *BTIMx, FunctionalState NewState) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + NewState ? (BTIMx->BCR |= BTIMx_BCR_EN_Msk) : (BTIMx->BCR &= ~BTIMx_BCR_EN_Msk); +} + + +/******************************************************************************* +// 说明：配置BTIMx的中断 +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_IT 中断事件类型 +// 参数：NewState 中断事件类型的状态，ENABLE 或 DISABLE +// 返回值：无 +*******************************************************************************/ +void BTIM_ITConfig(BTIM_TypeDef *BTIMx, uint16_t BTIM_IT, FunctionalState NewState) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_BTIM_IT(BTIM_IT)); + NewState ? (BTIMx->IER |= BTIM_IT) : (BTIMx->IER &= ~BTIM_IT); +} + + +/******************************************************************************* +// 说明：配置BTIMx的DMA功能 +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_DMASource DMA触发事件类型 +// 参数：NewState 中断事件类型的状态，ENABLE 或 DISABLE +// 返回值：无 +*******************************************************************************/ +void BTIM_DMACmd(BTIM_TypeDef *BTIMx, uint16_t BTIM_DMASource, FunctionalState NewState) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_BTIM_DMA_SOURCE(BTIM_DMASource)); + NewState ? (BTIMx->DMA |= BTIM_DMASource) : (BTIMx->DMA &= ~BTIM_DMASource); +} + +/******************************************************************************* +// 说明：配置BTIMx的预分配系数 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Prescaler 预分配系数 +// 参数：BTIM_PSCReloadMode 预分配系数是立即更新还是在溢出时更新,取值范围 +// BTIM_PSCReloadMode_Update 预分配系数在溢出时更新 +// BTIM_PSCReloadMode_Immediate 预分配系数立即更新 +// 返回值：无 +*******************************************************************************/ +void BTIM_PrescalerConfig(BTIM_TypeDef *BTIMx, uint16_t Prescaler, uint16_t BTIM_PSCReloadMode) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_PRS_DIV(Prescaler)); + assert_param(IS_BTIM_PRESCALER_RELOAD(BTIM_PSCReloadMode)); + REGBITS_MODIFY(BTIMx->BCR, BTIMx_BCR_PRS_Msk, Prescaler); + if (BTIM_PSCReloadMode == BTIM_PSCReloadMode_Immediate) + { + BTIMx->BCR &= ~BTIMx_BCR_EN_Msk; + BTIMx->BCR |= BTIMx_BCR_EN_Msk; + } +} + +/******************************************************************************* +// 说明：配置BTIMx的工作模式 +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_Mode 模式类型 +// BTIM_Mode_TIMER 定时器模式 +// BTIM_Mode_COUNTER 计数器模式 +// BTIM_Mode_TRIGGER 触发启动模式 +// BTIM_Mode_GATE 门控模式 +// 返回值：无 +*******************************************************************************/ +void BTIM_ModeConfig(BTIM_TypeDef *BTIMx, uint16_t BTIM_Mode) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_MODE(BTIM_Mode)); + REGBITS_MODIFY(BTIMx->BCR, BTIMx_BCR_MODE_Msk, BTIM_Mode); +} + +/******************************************************************************* +// 说明：配置BTIMx的触发输入信号来源 +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_InputTriggerSource 触发源 +// BTIM_TS_ITR 内部ITR信号 +// BTIM_TS_ETR 外部ETR信号 +// 返回值：无 +*******************************************************************************/ +void BTIM_SelectInputTrigger(BTIM_TypeDef *BTIMx, uint16_t BTIM_InputTriggerSource) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_TRIGGER_SELECTION(BTIM_InputTriggerSource)); + REGBITS_MODIFY(BTIMx->BCR, BTIMx_BCR_TRS_Msk, BTIM_InputTriggerSource); +} + +/******************************************************************************* +// 说明：配置BTIMx外部输入ETR信号的极性 +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_ETR_Polarity 极性类型 +// BTIM_ETR_Polarity_Positive 正极性 +// BTIM_ETR_Polarity_Negative 负极性 +// 返回值：无 +*******************************************************************************/ +void BTIM_SelectETRInputPolarity(BTIM_TypeDef *BTIMx, uint16_t BTIM_ETR_Polarity) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_ETR_POLARITY(BTIM_ETR_Polarity)); + REGBITS_MODIFY(BTIMx->BCR, BTIMx_BCR_POL_Msk, BTIM_ETR_Polarity); +} + +/******************************************************************************* +// 说明：配置BTIMx的单次运行模式 +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_OPMode 运行类型 +// BTIM_OPMode_Single 单次运行 +// BTIM_OPMode_Repetitive 连续运行 +// 返回值：无 +*******************************************************************************/ +void BTIM_SelectOnePulseMode(BTIM_TypeDef *BTIMx, uint16_t BTIM_OPMode) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_OPM_MODE(BTIM_OPMode)); + REGBITS_MODIFY(BTIMx->BCR, BTIMx_BCR_ONESHOT_Msk, BTIM_OPMode); +} + +/******************************************************************************* +// 说明：配置BTIMx的翻转输出功能 +// 参数：BTIMx CW_BTIM1~3 +// 参数：NewState ENABLE 或 DISABLE +// 返回值：无 +*******************************************************************************/ +void BTIM_OutputToggleCmd(BTIM_TypeDef *BTIMx, FunctionalState NewState) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + NewState ? (BTIMx->BCR |= BTIMx_BCR_TOGEN_Msk) : (BTIMx->BCR &= ~BTIMx_BCR_TOGEN_Msk); +} + +/******************************************************************************* +// 说明：配置BTIMx的外部输入ETR +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_ExtTRGPolarity ETR信号的极性 BTIM_ETR_Polarity_Positive +// BTIM_ETR_Polarity_Negative +// 参数：ExtTRGFilter ETR滤波器配置 +// 返回值：无 +*******************************************************************************/ +void BTIM_ETRConfig(BTIM_TypeDef *BTIMx, uint16_t BTIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_ETR_POLARITY(BTIM_ExtTRGPolarity)); + assert_param(IS_BTIM_EXT_FILTER(ExtTRGFilter)); + REGBITS_MODIFY(BTIMx->BCR, BTIMx_BCR_POL_Msk, BTIM_ExtTRGPolarity); + REGBITS_MODIFY(BTIMx->ACR, BTIMx_ACR_ETRFLT_Msk, ExtTRGFilter); +} + +/******************************************************************************* +// 说明：设置BTIM的计数初值 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Counter 范围0x0000~0xFFFF +// 返回值：无 +*******************************************************************************/ +void BTIM_SetCounter(BTIM_TypeDef *BTIMx, uint16_t Counter) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + BTIMx->CNT = Counter; +} + +/******************************************************************************* +// 说明：设置BTIM的自动重载值 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Autoreload 范围0x0000~0xFFFF +// 返回值：无 +*******************************************************************************/ +void BTIM_SetAutoreload(BTIM_TypeDef *BTIMx, uint16_t Autoreload) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + BTIMx->ARR = Autoreload; +} + +/******************************************************************************* +// 说明：获取BTIM的当前计数值 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：CNT寄存器的值 +*******************************************************************************/ +uint16_t BTIM_GetCounter(BTIM_TypeDef *BTIMx) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + return BTIMx->CNT; +} + +/******************************************************************************* +// 说明：获取BTIM的当前自动重载值 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：ARR寄存器的值 +*******************************************************************************/ +uint16_t BTIM_GetAutoreload(BTIM_TypeDef *BTIMx) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + return BTIMx->ARR; +} + +/******************************************************************************* +// 说明：获取BTIM的当前预分配系数 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：预分频器当前正在使用的分频系数 +*******************************************************************************/ +uint16_t BTIM_GetPrescaler(BTIM_TypeDef *BTIMx) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + return BTIMx->BCR_f.PRSSTATUS; +} +/******************************************************************************* +// 说明： 检查BTIM的状态寄存器的各状态位是否置位 +// 参数： BTIMx CW_BTIM1~3 +// 参数： BTIM_FLAG 指定的状态位 ，参数范围： BTIM_IT_OV +// BTIM_IT_TI +// BTIM_IT_TOP +// +// 返回值： ITStatus +*******************************************************************************/ +ITStatus BTIM_GetITStatus(BTIM_TypeDef *BTIMx, uint16_t BTIM_FLAG) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_IT(BTIM_FLAG)); + return (REGBITS_GET(BTIMx->ISR, BTIM_FLAG) ? SET : RESET); +} + +/******************************************************************************* +// 说明： 清除BTIM的状态寄存器的各状态位 +// 参数： BTIMx CW_BTIM1~3 +// 参数： BTIM_FLAG 指定的状态位 ，参数范围： BTIM_IT_OV +// BTIM_IT_TI +// BTIM_IT_TOP +// +// 返回值： 预分频器当前正在使用的分频系数 +*******************************************************************************/ + +void BTIM_ClearITPendingBit(BTIM_TypeDef *BTIMx, uint16_t BTIM_FLAG) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_IT(BTIM_FLAG)); + REGBITS_CLR(BTIMx->ICR, BTIM_FLAG); +} + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_crc.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_crc.c new file mode 100644 index 0000000..abf44c0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_crc.c @@ -0,0 +1,190 @@ +/** + * @file cw32f030_crc.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-08 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_crc.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief 采用8bit方式，计算CRC16 + * + * @param CrcMode : CRC16_IBM CRC16_MAXIM + * CRC16_USB CRC16_MODBUS + * CRC16_CCITT CRC16_CCITTFALSE + * CRC16_X25 CRC16_XMODEM + * @param pByteBuf : uint8_t型Buffer指针 + * @param ByteCnt ：0x01 - 0xFFFF + * @return uint16_t ：0x00 - 0xFFFF + */ +uint16_t CRC16_Calc_8bit(uint8_t CrcMode, uint8_t *pByteBuf, uint16_t ByteCnt) +{ + /* Check the parameters */ + assert_param(IS_CRC_CRC16_MODE(CrcMode)); + CW_CRC->CR = CrcMode; + while (ByteCnt) + { + CW_CRC->DR8 = *pByteBuf; + pByteBuf++; + ByteCnt--; + } + return (CW_CRC->RESULT16); +} + + +/** + * @brief 采用16bit方式，计算CRC16 + * + * @param CrcMode : CRC16_IBM CRC16_MAXIM + * CRC16_USB CRC16_MODBUS + * CRC16_CCITT CRC16_CCITTFALSE + * CRC16_X25 CRC16_XMODEM + * @param pHWBuf : uint16_t型Buffer指针 + * @param HalfWordCnt ：0x01 - 0xFFFF + * @return uint16_t ：0x00 - 0xFFFF + */ +uint16_t CRC16_Calc_16bit(uint8_t CrcMode, uint16_t *pHWBuf, uint16_t HalfWordCnt) +{ + /* Check the parameters */ + assert_param(IS_CRC_CRC16_MODE(CrcMode)); + CW_CRC->CR = CrcMode; + while (HalfWordCnt) + { + CW_CRC->DR16 = *pHWBuf; + pHWBuf++; + HalfWordCnt--; + } + return (CW_CRC->RESULT16); +} + + +/** + * @brief 采用32bit方式，计算CRC16 + * + * @param CrcMode : CRC16_IBM CRC16_MAXIM + * CRC16_USB CRC16_MODBUS + * CRC16_CCITT CRC16_CCITTFALSE + * CRC16_X25 CRC16_XMODEM + * @param pWBuf : uint32_t型Buffer指针 + * @param WordCnt ：0x01 - 0xFFFF + * @return uint16_t ：0x00 - 0xFFFF + */ +uint16_t CRC16_Calc_32bit(uint8_t CrcMode, uint32_t *pWBuf, uint16_t WordCnt) +{ + /* Check the parameters */ + assert_param(IS_CRC_CRC16_MODE(CrcMode)); + CW_CRC->CR = CrcMode; + while (WordCnt) + { + CW_CRC->DR32 = *pWBuf; + pWBuf++; + WordCnt--; + } + return (CW_CRC->RESULT16); +} + +/** + * @brief 采用8bit方式，计算CRC32 + * + * @param CrcMode : CRC32_DEFAULT CRC32_MPEG2 + * @param pByteBuf : uint8_t型Buffer指针 + * @param ByteCnt ：0x01 - 0xFFFF + * @return uint32_t ：0x00 - 0xFFFF FFFF + */ +uint32_t CRC32_Calc_8bit(uint8_t CrcMode, uint8_t *pByteBuf, uint16_t ByteCnt) +{ + /* Check the parameters */ + assert_param(IS_CRC_CRC32_MODE(CrcMode)); + CW_CRC->CR = CrcMode; + while (ByteCnt) + { + CW_CRC->DR8 = *pByteBuf; + pByteBuf++; + ByteCnt--; + } + return (CW_CRC->RESULT32); +} + + +/** + * @brief 采用16bit方式，计算CRC32 + * + * @param CrcMode : CRC32_DEFAULT CRC32_MPEG2 + * @param pHWBuf : uint16_t型Buffer指针 + * @param HalfWordCnt ：0x01 - 0xFFFF + * @return uint32_t ：0x00 - 0xFFFF FFFF + */ +uint32_t CRC32_Calc_16bit(uint8_t CrcMode, uint16_t *pHWBuf, uint16_t HalfWordCnt) +{ + /* Check the parameters */ + assert_param(IS_CRC_CRC32_MODE(CrcMode)); + CW_CRC->CR = CrcMode; + while (HalfWordCnt) + { + CW_CRC->DR16 = *pHWBuf; + pHWBuf++; + HalfWordCnt--; + } + return (CW_CRC->RESULT32); +} + + +/** + * @brief 采用32bit方式，计算CRC16 + * + * @param CrcMode : CRC32_DEFAULT CRC32_MPEG2 + * @param pWBuf : uint32_t型Buffer指针 + * @param WordCnt ：0x01 - 0xFFFF + * @return uint32_t ：0x00 - 0xFFFF FFFF + */ +uint32_t CRC32_Calc_32bit(uint8_t CrcMode, uint32_t *pWBuf, uint16_t WordCnt) +{ + /* Check the parameters */ + assert_param(IS_CRC_CRC32_MODE(CrcMode)); + CW_CRC->CR = CrcMode; + while (WordCnt) + { + CW_CRC->DR32 = *pWBuf; + pWBuf++; + WordCnt--; + } + return (CW_CRC->RESULT32); +} + +//============================================================================= + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_debug.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_debug.c new file mode 100644 index 0000000..0ab45a1 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_debug.c @@ -0,0 +1,68 @@ +/** + * @file cw32f030_debug.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-13 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_debug.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief + * + * @param DBGMCU_Periph : DBGMCU_ATIM_STOP DBGMCU_GTIM1_STOP + * DBGMCU_GTIM2_STOP DBGMCU_GTIM3_STOP + * DBGMCU_GTIM4_STOP DBGMCU_BTIM123_STOP + * DBGMCU_AWT_STOP DBGMCU_RTC_STOP + * DBGMCU_IWDT_STOP DBGMCU_WWDT_STOP + * @param NewState : ENABLE DISABLE + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + CW_SYSCTRL->DEBUG |= DBGMCU_Periph; + } + else + { + CW_SYSCTRL->DEBUG &= ~DBGMCU_Periph; + } +} + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_digitalsign.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_digitalsign.c new file mode 100644 index 0000000..f5b4266 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_digitalsign.c @@ -0,0 +1,104 @@ +/** + * @file cw32f030_digitalsign.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-14 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_digitalsign.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief 获取芯片型号 + * + * @param pChipType : 存放芯片类型的Buffer，最长22字节 + */ +void DIGITALSIGN_GetChipType(uint8_t *pChipType) +{ + uint8_t tmpcnt = 0; + while (tmpcnt < CHIP_TYPE_LENGTH) + { + * (uint8_t *)(pChipType + tmpcnt) = *((uint8_t *)(CHIP_TYPE_BASE + tmpcnt)); + tmpcnt ++; + } +} + +/** + * @brief 获取芯片引脚数 + * + * @return uint16_t + */ +uint16_t DIGITALSIGN_GetPinCount(void) +{ + return (*((uint16_t *) PIN_COUNT_BASE)); +} + +/** + * @brief //获取FLASH容量// + * + * @return uint32_t + */ +uint32_t DIGITALSIGN_GetFlashSize(void) +{ + return (*((uint32_t *) FLASH_SIZE_BASE)); +} + +/** + * @brief //获取RAM容量// + * + * @return uint32_t + */ +uint32_t DIGITALSIGN_GetRamSize(void) +{ + return (*((uint32_t *) RAM_SIZE_BASE)); +} + +/** + * @brief 获取芯片UID + * + * @param pChipUid : 存放芯片UID的Buffer，10字节 + */ +void DIGITALSIGN_GetChipUid(uint8_t *pChipUid) +{ + uint8_t tmpcnt = 0; + while (tmpcnt < CHIP_UID_LENGTH) + { + * (uint8_t *)(pChipUid + tmpcnt) = *((uint8_t *)(CHIP_UID_BASE + tmpcnt)); + tmpcnt ++; + } +} + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_dma.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_dma.c new file mode 100644 index 0000000..4f04e85 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_dma.c @@ -0,0 +1,235 @@ +/** + * @file cw32f030_dma.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-17 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_dma.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +void DMA_DeInit(DMACHANNEL_TypeDef *DMA_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx)); + /* Disable the selected DMAy Channelx */ + DMA_Channelx->CSR &= (~DMA_CHANNEL_EN); ///disable DMA Channel + DMA_Channelx->CSR = 0x00UL; ///reset CSR register + DMA_Channelx->TRIG = 0x00UL; ///reset the trig register + DMA_Channelx->CNT = 0x00010000UL; ///reset the CNT register + DMA_Channelx->SRCADDR = 0x00UL; ///reset srcaddr register + DMA_Channelx->DSTADDR = 0x00UL; ///reset dstaddr register +} + +/** + * @brief DMA通道初始化 + * + * @param DMA_Channelx + * @param DMA_InitStruct + */ +void DMA_Init(DMACHANNEL_TypeDef *DMA_Channelx, DMA_InitTypeDef *DMA_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_TRANSFER_WIDTH(DMA_InitStruct->DMA_TransferWidth)); + assert_param(IS_DMA_SRCADDRESS_INC(DMA_InitStruct->DMA_SrcInc)); + assert_param(IS_DMA_DSTADDRESS_INC(DMA_InitStruct->DMA_DstInc)); + assert_param(IS_DMA_TRIG(DMA_InitStruct->TrigMode)); + assert_param(IS_DMA_HARD_TRIGSRC(DMA_InitStruct->HardTrigSource)); + assert_param(IS_DMA_TRANSFERCNT(DMA_InitStruct->DMA_TransferCnt)); + DMA_Channelx->CSR = ((DMA_Channelx->CSR & CSR_CLEAR_Mask) | \ + DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_TransferWidth | \ + DMA_InitStruct->DMA_SrcInc | DMA_InitStruct->DMA_DstInc); + DMA_Channelx->TRIG = ((DMA_Channelx->TRIG & TRIG_CLEAR_Mask) | DMA_InitStruct->TrigMode | \ + DMA_InitStruct->HardTrigSource) ; + DMA_Channelx->CNT = bv16 | DMA_InitStruct->DMA_TransferCnt ; + DMA_Channelx->SRCADDR = DMA_InitStruct->DMA_SrcAddress ; + DMA_Channelx->DSTADDR = DMA_InitStruct->DMA_DstAddress ; +} + + +/** + * @brief DMA结构初始化 + * + * @param DMA_InitStruct + */ +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) +{ + /*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_Mode */ + DMA_InitStruct->DMA_Mode = DMA_MODE_BLOCK; + /* Initialize the DMA_TransferWidth */ + DMA_InitStruct->DMA_TransferWidth = DMA_TRANSFER_WIDTH_8BIT; + /* Initialize the DMA_SrcInc */ + DMA_InitStruct->DMA_SrcInc = DMA_SrcAddress_Fix; + /* Initialize the DMA_DstInc */ + DMA_InitStruct->DMA_DstInc = DMA_DstAddress_Fix; + /* Initialize the TrigMode */ + DMA_InitStruct->TrigMode = DMA_SWTrig; + /* Initialize the HardTrigSource, if we use softtrig ,we can not config it*/ + DMA_InitStruct->HardTrigSource = DMA_HardTrig_UART1_RXBufferNE; + /* Initialize the DMA_TransferCnt */ + DMA_InitStruct->DMA_TransferCnt = 0x00; + /* Initialize the DMA_SrcAddress */ + DMA_InitStruct->DMA_SrcAddress = 0x00; + /* Initialize the DMA_DstAddress */ + DMA_InitStruct->DMA_DstAddress = 0x00; +} + +/** + * @brief 使能DMAy_Channelx 进行DMA传输 + * + * @param DMA_Channelx + * @param NewState + */ +void DMA_Cmd(DMACHANNEL_TypeDef *DMA_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMA_Channelx->CSR |= DMA_CHANNEL_EN; + } + else + { + /* Disable the selected DMAy Channelx */ + DMA_Channelx->CSR &= ~DMA_CHANNEL_EN; + } +} + + +/** + * @brief 通过软件置1，立即触发该通道启动传输 + * + * @param DMA_Channelx + */ +void DMA_SWTrigCmd(DMACHANNEL_TypeDef *DMA_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx)); + DMA_Channelx->TRIG |= DMA_SOFTTRIG_EN; +} + + +/** + * @brief 配置DMA_Channelx 指定中断使能 + * + * @param DMA_Channelx ：CW_DMACHANNEL1/2/3/4/5 + * @param DMA_IT ：DMA_IT_TC DMA_IT_TE + * @param NewState ：ENABLE DISABLE + */ +void DMA_ITConfig(DMACHANNEL_TypeDef *DMA_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMA_Channelx->CSR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMA_Channelx->CSR &= ~DMA_IT; + } +} + +/** + * @brief 获取DMA_Channelx's 指定中断标志。 + * @param DMAy_IT: specifies the DMAy interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC1: DMA Channel1 transfer complete interrupt. + * @arg DMA_IT_TE1: DMA Channel1 transfer error interrupt. + * @arg DMA_IT_TC2: DMA Channel2 transfer complete interrupt. + * @arg DMA_IT_TE2: DMA Channel2 transfer error interrupt. + * @arg DMA_IT_TC3: DMA Channel3 transfer complete interrupt. + * @arg DMA_IT_TE3: DMA Channel3 transfer error interrupt. + * @arg DMA_IT_TC4: DMA Channel4 transfer complete interrupt. + * @arg DMA_IT_TE4: DMA Channel4 transfer error interrupt. + * @arg DMA_IT_TC5: DMA Channel5 transfer complete interrupt. + * @arg DMA_IT_TE5: DMA Channel5 transfer error interrupt. + * @retval The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMA_IT)); + return (CW_DMA->ISR & DMA_IT) ? SET : RESET; +} + +/** + * @brief 清除DMA_Channelx's 指定中断标志。 + * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA_IT_TC1: DMA Channel1 transfer complete interrupt. + * @arg DMA_IT_TE1: DMA Channel1 transfer error interrupt. + * @arg DMA_IT_TC2: DMA Channel2 transfer complete interrupt. + * @arg DMA_IT_TE2: DMA Channel2 transfer error interrupt. + * @arg DMA_IT_TC3: DMA Channel3 transfer complete interrupt. + * @arg DMA_IT_TE3: DMA Channel3 transfer error interrupt. + * @arg DMA_IT_TC4: DMA Channel4 transfer complete interrupt. + * @arg DMA_IT_TE4: DMA Channel4 transfer error interrupt. + * @arg DMA_IT_TC5: DMA Channel5 transfer complete interrupt. + * @arg DMA_IT_TE5: DMA Channel5 transfer error interrupt. + * @retval None + */ +void DMA_ClearITPendingBit(uint32_t DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_IT(DMA_IT)); + CW_DMA->ICR &= (~DMA_IT); +} + +/** + * @brief 获取DMAy Channelx传输状态 + * + * @param DMA_Channelx ：CW_DMACHANNEL1/2/3/4/5 + * @return uint8_t : DMA_CHANNEL_STATUS_INIT DMA_CHANNEL_STATUS_ADDRESSOUTRANGE + * DMA_CHANNEL_STATUS_STOPREQ DMA_CHANNEL_STATUS_SRCADDERR + * DMA_CHANNEL_STATUS_DSTADDERR DMA_CHANNEL_STATUS_TRANSCOMPLETE + */ +uint8_t DMA_GetFlagStatus(DMACHANNEL_TypeDef *DMA_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx)); + return ((uint8_t)(DMA_Channelx->CSR >> 8)); +} + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_flash.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_flash.c new file mode 100644 index 0000000..c08147d --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_flash.c @@ -0,0 +1,499 @@ +/** + * @file cw32f030_flash.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-08 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_flash.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief 设置FLASH的读等待周期 + * + * @param FLASH_Latency ：FLASH_Latency_1 FLASH_Latency_2 FLASH_Latency_3 + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmp8; + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + CW_SYSCTRL->AHBEN_f.FLASH = 1; + tmp8 = FLASH_Latency > 0 ? (FLASH_Latency | bv3 | bv4) : 0; //WAIT不为0时，需要开启FETCH及CACHE + CW_FLASH->CR2 = 0x5A5A0000 | tmp8; +} + +/** + * @brief 预取功能设置 + * + * @param FLASH_Prefetch ：FLASH_Prefetch_Enable FLASH_Prefetch_Disable + */ +void FLASH_PrefetchCmd(uint32_t FLASH_Prefetch) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PREFETCH_STATE(FLASH_Prefetch)); + /* Enable or disable the Prefetch Buffer */ + CW_SYSCTRL->AHBEN_f.FLASH = 1; + CW_FLASH->CR2 = (CW_FLASH->CR2 & (~bv3)) | 0x5A5A0000 | FLASH_Prefetch; +} + +/** + * @brief CACHE功能设置 + * + * @param FLASH_Cache :FLASH_Cache_Enable FLASH_Cache_Disable + */ +void FLASH_CacheCmd(uint32_t FLASH_Cache) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CACHE_STATE(FLASH_Cache)); + /* Enable or disable the Prefetch Buffer */ + CW_SYSCTRL->AHBEN_f.FLASH = 1; + CW_FLASH->CR2 = (CW_FLASH->CR2 & (~bv4)) | 0x5A5A0000 | FLASH_Cache; +} + +/** + * @brief 获取Prefetch 开关情况 + * + * @return FlagStatus ：SET RESET + */ +FlagStatus FLASH_GetPrefetchStatus(void) +{ + return (CW_FLASH->CR2_f.FETCH ? SET : RESET); +} + +/** + * @brief 获取Buffer 开关情况 + * + * @return FlagStatus ：SET RESET + */ +FlagStatus FLASH_GetCacheStatus(void) +{ + /* Get the status */ + return (CW_FLASH->CR2_f.CACHE ? SET : RESET); +} + +/** + * @brief 获取当前的读保护等级 + * + * @return uint8_t ：0/1/2/3 + */ +uint8_t FLASH_GetReadOutLevel(void) +{ + return (CW_FLASH->CR1_f.SECURITY); +} + +/** + * @brief 设置MCU的读保护等级,RdLevel的有效取值范围为0,1,2,3 + * //将等级写入MCU后，MCU会自动重启并完成读保护等级修改 + * //如果从非0等级变为等级0，则MCU会擦除FLASH内的所有数据 + * //Level0，ISP可读写，SWD可读写 + * //Level1，ISP可降级，SWD可降级；数据不可读出 + * //Level2，ISP可降级，SWD无功能；数据不可读出 + * //Level3，ISP无功能，SWD无功能；数据不可读出 + * @param RdLevel : FLASH_RDLEVEL0 FLASH_RDLEVEL1 + * : FLASH_RDLEVEL2 FLASH_RDLEVEL3 + */ +void FLASH_SetReadOutLevel(uint16_t RdLevel) +{ + assert_param(IS_FLASH_RDLEVEL(RdLevel)); + if (FLASH_GetReadOutLevel() != RdLevel) + { + RdLevel = 0x5A50 | (RdLevel & 0x03u); + *((volatile uint32_t *)(0x4001031C)) = RdLevel; + *((volatile uint32_t *)(0x40010370)) = 0x5A5AABCD; //MCU重启以更新读保护等级 + while (1); //MCU重启以更新保护等级 + } +} + +/** + * @brief 解锁所有页面 + * + */ +void FLASH_UnlockAllPages(void) +{ + CW_FLASH->PAGELOCK = 0x5A5Affff; //解锁所有页面 +} + +/** + * @brief 锁定所有页面 + * + */ +void FLASH_LockAllPages(void) +{ + CW_FLASH->PAGELOCK = 0x5A5A0000; +} + +/** + * @brief 解锁指定页面 + * + * @param Page_Number : 0 - 127 + * @return uint8_t : 正常返回0x00 + */ +uint8_t FLASH_UnlockPage(uint8_t Page_Number) +{ + uint16_t Currentlockstatus; + assert_param(IS_FLASH_PAGE_Number(Page_Number)); + Currentlockstatus = CW_FLASH->PAGELOCK; //读取当前锁定位 + CW_FLASH->PAGELOCK = 0x5A5A0000 | Currentlockstatus | (1UL << (Page_Number / 8)); //解锁指定页面 + return (0x00); +} + +/** + * @brief 解锁指定地址范围内所有页面,返回0x00代表成功，非0代表失败 + * + * @param StartAddr : 0x00000000 - 0x0000FFFF + * @param EndAddr : 0x00000000 - 0x0000FFFF + * @return uint8_t ：错误返回0x80，正确返回0x00 + */ +uint8_t FLASH_UnlockPages(uint32_t StartAddr, uint32_t EndAddr) +{ + uint16_t Currentlockstatus; + uint16_t UnlockMask; + uint32_t i; + UnlockMask = 0x00; + if (EndAddr > 0xFFFF) + { + return (FLASH_ERROR_ADDR); //待解锁页面地址出错 + } + if (StartAddr > EndAddr) + { + return (FLASH_ERROR_ADDR); //待解锁页面地址出错 + } + for (i = (StartAddr >> 12); i <= (EndAddr >> 12); i++) + { + UnlockMask |= (1UL << i); + } + Currentlockstatus = CW_FLASH->PAGELOCK; //读取当前锁定位 + CW_FLASH->PAGELOCK = 0x5A5A0000 | Currentlockstatus | UnlockMask; //解锁页面所在的区块 + return (0x00); +} + +/** + * @brief 擦除指定页 + * + * @param Page_Number : 0 - 127 + * @return uint8_t ：错误返回0x80，正确返回0x00 + */ +uint8_t FLASH_ErasePage(uint8_t Page_Number) +{ + uint16_t CR1BAK, CR2BAK; + if ((Page_Number > 127)) + { + return (FLASH_ERROR_ADDR); + } + while (CW_FLASH->CR1 & bv5); //等待上1次操作完成，未作超时处理 + CW_FLASH->ICR = 0x00; //clear all int flag + CR2BAK = CW_FLASH->CR2; + CR1BAK = CW_FLASH->CR1; + CW_FLASH->CR2 = 0x5A5A0000 | (CR2BAK & 0xffe7); //关掉FETCH和BUFFER功能 + CW_FLASH->CR1 = 0x5A5A0000 | (CR1BAK | 0x02u); // 设置为页擦模式 + *((volatile uint8_t *)(Page_Number * 512)) = 0x00; //erase page + while (CW_FLASH->CR1 & bv5); //等待操作完成 + CW_FLASH->CR1 = 0x5A5A0000 | CR1BAK; + CW_FLASH->CR2 = 0x5A5A0000 | CR2BAK; + return (CW_FLASH->ISR); +} + +/** + * @brief 擦除从STARTADDR到ENDADDR所在的页面,返回0x00代表成功，非0代表失败 + * + * @param StartAddr : 0x00000000 - 0x0000FFFF + * @param EndAddr : 0x00000000 - 0x0000FFFF + * @return uint8_t ：错误返回0x80，正确返回0x00 + */ +uint8_t FLASH_ErasePages(uint32_t StartAddr, uint32_t EndAddr) +{ + uint16_t CR1BAK, CR2BAK; + uint32_t i; + if ((StartAddr > 65535) || (EndAddr > 65535)) + { + return (FLASH_ERROR_ADDR); + } + while (CW_FLASH->CR1 & bv5); //等待上1次操作完成，未作超时处理 + CW_FLASH->ICR = 0x00; //clear all int flag + CR2BAK = CW_FLASH->CR2; + CR1BAK = CW_FLASH->CR1; + CW_FLASH->CR2 = 0x5A5A0000 | (CR2BAK & 0xffe7); //关掉FETCH和BUFFER功能 + CW_FLASH->CR1 = 0x5A5A0000 | (CR1BAK | 0x02u); // 设置为页擦模式 + for (i = (StartAddr >> 9); i <= (EndAddr >> 9); i++) + { + *((volatile uint8_t *)(StartAddr)) = 0x00; //erase page + while (CW_FLASH->CR1 & bv5); //等待操作完成 + StartAddr += 512; + } + CW_FLASH->CR1 = 0x5A5A0000 | CR1BAK; + CW_FLASH->CR2 = 0x5A5A0000 | CR2BAK; + return (CW_FLASH->ISR); +} + + +/** + * @brief 以WriteAddr作为起始地址，依次写入pWrBuf内的WrByteCnt个字节（8bit）的数据 + * //待写入起始地址和结束地址需要位于同一个页面以内 + * //待写入地址的页面已做擦除，并解除保护 + * //返回0x00代表成功，非0代表失败 + * @param WriteAddr : 0x00000000 - 0x0000FFFF + * @param pWrBuf + * @param WrByteCnt ：1 - 512 + * @return uint8_t ：错误返回0x80，正确返回0x00 + */ +uint8_t FLASH_WriteBytes(uint32_t WriteAddr, uint8_t *pWrBuf, uint16_t WrByteCnt) +{ + uint16_t CR1BAK, CR2BAK; + if (WriteAddr + WrByteCnt > 65536) + { + return (FLASH_ERROR_ADDR); + } + while (CW_FLASH->CR1 & bv5); //等待上1次操作完成，未作超时处理 + CW_FLASH->ICR = 0x00; //clear all int flag + CR2BAK = CW_FLASH->CR2; + CR1BAK = CW_FLASH->CR1; + CW_FLASH->CR2 = 0x5A5A0000 | (CR2BAK & 0xffe7u); //关掉FETCH和BUFFER功能 + CW_FLASH->CR1 = 0x5A5A0000 | (CR1BAK | 0x01u); // 设置为页写模式 + while (WrByteCnt) + { + *((volatile uint8_t *)(WriteAddr)) = *pWrBuf; //write byte + while (CW_FLASH->CR1 & bv5); //等待操作完成 + WriteAddr++; + WrByteCnt--; + pWrBuf++; + } + CW_FLASH->CR1 = 0x5A5A0000 | CR1BAK; + CW_FLASH->CR2 = 0x5A5A0000 | CR2BAK; + return (CW_FLASH->ISR); +} + +/** + * @brief 以WriteAddr作为起始地址，依次写入pWrBuf内的WrByteCnt个半字（16bit）的数据 + * + * @param WriteAddr + * @param pWrBuf + * @param WrByteCnt + * @return uint8_t + */ +uint8_t FLASH_WriteHalfWords(uint32_t WriteAddr, uint16_t *pWrBuf, uint16_t WrByteCnt) +{ + uint16_t CR1BAK, CR2BAK; + if (WriteAddr + WrByteCnt > 65536) + { + return (FLASH_ERROR_ADDR); + } + if ((WriteAddr & 0x00000001) != 0) // 地址未对齐 + { + return (FLASH_ERROR_ADDR); + } + while (CW_FLASH->CR1 & bv5); //等待上1次操作完成，未作超时处理 + CW_FLASH->ICR = 0x00; //clear all int flag + CR2BAK = CW_FLASH->CR2; + CR1BAK = CW_FLASH->CR1; + CW_FLASH->CR2 = 0x5A5A0000 | (CR2BAK & 0xffe7u); //关掉FETCH和BUFFER功能 + CW_FLASH->CR1 = 0x5A5A0000 | (CR1BAK | 0x01u); // 设置为页写模式 + while (WrByteCnt) + { + *((volatile uint16_t *)(WriteAddr)) = *pWrBuf; //write byte + while (CW_FLASH->CR1 & bv5); //等待操作完成 + WriteAddr += 2; + WrByteCnt--; + pWrBuf++; + } + CW_FLASH->CR1 = 0x5A5A0000 | CR1BAK; + CW_FLASH->CR2 = 0x5A5A0000 | CR2BAK; + return (CW_FLASH->ISR); +} + +uint8_t FLASH_WriteWords(uint32_t WriteAddr, uint32_t *pWrBuf, uint16_t WrByteCnt) +{ + uint16_t CR1BAK, CR2BAK; + if (WriteAddr + WrByteCnt > 65536) + { + return (FLASH_ERROR_ADDR); + } + if ((WriteAddr & 0x00000003) != 0) // 地址未对齐 + { + return (FLASH_ERROR_ADDR); + } + while (CW_FLASH->CR1 & bv5); //等待上1次操作完成，未作超时处理 + CW_FLASH->ICR = 0x00; //clear all int flag + CR2BAK = CW_FLASH->CR2; + CR1BAK = CW_FLASH->CR1; + CW_FLASH->CR2 = 0x5A5A0000 | (CR2BAK & 0xffe7u); //关掉FETCH和BUFFER功能 + CW_FLASH->CR1 = 0x5A5A0000 | (CR1BAK | 0x01u); // 设置为页写模式 + while (WrByteCnt) + { + *((volatile uint32_t *)(WriteAddr)) = *pWrBuf; //write byte + while (CW_FLASH->CR1 & bv5); //等待操作完成 + WriteAddr += 4; + WrByteCnt--; + pWrBuf++; + } + CW_FLASH->CR1 = 0x5A5A0000 | CR1BAK; + CW_FLASH->CR2 = 0x5A5A0000 | CR2BAK; + return (CW_FLASH->ISR); +} + +/** + * @brief 锁定指定页面,返回0x00代表成功，非0代表失败 + * + * @param Page_Number : 0 - 127 + * @return uint8_t : 正常返回0x00 + */ +uint8_t FLASH_LockPage(uint8_t Page_Number) +{ + uint16_t Currentlockstatus; + assert_param(IS_FLASH_PAGE_Number(Page_Number)); + Currentlockstatus = CW_FLASH->PAGELOCK; //读取当前锁定位 + CW_FLASH->PAGELOCK = ((0x5A5A0000 | Currentlockstatus) & (~(1UL << (Page_Number / 8)))); //锁定指定页面 + return (0x00); +} + +/** + * @brief 锁定指定地址范围内所有页面,返回0x00代表成功，非0代表失败 + * + * @param StartAddr : 0x00000000 - 0x0000FFFF + * @param EndAddr : 0x00000000 - 0x0000FFFF + * @return uint8_t : 错误返回0x80，正常返回0x00 + */ +uint8_t FLASH_LockPages(uint32_t StartAddr, uint32_t EndAddr) +{ + uint16_t UnlockMask; + uint16_t Currentlockstatus; + uint32_t i; + UnlockMask = 0x00; + + if (EndAddr > 0xFFFF) + { + return (FLASH_ERROR_ADDR); //待解锁页面地址出错 + } + if (StartAddr > EndAddr) + { + return (FLASH_ERROR_ADDR); //待解锁页面地址出错 + } + for (i = (StartAddr >> 12); i <= (EndAddr >> 12); i++) + { + UnlockMask |= (1UL << i); + } + if (UnlockMask == 0x00) + { + return (FLASH_ERROR_ADDR); //待锁定页面地址出错 + } + Currentlockstatus = CW_FLASH->PAGELOCK; //读取当前锁定位 + CW_FLASH->PAGELOCK = ((0x5A5A0000 | Currentlockstatus) & (~UnlockMask)); //锁定页面所在的区块 + return (0x00); +} + + +/** + * @brief FLASH中断配置 + * + * @param FLASH_IT : FLASH_IT_PROG + * FLASH_IT_PAGELOCK + * FLASH_IT_PC + * @param NewState : ENABLE DISABLE + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + CW_FLASH->IER |= FLASH_IT; + } + else + { + CW_FLASH->IER &= (~FLASH_IT); + } +} + +/** + * @brief 获取FLASH指定中断状态 + * + * @param FLASH_IT : FLASH_IT_PROG + * FLASH_IT_PAGELOCK + * FLASH_IT_PC + * @return ITStatus : SET RESET + */ +ITStatus FLASH_GetITStatus(uint32_t FLASH_IT) +{ + assert_param(IS_FLASH_GET_IT(FLASH_IT)); + return (CW_FLASH->ISR & FLASH_IT) ? SET : RESET; +} + + +/** + * @brief 清除FLASH指定中断标志 + * + * @param FLASH_IT : FLASH_IT_PROG + * FLASH_IT_PAGELOCK + * FLASH_IT_PC + */ +void FLASH_ClearITPendingBit(uint32_t FLASH_IT) +{ + assert_param(IS_FLASH_IT(FLASH_IT)); + CW_FLASH->ICR &= (~FLASH_IT); +} + +/** + * @brief 获取FLASH模块的状态 + * + * @return uint8_t 00:正常 + * FLASH_FLAG_BSY 忙 + * FLASH_FLAG_PCERR 擦写PC指针所在页错误 + * FLASH_FLAG_WRPRTERR 擦写未解锁保护页错误 + * FLASH_FLAG_PGERR 编程目标地址数据不全为0XFF错误 + */ +uint32_t FLASH_GetStatus(void) +{ + uint32_t flashstatus; + if (1 == CW_FLASH->CR1_f.BUSY) + { + return FLASH_FLAG_BSY; + } + flashstatus = CW_FLASH->ISR; + if (flashstatus & FLASH_FLAG_PCERR) + { + return FLASH_FLAG_PCERR; + } + if (flashstatus & FLASH_FLAG_WRPRTERR) + { + return FLASH_FLAG_WRPRTERR; + } + if (flashstatus & FLASH_FLAG_PGERR) + { + return FLASH_FLAG_PGERR; + } + return FLASH_FLAG_OK; +} + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_gpio.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_gpio.c new file mode 100644 index 0000000..be88245 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_gpio.c @@ -0,0 +1,278 @@ +/** + ****************************************************************************** + * @file CW030xx_gpio.c + * @author WHXY + * @version + * @date 2021-03-16 + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * +***/ + + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_gpio.h" + + + +//============================================================================= +//GPIO 初始化，多个引脚 +/** + * @brief GPIO 初始化，可同时设置多个引脚或单个引脚 + * + * @param GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOC CW_GPIOF + * @param GPIO_Init 参见GPIO_InitTypeDef的定义 + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + if (GPIO_Init->Mode == GPIO_MODE_ANALOG) //模拟功能 + { + REGBITS_SET(GPIOx->ANALOG, GPIO_Init->Pins); + } + else + { + REGBITS_CLR(GPIOx->ANALOG, GPIO_Init->Pins); //数字功能 + if ((GPIO_Init->Mode & GPIO_MODE_INPUT) == GPIO_MODE_INPUT) //输入模式 + { + REGBITS_SET(GPIOx->DIR, GPIO_Init->Pins); + if (GPIO_Init->Mode == GPIO_MODE_INPUT_PULLUP) + { + REGBITS_SET(GPIOx->PUR, GPIO_Init->Pins); + REGBITS_CLR(GPIOx->PDR, GPIO_Init->Pins); + } + if (GPIO_Init->Mode == GPIO_MODE_INPUT_PULLDOWN) + { + REGBITS_SET(GPIOx->PDR, GPIO_Init->Pins); + REGBITS_CLR(GPIOx->PUR, GPIO_Init->Pins); + } + REGBITS_CLR(GPIOx->RISEIE, GPIO_Init->Pins); + REGBITS_CLR(GPIOx->FALLIE, GPIO_Init->Pins); + REGBITS_CLR(GPIOx->HIGHIE, GPIO_Init->Pins); + REGBITS_CLR(GPIOx->LOWIE, GPIO_Init->Pins); + if ((GPIO_Init->IT & GPIO_IT_RISING) == GPIO_IT_RISING) + { + REGBITS_SET(GPIOx->RISEIE, GPIO_Init->Pins); + } + if ((GPIO_Init->IT & GPIO_IT_FALLING) == GPIO_IT_FALLING) + { + REGBITS_SET(GPIOx->FALLIE, GPIO_Init->Pins); + } + if ((GPIO_Init->IT & GPIO_IT_HIGH) == GPIO_IT_HIGH) + { + REGBITS_SET(GPIOx->HIGHIE, GPIO_Init->Pins); + } + if ((GPIO_Init->IT & GPIO_IT_LOW) == GPIO_IT_LOW) + { + REGBITS_SET(GPIOx->LOWIE, GPIO_Init->Pins); + } + } + else //输出模式 + { + REGBITS_CLR(GPIOx->DIR, GPIO_Init->Pins); + if (GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) + { + REGBITS_CLR(GPIOx->OPENDRAIN, GPIO_Init->Pins); + } + else + { + REGBITS_SET(GPIOx->OPENDRAIN, GPIO_Init->Pins); + } + if (GPIO_Init->Speed == GPIO_SPEED_HIGH) + { + REGBITS_SET(GPIOx->SPEED, GPIO_Init->Pins); + } + else + { + REGBITS_CLR(GPIOx->SPEED, GPIO_Init->Pins); + } + } + } +} + +//============================================================================= +//GPIO 反初始化， 多个引脚 +/** + * @brief GPIO 去初始化，可同时设置多个引脚或单个引脚 + * + * @param GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOC CW_GPIOF + * + * @param GPIO_Pins 参数取值如下 + * @arg GPIO_PIN_0/1/2.../15/ALL 可通过与运算同时操作多个引脚 + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pins) +{ + REGBITS_SET(GPIOx->ANALOG, GPIO_Pins); + REGBITS_SET(GPIOx->DIR, GPIO_Pins); + REGBITS_CLR(GPIOx->PUR, GPIO_Pins); + REGBITS_CLR(GPIOx->PDR, GPIO_Pins); + REGBITS_CLR(GPIOx->RISEIE, GPIO_Pins); + REGBITS_CLR(GPIOx->FALLIE, GPIO_Pins); + REGBITS_CLR(GPIOx->HIGHIE, GPIO_Pins); + REGBITS_CLR(GPIOx->LOWIE, GPIO_Pins); + REGBITS_CLR(GPIOx->OPENDRAIN, GPIO_Pins); +} +//============================================================================= +//获取指定引脚电平，一个引脚 +//注意：建议采用宏函数来获取引脚电平，例PA00_GETVALUE() +/** + * @brief 获取一个引脚的电平 + * + * @param GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOC CW_GPIOF + * @param GPIO_Pin 参数取值如下 + * @arg GPIO_PIN_0/1/2.../15 + * @return GPIO_PinState 取值如下: + * @arg GPIO_Pin_SET + * @arg GPIO_Pin_RESET + */ +GPIO_PinState GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + if (GPIOx->IDR & GPIO_Pin) + { + return (GPIO_Pin_SET); + } + return (GPIO_Pin_RESET); +} + +//============================================================================= +//设置指定引脚电平，多个引脚 +//注意：如只操作一只引脚，建议采用宏函数，例PA00_SETHIGH(), PA00_SETLOW() +/** + * @brief 设置指定引脚电平，可同时设置多个引脚 + * + * @param GPIOx GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOC CW_GPIOF + * @param GPIO_Pins 参数取值如下 + * @arg GPIO_PIN_0/1/2.../15/ALL; + * @param PinState 取值如下: + * @arg GPIO_Pin_SET + * @arg GPIO_Pin_RESET + */ +void GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pins, GPIO_PinState PinState) +{ + if (PinState == GPIO_Pin_SET) + { + GPIOx->BSRR = GPIO_Pins; + } + else + { + GPIOx->BRR = GPIO_Pins; + } +} + +/** + * @brief 设置指定引脚端口的输出值 + * + * @param GPIOx GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOC + * @param Value + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t Value) +{ + GPIOx->ODR = Value; + +} +//============================================================================= +//设置端口低字节（B0-B7）引脚电平 +/** + * @brief 设置端口低字节（B0-B7）引脚电平 + * + * @param GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOF + * @param Value 取值范围：0x00~0xFF + */ +void GPIO_LowByte_Write(GPIO_TypeDef *GPIOx, uint8_t Value) +{ + GPIOx->ODRLOWBYTE = Value; +} + +//============================================================================= +//设置端口高字节（B8-B15）引脚电平 +/** + * @brief 设置端口高字节（B8-B15）引脚电平 + * + * @param GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOC + * @param Value 取值范围：0x00~0xFF + */ +void GPIO_HighByte_Write(GPIO_TypeDef *GPIOx, uint8_t Value) +{ + GPIOx->ODRHIGHBYTE = Value; +} + +//============================================================================= +//翻转指定引脚电平，多个引脚 +//注意：如只操作一只引脚，建议采用宏函数，例PA00_TOG() +/** + * @brief 翻转指定引脚电平，可同时设置多个引脚 + * + * @param GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOC CW_GPIOF + * @param GPIO_Pins + */ +void GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pins) +{ + GPIOx->TOG = GPIO_Pins; +} + +//============================================================================= +//锁定指定引脚配置项，多个引脚 +/** + * @brief 锁定指定引脚配置项，可同时设置多个引脚 + * + * @param GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOC CW_GPIOF + * @param GPIO_Pins + */ +void GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pins) +{ + REGBITS_SET(GPIOx->LOCK, GPIO_Pins); +} + +//============================================================================= +//将PA13/PA14设置成GPIO +/** + * @brief 将PA13/PA14设置成GPIO + * + */ +void GPIO_SWD2GPIO(void) +{ + CW_SYSCTRL->CR2 = CW_SYSCTRL->CR2 | (0x5A5A0000 | bv1); +} + +//============================================================================= +//将PA13/PA14设置成SWD +/** + * @brief 将PA13/PA14设置成SWD，PA13/SWDIO PA14/SWCLK + * + */ +void GPIO_GPIO2SWD(void) +{ + CW_SYSCTRL->CR2 = 0x5A5A0000 | (CW_SYSCTRL->CR2 & (~(bv1))); +} + +//============================================================================= +//配置端口滤波 +// FltClk 只能是宏定义中定义的参数 +/** + * @brief 配置端口滤波 + * + * @param GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOC CW_GPIOF + * @param GPIO_Pins + * @param FltClk 只能是宏定义中定义的参数 GPIO_FLTCLK_xxx + */ +void GPIO_ConfigFilter(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pins, uint32_t FltClk) +{ + GPIOx->FILTER = FltClk | GPIO_Pins; +} + +//============================================================================= +//配置端口辅助功能 +//请使用CW32f030_gpio.h中的宏定义来配置每个端口的辅助功能 + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_gtim.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_gtim.c new file mode 100644 index 0000000..ea1e09f --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_gtim.c @@ -0,0 +1,406 @@ +/** + * @file cw32f030_gtim.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-04-27 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_gtim.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief + * @param GTIMx + */ +void GTIM1_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.GTIM1 = 0; + CW_SYSCTRL->APBRST1_f.GTIM1 = 1; +} + +void GTIM2_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.GTIM2 = 0; + CW_SYSCTRL->APBRST1_f.GTIM2 = 1; +} + +void GTIM3_DeInit(void) +{ + CW_SYSCTRL->APBRST2_f.GTIM3 = 0; + CW_SYSCTRL->APBRST2_f.GTIM3 = 1; +} + +void GTIM4_DeInit(void) +{ + CW_SYSCTRL->APBRST2_f.GTIM4 = 0; + CW_SYSCTRL->APBRST2_f.GTIM4 = 1; +} + +/** + * @brief GTIM的基础参数初始化 + * @param GTIMx 取值范围：CW_GTIM1,CW_GTIM2,CW_GTIM3,CW_GTIM4 + * @param GTIM_InitStruct 详见GTIM_InitTypeDef的定义 + */ +void GTIM_TimeBaseInit(GTIM_TypeDef *GTIMx, GTIM_InitTypeDef *GTIM_InitStruct) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_MODE(GTIM_InitStruct->Mode)); + assert_param(IS_GTIM_ONESHOT(GTIM_InitStruct->OneShotMode)); + assert_param(IS_GTIM_PRESCALER(GTIM_InitStruct->Prescaler)); + REGBITS_MODIFY(GTIMx->CR0, GTIMx_CR0_PRS_Msk | GTIMx_CR0_ONESHOT_Msk | \ + GTIMx_CR0_MODE_Msk | GTIMx_CR0_TOGEN_Msk, \ + GTIM_InitStruct->Prescaler | GTIM_InitStruct->OneShotMode | \ + GTIM_InitStruct->Mode | \ + (GTIM_InitStruct->ToggleOutState ? GTIMx_CR0_TOGEN_Msk : 0)); + GTIMx->ARR = GTIM_InitStruct->ReloadValue; +} + +/** + * @brief 编码模式初始化。 + * @param GTIMx 取值范围：CW_GTIM1,CW_GTIM2,CW_GTIM3,CW_GTIM4 + * @param GTIM_EncodeInitStruct + */ +void GTIM_EncodeInit(GTIM_TypeDef *GTIMx, GTIM_EncodeInitTypeDef *GTIM_EncodeInitStruct) +{ + uint32_t tmp; + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_ENCODE_MODE(GTIM_EncodeInitStruct->EncodeMode)); + assert_param(IS_GTIM_ENCODE_RESET(GTIM_EncodeInitStruct->EncodeResetMode)); + assert_param(IS_GTIM_ENCODE_RELOAD(GTIM_EncodeInitStruct->EncodeReloadMode)); + assert_param(IS_GTIM_CHx_FILTER(GTIM_EncodeInitStruct->CH1Filter)); + assert_param(IS_GTIM_CHx_FILTER(GTIM_EncodeInitStruct->CH2Filter)); + assert_param(IS_GTIM_CHx_FILTER(GTIM_EncodeInitStruct->CH3Filter)); + assert_param(IS_GTIM_CHx_INVERT(GTIM_EncodeInitStruct->CH1Invert)); + assert_param(IS_GTIM_CHx_INVERT(GTIM_EncodeInitStruct->CH2Invert)); + assert_param(IS_GTIM_CHx_INVERT(GTIM_EncodeInitStruct->CH3Invert)); + REGBITS_MODIFY(GTIMx->CR0, + GTIMx_CR0_ENCRELOAD_Msk | GTIMx_CR0_ENCRESET_Msk | GTIMx_CR0_ENCMODE_Msk, + GTIM_EncodeInitStruct->EncodeMode | GTIM_EncodeInitStruct->EncodeResetMode | + GTIM_EncodeInitStruct->EncodeReloadMode); + tmp = GTIM_EncodeInitStruct->CH1Filter | GTIM_EncodeInitStruct->CH1Invert | + (GTIM_EncodeInitStruct->CH2Filter << 4) | (GTIM_EncodeInitStruct->CH2Invert << 7) | + (GTIM_EncodeInitStruct->CH3Filter << 8) | (GTIM_EncodeInitStruct->CH3Invert << 11); + REGBITS_MODIFY(GTIMx->CR1, ~(GTIMx_CR1_CH4FLT_Msk | GTIMx_CR1_CH4POL_Msk), tmp); +} + +/** + * @brief 比较输出功能初始化 + * @param GTIMx 取值范围：CW_GTIM1,CW_GTIM2,CW_GTIM3,CW_GTIM4 + * @param CHx 输出通道：CH1~CH4 + * @param OCMode + */ +void GTIM_OCInit(GTIM_TypeDef *GTIMx, uint32_t CHx, uint32_t OCMode) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_CHANNEL(CHx)); + assert_param(IS_GTIM_OC_OUTPUT(OCMode)); + REGBITS_MODIFY(GTIMx->CMMR, (GTIMx_CMMR_CC1M_Msk << CHx), (OCMode << CHx)); +} + +void GTIM_ICInit(GTIM_TypeDef *GTIMx, GTIM_ICInitTypeDef *GTIM_ICInitStruct) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_CHANNEL(GTIM_ICInitStruct->CHx)); + assert_param(IS_GTIM_ICPolarity(GTIM_ICInitStruct->ICPolarity)); + assert_param(IS_GTIM_CHx_FILTER(GTIM_ICInitStruct->ICFilter)); + assert_param(IS_GTIM_CHx_INVERT(GTIM_ICInitStruct->ICInvert)); + REGBITS_MODIFY(GTIMx->CMMR, (GTIMx_CMMR_CC1M_Msk << GTIM_ICInitStruct->CHx), + (GTIM_ICInitStruct->ICPolarity << GTIM_ICInitStruct->CHx)); + REGBITS_MODIFY(GTIMx->CR1, (0xFUL << GTIM_ICInitStruct->CHx), + (GTIM_ICInitStruct->ICFilter | (GTIM_ICInitStruct->ICInvert << 3)) << GTIM_ICInitStruct->CHx); +} + +/** + * @brief GTIM使能 + * @param GTIMx + */ +void GTIM_Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + GTIMx->CR0_f.EN = NewState; +} + +/** + * @brief 配置ETR信号的极性和滤波器 + * @param GTIMx + * @param ETRPolarity 极性 + * @param ETRFilter 滤波参数 + */ +void GTIM_ETRConfig(GTIM_TypeDef *GTIMx, uint32_t ETRPolarity, uint32_t ETRFilter) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_ETR_POL(ETRPolarity)); + assert_param(IS_GTIM_ETR_FILTER(ETRFilter)); + REGBITS_MODIFY(GTIMx->CR0, GTIMx_CR0_TRS_Msk | GTIMx_CR0_POL_Msk, ETRPolarity); + REGBITS_MODIFY(GTIMx->ETR, GTIMx_ETR_ETRFLT_Msk, ETRFilter); +} + +/** + * @brief + * + * @param ITRSouce ITR_SOURCE_BTIM1 ITR_SOURCE_BTIM2 ITR_SOURCE_BTIM3 + * ITR_SOURCE_GTIM2 ITR_SOURCE_GTIM3 ITR_SOURCE_GTIM4 + * ITR_SOURCE_ATIM + */ +void GTIM1_ITRConfig(uint32_t ITRSouce) +{ + assert_param(IS_ITR_SOURCE(ITRSouce)); + assert_param(ITRSouce != ITR_SOURCE_GTIM1); + REGBITS_SET(CW_GTIM1->CR0, GTIMx_CR0_TRS_Msk); + CW_SYSCTRL->TIMITR_f.GTIM1ITR = ITRSouce; +} + +/** + * @brief + * + * @param ITRSouce ITR_SOURCE_BTIM1 ITR_SOURCE_BTIM2 ITR_SOURCE_BTIM3 + * ITR_SOURCE_GTIM1 ITR_SOURCE_GTIM3 ITR_SOURCE_GTIM4 + * ITR_SOURCE_ATIM + */ +void GTIM2_ITRConfig(uint32_t ITRSouce) +{ + assert_param(IS_ITR_SOURCE(ITRSouce)); + assert_param(ITRSouce != ITR_SOURCE_GTIM2); + REGBITS_SET(CW_GTIM2->CR0, GTIMx_CR0_TRS_Msk); + CW_SYSCTRL->TIMITR_f.GTIM2ITR = ITRSouce; +} + +/** + * @brief + * + * @param ITRSouce ITR_SOURCE_BTIM1 ITR_SOURCE_BTIM2 ITR_SOURCE_BTIM3 + * ITR_SOURCE_GTIM1 ITR_SOURCE_GTIM2 ITR_SOURCE_GTIM4 + * ITR_SOURCE_ATIM + */ +void GTIM3_ITRConfig(uint32_t ITRSouce) +{ + assert_param(IS_ITR_SOURCE(ITRSouce)); + assert_param(ITRSouce != ITR_SOURCE_GTIM3); + REGBITS_SET(CW_GTIM3->CR0, GTIMx_CR0_TRS_Msk); + CW_SYSCTRL->TIMITR_f.GTIM3ITR = ITRSouce; +} + +/** + * @brief + * + * @param ITRSouce ITR_SOURCE_BTIM1 ITR_SOURCE_BTIM2 ITR_SOURCE_BTIM3 + * ITR_SOURCE_GTIM1 ITR_SOURCE_GTIM2 ITR_SOURCE_GTIM3 + * ITR_SOURCE_ATIM + */ +void GTIM4_ITRConfig(uint32_t ITRSouce) +{ + assert_param(IS_ITR_SOURCE(ITRSouce)); + assert_param(ITRSouce != ITR_SOURCE_GTIM4); + REGBITS_SET(CW_GTIM1->CR0, GTIMx_CR0_TRS_Msk); + CW_SYSCTRL->TIMITR_f.GTIM4ITR = ITRSouce; +} + +/** + * @brief 配置输入通道的参数 + * @param GTIMx + * @param CHx + * @param CHxFilter + * @param CHxInvert + */ +void GTIM_ICChannelConfig(GTIM_TypeDef *GTIMx, uint32_t CHx, uint32_t CHxFilter, uint32_t CHxInvert) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_CHANNEL(CHx)); + assert_param(IS_GTIM_CHx_FILTER(CHxFilter)); + assert_param(IS_GTIM_CHx_INVERT(CHxInvert)); + REGBITS_MODIFY(GTIMx->CR1, (0xFUL << CHx), (CHxFilter | (CHxInvert << 3)) << CHx); +} + +/** + * @brief 设置预分频系数 + * @param GTIMx + * @param GTIMPrescaler + */ +void GTIM_SetPrescaler(GTIM_TypeDef *GTIMx, uint32_t GTIMPrescaler) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_PRESCALER(GTIMPrescaler)); + REGBITS_MODIFY(GTIMx->CR0, GTIMx_CR0_PRS_Msk, GTIMPrescaler); +} + +/** + * @brief 设置重载值 + * @param GTIMx + * @param ReloadValue 取值范围：0x0000~0xFFFF + */ +void GTIM_SetReloadValue(GTIM_TypeDef *GTIMx, uint32_t ReloadValue) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + GTIMx->ARR = ReloadValue; +} + +/** + * @brief + * @param GTIMx + * @param Value + */ +void GTIM_SetCounterValue(GTIM_TypeDef *GTIMx, uint32_t Value) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + GTIMx->CNT = Value; +} + +void GTIM_SetCompare1(GTIM_TypeDef *GTIMx, uint32_t Value) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + GTIMx->CCR1 = 0x0000FFFF & Value; +} + +void GTIM_SetCompare2(GTIM_TypeDef *GTIMx, uint32_t Value) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + GTIMx->CCR2 = 0x0000FFFF & Value; +} + +void GTIM_SetCompare3(GTIM_TypeDef *GTIMx, uint32_t Value) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + GTIMx->CCR3 = 0x0000FFFF & Value; +} + +void GTIM_SetCompare4(GTIM_TypeDef *GTIMx, uint32_t Value) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + GTIMx->CCR4 = 0x0000FFFF & Value; +} + +/** + * @brief + * @param GTIMx + * @return uint32_t + */ +uint32_t GTIM_GetCapture1(GTIM_TypeDef *GTIMx) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + return GTIMx->CCR1; +} + +/** + * @brief + * @param GTIMx + * @return uint32_t + */ +uint32_t GTIM_GetCapture2(GTIM_TypeDef *GTIMx) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + return GTIMx->CCR2; +} + +/** + * @brief + * @param GTIMx + * @return uint32_t + */ +uint32_t GTIM_GetCapture3(GTIM_TypeDef *GTIMx) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + return GTIMx->CCR3; +} + +/** + * @brief + * @param GTIMx + * @return uint32_t + */ +uint32_t GTIM_GetCapture4(GTIM_TypeDef *GTIMx) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + return GTIMx->CCR4; +} + +/** + * @brief + * @param GTIMx + * @param GTIM_IT + * @param NewState + */ +void GTIM_ITConfig(GTIM_TypeDef *GTIMx, uint32_t GTIM_IT, FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_IT(GTIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + GTIMx->IER |= GTIM_IT; + } + else + { + GTIMx->IER &= ~GTIM_IT; + } +} + +/** + * @brief + * @param GTIMx + * @param GTIM_IT + * @return ITStatus + */ +ITStatus GTIM_GetITStatus(GTIM_TypeDef *GTIMx, uint32_t GTIM_IT) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_GET_IT(GTIM_IT)); + return (GTIMx->ISR & GTIM_IT) ? SET : RESET; +} + +/** + * @brief + * @param GTIMx + * @param GTIM_IT + */ +void GTIM_ClearITPendingBit(GTIM_TypeDef *GTIMx, uint32_t GTIM_IT) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_IT(GTIM_IT)); + GTIMx->ICR = ~GTIM_IT; +} + +/** + * @brief + * @param GTIMx + * @param GTIM_DMA + */ +void GTIM_DMAConfig(GTIM_TypeDef *GTIMx, uint32_t GTIM_DMA, FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_DMA(GTIM_DMA)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + NewState ? (GTIMx->DMA |= GTIM_DMA) : (GTIMx->DMA &= ~GTIM_DMA); +} diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_i2c.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_i2c.c new file mode 100644 index 0000000..6ba78dd --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_i2c.c @@ -0,0 +1,789 @@ +/** + * @file cw32f030_i2c.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-04-27 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_i2c.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief I2C 波特率发生器使能 + * + * @param I2Cx : I2C1 I2C2 + * @param NewState : ENABLE DISABLE + */ +void I2C_BaudGeneratorEnable(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->BRREN_f.EN = 1; + } + else + { + /* Peripheral not under reset */ + I2Cx->BRREN_f.EN = 0; + } +} + +/** + * @brief I2C：设置波特率计数器配置寄存器函数 + * + * @param I2Cx : I2C1 I2C2 + * @param u8TBaud : 设置值= fPCLK/(8*fSCL) - 1 + * : 设置值需要根据fPCLK和fSCL计算 + */ +void I2C_SetBaud(I2C_TypeDef *I2Cx, uint8_t u8TBaud) +{ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_Baud_BRR(u8TBaud)); + I2Cx->BRR = u8TBaud; +} + +/** + * @brief 发送START信号 + * + * @param I2Cx : I2C1 I2C2 + * @param NewState : ENABLE DISABLE + */ +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a START condition */ + if (I2Cx->STAT != 0xF8) + { + I2Cx->CR_f.STA = 1; //set start + I2Cx->CR_f.SI = 0; //clear si + } + else + { + I2Cx->CR_f.STA = 1; //set start + } + while ((I2Cx->CR & bv3) == 0x00); //已产生0X08状态 + I2Cx->CR_f.STA = 0; //clear start + } + else + { + /* Disable the START condition generation */ + I2Cx->CR_f.STA = 0; + } +} + +/** + * @brief 发送STOP信号 + * + * @param I2Cx : I2C1 I2C2 + * @param NewState : ENABLE DISABLE + */ +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR_f.STO = 1; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR_f.STO = 0; + } +} + +/** + * @brief ACK应答配置 + * + * @param I2Cx : I2C1 I2C2 + * @param NewState : ENABLE DISABLE + */ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR_f.AA = 1; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR_f.AA = 0; + } +} + +/** + * @brief 滤波器配置 + * + * @param I2Cx : I2C1 I2C2 + * @param NewState : ENABLE DISABLE + * 作为主机时，如果BRR的值小于或等于9，则I2Cx_CR.FLT设置为ENABLE； + * 如果BRR的值大于9，则 I2Cx_CR.FLT为DISABLE； + * + * 作从机时，如果PCLK与SCL的频率比值小于或等于40，则I2Cx_CR.FLT设置为ENABLE； + * 如果PCLK与SCL的频率比值大于40，则I2Cx_CR.FLT设置为DISABLE； + */ +void I2C_FilterConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CR_f.FLT = 1; + } + else + { + /* Peripheral not under reset */ + I2Cx->CR_f.FLT = 0; + } +} + +/** + * @brief 做从机时的I2C地址0配置 + * + * @param I2Cx : I2C1 I2C2 + * @param I2CSlaveAddr ：不能全0，可设置范围为0x01 - 0x7F + */ +void I2C_SetOwnSlaveAddress0(I2C_TypeDef *I2Cx, uint8_t I2CSlaveAddr) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Get the old register value */ + I2Cx->ADDR0_f.ADDR0 = (I2CSlaveAddr >> 1); +} + +/** + * @brief 做从机时的I2C地址1配置 + * + * @param I2Cx : I2C1 I2C2 + * @param I2CSlaveAddr ：不能全0，可设置范围为0x01 - 0x7F + */ +void I2C_SetOwnSlaveAddress1(I2C_TypeDef *I2Cx, uint8_t I2CSlaveAddr) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Get the old register value */ + I2Cx->ADDR1_f.ADDR1 = (I2CSlaveAddr >> 1); +} + +/** + * @brief 做从机时的I2C地址2配置 + * + * @param I2Cx : I2C1 I2C2 + * @param I2CSlaveAddr ：不能全0，可设置范围为0x01 - 0x7F + */ +void I2C_SetOwnSlaveAddress2(I2C_TypeDef *I2Cx, uint8_t I2CSlaveAddr) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Get the old register value */ + I2Cx->ADDR2_f.ADDR2 = (I2CSlaveAddr >> 1); +} + +/** + * @brief 广播地址响应位配置 + * + * @param I2Cx : I2C1 I2C2 + * @param NewState : ENABLE DISABLE + */ +void I2C_GcConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* 允许响应广播 */ + I2Cx->ADDR0_f.GC = 1; + } + else + { + /* 禁止响应广播 */ + I2Cx->ADDR0_f.GC = 0; + } +} + +/** + * @brief I2C模块使能控制 + * + * @param I2Cx : I2C1 I2C2 + * @param NewState : ENABLE DISABLE + */ +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR_f.EN = 1; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR_f.EN = 0; + } +} + +/** + * @brief I2C：获取中断标志位函数 + * + * @param I2Cx : I2C1 I2C2 + * @return ITStatus : 为0表示无中断标志(SI = 0)，为1则为有中断标志(SI = 1) + */ +ITStatus I2C_GetIrq(I2C_TypeDef *I2Cx) +{ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + return (I2Cx->CR & bv3) ? SET : RESET; +} + +/** + * @brief I2C：清除中断标志位函数 + * + * @param I2Cx : I2C1 I2C2 + */ +void I2C_ClearIrq(I2C_TypeDef *I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + I2Cx->CR_f.SI = 0; +} + +/** + * @brief I2C：读取状态寄存器函数 + * + * @param I2Cx : I2C1 I2C2 + * @return uint8_t : 26种返回值，含义在不同模式下不同 + * + */ +uint8_t I2C_GetState(I2C_TypeDef *I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + return ((uint8_t)(I2Cx->STAT)); +} + +/** + * @brief I2C:MASTER初始化函数 + * + * @param I2Cx : I2C1 I2C2 + * @param I2C_InitStruct + */ +void I2C_Master_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_SetBaud(I2Cx, I2C_InitStruct->I2C_Baud); + I2C_BaudGeneratorEnable(I2Cx, I2C_InitStruct->I2C_BaudEn); + I2C_FilterConfig(I2Cx, I2C_InitStruct->I2C_FLT); + I2C_AcknowledgeConfig(I2Cx, I2C_InitStruct->I2C_AA); + if (I2C_InitStruct->I2C_Baud <= 9) + { + I2C_FilterConfig(I2Cx, ENABLE); + } +} + +/** + * @brief I2C:SLAVE初始化函数 + * + * @param I2Cx : I2C1 I2C2 + * @param I2C_InitStruct + */ +void I2C_Slave_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_FilterConfig(I2Cx, ENABLE); + I2C_AcknowledgeConfig(I2Cx, I2C_InitStruct->I2C_AA); + I2C_SetOwnSlaveAddress0(I2Cx, I2C_InitStruct->I2C_OwnSlaveAddr0); + I2C_GcConfig(I2Cx, I2C_InitStruct->I2C_OwnGc); + I2C_SetOwnSlaveAddress1(I2Cx, I2C_InitStruct->I2C_OwnSlaveAddr1); + I2C_SetOwnSlaveAddress2(I2Cx, I2C_InitStruct->I2C_OwnSlaveAddr2); +} + +/** + * @brief I2C1 关闭初始化 + * + */ +void I2C1_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.I2C1 = 0; + CW_SYSCTRL->APBRST1_f.I2C1 = 1; + CW_I2C1->CR = 0x00; +} + +/** + * @brief I2C2 关闭初始化 + * + */ +void I2C2_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.I2C2 = 0; + CW_SYSCTRL->APBRST1_f.I2C2 = 1; + CW_I2C2->CR = 0x00; +} + +/** + * @brief 发送1字节数据 + * + * @param I2Cx : I2C1 I2C2 + * @param Data : 0x00 - 0xFF + */ +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Write in the DR register the data to be sent */ + I2Cx->DR = Data; +} + +/** + * @brief 接收1字节数据 + * + * @param I2Cx : I2C1 I2C2 + * @return uint8_t : 0x00 - 0xFF + */ +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the data in the DR register */ + return (uint8_t)I2Cx->DR; +} + +/** + * @brief 做主时发送从机地址字节 + * + * @param I2Cx : I2C1 I2C2 + * @param Address : 按照8BIT设置，最低bit为0或者1均可以 + * @param I2C_Direction : I2C_Direction_Transmitter I2C_Direction_Receiver + */ +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_Direction_Transmitter) + { + /* Set the address bit0 for read */ + Address |= 0x01; + } + else + { + /* Reset the address bit0 for write */ + Address &= 0xfe; + } + /* Send the address */ + I2Cx->DR = Address; +} + +/** + * @brief 软复位I2C1 + * + * @param NewState : ENABLE DISABLE + */ +void I2C1_SoftwareResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + CW_SYSCTRL->APBRST1_f.I2C1 = 1; + } + else + { + /* Peripheral not under reset */ + CW_SYSCTRL->APBRST1_f.I2C1 = 0; + } +} + +/** + * @brief 软复位I2C2 + * + * @param NewState : ENABLE DISABLE + */ +void I2C2_SoftwareResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + CW_SYSCTRL->APBRST1_f.I2C2 = 1; + } + else + { + /* Peripheral not under reset */ + CW_SYSCTRL->APBRST1_f.I2C2 = 0; + } +} + +/** + ****************************************************************************** + * @brief 主机接收函数，适用读取EEPROM方式采用随机读取方式：需要先写入EEPROM的地址 + * + * @param I2Cx : I2C1 I2C2 + * @param u8Addr : 读取EEPROM内存器地址 + * @param pu8Data : 读取到的EEPROM的数据地址 + * @param u32Len : 读取到的EEPROM的数据长度 + * + ******************************************************************************/ +void I2C_MasterReadEepomData(I2C_TypeDef *I2Cx, uint8_t u8Addr, uint8_t *pu8Data, uint32_t u32Len) +{ + uint8_t u8i = 0, u8State; + I2C_GenerateSTART(I2Cx, ENABLE); + while (1) + { + while (0 == I2C_GetIrq(I2Cx)) + {} + u8State = I2C_GetState(I2Cx); + switch (u8State) + { + case 0x08: //发送完START信号 + I2C_GenerateSTART(I2Cx, DISABLE); + I2C_Send7bitAddress(I2Cx, I2C_SLAVEADDRESS, 0X00); //发送从机地址 + break; + case 0x18: //发送完SLA+W/R字节 + I2C_SendData(I2Cx, u8Addr); + break; + case 0x28: //发送完1字节数据：发送EEPROM中memory地址也会产生，发送后面的数据也会产生 + I2Cx->CR_f.STA = 1; //set start //发送重复START信号,START生成函数改写后，会导致0X10状态被略过，故此处不调用函数 + break; + case 0x10: //发送完重复起始信号 + I2C_GenerateSTART(I2Cx, DISABLE); + I2C_Send7bitAddress(I2Cx, I2C_SLAVEADDRESS, 0X01); + break; + case 0x40: //发送完SLA+R信号，开始接收数据 + if (u32Len > 1) + { + I2C_AcknowledgeConfig(I2Cx, ENABLE); + } + break; + case 0x50: //接收完一字节数据，在接收最后1字节数据之前设置AA=0; + pu8Data[u8i++] = I2C_ReceiveData(I2Cx); + if (u8i == u32Len - 1) + { + I2C_AcknowledgeConfig(I2Cx, DISABLE); + } + break; + case 0x58: //接收到一个数据字节，且NACK已回复 + pu8Data[u8i++] = I2C_ReceiveData(I2Cx); + I2C_GenerateSTOP(I2Cx, ENABLE); + break; + case 0x38: //主机在发送 SLA+W 阶段或者发送数据阶段丢失仲裁 或者 主机在发送 SLA+R 阶段或者回应 NACK 阶段丢失仲裁 + I2C_GenerateSTART(I2Cx, ENABLE); + break; + case 0x48: //发送完SLA+R后从机返回NACK + I2C_GenerateSTOP(I2Cx, ENABLE); + break; + default: + I2C_GenerateSTART(I2Cx, ENABLE);//其他错误状态，重新发送起始条件 + break; + } + I2C_ClearIrq(I2Cx); + if (u8i == u32Len) + { + break; + } + } +} + +/** + ****************************************************************************** + * @brief 主机发送函数，适用读取EEPROM方式采用随机读取方式：需要先写入EEPROM的地址 + * + * @param I2Cx : I2C1 I2C2 + * @param u8Addr : 写入EEPROM内存器地址 + * @param pu8Data : 写入数据存放地址 + * @param u32Len : 写入数据长度 + * + ******************************************************************************/ + +void I2C_MasterWriteEepromData(I2C_TypeDef *I2Cx, uint8_t u8Addr, uint8_t *pu8Data, uint32_t u32Len) +{ + uint8_t u8i = 0, u8State; + I2C_GenerateSTART(I2Cx, ENABLE); + while (1) + { + while (0 == I2C_GetIrq(I2Cx)) + {;} + u8State = I2C_GetState(I2Cx); + switch (u8State) + { + case 0x08: //发送完START信号 + I2C_GenerateSTART(I2Cx, DISABLE); + I2C_Send7bitAddress(I2Cx, I2C_SLAVEADDRESS, 0X00); //从设备地址发送 + break; + case 0x18: //发送完SLA+W信号,ACK已收到 + I2C_SendData(I2Cx, u8Addr); //从设备内存地址发送 + break; + case 0x28: //发送完1字节数据：发送EEPROM中memory地址也会产生，发送后面的数据也会产生 + I2C_SendData(I2Cx, pu8Data[u8i++]); + break; + case 0x20: //发送完SLA+W后从机返回NACK + case 0x38: //主机在发送 SLA+W 阶段或者发送数据阶段丢失仲裁 或者 主机在发送 SLA+R 阶段或者回应 NACK 阶段丢失仲裁 + I2C_GenerateSTART(I2Cx, ENABLE); + break; + case 0x30: //发送完一个数据字节后从机返回NACK + I2C_GenerateSTOP(I2Cx, ENABLE); + break; + default: + break; + } + if (u8i > u32Len) + { + I2C_GenerateSTOP(I2Cx, ENABLE);//此顺序不能调换，出停止条件 + I2C_ClearIrq(I2Cx); + break; + } + I2C_ClearIrq(I2Cx); + } +} + +/** + ****************************************************************************** + * @brief 主机接收函数，适用MCU之间进行主从通信 + * + * @param I2Cx : I2C1 I2C2 + * @param pu8Data : 接收数据存放地址 + * @param u32Len : 接收数据长度 + * + ******************************************************************************/ +void I2C_MasterRecDataFromSlave(I2C_TypeDef *I2Cx, uint8_t *pu8Data, uint32_t u32Len) +{ + uint8_t u8i = 0, u8State; + I2C_GenerateSTART(I2Cx, ENABLE); + while (1) + { + while (0 == I2C_GetIrq(I2Cx)) + {} + u8State = I2C_GetState(I2Cx); + switch (u8State) + { + case 0x08: //发送完START信号 + case 0x10: //发送完重复起始信号 + I2C_GenerateSTART(I2Cx, DISABLE); + I2C_Send7bitAddress(I2Cx, I2C_SLAVEADDRESS, 0X01); //发送从机地址+R字节 + break; + case 0x40: //发送完SLA+R信号，开始接收数据 + if (u32Len > 1) + { + I2C_AcknowledgeConfig(I2Cx, ENABLE); + } + break; + case 0x50: //接收完一字节数据，在接收最后1字节数据之前设置AA=0; + pu8Data[u8i++] = I2C_ReceiveData(I2Cx); + if (u8i == u32Len - 1) + { + I2C_AcknowledgeConfig(I2Cx, DISABLE); + } + break; + case 0x58: //接收到一个数据字节，且NACK已回复 + pu8Data[u8i++] = I2C_ReceiveData(I2Cx); + I2C_GenerateSTOP(I2Cx, ENABLE); + break; + case 0x38: //主机在发送 SLA+W 阶段或者发送数据阶段丢失仲裁 或者 主机在发送 SLA+R 阶段或者回应 NACK 阶段丢失仲裁 + I2C_GenerateSTART(I2Cx, ENABLE); + break; + case 0x48: //发送完SLA+R后从机返回NACK + I2C_GenerateSTOP(I2Cx, ENABLE); + I2C_GenerateSTART(I2Cx, ENABLE); + break; + default: + I2C_GenerateSTART(I2Cx, ENABLE);//其他错误状态，重新发送起始条件 + break; + } + I2C_ClearIrq(I2Cx); + if (u8i == u32Len) + { + break; + } + } +} + +/** + ****************************************************************************** + * @brief 主机发送函数，适用MCU之间进行主从通信 + * + * @param I2Cx : I2C1 I2C2 + * @param pu8Data : 发送数据存放地址 + * @param u32Len : 发送数据长度 + * + ******************************************************************************/ +void I2C_MasterSendDataToSlave(I2C_TypeDef *I2Cx, uint8_t *pu8Data, uint32_t u32Len) +{ + uint8_t u8i = 0; + uint8_t u8State; + + I2C_ClearIrq(I2Cx); + I2C_GenerateSTART(I2Cx, ENABLE); + + while (1) + { + + while (0 == I2C_GetIrq(I2Cx)) + {;} + u8State = I2C_GetState(I2Cx); + + switch (u8State) + { + case 0x08: //发送完START信号 + case 0x10: //已发送重复起始信号 + I2C_GenerateSTART(I2Cx, DISABLE); + I2C_Send7bitAddress(I2Cx, I2C_SLAVEADDRESS, 0X00); //从设备地址+W发送 + break; + case 0x18: //发送完SLA+W信号 + I2C_SendData(I2Cx, pu8Data[u8i++]); + break; + case 0x28: //发送完1字节数据 + if (u8i >= u32Len) + { + I2C_GenerateSTOP(I2Cx, ENABLE); + I2C_ClearIrq(I2Cx); + return; + } + I2C_SendData(I2Cx, pu8Data[u8i++]); + break; + case 0x20: //发送完SLA+W后从机返回NACK + case 0x38: //主机在发送 SLA+W 阶段或者发送数据阶段丢失仲裁 或者 主机在发送 SLA+R 阶段或者回应 NACK 阶段丢失仲裁 + case 0x30: //发送完一个数据字节后从机返回NACK + default: + I2C_GenerateSTOP(I2Cx, ENABLE); + I2C_ClearIrq(I2Cx); + return; + } + I2C_ClearIrq(I2Cx); + } +} + + +/** + * @brief 从机发送函数，适用MCU之间进行主从通信 + * + * @param I2Cx : I2C1 I2C2 + * @param pu8Data : 发送数据存放地址 + * @param u32Len : 发送数据长度 + */ +void I2C_SlaveSendDataToMaster(I2C_TypeDef *I2Cx, uint8_t *pu8Data, uint32_t *u32Len) +{ + uint8_t u8i = 0, u8State; + while (1) + { + while (0 == I2C_GetIrq(I2Cx)) + {} + u8State = I2C_GetState(I2Cx); + switch (u8State) + { + case 0xA8: //接收到SLA+R,ACK已回应 + case 0xB0: //主机丢失仲裁后被转从机并被SLA+R寻址，ACK已回应 + I2C_SendData(I2Cx, pu8Data[u8i++]); + break; + case 0xB8: //从机已发送1字节数据，ACK已收到 + I2C_SendData(I2Cx, pu8Data[u8i++]); + break; + case 0xC8: //从机最后一个数据字节已被发送(发送前自身AA被设置为0)，并已接收到ACK + // I2C_SendData(I2Cx,pu8Data[u8i++]); //不需要发 + // break; + case 0xC0: //已发送数据字节，已接收 NACK + *u32Len = u8i; + break; + default: + break; + } + I2C_ClearIrq(I2Cx); + if ((0xC0 == u8State) || (0xC8 == u8State)) + { + break; + } + } +} + +/** + * @brief 从机接收函数，适用MCU之间进行主从通信 + * + * @param I2Cx : I2C1 I2C2 + * @param pu8Data : 接收数据存放地址 + * @param u32Len : 接收数据长度 + */ +void I2C_SlaveRecDataFromMaster(I2C_TypeDef *I2Cx, uint8_t *pu8Data, uint32_t *pu32Len) +{ + uint8_t u8i = 0, u8State; + I2C_AcknowledgeConfig(CW_I2C2, ENABLE); //ACK打开 + while (1) + { + while (0 == I2C_GetIrq(I2Cx)) + {} + u8State = I2C_GetState(I2Cx); + switch (u8State) + { + case 0x60: //接收到SLA+W，ACK已回应 + case 0x68: //主机丢失仲裁后被SLA+W寻址，ACK已回应 + case 0x70: //接收到SLA（广播地址）+W，ACK已回应 + case 0x78: //主机丢失仲裁后被SLA（广播地址）+W寻址，ACK已回应 + break; + case 0x80: //从机已接收到1字节数据，ACK已回复 + case 0x90: //从机已接收到1字节广播数据，ACK已回复 + case 0x88: //从机已接收到1字节数据，NACK已回应 + case 0x98: //从机已接收到1字节广播数据，NACK已回应 + pu8Data[u8i++] = I2C_ReceiveData(I2Cx); + break; + case 0xA0: //重复START信号或者STOP信号已收到 + *pu32Len = u8i; + break; + default: + break; + } + I2C_ClearIrq(I2Cx); + if (0xA0 == u8State) + { + break; + } + } +} + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_iwdt.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_iwdt.c new file mode 100644 index 0000000..d08b8ad --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_iwdt.c @@ -0,0 +1,244 @@ +/** + * @file cw32f030_iwdt.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-04-25 + * + * @copyright Copyright (c) 2021 + * + */ +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_iwdt.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief IWDT去初始化 + */ +void IWDT_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.IWDT = 0; + CW_SYSCTRL->APBRST1_f.IWDT = 1; +} + +/** + * @brief IWDT初始化 + * @param IWDT_InitStruct 该结构体包含IWDT需要配置的参数 + * @return 0:sucess 1:error + */ +int IWDT_Init(IWDT_InitTypeDef *IWDT_InitStruct) +{ + uint16_t timeout = 0xffff; + assert_param(IS_IWDT_PRESCALER(IWDT_InitStruct->IWDT_Prescaler)); + assert_param(IS_IWDT_ACTION(IWDT_InitStruct->IWDT_OverFlowAction)); + assert_param(IS_IWDT_SLEEP_MODE(IWDT_InitStruct->IWDT_Pause)); + assert_param(IS_IWDT_WINDOW_VALUE(IWDT_InitStruct->IWDT_WindowValue)); + assert_param(IS_IWDT_RELOAD(IWDT_InitStruct->IWDT_ReloadValue)); + __IWDT_RUN(); // 需要先启动IWDT后，才能修改其他寄存器 + __IWDT_UNLOCK(); // 解锁寄存器保护 + if (IWDT_InitStruct->IWDT_ITState == ENABLE) + { + CW_IWDT->CR = IWDT_InitStruct->IWDT_Prescaler | \ + IWDT_InitStruct->IWDT_OverFlowAction | \ + IWDT_CR_IE_Msk | IWDT_InitStruct->IWDT_Pause; + } + else + { + CW_IWDT->CR = (IWDT_InitStruct->IWDT_Prescaler | \ + IWDT_InitStruct->IWDT_OverFlowAction | \ + IWDT_InitStruct->IWDT_Pause); + } + CW_IWDT->ARR = IWDT_InitStruct->IWDT_ReloadValue; + CW_IWDT->WINR = IWDT_InitStruct->IWDT_WindowValue; + while ((CW_IWDT->SR & (IWDT_SR_CRF_Msk | IWDT_SR_ARRF_Msk | IWDT_SR_WINRF_Msk)) && timeout--); + if (timeout == 0) return 1; + + __IWDT_LOCK(); + return 0; +} + +/** + * @brief 启动IWDT + */ +void inline IWDT_Cmd(void) +{ + __IWDT_RUN(); +} + +/** + * @brief 喂狗 + */ +void inline IWDT_Refresh(void) +{ + __IWDT_REFRESH(); +} + +/** + * @brief 寄存器保护解锁 + */ +void inline IWDT_Unlock(void) +{ + __IWDT_UNLOCK(); +} + +/** + * @brief 寄存器保护上锁 + */ +void inline IWDT_Lock(void) +{ + __IWDT_LOCK(); +} + +/** + * @brief 停止IWDT + */ +void inline IWDT_Stop(void) +{ + __IWDT_STOP(); +} + +/** + * @brief 设置IWDT的预分频因数 + * @param IWDT_Prescaler 取值范围 IWDT_Prescaler_DIV4~IWDT_Prescaler_DIV512 + */ +int IWDT_SetPrescaler(uint32_t IWDT_Prescaler) +{ + uint16_t timeout = 0xffff; + assert_param(IS_IWDT_PRESCALER(IWDT_Prescaler)); + + __IWDT_UNLOCK(); + while ((CW_IWDT->SR & IWDT_SR_CRF_Msk) && timeout--); + if (timeout == 0) return 1; + CW_IWDT->CR_f.PRS = IWDT_Prescaler; + __IWDT_LOCK(); + return 0; +} + +/** + * @brief 设置IWDT的窗口值 + * @param WindowValue 取值范围0x00000000~0x00000FFF,当值为0x00000FFF时，窗口功能不开启 + */ +int IWDT_SetWindowValue(uint32_t WindowValue) +{ + uint16_t timeout = 0xffff; + assert_param(IS_IWDT_WINDOW_VALUE(WindowValue)); + + __IWDT_UNLOCK(); + while ((CW_IWDT->SR & IWDT_SR_WINRF_Msk) && timeout--); + if (timeout == 0) return 1; + CW_IWDT->WINR = WindowValue; + __IWDT_LOCK(); + return 0; +} + +/** + * @brief 设置IWDT的重载寄存器的值 + * @param ReloadValue 取值范围0x00000000~0x00000FFF + */ +int IWDT_SetReloadValue(uint32_t ReloadValue) +{ + uint16_t timeout = 0xffff; + assert_param(IS_IWDT_RELOAD(ReloadValue)); + + __IWDT_UNLOCK(); + while ((CW_IWDT->SR & IWDT_SR_ARRF_Msk) && timeout--); + if (timeout == 0) return 1; + CW_IWDT->ARR = ReloadValue; + __IWDT_LOCK(); + return 0; +} + +/** + * @brief 设置IWDT的中断使能与禁能 + * @param NewState IWDT中断使能位状态 范围：ENABLE或DISABLE + */ +int IWDT_ITConfig(FunctionalState NewState) +{ + uint16_t timeout = 0xffff; + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + __IWDT_UNLOCK(); + while ((CW_IWDT->SR & IWDT_SR_CRF_Msk) && timeout--); + if (timeout == 0) return 1; + NewState ? (CW_IWDT->CR_f.IE = ENABLE) : (CW_IWDT->CR_f.IE = DISABLE); + __IWDT_LOCK(); + return 0; +} + +/** + * @brief 获取IWDT的状态 + * @param StatusBit 状态位的位置,取值范围为：IWDT_SR_CRF_Msk + * IWDT_SR_ARRF_Msk + * IWDT_SR_WINRF_Msk + * IWDT_SR_OV_Msk + * IWDT_SR_RUN_Msk + * IWDT_SR_RELOAD_Msk + * + * @return FlagStatus + */ +FlagStatus IWDT_GetFlagStatus(uint32_t StatusBit) +{ + return (FlagStatus)(CW_IWDT->SR & StatusBit); +} + +/** + * @brief 清除IWDT的溢出标志OV + */ +void inline IWDT_ClearOVFlag(void) +{ + CW_IWDT->SR_f.OV = 0; +} + +/** + * @brief + * @return uint32_t 返回IWDT的计数值 + */ +uint32_t IWDT_GetCounterValue(void) +{ + uint32_t tmp1, tmp2; + do + { + tmp1 = CW_IWDT->CNT; + tmp2 = CW_IWDT->CNT; + } while(tmp1 != tmp2); + + return tmp1; +} + +/** + * @brief Set IWDT counting period. + * @param counting period: + WDT_2_SECS + WDT_1_SECS + WDT_0_5_SECS + WDT_0_25_SECS + * @retval None + */ +void IWDT_SetPeriod(uint32_t period) +{ + IWDT_InitTypeDef IWDT_InitStruct = {0}; + + assert_param(IS_IWDT_PERIOD(period)); + + + IWDT_InitStruct.IWDT_ITState = DISABLE; + IWDT_InitStruct.IWDT_OverFlowAction = IWDT_OVERFLOW_ACTION_RESET; + IWDT_InitStruct.IWDT_Pause = IWDT_SLEEP_CONTINUE; + IWDT_InitStruct.IWDT_Prescaler = IWDT_Prescaler_DIV512; // 默认设置为最大分频，计时间隔为51.2ms + IWDT_InitStruct.IWDT_WindowValue = 0xFFF; // 关闭窗口看门狗的功能 + IWDT_InitStruct.IWDT_ReloadValue = period; + + IWDT_Init(&IWDT_InitStruct); + IWDT_Refresh(); +} diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_lvd.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_lvd.c new file mode 100644 index 0000000..573316c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_lvd.c @@ -0,0 +1,299 @@ +/** + * @file cw32f030_lvd.c + * @author WHXY + * @brief + * @version 0.1 + * @file cw32f030_lvd.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-07-27 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉力源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉力源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉力源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "cw32f030.h" +#include "cw32f030_lvd.h" + +/** + ****************************************************************************** + ** \addtogroup LvdGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#define IS_VALID_INPUT(x) ( (x) <= LvdInputPB11 ) + +#define IS_VALID_THRESHOLD(x) ( (x) <= LvdTH3p3V ) + +#define IS_VALID_CLK(x) ( (x) <= LvdFilterHsi ) + +#define IS_VALID_FILTER(x) ( (x) <= LvdFilter4095Clk ) + +#define IS_VALID_IRQTYPE(x) ( (x) <= LvdIrqFall ) + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') * + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** + * @brief + * 使能NVIC的LVD中断 + * + * @param intPriority:0~3 + * + * @return 无 + */ +void LVD_EnableNvic(uint8_t intPriority) +{ + NVIC_ClearPendingIRQ(LVD_IRQn); + NVIC_SetPriority(LVD_IRQn, intPriority); + NVIC_EnableIRQ(LVD_IRQn); +} + +/** + * @brief + * 停止NVIC的LVD中断 + * + * @param 无 + * + * @return 无 + */ +void LVD_DisableNvic(void) +{ + NVIC_ClearPendingIRQ(LVD_IRQn); + NVIC_DisableIRQ(LVD_IRQn); +} + +/** + * @brief + * 配置LVD中断/系统复位触发方式 + * + * @param LVD_TRIG: + * @arg LVD_TRIG_LEVEL + * @arg LVD_TRIG_FALL + * @arg LVD_TRIG_RISE + * @param NewState: + * @arg DISABLE + * @arg ENABLE + * + * @return 无 + */ +void LVD_TrigConfig(uint16_t LVD_TRIG, FunctionalState NewState) +{ + uint8_t itMask = 0; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_LVD_TRIG(LVD_TRIG)); + /* Get the LVD TRIG index */ + itMask = (uint8_t) LVD_TRIG; + if (NewState != DISABLE) + { + /* Enable the selected LVD interrupts */ + CW_LVD->CR1 |= itMask; + } + else + { + /* Disable the selected LVD interrupts */ + CW_LVD->CR1 &= (~(uint32_t) itMask); + } +} + +/** + * @brief + * 使能LVD中断 + * + * @param intPriority:0~3 + * + * @return + */ +void LVD_EnableIrq(uint8_t intPriority) +{ + REGBITS_SET(CW_LVD->CR0, LVD_CR0_IE_Msk); + LVD_EnableNvic(intPriority); +} + +/** + * @brief + * 禁止LVD中断 + * + * @param 无 + * + * @return 无 + */ +void LVD_DisableIrq(void) +{ + LVD_DisableNvic(); + REGBITS_CLR(CW_LVD->CR0, LVD_CR0_IE_Msk); + REGBITS_CLR(CW_LVD->CR1, LVD_CR1_LEVEL_Msk | LVD_CR1_FALL_Msk | LVD_CR1_RISE_Msk); +} + +/** + * @brief + * LVD初始化 + * + * @param LVD_InitStruct + * + * @return 无 + */ +void LVD_Init(LVD_InitTypeDef *LVD_InitStruct) +{ + ASSERT(LVD_InitStruct); + assert_param(IS_LVD_ACTION(LVD_InitStruct->LVD_Action)); + assert_param(IS_LVD_SOURCE(LVD_InitStruct->LVD_Source)); + assert_param(IS_LVD_THRESHOLD(LVD_InitStruct->LVD_Threshold)); + assert_param(IS_LVD_FILTER_CLK(LVD_InitStruct->LVD_FilterClk)); + assert_param(IS_LVD_FILTER_TIME(LVD_InitStruct->LVD_FilterTime)); + assert_param(IS_LVD_FILTER(LVD_InitStruct->LVD_FilterEn)); + //Need to DISABLE first. + LVD_Disable(); + LVD_DisableIrq(); + REGBITS_MODIFY(CW_LVD->CR1, LVD_CR1_FLTCLK_Msk | LVD_CR1_FLTTIME_Msk | LVD_CR1_FLTEN_Msk, \ + (LVD_InitStruct->LVD_FilterClk | \ + LVD_InitStruct->LVD_FilterTime | \ + LVD_InitStruct->LVD_FilterEn)); + REGBITS_MODIFY(CW_LVD->CR0, LVD_CR0_VTH_Msk | LVD_CR0_SOURCE_Msk | LVD_CR0_ACTION_Msk, \ + (LVD_InitStruct->LVD_Threshold | \ + LVD_InitStruct->LVD_Source | \ + LVD_InitStruct->LVD_Action)); +} + +/** + * @brief + * LVD deinit + * + * @param 无 + * + * @return 无 + */ +void LVD_DeInit(void) +{ + LVD_DisableIrq(); + LVD_Disable(); +} + +/** + * @brief + * 使能LVD + * + * @param 无 + * + * @return 无 + */ +void LVD_Enable(void) +{ + REGBITS_SET(CW_LVD->CR0, LVD_CR0_EN_Msk); +} + +/** + * @brief + * 停止LVD + * + * @param 无 + * + * @return 无 + */ +void LVD_Disable(void) +{ + REGBITS_CLR(CW_LVD->CR0, LVD_CR0_EN_Msk); +} + +/** + * @brief + * 获取LVD中断标志 + * + * @param 无 + * + * @return boolean_t: TRUE or FALSE + */ +boolean_t LVD_GetIrqStatus(void) +{ + return (boolean_t)(REGBITS_GET(CW_LVD->SR, LVD_SR_INTF_Msk)); +} + +/** + * @brief + * 获取LVD指定的中断状态 + * + * @param LVD_FLAG: + * @arg LVD_FLAG_FLTV + * @arg LVD_FLAG_INTF + * + * @return FlagStatus: SET or RESET + */ +FlagStatus LVD_GetFlagStatus(uint16_t LVD_FLAG) +{ + assert_param(IS_LVD_GET_FLAG(LVD_FLAG)); + return (REGBITS_GET(CW_LVD->SR, LVD_FLAG) ? SET : RESET); +} + +/** + * @brief + * 清除LVD中断标志 + * + * @param 无 + * + * @return 无 + */ +void LVD_ClearIrq(void) +{ + REGBITS_CLR(CW_LVD->SR, LVD_SR_INTF_Msk); +} + +/** + * @brief + * 获取Filter结果 + * + * @param 无 + * + * @return boolean_t: TRUE or FALSE + */ +boolean_t LVD_GetFilterResult(void) +{ + return (boolean_t)(REGBITS_GET(CW_LVD->SR, LVD_SR_FLTV_Msk)); +} +//@} // LvdGroup + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_pwr.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_pwr.c new file mode 100644 index 0000000..af119a7 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_pwr.c @@ -0,0 +1,120 @@ +/** + * @file cw32f030_pwr.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-08-09 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "cw32f030.h" +#include "cw32f030_pwr.h" + +/** + ******************************************************************************* + ** \addtogroup LpmGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +/* +#define IS_VALID_SEVONPEND(x) (SevPndDisable == (x) ||\ + SevPndEnable == (x)) +#define IS_VALID_SLEEPDEEP(x) (SlpDpDisable == (x) ||\ + SlpDpEnable == (x)) +#define IS_VALID_SLEEPONEXIT(x) (SlpExtDisable == (x) ||\ + SlpExtEnable == (x)) +*/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief 低功耗模式配置 + * + * @param PWR_InitStruct 低功耗模式配置结构体指针 + * + * @return + */ +void PWR_Config(PWR_InitTypeDef *PWR_InitStruct) +{ + //ASSERT(NULL != PWR_InitStruct); + assert_param(IS_PWR_SEVONPEND(PWR_InitStruct->PWR_Sevonpend)); + assert_param(IS_PWR_SLEEPDEEP(PWR_InitStruct->PWR_SleepDeep)); + assert_param(IS_PWR_SLEEPONEXIT(PWR_InitStruct->PWR_SleepOnExit)); + REGBITS_MODIFY(SCB->SCR, SCB_SCR_SEVONPEND_Msk | \ + SCB_SCR_SLEEPDEEP_Msk | \ + SCB_SCR_SLEEPONEXIT_Msk, \ + PWR_InitStruct->PWR_Sevonpend | \ + PWR_InitStruct->PWR_SleepDeep | \ + PWR_InitStruct->PWR_SleepOnExit); +} + +/** + * @brief 进入睡眠模式 + * + * @return + */ +void PWR_GotoLpmMode(void) +{ + uint32_t RegBack; + if (SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) // 进入深度休眠，需要做一些保护操作 + { + if (CW_SYSCTRL->APBEN2_f.VC) // VC的时钟打开，需要判断VC的ready位状态是否为1，否则无法进入深度睡眠 + { + while (!CW_VC1->SR_f.READY); + while (!CW_VC2->SR_f.READY); + } + // 进入深度休眠，HCLK的时钟频率需要小于等于4Mhz，否者容易损坏内核 + RegBack = CW_SYSCTRL->CR0; + CW_SYSCTRL->CR0_f.HCLKPRS = 6; // 64分频，HCLK的频率不会超过4Mhz + } + __WFI(); + // 退出休眠后，恢复HCLK的配置 + CW_SYSCTRL->CR0 = RegBack; +} + +//@} // LpmGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_ram.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_ram.c new file mode 100644 index 0000000..09a7cf9 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_ram.c @@ -0,0 +1,96 @@ +/** + * @file cw32f030_ram.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-14 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_ram.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief RAM中断配置 + * + * @param RAM_IT : RAM_IT_PARITY + * @param NewState : ENABLE DISABLE + */ +void RAM_ITConfig(uint32_t RAM_IT, FunctionalState NewState) +{ + assert_param(IS_RAM_IT(RAM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + CW_RAM->IER |= RAM_IT; + } + else + { + CW_RAM->IER &= (~RAM_IT); + } +} + +/** + * @brief 获取RAM中断标志 + * + * @param RAM_IT : RAM_IT_PARITY + * @return ITStatus : SET RESET + */ +ITStatus RAM_GetITStatus(uint32_t RAM_IT) +{ + assert_param(IS_RAM_GET_IT(RAM_IT)); + return (CW_RAM->ISR & RAM_IT) ? SET : RESET; +} + +/** + * @brief 清除RAM中断标志 + * + * @param RAM_IT : RAM_IT_PARITY + */ +void RAM_ClearITPendingBit(uint32_t RAM_IT) +{ + assert_param(IS_RAM_IT(RAM_IT)); + CW_RAM->ICR &= (~RAM_IT); +} + +/** + * @brief 获取发生奇偶校验错的RAM地址 + * + * @return uint32_t + */ +uint32_t RAM_GetErrorAddress(void) +{ + return (CW_RAM->ADDR); +} + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_rcc.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_rcc.c new file mode 100644 index 0000000..663d94e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_rcc.c @@ -0,0 +1,1024 @@ +/** + * @file cw32f030_rcc.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-13 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_rcc.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ +const uint32_t hsiprs_tbl[] = {6, 6, 6, 6, 6, 6, 1, 3, 2, 4, 6, 8, 10, 12, 14, 16}; + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief 配置SysClk 到 HCLK的分频系数 + * + * @param HCLKPRS ：RCC_HCLK_DIV1/2/4/8/16/32/64/128 + */ +void RCC_HCLKPRS_Config(uint32_t HCLKPRS) +{ + assert_param(IS_RCC_HCLKPRS(HCLKPRS)); + CW_SYSCTRL->CR0 = ((CW_SYSCTRL->CR0 & (~(SYSCTRL_BYPASS_MASK | SYSCTRL_CR0_HCLKPRS_Msk))) | SYSCTRL_BYPASS | HCLKPRS); +} +/** + * @brief 配置HCLK 到 PCLK的分频系数 + * + * @param PCLKPRS ：RCC_PCLK_DIV1/2/4/8 + */ +void RCC_PCLKPRS_Config(uint32_t PCLKPRS) +{ + assert_param(IS_RCC_PCLKPRS(PCLKPRS)); + CW_SYSCTRL->CR0 = ((CW_SYSCTRL->CR0 & (~(SYSCTRL_BYPASS_MASK | SYSCTRL_CR0_PCLKPRS_Msk))) | SYSCTRL_BYPASS | PCLKPRS); +} + +/** + * @brief 配置SysClk的时钟源 + * + * @param SYSCLKSRC ：RCC_SYSCLKSRC_HSI RCC_SYSCLKSRC_HSE RCC_SYSCLKSRC_PLL + * RCC_SYSCLKSRC_LSI RCC_SYSCLKSRC_LSE + */ +void RCC_SYSCLKSRC_Config(uint32_t SYSCLKSRC) +{ + assert_param(IS_RCC_SYSCLKSRC(SYSCLKSRC)); + CW_SYSCTRL->CR0 = ((CW_SYSCTRL->CR0 & (~(SYSCTRL_BYPASS_MASK | SYSCTRL_CR0_SYSCLK_Msk))) | SYSCTRL_BYPASS | SYSCLKSRC); + RCC_SystemCoreClockUpdate(RCC_Sysctrl_GetHClkFreq()); +} + +/** + * @brief 配置CLKCCS HSECCS LSECCS 功能 + * + * @param CCS ：RCC_SYSCTRL_LSECCS RCC_SYSCTRL_HSECCS RCC_SYSCTRL_CLKCCS + * @param NewState :ENABLE DISABLE + */ +void RCC_CCS_Config(uint32_t CCS, FunctionalState NewState) +{ + assert_param(IS_RCC_CCS_STATUS(CCS)); + if (NewState != DISABLE) + { + CW_SYSCTRL->CR1 = (((CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK)) | SYSCTRL_BYPASS) | CCS); + } + else + { + CW_SYSCTRL->CR1 = (((CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK)) | SYSCTRL_BYPASS) & (~CCS)); + } +} + +/** + * @brief 配置LSELOCK功能：使能后软件无法关闭LSE时钟 + * + * @param LSELOCK ： RCC_SYSCTRL_LSELOCKEN RCC_SYSCTRL_LSELOCKDIS + */ +void RCC_LSELOCK_Config(uint32_t LSELOCK) +{ + assert_param(IS_RCC_LSELOCK_STATUS(LSELOCK)); + CW_SYSCTRL->CR1 = ((CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK)) | SYSCTRL_BYPASS | LSELOCK); +} + +/** + * @brief 配置WAKEUPCLK功能:决定从深度休眠模式唤醒后所使用的系统时钟源 + * + * @param WAKEUPCLK ：RCC_SYSCTRL_WAKEUPCLKEN RCC_SYSCTRL_WAKEUPCLKDIS + */ +void RCC_WAKEUPCLK_Config(uint32_t WAKEUPCLK) +{ + assert_param(IS_RCC_WAKEUPCLK_STATUS(WAKEUPCLK)); + CW_SYSCTRL->CR2 = ((CW_SYSCTRL->CR2 & (~(SYSCTRL_BYPASS_MASK | SYSCTRL_CR2_WAKEUPCLK_Msk))) | SYSCTRL_BYPASS | WAKEUPCLK); +} + +/** + * @brief 配置LOCK功能：决定异常故障后是否产生LOCKUP复位 + * + * @param LOCKUP ：RCC_SYSCTRL_LOCKUPEN RCC_SYSCTRL_LOCKUPDIS + */ +void RCC_LOCKUP_Config(uint32_t LOCKUP) +{ + assert_param(IS_RCC_LOCKUP_STATUS(LOCKUP)); + CW_SYSCTRL->CR2 = ((CW_SYSCTRL->CR2 & (~(SYSCTRL_BYPASS_MASK | SYSCTRL_CR2_LOCKUP_Msk))) | SYSCTRL_BYPASS | LOCKUP); +} + +/** + * @brief 配置端口SWDIO功能 + * + * @param SWDIO ：RCC_SYSCTRL_SWDIOEN RCC_SYSCTRL_SWDIODIS + */ +void RCC_SWDIO_Config(uint32_t SWDIO) +{ + assert_param(IS_RCC_SWDIO_STATUS(SWDIO)); + CW_SYSCTRL->CR2 = ((CW_SYSCTRL->CR2 & (~(SYSCTRL_BYPASS_MASK | SYSCTRL_CR2_SWDIO_Msk))) | SYSCTRL_BYPASS | SWDIO); +} + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @param None + * @retval None + * CAUTION: + * 1、LSEEN Bit Not Changed ,so it will not affect RTC,BUT LSELOCK BIT Changed. + * 2、Before CALL this funciton,we should set FLASH_CR2.WAIT + */ +int RCC_DeInit(void) +{ + uint16_t timeout = 0xffff; + /* HSIEN Enable*/ + CW_SYSCTRL->CR1 = ((CW_SYSCTRL->CR1 & (~SYSCTRL_BYPASS_MASK)) | SYSCTRL_BYPASS | RCC_SYSCTRL_HSIEN); + + //Here need wait HSI STBALE + while (((CW_SYSCTRL->HSI & SYSCTRL_HSI_STABLE_Msk) != SYSCTRL_HSI_STABLE_Msk) && timeout--); //Wait stable + if (timeout == 0) return 1; + + + // CW_FLASH->CR2 = ( ((CW_FLASH->CR2) & (~ SYSCTRL_BYPASS_MASK) ) | (uint32_t)0x5A5A0001 ); + /* SWITCH TO HSI*/ + CW_SYSCTRL->CR0 = ((CW_SYSCTRL->CR0 & (~ SYSCTRL_BYPASS_MASK)) | SYSCTRL_BYPASS | RCC_SYSCLKSRC_HSI); + /* HCLKPRS SET TO 000,PCLKPRS SET TO 00*/ + CW_SYSCTRL->CR0 = ((CW_SYSCTRL->CR0 & (~ SYSCTRL_BYPASS_MASK)) | SYSCTRL_BYPASS | RCC_HCLK_DIV1 | \ + RCC_PCLK_DIV1 | RCC_SYSCLKSRC_HSI); + /* CLKCCS/HSECCS/LSECCS/LSELOCK/LSIEN/PLLEN/HSEEN Disable CLKCCS / LSEEN NO CHANGE*/ + CW_SYSCTRL->CR1 = (((CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK)) | SYSCTRL_BYPASS | RCC_SYSCTRL_HSIEN) \ + & (~ RCC_SYSCTRL_CLKCCS) & (~ RCC_SYSCTRL_HSECCS) & (~ RCC_SYSCTRL_LSECCS) \ + & (~ RCC_SYSCTRL_LSELOCKEN) & (~ RCC_SYSCTRL_LSIEN) & (~ RCC_SYSCTRL_PLLEN) \ + & (~ RCC_SYSCTRL_HSEEN)); + /* SWDIO Enable,LOCKUP/WAKEUPCLK Disable*/ + CW_SYSCTRL->CR2 = (((((CW_SYSCTRL->CR2 & (~ SYSCTRL_BYPASS_MASK)) | SYSCTRL_BYPASS) \ + & (~ RCC_SYSCTRL_SWDIOEN)) & (~ RCC_SYSCTRL_LOCKUPEN)) & (~ RCC_SYSCTRL_WAKEUPCLKEN)); + /* Disable all interrupts */ + CW_SYSCTRL->IER = 0x5A5AFE00; //IER have KEY attribute + /* Clear all pending bits */ + CW_SYSCTRL->ICR &= 0xFFFFFE00; + //外设时钟和复位寄存器设置 ?? + return 0; +} + +/** + * @brief + * + * @param NewFreq + */ +void RCC_SystemCoreClockUpdate(uint32_t NewFreq) +{ + SystemCoreClock = NewFreq; +} + +/** + * @brief 获得系统时钟（HCLK）频率值 + * + * @return uint32_t HCLK频率值(Hz) + */ +uint32_t RCC_Sysctrl_GetHClkFreq(void) +{ + uint32_t u32rtnVal = 0; + uint32_t sysclksource = 0; + uint32_t hsiprs = 0; + uint32_t pllmul = 0; + uint32_t pllrefclk = 0; + sysclksource = CW_SYSCTRL->CR0_f.SYSCLK; + hsiprs = CW_SYSCTRL->HSI_f.DIV; + pllrefclk = CW_SYSCTRL->PLL_f.SOURCE; + pllmul = CW_SYSCTRL->PLL_f.MUL; + switch (sysclksource) + { + case 0x00: /* HSI used as system clock */ + u32rtnVal = (HSIOSC_VALUE / hsiprs_tbl[hsiprs]); + break; + case 0x01: /* HSE used as system clock */ + u32rtnVal = HSE_VALUE; + break; + case 0x03: /* LSI used as system clock */ + u32rtnVal = LSI_VALUE; + break; + case 0x04: /* LSE used as system clock */ + u32rtnVal = LSE_VALUE; + break; + case 0x02: /* PLL used as system clock */ + switch (pllrefclk) + { + case 0x00: /* HSEOSC used as pll refclk */ + case 0x01: /* HSEIN used as pll refclk */ + u32rtnVal = (HSE_VALUE * pllmul) ; + break; + case 0x03: /* HSI used as pll refclk */ + u32rtnVal = ((HSIOSC_VALUE / hsiprs_tbl[hsiprs]) * pllmul) ; + break; + default: + u32rtnVal = ((HSIOSC_VALUE / hsiprs_tbl[hsiprs]) * pllmul) ; + break; + } + break; + default: + u32rtnVal = (HSIOSC_VALUE / hsiprs_tbl[hsiprs]) ; + break; + } + u32rtnVal = (u32rtnVal >> CW_SYSCTRL->CR0_f.HCLKPRS) ; + return u32rtnVal; +} + +/** + * @brief 获得外设时钟（PCLK）频率值 + * + * @return uint32_t PCLK频率值(Hz) + */ +uint32_t RCC_Sysctrl_GetPClkFreq(void) +{ + uint32_t u32Val = 0; + u32Val = RCC_Sysctrl_GetHClkFreq(); + u32Val = (u32Val >> (CW_SYSCTRL->CR0_f.PCLKPRS)); + return u32Val; +} + +/** +* @brief Enable HSI +* @param HSIDiv: +* RCC_HSIOSC_DIV1 +* RCC_HSIOSC_DIV2 +* RCC_HSIOSC_DIV3 +* RCC_HSIOSC_DIV4 +* RCC_HSIOSC_DIV6 +* RCC_HSIOSC_DIV8 +* RCC_HSIOSC_DIV10 +* RCC_HSIOSC_DIV12 +* RCC_HSIOSC_DIV14 +* RCC_HSIOSC_DIV16 +* +* @retval None +*/ +int RCC_HSI_Enable(uint32_t HSIDiv) +{ + uint16_t timeout = 0xffff; + assert_param(IS_RCC_HSIOSC_DIV(HSIDiv)); + //CW_SYSCTRL->HSI_f.DIV = HSIDiv; + CW_SYSCTRL->HSI = (HSIDiv << SYSCTRL_HSI_DIV_Pos) | (*((volatile uint16_t *)RCC_HSI_TRIMCODEADDR)) ; //正式版芯片才需要加载Trim值 + CW_SYSCTRL->CR1 |= SYSCTRL_BYPASS | SYSCTRL_CR1_HSIEN_Msk ; //Enable HSI + while (((CW_SYSCTRL->HSI & SYSCTRL_HSI_STABLE_Msk) != SYSCTRL_HSI_STABLE_Msk) && timeout--); //Wait stable + if (timeout == 0) return 1; + return 0; +} + +/** +* @brief Disable HSI +* @param None. +* @retval None. +*/ +void RCC_HSI_Disable(void) +{ + CW_SYSCTRL->CR1 = (((CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK)) | SYSCTRL_BYPASS) & \ + (~SYSCTRL_CR1_HSIEN_Msk)); +} + + +/** +* @brief Enable LSI +* @param None: +* @retval None +*/ +int RCC_LSI_Enable(void) +{ + uint16_t timeout = 0xffff; + CW_SYSCTRL->LSI = *((uint16_t*)RCC_LSI_TRIMCODEADDR); + CW_SYSCTRL->LSI |= RCC_LSI_WAITCYCLE_258; //WaitCycle = 258 + CW_SYSCTRL->CR1 |= SYSCTRL_BYPASS | SYSCTRL_CR1_LSIEN_Msk; //Enable LSI + while (((CW_SYSCTRL->LSI & SYSCTRL_LSI_STABLE_Msk) != SYSCTRL_LSI_STABLE_Msk) && timeout--); //Wait stable + if (timeout == 0) return 1; + return 0; + +} + +/** +* @brief Disable LSI +* @param None. +* @retval None. +*/ +void RCC_LSI_Disable(void) +{ + CW_SYSCTRL->CR1 = (((CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK)) | SYSCTRL_BYPASS) & \ + (~SYSCTRL_CR1_LSIEN_Msk)); +} + + +/** +* @brief Enable HSE +* @param Mode: RCC_HSE_MODE_OSC: Oscillator, +* RCC_HSE_MODE_CLK: Input Clk +* +* @param FreqIn: 4000000Hz ~ 32000000Hz +* +* @param Driver: RCC_HSE_DRIVER_LEAST, +* RCC_HSE_DRIVER_SMALL, +* RCC_HSE_DRIVER_NORMAL, (default) +* RCC_HSE_DRIVER_LARGER +* +* @param Flt: RCC_HSE_FLT_OPEN, +* RCC_HSE_FLT_CLOSE +* +* @retval None + +16M驱动配置建议： +Range: 建议配置为2 +Driver：建议配置为1或者2 + +24M驱动配置建议： +Range: 建议配置为3 +Driver：建议配置为1 + +32M驱动配置建议： +Range: 建议配置为3 +Driver：建议配置为2 + +注意：1、选择负载电容小的晶体更容易起振。 +2、Flt: 强干扰环境打开,一般不打开 +*/ +int RCC_HSE_Enable(uint32_t Mode, uint32_t FreqIn, uint8_t Driver, uint32_t Flt) +{ + uint8_t freqRange = 0; + uint16_t timeout = 0xffff; + //参数断言 + assert_param(IS_RCC_HSE_MODE(Mode)); + assert_param(IS_RCC_HSE_FREQIN(FreqIn)); //FPGA测试注释掉，正式版打开 + assert_param(IS_RCC_HSE_DRIVER(Driver)); + assert_param(IS_RCC_HSE_FLT(Flt)); + //根据HSE模式设置IO口功能 + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOF_Msk; //Open GPIOF Clk + if (Mode == RCC_HSE_MODE_OSC) //Oscillator + { + CW_GPIOF->ANALOG |= (bv0 | bv1); //PF00 PF01 as analog pin + } + else //Input clk + { + CW_GPIOF->ANALOG &= ~bv0; //PF00 as input clk pin + CW_GPIOF->DIR |= bv0; //PF00 input + CW_GPIOF->PUR &= ~bv0; + CW_GPIOF->PDR |= bv0; + } + //根据输入频率参数得到对应设置值 + freqRange = (FreqIn == 32000000) ? 0x3UL : (FreqIn / 8000000); + //设置HSE参数 + CW_SYSCTRL->HSE = ((8000000000 / FreqIn) << 8) | \ + (Mode | \ + (RCC_HSE_WAITCYCLE_131072) | \ + (((uint32_t)freqRange << SYSCTRL_HSE_FREQRANGE_Pos)) | \ + (Driver) | \ + (Flt)); + //使能HSE,同时使能CLKCCS和HSECCS，使能时钟失效切换 + CW_SYSCTRL->CR1 |= SYSCTRL_BYPASS | RCC_SYSCTRL_CLKCCS | SYSCTRL_CR1_HSECCS_Msk | SYSCTRL_CR1_HSEEN_Msk; //Enable HSE + //等待HSE稳定 + while (((CW_SYSCTRL->HSE & SYSCTRL_HSE_STABLE_Msk) != SYSCTRL_HSE_STABLE_Msk) && timeout--); //Wait stable + if (timeout == 0) return 1; + return 0; +} + +/** +* @brief Disable HSE +* @param None. +* @retval None. +*/ +void RCC_HSE_Disable(void) +{ + CW_SYSCTRL->CR1 = (((CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK)) | SYSCTRL_BYPASS) & \ + (~SYSCTRL_CR1_HSEEN_Msk)); +} + +/** +* @brief Enable LSE +* @param Mode: RCC_LSE_MODE_OSC: Oscillator, +* RCC_LSE_MODE_CLK: Input Clk +* @param Amp: RCC_LSE_AMP_LEAST, RCC_LSE_AMP_SMALL +* RCC_LSE_AMP_NORMAL，RCC_LSE_AMP_LARGER +* @param Driver: RCC_LSE_DRIVER_LEAST, RCC_LSE_DRIVER_SMALL +* RCC_LSE_DRIVER_NORMAL，RCC_LSE_DRIVER_LARGER +* +* @retval None + +驱动配置建议： +AMP: 建议配置为2（RCC_LSE_AMP_NORMAL）或3（RCC_LSE_AMP_LARGER） +Driver：建议配置为3（RCC_LSE_DRIVER_LARGER） +*/ +int RCC_LSE_Enable(uint32_t Mode, uint8_t Amp, uint8_t Driver) +{ + uint16_t timeout = 0xffff; + //参数断言 + assert_param(IS_RCC_LSE_MODE(Mode)); + assert_param(IS_RCC_LSE_AMP(Amp)); + assert_param(IS_RCC_LSE_DRIVER(Driver)); + //根据LSE模式，设置IO功能 + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOC_Msk; //Open GPIOC clk + if (Mode == RCC_LSE_MODE_OSC) //Oscillator + { + CW_GPIOC->ANALOG |= (bv15 | bv14); //PC15 PC14 as analog pin + } + else //Input clk + { + CW_GPIOC->ANALOG &= ~bv14; //PC14 as input clk pin + CW_GPIOC->DIR |= bv14; //PC14 input + CW_GPIOC->PUR &= bv14; + CW_GPIOC->PDR |= bv14; + } + //设置LSE参数 + CW_SYSCTRL->LSE = ((Mode) | \ + (RCC_LSE_WAITCYCLE_16384) | \ + (Amp) | \ + (Driver)); + //LSE使能,同时使能CLKCCS和LSECCS，使能时钟失效切换 + CW_SYSCTRL->CR1 |= SYSCTRL_BYPASS | RCC_SYSCTRL_CLKCCS | SYSCTRL_CR1_LSECCS_Msk | SYSCTRL_CR1_LSEEN_Msk; //Enable LSE + //等待LSE稳定 + while (((CW_SYSCTRL->LSE & SYSCTRL_LSE_STABLE_Msk) != SYSCTRL_LSE_STABLE_Msk) && timeout--);//Wait stable + if (timeout == 0) return 1; + return 0; +} + +/** +* @brief Disable LSE +* @param None +* @retval None +*/ +void RCC_LSE_Disable(void) +{ + CW_SYSCTRL->CR1 = (((CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK)) | SYSCTRL_BYPASS) & \ + (~SYSCTRL_CR1_LSEEN_Msk)); +} + +/** +* @brief Enable PLL +* @param PLLSource: + RCC_PLLSOURCE_HSEOSC, + RCC_PLLSOURCE_HSECLK, + RCC_PLLSOURCE_HSI +* @param FreqIn: 4000000Hz ~ 24000000Hz +* @param PLLMul: 2~12 +* @retval None +*/ +int RCC_PLL_Enable(uint32_t PLLSource, uint32_t FreqIn, uint32_t PLLMul) +{ + uint8_t i = 0; + uint32_t freqInMsk = 0; + uint32_t freqOutMsk = 0; + uint32_t freqInTable[4] = { 6000000, 12000000, 20000000, 24000001 }; + //uint32_t freqInTable[4] = { 6000000 , 12000000, 20000000, 32000001 }; //FPGA测试打开 + uint32_t freqOutTable[5] = { 18000000, 24000000, 36000000, 48000000, 72000001 }; + uint16_t timeout = 0xffff; + //参数断言 + assert_param(IS_RCC_PLLSOURCE(PLLSource)); + assert_param(IS_RCC_PLL_FREQIN(FreqIn)); //FPGA测试注释掉，正式版打开 + assert_param(IS_RCC_PLL_MUL(PLLMul)); + //计算FREQIN设置值 + for (i = 0; i < (sizeof(freqInTable) / sizeof(freqInTable[0])); i++) + { + if (FreqIn < freqInTable[i]) + { + freqInMsk = i; + break; + } + } + ////计算FREQOUT设置值 + freqOutMsk = FreqIn * PLLMul; + for (i = 0; i < (sizeof(freqOutTable) / sizeof(freqOutTable[0])); i++) + { + if (freqOutMsk < freqOutTable[i]) + { + freqOutMsk = i; + break; + } + } + //设置PLL参数 + CW_SYSCTRL->PLL = (RCC_PLL_WAITCYCLE_16384 | \ + ((uint32_t)(freqOutMsk << SYSCTRL_PLL_FREQOUT_Pos)) | \ + ((uint32_t)(PLLMul << SYSCTRL_PLL_MUL_Pos)) | \ + ((uint32_t)(freqInMsk << SYSCTRL_PLL_FREQIN_Pos)) | \ + ((uint32_t)(PLLSource << SYSCTRL_PLL_SOURCE_Pos))); + //使能PLL + CW_SYSCTRL->CR1 |= SYSCTRL_BYPASS | SYSCTRL_CR1_PLLEN_Msk; //Enable PLL + //等待PLL时钟稳定 + while (((CW_SYSCTRL->PLL & SYSCTRL_PLL_STABLE_Msk) != SYSCTRL_PLL_STABLE_Msk) && timeout--); + if (timeout == 0) return 1; + return 0; +} + +/** +* @brief Disable PLL +* @param None +* @retval None +*/ +void RCC_PLL_Disable(void) +{ + CW_SYSCTRL->CR1 = (((CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK)) | SYSCTRL_BYPASS) & \ + (~SYSCTRL_CR1_PLLEN_Msk)); +} + +/** +* @brief CLKSRC switch +* @param NewClk: +* RCC_SYSCLKSRC_HSI, +* RCC_SYSCLKSRC_HSE, +* RCC_SYSCLKSRC_PLL, +* RCC_SYSCLKSRC_LSI, +* RCC_SYSCLKSRC_LSE +* @retval 0: PASS, 1: Fail +* +* NOTE:调用此函数之前需要保证新时钟源已经使能（ENABLE函数中已包含等待时钟稳定过程）。 +*/ + +uint8_t RCC_SysClk_Switch(uint32_t NewClk) +{ + assert_param(IS_RCC_SYSCLKSRC(NewClk)); + CW_SYSCTRL->CR0 = ((((CW_SYSCTRL->CR0 & (~ SYSCTRL_BYPASS_MASK)) | SYSCTRL_BYPASS) & (~SYSCTRL_CR0_SYSCLK_Msk)) | (NewClk)); + RCC_SystemCoreClockUpdate(RCC_Sysctrl_GetHClkFreq()); + return (((CW_SYSCTRL->CR0 & SYSCTRL_CR0_SYSCLK_Msk) == NewClk) ? 0U : 1U); +} + +/** + * @brief RCC中断配置 + * + * @param RCC_IT ：RCC_IT_HSEFAULT RCC_IT_LSEFAULT + * RCC_IT_HSEFAIL RCC_IT_LSEFAIL + * RCC_IT_LSERDY RCC_IT_LSIRDY + * RCC_IT_PLLRDY RCC_IT_HSERDY + * RCC_IT_HSIRDY + * @param NewState :ENABLE DISABLE + */ +void RCC_ITConfig(uint32_t RCC_IT, FunctionalState NewState) +{ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) //IER have KEY attribute + { + CW_SYSCTRL->IER = ((CW_SYSCTRL->IER & (~ SYSCTRL_BYPASS_MASK)) | SYSCTRL_BYPASS) | RCC_IT; + } + else //IER have KEY attribute + { + CW_SYSCTRL->IER = ((CW_SYSCTRL->IER & (~ SYSCTRL_BYPASS_MASK)) | SYSCTRL_BYPASS) & (~RCC_IT); + } +} + +/** + * @brief 获取RCC指定中断状态 + * + * @param RCC_IT ：RCC_IT_HSEFAULT RCC_IT_LSEFAULT + * RCC_IT_HSEFAIL RCC_IT_LSEFAIL + * RCC_IT_LSERDY RCC_IT_LSIRDY + * RCC_IT_PLLRDY RCC_IT_HSERDY + * RCC_IT_HSIRDY + * @return ITStatus : SET RESET + */ +ITStatus RCC_GetITStatus(uint32_t RCC_IT) +{ + assert_param(IS_RCC_GET_IT(RCC_IT)); + return (CW_SYSCTRL->ISR & RCC_IT) ? SET : RESET; +} + + +/** + * @brief 清除RCC指定中断标志 + * + * @param RCC_IT ：RCC_IT_HSEFAULT RCC_IT_LSEFAULT + * RCC_IT_HSEFAIL RCC_IT_LSEFAIL + * RCC_IT_LSERDY RCC_IT_LSIRDY + * RCC_IT_PLLRDY RCC_IT_HSERDY + * RCC_IT_HSIRDY + */ +void RCC_ClearITPendingBit(uint32_t RCC_IT) +{ + assert_param(IS_RCC_GET_IT(RCC_IT)); + CW_SYSCTRL->ICR &= (~RCC_IT); +} + +/** + * @brief 获取指定时钟源稳定标志 + * + * @param RCC_STABLEFLAG ：RCC_FLAG_HSISTABLE RCC_FLAG_HSESTABLE + * RCC_FLAG_PLLSTABLE RCC_FLAG_LSESTABLE + * RCC_FLAG_LSISTABLE + * @return FlagStatus ：SET RESET + */ +FlagStatus RCC_GetStableFlag(uint32_t RCC_STABLEFLAG) +{ + assert_param(IS_RCC_STABLEFLAG(RCC_STABLEFLAG)); + return (((CW_SYSCTRL->ISR) & RCC_STABLEFLAG) ? SET : RESET); +} + +/** + * @brief 获取所有时钟源稳定标志 + * + * @return uint32_t ：返回ISR寄存器内容 + */ +uint32_t RCC_GetAllStableFlag(void) +{ + return (CW_SYSCTRL->ISR); +} + + +/** + * @brief AHB外设时钟设置 + * + * @param Periph ：RCC_AHB_PERIPH_GPIOF RCC_AHB_PERIPH_GPIOC + * RCC_AHB_PERIPH_GPIOB RCC_AHB_PERIPH_GPIOA + * RCC_AHB_PERIPH_CRC RCC_AHB_PERIPH_FLASH + * RCC_AHB_PERIPH_DMA + * @param NewState ENABLE DISABLE + */ +void RCC_AHBPeriphClk_Enable(uint32_t Periph, FunctionalState NewState) +{ + assert_param(IS_RCC_AHB_PERIPH(Periph)); + if (NewState != DISABLE) + { + CW_SYSCTRL->AHBEN |= Periph; + } + else + { + CW_SYSCTRL->AHBEN &= (~Periph); + } +} + +/** + * @brief APB外设时钟设置1 + * + * @param Periph ： RCC_APB1_PERIPH_I2C2 RCC_APB1_PERIPH_I2C1 + * RCC_APB1_PERIPH_UART3 RCC_APB1_PERIPH_UART2 + * RCC_APB1_PERIPH_SPI2 RCC_APB1_PERIPH_IWDT + * RCC_APB1_PERIPH_WWDT RCC_APB1_PERIPH_RTC + * RCC_APB1_PERIPH_GTIM2 RCC_APB1_PERIPH_GTIM1 + * @param NewState ENABLE DISABLE + */ +void RCC_APBPeriphClk_Enable1(uint32_t Periph, FunctionalState NewState) +{ + assert_param(IS_RCC_APB1_PERIPH(Periph)); + if (NewState != DISABLE) + { + CW_SYSCTRL->APBEN1 |= Periph; + } + else + { + CW_SYSCTRL->APBEN1 &= (~Periph); + } +} + +/** + * @brief APB外设时钟设置2 + * + * @param Periph ： RCC_APB2_PERIPH_AWT RCC_APB2_PERIPH_BTIM + * RCC_APB2_PERIPH_GTIM4 RCC_APB2_PERIPH_GTIM3 + * RCC_APB2_PERIPH_UART1 RCC_APB2_PERIPH_SPI1 + * RCC_APB2_PERIPH_ATIM RCC_APB2_PERIPH_VC + * RCC_APB2_PERIPH_ADC + * @param NewState : ENABLE DISABLE + */ +void RCC_APBPeriphClk_Enable2(uint32_t Periph, FunctionalState NewState) +{ + assert_param(IS_RCC_APB2_PERIPH(Periph)); + if (NewState != DISABLE) + { + CW_SYSCTRL->APBEN2 |= Periph; + } + else + { + CW_SYSCTRL->APBEN2 &= (~Periph); + } +} + +/** + * @brief AHB外设复位设置 + * + * @param Periph ：RCC_AHB_PERIPH_GPIOF RCC_AHB_PERIPH_GPIOC + * RCC_AHB_PERIPH_GPIOB RCC_AHB_PERIPH_GPIOA + * RCC_AHB_PERIPH_CRC RCC_AHB_PERIPH_FLASH + * RCC_AHB_PERIPH_DMA + * @param NewState : ENABLE DISABLE + */ +void RCC_AHBPeriphReset(uint32_t Periph, FunctionalState NewState) +{ + assert_param(IS_RCC_AHB_PERIPH(Periph)); + if (NewState != DISABLE) + { + CW_SYSCTRL->AHBRST |= Periph; + } + else + { + CW_SYSCTRL->AHBRST &= (~Periph); + } +} + +/** + * @brief APB外设复位设置1 + * + * @param Periph ： RCC_APB1_PERIPH_I2C2 RCC_APB1_PERIPH_I2C1 + * RCC_APB1_PERIPH_UART3 RCC_APB1_PERIPH_UART2 + * RCC_APB1_PERIPH_SPI2 RCC_APB1_PERIPH_IWDT + * RCC_APB1_PERIPH_WWDT RCC_APB1_PERIPH_RTC + * RCC_APB1_PERIPH_GTIM2 RCC_APB1_PERIPH_GTIM1 + * @param NewState : ENABLE DISABLE + */ +void RCC_APBPeriphReset1(uint32_t Periph, FunctionalState NewState) +{ + assert_param(IS_RCC_APB1_PERIPH(Periph)); + if (NewState != DISABLE) + { + CW_SYSCTRL->APBRST1 |= Periph; + } + else + { + CW_SYSCTRL->APBRST1 &= (~Periph); + } +} + +/** + * @brief APB外设复位设置2 + * + * @param Periph ： RCC_APB2_PERIPH_AWT RCC_APB2_PERIPH_BTIM + * RCC_APB2_PERIPH_GTIM4 RCC_APB2_PERIPH_GTIM3 + * RCC_APB2_PERIPH_UART1 RCC_APB2_PERIPH_SPI1 + * RCC_APB2_PERIPH_ATIM RCC_APB2_PERIPH_VC + * RCC_APB2_PERIPH_ADC + * @param NewState : ENABLE DISABLE + */ +void RCC_APBPeriphReset2(uint32_t Periph, FunctionalState NewState) +{ + assert_param(IS_RCC_APB2_PERIPH(Periph)); + if (NewState != DISABLE) + { + CW_SYSCTRL->APBRST2 |= Periph; + } + else + { + CW_SYSCTRL->APBRST2 &= (~Periph); + } +} + +/** + * @brief 获取指定的系统复位标志 + * + * @param RCC_RSTFLAG ：RCC_FLAG_PINRST RCC_FLAG_PORRST + * RCC_FLAG_LVDRST RCC_FLAG_LOCKUPRST + * RCC_FLAG_IWDTRST RCC_FLAG_WWDTRST + * RCC_FLAG_SYSRESETREQRST + * @return FlagStatus SET RESET + */ +FlagStatus RCC_GetRstFlag(uint32_t RCC_RSTFLAG) +{ + assert_param(IS_RCC_RSTFLAG(RCC_RSTFLAG)); + return (((CW_SYSCTRL->RESETFLAG) & RCC_RSTFLAG) ? SET : RESET); +} + +/** + * @brief 获取复位标志寄存器内容 + * + * @return uint32_t + */ +uint32_t RCC_GetAllRstFlag(void) +{ + return (CW_SYSCTRL->RESETFLAG); +} + +/** + * @brief 清除指定或者全部复位标志 + * + * @param RCC_RSTFLAG ：RCC_FLAG_PINRST RCC_FLAG_PORRST + * RCC_FLAG_LVDRST RCC_FLAG_LOCKUPRST + * RCC_FLAG_IWDTRST RCC_FLAG_WWDTRST + * RCC_FLAG_SYSRESETREQRST RCC_FLAG_ALLRST + * @return + */ +void RCC_ClearRstFlag(uint32_t RCC_RSTFLAG) +{ + assert_param(IS_RCC_RSTFLAG(RCC_RSTFLAG)); + CW_SYSCTRL->RESETFLAG &= (~RCC_RSTFLAG); +} + +/** + * @brief 配置HCLK_OUT引脚输出HCLK时钟 + * + */ +void RCC_HCLK_OUT(void) +{ + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOA_Msk; + CW_GPIOA->ANALOG_f.PIN4 = 0U; + CW_GPIOA->DIR_f.PIN4 = 0U; + CW_GPIOA->AFRL_f.AFR4 = 4U; +} + +/** + * @brief 配置PCLK_OUT引脚输出PCLK时钟 + * + */ +void RCC_PCLK_OUT(void) +{ + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOA_Msk; + CW_GPIOA->ANALOG_f.PIN3 = 0U; + CW_GPIOA->DIR_f.PIN3 = 0U; + CW_GPIOA->AFRL_f.AFR3 = 4U; +} + +/** + * @brief 配置HSE_OUT引脚输出HSE时钟 + * + */ +void RCC_HSE_OUT(void) +{ + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOB_Msk; + CW_GPIOB->ANALOG_f.PIN2 = 0U; + CW_GPIOB->DIR_f.PIN2 = 0U; + CW_GPIOB->AFRL_f.AFR2 = 3U; +} + +/** + * @brief 配置HSI_OUT引脚输出HSIOSC时钟 + * + */ +void RCC_HSI_OUT(void) +{ + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOB_Msk; + CW_GPIOB->ANALOG_f.PIN0 = 0U; + CW_GPIOB->DIR_f.PIN0 = 0U; + CW_GPIOB->AFRL_f.AFR0 = 5U; +} + +/** + * @brief 配置LSE_OUT引脚输出LSE时钟 + * + */ +void RCC_LSE_OUT(void) +{ + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOB_Msk; + CW_GPIOB->ANALOG_f.PIN12 = 0U; + CW_GPIOB->DIR_f.PIN12 = 0U; + CW_GPIOB->AFRH_f.AFR12 = 3U; +} + +/** + * @brief 配置LSI_OUT引脚输出LSI时钟 + * + */ +void RCC_LSI_OUT(void) +{ + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOB_Msk; + CW_GPIOB->ANALOG_f.PIN11 = 0U; + CW_GPIOB->DIR_f.PIN11 = 0U; + CW_GPIOB->AFRH_f.AFR11 = 1U; +} +/** + * @brief 配置PLL_OUT引脚输出PLL时钟 + * + */ +void RCC_PLL_OUT(void) +{ + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOC_Msk; + CW_GPIOC->ANALOG_f.PIN13 = 0U; + CW_GPIOC->DIR_f.PIN13 = 0U; + CW_GPIOC->AFRH_f.AFR13 = 1U; +} + +/** + * @brief 配置MCO_OUT引脚输出指定的时钟源及分频比 + * + * @param Source ：RCC_MCO_SRC_NONE RCC_MCO_SRC_HCLK + * RCC_MCO_SRC_PCLK RCC_MCO_SRC_HSI + * RCC_MCO_SRC_LSI RCC_MCO_SRC_HSE + * RCC_MCO_SRC_LSE RCC_MCO_SRC_PLL + * RCC_MCO_SRC_RC150K RCC_MCO_SRC_RC10K + * @param Div ：RCC_MCO_DIV1/2/8/64/128/256/512/1024 + */ +void RCC_MCO_OUT(uint8_t Source, uint8_t Div) +{ + assert_param(IS_RCC_MCO_SRC(Source)); + assert_param(IS_RCC_MCO_DIV(Div)); + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOA_Msk; //Open GPIOA clk + CW_GPIOA->ANALOG &= ~GPIOx_ANALOG_PIN8_Msk; //Digit + CW_GPIOA->AFRH = ((CW_GPIOA->AFRH) & (~(uint32_t)(GPIOx_AFRH_AFR8_Msk))) | (uint32_t)(0x4U << GPIOx_AFRH_AFR8_Pos); + CW_GPIOA->DIR &= ~GPIOx_DIR_PIN8_Msk; //Output + CW_SYSCTRL->MCO = (uint32_t)(Source | Div); +} + +/** + * @brief 配置BTIM3的ITR来源 + * + * @param Source RCC_TIMITR_BTIM1 RCC_TIMITR_BTIM2 + * RCC_TIMITR_GTIM1 RCC_TIMITR_GTIM2 RCC_TIMITR_GTIM3 RCC_TIMITR_GTIM4 + * RCC_TIMITR_ATIM + */ +void RCC_BTIM3ITRSelect(uint32_t Source) +{ + assert_param(IS_RCC_TIMITR_SOURCE(Source)); + CW_SYSCTRL->TIMITR_f.BTIM3ITR = Source; +} + +/** + * @brief 配置BTIM2的ITR来源 + * + * @param Source RCC_TIMITR_BTIM1 RCC_TIMITR_BTIM3 + * RCC_TIMITR_GTIM1 RCC_TIMITR_GTIM2 RCC_TIMITR_GTIM3 RCC_TIMITR_GTIM4 + * RCC_TIMITR_ATIM + */ +void RCC_BTIM2ITRSelect(uint32_t Source) +{ + assert_param(IS_RCC_TIMITR_SOURCE(Source)); + CW_SYSCTRL->TIMITR_f.BTIM2ITR = Source; +} + +/** + * @brief 配置BTIM1的ITR来源 + * + * @param Source RCC_TIMITR_BTIM2 RCC_TIMITR_BTIM3 + * RCC_TIMITR_GTIM1 RCC_TIMITR_GTIM2 RCC_TIMITR_GTIM3 RCC_TIMITR_GTIM4 + * RCC_TIMITR_ATIM + */ +void RCC_BTIM1ITRSelect(uint32_t Source) +{ + assert_param(IS_RCC_TIMITR_SOURCE(Source)); + CW_SYSCTRL->TIMITR_f.BTIM1ITR = Source; +} + +/** + * @brief 配置GTIM1的ITR来源 + * + * @param Source RCC_TIMITR_BTIM1 RCC_TIMITR_BTIM2 RCC_TIMITR_BTIM3 + * RCC_TIMITR_GTIM2 RCC_TIMITR_GTIM3 RCC_TIMITR_GTIM4 + * RCC_TIMITR_ATIM + */ +void RCC_GTIM1ITRSelect(uint32_t Source) +{ + assert_param(IS_RCC_TIMITR_SOURCE(Source)); + CW_SYSCTRL->TIMITR_f.GTIM1ITR = Source; +} + +/** + * @brief 配置GTIM2的ITR来源 + * + * @param Source RCC_TIMITR_BTIM1 RCC_TIMITR_BTIM2 RCC_TIMITR_BTIM3 + * RCC_TIMITR_GTIM1 RCC_TIMITR_GTIM3 RCC_TIMITR_GTIM4 + * RCC_TIMITR_ATIM + */ +void RCC_GTIM2ITRSelect(uint32_t Source) +{ + assert_param(IS_RCC_TIMITR_SOURCE(Source)); + CW_SYSCTRL->TIMITR_f.GTIM2ITR = Source; +} + +/** + * @brief 配置GTIM3的ITR来源 + * + * @param Source RCC_TIMITR_BTIM1 RCC_TIMITR_BTIM2 RCC_TIMITR_BTIM3 + * RCC_TIMITR_GTIM1 RCC_TIMITR_GTIM2 RCC_TIMITR_GTIM4 + * RCC_TIMITR_ATIM + */ +void RCC_GTIM3ITRSelect(uint32_t Source) +{ + assert_param(IS_RCC_TIMITR_SOURCE(Source)); + CW_SYSCTRL->TIMITR_f.GTIM3ITR = Source; +} + +/** + * @brief 配置GTIM4的ITR来源 + * + * @param Source RCC_TIMITR_BTIM1 RCC_TIMITR_BTIM2 RCC_TIMITR_BTIM3 + * RCC_TIMITR_GTIM1 RCC_TIMITR_GTIM2 RCC_TIMITR_GTIM3 + * RCC_TIMITR_ATIM + */ +void RCC_GTIM4ITRSelect(uint32_t Source) +{ + assert_param(IS_RCC_TIMITR_SOURCE(Source)); + CW_SYSCTRL->TIMITR_f.GTIM4ITR = Source; +} + +/** + * @brief 配置ATIM的ITR来源 + * + * @param Source RCC_TIMITR_BTIM1 RCC_TIMITR_BTIM2 RCC_TIMITR_BTIM3 + * RCC_TIMITR_GTIM1 RCC_TIMITR_GTIM2 RCC_TIMITR_GTIM3 + * + */ +void RCC_ATIMITRSelect(uint32_t Source) +{ + assert_param(IS_RCC_TIMITR_SOURCE(Source)); + CW_SYSCTRL->TIMITR_f.ATIMITR = Source; +} + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_rtc.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_rtc.c new file mode 100644 index 0000000..354b7c5 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_rtc.c @@ -0,0 +1,597 @@ +/** + * @file cw32f030_rtc.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-04-29 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_rtc.h" +#include "cw32f030_rcc.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief RTC去初始化 + * + */ +void RTC_DeInit(void) +{ + /* 解锁RTC寄存器的写保护 */ + CW_RTC->KEY_f.KEY = RTC_KEY_WORD1; + CW_RTC->KEY_f.KEY = RTC_KEY_WORD2; + /* 对除RTC_CR0、RTC_CR1、RTC_CR2和RTC_COMPEN外，其他的RTC寄存器赋默认值 */ + CW_RTC->DATE = RTC_DATE_RESET_VALUE; + CW_RTC->TIME = RTC_TIME_RESET_VALUE; + CW_RTC->ALARMA = RTC_ALARMA_RESET_VALUE; + CW_RTC->ALARMB = RTC_ALARMB_RESET_VALUE; + CW_RTC->TAMPDATE = RTC_TAMPDATA_RESET_VALUE; + CW_RTC->TAMPTIME = RTC_TAMPTIME_RESET_VALUE; + CW_RTC->AWTARR = RTC_AWTARR_RESET_VALUE; + CW_RTC->IER = RTC_IER_RESET_VALUE; + CW_RTC->ICR = 0UL; // 清除中断标志位 + /* 使能RTC寄存器的写保护 */ + CW_RTC->KEY_f.KEY = RTC_KEY_WORD1; + CW_RTC->KEY_f.KEY = RTC_KEY_LOCKW; + /* 复位RTC模块，RTC_CR0、RTC_CR1、RTC_CR2和RTC_COMPEN复位为默认值 */ + CW_SYSCTRL->APBRST1_f.RTC = 0; + CW_SYSCTRL->APBRST1_f.RTC = 1; + /* 关闭RTC模块的时钟 */ + CW_SYSCTRL->APBEN1_f.RTC = 0; +} + +/** + * @brief RTC模块初始化 + * + * @param 初始化RTC模块，用户需首先启动启动RTC时钟源！！！自动运行RTC + * + * @return ErrorStatus 返回值为SUCCESS或ERROR + */ +ErrorStatus RTC_Init(RTC_InitTypeDef *RTC_InitStruct) +{ + assert_param(IS_RTC_RTCCLK_SOURCE(RTC_InitStruct->RTC_ClockSource)); + CW_SYSCTRL->APBEN1_f.RTC = 1; // 启动RTC外设时钟，使能RTC模块 + RTC_Cmd(DISABLE); // 停止RTC，保证正确访问RTC寄存器 + RTC_SetClockSource(RTC_InitStruct->RTC_ClockSource); // 设置RTC时钟源, 用户需首先启动RTC时钟源！！！ + if ((RCC_GetAllRstFlag()&SYSCTRL_RESETFLAG_POR_Msk) == RCC_FLAG_PORRST) //如果是上电复位,设置日期与时间,否则仅设置H24标志 + { + RTC_SetDate(&RTC_InitStruct->DateStruct); + RTC_SetTime(&RTC_InitStruct->TimeStruct); + } + else + { + RTC_UNLOCK(); + CW_RTC->CR0_f.H24 = RTC_InitStruct->TimeStruct.H24; + RTC_LOCK(); + } + CW_SYSCTRL->RESETFLAG = 0; // 清除复位标志 + RTC_Cmd(ENABLE); + return SUCCESS; +} + + +void RTC_Cmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + RTC_UNLOCK(); + CW_RTC->CR0_f.START = NewState; + RTC_LOCK(); +} + +/** + * @brief 读取中断RTC状态 + * + * @param RTC_ITState + * @return ITStatus + */ + +ITStatus RTC_GetITState(uint32_t RTC_ITState) +{ + uint32_t RegTmp; + assert_param(IS_RTC_GET_IT(RTC_ITState)); + do + { + RegTmp = CW_RTC->ISR; + } + while (RegTmp != CW_RTC->ISR); + return (RegTmp & RTC_ITState) ? SET : RESET; +} + +/** + * @brief 设置中断使能 + * + * @param RTC_IT + * @param NewState + */ +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) +{ + assert_param(IS_RTC_CONFIG_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + RTC_UNLOCK(); + // CW_RTC->CR1_f.ACCESS = 1; + // while (!CW_RTC->CR1_f.WINDOW); + if (!NewState) + { + CW_RTC->IER &= ~RTC_IT; + } + else + { + CW_RTC->IER |= RTC_IT; + } + // CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +/** + * @brief 清除中断标志 + * + * @param RTC_IT + */ +void RTC_ClearITPendingBit(uint32_t RTC_IT) +{ + assert_param(IS_RTC_CLAER_IT(RTC_IT)); + RTC_UNLOCK(); + // CW_RTC->CR1_f.ACCESS = 1; + // while (!CW_RTC->CR1_f.WINDOW); + CW_RTC->ICR = ~RTC_IT; + // CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +/** + * @brief 设置时间，HOUR、MINIUTE、SECOND必须为BCD方式，用户须保证HOUR、AMPM、H24之间的关联正确性 + * + * @param RTC_TimeStruct + */ +void RTC_SetTime(RTC_TimeTypeDef *RTC_TimeStruct) +{ + assert_param(IS_RTC_SECONDS(RTC_BCDToBin(RTC_TimeStruct->Second))); + assert_param(IS_RTC_MINUTES(RTC_BCDToBin(RTC_TimeStruct->Minute))); + if (RTC_TimeStruct->H24 == RTC_HOUR12) + { + assert_param(IS_RTC_HOUR12(RTC_BCDToBin(RTC_TimeStruct->Hour))); + } + else + { + assert_param(IS_RTC_HOUR24(RTC_BCDToBin(RTC_TimeStruct->Hour))); + } + RTC_UNLOCK(); + CW_RTC->CR0_f.H24 = RTC_TimeStruct->H24; + if (RTC_TimeStruct->H24 == RTC_HOUR12) + { + CW_RTC->TIME = ((uint32_t)(RTC_TimeStruct->AMPM) << 21) | + ((uint32_t)(RTC_TimeStruct->Hour) << 16) | + ((uint32_t)(RTC_TimeStruct->Minute) << 8) | + ((uint32_t)(RTC_TimeStruct->Second)); + } + else + { + CW_RTC->TIME = ((uint32_t)(RTC_TimeStruct->Hour) << 16) | + ((uint32_t)(RTC_TimeStruct->Minute) << 8) | + ((uint32_t)(RTC_TimeStruct->Second)); + } + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +/** + * @brief + * 设置日期，DAY、MONTH、YEAR必须为BCD方式，星期为0~6，代表星期日，星期一至星期六 + * @param RTC_DateStruct + */ +void RTC_SetDate(RTC_DateTypeDef *RTC_DateStruct) +{ + assert_param(IS_RTC_YEAR(RTC_BCDToBin(RTC_DateStruct->Year))); + assert_param(IS_RTC_MONTH(RTC_BCDToBin(RTC_DateStruct->Month))); + assert_param(IS_RTC_DAY(RTC_BCDToBin(RTC_DateStruct->Day))); + assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->Week)); + RTC_UNLOCK(); + CW_RTC->DATE = ((uint32_t)(RTC_DateStruct->Week) << 24) | + ((uint32_t)(RTC_DateStruct->Year) << 16) | + ((uint32_t)(RTC_DateStruct->Month) << 8) | + ((uint32_t)(RTC_DateStruct->Day)); + RTC_LOCK(); +} + +/** + * @brief 获取当前时间，BCD格式 + * + * @param RTC_TimeStruct + */ +void RTC_GetTime(RTC_TimeTypeDef *RTC_TimeStruct) +{ + uint32_t RegTmp = 0; + RTC_TimeStruct->H24 = CW_RTC->CR0_f.H24; // 读CR0是否需要连读两次，待硬件检测 + RegTmp = CW_RTC->TIME; + while (RegTmp != CW_RTC->TIME) + { + RegTmp = CW_RTC->TIME; // 连续两次读取的内容一致，认为读取成功 + } + RTC_TimeStruct->Hour = (uint8_t)((RegTmp & RTC_TIME_HOUR_Msk) >> 16); + RTC_TimeStruct->Minute = (uint8_t)((RegTmp & RTC_TIME_MINUTE_Msk) >> 8); + RTC_TimeStruct->Second = (uint8_t)(RegTmp & RTC_TIME_SECOND_Msk); + if (RTC_TimeStruct->H24 == RTC_HOUR12) + { + RTC_TimeStruct->AMPM = RTC_TimeStruct->Hour >> 5; + RTC_TimeStruct->Hour &= 0x1f; + } +} + + +/** + * @brief 获取用当前日期，BCD格式 + * + * @param RTC_Date + */ +void RTC_GetDate(RTC_DateTypeDef *RTC_Date) +{ + uint32_t RegTmp = 0; + RegTmp = CW_RTC->DATE; + while (RegTmp != CW_RTC->DATE) + { + RegTmp = CW_RTC->DATE; // 连续两次读取的内容一致，认为读取成功 + } + RTC_Date->Day = (uint8_t)(RegTmp & RTC_DATE_DAY_Msk); + RTC_Date->Month = (uint8_t)((RegTmp & RTC_DATE_MONTH_Msk) >> 8); + RTC_Date->Year = (uint8_t)((RegTmp & RTC_DATE_YEAR_Msk) >> 16); + RTC_Date->Week = (uint8_t)((RegTmp & RTC_DATE_WEEK_Msk) >> 24); +} + +/** + * @brief 设置闹钟，BCD格式。 || + * RTC_AlarmMask：bit32~24:WeeksMask，bit23:HourMask，bit15:MinuteMask，bit7:SecondMask || + * 闹钟时间，HOUR、MINIUTE、SECOND必须为BCD方式，用户须保证HOUR、AMPM、H24之间的关联正确性 + * + * @param RTC_Alarm + * @param RTC_AlarmStruct + */ +void RTC_SetAlarm(uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + uint32_t RegTmp = 0; + assert_param(IS_RTC_ALARM(RTC_Alarm)); + assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); + assert_param(IS_RTC_SECONDS(RTC_BCDToBin(RTC_AlarmStruct->RTC_AlarmTime.Second))); + assert_param(IS_RTC_MINUTES(RTC_BCDToBin(RTC_AlarmStruct->RTC_AlarmTime.Minute))); + if (RTC_AlarmStruct->RTC_AlarmTime.H24 == RTC_HOUR12) + { + assert_param(IS_RTC_HOUR12(RTC_BCDToBin(RTC_AlarmStruct->RTC_AlarmTime.Hour))); + } + else + { + assert_param(IS_RTC_HOUR24(RTC_BCDToBin(RTC_AlarmStruct->RTC_AlarmTime.Hour))); + } + RegTmp = RTC_AlarmStruct->RTC_AlarmMask | + (uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.Hour << 16) | + (uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.Minute << 8) | + (uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.Second); + RTC_UNLOCK(); + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + if (RTC_Alarm == RTC_Alarm_A) + { + CW_RTC->ALARMA = RegTmp; + } + else + { + CW_RTC->ALARMB = RegTmp; + } + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +/** + * @brief 获取闹钟的设置，时间为BCD格式。 + * + * @param RTC_Alarm + * @param RTC_AlarmStruct + */ +void RTC_GetAlarm(uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + uint32_t RegTmp = 0; + assert_param(IS_RTC_ALARM(RTC_Alarm)); + if (RTC_Alarm == RTC_Alarm_A) + { + RegTmp = CW_RTC->ALARMA; + while (RegTmp != CW_RTC->ALARMA) + { + RegTmp = CW_RTC->ALARMA; + } + } + else + { + RegTmp = CW_RTC->ALARMB; + while (RegTmp != CW_RTC->ALARMB) + { + RegTmp = CW_RTC->ALARMB; + } + } + RTC_AlarmStruct->RTC_AlarmMask = RegTmp & RTC_AlarmMask_All; + RTC_AlarmStruct->RTC_AlarmTime.H24 = CW_RTC->CR0_f.H24; // 读CR0是否需要连读两次，待硬件检测 + RTC_AlarmStruct->RTC_AlarmTime.Hour = (uint8_t)((RegTmp & RTC_TIME_HOUR_Msk) >> 16); + RTC_AlarmStruct->RTC_AlarmTime.Minute = (uint8_t)((RegTmp & RTC_TIME_MINUTE_Msk) >> 8); + RTC_AlarmStruct->RTC_AlarmTime.Second = (uint8_t)(RegTmp & RTC_TIME_SECOND_Msk); + if (RTC_AlarmStruct->RTC_AlarmTime.H24 == RTC_HOUR12) + { + RTC_AlarmStruct->RTC_AlarmTime.AMPM = RTC_AlarmStruct->RTC_AlarmTime.Hour >> 5; + RTC_AlarmStruct->RTC_AlarmTime.Hour &= 0x1f; + } +} + +void RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) +{ + assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + RTC_UNLOCK(); + if (IS_RTC_START()) // 如果RTC正在运行，则使用WINDOWS、ACCESS访问 + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + if (RTC_Alarm == RTC_Alarm_A) + { + CW_RTC->CR2_f.ALARMAEN = NewState; + } + else + { + CW_RTC->CR2_f.ALARMBEN = NewState; + } + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +void RTC_TamperTriggerConfig(uint32_t RTC_TamperTrigger) +{ + assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); + RTC_UNLOCK(); + if (IS_RTC_START()) // 如果RTC正在运行，则使用WINDOWS、ACCESS访问 + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + CW_RTC->CR2_f.TAMPEDGE = RTC_TamperTrigger; + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +void RTC_TamperCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + RTC_UNLOCK(); + if (IS_RTC_START()) // 如果RTC正在运行，则使用WINDOWS、ACCESS访问 + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + CW_RTC->CR2_f.TAMPEN = NewState; + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +void RTC_GetTamperDate(RTC_DateTypeDef *RTC_Date) +{ + uint32_t RegTmp = 0; + do + { + RegTmp = CW_RTC->TAMPDATE; + } + while (RegTmp != CW_RTC->TAMPDATE); + RTC_Date->Week = (uint8_t)((RegTmp & RTC_TAMPDATE_WEEK_Msk) >> 13); + RTC_Date->Month = (uint8_t)((RegTmp & RTC_TAMPDATE_MONTH_Msk) >> 8); + RTC_Date->Day = (uint8_t)(RegTmp & RTC_TAMPDATE_DAY_Msk); +} + +void RTC_GetTamperTime(RTC_TimeTypeDef *RTC_TimeStruct) +{ + uint32_t RegTmp = 0; + do + { + RegTmp = CW_RTC->TAMPTIME; + } + while (RegTmp != CW_RTC->TAMPTIME); // 连续两次读取的内容一致，认为读取成功 + RTC_TimeStruct->Second = (uint8_t)((RegTmp & RTC_TAMPTIME_SECOND_Msk) >> 16); + RTC_TimeStruct->Minute = (uint8_t)((RegTmp & RTC_TAMPTIME_MINUTE_Msk) >> 8); + RTC_TimeStruct->Hour = (uint8_t)(RegTmp & RTC_TAMPTIME_HOUR_Msk); + RTC_TimeStruct->H24 = CW_RTC->CR0_f.H24; // 读CR0是否需要连读两次，待硬件检测 + if (RTC_TimeStruct->H24 == RTC_HOUR12) + { + RTC_TimeStruct->AMPM = RTC_TimeStruct->Hour >> 5; + RTC_TimeStruct->Hour &= 0x1f; + } +} + + +/** + * @brief 设置RTC的OUTPUT的信号源 + * + * @param RTC_Output + */ +void RTC_OutputConfig(uint8_t RTC_Output) +{ + assert_param(IS_RTC_RTCOUT_SOURCE(RTC_Output)); + RTC_UNLOCK(); + if (IS_RTC_START()) // 如果RTC正在运行，则使用WINDOWS、ACCESS访问 + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + CW_RTC->CR2_f.RTCOUT = RTC_Output; + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +/** + * @brief RTC的自动唤醒定时器设置 + * + * @param RCT_AWTStruct + */ +void RTC_AWTConfig(RTC_AWTTypeDef *RCT_AWTStruct) +{ + assert_param(IS_RTC_AWTTIMER_SOURCE(RCT_AWTStruct->AWT_ClockSource)); + RTC_UNLOCK(); + if (IS_RTC_START()) // 如果RTC正在运行，则使用WINDOWS、ACCESS访问 + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + CW_RTC->CR2_f.AWTSRC = RCT_AWTStruct->AWT_ClockSource; + CW_RTC->AWTARR = (uint32_t)RCT_AWTStruct->AWT_ARRValue; + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +/** + * @brief 使能或禁止AWT功能 + * + * @param NewState + */ +void RTC_AWTCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + RTC_UNLOCK(); + if (IS_RTC_START()) // 如果RTC正在运行，则使用WINDOWS、ACCESS访问 + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + CW_RTC->CR2_f.AWTEN = NewState; + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +/** + * @brief + * + * @param Period + */ +void RTC_SetInterval(uint8_t Period) +{ + assert_param(IS_RTC_INTERVAL_PERIOD(Period)); + RTC_UNLOCK(); + if (IS_RTC_START()) // 如果RTC正在运行，则使用WINDOWS、ACCESS访问 + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + CW_RTC->CR0_f.INTERVAL = Period; + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +/** + * @brief 设置RTC的计时时钟来源 + * + * @param RTC_ClockSource ：只能是RTC_RTCCLK_FROM_LSE、LSI、HSE有效值，字操作，影响WINDOW、ACCESS位 + * 用户须先启动RTC时钟源 + */ +void RTC_SetClockSource(uint32_t RTC_ClockSource) +{ + assert_param(IS_RTC_RTCCLK_SOURCE(RTC_ClockSource)); + RTC_UNLOCK(); /* 解除RTC寄存器的写保护 */ + // CW_RTC->CR1_f.SOURCE = RTC_ClockSource; // 设置RTC时钟源 + CW_RTC->CR1 = RTC_ClockSource; // 设置RTC时钟源,同时将WINDOWS、ACCESS位清零 + RTC_LOCK(); +} + +/** + * @brief 设置校准时钟参数：FREQ、STEP、SIGN、COMPEN || + * 注:RTC_CalibStruct->Step 为 0 时，要保证 RTC_CalibStruct->RefClock 大于 4MHz || + * RTC_CalibStruct->Step 为 1 时，要保证 RTC_CalibStruct->RefClock 大于 12MHz || + * RTC_CalibStruct->Step 为 2 时，要保证 RTC_CalibStruct->RefClock 大于 24MHz + * + * @param RTC_CalibStruct + */ +void RTC_CalibrationConfig(RTC_CalibTypeDef *RTC_CalibStruct) +{ + assert_param(IS_RTC_COMPEN_FREQ(RTC_CalibStruct->Freq)); + assert_param(IS_RTC_COMPEN_STEP(RTC_CalibStruct->Step)); + assert_param(IS_RTC_COMPEN_SIGN(RTC_CalibStruct->Sign)); + assert_param(IS_RTC_COMPEN_VALUE(RTC_CalibStruct->CompensationValue)); + RTC_UNLOCK(); + if (IS_RTC_START()) // 如果RTC正在运行，则使用WINDOWS、ACCESS访问 + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + CW_RTC->COMPEN = (RTC_CalibStruct->Freq << 16) | + (RTC_CalibStruct->Sign << 14) | + (RTC_CalibStruct->Step << 12) | + RTC_CalibStruct->CompensationValue; + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +void RTC_CalibrationCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + RTC_UNLOCK(); + if (IS_RTC_START()) // 如果RTC正在运行，则使用WINDOWS、ACCESS访问 + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + CW_RTC->COMPEN_f.EN = NewState; + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +/** + * @brief Convert a 2 digit decimal to BCD format. + * @param Value Byte to be converted + * @retval Converted byte + */ +uint8_t RTC_BinToBCD(uint8_t Value) +{ + uint32_t bcdhigh = 0U; + uint8_t Param = Value; + while (Param >= 10U) + { + bcdhigh++; + Param -= 10U; + } + return ((uint8_t)(bcdhigh << 4U) | Param); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value BCD value to be converted + * @retval Converted byte + */ +uint8_t RTC_BCDToBin(uint8_t Value) +{ + uint32_t tmp; + tmp = (((uint32_t)Value & 0xF0U) >> 4U) * 10U; + return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU)); +} + +/** + * @} + */ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_spi.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_spi.c new file mode 100644 index 0000000..7734ff4 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_spi.c @@ -0,0 +1,426 @@ +/** + * @file cw32f030_spi.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-26 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_spi.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief 通过SPIx发送一个数据(4 ~ 16bit) + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1、CW_SPI2 + * @param Data :待发送的数据 + */ +void SPI_SendData(SPI_TypeDef *SPIx, uint16_t Data) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + SPIx->DR = Data; +} + +/** + * @brief 通过SPIx接收一个数据(4 ~ 16bit) + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1、CW_SPI2 + * @return uint16_t :接收的数据 + */ +uint16_t SPI_ReceiveData(SPI_TypeDef *SPIx) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + return (uint16_t)(SPIx->DR); +} + +/** + * @brief 根据SPI_InitStruct中指定的参数初始化SPIx外设 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1、CW_SPI2 + * @param SPI_InitStruct :指向SPI_InitTypeDef类型结构体的指针 + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_SPEED(SPI_InitStruct->SPI_Speed)); + REGBITS_MODIFY(SPIx->CR1, SPIx_CR1_MODE_Msk | \ + SPIx_CR1_WIDTH_Msk | SPIx_CR1_SSM_Msk | \ + SPIx_CR1_SMP_Msk | SPIx_CR1_LSBF_Msk | \ + SPIx_CR1_BR_Msk | SPIx_CR1_MSTR_Msk | \ + SPIx_CR1_CPOL_Msk | SPIx_CR1_CPHA_Msk \ + , \ + SPI_InitStruct->SPI_Direction | \ + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_NSS | \ + SPI_InitStruct->SPI_Speed | SPI_InitStruct->SPI_FirstBit | \ + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_Mode | \ + SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA); +} + +/** + * @brief 默认值赋值SPI_InitStruct结构体成员 + * + * @param SPI_InitStruct :指向SPI_InitTypeDef类型结构体的指针 + */ +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) +{ + /* SPI_InitStruct members default value */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_Speed = SPI_Speed_Low; +} + +/** + * @brief SPI1去初始化 + * + */ +void SPI1_DeInit(void) +{ + CW_SYSCTRL->APBRST2_f.SPI1 = 0; + CW_SYSCTRL->APBRST2_f.SPI1 = 1; +} + +/** + * @brief SPI2去初始化 + * + */ +void SPI2_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.SPI2 = 0; + CW_SYSCTRL->APBRST1_f.SPI2 = 1; +} + +/** + * @brief 使能或禁止SPIx + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1、CW_SPI2 + * @param NewState :ENABLE or DISABLE + */ +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + SPIx->CR1_f.EN = NewState; +} + +/** + * @brief 使能/失能SPIx中断 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1、CW_SPI2 + * @param SPI_IT :中断源 + * 参数可以是: + * @arg SPI_IT_MODF: 模式错误中断 + * @arg SPI_IT_SSERR: 从机模式下的从机选择错误中断 + * @arg SPI_IT_OV: 接收缓冲上溢错误中断 + * @arg SPI_IT_UD: 从机模式下发送缓冲下溢错误中断 + * @arg SPI_IT_SSR: 从机选择输入上升沿中断 + * @arg SPI_IT_SSF: 从机选择输入下降沿中断 + * @arg SPI_IT_RXNE: 接收缓冲非空中断 + * @arg SPI_IT_TXE: 发送缓冲空中断 + * @param NewState :ENABLE or DISABLE + */ +void SPI_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_IT, FunctionalState NewState) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_IT(SPI_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + SPIx->IER |= SPI_IT; + } + else + { + SPIx->IER &= ~SPI_IT; + } +} + +/** + * @brief 获取SPIx中断标志位 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1、CW_SPI2 + * @param SPI_IT :中断源 + * 参数可以是: + * @arg SPI_IT_MODF: 模式错误中断 + * @arg SPI_IT_SSERR: 从机模式下的从机选择错误中断 + * @arg SPI_IT_OV: 接收缓冲上溢错误中断 + * @arg SPI_IT_UD: 从机模式下发送缓冲下溢错误中断 + * @arg SPI_IT_SSR: 从机选择输入上升沿中断 + * @arg SPI_IT_SSF: 从机选择输入下降沿中断 + * @arg SPI_IT_RXNE: 接收缓冲非空中断 + * @arg SPI_IT_TXE: 发送缓冲空中断 + * @return ITStatus :SPI_IT当前状态 (SET or RESET) + */ +ITStatus SPI_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_IT) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_IT(SPI_IT)); + return ((SPIx->ISR & SPI_IT) ? SET : RESET); +} + +/** + * @brief 清除SPIx中断标志位 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1、CW_SPI2 + * @param SPI_IT :中断源 + * 参数可以是: + * @arg SPI_IT_MODF: 模式错误中断 + * @arg SPI_IT_SSERR: 从机模式下的从机选择错误中断 + * @arg SPI_IT_OV: 接收缓冲上溢错误中断 + * @arg SPI_IT_UD: 从机模式下发送缓冲下溢错误中断 + * @arg SPI_IT_SSR: 从机选择输入上升沿中断 + * @arg SPI_IT_SSF: 从机选择输入下降沿中断 + * @arg SPI_IT_RXNE: 接收缓冲非空中断 + * @note + * -TXE中断标志位只能通过写SPIx_DR寄存器来清除 + */ +void SPI_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_IT) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CLEAR_IT(SPI_IT)); + SPIx->ICR &= ~SPI_IT; +} + +/** + * @brief 获取SPIx标志位 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1、CW_SPI2 + * @param SPI_FLAG :标志位 + * 参数可以是: + * @arg SPI_FLAG_SSLVL: 从机选择信号状态 + * @arg SPI_FLAG_BUSY: 总线忙标志 + * @arg SPI_FLAG_MODF: 模式错误标志 + * @arg SPI_FLAG_SSERR: 从机模式下的从机选择错误标志 + * @arg SPI_FLAG_OV: 接收缓冲上溢错误中断 + * @arg SPI_FLAG_UD: 从机模式下发送缓冲下溢错误标志 + * @arg SPI_FLAG_SSR: 从机选择输入上升沿标志 + * @arg SPI_FLAG_SSF: 从机选择输入下降沿标志 + * @arg SPI_FLAG_RXNE: 接收缓冲非空标志 + * @arg SPI_FLAG_TXE: 发送缓冲空标志 + * @return FlagStatus :SPI_FLAG当前状态 (SET or RESET) + */ +FlagStatus SPI_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_FLAG) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_FLAG(SPI_FLAG)); + return ((SPIx->ISR & SPI_FLAG) ? SET : RESET); +} + +/** + * @brief 清除SPIx标志位 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1、CW_SPI2 + * @param SPI_FLAG :标志位 + * 参数可以是: + * @arg SPI_FLAG_MODF: 模式错误标志 + * @arg SPI_FLAG_SSERR: 从机模式下的从机选择错误标志 + * @arg SPI_FLAG_OV: 接收缓冲上溢错误中断 + * @arg SPI_FLAG_UD: 从机模式下发送缓冲下溢错误标志 + * @arg SPI_FLAG_SSR: 从机选择输入上升沿标志 + * @arg SPI_FLAG_SSF: 从机选择输入下降沿标志 + * @arg SPI_FLAG_RXNE: 接收缓冲非空标志 + * @note + * -SSLVL、BUSY标志位由硬件自动设置和清除 + * -TXE标志位只能通过写SPIx_DR寄存器来清除 + * -RXNE标志位也可以通过读SPIx_DR寄存器来清除 + * @return FlagStatus :SPI_FLAG当前状态 (SET or RESET) + */ +void SPI_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_FLAG) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CLEAR_FLAG(SPI_FLAG)); + SPIx->ICR &= ~SPI_FLAG; +} + +/** + * @brief 单线半双工数据传输方向配置 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1、CW_SPI2 + * @param SPI_Direction :发送/接收 + * 参数可以是： + * @arg SPI_Direction_Tx: 发送 + * @arg SPI_Direction_Rx: 接收 + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint8_t SPI_Direction) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + SPIx->CR2 = SPI_Direction; +} + +/** + * @brief 使能/失能SPIx DMA + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1、CW_SPI2 + * @param SPI_DMAReq :DMA请求 + * 参数可以是： + * @arg SPI_DMAReq_Tx: DMA发送请求 + * @arg SPI_DMAReq_Rx: DMA接收请求 + * @param NewState :ENABLE or DISABLE + */ +void SPI_DMACmd(SPI_TypeDef *SPIx, uint32_t SPI_DMAReq, FunctionalState NewState) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DMAREQ(SPI_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + SPIx->CR1 |= SPI_DMAReq; + } + else + { + SPIx->CR1 &= ~SPI_DMAReq; + } +} + +/** + * @brief 软件内部配置NSS + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1、CW_SPI2 + * @param SPI_NSSInternalSoft :NSS状态 + * 参数可以是： + * @arg SPI_NSSInternalSoft_Set: Set NSS + * @arg SPI_NSSInternalSoft_Reset: Reset NSS + * @note + * -SPIx_CR1.SSM = 1时有效，即软件NSS(SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) + * -主机时：0 - CS输出低 1 - CS输出高 + * -从机时：0 - 本机被选中 1 - 本机未被选中 + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint8_t SPI_NSSInternalSoft) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + SPIx->SSI = SPI_NSSInternalSoft; +} + +/** + * @brief 设置数据帧的位宽 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1、CW_SPI2 + * @param SPI_DataSize :数据帧宽度 + * 参数可以是： + * @arg SPI_DataSize_4b + * @arg SPI_DataSize_5b + * @arg SPI_DataSize_6b + * @arg SPI_DataSize_7b + * @arg SPI_DataSize_8b + * @arg SPI_DataSize_9b + * @arg SPI_DataSize_10b + * @arg SPI_DataSize_11b + * @arg SPI_DataSize_12b + * @arg SPI_DataSize_13b + * @arg SPI_DataSize_14b + * @arg SPI_DataSize_15b + * @arg SPI_DataSize_16b + */ +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + REGBITS_MODIFY(SPIx->CR1, SPIx_CR1_WIDTH_Msk, SPI_DataSize); +} + +/** + * @brief 从模式MISO输出配置 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1、CW_SPI2 + * @param SPI_MISOOutput :MISO输出配置 + * 参数可以是： + * @arg SPI_MISOOutput_HD: 从机被选中时 MISO 为 COMS 输出，未被选中时为高阻输出 + * @arg SPI_MISOOutput_CMOS: MISO 始终为 COMS 输出 + */ +void SPI_MISOOutputConfig(SPI_TypeDef *SPIx, uint8_t SPI_MISOOutput) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_MISOOUTPUT(SPI_MISOOutput)); + SPIx->CR1_f.MISOHD = SPI_MISOOutput; +} + +/** + * @brief 清空发送缓冲区和移位寄存器 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1、CW_SPI2 + */ +void SPI_FlushSendBuff(SPI_TypeDef *SPIx) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + SPIx->ICR_f.FLUSH = 0; +} + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_systick.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_systick.c new file mode 100644 index 0000000..2fc361e --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_systick.c @@ -0,0 +1,164 @@ +/** + * @file cw32f030_systick.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-05-13 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_systick.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +TickFreqTypeDef uwTickFreq = TICK_FREQ_DEFAULT; /* 1KHz */ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __Weak to be overwritten in case of other + * implementation in user file. + * @param system hclk freq. + * @retval HAL status + */ +__WEAK void InitTick(uint32_t HclkFreq) +{ + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (SysTick_Config(HclkFreq / (1000U / uwTickFreq)) > 0U) + { + return ; + } + /* Configure the SysTick IRQ priority */ + if (TICK_INT_PRIORITY < (1UL << __NVIC_PRIO_BITS)) + { + NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY); + uwTickPrio = TICK_INT_PRIORITY; + } + else + { + return ; + } +} + + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __WEAK to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__WEAK uint32_t GetTick(void) +{ + return uwTick; +} + + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note ThiS function is declared as __WEAK to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__WEAK void SysTickDelay(uint32_t Delay) +{ + uint32_t tickstart = GetTick(); + uint32_t wait = Delay; + /* Add a freq to guarantee minimum wait */ + if (wait < MAX_SYSTICK_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + while ((GetTick() - tickstart) < wait) + { + } +} + + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __WEAK to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__WEAK void SuspendTick(void) + +{ + /* Disable SysTick Interrupt */ + REGBITS_CLR(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __WEAK to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__WEAK void ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + REGBITS_SET(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + + +/** + * @brief This function handles System tick timer. + */ +__WEAK void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn */ + uwTick += uwTickFreq; + /* USER CODE END SysTick_IRQn */ +} diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_uart.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_uart.c new file mode 100644 index 0000000..3bb8c63 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_uart.c @@ -0,0 +1,503 @@ +/** + * @file cw32f030_uart.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-26 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_uart.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief 通过USARTx发送一个数据(16bit) + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param Data :待发送的数据 + */ +void USART_SendData(UART_TypeDef *USARTx, uint16_t Data) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA_16BIT(Data)); + USARTx->TDR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief 通过USARTx发送一个数据(8bit) + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param Data :待发送的数据 + */ +void USART_SendData_8bit(UART_TypeDef *USARTx, uint8_t Data) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA_8BIT(Data)); + USARTx->TDR = Data; +} + +/** + * @brief 通过USARTx接收一个数据(16bit) + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @return uint16_t :接收的数据 + */ +uint16_t USART_ReceiveData(UART_TypeDef *USARTx) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + return (uint16_t)(USARTx->RDR & (uint16_t)0x01FF); +} + +/** + * @brief 通过USARTx接收一个数据(8bit) + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @return uint8_t :接收的数据 + */ +uint8_t USART_ReceiveData_8bit(UART_TypeDef *USARTx) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + return (uint8_t)(USARTx->RDR); +} + +/** + * @brief 根据USART_InitStruct中指定的参数初始化UARTx外设 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param USART_InitStruct :指向USART_InitTypeDef类型结构体的指针 + */ +void USART_Init(UART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) +{ + uint16_t integerdivider = 0x00; + uint16_t fractionaldivider = 0x00; + float32_t temp = 0; + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + assert_param(IS_USART_Over(USART_InitStruct->USART_Over)); + assert_param(IS_USART_Source(USART_InitStruct->USART_Source)); + assert_param(IS_USART_UCLKFREQ(USART_InitStruct->USART_UclkFreq)); + assert_param(IS_USART_StartBit(USART_InitStruct->USART_StartBit)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + /* UARTx_CR1 */ + REGBITS_MODIFY(USARTx->CR1, UARTx_CR1_OVER_Msk | UARTx_CR1_START_Msk | \ + UARTx_CR1_STOP_Msk | UARTx_CR1_PARITY_Msk | \ + UARTx_CR1_RXEN_Msk | UARTx_CR1_TXEN_Msk \ + , \ + (uint32_t)USART_InitStruct->USART_Over | \ + USART_InitStruct->USART_StartBit | \ + USART_InitStruct->USART_StopBits | \ + USART_InitStruct->USART_Parity | \ + USART_InitStruct->USART_Mode); + /* UARTx_CR2 */ + REGBITS_MODIFY(USARTx->CR2, UARTx_CR2_SOURCE_Msk | UARTx_CR2_RTSEN_Msk | \ + UARTx_CR2_CTSEN_Msk \ + , \ + (uint32_t)USART_InitStruct->USART_Source | \ + USART_InitStruct->USART_HardwareFlowControl); + /* 波特率设置 */ + if (USART_Over_16 == USART_InitStruct->USART_Over) + { + /* 16倍采样 */ + temp = (float32_t)(USART_InitStruct->USART_UclkFreq) / (16 * (USART_InitStruct->USART_BaudRate)); + integerdivider = (uint16_t)temp; + fractionaldivider = (uint16_t)((temp - integerdivider) * 16 + 0.5); + USARTx->BRRI = (uint16_t)integerdivider; + USARTx->BRRF = (uint16_t)fractionaldivider; + } + else if (USART_Over_8 == USART_InitStruct->USART_Over) + { + /* 8倍采样 */ + integerdivider = (uint16_t)((float32_t)(USART_InitStruct->USART_UclkFreq) / (8 * (USART_InitStruct->USART_BaudRate)) + 0.5); + USARTx->BRRI = (uint16_t)integerdivider; + } + else if (USART_Over_4 == USART_InitStruct->USART_Over) + { + /* 4倍采样 */ + integerdivider = (uint16_t)((float32_t)(USART_InitStruct->USART_UclkFreq) / (4 * (USART_InitStruct->USART_BaudRate)) + 0.5); + USARTx->BRRI = (uint16_t)integerdivider; + } + else + { + /* 专用采样 */ + /* 专用采样仅适合传输时钟源为LSE或者LSI时，进行2400bps、4800bps或9600bps波特率下的UART通信 */ + integerdivider = (uint16_t)((float32_t)(USART_InitStruct->USART_UclkFreq) * 256 / (USART_InitStruct->USART_BaudRate) + 0.5); + USARTx->BRRI = (uint16_t)integerdivider; + } +} + +/** + * @brief 默认值赋值USART_InitStruct结构体成员 + * + * @param USART_InitStruct :指向USART_InitTypeDef类型结构体的指针 + */ +void USART_StructInit(USART_InitTypeDef *USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_Over = USART_Over_16; + USART_InitStruct->USART_Source = USART_Source_PCLK; + USART_InitStruct->USART_StartBit = USART_StartBit_FE; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/** + * @brief USARTx同步模式初始化，CPOL=1、CPHA=1，只能做主机 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param USART_ClockInitStruct :指向USART_ClockInitTypeDef类型结构体的指针 + */ +void USART_ClockInit(UART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); + assert_param(IS_USART_Source(USART_ClockInitStruct->USART_Source)); + REGBITS_MODIFY(USARTx->CR1, UARTx_CR1_SYNC_Msk, (uint32_t)USART_ClockInitStruct->USART_Clock); + REGBITS_MODIFY(USARTx->CR2, UARTx_CR2_SOURCE_Msk, (uint32_t)USART_ClockInitStruct->USART_Source); +} + +/** + * @brief 默认值赋值USART_ClockInitStruct结构体成员 + * + * @param USART_ClockInitStruct :指向USART_ClockInitTypeDef类型结构体的指针 + */ +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_Source = USART_Source_PCLK; +} + +/** + * @brief UART1去初始化 + * + */ +void UART1_DeInit(void) +{ + CW_SYSCTRL->APBRST2_f.UART1 = 0; + CW_SYSCTRL->APBRST2_f.UART1 = 1; +} + +/** + * @brief UART2去初始化 + * + */ +void UART2_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.UART2 = 0; + CW_SYSCTRL->APBRST1_f.UART2 = 1; +} + +/** + * @brief UART3去初始化 + * + */ +void UART3_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.UART3 = 0; + CW_SYSCTRL->APBRST1_f.UART3 = 1; +} + +/** + * @brief 使能/失能USARTx中断 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param USART_IT :中断源 + * 参数可以是: + * @arg USART_IT_CTS: CTS信号变化中断 + * @arg USART_IT_PE: 奇偶校验错误中断 + * @arg USART_IT_FE: 帧结构错误中断 + * @arg USART_IT_RC: 接收完成中断 + * @arg USART_IT_TC: 发送完成中断 + * @arg USART_IT_TXE: 发送缓冲空中断 + * @param NewState :ENABLE or DISABLE + */ +void USART_ITConfig(UART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IT(USART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + NewState ? (USARTx->IER |= USART_IT) : (USARTx->IER &= (uint16_t)~USART_IT); + // if (NewState != DISABLE) + // { + // USARTx->IER |= USART_IT; + // } + // else + // { + // USARTx->IER &= (uint16_t)~USART_IT; + // } +} + +/** + * @brief 获取USARTx中断标志位 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param USART_IT :中断源 + * 参数可以是： + * @arg USART_IT_CTS: CTS信号变化中断 + * @arg USART_IT_PE: 奇偶校验错误中断 + * @arg USART_IT_FE: 帧结构错误中断 + * @arg USART_IT_RC: 接收完成中断 + * @arg USART_IT_TC: 发送完成中断 + * @arg USART_IT_TXE: 发送缓冲器空中断 + * @return ITStatus :USART_IT当前状态 (SET or RESET) + */ +ITStatus USART_GetITStatus(UART_TypeDef *USARTx, uint16_t USART_IT) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IT(USART_IT)); + return (REGBITS_GET(USARTx->ISR, USART_IT) ? SET : RESET); +} + +/** + * @brief 清除USARTx中断标志位 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param USART_IT :中断源 + * 参数可以是： + * @arg USART_IT_CTS: CTS信号变化中断 + * @arg USART_IT_PE: 奇偶校验错误中断 + * @arg USART_IT_FE: 帧结构错误中断 + * @arg USART_IT_RC: 接收完成中断 + * @arg USART_IT_TC: 发送完成中断 + * @note + * -TXE中断标志位只能通过写UARTx_TDR寄存器来清除 + * -RC中断标志位只能软件清除，不能通过读UARTx_RDR寄存器来清除 + */ +void USART_ClearITPendingBit(UART_TypeDef *USARTx, uint16_t USART_IT) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + REGBITS_CLR(USARTx->ICR, USART_IT); +} + +/** + * @brief 获取USARTx标志位 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param USART_FLAG :标志 + * 参数可以是： + * @arg USART_FLAG_TXBUSY: 发送忙标志 + * @arg USART_FLAG_CTSLV: CTS信号电平状态标志 + * @arg USART_FLAG_CTS: CTS信号变化标志 + * @arg USART_FLAG_MATCH: 从机地址匹配标志 + * @arg USART_FLAG_PE: 奇偶校验错误标志 + * @arg USART_FLAG_FE: 帧结构错误标志 + * @arg USART_FLAG_RC: 接收完成标志 + * @arg USART_FLAG_TC: 发送完成标志 + * @arg USART_FLAG_TXE: 发送缓冲器空标志 + * @return FlagStatus :USART_FLAG当前状态 (SET or RESET) + */ +FlagStatus USART_GetFlagStatus(UART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + return (REGBITS_GET(USARTx->ISR, USART_FLAG) ? SET : RESET); +} + +/** + * @brief 清除USARTx标志位 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param USART_FLAG :标志 + * 参数可以是： + * @arg USART_FLAG_CTS: CTS信号变化标志 + * @arg USART_FLAG_PE: 奇偶校验错误标志 + * @arg USART_FLAG_FE: 帧结构错误标志 + * @arg USART_FLAG_RC: 接收完成标志 + * @arg USART_FLAG_TC: 发送完成标志 + * @note + * -TXBUSY、CTSLV、MATCH标志位由硬件自动设置和清除 + * -TXE标志位只能通过写UARTx_TDR寄存器来清除 + * -RC标志位只能软件清除，不能通过读UARTx_RDR寄存器来清除 + */ +void USART_ClearFlag(UART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + REGBITS_CLR(USARTx->ICR, USART_FLAG); +} + +/** + * @brief 使能/失能TXD输出、RXD输入 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param USART_DirectionMode :传输方向 + * 参数可以是： + * @arg USART_Mode_Tx: TXD输出 + * @arg USART_Mode_Rx: RXD输入 + * @param NewState :ENABLE or DISABLE + */ +void USART_DirectionModeCmd(UART_TypeDef *USARTx, uint16_t USART_DirectionMode, FunctionalState NewState) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_MODE(USART_DirectionMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + NewState ? (USARTx->CR1 |= USART_DirectionMode) : (USARTx->CR1 &= (uint16_t)~USART_DirectionMode); + // if (NewState != DISABLE) + // { + // USARTx->CR1 |= USART_DirectionMode; + // } + // else + // { + // USARTx->CR1 &= (uint16_t)~USART_DirectionMode; + // } +} + +/** + * @brief 使能/失能TXD输出信号、RXD输入信号反相 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param USART_InvPin :反相引脚 + * 参数可以是： + * @arg USART_InvPin_Tx: TXD引脚输出信号反相 + * @arg USART_InvPin_Rx: RXD引脚输入信号反相 + * @param NewState :ENABLE or DISABLE + */ +void USART_InvPinCmd(UART_TypeDef *USARTx, uint16_t USART_InvPin, FunctionalState NewState) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_INVERSTION_PIN(USART_InvPin)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + NewState ? (USARTx->CR2 |= USART_InvPin) : (USARTx->CR2 &= (uint16_t)~USART_InvPin); + // if (NewState != DISABLE) + // { + // USARTx->CR2 |= USART_InvPin; + // } + // else + // { + // USARTx->CR2 &= (uint16_t)~USART_InvPin; + // } +} + +/** + * @brief 使能/失能USARTx半双工通信 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param NewState :ENABLE or DISABLE + */ + +void USART_HalfDuplexCmd(UART_TypeDef *USARTx, FunctionalState NewState) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + USARTx->CR2_f.SIGNAL = NewState; +} + +/** + * @brief 使能/失能USARTx DMA + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param USART_DMAReq :DMA请求 + * 参数可以是： + * @arg USART_DMAReq_Tx: DMA发送请求 + * @arg USART_DMAReq_Rx: DMA接收请求 + * @param NewState :ENABLE or DISABLE + */ +void USART_DMACmd(UART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + NewState ? (USARTx->CR2 |= USART_DMAReq) : (USARTx->CR2 &= (uint16_t)~USART_DMAReq); + // if (NewState != DISABLE) + // { + // USARTx->CR2 |= USART_DMAReq; + // } + // else + // { + // USARTx->CR2 &= (uint16_t)~USART_DMAReq; + // } +} + +/** + * @brief USARTx多机通信配置 + * + * @param USARTx :USARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param USART_Address :从机地址 + * @param USART_AddressMsK :从机地址掩码 + * @note + * 主机和从机均需配置为自定义校验 + */ +void USART_SetMultiMode(UART_TypeDef *USARTx, uint8_t USART_Address, uint8_t USART_AddressMsK) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Address)); + assert_param(IS_USART_ADDRESSMSK(USART_AddressMsK)); + REGBITS_SET(USARTx->CR2, UARTx_CR2_ADDREN_Msk); + REGBITS_MODIFY(USARTx->ADDR, UARTx_ADDR_ADDR_Msk, (uint32_t)USART_Address); + REGBITS_MODIFY(USARTx->MASK, UARTx_MASK_MASK_Msk, (uint32_t)USART_AddressMsK); +} + + + + + + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_vc.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_vc.c new file mode 100644 index 0000000..a4a16b0 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_vc.c @@ -0,0 +1,824 @@ +/** + * @file cw32f030_vc.c + * @author WHXY + * @brief + * @version 0.2 + * @date 2021-12-20 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "cw32f030.h" +#include "cw32f030_vc.h" +#include "cw32f030_adc.h" + +/** + ****************************************************************************** + ** \addtogroup VcGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_VALID_CHANNEL(x) ( VcChannel1==(x) || VcChannel2 == (x)) +#define IS_VALID_STAT(x) ( VcCmpResult==(x) || VcIntrResult == (x)) +#define IS_VALID_DIV(x) ( (x) <= 64u ) + +#define IS_VALID_INPUT_P(x) ( (x) <= VcInPCh7 ) + +#define IS_VALID_INPUT_N(x) ( (x) <= AiAdcVref ) + +#define IS_VALID_DLY(x) ( (VcDelay30mv == (x)) ||\ + (VcDelay20mv == (x)) ||\ + (VcDelay10mv == (x)) ||\ + (VcDelayoff == (x)) ) + +#define IS_VALID_BIAS(x) ( (VcRespExtraLow == (x)) ||\ + (VcRespLow == (x)) ||\ + (VcRespMedium == (x)) ||\ + (VcRespHigh == (x)) ) + +#define IS_VALID_CLK(x) ( (x) <= VcFilterPclk ) + +#define IS_VALID_FILTER(x) ( (x) <= VcFilter4095Clk ) + +#define IS_VALID_BLANK(x) ( (x) <= VcBlankAtimCh3 ) + +#define IS_VALID_OUTPUT(x) ( (x) <= VcOutAtimClr ) + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + + +/** + * @brief + * 使能NVIC中VCx中断 + * + * @param enIrqn: + * @arg VC1_IRQn + * @arg VC2_IRQn + * @param intPriority: + * @arg 0 ~ 3 + */ +void VC_EnableNvic(IRQn_Type enIrqn, uint8_t intPriority) +{ + if (intPriority < (1UL << __NVIC_PRIO_BITS)) + { + NVIC_ClearPendingIRQ(enIrqn); + NVIC_EnableIRQ(enIrqn); + NVIC_SetPriority(enIrqn, intPriority); + } +} + +/** + * @brief + * VC通道1中断使能 + * + * @param intPriority: + * @arg 0 ~ 3 + * + * @return + */ +void VC1_EnableIrq(uint8_t intPriority) +{ + VC_EnableNvic(VC1_IRQn, intPriority); + REGBITS_SET(CW_VC1->CR0, VCx_CR0_IE_Msk); +} + +/** + * @brief + * VC通道2中断使能 + * + * @param intPriority: + * @arg 0 ~ 3 + * + * @return + */ +void VC2_EnableIrq(uint8_t intPriority) +{ + VC_EnableNvic(VC2_IRQn, intPriority); + REGBITS_SET(CW_VC2->CR0, VCx_CR0_IE_Msk); +} + +/** + * @brief + * VC通道1中断禁用 + * + * @return + */ +void VC1_DisableIrq(void) +{ + REGBITS_CLR(CW_VC1->CR0, VCx_CR0_IE_Msk); + VC_DisableNvic(VC1_IRQn); +} + +/** + * @brief + * VC通道2中断禁用 + * + * @return + */ +void VC2_DisableIrq(void) +{ + REGBITS_CLR(CW_VC2->CR0, VCx_CR0_IE_Msk); + VC_DisableNvic(VC2_IRQn); +} + +/** + * @brief + * 禁止NVIC中VC中断 + * + * @param enIrqn: + * @arg VC1_IRQn + * @arg VC2_IRQn + * + * @return + */ +void VC_DisableNvic(IRQn_Type enIrqn) +{ + NVIC_ClearPendingIRQ(enIrqn); + NVIC_DisableIRQ(enIrqn); +} + +/** + * @brief + * 获取VC1指定的中断状态 + * + * @param VC_FLAG: + * @arg VC_FLAG_READY + * @arg VC_FLAG_FLTV + * @arg VC_FLAG_INTF + * + * @return FlagStatus: SET or RESET + */ +FlagStatus VC1_GetFlagStatus(uint16_t VC_FLAG) +{ + assert_param(IS_VC_GET_FLAG(VC_FLAG)); + return (REGBITS_GET(CW_VC1->SR, VC_FLAG) ? SET : RESET); +} + +/** + * @brief + * 获取VC2指定的中断状态 + * + * @param VC_FLAG: + * @arg VC_FLAG_READY + * @arg VC_FLAG_FLTV + * @arg VC_FLAG_INTF + * + * @return FlagStatus: SET or RESET + */ +FlagStatus VC2_GetFlagStatus(uint16_t VC_FLAG) +{ + assert_param(IS_VC_GET_FLAG(VC_FLAG)); + return (REGBITS_GET(CW_VC2->SR, VC_FLAG) ? SET : RESET); +} + +/** + * @brief + * 清除VC1中断标志 + * + * @param + * + * @return + */ +void VC1_ClearIrq(void) +{ + REGBITS_CLR(CW_VC1->SR, VCx_SR_INTF_Msk); +} + +/** + * @brief + * 清除VC2中断标志 + * + * @param + * + * @return + */ +void VC2_ClearIrq(void) +{ + REGBITS_CLR(CW_VC2->SR, VCx_SR_INTF_Msk); +} + +/** + * @brief + * VC1/VC2模块DIV参考电压初始化 + * + * @param VC_DivStruct + * + * @return + */ +void VC1VC2_DIVInit(VC_DivTypeDef *VC_DivStruct) +{ + //ASSERT(NULL != VC_DivStruct); + assert_param(IS_VC_DIV_EN(VC_DivStruct->VC_DivEn)); + assert_param(IS_VC_DIV_VREF(VC_DivStruct->VC_DivVref)); + REGBITS_MODIFY(CW_VC1->DIV, VCx_DIV_EN_Msk | VCx_DIV_VIN_Msk, \ + VC_DivStruct->VC_DivEn | VC_DivStruct->VC_DivVref); + REGBITS_MODIFY(CW_VC2->DIV, VCx_DIV_EN_Msk | VCx_DIV_VIN_Msk, \ + VC_DivStruct->VC_DivEn | VC_DivStruct->VC_DivVref); + if (VC_DivStruct->VC_DivValue < 0x40) + { + CW_VC1->DIV_f.DIV = VC_DivStruct->VC_DivValue; + CW_VC2->DIV_f.DIV = VC_DivStruct->VC_DivValue; + } + else + { + } +} + +/** + * @brief + * VC1/VC2模块DIV参考电压去初始化 + * + * @param + * + * @return + */ +void VC1VC2_DIVDeInit(void) +{ + CW_VC1->DIV = 0x0u; + CW_VC2->DIV = 0x0u; +} + +/** + * @brief + * VC1/VC2模块VCx负端输入信号初始化 + * + * @param VC_InitStruct + * + * @return + */ +void VC1VC2_INNInit(VC_InitTypeDef *VC_InitStruct) +{ + //ASSERT(NULL != VC_InitStruct); + assert_param(IS_VC_INPUT_N(VC_InitStruct->VC_InputN)); + switch (VC_InitStruct->VC_InputN) + { + case VC_InputN_Ts: + //VCx负端输入信号为温度传感器 + //打开ADC时钟 + REGBITS_SET(CW_SYSCTRL->APBEN2, SYSCTRL_APBEN2_ADC_Msk); + REGBITS_SET(CW_ADC->CR0, ADC_CR0_TSEN_Msk | ADC_CR0_BGREN_Msk); + break; + case VC_InputN_Bgr1P2: + //VCx负端输入信号为BGR 1.2V + //打开ADC时钟 + REGBITS_SET(CW_SYSCTRL->APBEN2, SYSCTRL_APBEN2_ADC_Msk); + REGBITS_SET(CW_ADC->CR0, ADC_CR0_BGREN_Msk); + break; + case VC_InputN_AdcVref: + //VCx负端输入信号为ADC VREF + //打开ADC时钟 + REGBITS_SET(CW_SYSCTRL->APBEN2, SYSCTRL_APBEN2_ADC_Msk); + ADC_Enable(); + break; + default: + break; + } +} + +/** + * @brief + * VC通道1初始化 + * + * @param VC_InitStruct + * + * @return + */ +void VC1_ChannelInit(VC_InitTypeDef *VC_InitStruct) +{ + //ASSERT(NULL != VC_InitStruct); + assert_param(IS_VC_INPUT_P(VC_InitStruct->VC_InputP)); + assert_param(IS_VC_INPUT_N(VC_InitStruct->VC_InputN)); + assert_param(IS_VC_HYS(VC_InitStruct->VC_Hys)); + assert_param(IS_VC_RESP(VC_InitStruct->VC_Resp)); + assert_param(IS_VC_FILTER(VC_InitStruct->VC_FilterEn)); + assert_param(IS_VC_FLT_CLK(VC_InitStruct->VC_FilterClk)); + assert_param(IS_VC_FLT_TIME(VC_InitStruct->VC_FilterTime)); + assert_param(IS_VC_WINDOW(VC_InitStruct->VC_Window)); + assert_param(IS_VC_POLARITY(VC_InitStruct->VC_Polarity)); + REGBITS_MODIFY(CW_VC1->CR0, \ + VCx_CR0_INN_Msk | VCx_CR0_INP_Msk | \ + VCx_CR0_WINDOW_Msk | VCx_CR0_POL_Msk | \ + VCx_CR0_HYS_Msk | VCx_CR0_RESP_Msk, \ + VC_InitStruct->VC_InputN | \ + VC_InitStruct->VC_InputP | \ + VC_InitStruct->VC_Window | \ + VC_InitStruct->VC_Polarity | \ + VC_InitStruct->VC_Hys | \ + VC_InitStruct->VC_Resp); + REGBITS_MODIFY(CW_VC1->CR1, \ + VCx_CR1_FLTCLK_Msk | VCx_CR1_FLTTIME_Msk | \ + VCx_CR1_FLTEN_Msk, \ + VC_InitStruct->VC_FilterClk | \ + VC_InitStruct->VC_FilterTime | \ + VC_InitStruct->VC_FilterEn); + //VCx负端输入信号初始化 + VC1VC2_INNInit(VC_InitStruct); +} + +/** + * @brief + * VC通道2初始化 + * + * @param VC_InitStruct + * + * @return + */ +void VC2_ChannelInit(VC_InitTypeDef *VC_InitStruct) +{ + //ASSERT(NULL != VC_InitStruct); + assert_param(IS_VC_INPUT_P(VC_InitStruct->VC_InputP)); + assert_param(IS_VC_INPUT_N(VC_InitStruct->VC_InputN)); + assert_param(IS_VC_HYS(VC_InitStruct->VC_Hys)); + assert_param(IS_VC_RESP(VC_InitStruct->VC_Resp)); + assert_param(IS_VC_FILTER(VC_InitStruct->VC_FilterEn)); + assert_param(IS_VC_FLT_CLK(VC_InitStruct->VC_FilterClk)); + assert_param(IS_VC_FLT_TIME(VC_InitStruct->VC_FilterTime)); + assert_param(IS_VC_WINDOW(VC_InitStruct->VC_Window)); + assert_param(IS_VC_POLARITY(VC_InitStruct->VC_Polarity)); + REGBITS_MODIFY(CW_VC2->CR0, \ + VCx_CR0_INN_Msk | VCx_CR0_INP_Msk | \ + VCx_CR0_WINDOW_Msk | VCx_CR0_POL_Msk | \ + VCx_CR0_HYS_Msk | VCx_CR0_RESP_Msk, \ + VC_InitStruct->VC_InputN | \ + VC_InitStruct->VC_InputP | \ + VC_InitStruct->VC_Window | \ + VC_InitStruct->VC_Polarity | \ + VC_InitStruct->VC_Hys | \ + VC_InitStruct->VC_Resp); + REGBITS_MODIFY(CW_VC2->CR1, \ + VCx_CR1_FLTCLK_Msk | VCx_CR1_FLTTIME_Msk | \ + VCx_CR1_FLTEN_Msk, \ + VC_InitStruct->VC_FilterClk | \ + VC_InitStruct->VC_FilterTime | \ + VC_InitStruct->VC_FilterEn); + //VCx负端输入信号初始化 + VC1VC2_INNInit(VC_InitStruct); +} + +/** + * @brief + * VC模块去初始化 + * + * @return + */ +void VC_DeInit(void) +{ + // Enable VC reset state + REGBITS_CLR(CW_SYSCTRL->APBRST2, SYSCTRL_APBRST2_VC_Msk); + // Release VC from reset state + REGBITS_SET(CW_SYSCTRL->APBRST2, SYSCTRL_APBRST2_VC_Msk); + VC1_ChannelDeInit(); + VC2_ChannelDeInit(); +} + +/** + * @brief + * VC通道1去初始化 + * + * @return + */ +void VC1_ChannelDeInit(void) +{ + CW_VC1->CR0 = 0u; + CW_VC1->CR1 = 0u; + VC_DisableNvic(VC1_IRQn); +} + +/** + * @brief + * VC通道2去初始化 + * + * @return + */ +void VC2_ChannelDeInit(void) +{ + CW_VC2->CR0 = 0u; + CW_VC2->CR1 = 0u; + VC_DisableNvic(VC2_IRQn); +} + +/** + * @brief + * VC1通道使能 + * + * @return + */ +void VC1_EnableChannel(void) +{ + REGBITS_SET(CW_VC1->CR0, VCx_CR0_EN_Msk); + //等待VCx稳定 + while (!(VC1_GetFlagStatus(VC_FLAG_READY))) + { + ; + } +} + +/** + * @brief + * VC2通道使能 + * + * @return + */ +void VC2_EnableChannel(void) +{ + REGBITS_SET(CW_VC2->CR0, VCx_CR0_EN_Msk); + //等待VCx稳定 + while (!(VC2_GetFlagStatus(VC_FLAG_READY))) + { + ; + } +} + +/** + * @brief + * VC1通道禁用 + * + * @return + */ +void VC1_DisableChannel(void) +{ + REGBITS_CLR(CW_VC1->CR0, VCx_CR0_EN_Msk); +} + +/** + * @brief + * VC2通道禁用 + * + * @return + */ +void VC2_DisableChannel(void) +{ + REGBITS_CLR(CW_VC2->CR0, VCx_CR0_EN_Msk); +} + +/** + * @brief + * VC1输出滤波使能 + * + * @return + */ +void VC1_EnableFilter(void) +{ + REGBITS_SET(CW_VC1->CR1, VCx_CR1_FLTEN_Msk); +} + +/** + * @brief + * VC2输出滤波使能 + * + * @return + */ +void VC2_EnableFilter(void) +{ + REGBITS_SET(CW_VC2->CR1, VCx_CR1_FLTEN_Msk); +} + +/** + * @brief + * VC1输出滤波禁用 + * + * @return + */ +void VC1_DisableFilter(void) +{ + REGBITS_CLR(CW_VC1->CR1, VCx_CR1_FLTEN_Msk); +} + +/** + * @brief + * VC2输出滤波禁用 + * + * @return + */ +void VC2_DisableFilter(void) +{ + REGBITS_CLR(CW_VC2->CR1, VCx_CR1_FLTEN_Msk); +} + +/** + * @brief + * VC通道1/2 输出连接默认值初始化 + * @param VC_OutStruct + * + * @return + */ +void VC1VC2_OutInit(VC_OutTypeDef *VC_OutStruct) +{ + VC_OutStruct->VC_ATIMBk = 0u; + VC_OutStruct->VC_OutAtimClr = 0u; +} + +/** + * @brief + * VC通道1输出连接配置 + * @param VC_OutStruct + * + * @return + */ +void VC1_OutputCfg(VC_OutTypeDef *VC_OutStruct) +{ + //ASSERT(NULL != VC_OutStruct); + assert_param(IS_VC_ATIMBK(VC_OutStruct->VC_ATIMBk)); + assert_param(IS_VC_ATIMCLR(VC_OutStruct->VC_OutAtimClr)); + REGBITS_MODIFY(CW_VC1->CR1, \ + VCx_CR1_ATIMBK_Msk | VCx_CR1_ATIMCLR_Msk, + VC_OutStruct->VC_ATIMBk | \ + VC_OutStruct->VC_OutAtimClr); +} + +/** + * @brief + * VC通道2输出连接配置 + * @param VC_OutStruct + * + * @return + */ +void VC2_OutputCfg(VC_OutTypeDef *VC_OutStruct) +{ + //ASSERT(NULL != VC_OutStruct); + assert_param(IS_VC_ATIMBK(VC_OutStruct->VC_ATIMBk)); + assert_param(IS_VC_ATIMCLR(VC_OutStruct->VC_OutAtimClr)); + REGBITS_MODIFY(CW_VC2->CR1, \ + VCx_CR1_ATIMBK_Msk | VCx_CR1_ATIMCLR_Msk, + VC_OutStruct->VC_ATIMBk | \ + VC_OutStruct->VC_OutAtimClr); +} + +/** + * @brief + * VC通道1/2 BlanK窗口默认值初始化 + * @param VC_BlankStruct + * + * @return + */ +void VC1VC2_BlankInit(VC_BlankTypeDef *VC_BlankStruct) +{ + VC_BlankStruct->VC_BlankFlt = 0u; + VC_BlankStruct->VC_BlankCh3B = 0u; + VC_BlankStruct->VC_BlankCh2B = 0u; + VC_BlankStruct->VC_BlankCh1B = 0u; +} + +/** + * @brief + * VC通道1 BlanK窗口配置 + * @param VC_BlankStruct + * + * @return + */ +void VC1_BlankCfg(VC_BlankTypeDef *VC_BlankStruct) +{ + //ASSERT(NULL != VC_BlankStruct); + assert_param(IS_VC_BLANK_FLT(VC_BlankStruct->VC_BlankFlt)); + assert_param(IS_VC_BLANK_CH3B(VC_BlankStruct->VC_BlankCh3B)); + assert_param(IS_VC_BLANK_CH2B(VC_BlankStruct->VC_BlankCh2B)); + assert_param(IS_VC_BLANK_CH1B(VC_BlankStruct->VC_BlankCh1B)); + REGBITS_MODIFY(CW_VC1->CR1, \ + VCx_CR1_BLANKFLT_Msk | VCx_CR1_BLANKCH3B_Msk | \ + VCx_CR1_BLANKCH2B_Msk | VCx_CR1_BLANKCH1B_Msk, + VC_BlankStruct->VC_BlankFlt | \ + VC_BlankStruct->VC_BlankCh3B | \ + VC_BlankStruct->VC_BlankCh2B | \ + VC_BlankStruct->VC_BlankCh1B); +} + +/** + * @brief + * VC通道2 BlanK窗口配置 + * @param VC_BlankStruct + * + * @return + */ +void VC2_BlankCfg(VC_BlankTypeDef *VC_BlankStruct) +{ + //ASSERT(NULL != VC_BlankStruct); + assert_param(IS_VC_BLANK_FLT(VC_BlankStruct->VC_BlankFlt)); + assert_param(IS_VC_BLANK_CH3B(VC_BlankStruct->VC_BlankCh3B)); + assert_param(IS_VC_BLANK_CH2B(VC_BlankStruct->VC_BlankCh2B)); + assert_param(IS_VC_BLANK_CH1B(VC_BlankStruct->VC_BlankCh1B)); + REGBITS_MODIFY(CW_VC2->CR1, \ + VCx_CR1_BLANKFLT_Msk | VCx_CR1_BLANKCH3B_Msk | \ + VCx_CR1_BLANKCH2B_Msk | VCx_CR1_BLANKCH1B_Msk, + VC_BlankStruct->VC_BlankFlt | \ + VC_BlankStruct->VC_BlankCh3B | \ + VC_BlankStruct->VC_BlankCh2B | \ + VC_BlankStruct->VC_BlankCh1B); +} + +/** + * @brief + * VC通道1窗口比较功能配置 + * + * @param bWindow: TRUE or FALSE + * + * @return + */ +void VC1_WindowEnable(boolean_t bWindow) +{ + if (bWindow) + { + REGBITS_SET(CW_VC1->CR0, VCx_CR0_WINDOW_Msk); + } + else + { + REGBITS_CLR(CW_VC1->CR0, VCx_CR0_WINDOW_Msk); + } +} + +/** + * @brief + * VC通道2窗口比较功能配置 + * + * @param bWindow: TRUE or FALSE + * + * @return + */ +void VC2_WindowEnable(boolean_t bWindow) +{ + if (bWindow) + { + REGBITS_SET(CW_VC2->CR0, VCx_CR0_WINDOW_Msk); + } + else + { + REGBITS_CLR(CW_VC2->CR0, VCx_CR0_WINDOW_Msk); + } +} + +/** + * @brief + * VC通道1输出信号极性设置 + * + * @param bPolarity: TRUE or FALSE + * + * @return + */ +void VC1_PolarityCfg(boolean_t bPolarity) +{ + if (bPolarity) + { + REGBITS_SET(CW_VC1->CR0, VCx_CR0_POL_Msk); + } + else + { + REGBITS_CLR(CW_VC1->CR0, VCx_CR0_POL_Msk); + } +} + +/** + * @brief + * VC通道2输出信号极性设置 + * + * @param bPolarity: TRUE or FALSE + * + * @return + */ +void VC2_PolarityCfg(boolean_t bPolarity) +{ + if (bPolarity) + { + REGBITS_SET(CW_VC2->CR0, VCx_CR0_POL_Msk); + } + else + { + REGBITS_CLR(CW_VC2->CR0, VCx_CR0_POL_Msk); + } +} + +/** + * @brief + * VC1中断配置 + * + * @param VC_IT: + * @arg VC_IT_HIGH + * @arg VC_IT_RISE + * @arg VC_IT_FALL + * @param NewState: + * @arg DISABLE + * @arg ENABLE + */ +void VC1_ITConfig(uint16_t VC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_VC_IT(VC_IT)); + if (NewState != DISABLE) + { + /* Enable the selected VC interrupts */ + CW_VC1->CR1 |= VC_IT; + } + else + { + /* Disable the selected VC interrupts */ + CW_VC1->CR1 &= (~(uint32_t) VC_IT); + } +} + +/** + * @brief + * VC2中断配置 + * + * @param VC_IT: + * @arg VC_IT_READY + * @arg VC_IT_OVW + * @arg VC_IT_WDTR + * @param NewState: + * @arg DISABLE + * @arg ENABLE + */ +void VC2_ITConfig(uint16_t VC_IT, FunctionalState NewState) +{ + uint8_t itMask = 0; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_VC_IT(VC_IT)); + /* Get the VC IT index */ + itMask = (uint8_t) VC_IT; + if (NewState != DISABLE) + { + /* Enable the selected VC interrupts */ + CW_VC2->CR1 |= itMask; + } + else + { + /* Disable the selected VC interrupts */ + CW_VC2->CR1 &= (~(uint32_t) itMask); + } +} + +/** + * @brief + * 获取VC1的使能控制状态 + * + * @param + * + * @return FlagStatus: SET or RESET + */ +FlagStatus VC1_GetEnableStatus(void) +{ + return (REGBITS_GET(CW_VC1->CR0, VCx_CR0_EN_Msk) ? SET : RESET); +} + +/** + * @brief + * 获取VC2的使能控制状态 + * + * @param + * + * @return FlagStatus: SET or RESET + */ +FlagStatus VC2_GetEnableStatus(void) +{ + return (REGBITS_GET(CW_VC2->CR0, VCx_CR0_EN_Msk) ? SET : RESET); +} +//@} // VcGroup + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_wwdt.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_wwdt.c new file mode 100644 index 0000000..202e930 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/cw32f030_wwdt.c @@ -0,0 +1,163 @@ +/** + * @file cw32f030_wwdt.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-04-23 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_wwdt.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief WWDT去初始化 + * @param 无 + * @return 无 + */ +void WWDT_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.WWDT = 0; + CW_SYSCTRL->APBRST1_f.WWDT = 1; +} + +/** + * @brief 初始化WWDT + * @param WWDT_InitStruct 详见结构体定义WWDT_InitTypeDef + */ +void WWDT_Init(WWDT_InitTypeDef *WWDT_InitStruct) +{ + assert_param(IS_WWDT_COUNTER(WWDT_InitStruct->WWDT_CounterValue)); + assert_param(IS_WWDT_PRESCALER(WWDT_InitStruct->WWDT_Prescaler)); + assert_param(IS_WWDT_WINDOW_VALUE(WWDT_InitStruct->WWDT_WindowValue)); + CW_SYSCTRL->APBEN1_f.WWDT = 1U; /* WWDT的APB总线访问时钟使能 */ + CW_WWDT->CR0 = (WWDT_InitStruct->WWDT_CounterValue & WWDT_CR0_WCNT_Msk); + if (WWDT_InitStruct->WWDT_ITState == ENABLE) + { + CW_WWDT->CR1 = WWDT_InitStruct->WWDT_WindowValue | WWDT_InitStruct->WWDT_Prescaler | WWDT_CR1_IE_Msk; + } + else + { + CW_WWDT->CR1 = (WWDT_InitStruct->WWDT_WindowValue | WWDT_InitStruct->WWDT_Prescaler) & (~WWDT_CR1_IE_Msk); + } +} + +/** + * @brief 使能WWDT，使能WWDT后不能禁止 + */ +void WWDT_Cmd(void) +{ + CW_WWDT->CR0_f.EN = 1U; +} + +/** + * @brief 喂狗函数 + * @param Counter WWDT计数器的更新值，取值范围0x40~0x7F + */ +void WWDT_Refresh(uint8_t Counter) +{ + assert_param(IS_WWDT_COUNTER(Counter)); + CW_WWDT->CR0_f.WCNT = Counter; +} + +/** + * @brief 设置WWDT的预分频系数 + * @param WWDT_Prescaler 取值范围WWDT_Prescaler_DIV4096~WWDT_Prescaler_DIV524288 + */ +void WWDT_SetPrescaler(uint32_t WWDT_Prescaler) +{ + assert_param(IS_WWDT_PRESCALER(WWDT_Prescaler)); + REGBITS_MODIFY(CW_WWDT->CR1, WWDT_CR1_PRS_Msk, WWDT_Prescaler); +} + +/** + * @brief 设置WWDT的窗口系数 + * @param WindowValue 窗口值，取值范围0x40~0x7F + */ +void WWDT_SetWindowValue(uint8_t WindowValue) +{ + assert_param(IS_WWDT_WINDOW_VALUE(WindowValue)); + CW_WWDT->CR1_f.WINR = WindowValue; +} + +/** + * @brief 设置WWDT的CNT值 + * @param CountValue 窗口值，取值范围0x40~0x7F, 小于0x40将产生复位 + */ +void WWDT_SetCountValue(uint8_t CountValue) +{ + CW_WWDT->CR0_f.WCNT = CountValue; +} + +/** + * @brief 获取当前计数器的值 + * @return uint8_t 当前计数器的值 + */ +uint8_t WWDT_GetCounterValue(void) +{ + return (uint8_t)(CW_WWDT->CR0 & WWDT_CR0_WCNT_Msk); +} + +/** + * @brief 获取当前设置的窗口值 + * @return uint8_t 当前设置的窗口值 + */ +uint8_t WWDT_GetWindowValue(void) +{ + return (uint8_t)(CW_WWDT->CR1 & WWDT_CR1_WINR_Msk); +} + +/** + * @brief 设置WWDT的预溢出中断使能 复位后，默认关闭中断使能 + */ +void WWDT_EnableIT(void) +{ + CW_WWDT->CR1_f.IE = ENABLE; +} + +/** + * @brief 获取WWDT的状态寄存器的预溢出位状态 + * @return FlagStatus + */ +FlagStatus WWDT_GetFlagStatus(void) +{ + return (FlagStatus)(CW_WWDT->SR); +} + +/** + * @brief 清除WWDT的状态寄存器的预溢出位状态 + */ +void WWDT_ClearFlag(void) +{ + REGBITS_CLR(CW_WWDT->SR, WWDT_SR_POV_Msk); +} diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/system_cw32f030.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/system_cw32f030.c new file mode 100644 index 0000000..1c3b24b --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Libraries/src/system_cw32f030.c @@ -0,0 +1,156 @@ + + +/****************************************************************************** +* Include files * +******************************************************************************/ +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "cw32f030_rcc.h" + +#define FLASH_MEMORY_BASE 0x00000000UL /*!< FLASH(up to 64 KB) base address in the alias region */ +#define SRAM_MEMORY_BASE 0x20000000UL /*!< SRAM1(8 KB) base address in the alias region */ +#define VECT_TAB_OFFSET 0x00002000UL + +/****************************************************************************** + ** System Clock Frequency (Core Clock) Variable according CMSIS + ******************************************************************************/ + +uint32_t SystemCoreClock = 8000000; + +void SystemCoreClockUpdate(void) // Update SystemCoreClock variable +{ + SystemCoreClock = 8000000; +} + +/** + ****************************************************************************** + ** \brief Setup the microcontroller system. Initialize the System and update + ** the SystemCoreClock variable. + ** + ** \param none + ** \return none + ******************************************************************************/ +void SystemInit(void) +{ + //Load TrimCode in this. + //... +#ifdef VECT_TAB_REMAP + SCB->VTOR = FLASH_MEMORY_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif + SystemCoreClockUpdate(); + CW_SYSCTRL->HSI_f.TRIM = *((volatile uint16_t *)RCC_HSI_TRIMCODEADDR); + CW_SYSCTRL->LSI_f.TRIM = *((volatile uint16_t *)RCC_LSI_TRIMCODEADDR); + //Init Hide thing. + //... +} + + + +/****************************************************************************** +* Internal Funcation * +******************************************************************************/ + +/** + * \brief delay1ms + * delay approximately 1ms. + * \param [in] u32Cnt + * \retval void + */ +void delay1ms(uint32_t u32Cnt) +{ + uint32_t u32end; + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; + while (u32Cnt-- > 0) + { + SysTick->VAL = 0; + u32end = 0x1000000 - SystemCoreClock / 1000; + while (SysTick->VAL > u32end) + { + ; + } + } + SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +} + + +/** + * \brief delay100us + * delay approximately 100us. + * \param [in] u32Cnt + * \retval void + */ +void delay100us(uint32_t u32Cnt) +{ + uint32_t u32end; + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; + while (u32Cnt-- > 0) + { + SysTick->VAL = 0; + u32end = 0x1000000 - SystemCoreClock / 10000; + while (SysTick->VAL > u32end) + { + ; + } + } + SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +} + + +/** + * \brief delay10us + * delay approximately 10us. + * \param [in] u32Cnt + * \retval void + */ +void delay10us(uint32_t u32Cnt) +{ + uint32_t u32end; + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; + while (u32Cnt-- > 0) + { + SysTick->VAL = 0; + u32end = 0x1000000 - SystemCoreClock / 100000; + while (SysTick->VAL > u32end) + { + ; + } + } + SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +} + + +void FirmwareDelay(uint32_t DlyCnt) +{ + volatile uint32_t thisCnt = DlyCnt; + while (thisCnt--) + { + ; + } +} + +/** + * \brief clear memory + * + * \param [in] start addr + * \param [in] memory size(byte) + * \retval void + */ +void MemClr(void *pu8Address, uint32_t u32Count) +{ + uint8_t *pu8Addr = (uint8_t *)pu8Address; + if (NULL == pu8Addr) + { + return; + } + while (u32Count--) + { + *pu8Addr++ = 0; + } +} + diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Utilities/cw32f030c8t6_startkit.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Utilities/cw32f030c8t6_startkit.c new file mode 100644 index 0000000..1ea81ca --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Utilities/cw32f030c8t6_startkit.c @@ -0,0 +1,65 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +#include "cw32f030c8t6_startkit.h" +static void LED_On(void *LED) +{ + LED_InitTypeDef *_LED; + _LED = (LED_InitTypeDef *)LED; + _LED->LED_Port->BSRR = _LED->LED_Pin; +} + +static void LED_Off(void *LED) +{ + LED_InitTypeDef *_LED; + _LED = (LED_InitTypeDef *)LED; + _LED->LED_Port->BRR = _LED->LED_Pin; +} + +static void LED_Toggle(void *LED) +{ + LED_InitTypeDef *_LED; + _LED = (LED_InitTypeDef *)LED; + _LED->LED_Port->TOG = _LED->LED_Pin; +} + +void LED_Init(void *LED) +{ + LED_InitTypeDef *_LED; + _LED = (LED_InitTypeDef *)LED; + switch ((uint32_t)_LED->LED_Port) + { + case (uint32_t)CW_GPIOA: + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOA_Msk; + break; + case (uint32_t)CW_GPIOB: + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOB_Msk; + break; + case (uint32_t)CW_GPIOC: + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOC_Msk; + break; + case (uint32_t)CW_GPIOF: + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOF_Msk; + break; + default: + break; + } + _LED->LED_Port->ANALOG &= ~(_LED->LED_Pin); + _LED->LED_Port->DIR &= ~(_LED->LED_Pin); + _LED->LED_Off = LED_Off; + _LED->LED_On = LED_On; + _LED->LED_Toggle = LED_Toggle; +} diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Utilities/cw32f030c8t6_startkit.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Utilities/cw32f030c8t6_startkit.h new file mode 100644 index 0000000..47a9ff2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Utilities/cw32f030c8t6_startkit.h @@ -0,0 +1,51 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030C8T6_STARTKIT_H +#define __CW32F030C8T6_STARTKIT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" + + +/* type definitions ('typedef') ----------------------------------------------*/ +typedef struct +{ + GPIO_TypeDef *LED_Port; + uint32_t LED_Pin; + void (*LED_On)(void *LED); + void (*LED_Off)(void *LED); + void (*LED_Toggle)(void *LED); +} LED_InitTypeDef; + +/* pre-processor symbols/macros ('#define') ----------------------------------*/ + + +/* Global variable definitions (declared in header file with 'extern') ------*/ + +/* Global function prototypes -----------------------------------------------*/ +void LED_Init(void *LED); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Utilities/log.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Utilities/log.c new file mode 100644 index 0000000..47eebcc --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Utilities/log.c @@ -0,0 +1,159 @@ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "log.h" +#include "cw32f030_gpio.h" +#include "cw32f030_rcc.h" +#include "cw32f030_uart.h" + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +static void SerialInit(uint32_t BaudRate); +static void SerialSend(uint8_t Data); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +static uint8_t const pow2_table[] = {0, 1, 2, 3, 4, 5, 6, 7}; + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +void LogInit(void) +{ + SerialInit(LOG_SERIAL_BPS); +} + +static void SerialInit(uint32_t BaudRate) +{ + uint32_t PCLK_Freq; + GPIO_InitTypeDef GPIO_InitStructure = {0}; + USART_InitTypeDef USART_InitStructure = {0}; + PCLK_Freq = SystemCoreClock >> pow2_table[CW_SYSCTRL->CR0_f.HCLKPRS]; + PCLK_Freq >>= pow2_table[CW_SYSCTRL->CR0_f.PCLKPRS]; +#ifdef DEBUG_USING_UART1 + //时钟使能 + __RCC_GPIOA_CLK_ENABLE(); + __RCC_UART1_CLK_ENABLE(); + // 默认UART1.TX 映射到PA08 UART1.RX 映射到PA09， + // 如需分配其他引脚请自行修改 + // 先设置UART TX RX 复用，后设置GPIO的属性，避免口线上出现毛刺 + PA08_AFx_UART1TXD(); + PA09_AFx_UART1RXD(); + GPIO_InitStructure.Pins = GPIO_PIN_8; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.Pins = GPIO_PIN_9; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); +#elif defined DEBUG_USING_UART2 + __RCC_UART2_CLK_ENABLE(); + __RCC_GPIOA_CLK_ENABLE(); + // 默认UART2.TX 映射到PA06 UART2.RX 映射到PA07， + // 如需分配其他引脚请自行修改 + PA06_AFx_UART2TXD(); + PA07_AFx_UART2RXD(); + GPIO_InitStructure.Pins = GPIO_PIN_6; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.Pins = GPIO_PIN_7; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); +#elif defined DEBUG_USING_UART3 + __RCC_UART3_CLK_ENABLE(); + __RCC_GPIOA_CLK_ENABLE(); + // 默认UART3.TX 映射到PA2 UART3.RX 映射到PA3 + // 如需分配其他引脚请自行修改 + PA02_AFx_UART3TXD(); + PA03_AFx_UART3RXD(); + GPIO_InitStructure.Pins = GPIO_PIN_2; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.Pins = GPIO_PIN_3; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); +#endif + USART_InitStructure.USART_BaudRate = BaudRate; + USART_InitStructure.USART_Over = USART_Over_16; + USART_InitStructure.USART_Source = USART_Source_PCLK; + USART_InitStructure.USART_UclkFreq = PCLK_Freq; + USART_InitStructure.USART_StartBit = USART_StartBit_FE; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; +#ifdef DEBUG_USING_UART1 + USART_Init(CW_UART1, &USART_InitStructure); +#elif defined DEBUG_USING_UART2 + USART_Init(CW_UART2, &USART_InitStructure); +#elif defined DEBUG_USING_UART3 + USART_Init(CW_UART3, &USART_InitStructure); +#endif +} + +static void SerialSend(uint8_t Data) +{ +#ifdef DEBUG_USING_UART1 + USART_SendData_8bit(CW_UART1, Data); + while (USART_GetFlagStatus(CW_UART1, USART_FLAG_TXE) == RESET); +#elif defined DEBUG_USING_UART2 + USART_SendData_8bit(CW_UART2, Data); + while (USART_GetFlagStatus(CW_UART2, USART_FLAG_TXE) == RESET); +#elif defined DEBUG_USING_UART3 + USART_SendData_8bit(CW_UART3, Data); + while (USART_GetFlagStatus(CW_UART3, USART_FLAG_TXE) == RESET); +#endif +} + +int fputc(int ch, FILE *f) +{ + SerialSend(ch); + return ch; +} + +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + size_t nChars = 0; + if (buffer == 0) + { + /* + * This means that we should flush internal buffers. Since we + * don't we just return. (Remember, "handle" == -1 means that all + * handles should be flushed.) + */ + return 0; + } + for (/* Empty */; size != 0; --size) + { + SerialSend(*buffer++); + ++nChars; + } + return nChars; +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Utilities/log.h b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Utilities/log.h new file mode 100644 index 0000000..e8d548c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Utilities/log.h @@ -0,0 +1,54 @@ +/** + * @file log.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2021-06-15 + * + * @copyright Copyright (c) 2021 + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LOG_H +#define __LOG_H +#include "base_types.h" +#include +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +#define LOG_SERIAL_BPS 115200 +#define DEBUG_USING_UART1 + + +/* Exported functions prototypes ---------------------------------------------*/ +void LogInit(void); + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Utilities/write.c b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Utilities/write.c new file mode 100644 index 0000000..30c3625 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/Utilities/write.c @@ -0,0 +1,68 @@ +/******************* + * + * Copyright 1998-2017 IAR Systems AB. + * + * This is a template implementation of the "__write" function used by + * the standard library. Replace it with a system-specific + * implementation. + * + * The "__write" function should output "size" number of bytes from + * "buffer" in some application-specific way. It should return the + * number of characters written, or _LLIO_ERROR on failure. + * + * If "buffer" is zero then __write should perform flushing of + * internal buffers, if any. In this case "handle" can be -1 to + * indicate that all handles should be flushed. + * + * The template implementation below assumes that the application + * provides the function "MyLowLevelPutchar". It should return the + * character written, or -1 on failure. + * + ********************/ + +#include + +#pragma module_name = "?__write" + +int MyLowLevelPutchar(int x); + +/* + * If the __write implementation uses internal buffering, uncomment + * the following line to ensure that we are called with "buffer" as 0 + * (i.e. flush) when the application terminates. + */ + +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + /* Remove the #if #endif pair to enable the implementation */ +#if 1 + size_t nChars = 0; + if (buffer == 0) + { + /* + * This means that we should flush internal buffers. Since we + * don't we just return. (Remember, "handle" == -1 means that all + * handles should be flushed.) + */ + return 0; + } + /* This template only writes to "standard out" and "standard err", + * for all other file handles it returns failure. */ + if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) + { + return _LLIO_ERROR; + } + for (/* Empty */; size != 0; --size) + { + if (MyLowLevelPutchar(*buffer++) < 0) + { + return _LLIO_ERROR; + } + ++nChars; + } + return nChars; +#else + /* Always return error code when implementation is disabled. */ + return _LLIO_ERROR; +#endif +} diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/readme.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/readme.txt new file mode 100644 index 0000000..e765aa2 --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/readme.txt @@ -0,0 +1,6 @@ +说明： +Documents：存放说明文档 +IdeSupport：MDK和IAR的支持文件 +Libraries： 驱动库 +Examples： 工程样例目录 +Utilities: 公共组件 \ No newline at end of file diff --git a/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/更新记录.txt b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/更新记录.txt new file mode 100644 index 0000000..495601c --- /dev/null +++ b/原单片机-CW32F030/MCU厂资料/CW32F030_StandardPeripheralLib_V2.2/更新记录.txt @@ -0,0 +1,23 @@ +V2.2 （2024-11-11） + 1.修改keil的package包，支持5.38以后的版本。 + 2.修改flash库文件中的拼写错误。 +v2.1 （2024-5-14） + 1.修改工程配置错误 + 2.修改SysTick_Handler（）函数的重定义 +v2.0 （2024-1-15） + 1.修改注释错误 +V1.9 （2023-11-23） + 1.修改库文件I2C中的bug +V1.8（2023-08-10） + 1.修改库文件FLASH中的bug +V1.7（2023-06-7） + 1.修改库文件I2C中的bug + 2.修改SVD文件的bug +V1.6（2023-04-2） + 1.修改已知的bug。 +V1.5（2023-03-16） + 1.修复RCC文件中对LSE时钟管脚的错误配置。 + +V1.4（2022-08-11） + 1.修复FLASH的写函数存在的bug + 2.整理libraries目录下头文件的格式。 diff --git a/原单片机-CW32F030/MCU厂资料/CW32x030_UserManual_CN_V2.5.pdf b/原单片机-CW32F030/MCU厂资料/CW32x030_UserManual_CN_V2.5.pdf new file mode 100644 index 0000000..7426fc2 Binary files /dev/null and b/原单片机-CW32F030/MCU厂资料/CW32x030_UserManual_CN_V2.5.pdf differ diff --git a/原单片机-CW32F030/原项目程序/SW.zip b/原单片机-CW32F030/原项目程序/SW.zip new file mode 100644 index 0000000..320ce4b Binary files /dev/null and b/原单片机-CW32F030/原项目程序/SW.zip differ diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/EventRecorderStub.scvd b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/EventRecorderStub.scvd new file mode 100644 index 0000000..2956b29 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/GPIO.uvoptx b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/GPIO.uvoptx new file mode 100644 index 0000000..9dd01c0 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/GPIO.uvoptx @@ -0,0 +1,775 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U69544988 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO31 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030.FLM -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FN1 -FC1000 -FD20000000 -FF0FlashCW32F030 -FL010000 -FS00 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + CMSIS_AGDI + UL2CM3(-S0 -C0 -P0 -FN1 -FC1000 -FD20000000 -FF0FlashCW32F030 -FL010000 -FS00 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + + + + 0 + 1 + temp1,0x0A + + + 1 + 1 + temp2,0x0A + + + 2 + 1 + u16AdcResult + + + 3 + 1 + Motor_Start_F,0x0A + + + 4 + 1 + ADC_Result_Array,0x0A + + + 5 + 1 + OutPwm,0x0A + + + 6 + 1 + Cur_step + + + 7 + 1 + SampleData,0x0A + + + 8 + 1 + CanshuV,0x0A + + + 9 + 1 + StepTime,0x0A + + + 10 + 1 + OutPwmValue,0x0A + + + 11 + 1 + SSumError + + + 12 + 1 + SError,0x0A + + + 13 + 1 + SdError,0x0A + + + 14 + 1 + SampleData[0],0x0A + + + 15 + 1 + SampleData[1],0x0A + + + 16 + 1 + SampleData[3],0x0A + + + 17 + 1 + RealS1,0x0A + + + 18 + 1 + TimeCountPID + + + 19 + 1 + STEP_last + + + 20 + 1 + MOTORSTATE + + + 21 + 1 + TargS1,0x0A + + + 22 + 1 + SetSpeed,0x0A + + + 23 + 1 + RealS1,0x0A + + + 24 + 1 + RealS,0x0A + + + 25 + 1 + ErrorCode,0x10 + + + 26 + 1 + SampleData,0x10 + + + 27 + 1 + MOTORSTATE + + + 28 + 1 + CanshuV,0x0A + + + 29 + 1 + RealS,0x0A + + + 30 + 1 + MOTORSTATE + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + USER + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\USER\interrupts_cw32f030.c + interrupts_cw32f030.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + .\USER\startup_cw32f030.s + startup_cw32f030.s + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + .\USER\MAIN.c + MAIN.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + .\USER\init.c + init.c + 0 + 0 + + + + + lib + 0 + 0 + 0 + 0 + + 2 + 5 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_adc.c + cw32f030_adc.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_atim.c + cw32f030_atim.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_awt.c + cw32f030_awt.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_btim.c + cw32f030_btim.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_crc.c + cw32f030_crc.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_debug.c + cw32f030_debug.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_digitalsign.c + cw32f030_digitalsign.c + 0 + 0 + + + 2 + 12 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_dma.c + cw32f030_dma.c + 0 + 0 + + + 2 + 13 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_flash.c + cw32f030_flash.c + 0 + 0 + + + 2 + 14 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_gpio.c + cw32f030_gpio.c + 0 + 0 + + + 2 + 15 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_gtim.c + cw32f030_gtim.c + 0 + 0 + + + 2 + 16 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_i2c.c + cw32f030_i2c.c + 0 + 0 + + + 2 + 17 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_lvd.c + cw32f030_lvd.c + 0 + 0 + + + 2 + 18 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_pwr.c + cw32f030_pwr.c + 0 + 0 + + + 2 + 19 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_ram.c + cw32f030_ram.c + 0 + 0 + + + 2 + 20 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_rcc.c + cw32f030_rcc.c + 0 + 0 + + + 2 + 21 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_rtc.c + cw32f030_rtc.c + 0 + 0 + + + 2 + 22 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_spi.c + cw32f030_spi.c + 0 + 0 + + + 2 + 23 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_systick.c + cw32f030_systick.c + 0 + 0 + + + 2 + 24 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_uart.c + cw32f030_uart.c + 0 + 0 + + + 2 + 25 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_vc.c + cw32f030_vc.c + 0 + 0 + + + 2 + 26 + 1 + 0 + 0 + 0 + ..\Libraries\src\cw32f030_wwdt.c + cw32f030_wwdt.c + 0 + 0 + + + 2 + 27 + 1 + 0 + 0 + 0 + ..\Libraries\src\system_cw32f030.c + system_cw32f030.c + 0 + 0 + + + + + Motor + 1 + 0 + 0 + 0 + + 3 + 28 + 1 + 0 + 0 + 0 + .\USER\globalv.c + globalv.c + 0 + 0 + + + 3 + 29 + 1 + 0 + 0 + 0 + .\USER\MOTOR.C + MOTOR.C + 0 + 0 + + + 3 + 30 + 1 + 0 + 0 + 0 + .\USER\compu.c + compu.c + 0 + 0 + + + 3 + 31 + 1 + 0 + 0 + 0 + .\USER\control.c + control.c + 0 + 0 + + + 3 + 32 + 1 + 0 + 0 + 0 + .\USER\pid.c + pid.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/GPIO.uvprojx b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/GPIO.uvprojx new file mode 100644 index 0000000..3337e99 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/GPIO.uvprojx @@ -0,0 +1,576 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32F030C8 + WHXY + WHXY.CW32F030_DFP.1.0.5 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32F030 -FS00 -FL010000 -FP0($$Device:CW32F030C8$Flash\FlashCW32F030.FLM)) + 0 + $$Device:CW32F030C8$Device\Include\CW32F030.h + + + + + + + + + + $$Device:CW32F030C8$SVD\CW32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + SWQQT904_V01 + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + + + __ARMCC_VERSION=5060006,__COMPILER_BARRIER=__schedule_barrier + + .\USER;..\Libraries\inc;..\..\..\..\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + USER + + + interrupts_cw32f030.c + 1 + .\USER\interrupts_cw32f030.c + + + startup_cw32f030.s + 2 + .\USER\startup_cw32f030.s + + + MAIN.c + 1 + .\USER\MAIN.c + + + init.c + 1 + .\USER\init.c + + + + + lib + + + cw32f030_adc.c + 1 + ..\Libraries\src\cw32f030_adc.c + + + cw32f030_atim.c + 1 + ..\Libraries\src\cw32f030_atim.c + + + cw32f030_awt.c + 1 + ..\Libraries\src\cw32f030_awt.c + + + cw32f030_btim.c + 1 + ..\Libraries\src\cw32f030_btim.c + + + cw32f030_crc.c + 1 + ..\Libraries\src\cw32f030_crc.c + + + cw32f030_debug.c + 1 + ..\Libraries\src\cw32f030_debug.c + + + cw32f030_digitalsign.c + 1 + ..\Libraries\src\cw32f030_digitalsign.c + + + cw32f030_dma.c + 1 + ..\Libraries\src\cw32f030_dma.c + + + cw32f030_flash.c + 1 + ..\Libraries\src\cw32f030_flash.c + + + cw32f030_gpio.c + 1 + ..\Libraries\src\cw32f030_gpio.c + + + cw32f030_gtim.c + 1 + ..\Libraries\src\cw32f030_gtim.c + + + cw32f030_i2c.c + 1 + ..\Libraries\src\cw32f030_i2c.c + + + cw32f030_lvd.c + 1 + ..\Libraries\src\cw32f030_lvd.c + + + cw32f030_pwr.c + 1 + ..\Libraries\src\cw32f030_pwr.c + + + cw32f030_ram.c + 1 + ..\Libraries\src\cw32f030_ram.c + + + cw32f030_rcc.c + 1 + ..\Libraries\src\cw32f030_rcc.c + + + cw32f030_rtc.c + 1 + ..\Libraries\src\cw32f030_rtc.c + + + cw32f030_spi.c + 1 + ..\Libraries\src\cw32f030_spi.c + + + cw32f030_systick.c + 1 + ..\Libraries\src\cw32f030_systick.c + + + cw32f030_uart.c + 1 + ..\Libraries\src\cw32f030_uart.c + + + cw32f030_vc.c + 1 + ..\Libraries\src\cw32f030_vc.c + + + cw32f030_wwdt.c + 1 + ..\Libraries\src\cw32f030_wwdt.c + + + system_cw32f030.c + 1 + ..\Libraries\src\system_cw32f030.c + + + + + Motor + + + globalv.c + 1 + .\USER\globalv.c + + + MOTOR.C + 1 + .\USER\MOTOR.C + + + compu.c + 1 + .\USER\compu.c + + + control.c + 1 + .\USER\control.c + + + pid.c + 1 + .\USER\pid.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/RTE/_Target_1/RTE_Components.h b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/RTE/_Target_1/RTE_Components.h new file mode 100644 index 0000000..0be9252 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/RTE/_Target_1/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'GPIO' + * Target: 'Target 1' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CW32F030.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/MAIN.c b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/MAIN.c new file mode 100644 index 0000000..57daff1 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/MAIN.c @@ -0,0 +1,306 @@ +/* +2ҳ˵1趨ٶȡʵʱٶȣ 2ĸߵѹʾ + KEY1лٶȼѹ˵ + KEY2лʱҲлLED2ʾͬķ + KEY3ͣƣLED3ʱ״̬ LED3ʱֹͣ״̬ + λ٣лٶȲ˵ʾǰ趨ת١ + Designed by Cache.lee from UET company + Tel:18129915976 +*/ +#include "main.h" +#include "motor.h" +#include "globalv.h" +#include "init.h" +#include "pid.h" +#include "compu.h" +#include "control.h" +//#include "OLED_I2C.h" + +unsigned int Menu=0; + + + +//UARTx +#define DEBUG_USARTx CW_UART3 +#define DEBUG_USART_CLK RCC_APB1_PERIPH_UART3 +#define DEBUG_USART_APBClkENx RCC_APBPeriphClk_Enable1 +#define DEBUG_USART_BaudRate 115200 +#define DEBUG_USART_UclkFreq 64000000 + +//UARTx GPIO +#define DEBUG_USART_GPIO_CLK RCC_AHB_PERIPH_GPIOB +#define DEBUG_USART_TX_GPIO_PORT CW_GPIOB +#define DEBUG_USART_TX_GPIO_PIN GPIO_PIN_6 +#define DEBUG_USART_RX_GPIO_PORT CW_GPIOB +#define DEBUG_USART_RX_GPIO_PIN GPIO_PIN_7 + +//GPIO AF +#define DEBUG_USART_AFTX PB06_AFx_UART3TXD() +#define DEBUG_USART_AFRX PB07_AFx_UART3RXD() + + + +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + + +/** + * @brief UART + * + */ +void UART_Configuration(void) +{ + USART_InitTypeDef USART_InitStructure; + + GPIO_InitTypeDef GPIO_InitStructure; + + //ʱʹ + RCC_AHBPeriphClk_Enable(DEBUG_USART_GPIO_CLK, ENABLE); + DEBUG_USART_APBClkENx(DEBUG_USART_CLK, ENABLE); + + //UART TX RX + DEBUG_USART_AFTX; + DEBUG_USART_AFRX; + + GPIO_InitStructure.Pins = DEBUG_USART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pins = DEBUG_USART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStructure); + + + USART_InitStructure.USART_BaudRate = DEBUG_USART_BaudRate; + USART_InitStructure.USART_Over = USART_Over_16; + USART_InitStructure.USART_Source = USART_Source_PCLK; + USART_InitStructure.USART_UclkFreq = DEBUG_USART_UclkFreq; + USART_InitStructure.USART_StartBit = USART_StartBit_FE; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(DEBUG_USARTx, &USART_InitStructure); +} + +/** + * @brief Retargets the C library printf function to the USART. + * + */ +PUTCHAR_PROTOTYPE +{ + + USART_SendData_8bit(DEBUG_USARTx, (uint8_t)ch); + + while (USART_GetFlagStatus(DEBUG_USARTx, USART_FLAG_TXE) == RESET); + + return ch; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + + +void PowerOnDelay(void) +{ + unsigned int i; + + for(i=0;i<60000;i++); + for(i=0;i<60000;i++); + for(i=0;i<60000;i++); + for(i=0;i<60000;i++); + for(i=0;i<60000;i++); + for(i=0;i<60000;i++); + + KKN=(MAXSPEED-MINSPEED); + KKN=KKN/(NMAXVD-NMINVD); +} + +unsigned int hte=0; +int main() +{ + unsigned char DZCount=0; + char temp_buff[100],temp_buff1[50]; + +// unsigned char key_1=0; + + PowerOnDelay(); + RCC_Configuration(); //ʱ + UART_Configuration(); + GPIOInit(); //GPIO + LEDON(); + ADC_Configuration(); //AD + PWMtimer_init(); + BTIM_init(); + Halltimer_init(); + //printf("ADC[0]:%d ADC[1]:%d ADC[2]:%d ADC[3]:%d\r\n",SampleData[0],SampleData[1],SampleData[2],SampleData[3]); + + PWM_AL_ON; + PWM_BL_ON; + PWM_CL_ON; + TimeCountTemp=0; + while(TimeCountTemp<50); + TimeCountTemp=0; + PWM_AL_OFF; + PWM_BL_OFF; + PWM_CL_OFF; + +// I2C_init(); //OLED init +// I2C_OLED_Init(); +// I2C_OLED_Clear(1); +// I2C_OLED_UPdata(); +// + printf("Update %s %s\r\n",__DATE__,__TIME__); + printf("ADC[0]:%d ADC[1]:%d ADC[2]:%d ADC[3]:%d\r\n",SampleData[0],SampleData[1],SampleData[2],SampleData[3]); + + + SampleVI(); //ɼѹ + startflag=1; + EnDirCheck(); + + DIin=0x500; //ƫõ趨 0.9V-1.1Vм䣬Ϊȷ + if(SampleData[1]>1117&&SampleData[1]<=1500)DIin=SampleData[1]; + else printf("Current read err\r\n"); + if(SampleData[2]>3000|| SampleData[2]<700) printf("Speed read err\r\n"); + if(HALL_Check()==0|| HALL_Check()==7) printf("HALL Read Err\r\n"); + if(CanshuV<30) printf("Votage read err\r\n"); + sprintf(temp_buff1,"Set :%4d RPM ",SetSpeed); //ʾռձ + sprintf(temp_buff,"Real:%4d RPM ",RealS); //ʾת + printf("%s\r\n",temp_buff); + printf("%s\r\n",temp_buff1); + sprintf(temp_buff1,"Vbus :%d.%d V ",CanshuV/10,CanshuV%10); //ʾռձ + sprintf(temp_buff,"I(MA):%d ",CanshuI); //ʾת + printf("%s\r\n",temp_buff); + printf("%s\r\n",temp_buff1); + GPIO_WritePin(VOUT_EN_GPIO_PORT,VOUT_EN_GPIO_PIN,GPIO_Pin_SET); //12V + while(1) + { + if(TimeCountCompuSpeed>20) //20MSɼһٶ趨ֵ,HALLǷ + { + TimeCountCompuSpeed=0; + SampleSpeed(); + HALL_Check(); + } + + if(TimeCountVI>=200)//100MSһεѹ,һʵʱٶȼ + { + printf("ADC[0]:%d ADC[1]:%d ADC[2]:%d ADC[3]:%d\r\n",SampleData[0],SampleData[1],SampleData[2],SampleData[3]); + + TimeCountVI=0; + SampleVI(); + + RealS=hte*50/MPolePairs;//HALLcount1*10*60/6/MPolePairs; 100MS洢һλ + + if(MOTORSTATE==STATESTARTPID||MOTORSTATE==STATERUNPID) + { + if(RealS==0) + { + DZCount++; + if(DZCount>=10)//2S + { + DZCount=0;ErrorCode=7;//ת + } + } + else DZCount=0; + } + } + + if(ErrorCode!=0&&MOTORSTATE!=STATEERROR&&MOTORSTATE!=STATEERROROVER)// + { + MOTORSTATE=STATEERROR; + printf("ErrorCode=%d\r\n",ErrorCode); + GPIO_WritePin(VOUT_EN_GPIO_PORT,VOUT_EN_GPIO_PIN,GPIO_Pin_RESET); //12V + } + + + if(TimeCountkey>=500) //500msˢʾ + { + LEDTOG(); + TimeCountkey=0; +// if(Menu==0) +// { + sprintf(temp_buff1,"Set :%4d RPM ",SetSpeed); //ʾռձ + sprintf(temp_buff,"Real:%4d RPM ",RealS); //ʾת + printf("%s\r\n",temp_buff); + printf("%s\r\n",temp_buff1); +// } +// else +// { + sprintf(temp_buff1,"Vbus :%d.%d V ",CanshuV/10,CanshuV%10); //ʾռձ + sprintf(temp_buff,"I(MA):%d ",CanshuI); //ʾת +// } + printf("%s\r\n",temp_buff); + printf("%s\r\n",temp_buff1); + // printf("MOTORSTATE=%d\r\n",MOTORSTATE); +// I2C_OLED_ShowString(0,0,temp_buff1); +// I2C_OLED_ShowString(0,15,temp_buff); +// I2C_OLED_UPdata(); + } + MotorBreak(); + EnDirCheck(); + + //״̬ + switch(MOTORSTATE) + { + case STATESTARTCHECK: + MotorStartCheck(); + break; + case STATESTARTPID: + MotorStartPID(); + break; + case STATERUNPID: + MotorRunPID(); + break; + case STATESTOP: MotorStop();break; + case STATEERROR: MotorError();break; + case STATEERROROVER: MotorErrorOver();break; + } + } +} + + +//1ms ʱ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + if(BTIM_GetITStatus(CW_BTIM1, BTIM_IT_OV)) + { //1MS timer + BTIM_ClearITPendingBit(CW_BTIM1, BTIM_IT_OV); + + TimeCountTemp++; + TimeCountCompuSpeed++; //ٶ + TimeCountRealSpd++; //˲ʱٶ + if(TimeCountAvgSpd>=200){hte=HALLcount1;HALLcount1=0;TimeCountAvgSpd=0;}//ʾٶֵ + if(TimeCountRealSpd>=20){HALLcountTemp=HALLcount;HALLcount=0;TimeCountRealSpd=0;} + TimeCountPID++; //PID + TimeCountAvgSpd++; //ƽٶ + TimeCountVI++;//ѹ + TimeCountkey++; + } + /* USER CODE END */ +} + + diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/MOTOR.C b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/MOTOR.C new file mode 100644 index 0000000..4569082 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/MOTOR.C @@ -0,0 +1,234 @@ +#include "motor.h" +#include "globalv.h" + +void PWMtimer_init(void) +{ + ATIM_InitTypeDef ATIM_InitStruct; + ATIM_OCInitTypeDef ATIM_OCInitStruct; + GPIO_InitTypeDef GPIO_InitStruct; + + __RCC_ATIM_CLK_ENABLE(); + __RCC_GPIOA_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); + + PA08_AFx_ATIMCH1A(); + PA09_AFx_ATIMCH2A(); + PA10_AFx_ATIMCH3A(); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + + PWM_AH_OFF; + PWM_BH_OFF; + PWM_CH_OFF; + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + + PWM_AL_OFF; + PWM_BL_OFF; + PWM_CL_OFF; + + ATIM_InitStruct.BufferState = ENABLE;//;//; + ATIM_InitStruct.ClockSelect = ATIM_CLOCK_PCLK; + ATIM_InitStruct.CounterAlignedMode = ATIM_COUNT_MODE_EDGE_ALIGN; + ATIM_InitStruct.CounterDirection = ATIM_COUNTING_UP; + ATIM_InitStruct.CounterOPMode = ATIM_OP_MODE_REPETITIVE; + ATIM_InitStruct.OverFlowMask = ENABLE; + ATIM_InitStruct.Prescaler = ATIM_Prescaler_DIV1; // ʱ1MHz + ATIM_InitStruct.ReloadValue = PWM_PERIOD; // 100us + ATIM_InitStruct.RepetitionCounter = 0; + ATIM_InitStruct.UnderFlowMask = DISABLE; + ATIM_Init(&ATIM_InitStruct); + + ATIM_OCInitStruct.BufferState = DISABLE; + ATIM_OCInitStruct.OCDMAState = DISABLE; + ATIM_OCInitStruct.OCInterruptSelect = ATIM_OC_IT_NONE; + ATIM_OCInitStruct.OCInterruptState = DISABLE; + ATIM_OCInitStruct.OCMode = ATIM_OCMODE_PWM1; + ATIM_OCInitStruct.OCPolarity = ATIM_OCPOLARITY_NONINVERT; + ATIM_OC1AInit(&ATIM_OCInitStruct); + ATIM_OC2AInit(&ATIM_OCInitStruct); + ATIM_OC3AInit(&ATIM_OCInitStruct); + + ATIM_SetCompare1A(0); + ATIM_SetCompare2A(0); + ATIM_SetCompare3A(0); + ATIM_PWMOutputConfig(OCREFA_TYPE_SINGLE, OUTPUT_TYPE_ALONE, -1); + ATIM_CtrlPWMOutputs(ENABLE); + ATIM_Cmd(ENABLE); + + CW_ATIM->MSCR_f.CCDS = 1; // DMA ܿ + ATIM_OC4Init(ENABLE, ATIM_OC_IT_UP_COUNTER, ENABLE, DISABLE, DISABLE); + ATIM_SetCompare4(PWM_PERIOD/2); // ʱ + ATIM_Cmd(ENABLE); +} + +void ATIM_IRQHandler(void) +{ + if (ATIM_GetITStatus(ATIM_IT_OVF)) + { + ATIM_ClearITPendingBit(ATIM_IT_OVF); + } +} + +//steP,ΪǰPWM_ON_flag=1ʱPWM +void Commutation(unsigned int step,unsigned int PWM_ON_flag) +{ + if(PWM_ON_flag==0||MOTORSTATE==STATEERROR||MOTORSTATE==STATEERROROVER) + { + CW_ATIM->CH1CCRA=0;CW_ATIM->CH2CCRA=0;CW_ATIM->CH3CCRA=0; + PWM_AL_OFF; PWM_BL_OFF; PWM_CL_OFF; + return; + } + if(step==0||step==5){ PWM_AL_OFF; PWM_CL_OFF;}//AB + else if(step==1||step==2){ PWM_AL_OFF; PWM_BL_OFF; }//AC + else if(step==3||step==4){ PWM_BL_OFF; PWM_CL_OFF; }//BA + + if(step==0||step==1){ CW_ATIM->CH2CCRA=0;CW_ATIM->CH3CCRA=0;CW_ATIM->CH1CCRA=OutPwmValue; } + if(step==2||step==3){ CW_ATIM->CH1CCRA=0;CW_ATIM->CH3CCRA=0;CW_ATIM->CH2CCRA=OutPwmValue; } + if(step==4||step==5){ CW_ATIM->CH1CCRA=0;CW_ATIM->CH2CCRA=0;CW_ATIM->CH3CCRA=OutPwmValue; } + + + if(step==0||step==5){PWM_BL_ON;}//AB + else if(step==1||step==2){PWM_CL_ON;}//AC + else if(step==3||step==4){PWM_AL_ON;}//BA + STEP_last=step; +} + +//ռձ +void UPPWM(void) +{ + if(STEP_last==0||STEP_last==1){ CW_ATIM->CH2CCRA=0;CW_ATIM->CH3CCRA=0; CW_ATIM->CH1CCRA=OutPwmValue; } + if(STEP_last==2||STEP_last==3){ CW_ATIM->CH1CCRA=0;CW_ATIM->CH3CCRA=0;CW_ATIM->CH2CCRA=OutPwmValue; } + if(STEP_last==4||STEP_last==5){ CW_ATIM->CH1CCRA=0;CW_ATIM->CH2CCRA=0;CW_ATIM->CH3CCRA=OutPwmValue; } +} + +//ʱʼ +void Halltimer_init(void) +{ + GTIM_InitTypeDef GTIM_InitStruct; + GTIM_ICInitTypeDef GTIM_ICInitStruct; + GPIO_InitTypeDef GPIO_InitStruct; + + __RCC_GTIM2_CLK_ENABLE(); + __RCC_GPIOA_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode =GPIO_MODE_INPUT_PULLUP;// GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_15 |GPIO_PIN_1; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode =GPIO_MODE_INPUT_PULLUP;// GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_10; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + + PA15_AFx_GTIM2CH1(); + PA01_AFx_GTIM2CH2(); + PB10_AFx_GTIM2CH3(); + + __disable_irq(); + NVIC_EnableIRQ(GTIM2_IRQn); + __enable_irq(); + + GTIM_InitStruct.Mode = GTIM_MODE_TIME; + GTIM_InitStruct.OneShotMode = GTIM_COUNT_CONTINUE; + GTIM_InitStruct.Prescaler = GTIM_PRESCALER_DIV1; + GTIM_InitStruct.ReloadValue = 0xFFFF; + GTIM_InitStruct.ToggleOutState = DISABLE; + GTIM_TimeBaseInit(CW_GTIM2, >IM_InitStruct); + + GTIM_ICInitStruct.CHx = GTIM_CHANNEL1; + GTIM_ICInitStruct.ICFilter = GTIM_CHx_FILTER_PCLK_N2; + GTIM_ICInitStruct.ICInvert = GTIM_CHx_INVERT_OFF; + GTIM_ICInitStruct.ICPolarity = GTIM_ICPolarity_BothEdge; + GTIM_ICInit(CW_GTIM2, >IM_ICInitStruct); + + GTIM_ICInitStruct.CHx = GTIM_CHANNEL2; + GTIM_ICInit(CW_GTIM2, >IM_ICInitStruct); + + GTIM_ICInitStruct.CHx = GTIM_CHANNEL3; + GTIM_ICInit(CW_GTIM2, >IM_ICInitStruct); + + GTIM_ITConfig(CW_GTIM2, GTIM_IT_CC1 | GTIM_IT_CC2 | GTIM_IT_CC3, ENABLE); + GTIM_Cmd(CW_GTIM2, ENABLE); +} + +//źŶȡ +unsigned char HALL_Check(void) +{ + static unsigned char hallerrnum=0; + unsigned char x=0; + + if(GPIO_ReadPin(CW_GPIOA,GPIO_PIN_15)!=0)x=1; + if(GPIO_ReadPin(CW_GPIOA,GPIO_PIN_1)!=0)x|=0x2; + if(GPIO_ReadPin(CW_GPIOB,GPIO_PIN_10)!=0)x|=0x4; + // printf("X=%x\n",x); + if(x==0||x==7) + {hallerrnum++;if(hallerrnum>=10){hallerrnum=10;ErrorCode=2;}} + else hallerrnum=0; + + return x; +} + +//źű任 +void GTIM2_IRQHandler(void) +{ + unsigned char x = 0; + + /* USER CODE BEGIN */ + if (GTIM_GetITStatus(CW_GTIM2, GTIM_IT_CC1)) + { + GTIM_ClearITPendingBit(CW_GTIM2, GTIM_IT_CC1); + } + + if (GTIM_GetITStatus(CW_GTIM2, GTIM_IT_CC2)) + { + GTIM_ClearITPendingBit(CW_GTIM2, GTIM_IT_CC2); + } + + if (GTIM_GetITStatus(CW_GTIM2, GTIM_IT_CC3)) + { + GTIM_ClearITPendingBit(CW_GTIM2, GTIM_IT_CC3); + } + + x=HALL_Check(); + if(x==0||x==7){return;} + + HALLcount++;HALLcount1++; + Cur_step=STEP_TAB[Dir][x-1]; + if(Motor_Start_F==1&&ErrorCode==0) + Commutation(Cur_step,Motor_Start_F); +} + +// +void HALL_MOTOR_START(void) +{ + unsigned char x=0; + + x=HALL_Check(); + if(x==0||x==7){return;} + Cur_step=STEP_TAB[Dir][x-1]; + RealS1=0; + Motor_Start_F=1; + Commutation(Cur_step,Motor_Start_F); +} + +//ֹͣ +void MOTOR_STOP0(void) +{ + Motor_Start_F=0; + Commutation(0,0); +} + + diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/MOTORCONTROL.C b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/MOTORCONTROL.C new file mode 100644 index 0000000..ba1e2b5 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/MOTORCONTROL.C @@ -0,0 +1,40 @@ +#include "motorcontrol.h" + +//const unsigned int PWM_EN_TAB[6]={0x001,0x001,0x010,0x010,0x100,0x100};// 6PWMʹܿ AB,AC,BC,BA,CA,CB +//const unsigned char STEP_TAB[6]={1,3,2,5,0,4};//{4,0,5,2,3,1};// + +//unsigned int Cur_step=0; //ǰHALL״̬ +//unsigned int Motor_Start_F=0; //б־ +//unsigned int OutPwm=0; + + +////steP,ΪǰOutPwmValue PWMֵPWM_ON_flag=1ʱPWM +//void Commutation(unsigned int step,unsigned int OutPwmValue,unsigned int PWM_ON_flag) +//{ +// if(PWM_ON_flag==0) +// { +// CW_ATIM->CH1CCRA=0;CW_ATIM->CH2CCRA=0;CW_ATIM->CH3CCRA=0; +// ATIM_CtrlPWMOutputs(DISABLE); +// PWM_AL_OFF; PWM_BL_OFF; PWM_CL_OFF; +// return; +// } +// +// PWM_AL_OFF; PWM_BL_OFF; PWM_CL_OFF; +// +// if(step==0||step==1){ CW_ATIM->CH1CCRA=OutPwmValue;CW_ATIM->CH2CCRA=0;CW_ATIM->CH3CCRA=0; } +// if(step==2||step==3){ CW_ATIM->CH1CCRA=0;CW_ATIM->CH2CCRA=OutPwmValue;CW_ATIM->CH3CCRA=0; } +// if(step==4||step==5){ CW_ATIM->CH1CCRA=0;CW_ATIM->CH2CCRA=0;CW_ATIM->CH3CCRA=OutPwmValue; } +// +// if(step==0||step==5){PWM_AL_OFF; PWM_CL_OFF;PWM_BL_ON;}//AB +// else if(step==1||step==2){ PWM_AL_OFF; PWM_BL_OFF; PWM_CL_ON;}//AC +// else if(step==3||step==4){ PWM_BL_OFF; PWM_CL_OFF; PWM_AL_ON;}//BA +// +// ATIM_CtrlPWMOutputs(ENABLE); +//} + +//void HALL_MOTOR_START(void) +//{ +// unsigned int x; +// Cur_step=STEP_TAB[(CW_GPIOA->IDR&0x0007)-1]; +// Commutation(Cur_step,OutPwm,Motor_Start_F); +//} diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/MOTORCONTROL.H b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/MOTORCONTROL.H new file mode 100644 index 0000000..4bfbef9 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/MOTORCONTROL.H @@ -0,0 +1,43 @@ + +#include "MAIN.h" + +///*********************** PWM definition *************************/ + +//#define PWM_AN_PORT (CW_GPIOB) +//#define PWM_AN_PIN (GPIO_PIN_13) + +//#define PWM_BN_PORT (CW_GPIOB) +//#define PWM_BN_PIN (GPIO_PIN_14) + +//#define PWM_CN_PORT (CW_GPIOB) +//#define PWM_CN_PIN (GPIO_PIN_15) + +////Ϲܵƣ¹ܿؿ, ¹ܸߵƽعܵͨ +//#define PWM_AL_OFF GPIO_WritePin(PWM_AN_PORT,PWM_AN_PIN,GPIO_Pin_SET) +//#define PWM_BL_OFF GPIO_WritePin(PWM_BN_PORT,PWM_BN_PIN,GPIO_Pin_SET) +//#define PWM_CL_OFF GPIO_WritePin(PWM_CN_PORT,PWM_CN_PIN,GPIO_Pin_SET) + +//#define PWM_AL_ON GPIO_WritePin(PWM_AN_PORT,PWM_AN_PIN,GPIO_Pin_RESET) +//#define PWM_BL_ON GPIO_WritePin(PWM_BN_PORT,PWM_BN_PIN,GPIO_Pin_RESET) +//#define PWM_CL_ON GPIO_WritePin(PWM_CN_PORT,PWM_CN_PIN,GPIO_Pin_RESET) + +//#define PWM_FRQ (20000) //PWMƵ(HZ) +#define TS 7200 +////(unsigned short)(72*1000*1000/PWM_FRQ) //PWM_TIM +// +//#define OUTMAXPWM TS*1.05 +//#define OUTMINPWM TS*0.15 + +//extern const unsigned char STEP_TAB[6]; + +//extern unsigned int ErrorCode; //д +//extern unsigned int Cur_step; //ǰHALL״̬ +//extern unsigned int SpeedTime; //HALLлʱ +//extern unsigned int Motor_Start_F; //б־ +//extern unsigned int OutPwm; //PWMֵ + + +//extern void Commutation(unsigned int step,unsigned int OutPwmValue,unsigned int PWM_ON_flag); + +//extern void HALL_MOTOR_START(void); +///////////////////////// diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/OLED_I2C.c b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/OLED_I2C.c new file mode 100644 index 0000000..ae6e3be --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/OLED_I2C.c @@ -0,0 +1,628 @@ + +#include "OLED_I2C.h" + +#include "font.h" + + +sFONT *Fonttemp = &Font8x16; +//sFONT *Fonttemp = &Font16x24; +//sFONT *Fonttemp = &Font24x32; + +short I2C_OFFSET_W = I2C_PIC_W / 2 - I2C_OLED_W / 2; +short I2C_OFFSET_H = I2C_PIC_H / 2 - I2C_OLED_H / 2; //ʾ뻭ƫ + +uint8_t I2C_P_x = 0, I2C_P_y = 0; //OLED_Printַ +uint8_t I2C_OLED_GRAM[I2C_PIC_H][I2C_PIC_W]; //256*128ʾ(64,32)~(191,95) + + + +void I2C_init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + I2C_InitTypeDef I2C_InitStruct; + + __RCC_I2C1_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); + + PB06_AFx_I2C1SCL(); + PB07_AFx_I2C1SDA(); + + GPIO_InitStructure.Pins = GPIO_PIN_6 | GPIO_PIN_7; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD; ////I2C뿪© + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + + I2C_InitStruct.I2C_BaudEn = ENABLE; + I2C_InitStruct.I2C_Baud = 0x04; + I2C_InitStruct.I2C_FLT = DISABLE; + I2C_InitStruct.I2C_AA = DISABLE; //DISABLE ENABLE + + I2C1_DeInit(); + I2C_Master_Init(CW_I2C1,&I2C_InitStruct);//ʼģ + I2C_Cmd(CW_I2C1,ENABLE); //ģʹ +} + +void I2C_MasterWriteEepromData1(I2C_TypeDef *I2Cx,uint8_t u8Addr,uint8_t *pu8Data,uint32_t u32Len) +{ + uint8_t u8i=0,u8State; + I2C_GenerateSTART(I2Cx, ENABLE); + while(1) + { + while(0 == I2C_GetIrq(I2Cx)) + {;} + u8State = I2C_GetState(I2Cx); + switch(u8State) + { + case 0x08: //STARTź + I2C_GenerateSTART(I2Cx, DISABLE); + I2C_Send7bitAddress(I2Cx, OLED_ADDRESS,0X00); //豸ַ + break; + case 0x18: //SLA+Wź,ACKյ + I2C_SendData(I2Cx,u8Addr);//豸ڴַ + break; + case 0x28: //1ֽݣEEPROMmemoryַҲͺҲ + I2C_SendData(I2Cx,pu8Data[u8i++]); + break; + case 0x20: //SLA+WӻNACK + case 0x38: //ڷ SLA+W ׶λ߷ݽ׶ζʧٲ ڷ SLA+R ׶λ߻Ӧ NACK ׶ζʧٲ + I2C_GenerateSTART(I2Cx, ENABLE); + break; + case 0x30: //һֽںӻNACK + I2C_GenerateSTOP(I2Cx, ENABLE); + break; + default: + break; + } + if(u8i>u32Len) + { + I2C_GenerateSTOP(I2Cx, ENABLE);//˳ֹܵͣ + I2C_ClearIrq(I2Cx); + break; + } + I2C_ClearIrq(I2Cx); + } +} + + +void WriteCmd(unsigned char I2C_Command)//д +{ + I2C_MasterWriteEepromData1(CW_I2C1,COM,&I2C_Command,1); +} + +void WriteDat(unsigned char I2C_Data)//д +{ + I2C_MasterWriteEepromData1(CW_I2C1,DAT,&I2C_Data,1); +} + +//OLEDʾ +void I2C_OLED_DisPlay_On(void) +{ + WriteCmd(0x8D); //ɱʹ + WriteCmd(0x14); //ɱ + WriteCmd(0xAF); //Ļ +} + +//رOLEDʾ +void I2C_OLED_DisPlay_Off(void) +{ + WriteCmd(0x8D); //ɱʹ + WriteCmd(0x10); //رյɱ + WriteCmd(0xAF); //رĻ +} + + +//Դ浽OLED +void I2C_OLED_UPdata(void) +{ + uint8_t i, n; + //ˮƽģʽ + WriteCmd(0x21); // + WriteCmd(0x00); //ʼַ + WriteCmd(0x7f); //нַ + WriteCmd(0x22); //ҳ + WriteCmd(0x00); //ҳʼַ + WriteCmd(0x07); //ҳַ + for (i = 0; i < I2C_OLED_H; i++) + { + for (n = 0; n < I2C_OLED_W; n++) + { + WriteDat(I2C_OLED_GRAM[i + I2C_OFFSET_H][n + I2C_OFFSET_W]); + } + } +} + +/** + * @brief ijߵ + * @param Line:ѡҪУ01234567 + * @param Start_x:xῪʼ + * @param End_x: x + * @retval + */ +void I2C_OLED_Clear_Line(uint8_t Line,uint8_t Start_x,uint8_t End_x) +{ + for(uint8_t x=Start_x;x= r * r) + { + I2C_OLED_DrawPoint(x + a, y - b); + I2C_OLED_DrawPoint(x - a, y - b); + I2C_OLED_DrawPoint(x - a, y + b); + I2C_OLED_DrawPoint(x + a, y + b); + + I2C_OLED_DrawPoint(x + b, y + a); + I2C_OLED_DrawPoint(x + b, y - a); + I2C_OLED_DrawPoint(x - b, y - a); + I2C_OLED_DrawPoint(x - b, y + a); + + a++; + num = (a * a + b * b) - r * r; //㻭ĵԲĵľ + if (num > 0) + { + b--; + a--; + } + } +} + + +void I2C_OLED_ShowChar(uint8_t x, uint8_t y, char chr) +{ + uint8_t i, m, temp, size = Fonttemp->Height * Fonttemp->Width / 8; + uint8_t x0 = x; + uint8_t Pfont[size]; + + //ȡַ + GetConslonsCode(Pfont, chr, Fonttemp); + + // size=Fonttemp->Height*Fonttemp->Width/8; //õһַӦռֽ + for (i = 0; i < size; i++) + { + temp = Pfont[i]; + for (m = 0; m < 8; m++) //д + { + if (temp & 0x80) + I2C_OLED_DrawPoint(x, y); + else + I2C_OLED_ClearPoint(x, y); + temp <<= 1; + x++; + } + if ((x - x0) == (Fonttemp->Width)) + { + x = x0; + y++; + } + } +} + + +void I2C_OLED_ShowChar_CH(uint8_t x, uint8_t y, uint16_t usChar) +{ + uint8_t rowCount, bitCount; + uint8_t ucBuffer[WIDTH_CH_CHAR * HEIGHT_CH_CHAR / 8]; + uint16_t usTemp; + uint8_t x0 = x; + //ȡģ + GetGBKCode(ucBuffer, usChar); + + for (rowCount = 0; rowCount < HEIGHT_CH_CHAR; rowCount++) + { + /* ȡֽڵݣlcdϼһֵһ */ + usTemp = ucBuffer[rowCount * 2]; //ȡλ + usTemp = (usTemp << 8); + usTemp |= ucBuffer[rowCount * 2 + 1]; //ȡλ + + for (bitCount = 0; bitCount < WIDTH_CH_CHAR; bitCount++) + { + if (usTemp & (0x8000 >> bitCount)) //λǰ + I2C_OLED_DrawPoint(x, y); + else + I2C_OLED_ClearPoint(x, y); + x++; + } + if (x - x0 == WIDTH_CH_CHAR) + { + x = x0; + y++; + } + } +} + +//dir ƶ +//pix ƶ +//cir ߽ʱص߽磬ѭЧ,0ʾѭ1ʾѭ +void I2C_OLED_Move(uint8_t dir, uint8_t pix, uint8_t cir) //Ļʾƶ +{ + switch (dir) + { + case UP: + { + I2C_OFFSET_H += pix; + if (I2C_OFFSET_H >= I2C_PIC_H - I2C_OLED_H) + { + if (cir == 0) + I2C_OFFSET_H = I2C_PIC_H - I2C_OLED_H; + else + I2C_OFFSET_H = 0; + } + break; + } + case DOWN: + { + I2C_OFFSET_H -= pix; + if (I2C_OFFSET_H <= 0) + { + if (cir == 0) + I2C_OFFSET_H = 0; + else + I2C_OFFSET_H = I2C_PIC_H - I2C_OLED_H; + } + break; + } + case LEFT: + { + I2C_OFFSET_W += pix; + if (I2C_OFFSET_W >= I2C_PIC_W - I2C_OLED_W) + { + if (cir == 0) + I2C_OFFSET_W = I2C_PIC_W - I2C_OLED_W; + else + I2C_OFFSET_W = 0; + } + break; + } + case RIGHT: + { + I2C_OFFSET_W -= pix; + if (I2C_OFFSET_W <= 0) + { + if (cir == 0) + I2C_OFFSET_W = 0; + else + I2C_OFFSET_W = I2C_PIC_W - I2C_OLED_W; + } + break; + } + } + I2C_OLED_UPdata(); +} + +/** + * @brief תַ + * @param usX ǰX + * @param usY ǰY + * @param pStr ҪʾӢַ + * @note + * @retval ַеתַشַַ + */ +char* OLED_StrEscCharacter(uint8_t *x,uint8_t *y,char *chr) +{ + uint8_t TabSize; + while(*chr < ' '&&*chr != '\0') + { + switch (*chr) + { + case '\b': //˸BS + { + *x = *x - Fonttemp->Width; + break; + } + case '\n': //УLF + { + switch(Fonttemp->Height) + { + case 32:I2C_OLED_Clear_Line((*y/8)+3,*x,128);//3 + case 24:I2C_OLED_Clear_Line((*y/8)+2,*x,128);//2 + case 16:I2C_OLED_Clear_Line((*y/8)+1,*x,128);//1 + case 8:I2C_OLED_Clear_Line((*y/8),*x,128);break;//0 + } + *x = 0; + *y = *y + Fonttemp->Height; + if (*y > (I2C_OLED_H * 8) - Fonttemp->Height) //Ļд + { + I2C_OLED_Move(UP, 2, 0); + *y = *y - Fonttemp->Height; + } + break; + } + case '\r': //سCR + { + switch(Fonttemp->Height) + { + case 32:I2C_OLED_Clear_Line((*y/8)+3,*x,128);//3 + case 24:I2C_OLED_Clear_Line((*y/8)+2,*x,128);//2 + case 16:I2C_OLED_Clear_Line((*y/8)+1,*x,128);//1 + case 8:I2C_OLED_Clear_Line((*y/8),*x,128);break;//0 + } + *x = 0; + *y = *y + Fonttemp->Height; + if (*y > (I2C_OLED_H * 8) - Fonttemp->Height) //Ļд + { + I2C_OLED_Move(UP, 2, 0); + *y = *y - Fonttemp->Height; + } + break; + } + case '\t': //ˮƽƱHT + { + TabSize = 4 * Fonttemp->Width - (*x % (4 * Fonttemp->Width)); + switch(Fonttemp->Height) + { + case 32:I2C_OLED_Clear_Line((*y/8)+3,*x,*x+TabSize);//3 + case 24:I2C_OLED_Clear_Line((*y/8)+2,*x,*x+TabSize);//2 + case 16:I2C_OLED_Clear_Line((*y/8)+1,*x,*x+TabSize);//1 + case 8:I2C_OLED_Clear_Line((*y/8),*x,*x+TabSize);break;//0 + } + *x = *x + TabSize; + break; + } + } + chr++; + } + return chr; +} + +//ʾַ +//x,y: +//size1:С +//*chr:ַʼַ +void I2C_OLED_ShowString(uint8_t x, uint8_t y, char *chr) +{ + uint16_t chinese_chr; + while (*chr != '\0') //жDzǷǷַ! + { + chr=OLED_StrEscCharacter(&x,&y,chr); + if( * chr == '\0' ) + break; + if (*chr < 127) //Ӣַ + { + I2C_OLED_ShowChar(x, y, *chr); + x += Fonttemp->Width; + if (x > 128 - Fonttemp->Width) // + { + x = 0; + y += Fonttemp->Height; + } + chr++; + } + else if (*chr > 127) //ַ + { + chinese_chr = *(uint16_t *)chr; + chinese_chr = (chinese_chr << 8) + (chinese_chr >> 8); //õַ + I2C_OLED_ShowChar_CH(x, y, chinese_chr); + x += WIDTH_CH_CHAR; + if (x > 128 - WIDTH_CH_CHAR) // + { + x = 0; + y += HEIGHT_CH_CHAR; + } + chr += 2; + } + } +} + +//m^n +uint32_t I2C_OLED_Pow(uint8_t m, uint8_t n) +{ + uint32_t result = 1; + while (n--) + { + result *= m; + } + return result; +} + +//strָҪʾַָ +//sizeʾַֺ +void I2C_OLED_Print(char *str) //OLEDϴӡַ +{ + uint16_t chinese_str; + + while (*str != '\0') + { + str=OLED_StrEscCharacter(&I2C_P_x,&I2C_P_y,str); + if( * str == '\0' ) + break; + if (*str < 127) //Ӣַ + { + I2C_OLED_ShowChar(I2C_P_x, I2C_P_y, *str); + I2C_P_x = I2C_P_x + Fonttemp->Width; + if (I2C_P_x > 128 - Fonttemp->Width) // + { + I2C_P_x = 0; + I2C_P_y = I2C_P_y + Fonttemp->Height; + if (I2C_P_y > 32 - Fonttemp->Height) //Ļд + { + I2C_OLED_Move(UP, 2, 0); + I2C_P_y = I2C_P_y - Fonttemp->Height; + } + } + str++; + } + else //ַ + { + chinese_str = *(uint16_t *)str; + chinese_str = (chinese_str << 8) + (chinese_str >> 8); //õַ + I2C_OLED_ShowChar_CH(I2C_P_x, I2C_P_y, chinese_str); + I2C_P_x += WIDTH_CH_CHAR; + + if (I2C_P_x > 128 - WIDTH_CH_CHAR) // + { + I2C_P_x = 0; + I2C_P_y = I2C_P_y + HEIGHT_CH_CHAR; + if (I2C_P_y > 32 - HEIGHT_CH_CHAR) //Ļд + { + I2C_OLED_Move(UP, 2, 0); + I2C_P_y = I2C_P_y - HEIGHT_CH_CHAR; + } + } + str += 2; //һֽ + } + } + I2C_OLED_UPdata(); +} + + +void I2C_OLED_ShowPicture(uint8_t x, uint8_t y, uint8_t Bmp_W, uint8_t Bmp_H, uint8_t *BMP) +{ + uint8_t x0, y0; //ʱxyֵ + x0 = x; + y0 = y; + for (y = y0; y < y0 + Bmp_H; y++) + { + for (x = x0; x < x0 + Bmp_W; x++) + { + I2C_OLED_GRAM[y + I2C_OFFSET_H][x + I2C_OFFSET_W] = *BMP; + BMP++; + } + } + I2C_OLED_UPdata(); +} + + +//OLEDijʼ +void I2C_OLED_Init(void) +{ +// delay1ms(200); + + WriteCmd(0xAE);//رʾ + + WriteCmd(0x40);//---set low column address + WriteCmd(0xB0);//---set high column address + + WriteCmd(0xC8);//-not offset + + WriteCmd(0x81);//öԱȶ + WriteCmd(0xff); + + WriteCmd(0xa1);//ض + + WriteCmd(0xa6);// + + WriteCmd(0xa8);//· + WriteCmd(0x1f); + + WriteCmd(0xd3); + WriteCmd(0x00); + + WriteCmd(0xd5); + WriteCmd(0xf0); + + WriteCmd(0xd9); + WriteCmd(0x22); + + WriteCmd(0xda); + WriteCmd(0x02); + + WriteCmd(0x20); //-Set Page Addressing Mode (0x00/0x01/0x02) + //WriteCmd(0x02);//ҳַģʽ + WriteCmd(0x00); //ˮƽѰַģʽ + + WriteCmd(0xdb); + WriteCmd(0x49); + + WriteCmd(0x8d); + WriteCmd(0x14); + + WriteCmd(0xaf); + +} diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/OLED_I2C.h b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/OLED_I2C.h new file mode 100644 index 0000000..258d1e4 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/OLED_I2C.h @@ -0,0 +1,51 @@ +#ifndef __OLED_I2C_H +#define __OLED_I2C_H + +#include "main.h" + +#define OLED_ADDRESS 0x78 //ͨ0R,0x780x7Aַ -- Ĭ0x78 +#define COM 0x00 // OLED ָֹ޸ģ д +#define DAT 0x40 // OLED ݣֹ޸ģ д + + +#define UP 8 // +#define DOWN 2 // +#define LEFT 4 // +#define RIGHT 6 // + +#define I2C_PIC_W 128 +#define I2C_PIC_H 8 //С +#define I2C_OLED_W 128 +#define I2C_OLED_H 8 //ʾС + + + +static void I2C_OLED_WR_Byte(unsigned dat,unsigned cmd); +static void I2C_OLED_Write_Command(unsigned char IIC_Command); +static void I2C_OLED_Write_Data(unsigned char IIC_Data); +static void I2C_OLED_Byte_Write(uint8_t addr,uint8_t data); + +void I2C_OLED_Init(void); +void I2C_init(void); + +void I2C_OLED_ColorTurn(uint8_t i); +void I2C_OLED_DisplayTurn(uint8_t i); +void I2C_OLED_DisPlay_On(void); +void I2C_OLED_DisPlay_Off(void); +void I2C_OLED_UPdata(void); +void I2C_OLED_Clear_Line(uint8_t Line,uint8_t Start_x,uint8_t End_x); +void I2C_OLED_Clear(uint8_t OLEDShowUP); +void I2C_OLED_DrawPoint(uint8_t x,uint8_t y); +void I2C_OLED_ClearPoint(uint8_t x,uint8_t y); +void I2C_OLED_DrawLine(uint8_t x1,uint8_t y1,uint8_t x2,uint8_t y2); +void I2C_OLED_DrawCircle(uint8_t x,uint8_t y,uint8_t r); +void I2C_OLED_ShowChar(uint8_t x,uint8_t y,char chr); +void I2C_OLED_ShowChar_CH(uint8_t x,uint8_t y,uint16_t usChar); +void I2C_OLED_ShowString(uint8_t x,uint8_t y,char *chr); +void I2C_OLED_Move(uint8_t dir,uint8_t pix,uint8_t cir); +void I2C_OLED_Print(char *str); +void I2C_OLED_WR_BP(uint8_t x,uint8_t y); +void I2C_OLED_ShowPicture(uint8_t x,uint8_t y,uint8_t Bmp_W,uint8_t Bmp_H,uint8_t *BMP); + + +#endif diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/UART_Pri.c b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/UART_Pri.c new file mode 100644 index 0000000..113c94b --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/UART_Pri.c @@ -0,0 +1,104 @@ + +#include "main.h" + + +//UARTx +#define DEBUG_USARTx CW_UART3 +#define DEBUG_USART_CLK RCC_APB1_PERIPH_UART3 +#define DEBUG_USART_APBClkENx RCC_APBPeriphClk_Enable1 +#define DEBUG_USART_BaudRate 115200 +#define DEBUG_USART_UclkFreq 8000000 + +//UARTx GPIO +#define DEBUG_USART_GPIO_CLK RCC_AHB_PERIPH_GPIOB +#define DEBUG_USART_TX_GPIO_PORT CW_GPIOB +#define DEBUG_USART_TX_GPIO_PIN GPIO_PIN_6 +#define DEBUG_USART_RX_GPIO_PORT CW_GPIOB +#define DEBUG_USART_RX_GPIO_PIN GPIO_PIN_7 + +//GPIO AF +#define DEBUG_USART_AFTX PB06_AFx_UART3TXD() +#define DEBUG_USART_AFRX PB07_AFx_UART3RXD() + + + +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + + +/** + * @brief UART + * + */ +void UART_Configuration(void) +{ + USART_InitTypeDef USART_InitStructure; + + GPIO_InitTypeDef GPIO_InitStructure; + + //UART TX RX + DEBUG_USART_AFTX; + DEBUG_USART_AFRX; + + GPIO_InitStructure.Pins = DEBUG_USART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pins = DEBUG_USART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStructure); + + + USART_InitStructure.USART_BaudRate = DEBUG_USART_BaudRate; + USART_InitStructure.USART_Over = USART_Over_16; + USART_InitStructure.USART_Source = USART_Source_PCLK; + USART_InitStructure.USART_UclkFreq = DEBUG_USART_UclkFreq; + USART_InitStructure.USART_StartBit = USART_StartBit_FE; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(DEBUG_USARTx, &USART_InitStructure); +} + +/** + * @brief Retargets the C library printf function to the USART. + * + */ +PUTCHAR_PROTOTYPE +{ + USART_SendData_8bit(DEBUG_USARTx, (uint8_t)ch); + + while (USART_GetFlagStatus(DEBUG_USARTx, USART_FLAG_TXE) == RESET); + + return ch; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + + + diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/compu.c b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/compu.c new file mode 100644 index 0000000..4c00cea --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/compu.c @@ -0,0 +1,76 @@ +#include "compu.h" + +void SampleSpeed(void) +{ + unsigned int tem=0; + unsigned int st=0; + + st=SampleData[2]; + + if(st=ISH*1000&&ErrorCode==0) // + { + + IErCount++; + if(IErCount>=NumErr) + { + ErrorCode=4; + + } + } + else IErCount=0; + + t =SampleData[3]; + t=t/4096*5.0/RV1*(RV1+RV2); + CanshuV=t*10; //ɼĸߵѹŴ10 + + if(CanshuV>=VSH*10&&ErrorCode==0) //ѹж + { + VErCount++; + if(VErCount>=NumErr) + {ErrorCode=6;} + } + else VErCount=0; + +} diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/compu.h b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/compu.h new file mode 100644 index 0000000..d5fd06b --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/compu.h @@ -0,0 +1,4 @@ +#include "globalv.h" + +void SampleSpeed(void); +void SampleVI(void); diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/control.c b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/control.c new file mode 100644 index 0000000..f7412db --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/control.c @@ -0,0 +1,133 @@ +#include "control.h" + +extern unsigned char save_flag; +extern void Flash_Save(void); + +void MotorStartCheck(void) +{ + if(MOTORSTATE==STATEERROR)return; + + if(SetSpeed>0&&startflag==1) + { + MOTORSTATE=STATESTARTPID; + Dir=dirflag; + HALLcount=0; + HALLcount1=0; + HALLcountTemp=0; + } +} + +void MotorStartPID(void) +{ + if(MOTORSTATE==STATEERROR)return; + + PID_init(); + PIDcompute(MINSPEED,0); + HALL_MOTOR_START(); + + TargS1=SetSpeed; + MOTORSTATE=STATERUNPID; +} + +void MotorRunPID(void) +{ + + if(MOTORSTATE==STATEERROR)return; + if(SetSpeed==0||startflag==0) //ֹͣź + { + MOTORSTATE=STATESTOP; + } + + TargS1=SetSpeed; + if(TimeCountPID>=20)//ʵʱٶȲʱPID + { + TimeCountPID=0; + RealS1=HALLcountTemp*500/MPolePairs;//HALLcount*100*60/6/POLEPAIRS; + PIDcompute(TargS1,RealS1); + } +} + +void MotorStop(void) +{ + if(MOTORSTATE==STATEERROR)return; + Motor_Start_F=0; + MOTOR_STOP0(); + + if(RealS==0) + { + MOTORSTATE=STATESTARTCHECK; //ͣл + } +} + +void MotorError(void) +{ + MOTOR_STOP0(); + Motor_Start_F=0; + MOTORSTATE=STATEERROROVER; + printf("MotorError\n"); +} + +void MotorBreak(void) +{ + unsigned int dd; + if(GPIO_ReadPin(BKIN_GPIO_PORT,BKIN_GPIO_PIN)==GPIO_Pin_RESET) + { + for(dd=0;dd<500;dd++) + {;} + if(GPIO_ReadPin(BKIN_GPIO_PORT,BKIN_GPIO_PIN)==GPIO_Pin_RESET) + { + MOTOR_STOP0(); + Motor_Start_F=0; + while(GPIO_ReadPin(BKIN_GPIO_PORT,BKIN_GPIO_PIN)==GPIO_Pin_RESET); + } + } +} + +void MotorErrorOver(void) +{ + unsigned char times=0; + + times=0; + + LEDOFF();TimeCountTemp=0; + while(TimeCountTemp<200); + while(1) //ϣָʾ˸ + { + SampleSpeed(); + if(SetSpeed == 0) //ʱٺָ + { + ErrorCode = 0; + WaitStart(); + GPIO_WritePin(VOUT_EN_GPIO_PORT,VOUT_EN_GPIO_PIN,GPIO_Pin_SET); + break; + } + + } +} + +void WaitStart(void) +{ + if(SetSpeed==0) MOTORSTATE=STATESTARTCHECK; +} + +void EnDirCheck(void) +{ + + + if((GPIO_ReadPin(EN_GPIO_PORT,EN_GPIO_PIN)==GPIO_Pin_SET)\ + &&(GPIO_ReadPin(DR_GPIO_PORT,DR_GPIO_PIN)==GPIO_Pin_SET) ) + { + LevelSet = 2; + } + else if((GPIO_ReadPin(EN_GPIO_PORT,EN_GPIO_PIN)==GPIO_Pin_RESET)\ + &&(GPIO_ReadPin(DR_GPIO_PORT,DR_GPIO_PIN)==GPIO_Pin_SET) ) + { + LevelSet = 3; + } + if((GPIO_ReadPin(EN_GPIO_PORT,EN_GPIO_PIN)==GPIO_Pin_SET)\ + &&(GPIO_ReadPin(DR_GPIO_PORT,DR_GPIO_PIN)==GPIO_Pin_RESET) ) + { + LevelSet = 1; + } + printf("Level=%d\n",LevelSet); +} diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/control.h b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/control.h new file mode 100644 index 0000000..a744ee2 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/control.h @@ -0,0 +1,20 @@ +#include "globalv.h" +#include "compu.h" +#include "motor.h" +#include "pid.h" + +void MotorStartCheck(void); +void MotorStartDealy(void); +void MotorStartOPEN(void); +void MotorRunOPEN(void); +void MotorStartPID(void); +void MotorRunPID(void); +void MotorStop(void); +void MotorError(void); +void MotorErrorOver(void); +void MotorBreak(void); +void WaitStart(void); +void EnDirCheck(void); + +extern void Send_Value(void); + diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/core_cm0plus.h b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/core_cm0plus.h new file mode 100644 index 0000000..4e7179a --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/font.c b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/font.c new file mode 100644 index 0000000..c72de61 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/font.c @@ -0,0 +1,178 @@ +#include "font.h" + +uint8_t everRead=0;//¼FlashǷʼ 0ûгʼ1ʼ + +sFONT Font8x16 = { + 10*1024, /*Flashʼַ*/ + 8, /* Width */ + 16, /* Height */ +#if !FLASH_FONT //ʹڴеֿʱڴַ + ASCII8x16_Table, /* ڴַ */ +#endif +}; + +sFONT Font16x24 = { + 12*1024, /*ʼַ*/ + 16, /* Width */ + 24, /* Height */ +#if !FLASH_FONT //ʹڴеֿʱڴַ + ASCII16x24_Table, /* ڴַ */ +#endif +}; + +sFONT Font24x32 = { + 17*1024, /*ʼַ*/ + 24, /* Width */ + 32, /* Height */ +#if !FLASH_FONT //ʹڴеֿʱڴַ + ASCII24x32_Table, /* ڴַ */ +#endif +}; +sFONT GB2312_H1616 = { + 256*1024, /*ʼַ*/ + WIDTH_CH_CHAR, /* Width */ + HEIGHT_CH_CHAR, /* Height */ + /* ûڴַڴռ̫ */ +}; + + +//ѡʹFLASHģSDģ +#if GBKCODE_FLASH + + +// 0HZLIBģ(ɰ棬ʹ), 1GB2312ģ +#if 1 + +/** + * @brief ȡFLASHʾֿ + * @param pBuffer:洢ֿĻ + * @param c Ҫȡ + * @retval None. + */ +uint8_t GetGBKCode_from_EXFlash( uint8_t * pBuffer, uint16_t c) +{ +#if FLASH_FONT //ʹڴеֿʱ֧ + unsigned char High8bit,Low8bit; + unsigned int pos,datnum; + + High8bit= c >> 8; /* ȡ8λ */ + Low8bit= c & 0x00FF; /* ȡ8λ */ + + //Ҫȡֽ + datnum=GB2312_H1616.Width*GB2312_H1616.Height/8; + /*GB2312 ʽ*/ + pos = ( (High8bit-0xa1)*94 + Low8bit-0xa1 )*datnum; + //ȡֿ + SPI_FLASH_BufferRead(pBuffer , GB2312_H1616.AddrStart + pos , datnum); +#else + FONT_Bebug("ǰ岻֧\n"); +#endif + return 0; +} + +/** + * @brief ȡFlashеӢַ + * @param pBuffer:洢ֿĻ + * @param c Ҫȡ + * @param Fonts + * @retval None. + */ +uint8_t GetConslonsCode_from_EXFlash( uint8_t * pBuffer, const char c , sFONT *Fonts) +{ + unsigned char chr; + unsigned int pos,datnum; + + chr = c - ' '; + + //Ҫȡֽ(ռdatnumֽ) + datnum = (Fonts->Width * Fonts->Height)/8; + /*ģƫƵַ*/ + pos = chr*datnum; + #if FLASH_FONT + //ȡֿ + SPI_FLASH_BufferRead(pBuffer , Fonts->AddrStart + pos , datnum); + #else + for(uint16_t i=0;iFont_Table[pos+i]);//ȡijַ׵ַ + } + #endif + return 0; +} + + +#else //ɰģHZLIB ׵ĺ + + /*HZLIBֿ洢FLASHʼַ*/ + #define HZLIB_START_ADDRESS 1*4096 + + //ɰHZLIBֿʹõĺHZLIBֱ֧ + //ʹõѰַʽGB2312Ҳ + int GetGBKCode_from_EXFlash( uint8_t * pBuffer, uint16_t c) + { + unsigned char High8bit,Low8bit; + unsigned int pos; + static uint8_t everRead=0; + + High8bit= c >> 8; /* ȡ8λ */ + Low8bit= c & 0x00FF; /* ȡ8λ */ + + //ģʹõѰַʽGB2312 + pos = ((High8bit-0xa0-16)*94+Low8bit-0xa1)*WIDTH_CH_CHAR*HEIGHT_CH_CHAR/8; + //ַָHZLIBģĵַHZLIB_START_ADDRESS + SPI_FLASH_BufferRead(pBuffer,HZLIB_START_ADDRESS+pos,WIDTH_CH_CHAR*HEIGHT_CH_CHAR/8); + //printf ( "%02x %02x %02x %02x\n", pBuffer[0],pBuffer[1],pBuffer[2],pBuffer[3]); + + return 0; + } + #endif + +#else //SDģ + + static FIL fnew; /* file objects */ + static FATFS fs; /* Work area (file system object) for logical drives */ + static FRESULT res_sd; + static UINT br; /* File R/W count */ + + /** + * @brief ȡSDʾֿ + * @param pBuffer:洢ֿĻ + * @param c Ҫȡ + * @retval None. + */ + int GetGBKCode_from_sd ( uint8_t * pBuffer, uint16_t c) + { + unsigned char High8bit,Low8bit; + unsigned int pos; + static uint8_t everRead = 0; + + High8bit= c >> 8; /* ȡ8λ */ + Low8bit= c & 0x00FF; /* ȡ8λ */ + + pos = ((High8bit-0xa1)*94+Low8bit-0xa1)*WIDTH_CH_CHAR*HEIGHT_CH_CHAR/8; + + /*һʹãļϵͳʼsd*/ + if(everRead == 0) + { + res_sd = f_mount(&fs,"0:",1); + everRead = 1; + } + res_sd = f_open(&fnew , GBKCODE_FILE_NAME, FA_OPEN_EXISTING | FA_READ); + if ( res_sd == FR_OK ) + { + f_lseek (&fnew, pos); //ָƫ + f_read( &fnew, pBuffer, WIDTH_CH_CHAR*HEIGHT_CH_CHAR/8, &br );//16*16Сĺ ģ ռ16*16/8ֽ + f_close(&fnew); + return 0; + } + else + return -1; + } + +#endif + + + + + + diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/font.h b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/font.h new file mode 100644 index 0000000..1205439 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/font.h @@ -0,0 +1,1075 @@ +#ifndef __FONT_H +#define __FONT_H + +#include "main.h" + + +#define FONT_Bebug(str , ...) printf( str , ##__VA_ARGS__ ) + +#define LINE(x) ((x) * (((sFONT *)LCD_GetFont())->Height)) +#define LINEY(x) ((x) * (((sFONT *)LCD_GetFont())->Width)) + +//дFlashݺ꣬ҪFlashдݣֵ1 +#define Write_Flash 0 + + + +//0ʾʹSDģ0ʾⲿFLASHģ(ʹFlashֿʱѡʹðFlashֿ) +//SDģļϵͳٶܶࡣ +#define GBKCODE_FLASH 1 + + +//0 ʹðFlashֿ(֧)1 ʹⲿFlashֿ(֧) +#define FLASH_FONT 0 + + + + + +/** @defgroup FONTS_Exported_Types + * @{ + */ +typedef struct _tFont +{ + uint64_t AddrStart; //Flashϵĵַ + uint16_t Width; // + uint16_t Height; //߶ + const uint8_t *Font_Table;//ֿ + +}sFONT; + +extern sFONT Font8x16; //1 +extern sFONT Font16x24; //2 +extern sFONT Font24x32; //3 +extern sFONT GB2312_H1616; //4 + + +/***************************** ʾʾַС ***************************/ +#define WIDTH_CH_CHAR 16 //ַ +#define HEIGHT_CH_CHAR 16 //ַ߶ + + +#if GBKCODE_FLASH + /*ʹFLASHģ*/ + /*ֿ洢FLASHʼַ*/ + /*FLASH*/ + #define GBKCODE_START_ADDRESS 387*4096 + + /*ȡֿĺ*/ + + uint8_t GetGBKCode_from_EXFlash( uint8_t * pBuffer, uint16_t c); + uint8_t GetConslonsCode_from_EXFlash( uint8_t * pBuffer, char c , sFONT *Fonts); + +#else + /*ʹSDģ*/ + /*SDģ·*/ + #define GBKCODE_FILE_NAME "0:/System/Fonts/GB2312_H1616.FON" + //#define GBKCODE_FILE_NAME "0:/System/Fonts/consolas8x16.FON" + //#define GBKCODE_FILE_NAME "0:/System/Fonts/consolas16x24.FON" + //#define GBKCODE_FILE_NAME "0:/System/Fonts/consolas24x32.FON" + //#define GBKCODE_FILE_NAME "0:/System/Fonts/consolas32x32.FON" + + /*ȡֿĺ*/ + //ȡַģĺucBufferΪģusCharΪַ룩 + int GetGBKCode_from_sd ( uint8_t * pBuffer, uint16_t c); + + #define GetGBKCode( ucBuffer, usChar ) GetGBKCode_from_sd( ucBuffer, usChar ) + +#endif + + +/** + * ꣬ѡʹֿ(FlashSD) +*/ + +//ȡַģĺucBufferΪģusCharΪַ룩 +#define GetGBKCode( ucBuffer, usChar ) GetGBKCode_from_EXFlash( ucBuffer, usChar ) +//ȡConslonsַucBufferΪģusCharΪַ루룩FontsΪṹ +#define GetConslonsCode( ucBuffer, usChar ,Fonts) GetConslonsCode_from_EXFlash( ucBuffer, usChar ,Fonts) + + + + +//ҪдFlashлҪʹøֿʱʹ +#if Write_Flash | !FLASH_FONT //ҪдFlash +/* + * ASCIIƫ32С:16߶ȣ* 8 ȣ + *1520ֽ + */ +static const uint8_t ASCII8x16_Table [] = { //@conslons壬ʽ˳ȡ +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x18,0x18,0x18,0x18,0x18,0x18,0x08,0x00,0x08,0x18,0x00,0x00,0x00, +0x00,0x00,0x00,0x34,0x24,0x24,0x24,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x16,0x24,0x7f,0x24,0x24,0x24,0x7e,0x24,0x24,0x00,0x00,0x00, +0x00,0x00,0x00,0x08,0x3e,0x68,0x48,0x68,0x1c,0x16,0x12,0x12,0x7c,0x10,0x10,0x00, +0x00,0x00,0x00,0x61,0xd2,0x96,0x74,0x08,0x10,0x16,0x29,0x49,0xc6,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x3c,0x64,0x64,0x38,0x72,0x4a,0xce,0x46,0x7f,0x00,0x00,0x00, +0x00,0x00,0x00,0x18,0x18,0x18,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x04,0x08,0x18,0x10,0x30,0x30,0x30,0x30,0x10,0x10,0x18,0x0c,0x04, +0x00,0x00,0x00,0x20,0x10,0x08,0x08,0x0c,0x04,0x04,0x04,0x0c,0x08,0x18,0x10,0x20, +0x00,0x00,0x00,0x08,0x0a,0x34,0x1c,0x6a,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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ASCIIƫ32С:24߶ȣ* 16 ȣ + *4560ֽ + */ +static const uint8_t ASCII16x24_Table [] = { //@conslons壬ʽ˳ȡ +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x01,0x80,0x01,0x80, +0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x00,0x00, +0x00,0x00,0x03,0xc0,0x03,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0e,0x70,0x0e,0x70,0x0e,0x70, +0x0c,0x30,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x18,0x06,0x38, +0x06,0x30,0x7f,0xfe,0x0c,0x30,0x0c,0x30,0x0c,0x30,0x0c,0x30,0x7f,0xfe,0x0c,0x60, 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TimeCountRealSpd=0,TimeCountPID=0,TimeCountAvgSpd=0,TimeCountVI=0; + +unsigned char MOTORSTATE=STATESTARTCHECK; + +const unsigned int PWM_EN_TAB[6]={0x001,0x001,0x010,0x010,0x100,0x100};// 6?PWM?????? AB,AC,BC,BA,CA,CB +const unsigned char STEP_TAB[2][6]={{1,3,2,5,0,4},{4,0,5,2,3,1}}; + +uint16_t SampleData[4];//ڲ U綯 V綯 ĸߵѹ W綯 ѹ ڲ ⲿ + +unsigned char ErrorCode=0; //״̬ +unsigned int Motor_Start_F=0; //ͣ״̬ +unsigned int Cur_step=0; //ǰ +unsigned char Dir=1; // + +unsigned int HALLcount=0,HALLcount1=0,HALLcountTemp; // ֵڼƽٶȺ˲ʱٶ +unsigned int TargS1=150;//PIDĿٶ +unsigned int RealS1=0;//ʵʱ˲ʱٶ +unsigned int RealS=0;//ƽٶ +unsigned int SetSpeed=0; +float KKN=0,KPWMN=0;//λٶʱб + +unsigned int OutPwmValue=0;//ռձֵ + + +unsigned int DIin=0; //ƫ +unsigned int CanshuV=0;//ĸߵѹ100mVΪλ +unsigned int CanshuI=0;//ĸߵmA + +//²Ϊ籣 + +unsigned int MPolePairs=15; // +unsigned int MAXSPEED=680; //ת + +unsigned int ISH=8;//ֵ A +unsigned int VSH=40;//ѹֵ V +unsigned int LSH=9;//Ƿѹֵ V + +//ٶȱջ ʵС1000 +unsigned int MINSPEED=10; //ת +unsigned int SP=50,SI=50,SD=50; +////Ϊ籣 +unsigned int STEP_last; + +unsigned int startflag=0,dirflag=1; +unsigned int LevelSet = 1; + + diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/globalv.h b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/globalv.h new file mode 100644 index 0000000..e4e8274 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/globalv.h @@ -0,0 +1,163 @@ +#include "main.h" + +//LED +#define LED_GPIO_PIN GPIO_PIN_13 +#define LED_GPIO_PORT CW_GPIOC +#define LEDON() {GPIO_WritePin(LED_GPIO_PORT,LED_GPIO_PIN,GPIO_Pin_RESET);} +#define LEDOFF() {GPIO_WritePin(LED_GPIO_PORT,LED_GPIO_PIN,GPIO_Pin_SET);} +#define LEDTOG() {GPIO_TogglePin(LED_GPIO_PORT,LED_GPIO_PIN);} +//BKIN˿ڶ +#define BKIN_GPIO_PIN GPIO_PIN_11 +#define BKIN_GPIO_PORT CW_GPIOA + +//ưIO +#define DR_GPIO_PIN GPIO_PIN_5 +#define DR_GPIO_PORT CW_GPIOB + +//ʹܿƶ˰IO +#define EN_GPIO_PIN GPIO_PIN_14 +#define EN_GPIO_PORT CW_GPIOC + +//ԴʹIO +#define VOUT_EN_GPIO_PIN GPIO_PIN_6 +#define VOUT_EN_GPIO_PORT CW_GPIOF + +//ָʾIO +#define LEDDIR_GPIO_PIN GPIO_PIN_12 +#define LEDDIR_GPIO_PORT CW_GPIOA + +//ָͣʾIO +#define LEDSTSTO_GPIO_PIN GPIO_PIN_11 +#define LEDSTSTO_GPIO_PORT CW_GPIOB + + +//·PWM IO +#define PWM_AP_PORT (CW_GPIOA) +#define PWM_AP_PIN (GPIO_PIN_8) +#define PWM_AN_PORT (CW_GPIOB) +#define PWM_AN_PIN (GPIO_PIN_13) + +#define PWM_BP_PORT (CW_GPIOA) +#define PWM_BP_PIN (GPIO_PIN_9) +#define PWM_BN_PORT (CW_GPIOB) +#define PWM_BN_PIN (GPIO_PIN_14) + +#define PWM_CP_PORT (CW_GPIOA) +#define PWM_CP_PIN (GPIO_PIN_10) +#define PWM_CN_PORT (CW_GPIOB) +#define PWM_CN_PIN (GPIO_PIN_15) + + +#define PWM_AH_OFF GPIO_WritePin(PWM_AP_PORT,PWM_AP_PIN,GPIO_Pin_RESET) +#define PWM_BH_OFF GPIO_WritePin(PWM_BP_PORT,PWM_BP_PIN,GPIO_Pin_RESET) +#define PWM_CH_OFF GPIO_WritePin(PWM_CP_PORT,PWM_CP_PIN,GPIO_Pin_RESET) + +#define PWM_AH_ON GPIO_WritePin(PWM_AP_PORT,PWM_AP_PIN,GPIO_Pin_SET) +#define PWM_BH_ON GPIO_WritePin(PWM_BP_PORT,PWM_BP_PIN,GPIO_Pin_SET) +#define PWM_CH_ON GPIO_WritePin(PWM_CP_PORT,PWM_CP_PIN,GPIO_Pin_SET) + +//Ϲܵƣ¹ܿؿ, ϸߵƽµ͵ƽ +#define PWM_AL_OFF GPIO_WritePin(PWM_AN_PORT,PWM_AN_PIN,GPIO_Pin_RESET) +#define PWM_BL_OFF GPIO_WritePin(PWM_BN_PORT,PWM_BN_PIN,GPIO_Pin_RESET) +#define PWM_CL_OFF GPIO_WritePin(PWM_CN_PORT,PWM_CN_PIN,GPIO_Pin_RESET) + +#define PWM_AL_ON GPIO_WritePin(PWM_AN_PORT,PWM_AN_PIN,GPIO_Pin_SET) +#define PWM_BL_ON GPIO_WritePin(PWM_BN_PORT,PWM_BN_PIN,GPIO_Pin_SET) +#define PWM_CL_ON GPIO_WritePin(PWM_CN_PORT,PWM_CN_PIN,GPIO_Pin_SET) + + + + + +//زƵ20k +#define PWM_PERIOD 2399 +// (48000000 / 20000 ) - 1; +#define OnepercentPWM (PWM_PERIOD+1)/100 + +#define STATESTARTCHECK 0 +#define STATESTARTPID 1 +#define STATERUNPID 2 +#define STATESTOP 3 +#define STATEERROR 5 +#define STATEERROROVER 6 + +//λ +#define NMAXVD 2950 +#define NMINVD 750 +//0.4V~3.2Vе + +#define RS (float)0.005 +//ȡ +#define AP 21 +//Ŵ +#define Ikvalue (float)1200/(float)AP/RS +//㳣 ڲο1.2V + +#define NumErr 2 +//ѹ϶ + +//#define VSh 60 +//ѹֵ趨 +#define RV1 1 +#define RV2 20 +//ѹߵѹ֮ȣΪRV1:(RV1+RV2) + +#define Kvvalue (float)1.2/RV1*(RV1+RV2) + + +extern uint8_t ADC_CR1Array[4] ; // ͨADCCR1ĴʵADCͨԶл +extern uint8_t ADC_Start ; + +extern unsigned int TimeCountCompuSpeed,TimeCountTemp,TimeCountkey; +extern unsigned int TimeCountRealSpd,TimeCountPID,TimeCountAvgSpd,TimeCountVI; + +extern unsigned char MOTORSTATE; + +extern const unsigned int PWM_EN_TAB[6]; +extern const unsigned char STEP_TAB[2][6]; + +extern uint16_t SampleData[4]; + +extern unsigned char ErrorCode; //״̬ +extern unsigned int Motor_Start_F; //ͣ״̬ +extern unsigned int Cur_step; //ǰ +extern unsigned char Dir; // + +extern unsigned int HALLcount,HALLcount1,HALLcountTemp; // ֵڼƽٶȺ˲ʱٶ +extern unsigned int TargS1;//PIDĿٶ +extern unsigned int RealS1;//ʵʱ˲ʱٶ +extern unsigned int RealS;//ƽٶ +extern unsigned int SetSpeed; +extern float KKN,KPWMN;//λٶʱб + +extern unsigned int OutPwmValue;//ռձֵ + +extern unsigned char ErrCleFlag; + +extern unsigned int SpeedD;// + +extern unsigned int DIin; //ƫ +extern unsigned int CanshuV;//ĸߵѹ100mVΪλ +extern unsigned int CanshuI;//ĸߵmA + + +//²Ϊ籣 +extern unsigned int MPolePairs; // +extern unsigned int MAXSPEED; //ת +extern unsigned int CanshuTimeDelay;//ʱMS + +extern unsigned int ISH;//ֵ A +extern unsigned int VSH;//ѹֵ V +extern unsigned int LSH;//Ƿѹֵ V +// +extern unsigned int PWMMin;//ռձ +extern unsigned int PWMMax;//ռձ +extern unsigned int TImeUP;//Сռձȵռձȵʱ +//ٶȱջ ʵС1000 +extern unsigned int MINSPEED; //ת +extern unsigned int CanshuSTT;//ʱMS ʱ +extern unsigned int SP,SI,SD; + +extern unsigned int STEP_last; +extern unsigned int startflag,dirflag; +extern unsigned int LevelSet; diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/init.c b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/init.c new file mode 100644 index 0000000..e9c0c70 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/init.c @@ -0,0 +1,251 @@ +#include "globalv.h" +#include "init.h" + +uint8_t ADC_CR1Array[4] = {0x84, 0x85, 0x86, 0x87}; // ͨADCCR1ĴʵADCͨԶл +uint8_t ADC_Start = 0x01; + +//void RCC_Configuration(void) +//{//48M, +// +// //.......................... 48M +// RCC_HSI_Enable(RCC_HSIOSC_DIV6); +// __RCC_FLASH_CLK_ENABLE(); +// FLASH_SetLatency(FLASH_Latency_3); +// RCC_HSI_Enable(RCC_HSIOSC_DIV1); +// //............................. +//} + + + +void RCC_Configuration(void) +{ + //...........................64M + // 0. HSIʹܲУ׼ + RCC_HSI_Enable(RCC_HSIOSC_DIV6); + + // 1. HCLKPCLKķƵϵ + RCC_HCLKPRS_Config(RCC_HCLK_DIV1); + RCC_PCLKPRS_Config(RCC_PCLK_DIV1); + + // 2. ʹPLLͨPLLƵ64MHz + RCC_PLL_Enable(RCC_PLLSOURCE_HSI, 8000000, 8); // HSI ĬƵ8MHz + + ///< ʹõʱԴHCLK24M,Сڵ48MHzFLASH ȴΪ2 cycle + ///< ʹõʱԴHCLK48MHzFLASH ȴΪ3 cycle + __RCC_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_3); + + // 3. ʱлPLL + RCC_SysClk_Switch(RCC_SYSCLKSRC_PLL); + RCC_SystemCoreClockUpdate(64000000); + //.............................. +} + +void GPIOInit(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + __RCC_GPIOA_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); + __RCC_GPIOC_CLK_ENABLE(); + __RCC_GPIOF_CLK_ENABLE(); + GPIO_InitStruct.IT = GPIO_IT_NONE; //LED1 + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + + GPIO_InitStruct.Pins = LED_GPIO_PIN; + GPIO_Init(LED_GPIO_PORT, &GPIO_InitStruct); +// GPIO_InitStruct.Pins = LEDDIR_GPIO_PIN; +// GPIO_Init(LEDDIR_GPIO_PORT, &GPIO_InitStruct); +// GPIO_InitStruct.Pins = LEDSTSTO_GPIO_PIN; +// GPIO_Init(LEDSTSTO_GPIO_PORT, &GPIO_InitStruct); + GPIO_InitStruct.Pins = VOUT_EN_GPIO_PIN; + GPIO_Init(VOUT_EN_GPIO_PORT, &GPIO_InitStruct); + + +// GPIO_WritePin(LEDDIR_GPIO_PORT,LEDDIR_GPIO_PIN,GPIO_Pin_RESET); //ָʾ +// GPIO_WritePin(LEDSTSTO_GPIO_PORT,LEDSTSTO_GPIO_PIN,GPIO_Pin_SET); //ָͣʾ + GPIO_WritePin(VOUT_EN_GPIO_PORT,VOUT_EN_GPIO_PIN,GPIO_Pin_RESET); //ָͣʾ + + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + + GPIO_InitStruct.Pins = EN_GPIO_PIN; + GPIO_Init(EN_GPIO_PORT, &GPIO_InitStruct); + GPIO_InitStruct.Pins = DR_GPIO_PIN; + GPIO_Init(DR_GPIO_PORT, &GPIO_InitStruct); + GPIO_InitStruct.Pins = BKIN_GPIO_PIN; + GPIO_Init(BKIN_GPIO_PORT, &GPIO_InitStruct); + +} + + + +void ADC_Configuration(void) +{ + ADC_InitTypeDef ADC_InitStruct; + DMA_InitTypeDef DMA_InitStruct = {0}; + + __RCC_GPIOA_CLK_ENABLE(); + __RCC_GPIOB_CLK_ENABLE(); + __RCC_ADC_CLK_ENABLE(); + + + //ADCIO + PA04_ANALOG_ENABLE() ; //ĸߵѹ + PA05_ANALOG_ENABLE() ; //NTC¶ + PA06_ANALOG_ENABLE() ; // + PA07_ANALOG_ENABLE() ; //λ + + + ADC_InitStruct.ADC_AccEn = ADC_AccDisable; + ADC_InitStruct.ADC_Align = ADC_AlignRight; + ADC_InitStruct.ADC_ClkDiv = ADC_Clk_Div2; // ADCCLK=16MHz + ADC_InitStruct.ADC_DMAEn = ADC_DmaEnable; + ADC_InitStruct.ADC_InBufEn = ADC_BufDisable; + ADC_InitStruct.ADC_OpMode = ADC_SingleChOneMode; + ADC_InitStruct.ADC_SampleTime = ADC_SampTime10Clk; + ADC_InitStruct.ADC_TsEn = ADC_TsDisable; + ADC_InitStruct.ADC_VrefSel = ADC_Vref_VDDA; + + ADC_Init(&ADC_InitStruct); + + CW_ADC->CR1_f.CHMUX = 3; // AN0 + ADC_Enable(); + + // ʹ4·DMAͨCH1CH2CH3 CH4 + // CH1 ADCεͨIJRAMADC_ResultBuff[6] + // CH2 ADCCR1ĴֵRAMADC_CR1ArrayĴ + // CH3 ADCSTARTĴֵRAMADC_Start)Ĵ + // CH1CH2CH3ADCӲ + // CH4ATIMӲ,ADC + + + __RCC_DMA_CLK_ENABLE(); + + DMA_InitStruct.DMA_DstAddress = (uint32_t)&SampleData[0]; // Ŀַ + DMA_InitStruct.DMA_DstInc = DMA_DstAddress_Increase; // Ŀַ + DMA_InitStruct.DMA_Mode = DMA_MODE_BLOCK; // BLOCKģʽ + DMA_InitStruct.DMA_SrcAddress = (uint32_t)&CW_ADC->RESULT0; // Դַ ADCĽĴ + DMA_InitStruct.DMA_SrcInc = DMA_SrcAddress_Fix; // Դ̶ַ + DMA_InitStruct.DMA_TransferCnt = 0x4; // DMA + DMA_InitStruct.DMA_TransferWidth = DMA_TRANSFER_WIDTH_16BIT; // λ16bit + DMA_InitStruct.HardTrigSource = DMA_HardTrig_ADC_TRANSCOMPLETE; // ADCתӲ + DMA_InitStruct.TrigMode = DMA_HardTrig; // Ӳģʽ + DMA_Init(CW_DMACHANNEL1, &DMA_InitStruct); + DMA_Cmd(CW_DMACHANNEL1, ENABLE); + + DMA_InitStruct.DMA_DstAddress = (uint32_t)&CW_ADC->CR1; // Ŀַ + DMA_InitStruct.DMA_DstInc = DMA_DstAddress_Fix; // Ŀ̶ַ + DMA_InitStruct.DMA_Mode = DMA_MODE_BLOCK; // BLOCKģʽ + DMA_InitStruct.DMA_SrcAddress = (uint32_t)&ADC_CR1Array[0]; // Դַ + DMA_InitStruct.DMA_SrcInc = DMA_SrcAddress_Increase; // Դַ + DMA_InitStruct.DMA_TransferCnt = 0x3; // DMA + DMA_InitStruct.DMA_TransferWidth = DMA_TRANSFER_WIDTH_8BIT; // λ8bit + DMA_InitStruct.HardTrigSource = DMA_HardTrig_ADC_TRANSCOMPLETE; // ADCתӲ + DMA_InitStruct.TrigMode = DMA_HardTrig; // Ӳģʽ + DMA_Init(CW_DMACHANNEL2, &DMA_InitStruct); + DMA_Cmd(CW_DMACHANNEL2, ENABLE); + + DMA_InitStruct.DMA_DstAddress = (uint32_t)&CW_ADC->START; // Ŀַ + DMA_InitStruct.DMA_DstInc = DMA_DstAddress_Fix; // Ŀ̶ַ + DMA_InitStruct.DMA_Mode = DMA_MODE_BLOCK; // BLOCKģʽ + DMA_InitStruct.DMA_SrcAddress = (uint32_t)&ADC_Start; // Դַ + DMA_InitStruct.DMA_SrcInc = DMA_SrcAddress_Fix; // Դ̶ַ + DMA_InitStruct.DMA_TransferCnt = 0x3; // DMA + DMA_InitStruct.DMA_TransferWidth = DMA_TRANSFER_WIDTH_8BIT; // λ8bit + DMA_InitStruct.HardTrigSource = DMA_HardTrig_ADC_TRANSCOMPLETE; // ADCתӲ + DMA_InitStruct.TrigMode = DMA_HardTrig; // Ӳģʽ + DMA_Init(CW_DMACHANNEL3, &DMA_InitStruct); + DMA_Cmd(CW_DMACHANNEL3, ENABLE); + + DMA_InitStruct.DMA_DstAddress = (uint32_t)&CW_ADC->START; // Ŀַ + DMA_InitStruct.DMA_DstInc = DMA_DstAddress_Fix; // Ŀ̶ַ + DMA_InitStruct.DMA_Mode = DMA_MODE_BLOCK; // BLOCKģʽ + DMA_InitStruct.DMA_SrcAddress = (uint32_t)&ADC_Start; // Դַ + DMA_InitStruct.DMA_SrcInc = DMA_SrcAddress_Fix; // Դ̶ַ + DMA_InitStruct.DMA_TransferCnt = 0x1; // DMA + DMA_InitStruct.DMA_TransferWidth = DMA_TRANSFER_WIDTH_8BIT; // λ8bit + DMA_InitStruct.HardTrigSource = DMA_HardTrig_ATIM_CH1A2A3A4; // ATIMӲ + DMA_InitStruct.TrigMode = DMA_HardTrig; // Ӳģʽ + DMA_Init(CW_DMACHANNEL4, &DMA_InitStruct); + DMA_Cmd(CW_DMACHANNEL4, ENABLE); + + DMA_ITConfig(CW_DMACHANNEL1, DMA_IT_TC, ENABLE); + + + __disable_irq(); + NVIC_EnableIRQ(DMACH1_IRQn); + __enable_irq(); +} + +void DMACH1_IRQHandlerCallBack(void) +{ + CW_DMA->ICR_f.TC1 = 0x00; // жϱ־ + CW_ATIM->ICR = 0x00; // ATIMжϱ־ + CW_ADC->ICR = 0x00; // ADCжϱ־ + CW_ADC->CR1 = 0x83; // AdcIn = ch0 + //------------------------------------------------ + // DMA.CH1 : ADC_Result -> RAM + CW_DMACHANNEL1->CNT = 0x10004; //4 + CW_DMACHANNEL1->SRCADDR = (uint32_t)(&CW_ADC->RESULT0); + CW_DMACHANNEL1->DSTADDR = (uint32_t)(&SampleData[0]); + CW_DMACHANNEL1->CSR_f.EN = 1; + + + //------------------------------------------------ + // DMA.CH2 : RAM -> ADC_CR1 + CW_DMACHANNEL2->CNT = 0x10003; //3 + CW_DMACHANNEL2->SRCADDR = (uint32_t)(&ADC_CR1Array[1]); + CW_DMACHANNEL2->DSTADDR = (uint32_t)(&CW_ADC->CR1); + CW_DMACHANNEL2->CSR_f.EN = 1; + + //------------------------------------------------ + // DMA.CH3 : RAM -> ADC_START + CW_DMACHANNEL3->CNT = 0x10003; //3 + CW_DMACHANNEL3->SRCADDR = (uint32_t)(&ADC_Start); + CW_DMACHANNEL3->DSTADDR = (uint32_t)(&CW_ADC->START); + CW_DMACHANNEL3->CSR_f.EN = 1; + + //------------------------------------------------ + // DMA.CH4 : RAM -> ADC_START + CW_DMACHANNEL4->CNT = 0x10001; //1 + CW_DMACHANNEL4->SRCADDR = (uint32_t)(&ADC_Start); + CW_DMACHANNEL4->DSTADDR = (uint32_t)(&CW_ADC->START); + CW_DMACHANNEL4->CSR_f.EN = 1; +} + + +void BTIM_init(void) +{ + //1MS 48m/16/3000 + BTIM_TimeBaseInitTypeDef BTIM_InitStruct; + + __RCC_BTIM_CLK_ENABLE(); + + __disable_irq(); + NVIC_EnableIRQ(BTIM1_IRQn); + __enable_irq(); + + BTIM_InitStruct.BTIM_Mode = BTIM_Mode_TIMER; //1msʱ + BTIM_InitStruct.BTIM_OPMode = BTIM_OPMode_Repetitive; + BTIM_InitStruct.BTIM_Period = 3000; + BTIM_InitStruct.BTIM_Prescaler = BTIM_PRS_DIV16; + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_InitStruct); + + BTIM_ITConfig(CW_BTIM1, BTIM_IT_OV, ENABLE); + BTIM_Cmd(CW_BTIM1, ENABLE); +} + +//void UART3_IRQHandler() +//{ //δ +// // unsigned char tx; +// +// if(USART_GetITStatus(CW_UART3, USART_IT_RC) != RESET) +// { +// USART_ClearITPendingBit(CW_UART3, USART_IT_RC); +// // tx = USART_ReceiveData_8bit(CW_UART3); +// } +//} diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/init.h b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/init.h new file mode 100644 index 0000000..db45443 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/init.h @@ -0,0 +1,11 @@ +#include "MAIN.h" +//#include "globalv.h" + + +void RCC_Configuration(void); +void ADC_Configuration(void); +void GPIOInit(void); +void BTIM_init(void); +void Usart3_init(void); +void Usart3_sendchar(unsigned char cs); +void Rec_Check(void); diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/interrupts_cw32f030.c b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/interrupts_cw32f030.c new file mode 100644 index 0000000..3c19513 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/interrupts_cw32f030.c @@ -0,0 +1,448 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "interrupts_cw32f030.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ + + +extern void DMACH1_IRQHandlerCallBack(void); + +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles RCC + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1 + */ +void DMACH1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + + if( DMA_GetITStatus(DMA_IT_TC1) ) + { + DMA_ClearITPendingBit(DMA_IT_TC1); + + DMACH1_IRQHandlerCallBack(); + } + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH23 + */ +void DMACH23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMA34 + */ +void DMACH45_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +//void ATIM_IRQHandler(void) +//{ +// /* USER CODE BEGIN */ + +// /* USER CODE END */ +//} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + + + +/** + * @brief This funcation handles GTIM2 + */ +//void GTIM2_IRQHandler(void) +//{ +// /* USER CODE BEGIN */ + +// /* USER CODE END */ +//} + +/** + * @brief This funcation handles GTIM3 + */ +void GTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM4 + */ +void GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + + + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ + + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2 + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + if(GTIM_GetITStatus(CW_GTIM1,GTIM_IT_OV)) + { + GTIM_ClearITPendingBit(CW_GTIM1,GTIM_IT_OV); + + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +//void UART3_IRQHandler(void) +//{ +// /* USER CODE BEGIN */ + +// /* USER CODE END */ +//} + +/** + * @brief This funcation handles AWT + */ +void AWT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void FAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/interrupts_cw32f030.h b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/interrupts_cw32f030.h new file mode 100644 index 0000000..96d2a71 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/interrupts_cw32f030.h @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32f030.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32F030_H +#define __INTERRUPTS_CW32F030_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void RCC_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_IRQHandler(void); +extern void DMACH23_IRQHandler(void); +extern void DMACH45_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_IRQHandler(void); +extern void GTIM4_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI2_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void AWT_IRQHandler(void); +extern void FAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32F030_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/main.h b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/main.h new file mode 100644 index 0000000..0213123 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/main.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "interrupts_cw32f030.h" + + +#include "cw32f030_adc.h" +#include "cw32f030_atim.h" +#include "cw32f030_awt.h" +#include "cw32f030_btim.h" +#include "cw32f030_crc.h" +#include "cw32f030_debug.h" +#include "cw32f030_digitalsign.h" +#include "cw32f030_dma.h" +#include "cw32f030_flash.h" +#include "cw32f030_gpio.h" +#include "cw32f030_gtim.h" +#include "cw32f030_i2c.h" +#include "cw32f030_iwdt.h" +#include "cw32f030_lvd.h" +#include "cw32f030_pwr.h" +#include "cw32f030_ram.h" +#include "cw32f030_rcc.h" +#include "cw32f030_rtc.h" +#include "cw32f030_spi.h" +#include "cw32f030_systick.h" +#include "cw32f030_uart.h" +#include "cw32f030_wwdt.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void LED_Init(void); + +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/motor.h b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/motor.h new file mode 100644 index 0000000..c0f9d33 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/motor.h @@ -0,0 +1,14 @@ +#include "main.h" + +#include "globalv.h" +#include "init.h" + +void PWMtimer_init(void); +void Halltimer_init(void); + +void Commutation(unsigned int step,unsigned int PWM_ON_flag); +void UPPWM(void); +unsigned char HALL_Check(void); +//void Halltimer_ioinit(void); +void HALL_MOTOR_START(void); +void MOTOR_STOP0(void); diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/pid.c b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/pid.c new file mode 100644 index 0000000..52b6e06 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/pid.c @@ -0,0 +1,96 @@ +#include "PID.h" + +float SPEED_P,SPEED_I,SPEED_D=0; + +double SSumError=0,SPrevError=0,SLastError=0; +int SdError=0,SError=0; + +void PID_init(void) +{ + SError=0;SSumError=0;SLastError=0; + + + SPEED_P=(float)SP/1000; + SPEED_I=(float)SI/1000; + SPEED_D=(float)SD/1000; + +// SSumError=OutPwmValue; +// SSumError=SSumError/SPEED_I; +} + +void PIDcompute(unsigned int Target, unsigned int Real) +{ + float j = 0.0f; + + if(Target * MPolePairs < 600) Target = 600 / MPolePairs; + + SError = (Target - Real); + + // ĽĻ + float temp_integral = SSumError + SError; + float integral_limit = PWM_PERIOD / SPEED_I; + + // ޷ + if(temp_integral > integral_limit) { + SSumError = integral_limit; + } else if(temp_integral < -integral_limit) { + SSumError = -integral_limit; + } else { + SSumError = temp_integral; + } + + // ΢ + SdError = SError - SLastError; + SLastError = SError; + + // PID + j = SPEED_P * SError + SPEED_I * SSumError + SPEED_D * SdError; + + // ޷ + if(j > PWM_PERIOD) { + OutPwmValue = PWM_PERIOD; + } else if(j < 1) { + OutPwmValue = 1; + } else { + OutPwmValue = (int)j; + } + + UPPWM(); +} +/* +void PIDcompute(unsigned int Target,unsigned int Real) +{ + float j=0.0,i; + + + if(Target*MPolePairs<600)Target=600/MPolePairs; //٣4Լ150RPM + + SError =(Target-Real); //ƫ + + if(SSumError<500)SSumError=500; + else if(SSumError*SPEED_I>PWM_PERIOD) + { + SSumError=PWM_PERIOD; + SSumError=SSumError/SPEED_I; + } // ֵ󣬲ۼƫֱ + else SSumError +=SError; + + + SdError=SError-SLastError; //΢ƫı仯 + SLastError=SError; //¼ƫ´μ + + i=SPEED_P; + j=SError*i; + i=SPEED_I; + j=j+SSumError*i; + i=SPEED_D; + j=j+SdError*i; + + if(j>PWM_PERIOD)OutPwmValue=PWM_PERIOD; + else if(j<1)OutPwmValue=1; + else OutPwmValue=j; + + + UPPWM(); +} +*/ diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/pid.h b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/pid.h new file mode 100644 index 0000000..9a25f8b --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/pid.h @@ -0,0 +1,6 @@ +#include "motor.h" +#include "globalv.h" + +void PID_init(void); +void PIDcompute(unsigned int Target,unsigned int Real); +void PIDIcompute(unsigned int Target,unsigned int Real); diff --git a/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/startup_cw32f030.s b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/startup_cw32f030.s new file mode 100644 index 0000000..d1e2ceb --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/startup_cw32f030.s @@ -0,0 +1,257 @@ + +;/*****************************************************************************/ +;/* Startup for ARM */ +;/* Version V1.0 */ +;/* Date 2021-03-12 */ +;/* Target-mcu {MCU_PN_H} */ +;/*****************************************************************************/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors + DCD __initial_sp ; Top of Stack + DCD Reset_Handler ;< -15 Reset Vector, invoked on Power up and warm reset + DCD NMI_Handler ;< -14 Non maskable Interrupt, cannot be stopped or preempted + DCD HardFault_Handler ;< -13 Hard Fault, all classes of Fault + DCD 0 ;< -12 Reserved + DCD 0 ;< -11 Reserved + DCD 0 ;< -10 Reserved + DCD 0 ;< -9 Reserved + DCD 0 ;< -8 Reserved + DCD 0 ;< -7 Reserved + DCD 0 ;< -6 Reserved + DCD SVC_Handler ;< -5 System Service Call via SVC instruction + DCD 0 ;< -4 Reserved + DCD 0 ;< -3 Reserved + DCD PendSV_Handler ;< -2 Pendable request for system service + DCD SysTick_Handler ;< -1 System Tick Timer + + DCD WDT_IRQHandler ;< 0 Watch Dog Timer Interrupt Handler + DCD LVD_IRQHandler ;< 1 Low Voltage Detect Interrupt Handler + DCD RTC_IRQHandler ;< 2 Real Time Clock Interrupt Handler + DCD FLASHRAM_IRQHandler ;< 3 Flash/RAM Interrupt Handler + DCD RCC_IRQHandler ;< 4 RCC Interupt Handler + DCD GPIOA_IRQHandler ;< 5 GPIOA Interrupt Handler + DCD GPIOB_IRQHandler ;< 6 GPIOB Interrupt Handler + DCD GPIOC_IRQHandler ;< 7 GPIOC Interrupt Handler + DCD GPIOF_IRQHandler ;< 8 GPIOF Interrupt Handler + DCD DMACH1_IRQHandler ;< 9 DMA Channel 1 Interrupt Handler + DCD DMACH23_IRQHandler ;< 10 DMA Channel 2/3 Interrupt Handler + DCD DMACH45_IRQHandler ;< 11 DMA Channel 4/5 Interrupt Handler + DCD ADC_IRQHandler ;< 12 ADC Interrupt Handler + DCD ATIM_IRQHandler ;< 13 Advanced Timer Interrupt Handler + DCD VC1_IRQHandler ;< 14 Voltage Comparator 1 Interrupt Handler + DCD VC2_IRQHandler ;< 15 Voltage Comparator 2 Interrupt Handler + DCD GTIM1_IRQHandler ;< 16 General Timer1 Interrupt Handler + DCD GTIM2_IRQHandler ;< 17 General Timer2 Interrupt Handler + DCD GTIM3_IRQHandler ;< 18 General Timer3 Interrupt Handler + DCD GTIM4_IRQHandler ;< 19 General Timer4 Interrupt Handler + DCD BTIM1_IRQHandler ;< 20 Base Timer1 Interrupt Handler + DCD BTIM2_IRQHandler ;< 21 Base Timer2 Interrupt Handler + DCD BTIM3_IRQHandler ;< 22 Base Timer3 Interrupt Handler + DCD I2C1_IRQHandler ;< 23 I2C1 Interrupt Handler + DCD I2C2_IRQHandler ;< 24 I2C2 Interrupt Handler + DCD SPI1_IRQHandler ;< 25 SPI1 Interrupt Handler + DCD SPI2_IRQHandler ;< 26 SPI2 Interrupt Handler + DCD UART1_IRQHandler ;< 27 UART1 Interrupt Handler + DCD UART2_IRQHandler ;< 28 UART2 Interrupt Handler + DCD UART3_IRQHandler ;< 29 UART3 Interrupt Handler + DCD AWT_IRQHandler ;< 30 Auto Wakeup Timer Handler + DCD FAULT_IRQHandler ;< 31 FAULT Interrupt Handler + + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + ;reset NVIC if in rom debug + LDR R0, =0x20000000 + LDR R2, =0x0 + MOVS R1, #0 ; for warning, + ADD R1, PC,#0 ; for A1609W, + CMP R1, R0 + BLS RAMCODE + + ; ram code base address. + ADD R2, R0,R2 +RAMCODE + ; reset Vector table address. + LDR R0, =0xE000ED08 + STR R2, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + + +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT WDT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASHRAM_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT GPIOA_IRQHandler [WEAK] + EXPORT GPIOB_IRQHandler [WEAK] + EXPORT GPIOC_IRQHandler [WEAK] + EXPORT GPIOF_IRQHandler [WEAK] + EXPORT DMACH1_IRQHandler [WEAK] + EXPORT DMACH23_IRQHandler [WEAK] + EXPORT DMACH45_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT ATIM_IRQHandler [WEAK] + EXPORT VC1_IRQHandler [WEAK] + EXPORT VC2_IRQHandler [WEAK] + EXPORT GTIM1_IRQHandler [WEAK] + EXPORT GTIM2_IRQHandler [WEAK] + EXPORT GTIM3_IRQHandler [WEAK] + EXPORT GTIM4_IRQHandler [WEAK] + EXPORT BTIM1_IRQHandler [WEAK] + EXPORT BTIM2_IRQHandler [WEAK] + EXPORT BTIM3_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT AWT_IRQHandler [WEAK] + EXPORT FAULT_IRQHandler [WEAK] + +WDT_IRQHandler +LVD_IRQHandler +RTC_IRQHandler +FLASHRAM_IRQHandler +RCC_IRQHandler +GPIOA_IRQHandler +GPIOB_IRQHandler +GPIOC_IRQHandler +GPIOF_IRQHandler +DMACH1_IRQHandler +DMACH23_IRQHandler +DMACH45_IRQHandler +ADC_IRQHandler +ATIM_IRQHandler +VC1_IRQHandler +VC2_IRQHandler +GTIM1_IRQHandler +GTIM2_IRQHandler +GTIM3_IRQHandler +GTIM4_IRQHandler +BTIM1_IRQHandler +BTIM2_IRQHandler +BTIM3_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +AWT_IRQHandler +FAULT_IRQHandler + + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/base_types.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/base_types.h new file mode 100644 index 0000000..4185367 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/base_types.h @@ -0,0 +1,145 @@ + +#ifndef __BASE_TYPES_H +#define __BASE_TYPES_H + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include +#include +#include + + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +#ifndef TRUE + /** Value is true (boolean_t type) */ + #define TRUE ((boolean_t) 1u) +#endif + +#ifndef FALSE + /** Value is false (boolean_t type) */ + #define FALSE ((boolean_t) 0u) +#endif + +/** Returns the minimum value out of two values */ +#define MINIMUM( X, Y ) ((X) < (Y) ? (X) : (Y)) + +/** Returns the maximum value out of two values */ +#define MAXIMUM( X, Y ) ((X) > (Y) ? (X) : (Y)) + +/** Returns the dimension of an array */ +#define ARRAY_SZ( X ) (sizeof(X) / sizeof((X)[0])) + +#ifdef __DEBUG_ASSERT + #define ASSERT(x) do{ assert((x)> 0u) ; }while(0); +#else + #define ASSERT(x) {} +#endif +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** logical datatype (only values are TRUE and FALSE) */ +typedef uint8_t boolean_t; + +/** single precision floating point number (4 byte) */ +typedef float float32_t; + +/** double precision floating point number (8 byte) */ +typedef double float64_t; + +/** ASCII character for string generation (8 bit) */ +typedef char char_t; + +/** function pointer type to void/void function */ +typedef void (*func_ptr_t)(void); + +/** function pointer type to void/uint8_t function */ +typedef void (*func_ptr_arg1_t)(uint8_t u8Param); + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + + + +#define bv(n) ((uint32_t)1u << (n)) + +#define bv0 (((uint32_t)1u) << 0) +#define bv1 (((uint32_t)1u) << 1) +#define bv2 (((uint32_t)1u) << 2) +#define bv3 (((uint32_t)1u) << 3) +#define bv4 (((uint32_t)1u) << 4) +#define bv5 (((uint32_t)1u) << 5) +#define bv6 (((uint32_t)1u) << 6) +#define bv7 (((uint32_t)1u) << 7) +#define bv8 (((uint32_t)1u) << 8) +#define bv9 (((uint32_t)1u) << 9) +#define bv10 (((uint32_t)1u) << 10) +#define bv11 (((uint32_t)1u) << 11) +#define bv12 (((uint32_t)1u) << 12) +#define bv13 (((uint32_t)1u) << 13) +#define bv14 (((uint32_t)1u) << 14) +#define bv15 (((uint32_t)1u) << 15) +#define bv16 (((uint32_t)1u) << 16) +#define bv17 (((uint32_t)1u) << 17) +#define bv18 (((uint32_t)1u) << 18) +#define bv19 (((uint32_t)1u) << 19) +#define bv20 (((uint32_t)1u) << 20) +#define bv21 (((uint32_t)1u) << 21) +#define bv22 (((uint32_t)1u) << 22) +#define bv23 (((uint32_t)1u) << 23) +#define bv24 (((uint32_t)1u) << 24) +#define bv25 (((uint32_t)1u) << 25) +#define bv26 (((uint32_t)1u) << 26) +#define bv27 (((uint32_t)1u) << 27) +#define bv28 (((uint32_t)1u) << 28) +#define bv29 (((uint32_t)1u) << 29) +#define bv30 (((uint32_t)1u) << 30) +#define bv31 (((uint32_t)1u) << 31) + +#define REGBITS_SET( Reg , Mask ) ( (Reg) |= (Mask) ) +#define REGBITS_CLR( Reg , Mask ) ( (Reg) &= (~((uint32_t)(Mask))) ) +#define REGBITS_GET( Reg , Mask ) ( (Reg) & (Mask) ) +#define REGBITS_MODIFY( Reg , Mask , Value ) ( (Reg) = ((Reg) & (~(uint32_t)(Mask))) | (Value) ) + +/* Exported macro ------------------------------------------------------------*/ +// #define USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t* file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +#endif /* __BASE_TYPES_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + + + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030.h new file mode 100644 index 0000000..b5b719e --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030.h @@ -0,0 +1,7401 @@ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * @file cw32f030.h + * @brief CMSIS HeaderFile + * @version 1.2 + * @date 22. July 2021 + * @note Generated by SVDConv V3.3.25 on Thursday, 22.07.2021 14:07:41 + * from File 'cw32f030.svd', + * last modified on Thursday, 22.07.2021 06:07:37 + */ + + + +/** @addtogroup CW Co.Ltd + * @{ + */ + + +/** @addtogroup cw32f030 + * @{ + */ + + +#ifndef CW32F030_H +#define CW32F030_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== cw32f030 Specific Interrupt Numbers ========================================== */ + WDT_IRQn = 0, /*!< 0 Watch Dog Timer Interrupt */ + LVD_IRQn = 1, /*!< 1 Low Voltage Detect Interrupt */ + RTC_IRQn = 2, /*!< 2 Real Time Clock Interrupt */ + FLASHRAM_IRQn = 3, /*!< 3 Flash/RAM Interrupt */ + RCC_IRQn = 4, /*!< 4 RCC Interupt */ + GPIOA_IRQn = 5, /*!< 5 GPIOA Interrupt */ + GPIOB_IRQn = 6, /*!< 6 GPIOB Interrupt */ + GPIOC_IRQn = 7, /*!< 7 GPIOC Interrupt */ + GPIOF_IRQn = 8, /*!< 8 GPIOF Interrupt */ + DMACH1_IRQn = 9, /*!< 9 DMA Channel 1 Interrupt */ + DMACH23_IRQn = 10, /*!< 10 DMA Channel 2/3 Interrupt */ + DMACH45_IRQn = 11, /*!< 11 DMA Channel 2/3 Interrupt */ + ADC_IRQn = 12, /*!< 12 ADC Interrupt */ + ATIM_IRQn = 13, /*!< 13 Advanced Timer Interrupt */ + VC1_IRQn = 14, /*!< 14 Voltage Comparator 1 Interrupt */ + VC2_IRQn = 15, /*!< 15 Voltage Comparator 2 Interrupt */ + GTIM1_IRQn = 16, /*!< 16 General Timer1 Interrupt */ + GTIM2_IRQn = 17, /*!< 17 General Timer2 Interrupt */ + GTIM3_IRQn = 18, /*!< 18 General Timer3 Interrupt */ + GTIM4_IRQn = 19, /*!< 19 General Timer4 Interrupt */ + BTIM1_IRQn = 20, /*!< 20 Base Timer1 Interrupt */ + BTIM2_IRQn = 21, /*!< 21 Base Timer2 Interrupt */ + BTIM3_IRQn = 22, /*!< 22 Base Timer3 Interrupt */ + I2C1_IRQn = 23, /*!< 23 I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< 24 I2C2 Interrput */ + SPI1_IRQn = 25, /*!< 25 SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< 26 SPI2 Interrupt */ + UART1_IRQn = 27, /*!< 27 UART1 Interrupt */ + UART2_IRQn = 28, /*!< 28 UART2 Interrupt */ + UART3_IRQn = 29, /*!< 29 UART3 Interrupt */ + AWT_IRQn = 30, /*!< 30 Auto Wakeup Timer Interrupt */ + FAULT_IRQn = 31 /*!< 31 FAULT Interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 0 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ +#include "system_cw32f030.h" /*!< cw32f030 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc ADC (ADC) + */ + +typedef struct { /*!< (@ 0x40012400) ADC Structure */ + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control register0 */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t MODE : 3; /*!< [3..1] desc MODE */ + __IOM uint32_t BGREN : 1; /*!< [4..4] desc BGREN */ + __IOM uint32_t TSEN : 1; /*!< [5..5] desc TSEN */ + __IOM uint32_t REF : 2; /*!< [7..6] desc REF */ + __IOM uint32_t CLK : 3; /*!< [10..8] desc CLK */ + __IOM uint32_t SAM : 2; /*!< [12..11] desc SAM */ + __IOM uint32_t BUF : 1; /*!< [13..13] desc BUF */ + __IOM uint32_t BIAS : 2; /*!< [15..14] desc BIAS */ + } CR0_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000004) Control register1 */ + + struct { + __IOM uint32_t CHMUX : 4; /*!< [3..0] desc CHMUX */ + __IM uint32_t : 1; + __IOM uint32_t DISCARD : 1; /*!< [5..5] desc DISCARD */ + __IOM uint32_t ALIGN : 1; /*!< [6..6] desc ALIGN */ + __IOM uint32_t DMAEN : 1; /*!< [7..7] desc DMAEN */ + __IOM uint32_t WDTCH : 4; /*!< [11..8] desc WDTCH */ + __IM uint32_t : 1; + __IOM uint32_t WDTALL : 1; /*!< [13..13] desc WDTALL */ + } CR1_f; + } ; + + union { + __IOM uint32_t START; /*!< (@ 0x00000008) desc START */ + + struct { + __IOM uint32_t START : 1; /*!< [0..0] desc START */ + __IOM uint32_t AUTOSTOP : 1; /*!< [1..1] desc AUTOSTOP */ + } START_f; + } ; + + union { + __IOM uint32_t SQR; /*!< (@ 0x0000000C) desc SQR */ + + struct { + __IOM uint32_t SQR0 : 4; /*!< [3..0] desc SQR0 */ + __IOM uint32_t SQR1 : 4; /*!< [7..4] desc SQR1 */ + __IOM uint32_t SQR2 : 4; /*!< [11..8] desc SQR2 */ + __IOM uint32_t SQR3 : 4; /*!< [15..12] desc SQR3 */ + __IOM uint32_t ENS : 2; /*!< [17..16] desc ENS */ + } SQR_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000010) Control register2 */ + + struct { + __IOM uint32_t CNT : 8; /*!< [7..0] desc CNT */ + __IOM uint32_t ACCEN : 1; /*!< [8..8] desc ACCEN */ + __IOM uint32_t ACCRST : 1; /*!< [9..9] desc ACCRST */ + } CR2_f; + } ; + + union { + __IOM uint32_t VTH; /*!< (@ 0x00000014) desc VTH */ + + struct { + __IOM uint32_t VTH : 12; /*!< [11..0] desc VTH */ + } VTH_f; + } ; + + union { + __IOM uint32_t VTL; /*!< (@ 0x00000018) desc VTL */ + + struct { + __IOM uint32_t VTL : 12; /*!< [11..0] desc VTL */ + } VTL_f; + } ; + + union { + __IOM uint32_t TRIGGER; /*!< (@ 0x0000001C) desc TRIGGER */ + + struct { + __IOM uint32_t ATIM : 1; /*!< [0..0] desc ATIM */ + __IOM uint32_t GTIM1 : 1; /*!< [1..1] desc GTIM1 */ + __IOM uint32_t GTIM2 : 1; /*!< [2..2] desc GTIM2 */ + __IOM uint32_t GTIM3 : 1; /*!< [3..3] desc GTIM3 */ + __IOM uint32_t GTIM4 : 1; /*!< [4..4] desc GTIM4 */ + __IOM uint32_t BTIM1 : 1; /*!< [5..5] desc BTIM1 */ + __IOM uint32_t BTIM2 : 1; /*!< [6..6] desc BTIM2 */ + __IOM uint32_t BTIM3 : 1; /*!< [7..7] desc BTIM3 */ + __IOM uint32_t UART1 : 1; /*!< [8..8] desc UART1 */ + __IOM uint32_t UART2 : 1; /*!< [9..9] desc UART2 */ + __IOM uint32_t UART3 : 1; /*!< [10..10] desc UART3 */ + __IOM uint32_t SPI1 : 1; /*!< [11..11] desc SPI1 */ + __IOM uint32_t SPI2 : 1; /*!< [12..12] desc SPI2 */ + __IOM uint32_t I2C1 : 1; /*!< [13..13] desc I2C1 */ + __IOM uint32_t I2C2 : 1; /*!< [14..14] desc I2C2 */ + __IOM uint32_t DMA : 1; /*!< [15..15] desc DMA */ + } TRIGGER_f; + } ; + + union { + __IM uint32_t RESULT0; /*!< (@ 0x00000020) desc RESULT0 */ + + struct { + __IM uint32_t RESULT : 16; /*!< [15..0] desc RESULT */ + } RESULT0_f; + } ; + + union { + __IM uint32_t RESULT1; /*!< (@ 0x00000024) desc RESULT1 */ + + struct { + __IM uint32_t RESULT : 16; /*!< [15..0] desc RESULT */ + } RESULT1_f; + } ; + + union { + __IM uint32_t RESULT2; /*!< (@ 0x00000028) desc RESULT2 */ + + struct { + __IM uint32_t RESULT : 16; /*!< [15..0] desc RESULT */ + } RESULT2_f; + } ; + + union { + __IM uint32_t RESULT3; /*!< (@ 0x0000002C) desc RESULT3 */ + + struct { + __IM uint32_t RESULT : 16; /*!< [15..0] desc RESULT */ + } RESULT3_f; + } ; + + union { + __IM uint32_t RESULTACC; /*!< (@ 0x00000030) desc RESULTACC */ + + struct { + __IM uint32_t RESULT : 24; /*!< [23..0] desc RESULT */ + } RESULTACC_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000034) Interrupt enable register */ + + struct { + __IOM uint32_t EOC : 1; /*!< [0..0] desc EOC */ + __IOM uint32_t EOS : 1; /*!< [1..1] desc EOS */ + __IOM uint32_t EOA : 1; /*!< [2..2] desc EOA */ + __IOM uint32_t WDTL : 1; /*!< [3..3] desc WDTL */ + __IOM uint32_t WDTH : 1; /*!< [4..4] desc WDTH */ + __IOM uint32_t WDTR : 1; /*!< [5..5] desc WDTR */ + __IOM uint32_t OVW : 1; /*!< [6..6] desc OVW */ + } IER_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000038) Interrupt flag clear register */ + + struct { + __IOM uint32_t EOC : 1; /*!< [0..0] desc EOC */ + __IOM uint32_t EOS : 1; /*!< [1..1] desc EOS */ + __IOM uint32_t EOA : 1; /*!< [2..2] desc EOA */ + __IOM uint32_t WDTL : 1; /*!< [3..3] desc WDTL */ + __IOM uint32_t WDTH : 1; /*!< [4..4] desc WDTH */ + __IOM uint32_t WDTR : 1; /*!< [5..5] desc WDTR */ + __IOM uint32_t OVW : 1; /*!< [6..6] desc OVW */ + } ICR_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x0000003C) Interrupt status register */ + + struct { + __IM uint32_t EOC : 1; /*!< [0..0] desc EOC */ + __IM uint32_t EOS : 1; /*!< [1..1] desc EOS */ + __IM uint32_t EOA : 1; /*!< [2..2] desc EOA */ + __IM uint32_t WDTL : 1; /*!< [3..3] desc WDTL */ + __IM uint32_t WDTH : 1; /*!< [4..4] desc WDTH */ + __IM uint32_t WDTR : 1; /*!< [5..5] desc WDTR */ + __IM uint32_t OVW : 1; /*!< [6..6] desc OVW */ + __IM uint32_t READY : 1; /*!< [7..7] desc READY */ + } ISR_f; + } ; + + union { + __IM uint32_t RESULT140; /*!< (@ 0x00000040) desc RESULT140 */ + + struct { + __IM uint32_t RESULT : 16; /*!< [15..0] desc RESULT */ + } RESULT140_f; + } ; + + union { + __IM uint32_t RESULT141; /*!< (@ 0x00000044) desc RESULT141 */ + + struct { + __IM uint32_t RESULT : 16; /*!< [15..0] desc RESULT */ + } RESULT141_f; + } ; + + union { + __IM uint32_t RESULT142; /*!< (@ 0x00000048) desc RESULT142 */ + + struct { + __IM uint32_t RESULT : 16; /*!< [15..0] desc RESULT */ + } RESULT142_f; + } ; + + union { + __IM uint32_t RESULT143; /*!< (@ 0x0000004C) desc RESULT143 */ + + struct { + __IM uint32_t RESULT : 16; /*!< [15..0] desc RESULT */ + } RESULT143_f; + } ; + __IM uint32_t RESERVED[14]; + + union { + __OM uint32_t ENABLE14; /*!< (@ 0x00000088) desc ENABLE14 */ + + struct { + __OM uint32_t KEY : 16; /*!< [15..0] desc KEY */ + } ENABLE14_f; + } ; +} ADC_TypeDef; /*!< Size = 140 (0x8c) */ + + + +/* =========================================================================================================================== */ +/* ================ ATIM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc ATIM (ATIM) + */ + +typedef struct { /*!< (@ 0x40012C00) ATIM Structure */ + + union { + __IOM uint32_t ARR; /*!< (@ 0x00000000) desc ARR */ + + struct { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } ARR_f; + } ; + + union { + __IOM uint32_t CNT; /*!< (@ 0x00000004) desc CNT */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + } CNT_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t CR; /*!< (@ 0x0000000C) desc CR */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t COMP : 1; /*!< [1..1] desc COMP */ + __IOM uint32_t CT : 1; /*!< [2..2] desc CT */ + __IOM uint32_t PWM2S : 1; /*!< [3..3] desc PWM2S */ + __IOM uint32_t PRS : 3; /*!< [6..4] desc PRS */ + __IOM uint32_t BUFPEN : 1; /*!< [7..7] desc BUFPEN */ + __IM uint32_t : 2; + __IOM uint32_t UIE : 1; /*!< [10..10] desc UIE */ + __IM uint32_t : 1; + __IOM uint32_t MODE : 2; /*!< [13..12] Please keep 10/11 */ + __IOM uint32_t ONESHOT : 1; /*!< [14..14] desc ONESHOT */ + __IM uint32_t : 1; + __IOM uint32_t OCCS : 1; /*!< [16..16] desc OCCS */ + __IOM uint32_t URS : 1; /*!< [17..17] desc URS */ + __IM uint32_t : 1; + __IOM uint32_t TIE : 1; /*!< [19..19] desc TIE */ + __IOM uint32_t BIE : 1; /*!< [20..20] desc BIE */ + __IOM uint32_t CISA : 2; /*!< [22..21] desc CISA */ + __IOM uint32_t OCCE : 1; /*!< [23..23] desc OCCE */ + __IOM uint32_t TG : 1; /*!< [24..24] desc TG */ + __IOM uint32_t UG : 1; /*!< [25..25] desc UG */ + __IOM uint32_t BG : 1; /*!< [26..26] desc BG */ + __IOM uint32_t DIR : 1; /*!< [27..27] desc DIR */ + __IOM uint32_t OVE : 1; /*!< [28..28] desc OVE */ + __IOM uint32_t UNDE : 1; /*!< [29..29] desc UNDE */ + } CR_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000010) desc ISR */ + + struct { + __IM uint32_t UIF : 1; /*!< [0..0] desc UIF */ + __IM uint32_t : 1; + __IM uint32_t C1AF : 1; /*!< [2..2] desc C1AF */ + __IM uint32_t C2AF : 1; /*!< [3..3] desc C2AF */ + __IM uint32_t C3AF : 1; /*!< [4..4] desc C3AF */ + __IM uint32_t C1BF : 1; /*!< [5..5] desc C1BF */ + __IM uint32_t C2BF : 1; /*!< [6..6] desc C2BF */ + __IM uint32_t C3BF : 1; /*!< [7..7] desc C3BF */ + __IM uint32_t C1AE : 1; /*!< [8..8] desc C1AE */ + __IM uint32_t C2AE : 1; /*!< [9..9] desc C2AE */ + __IM uint32_t C3AE : 1; /*!< [10..10] desc C3AE */ + __IM uint32_t C1BE : 1; /*!< [11..11] desc C1BE */ + __IM uint32_t C2BE : 1; /*!< [12..12] desc C2BE */ + __IM uint32_t C3BE : 1; /*!< [13..13] desc C3BE */ + __IM uint32_t BIF : 1; /*!< [14..14] desc BIF */ + __IM uint32_t TIF : 1; /*!< [15..15] desc TIF */ + __IM uint32_t OVF : 1; /*!< [16..16] desc OVF */ + __IM uint32_t UNDF : 1; /*!< [17..17] desc UNDF */ + __IM uint32_t C4AF : 1; /*!< [18..18] desc C4AF */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000014) desc ICR */ + + struct { + __IOM uint32_t UIF : 1; /*!< [0..0] desc UIF */ + __IM uint32_t : 1; + __IOM uint32_t C1AF : 1; /*!< [2..2] desc C1AF */ + __IOM uint32_t C2AF : 1; /*!< [3..3] desc C2AF */ + __IOM uint32_t C3AF : 1; /*!< [4..4] desc C3AF */ + __IOM uint32_t C1BF : 1; /*!< [5..5] desc C1BF */ + __IOM uint32_t C2BF : 1; /*!< [6..6] desc C2BF */ + __IOM uint32_t C3BF : 1; /*!< [7..7] desc C3BF */ + __IOM uint32_t C1AE : 1; /*!< [8..8] desc C1AE */ + __IOM uint32_t C2AE : 1; /*!< [9..9] desc C2AE */ + __IOM uint32_t C3AE : 1; /*!< [10..10] desc C3AE */ + __IOM uint32_t C1BE : 1; /*!< [11..11] desc C1BE */ + __IOM uint32_t C2BE : 1; /*!< [12..12] desc C2BE */ + __IOM uint32_t C3BE : 1; /*!< [13..13] desc C3BE */ + __IOM uint32_t BIF : 1; /*!< [14..14] desc BIF */ + __IOM uint32_t TIF : 1; /*!< [15..15] desc TIF */ + __IOM uint32_t OVF : 1; /*!< [16..16] desc OVF */ + __IOM uint32_t UNDF : 1; /*!< [17..17] desc UNDF */ + __IOM uint32_t C4AF : 1; /*!< [18..18] desc C4AF */ + } ICR_f; + } ; + + union { + __IOM uint32_t MSCR; /*!< (@ 0x00000018) desc MSCR */ + + struct { + __IOM uint32_t MMS : 3; /*!< [2..0] desc MMS */ + __IOM uint32_t CCDS : 1; /*!< [3..3] desc CCDS */ + __IM uint32_t : 1; + __IOM uint32_t TS : 3; /*!< [7..5] desc TS */ + __IOM uint32_t SMS : 3; /*!< [10..8] desc SMS */ + __IOM uint32_t IA1S : 1; /*!< [11..11] desc IA1S */ + __IOM uint32_t IB1S : 1; /*!< [12..12] desc IB1S */ + } MSCR_f; + } ; + + union { + __IOM uint32_t FLTR; /*!< (@ 0x0000001C) desc FLTR */ + + struct { + __IOM uint32_t OCM1AFLT1A : 3; /*!< [2..0] desc OCM1AFLT1A */ + __IOM uint32_t CCP1A : 1; /*!< [3..3] desc CCP1A */ + __IOM uint32_t OCM1BFLT1B : 3; /*!< [6..4] desc OCM1BFLT1B */ + __IOM uint32_t CCP1B : 1; /*!< [7..7] desc CCP1B */ + __IOM uint32_t OCM2AFLT2A : 3; /*!< [10..8] desc OCM2AFLT2A */ + __IOM uint32_t CCP2A : 1; /*!< [11..11] desc CCP2A */ + __IOM uint32_t OCM2BFLT2B : 3; /*!< [14..12] desc OCM2BFLT2B */ + __IOM uint32_t CCP2B : 1; /*!< [15..15] desc CCP2B */ + __IOM uint32_t OCM3AFLT3A : 3; /*!< [18..16] desc OCM3AFLT3A */ + __IOM uint32_t CCP3A : 1; /*!< [19..19] desc CCP3A */ + __IOM uint32_t OCM3BFLT3B : 3; /*!< [22..20] desc OCM3BFLT3B */ + __IOM uint32_t CCP3B : 1; /*!< [23..23] desc CCP3B */ + __IOM uint32_t FLTBK : 3; /*!< [26..24] desc FLTBK */ + __IOM uint32_t BKP : 1; /*!< [27..27] desc BKP */ + __IOM uint32_t FLTET : 3; /*!< [30..28] desc FLTET */ + __IOM uint32_t ETP : 1; /*!< [31..31] desc ETP */ + } FLTR_f; + } ; + + union { + __IOM uint32_t TRIG; /*!< (@ 0x00000020) desc TRIG */ + + struct { + __IOM uint32_t UEVE : 1; /*!< [0..0] desc UEVE */ + __IOM uint32_t CM1AE : 1; /*!< [1..1] desc CM1AE */ + __IOM uint32_t CM2AE : 1; /*!< [2..2] desc CM2AE */ + __IOM uint32_t CM3AE : 1; /*!< [3..3] desc CM3AE */ + __IOM uint32_t CM1BE : 1; /*!< [4..4] desc CM1BE */ + __IOM uint32_t CM2BE : 1; /*!< [5..5] desc CM2BE */ + __IOM uint32_t CM3BE : 1; /*!< [6..6] desc CM3BE */ + __IOM uint32_t ADTE : 1; /*!< [7..7] desc ADTE */ + } TRIG_f; + } ; + + union { + __IOM uint32_t CH1CR; /*!< (@ 0x00000024) desc CH1CR */ + + struct { + __IOM uint32_t BKSA : 2; /*!< [1..0] desc BKSA */ + __IOM uint32_t BKSB : 2; /*!< [3..2] desc BKSB */ + __IOM uint32_t CSA : 1; /*!< [4..4] desc CSA */ + __IOM uint32_t CSB : 1; /*!< [5..5] desc CSB */ + __IOM uint32_t BUFEA : 1; /*!< [6..6] desc BUFEA */ + __IOM uint32_t BUFEB : 1; /*!< [7..7] desc BUFEB */ + __IOM uint32_t CIEA : 1; /*!< [8..8] desc CIEA */ + __IOM uint32_t CIEB : 1; /*!< [9..9] desc CIEB */ + __IOM uint32_t CDEA : 1; /*!< [10..10] desc CDEA */ + __IOM uint32_t CDEB : 1; /*!< [11..11] desc CDEB */ + __IOM uint32_t CISB : 2; /*!< [13..12] desc CISB */ + __IOM uint32_t CCGA : 1; /*!< [14..14] desc CCGA */ + __IOM uint32_t CCGB : 1; /*!< [15..15] desc CCGB */ + } CH1CR_f; + } ; + + union { + __IOM uint32_t CH2CR; /*!< (@ 0x00000028) desc CH2CR */ + + struct { + __IOM uint32_t BKSA : 2; /*!< [1..0] desc BKSA */ + __IOM uint32_t BKSB : 2; /*!< [3..2] desc BKSB */ + __IOM uint32_t CSA : 1; /*!< [4..4] desc CSA */ + __IOM uint32_t CSB : 1; /*!< [5..5] desc CSB */ + __IOM uint32_t BUFEA : 1; /*!< [6..6] desc BUFEA */ + __IOM uint32_t BUFEB : 1; /*!< [7..7] desc BUFEB */ + __IOM uint32_t CIEA : 1; /*!< [8..8] desc CIEA */ + __IOM uint32_t CIEB : 1; /*!< [9..9] desc CIEB */ + __IOM uint32_t CDEA : 1; /*!< [10..10] desc CDEA */ + __IOM uint32_t CDEB : 1; /*!< [11..11] desc CDEB */ + __IOM uint32_t CISB : 2; /*!< [13..12] desc CISB */ + __IOM uint32_t CCGA : 1; /*!< [14..14] desc CCGA */ + __IOM uint32_t CCGB : 1; /*!< [15..15] desc CCGB */ + } CH2CR_f; + } ; + + union { + __IOM uint32_t CH3CR; /*!< (@ 0x0000002C) desc CH3CR */ + + struct { + __IOM uint32_t BKSA : 2; /*!< [1..0] desc BKSA */ + __IOM uint32_t BKSB : 2; /*!< [3..2] desc BKSB */ + __IOM uint32_t CSA : 1; /*!< [4..4] desc CSA */ + __IOM uint32_t CSB : 1; /*!< [5..5] desc CSB */ + __IOM uint32_t BUFEA : 1; /*!< [6..6] desc BUFEA */ + __IOM uint32_t BUFEB : 1; /*!< [7..7] desc BUFEB */ + __IOM uint32_t CIEA : 1; /*!< [8..8] desc CIEA */ + __IOM uint32_t CIEB : 1; /*!< [9..9] desc CIEB */ + __IOM uint32_t CDEA : 1; /*!< [10..10] desc CDEA */ + __IOM uint32_t CDEB : 1; /*!< [11..11] desc CDEB */ + __IOM uint32_t CISB : 2; /*!< [13..12] desc CISB */ + __IOM uint32_t CCGA : 1; /*!< [14..14] desc CCGA */ + __IOM uint32_t CCGB : 1; /*!< [15..15] desc CCGB */ + } CH3CR_f; + } ; + + union { + __IOM uint32_t DTR; /*!< (@ 0x00000030) desc DTR */ + + struct { + __IOM uint32_t DTR : 8; /*!< [7..0] desc DTR */ + __IM uint32_t : 1; + __IOM uint32_t DTEN : 1; /*!< [9..9] desc DTEN */ + __IOM uint32_t BKE : 1; /*!< [10..10] desc BKE */ + __IOM uint32_t AOE : 1; /*!< [11..11] desc AOE */ + __IOM uint32_t MOE : 1; /*!< [12..12] desc MOE */ + __IOM uint32_t SAFEEN : 1; /*!< [13..13] desc SAFEEN */ + __IOM uint32_t VCE : 1; /*!< [14..14] desc VCE */ + } DTR_f; + } ; + + union { + __IOM uint32_t RCR; /*!< (@ 0x00000034) desc RCR */ + + struct { + __IOM uint32_t RCR : 8; /*!< [7..0] desc RCR */ + __IOM uint32_t OV : 1; /*!< [8..8] desc OV */ + __IOM uint32_t UD : 1; /*!< [9..9] desc UD */ + } RCR_f; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t CH1CCRA; /*!< (@ 0x0000003C) desc CH1CCRA */ + + struct { + __IOM uint32_t CCR1A : 16; /*!< [15..0] desc CCR1A */ + } CH1CCRA_f; + } ; + + union { + __IOM uint32_t CH1CCRB; /*!< (@ 0x00000040) desc CH1CCRB */ + + struct { + __IOM uint32_t CCR1B : 16; /*!< [15..0] desc CCR1B */ + } CH1CCRB_f; + } ; + + union { + __IOM uint32_t CH2CCRA; /*!< (@ 0x00000044) desc CH2CCRA */ + + struct { + __IOM uint32_t CCR2A : 16; /*!< [15..0] desc CCR2A */ + } CH2CCRA_f; + } ; + + union { + __IOM uint32_t CH2CCRB; /*!< (@ 0x00000048) desc CH2CCRB */ + + struct { + __IOM uint32_t CCR2B : 16; /*!< [15..0] desc CCR2B */ + } CH2CCRB_f; + } ; + + union { + __IOM uint32_t CH3CCRA; /*!< (@ 0x0000004C) desc CH3CCRA */ + + struct { + __IOM uint32_t CCR3A : 16; /*!< [15..0] desc CCR3A */ + } CH3CCRA_f; + } ; + + union { + __IOM uint32_t CH3CCRB; /*!< (@ 0x00000050) desc CH3CCRB */ + + struct { + __IOM uint32_t CCR3B : 16; /*!< [15..0] desc CCR3B */ + } CH3CCRB_f; + } ; + + union { + __IOM uint32_t CH4CCR; /*!< (@ 0x00000054) desc CH4CCR */ + + struct { + __IOM uint32_t CCR4 : 16; /*!< [15..0] desc CCR4 */ + } CH4CCR_f; + } ; + + union { + __IOM uint32_t CH4CR; /*!< (@ 0x00000058) desc CH4CR */ + + struct { + __IOM uint32_t BUFE : 1; /*!< [0..0] desc BUFE */ + __IOM uint32_t CIE : 1; /*!< [1..1] desc CIE */ + __IOM uint32_t CDE : 1; /*!< [2..2] desc CDE */ + __IOM uint32_t CIS : 2; /*!< [4..3] desc CIS */ + __IOM uint32_t C4EN : 1; /*!< [5..5] desc C4EN */ + } CH4CR_f; + } ; +} ATIM_TypeDef; /*!< Size = 92 (0x5c) */ + + + +/* =========================================================================================================================== */ +/* ================ AWT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc AWT (AWT) + */ + +typedef struct { /*!< (@ 0x40014C00) AWT Structure */ + + union { + __IOM uint32_t CR; /*!< (@ 0x00000000) Control register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t MD : 2; /*!< [2..1] desc MD */ + __IM uint32_t : 1; + __IOM uint32_t PRS : 4; /*!< [7..4] desc PRS */ + __IOM uint32_t SRC : 3; /*!< [10..8] desc SRC */ + } CR_f; + } ; + + union { + __IOM uint32_t ARR; /*!< (@ 0x00000004) Auto reload register */ + + struct { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } ARR_f; + } ; + + union { + __IM uint32_t CNT; /*!< (@ 0x00000008) counter */ + + struct { + __IM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + } CNT_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000010) Interrupt enable register */ + + struct { + __IM uint32_t : 3; + __IOM uint32_t UD : 1; /*!< [3..3] desc UD */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000014) Interrupt status register */ + + struct { + __IM uint32_t : 3; + __IM uint32_t UD : 1; /*!< [3..3] desc UD */ + } ISR_f; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t ICR; /*!< (@ 0x0000001C) Interrupt flag clear register */ + + struct { + __IM uint32_t : 3; + __IOM uint32_t UD : 1; /*!< [3..3] desc UD */ + } ICR_f; + } ; +} AWT_TypeDef; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ BTIM1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Base Timer 1 (BTIM1) + */ + +typedef struct { /*!< (@ 0x40014800) BTIM1 Structure */ + + union { + __IOM uint32_t ARR; /*!< (@ 0x00000000) Auto Reload Register */ + + struct { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } ARR_f; + } ; + + union { + __IOM uint32_t CNT; /*!< (@ 0x00000004) Counter Register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + } CNT_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t ACR; /*!< (@ 0x0000000C) Advanced Control register */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t ETRFLT : 3; /*!< [6..4] desc ETRFLT */ + } ACR_f; + } ; + + union { + __IOM uint32_t BCR; /*!< (@ 0x00000010) Base Control register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t MODE : 2; /*!< [2..1] desc MODE */ + __IOM uint32_t TRS : 1; /*!< [3..3] desc TRS */ + __IOM uint32_t POL : 1; /*!< [4..4] desc POL */ + __IOM uint32_t ONESHOT : 1; /*!< [5..5] desc ONESHOT */ + __IOM uint32_t TOGEN : 1; /*!< [6..6] desc TOGEN */ + __IOM uint32_t PRS : 4; /*!< [10..7] desc PRS */ + __IM uint32_t PRSSTATUS : 4; /*!< [14..11] desc PRSSTATUS */ + } BCR_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000014) Interrupt enable register */ + + struct { + __IOM uint32_t OV : 1; /*!< [0..0] desc OV */ + __IOM uint32_t TI : 1; /*!< [1..1] desc TI */ + __IOM uint32_t TOP : 1; /*!< [2..2] desc TOP */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000018) Interrupt status register */ + + struct { + __IM uint32_t OV : 1; /*!< [0..0] desc OV */ + __IM uint32_t TI : 1; /*!< [1..1] desc TI */ + __IM uint32_t TOP : 1; /*!< [2..2] desc TOP */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x0000001C) Interrupt flag clear register */ + + struct { + __IOM uint32_t OV : 1; /*!< [0..0] desc OV */ + __IOM uint32_t TI : 1; /*!< [1..1] desc TI */ + __IOM uint32_t TOP : 1; /*!< [2..2] desc TOP */ + } ICR_f; + } ; + + union { + __IOM uint32_t DMA; /*!< (@ 0x00000020) DMA control register */ + + struct { + __IOM uint32_t OV : 1; /*!< [0..0] desc OV */ + __IOM uint32_t TRS : 1; /*!< [1..1] desc TRS */ + } DMA_f; + } ; +} BTIM_TypeDef; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ CRC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc CRC (CRC) + */ + +typedef struct { /*!< (@ 0x40023000) CRC Structure */ + + union { + __IOM uint32_t CR; /*!< (@ 0x00000000) Control register */ + + struct { + __IOM uint32_t MODE : 4; /*!< [3..0] desc MODE */ + } CR_f; + } ; + __IM uint32_t RESERVED; + + union { + union { + __IOM uint32_t DR32; /*!< (@ 0x00000008) Data register */ + + struct { + __IOM uint32_t DR32 : 32; /*!< [31..0] desc DR32 */ + } DR32_f; + } ; + + union { + __IOM uint16_t DR16; /*!< (@ 0x00000008) Data register */ + + struct { + __IOM uint16_t DR16 : 16; /*!< [15..0] desc DR16 */ + } DR16_f; + } ; + + union { + __IOM uint8_t DR8; /*!< (@ 0x00000008) Data register */ + + struct { + __IOM uint8_t DR8 : 8; /*!< [7..0] desc DR8 */ + } DR8_f; + } ; + }; + + union { + union { + __IM uint32_t RESULT32; /*!< (@ 0x0000000C) Result register */ + + struct { + __IM uint32_t RESULT32 : 32; /*!< [31..0] desc RESULT32 */ + } RESULT32_f; + } ; + + union { + __IM uint16_t RESULT16; /*!< (@ 0x0000000C) Result register */ + + struct { + __IM uint16_t RESULT16 : 16; /*!< [15..0] desc RESULT16 */ + } RESULT16_f; + } ; + }; +} CRC_TypeDef; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc DMA (DMA) + */ + +typedef struct { /*!< (@ 0x40020000) DMA Structure */ + + union { + __IM uint32_t ISR; /*!< (@ 0x00000000) Interrupt status register */ + + struct { + __IM uint32_t TC1 : 1; /*!< [0..0] desc TC1 */ + __IM uint32_t TE1 : 1; /*!< [1..1] desc TE1 */ + __IM uint32_t : 2; + __IM uint32_t TC2 : 1; /*!< [4..4] desc TC2 */ + __IM uint32_t TE2 : 1; /*!< [5..5] desc TE2 */ + __IM uint32_t : 2; + __IM uint32_t TC3 : 1; /*!< [8..8] desc TC3 */ + __IM uint32_t TE3 : 1; /*!< [9..9] desc TE3 */ + __IM uint32_t : 2; + __IM uint32_t TC4 : 1; /*!< [12..12] desc TC4 */ + __IM uint32_t TE4 : 1; /*!< [13..13] desc TE4 */ + __IM uint32_t : 2; + __IM uint32_t TC5 : 1; /*!< [16..16] desc TC5 */ + __IM uint32_t TE5 : 1; /*!< [17..17] desc TE5 */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000004) Interrupt flag clear register */ + + struct { + __IOM uint32_t TC1 : 1; /*!< [0..0] desc TC1 */ + __IOM uint32_t TE1 : 1; /*!< [1..1] desc TE1 */ + __IM uint32_t : 2; + __IOM uint32_t TC2 : 1; /*!< [4..4] desc TC2 */ + __IOM uint32_t TE2 : 1; /*!< [5..5] desc TE2 */ + __IM uint32_t : 2; + __IOM uint32_t TC3 : 1; /*!< [8..8] desc TC3 */ + __IOM uint32_t TE3 : 1; /*!< [9..9] desc TE3 */ + __IM uint32_t : 2; + __IOM uint32_t TC4 : 1; /*!< [12..12] desc TC4 */ + __IOM uint32_t TE4 : 1; /*!< [13..13] desc TE4 */ + __IM uint32_t : 2; + __IOM uint32_t TC5 : 1; /*!< [16..16] desc TC5 */ + __IOM uint32_t TE5 : 1; /*!< [17..17] desc TE5 */ + } ICR_f; + } ; + __IM uint32_t RESERVED[6]; + + union { + __IOM uint32_t CSR1; /*!< (@ 0x00000020) Channel1 control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + } CSR1_f; + } ; + + union { + __IOM uint32_t CNT1; /*!< (@ 0x00000024) Channel1 counter register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT1_f; + } ; + + union { + __IOM uint32_t SRCADDR1; /*!< (@ 0x00000028) Channel1 source address register */ + + struct { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR1_f; + } ; + + union { + __IOM uint32_t DSTADDR1; /*!< (@ 0x0000002C) Channel1 destination address register */ + + struct { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR1_f; + } ; + + union { + __IOM uint32_t TRIG1; /*!< (@ 0x00000030) Channel1 trigger register */ + + struct { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG1_f; + } ; + __IM uint32_t RESERVED1[3]; + + union { + __IOM uint32_t CSR2; /*!< (@ 0x00000040) Channel2 control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + } CSR2_f; + } ; + + union { + __IOM uint32_t CNT2; /*!< (@ 0x00000044) Channel2 counter register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT2_f; + } ; + + union { + __IOM uint32_t SRCADDR2; /*!< (@ 0x00000048) Channel2 source address register */ + + struct { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR2_f; + } ; + + union { + __IOM uint32_t DSTADDR2; /*!< (@ 0x0000004C) Channel2 destination address register */ + + struct { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR2_f; + } ; + + union { + __IOM uint32_t TRIG2; /*!< (@ 0x00000050) Channel2 trigger register */ + + struct { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG2_f; + } ; + __IM uint32_t RESERVED2[3]; + + union { + __IOM uint32_t CSR3; /*!< (@ 0x00000060) Channel3 control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + } CSR3_f; + } ; + + union { + __IOM uint32_t CNT3; /*!< (@ 0x00000064) Channel3 counter register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT3_f; + } ; + + union { + __IOM uint32_t SRCADDR3; /*!< (@ 0x00000068) Channel3 source address register */ + + struct { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR3_f; + } ; + + union { + __IOM uint32_t DSTADDR3; /*!< (@ 0x0000006C) Channel3 destination address register */ + + struct { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR3_f; + } ; + + union { + __IOM uint32_t TRIG3; /*!< (@ 0x00000070) Channel3 trigger register */ + + struct { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG3_f; + } ; + __IM uint32_t RESERVED3[3]; + + union { + __IOM uint32_t CSR4; /*!< (@ 0x00000080) Channel4 control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + } CSR4_f; + } ; + + union { + __IOM uint32_t CNT4; /*!< (@ 0x00000084) Channel4 counter register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT4_f; + } ; + + union { + __IOM uint32_t SRCADDR4; /*!< (@ 0x00000088) Channel4 source address register */ + + struct { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR4_f; + } ; + + union { + __IOM uint32_t DSTADDR4; /*!< (@ 0x0000008C) Channel4 destination address register */ + + struct { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR4_f; + } ; + + union { + __IOM uint32_t TRIG4; /*!< (@ 0x00000090) Channel4 trigger register */ + + struct { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG4_f; + } ; + __IM uint32_t RESERVED4[3]; + + union { + __IOM uint32_t CSR5; /*!< (@ 0x000000A0) Channel5 control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + } CSR5_f; + } ; + + union { + __IOM uint32_t CNT5; /*!< (@ 0x000000A4) Channel5 counter register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT5_f; + } ; + + union { + __IOM uint32_t SRCADDR5; /*!< (@ 0x000000A8) Channel5 source address register */ + + struct { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR5_f; + } ; + + union { + __IOM uint32_t DSTADDR5; /*!< (@ 0x000000AC) Channel5 destination address register */ + + struct { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR5_f; + } ; + + union { + __IOM uint32_t TRIG5; /*!< (@ 0x000000B0) Channel5 trigger register */ + + struct { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG5_f; + } ; +} DMA_TypeDef; /*!< Size = 180 (0xb4) */ + + + +/* =========================================================================================================================== */ +/* ================ DMACHANNEL1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DMA Channel 1 (DMACHANNEL1) + */ + +typedef struct { /*!< (@ 0x40020020) DMACHANNEL1 Structure */ + + union { + __IOM uint32_t CSR; /*!< (@ 0x00000000) Channel.y control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + } CSR_f; + } ; + + union { + __IOM uint32_t CNT; /*!< (@ 0x00000004) Channel.y counter register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT_f; + } ; + + union { + __IOM uint32_t SRCADDR; /*!< (@ 0x00000008) Channel.y source address register */ + + struct { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR_f; + } ; + + union { + __IOM uint32_t DSTADDR; /*!< (@ 0x0000000C) Channel.y destination address register */ + + struct { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR_f; + } ; + + union { + __IOM uint32_t TRIG; /*!< (@ 0x00000010) Channel.y trigger register */ + + struct { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG_f; + } ; +} DMACHANNEL_TypeDef; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ FLASH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc FLASH (FLASH) + */ + +typedef struct { /*!< (@ 0x40022000) FLASH Structure */ + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t MODE : 2; /*!< [1..0] desc MODE */ + __IM uint32_t : 2; + __IOM uint32_t STANDBY : 1; /*!< [4..4] desc STANDBY */ + __IM uint32_t BUSY : 1; /*!< [5..5] desc BUSY */ + __IM uint32_t SECURITY : 2; /*!< [7..6] desc SECURITY */ + __IM uint32_t : 8; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000004) Control register2 */ + + struct { + __IOM uint32_t WAIT : 3; /*!< [2..0] desc WAIT */ + __IOM uint32_t FETCH : 1; /*!< [3..3] desc FETCH */ + __IOM uint32_t CACHE : 1; /*!< [4..4] desc CACHE */ + __IM uint32_t : 11; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR2_f; + } ; + + union { + __IOM uint32_t PAGELOCK; /*!< (@ 0x00000008) Page Write Erase Lock */ + + struct { + __IOM uint32_t LOCK0 : 1; /*!< [0..0] Page0 - 7 */ + __IOM uint32_t LOCK1 : 1; /*!< [1..1] Page8 - 15 */ + __IOM uint32_t LOCK2 : 1; /*!< [2..2] Page16 - 23 */ + __IOM uint32_t LOCK3 : 1; /*!< [3..3] Page24 - 31 */ + __IOM uint32_t LOCK4 : 1; /*!< [4..4] Page32 - 39 */ + __IOM uint32_t LOCK5 : 1; /*!< [5..5] Page40 - 47 */ + __IOM uint32_t LOCK6 : 1; /*!< [6..6] Page48 - 55 */ + __IOM uint32_t LOCK7 : 1; /*!< [7..7] Page56 - 63 */ + __IOM uint32_t LOCK8 : 1; /*!< [8..8] Page64 - 71 */ + __IOM uint32_t LOCK9 : 1; /*!< [9..9] Page72 - 79 */ + __IOM uint32_t LOCK10 : 1; /*!< [10..10] Page80 - 87 */ + __IOM uint32_t LOCK11 : 1; /*!< [11..11] Page88 - 95 */ + __IOM uint32_t LOCK12 : 1; /*!< [12..12] Page96 - 103 */ + __IOM uint32_t LOCK13 : 1; /*!< [13..13] Page104 - 111 */ + __IOM uint32_t LOCK14 : 1; /*!< [14..14] Page112 - 119 */ + __IOM uint32_t LOCK15 : 1; /*!< [15..15] Page120 - 127 */ + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } PAGELOCK_f; + } ; + __IM uint32_t RESERVED[5]; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000020) Interrupt enable register */ + + struct { + __IOM uint32_t PC : 1; /*!< [0..0] desc PC */ + __IOM uint32_t PAGELOCK : 1; /*!< [1..1] desc PAGELOCK */ + __IM uint32_t : 2; + __IOM uint32_t PROG : 1; /*!< [4..4] desc PROG */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000024) Interrupt status register */ + + struct { + __IM uint32_t PC : 1; /*!< [0..0] desc PC */ + __IM uint32_t PAGELOCK : 1; /*!< [1..1] desc PAGELOCK */ + __IM uint32_t : 2; + __IM uint32_t PROG : 1; /*!< [4..4] desc PROG */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000028) Interrupt flag clear register */ + + struct { + __IOM uint32_t PC : 1; /*!< [0..0] desc PC */ + __IOM uint32_t PAGELOCK : 1; /*!< [1..1] desc PAGELOCK */ + __IM uint32_t : 2; + __IOM uint32_t PROG : 1; /*!< [4..4] desc PROG */ + } ICR_f; + } ; +} FLASH_TypeDef; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc GPIOA (GPIOA) + */ + +typedef struct { /*!< (@ 0x48000000) GPIOA Structure */ + + union { + __IOM uint32_t DIR; /*!< (@ 0x00000000) desc DIR */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } DIR_f; + } ; + + union { + __IOM uint32_t OPENDRAIN; /*!< (@ 0x00000004) desc OPENDRAIN */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } OPENDRAIN_f; + } ; + + union { + __IOM uint32_t SPEED; /*!< (@ 0x00000008) desc SPEED */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } SPEED_f; + } ; + + union { + __IOM uint32_t PDR; /*!< (@ 0x0000000C) desc PDR */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } PDR_f; + } ; + + union { + __IOM uint32_t PUR; /*!< (@ 0x00000010) desc PUR */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } PUR_f; + } ; + + union { + __IOM uint32_t AFRH; /*!< (@ 0x00000014) desc AFRH */ + + struct { + __IOM uint32_t AFR8 : 4; /*!< [3..0] desc AFR8 */ + __IOM uint32_t AFR9 : 4; /*!< [7..4] desc AFR9 */ + __IOM uint32_t AFR10 : 4; /*!< [11..8] desc AFR10 */ + __IOM uint32_t AFR11 : 4; /*!< [15..12] desc AFR11 */ + __IOM uint32_t AFR12 : 4; /*!< [19..16] desc AFR12 */ + __IOM uint32_t AFR13 : 4; /*!< [23..20] desc AFR13 */ + __IOM uint32_t AFR14 : 4; /*!< [27..24] desc AFR14 */ + __IOM uint32_t AFR15 : 4; /*!< [31..28] desc AFR15 */ + } AFRH_f; + } ; + + union { + __IOM uint32_t AFRL; /*!< (@ 0x00000018) desc AFRL */ + + struct { + __IOM uint32_t AFR0 : 4; /*!< [3..0] desc AFR0 */ + __IOM uint32_t AFR1 : 4; /*!< [7..4] desc AFR1 */ + __IOM uint32_t AFR2 : 4; /*!< [11..8] desc AFR2 */ + __IOM uint32_t AFR3 : 4; /*!< [15..12] desc AFR3 */ + __IOM uint32_t AFR4 : 4; /*!< [19..16] desc AFR4 */ + __IOM uint32_t AFR5 : 4; /*!< [23..20] desc AFR5 */ + __IOM uint32_t AFR6 : 4; /*!< [27..24] desc AFR6 */ + __IOM uint32_t AFR7 : 4; /*!< [31..28] desc AFR7 */ + } AFRL_f; + } ; + + union { + __IOM uint32_t ANALOG; /*!< (@ 0x0000001C) desc ANALOG */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ANALOG_f; + } ; + + union { + __IOM uint32_t DRIVER; /*!< (@ 0x00000020) desc DRIVER */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } DRIVER_f; + } ; + + union { + __IOM uint32_t RISEIE; /*!< (@ 0x00000024) Interrupt enable register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } RISEIE_f; + } ; + + union { + __IOM uint32_t FALLIE; /*!< (@ 0x00000028) Interrupt enable register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } FALLIE_f; + } ; + + union { + __IOM uint32_t HIGHIE; /*!< (@ 0x0000002C) Interrupt enable register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } HIGHIE_f; + } ; + + union { + __IOM uint32_t LOWIE; /*!< (@ 0x00000030) Interrupt enable register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } LOWIE_f; + } ; + + union { + __IOM uint32_t ISR; /*!< (@ 0x00000034) Interrupt status register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000038) Interrupt flag clear register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ICR_f; + } ; + + union { + __IOM uint32_t LOCK; /*!< (@ 0x0000003C) desc LOCK */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + __OM uint32_t KEY : 16; /*!< [31..16] KEY = 0x5A5A */ + } LOCK_f; + } ; + + union { + __IOM uint32_t FILTER; /*!< (@ 0x00000040) desc FILTER */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + __IOM uint32_t FLTCLK : 3; /*!< [18..16] desc FLTCLK */ + } FILTER_f; + } ; + __IM uint32_t RESERVED[3]; + + union { + __IOM uint32_t IDR; /*!< (@ 0x00000050) desc IDR */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } IDR_f; + } ; + + union { + union { + __IOM uint32_t ODR; /*!< (@ 0x00000054) desc ODR */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ODR_f; + } ; + + struct { + union { + __IOM uint8_t ODRLOWBYTE; /*!< (@ 0x00000054) desc ODRLOWBYTE */ + + struct { + __IOM uint8_t LOWBYTE : 8; /*!< [7..0] desc LOWBYTE */ + } ODRLOWBYTE_f; + } ; + + union { + __IOM uint8_t ODRHIGHBYTE; /*!< (@ 0x00000055) desc ODRHIGHBYTE */ + + struct { + __IOM uint8_t HIGHBYTE : 8; /*!< [7..0] desc HIGHBYTE */ + } ODRHIGHBYTE_f; + } ; + }; + }; + + union { + __IOM uint32_t BRR; /*!< (@ 0x00000058) desc BRR */ + + struct { + __IOM uint32_t BRR0 : 1; /*!< [0..0] desc BRR0 */ + __IOM uint32_t BRR1 : 1; /*!< [1..1] desc BRR1 */ + __IOM uint32_t BRR2 : 1; /*!< [2..2] desc BRR2 */ + __IOM uint32_t BRR3 : 1; /*!< [3..3] desc BRR3 */ + __IOM uint32_t BRR4 : 1; /*!< [4..4] desc BRR4 */ + __IOM uint32_t BRR5 : 1; /*!< [5..5] desc BRR5 */ + __IOM uint32_t BRR6 : 1; /*!< [6..6] desc BRR6 */ + __IOM uint32_t BRR7 : 1; /*!< [7..7] desc BRR7 */ + __IOM uint32_t BRR8 : 1; /*!< [8..8] desc BRR8 */ + __IOM uint32_t BRR9 : 1; /*!< [9..9] desc BRR9 */ + __IOM uint32_t BRR10 : 1; /*!< [10..10] desc BRR10 */ + __IOM uint32_t BRR11 : 1; /*!< [11..11] desc BRR11 */ + __IOM uint32_t BRR12 : 1; /*!< [12..12] desc BRR12 */ + __IOM uint32_t BRR13 : 1; /*!< [13..13] desc BRR13 */ + __IOM uint32_t BRR14 : 1; /*!< [14..14] desc BRR14 */ + __IOM uint32_t BRR15 : 1; /*!< [15..15] desc BRR15 */ + } BRR_f; + } ; + + union { + __IOM uint32_t BSRR; /*!< (@ 0x0000005C) desc BSRR */ + + struct { + __IOM uint32_t BSS0 : 1; /*!< [0..0] desc BSS0 */ + __IOM uint32_t BSS1 : 1; /*!< [1..1] desc BSS1 */ + __IOM uint32_t BSS2 : 1; /*!< [2..2] desc BSS2 */ + __IOM uint32_t BSS3 : 1; /*!< [3..3] desc BSS3 */ + __IOM uint32_t BSS4 : 1; /*!< [4..4] desc BSS4 */ + __IOM uint32_t BSS5 : 1; /*!< [5..5] desc BSS5 */ + __IOM uint32_t BSS6 : 1; /*!< [6..6] desc BSS6 */ + __IOM uint32_t BSS7 : 1; /*!< [7..7] desc BSS7 */ + __IOM uint32_t BSS8 : 1; /*!< [8..8] desc BSS8 */ + __IOM uint32_t BSS9 : 1; /*!< [9..9] desc BSS9 */ + __IOM uint32_t BSS10 : 1; /*!< [10..10] desc BSS10 */ + __IOM uint32_t BSS11 : 1; /*!< [11..11] desc BSS11 */ + __IOM uint32_t BSS12 : 1; /*!< [12..12] desc BSS12 */ + __IOM uint32_t BSS13 : 1; /*!< [13..13] desc BSS13 */ + __IOM uint32_t BSS14 : 1; /*!< [14..14] desc BSS14 */ + __IOM uint32_t BSS15 : 1; /*!< [15..15] desc BSS15 */ + __IOM uint32_t BRR0 : 1; /*!< [16..16] desc BRR0 */ + __IOM uint32_t BRR1 : 1; /*!< [17..17] desc BRR1 */ + __IOM uint32_t BRR2 : 1; /*!< [18..18] desc BRR2 */ + __IOM uint32_t BRR3 : 1; /*!< [19..19] desc BRR3 */ + __IOM uint32_t BRR4 : 1; /*!< [20..20] desc BRR4 */ + __IOM uint32_t BRR5 : 1; /*!< [21..21] desc BRR5 */ + __IOM uint32_t BRR6 : 1; /*!< [22..22] desc BRR6 */ + __IOM uint32_t BRR7 : 1; /*!< [23..23] desc BRR7 */ + __IOM uint32_t BRR8 : 1; /*!< [24..24] desc BRR8 */ + __IOM uint32_t BRR9 : 1; /*!< [25..25] desc BRR9 */ + __IOM uint32_t BRR10 : 1; /*!< [26..26] desc BRR10 */ + __IOM uint32_t BRR11 : 1; /*!< [27..27] desc BRR11 */ + __IOM uint32_t BRR12 : 1; /*!< [28..28] desc BRR12 */ + __IOM uint32_t BRR13 : 1; /*!< [29..29] desc BRR13 */ + __IOM uint32_t BRR14 : 1; /*!< [30..30] desc BRR14 */ + __IOM uint32_t BRR15 : 1; /*!< [31..31] desc BRR15 */ + } BSRR_f; + } ; + + union { + __IOM uint32_t TOG; /*!< (@ 0x00000060) desc TOG */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } TOG_f; + } ; +} GPIO_TypeDef; /*!< Size = 100 (0x64) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc GPIOC (GPIOC) + */ + +typedef struct { /*!< (@ 0x48000800) GPIOC Structure */ + + union { + __IOM uint32_t DIR; /*!< (@ 0x00000000) desc DIR */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } DIR_f; + } ; + + union { + __IOM uint32_t OPENDRAIN; /*!< (@ 0x00000004) desc OPENDRAIN */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } OPENDRAIN_f; + } ; + + union { + __IOM uint32_t SPEED; /*!< (@ 0x00000008) desc SPEED */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } SPEED_f; + } ; + + union { + __IOM uint32_t PDR; /*!< (@ 0x0000000C) desc PDR */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } PDR_f; + } ; + + union { + __IOM uint32_t PUR; /*!< (@ 0x00000010) desc PUR */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } PUR_f; + } ; + + union { + __IOM uint32_t AFRH; /*!< (@ 0x00000014) desc AFRH */ + + struct { + __IM uint32_t : 20; + __IOM uint32_t AFR13 : 4; /*!< [23..20] desc AFR13 */ + __IOM uint32_t AFR14 : 4; /*!< [27..24] desc AFR14 */ + __IOM uint32_t AFR15 : 4; /*!< [31..28] desc AFR15 */ + } AFRH_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t ANALOG; /*!< (@ 0x0000001C) desc ANALOG */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ANALOG_f; + } ; + + union { + __IOM uint32_t DRIVER; /*!< (@ 0x00000020) desc DRIVER */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } DRIVER_f; + } ; + + union { + __IOM uint32_t RISEIE; /*!< (@ 0x00000024) Interrupt enable register */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } RISEIE_f; + } ; + + union { + __IOM uint32_t FALLIE; /*!< (@ 0x00000028) Interrupt enable register */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } FALLIE_f; + } ; + + union { + __IOM uint32_t HIGHIE; /*!< (@ 0x0000002C) Interrupt enable register */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } HIGHIE_f; + } ; + + union { + __IOM uint32_t LOWIE; /*!< (@ 0x00000030) Interrupt enable register */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } LOWIE_f; + } ; + + union { + __IOM uint32_t ISR; /*!< (@ 0x00000034) Interrupt status register */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000038) Interrupt flag clear register */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ICR_f; + } ; + + union { + __IOM uint32_t LOCK; /*!< (@ 0x0000003C) desc LOCK */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + __OM uint32_t KEY : 16; /*!< [31..16] KEY = 0x5A5A */ + } LOCK_f; + } ; + + union { + __IOM uint32_t FILTER; /*!< (@ 0x00000040) desc FILTER */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + __IOM uint32_t FLTCLK : 3; /*!< [18..16] desc FLTCLK */ + } FILTER_f; + } ; + __IM uint32_t RESERVED1[3]; + + union { + __IOM uint32_t IDR; /*!< (@ 0x00000050) desc IDR */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } IDR_f; + } ; + + union { + union { + __IOM uint32_t ODR; /*!< (@ 0x00000054) desc ODR */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ODR_f; + } ; + + struct { + union { + __IOM uint8_t ODRLOWBYTE; /*!< (@ 0x00000054) desc ODRLOWBYTE */ + + struct { + __IOM uint8_t LOWBYTE : 8; /*!< [7..0] desc LOWBYTE */ + } ODRLOWBYTE_f; + } ; + + union { + __IOM uint8_t ODRHIGHBYTE; /*!< (@ 0x00000055) desc ODRHIGHBYTE */ + + struct { + __IOM uint8_t HIGHBYTE : 8; /*!< [7..0] desc HIGHBYTE */ + } ODRHIGHBYTE_f; + } ; + }; + }; + + union { + __IOM uint32_t BRR; /*!< (@ 0x00000058) desc BRR */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t BRR13 : 1; /*!< [13..13] desc BRR13 */ + __IOM uint32_t BRR14 : 1; /*!< [14..14] desc BRR14 */ + __IOM uint32_t BRR15 : 1; /*!< [15..15] desc BRR15 */ + } BRR_f; + } ; + + union { + __IOM uint32_t BSRR; /*!< (@ 0x0000005C) desc BSRR */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t BSS13 : 1; /*!< [13..13] desc BSS13 */ + __IOM uint32_t BSS14 : 1; /*!< [14..14] desc BSS14 */ + __IOM uint32_t BSS15 : 1; /*!< [15..15] desc BSS15 */ + __IM uint32_t : 13; + __IOM uint32_t BRR13 : 1; /*!< [29..29] desc BRR13 */ + __IOM uint32_t BRR14 : 1; /*!< [30..30] desc BRR14 */ + __IOM uint32_t BRR15 : 1; /*!< [31..31] desc BRR15 */ + } BSRR_f; + } ; + + union { + __IOM uint32_t TOG; /*!< (@ 0x00000060) desc TOG */ + + struct { + __IM uint32_t : 13; + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } TOG_f; + } ; +} GPIOC_TypeDef; /*!< Size = 100 (0x64) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOF ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc GPIOF (GPIOF) + */ + +typedef struct { /*!< (@ 0x48001400) GPIOF Structure */ + + union { + __IOM uint32_t DIR; /*!< (@ 0x00000000) desc DIR */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } DIR_f; + } ; + + union { + __IOM uint32_t OPENDRAIN; /*!< (@ 0x00000004) desc OPENDRAIN */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } OPENDRAIN_f; + } ; + + union { + __IOM uint32_t SPEED; /*!< (@ 0x00000008) desc SPEED */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } SPEED_f; + } ; + + union { + __IOM uint32_t PDR; /*!< (@ 0x0000000C) desc PDR */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } PDR_f; + } ; + + union { + __IOM uint32_t PUR; /*!< (@ 0x00000010) desc PUR */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } PUR_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t AFRL; /*!< (@ 0x00000018) desc AFRL */ + + struct { + __IOM uint32_t AFR0 : 4; /*!< [3..0] desc AFR0 */ + __IOM uint32_t AFR1 : 4; /*!< [7..4] desc AFR1 */ + __IM uint32_t : 4; + __IOM uint32_t AFR3 : 4; /*!< [15..12] desc AFR3 */ + __IM uint32_t : 8; + __IOM uint32_t AFR6 : 4; /*!< [27..24] desc AFR6 */ + __IOM uint32_t AFR7 : 4; /*!< [31..28] desc AFR7 */ + } AFRL_f; + } ; + + union { + __IOM uint32_t ANALOG; /*!< (@ 0x0000001C) desc ANALOG */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } ANALOG_f; + } ; + + union { + __IOM uint32_t DRIVER; /*!< (@ 0x00000020) desc DRIVER */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } DRIVER_f; + } ; + + union { + __IOM uint32_t RISEIE; /*!< (@ 0x00000024) Interrupt enable register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } RISEIE_f; + } ; + + union { + __IOM uint32_t FALLIE; /*!< (@ 0x00000028) Interrupt enable register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } FALLIE_f; + } ; + + union { + __IOM uint32_t HIGHIE; /*!< (@ 0x0000002C) Interrupt enable register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } HIGHIE_f; + } ; + + union { + __IOM uint32_t LOWIE; /*!< (@ 0x00000030) Interrupt enable register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } LOWIE_f; + } ; + + union { + __IOM uint32_t ISR; /*!< (@ 0x00000034) Interrupt status register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000038) Interrupt flag clear register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } ICR_f; + } ; + + union { + __IOM uint32_t LOCK; /*!< (@ 0x0000003C) desc LOCK */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IM uint32_t : 8; + __OM uint32_t KEY : 16; /*!< [31..16] KEY = 0x5A5A */ + } LOCK_f; + } ; + + union { + __IOM uint32_t FILTER; /*!< (@ 0x00000040) desc FILTER */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IM uint32_t : 8; + __IOM uint32_t FLTCLK : 3; /*!< [18..16] desc FLTCLK */ + } FILTER_f; + } ; + __IM uint32_t RESERVED1[3]; + + union { + __IOM uint32_t IDR; /*!< (@ 0x00000050) desc IDR */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } IDR_f; + } ; + + union { + union { + __IOM uint32_t ODR; /*!< (@ 0x00000054) desc ODR */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } ODR_f; + } ; + + union { + __IOM uint8_t ODRLOWBYTE; /*!< (@ 0x00000054) desc ODRLOWBYTE */ + + struct { + __IOM uint8_t LOWBYTE : 8; /*!< [7..0] desc LOWBYTE */ + } ODRLOWBYTE_f; + } ; + }; + + union { + __IOM uint32_t BRR; /*!< (@ 0x00000058) desc BRR */ + + struct { + __IOM uint32_t BRR0 : 1; /*!< [0..0] desc BRR0 */ + __IOM uint32_t BRR1 : 1; /*!< [1..1] desc BRR1 */ + __IM uint32_t : 1; + __IOM uint32_t BRR3 : 1; /*!< [3..3] desc BRR3 */ + __IM uint32_t : 2; + __IOM uint32_t BRR6 : 1; /*!< [6..6] desc BRR6 */ + __IOM uint32_t BRR7 : 1; /*!< [7..7] desc BRR7 */ + } BRR_f; + } ; + + union { + __IOM uint32_t BSRR; /*!< (@ 0x0000005C) desc BSRR */ + + struct { + __IOM uint32_t BSS0 : 1; /*!< [0..0] desc BSS0 */ + __IOM uint32_t BSS1 : 1; /*!< [1..1] desc BSS1 */ + __IM uint32_t : 1; + __IOM uint32_t BSS3 : 1; /*!< [3..3] desc BSS3 */ + __IM uint32_t : 2; + __IOM uint32_t BSS6 : 1; /*!< [6..6] desc BSS6 */ + __IOM uint32_t BSS7 : 1; /*!< [7..7] desc BSS7 */ + } BSRR_f; + } ; + + union { + __IOM uint32_t TOG; /*!< (@ 0x00000060) desc TOG */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t : 1; + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t : 2; + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + } TOG_f; + } ; +} GPIOF_TypeDef; /*!< Size = 100 (0x64) */ + + + +/* =========================================================================================================================== */ +/* ================ GTIM1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Timer 1 (GTIM1) + */ + +typedef struct { /*!< (@ 0x40000400) GTIM1 Structure */ + __IM uint32_t RESERVED[192]; + + union { + __IOM uint32_t ARR; /*!< (@ 0x00000300) Auto Reload Register */ + + struct { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } ARR_f; + } ; + + union { + __IOM uint32_t CNT; /*!< (@ 0x00000304) Counter Register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + } CNT_f; + } ; + + union { + __IOM uint32_t CMMR; /*!< (@ 0x00000308) Capture compare control Register */ + + struct { + __IOM uint32_t CC1M : 4; /*!< [3..0] desc CC1M */ + __IOM uint32_t CC2M : 4; /*!< [7..4] desc CC2M */ + __IOM uint32_t CC3M : 4; /*!< [11..8] desc CC3M */ + __IOM uint32_t CC4M : 4; /*!< [15..12] desc CC4M */ + } CMMR_f; + } ; + + union { + __IOM uint32_t ETR; /*!< (@ 0x0000030C) ETR Control register */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t ETRFLT : 3; /*!< [6..4] desc ETRFLT */ + } ETR_f; + } ; + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000310) Control register0 */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t MODE : 2; /*!< [2..1] desc MODE */ + __IOM uint32_t TRS : 1; /*!< [3..3] desc TRS */ + __IOM uint32_t POL : 1; /*!< [4..4] desc POL */ + __IOM uint32_t ONESHOT : 1; /*!< [5..5] desc ONESHOT */ + __IOM uint32_t TOGEN : 1; /*!< [6..6] desc TOGEN */ + __IOM uint32_t PRS : 4; /*!< [10..7] desc PRS */ + __IM uint32_t PRSSTATUS : 4; /*!< [14..11] desc PRSSTATUS */ + __IOM uint32_t ENCMODE : 2; /*!< [16..15] desc ENCMODE */ + __IOM uint32_t ENCRESET : 2; /*!< [18..17] desc ENCRESET */ + __IOM uint32_t ENCRELOAD : 2; /*!< [20..19] desc ENCRELOAD */ + } CR0_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000314) Interrupt enable register */ + + struct { + __IOM uint32_t OV : 1; /*!< [0..0] desc OV */ + __IOM uint32_t TI : 1; /*!< [1..1] desc TI */ + __IOM uint32_t UD : 1; /*!< [2..2] desc UD */ + __IOM uint32_t CC1 : 1; /*!< [3..3] desc CC1 */ + __IOM uint32_t CC2 : 1; /*!< [4..4] desc CC2 */ + __IOM uint32_t CC3 : 1; /*!< [5..5] desc CC3 */ + __IOM uint32_t CC4 : 1; /*!< [6..6] desc CC4 */ + __IM uint32_t : 2; + __IOM uint32_t DIRCHANGE : 1; /*!< [9..9] desc DIRCHANGE */ + } IER_f; + } ; + + union { + __IOM uint32_t ISR; /*!< (@ 0x00000318) Interrupt status register */ + + struct { + __IOM uint32_t OV : 1; /*!< [0..0] desc OV */ + __IOM uint32_t TI : 1; /*!< [1..1] desc TI */ + __IOM uint32_t UD : 1; /*!< [2..2] desc UD */ + __IM uint32_t CC1 : 1; /*!< [3..3] desc CC1 */ + __IM uint32_t CC2 : 1; /*!< [4..4] desc CC2 */ + __IM uint32_t CC3 : 1; /*!< [5..5] desc CC3 */ + __IM uint32_t CC4 : 1; /*!< [6..6] desc CC4 */ + __IM uint32_t : 2; + __IM uint32_t DIRCHANGE : 1; /*!< [9..9] desc DIRCHANGE */ + __IM uint32_t DIR : 1; /*!< [10..10] desc DIR */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x0000031C) Interrupt flag clear register */ + + struct { + __IOM uint32_t OV : 1; /*!< [0..0] desc OV */ + __IOM uint32_t TI : 1; /*!< [1..1] desc TI */ + __IOM uint32_t UD : 1; /*!< [2..2] desc UD */ + __IOM uint32_t CC1 : 1; /*!< [3..3] desc CC1 */ + __IOM uint32_t CC2 : 1; /*!< [4..4] desc CC2 */ + __IOM uint32_t CC3 : 1; /*!< [5..5] desc CC3 */ + __IOM uint32_t CC4 : 1; /*!< [6..6] desc CC4 */ + __IM uint32_t : 2; + __IOM uint32_t DIRCHANGE : 1; /*!< [9..9] desc DIRCHANGE */ + } ICR_f; + } ; + + union { + __IOM uint32_t CCR1; /*!< (@ 0x00000320) capture compare register */ + + struct { + __IOM uint32_t CCR : 16; /*!< [15..0] desc CCR */ + } CCR1_f; + } ; + + union { + __IOM uint32_t CCR2; /*!< (@ 0x00000324) capture compare register */ + + struct { + __IOM uint32_t CCR : 16; /*!< [15..0] desc CCR */ + } CCR2_f; + } ; + + union { + __IOM uint32_t CCR3; /*!< (@ 0x00000328) capture compare register */ + + struct { + __IOM uint32_t CCR : 16; /*!< [15..0] desc CCR */ + } CCR3_f; + } ; + + union { + __IOM uint32_t CCR4; /*!< (@ 0x0000032C) capture compare register */ + + struct { + __IOM uint32_t CCR : 16; /*!< [15..0] desc CCR */ + } CCR4_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000330) Control register1 */ + + struct { + __IOM uint32_t CH1FLT : 3; /*!< [2..0] desc CH1FLT */ + __IOM uint32_t CH1POL : 1; /*!< [3..3] desc CH1POL */ + __IOM uint32_t CH2FLT : 3; /*!< [6..4] desc CH2FLT */ + __IOM uint32_t CH2POL : 1; /*!< [7..7] desc CH2POL */ + __IOM uint32_t CH3FLT : 3; /*!< [10..8] desc CH3FLT */ + __IOM uint32_t CH3POL : 1; /*!< [11..11] desc CH3POL */ + __IOM uint32_t CH4FLT : 3; /*!< [14..12] desc CH4FLT */ + __IOM uint32_t CH4POL : 1; /*!< [15..15] desc CH4POL */ + } CR1_f; + } ; + __IM uint32_t RESERVED1[3]; + + union { + __IOM uint32_t DMA; /*!< (@ 0x00000340) DMA Control register */ + + struct { + __IOM uint32_t OV : 1; /*!< [0..0] desc OV */ + __IOM uint32_t TRS : 1; /*!< [1..1] desc TRS */ + __IOM uint32_t CC1 : 1; /*!< [2..2] desc CC1 */ + __IOM uint32_t CC2 : 1; /*!< [3..3] desc CC2 */ + __IOM uint32_t CC3 : 1; /*!< [4..4] desc CC3 */ + __IOM uint32_t CC4 : 1; /*!< [5..5] desc CC4 */ + } DMA_f; + } ; +} GTIM_TypeDef; /*!< Size = 836 (0x344) */ + + + +/* =========================================================================================================================== */ +/* ================ I2C1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc I2C1 (I2C1) + */ + +typedef struct { /*!< (@ 0x40005400) I2C1 Structure */ + + union { + __IOM uint32_t BRREN; /*!< (@ 0x00000000) desc BRREN */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + } BRREN_f; + } ; + + union { + __IOM uint32_t BRR; /*!< (@ 0x00000004) desc BRR */ + + struct { + __IOM uint32_t BRR : 8; /*!< [7..0] fSCL = fPCLK / 8 / (BRR+1) */ + } BRR_f; + } ; + + union { + __IOM uint32_t CR; /*!< (@ 0x00000008) Control register */ + + struct { + __IOM uint32_t FLT : 1; /*!< [0..0] desc FLT */ + __IM uint32_t : 1; + __IOM uint32_t AA : 1; /*!< [2..2] desc AA */ + __IOM uint32_t SI : 1; /*!< [3..3] desc SI */ + __IOM uint32_t STO : 1; /*!< [4..4] desc STO */ + __IOM uint32_t STA : 1; /*!< [5..5] desc STA */ + __IOM uint32_t EN : 1; /*!< [6..6] desc EN */ + } CR_f; + } ; + + union { + __IOM uint32_t DR; /*!< (@ 0x0000000C) Data register */ + + struct { + __IOM uint32_t DR : 8; /*!< [7..0] desc DR */ + } DR_f; + } ; + + union { + __IOM uint32_t ADDR0; /*!< (@ 0x00000010) Slave Addrress0 */ + + struct { + __IOM uint32_t GC : 1; /*!< [0..0] desc GC */ + __IOM uint32_t ADDR0 : 7; /*!< [7..1] desc ADDR0 */ + } ADDR0_f; + } ; + + union { + __IM uint32_t STAT; /*!< (@ 0x00000014) Status register */ + + struct { + __IM uint32_t STAT : 8; /*!< [7..0] desc STAT */ + } STAT_f; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t ADDR1; /*!< (@ 0x00000020) Slave Addrress1 */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t ADDR1 : 7; /*!< [7..1] desc ADDR1 */ + } ADDR1_f; + } ; + + union { + __IOM uint32_t ADDR2; /*!< (@ 0x00000024) Slave Addrress2 */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t ADDR2 : 7; /*!< [7..1] desc ADDR2 */ + } ADDR2_f; + } ; + + union { + __IM uint32_t MATCH; /*!< (@ 0x00000028) Slave Addrress match flag */ + + struct { + __IM uint32_t ADDR0 : 1; /*!< [0..0] desc ADDR0 */ + __IM uint32_t ADDR1 : 1; /*!< [1..1] desc ADDR1 */ + __IM uint32_t ADDR2 : 1; /*!< [2..2] desc ADDR2 */ + } MATCH_f; + } ; +} I2C_TypeDef; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ IWDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc IWDT (IWDT) + */ + +typedef struct { /*!< (@ 0x40003000) IWDT Structure */ + + union { + __OM uint32_t KR; /*!< (@ 0x00000000) Key register */ + + struct { + __OM uint32_t KR : 16; /*!< [15..0] desc KR */ + } KR_f; + } ; + + union { + __IOM uint32_t CR; /*!< (@ 0x00000004) Control register */ + + struct { + __IOM uint32_t PRS : 3; /*!< [2..0] desc PRS */ + __IOM uint32_t ACTION : 1; /*!< [3..3] desc ACTION */ + __IOM uint32_t IE : 1; /*!< [4..4] desc IE */ + __IOM uint32_t PAUSE : 1; /*!< [5..5] desc PAUSE */ + } CR_f; + } ; + + union { + __IOM uint32_t ARR; /*!< (@ 0x00000008) Auto reload register */ + + struct { + __IOM uint32_t ARR : 12; /*!< [11..0] desc ARR */ + } ARR_f; + } ; + + union { + __IOM uint32_t SR; /*!< (@ 0x0000000C) Status register */ + + struct { + __IM uint32_t CRF : 1; /*!< [0..0] desc CRF */ + __IM uint32_t ARRF : 1; /*!< [1..1] desc ARRF */ + __IM uint32_t WINRF : 1; /*!< [2..2] desc WINRF */ + __IOM uint32_t OV : 1; /*!< [3..3] desc OV */ + __IM uint32_t RUN : 1; /*!< [4..4] desc RUN */ + __IM uint32_t RELOAD : 1; /*!< [5..5] desc RELOAD */ + } SR_f; + } ; + + union { + __IOM uint32_t WINR; /*!< (@ 0x00000010) Window register */ + + struct { + __IOM uint32_t WINR : 12; /*!< [11..0] desc WINR */ + } WINR_f; + } ; + __IM uint32_t RESERVED[4]; + + union { + __IM uint32_t CNT; /*!< (@ 0x00000024) counter */ + + struct { + __IM uint32_t CNT : 12; /*!< [11..0] desc CNT */ + } CNT_f; + } ; +} IWDT_TypeDef; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ LVD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc LVD (LVD) + */ + +typedef struct { /*!< (@ 0x40012A80) LVD Structure */ + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control register0 */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t ACTION : 1; /*!< [1..1] desc ACTION */ + __IOM uint32_t SOURCE : 2; /*!< [3..2] desc SOURCE */ + __IOM uint32_t VTH : 4; /*!< [7..4] desc VTH */ + __IM uint32_t : 1; + __IOM uint32_t IE : 1; /*!< [9..9] desc IE */ + } CR0_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000004) Control register1 */ + + struct { + __IOM uint32_t FLTEN : 1; /*!< [0..0] desc FLTEN */ + __IOM uint32_t FLTTIME : 3; /*!< [3..1] desc FLTTIME */ + __IOM uint32_t FLTCLK : 1; /*!< [4..4] desc FLTCLK */ + __IOM uint32_t RISE : 1; /*!< [5..5] desc RISE */ + __IOM uint32_t FALL : 1; /*!< [6..6] desc FALL */ + __IOM uint32_t LEVEL : 1; /*!< [7..7] desc LEVEL */ + } CR1_f; + } ; + + union { + __IOM uint32_t SR; /*!< (@ 0x00000008) status register */ + + struct { + __IOM uint32_t INTF : 1; /*!< [0..0] desc INTF */ + __IM uint32_t FLTV : 1; /*!< [1..1] desc FLTV */ + } SR_f; + } ; +} LVD_TypeDef; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ RAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc RAM (RAM) + */ + +typedef struct { /*!< (@ 0x40022400) RAM Structure */ + + union { + __IOM uint32_t IER; /*!< (@ 0x00000000) Interrupt enable register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t PARITY : 1; /*!< [1..1] desc PARITY */ + } IER_f; + } ; + + union { + __IM uint32_t ADDR; /*!< (@ 0x00000004) Parity check error addr register */ + + struct { + __IM uint32_t ADDR : 32; /*!< [31..0] desc ADDR */ + } ADDR_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000008) Interrupt flag register */ + + struct { + __IM uint32_t PARITY : 1; /*!< [0..0] desc PARITY */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x0000000C) Interrupt flag clear register */ + + struct { + __IOM uint32_t PARITY : 1; /*!< [0..0] desc PARITY */ + } ICR_f; + } ; +} RAM_TypeDef; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc RTC (RTC) + */ + +typedef struct { /*!< (@ 0x40002800) RTC Structure */ + + union { + __OM uint32_t KEY; /*!< (@ 0x00000000) desc KEY */ + + struct { + __OM uint32_t KEY : 8; /*!< [7..0] Key = 0xCA - 0x53 */ + } KEY_f; + } ; + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000004) Control register0 */ + + struct { + __IOM uint32_t INTERVAL : 3; /*!< [2..0] desc INTERVAL */ + __IOM uint32_t H24 : 1; /*!< [3..3] desc H24 */ + __IM uint32_t : 1; + __IOM uint32_t RTC1HZ : 2; /*!< [6..5] desc RTC1HZ */ + __IOM uint32_t START : 1; /*!< [7..7] desc START */ + } CR0_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000008) Control register1 */ + + struct { + __IOM uint32_t ACCESS : 1; /*!< [0..0] desc ACCESS */ + __IM uint32_t WINDOW : 1; /*!< [1..1] desc WINDOW */ + __IM uint32_t : 6; + __IOM uint32_t SOURCE : 3; /*!< [10..8] desc SOURCE */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x0000000C) Control register2 */ + + struct { + __IOM uint32_t AWTSRC : 3; /*!< [2..0] desc AWTSRC */ + __IOM uint32_t TAMPEDGE : 1; /*!< [3..3] desc TAMPEDGE */ + __IOM uint32_t RTCOUT : 2; /*!< [5..4] desc RTCOUT */ + __IOM uint32_t TAMPEN : 1; /*!< [6..6] desc TAMPEN */ + __IOM uint32_t AWTEN : 1; /*!< [7..7] desc AWTEN */ + __IM uint32_t : 1; + __IOM uint32_t ALARMAEN : 1; /*!< [9..9] desc ALARMAEN */ + __IOM uint32_t ALARMBEN : 1; /*!< [10..10] desc ALARMBEN */ + } CR2_f; + } ; + + union { + __IOM uint32_t COMPEN; /*!< (@ 0x00000010) Compen register */ + + struct { + __IOM uint32_t COMP : 12; /*!< [11..0] desc COMP */ + __IOM uint32_t STEP : 2; /*!< [13..12] desc STEP */ + __IOM uint32_t SIGN : 1; /*!< [14..14] desc SIGN */ + __IOM uint32_t EN : 1; /*!< [15..15] desc EN */ + __IOM uint32_t FREQ : 4; /*!< [19..16] desc FREQ */ + } COMPEN_f; + } ; + + union { + __IOM uint32_t DATE; /*!< (@ 0x00000014) Time.Second register */ + + struct { + __IOM uint32_t DAY : 8; /*!< [7..0] desc DAY */ + __IOM uint32_t MONTH : 8; /*!< [15..8] desc MONTH */ + __IOM uint32_t YEAR : 8; /*!< [23..16] desc YEAR */ + __IOM uint32_t WEEK : 3; /*!< [26..24] desc WEEK */ + } DATE_f; + } ; + + union { + __IOM uint32_t TIME; /*!< (@ 0x00000018) Time.Second register */ + + struct { + __IOM uint32_t SECOND : 7; /*!< [6..0] desc SECOND */ + __IM uint32_t : 1; + __IOM uint32_t MINUTE : 7; /*!< [14..8] desc MINUTE */ + __IM uint32_t : 1; + __IOM uint32_t HOUR : 6; /*!< [21..16] desc HOUR */ + } TIME_f; + } ; + + union { + __IOM uint32_t ALARMA; /*!< (@ 0x0000001C) Alarm - A */ + + struct { + __IOM uint32_t SECOND : 7; /*!< [6..0] desc SECOND */ + __IOM uint32_t SECONDMASK : 1; /*!< [7..7] desc SECONDMASK */ + __IOM uint32_t MINUTE : 7; /*!< [14..8] desc MINUTE */ + __IOM uint32_t MINUTEMASK : 1; /*!< [15..15] desc MINUTEMASK */ + __IOM uint32_t HOUR : 6; /*!< [21..16] desc HOUR */ + __IM uint32_t : 1; + __IOM uint32_t HOURMASK : 1; /*!< [23..23] desc HOURMASK */ + __IOM uint32_t WEEK : 7; /*!< [30..24] desc WEEK */ + } ALARMA_f; + } ; + + union { + __IOM uint32_t ALARMB; /*!< (@ 0x00000020) Alarm - B */ + + struct { + __IOM uint32_t SECOND : 7; /*!< [6..0] desc SECOND */ + __IOM uint32_t SECONDMASK : 1; /*!< [7..7] desc SECONDMASK */ + __IOM uint32_t MINUTE : 7; /*!< [14..8] desc MINUTE */ + __IOM uint32_t MINUTEMASK : 1; /*!< [15..15] desc MINUTEMASK */ + __IOM uint32_t HOUR : 6; /*!< [21..16] desc HOUR */ + __IM uint32_t : 1; + __IOM uint32_t HOURMASK : 1; /*!< [23..23] desc HOURMASK */ + __IOM uint32_t WEEK : 7; /*!< [30..24] desc WEEK */ + } ALARMB_f; + } ; + + union { + __IOM uint32_t TAMPDATE; /*!< (@ 0x00000024) desc TAMPDATE */ + + struct { + __IOM uint32_t DAY : 6; /*!< [5..0] desc DAY */ + __IM uint32_t : 2; + __IOM uint32_t MONTH : 5; /*!< [12..8] desc MONTH */ + __IOM uint32_t WEEK : 3; /*!< [15..13] desc WEEK */ + } TAMPDATE_f; + } ; + + union { + __IOM uint32_t TAMPTIME; /*!< (@ 0x00000028) desc TAMPTIME */ + + struct { + __IOM uint32_t SECOND : 7; /*!< [6..0] desc SECOND */ + __IM uint32_t : 1; + __IOM uint32_t MINUTE : 7; /*!< [14..8] desc MINUTE */ + __IM uint32_t : 1; + __IOM uint32_t HOUR : 6; /*!< [21..16] desc HOUR */ + } TAMPTIME_f; + } ; + + union { + __IOM uint32_t AWTARR; /*!< (@ 0x0000002C) Auto Wakeup Timer Auto Reload Register */ + + struct { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } AWTARR_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000030) Interrupt enable register */ + + struct { + __IOM uint32_t ALARMA : 1; /*!< [0..0] desc ALARMA */ + __IOM uint32_t ALARMB : 1; /*!< [1..1] desc ALARMB */ + __IOM uint32_t AWTIMER : 1; /*!< [2..2] desc AWTIMER */ + __IOM uint32_t TAMP : 1; /*!< [3..3] desc TAMP */ + __IOM uint32_t TAMPOV : 1; /*!< [4..4] desc TAMPOV */ + __IM uint32_t : 1; + __IOM uint32_t INTERVAL : 1; /*!< [6..6] desc INTERVAL */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000034) Interrupt status register */ + + struct { + __IM uint32_t ALARMA : 1; /*!< [0..0] desc ALARMA */ + __IM uint32_t ALARMB : 1; /*!< [1..1] desc ALARMB */ + __IM uint32_t AWTIMER : 1; /*!< [2..2] desc AWTIMER */ + __IM uint32_t TAMP : 1; /*!< [3..3] desc TAMP */ + __IM uint32_t TAMPOV : 1; /*!< [4..4] desc TAMPOV */ + __IM uint32_t : 1; + __IM uint32_t INTERVAL : 1; /*!< [6..6] desc INTERVAL */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000038) Interrupt flag clear register */ + + struct { + __IOM uint32_t ALARMA : 1; /*!< [0..0] desc ALARMA */ + __IOM uint32_t ALARMB : 1; /*!< [1..1] desc ALARMB */ + __IOM uint32_t AWTIMER : 1; /*!< [2..2] desc AWTIMER */ + __IOM uint32_t TAMP : 1; /*!< [3..3] desc TAMP */ + __IOM uint32_t TAMPOV : 1; /*!< [4..4] desc TAMPOV */ + __IM uint32_t : 1; + __IOM uint32_t INTERVAL : 1; /*!< [6..6] desc INTERVAL */ + } ICR_f; + } ; +} RTC_TypeDef; /*!< Size = 60 (0x3c) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc SPI1 (SPI1) + */ + +typedef struct { /*!< (@ 0x40013000) SPI1 Structure */ + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t CPHA : 1; /*!< [0..0] desc CPHA */ + __IOM uint32_t CPOL : 1; /*!< [1..1] desc CPOL */ + __IOM uint32_t MSTR : 1; /*!< [2..2] desc MSTR */ + __IOM uint32_t BR : 3; /*!< [5..3] desc BR */ + __IOM uint32_t EN : 1; /*!< [6..6] desc EN */ + __IOM uint32_t LSBF : 1; /*!< [7..7] desc LSBF */ + __IOM uint32_t SMP : 1; /*!< [8..8] desc SMP */ + __IOM uint32_t SSM : 1; /*!< [9..9] desc SSM */ + __IOM uint32_t WIDTH : 4; /*!< [13..10] desc WIDTH */ + __IOM uint32_t MODE : 2; /*!< [15..14] desc MODE */ + __IOM uint32_t DMARX : 1; /*!< [16..16] desc DMARX */ + __IOM uint32_t DMATX : 1; /*!< [17..17] desc DMATX */ + __IOM uint32_t MISOHD : 1; /*!< [18..18] desc MISOHD */ + } CR1_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000004) Interrupt enable register */ + + struct { + __IOM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IOM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IOM uint32_t SSF : 1; /*!< [2..2] desc SSF */ + __IOM uint32_t SSR : 1; /*!< [3..3] desc SSR */ + __IOM uint32_t UD : 1; /*!< [4..4] desc UD */ + __IOM uint32_t OV : 1; /*!< [5..5] desc OV */ + __IOM uint32_t SSERR : 1; /*!< [6..6] desc SSERR */ + __IOM uint32_t MODF : 1; /*!< [7..7] desc MODF */ + } IER_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000008) Control register2 */ + + struct { + __IOM uint32_t HDOE : 1; /*!< [0..0] desc HDOE */ + } CR2_f; + } ; + + union { + __IOM uint32_t SSI; /*!< (@ 0x0000000C) Slave slect register */ + + struct { + __IOM uint32_t SSI : 1; /*!< [0..0] desc SSI */ + } SSI_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000010) Interrupt status register */ + + struct { + __IM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IM uint32_t SSF : 1; /*!< [2..2] desc SSF */ + __IM uint32_t SSR : 1; /*!< [3..3] desc SSR */ + __IM uint32_t UD : 1; /*!< [4..4] desc UD */ + __IM uint32_t OV : 1; /*!< [5..5] desc OV */ + __IM uint32_t SSERR : 1; /*!< [6..6] desc SSERR */ + __IM uint32_t MODF : 1; /*!< [7..7] desc MODF */ + __IM uint32_t BUSY : 1; /*!< [8..8] desc BUSY */ + __IM uint32_t SSLVL : 1; /*!< [9..9] desc SSLVL */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000014) Interrupt flag clear register */ + + struct { + __IOM uint32_t FLUSH : 1; /*!< [0..0] desc FLUSH */ + __IOM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IOM uint32_t SSF : 1; /*!< [2..2] desc SSF */ + __IOM uint32_t SSR : 1; /*!< [3..3] desc SSR */ + __IOM uint32_t UD : 1; /*!< [4..4] desc UD */ + __IOM uint32_t OV : 1; /*!< [5..5] desc OV */ + __IOM uint32_t SSERR : 1; /*!< [6..6] desc SSERR */ + __IOM uint32_t MODF : 1; /*!< [7..7] desc MODF */ + } ICR_f; + } ; + + union { + __IOM uint32_t DR; /*!< (@ 0x00000018) Data register */ + + struct { + __IOM uint32_t DR : 16; /*!< [15..0] desc DR */ + } DR_f; + } ; +} SPI_TypeDef; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Ctrl (SYSCTRL) + */ + +typedef struct { /*!< (@ 0x40010000) SYSCTRL Structure */ + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control Reg0 */ + + struct { + __IOM uint32_t SYSCLK : 3; /*!< [2..0] desc SYSCLK */ + __IOM uint32_t PCLKPRS : 2; /*!< [4..3] desc PCLKPRS */ + __IOM uint32_t HCLKPRS : 3; /*!< [7..5] desc HCLKPRS */ + __IM uint32_t : 8; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR0_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000004) Control Reg1 */ + + struct { + __IOM uint32_t HSIEN : 1; /*!< [0..0] desc HSIEN */ + __IOM uint32_t HSEEN : 1; /*!< [1..1] desc HSEEN */ + __IOM uint32_t PLLEN : 1; /*!< [2..2] desc PLLEN */ + __IOM uint32_t LSIEN : 1; /*!< [3..3] desc LSIEN */ + __IOM uint32_t LSEEN : 1; /*!< [4..4] desc LSEEN */ + __IOM uint32_t LSELOCK : 1; /*!< [5..5] desc LSELOCK */ + __IOM uint32_t LSECCS : 1; /*!< [6..6] desc LSECCS */ + __IOM uint32_t HSECCS : 1; /*!< [7..7] desc HSECCS */ + __IOM uint32_t CLKCCS : 1; /*!< [8..8] desc CLKCCS */ + __IM uint32_t : 7; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000008) Control Reg2 */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t SWDIO : 1; /*!< [1..1] desc SWDIO */ + __IOM uint32_t LOCKUP : 1; /*!< [2..2] desc LOCKUP */ + __IOM uint32_t WAKEUPCLK : 1; /*!< [3..3] desc WAKEUPCLK */ + __IM uint32_t : 12; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR2_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x0000000C) Interupt Enable Reg */ + + struct { + __IOM uint32_t HSIRDY : 1; /*!< [0..0] desc HSIRDY */ + __IOM uint32_t HSERDY : 1; /*!< [1..1] desc HSERDY */ + __IOM uint32_t PLLRDY : 1; /*!< [2..2] desc PLLRDY */ + __IOM uint32_t LSIRDY : 1; /*!< [3..3] desc LSIRDY */ + __IOM uint32_t LSERDY : 1; /*!< [4..4] desc LSERDY */ + __IOM uint32_t LSEFAIL : 1; /*!< [5..5] desc LSEFAIL */ + __IOM uint32_t HSEFAIL : 1; /*!< [6..6] desc HSEFAIL */ + __IOM uint32_t LSEFAULT : 1; /*!< [7..7] desc LSEFAULT */ + __IOM uint32_t HSEFAULT : 1; /*!< [8..8] desc HSEFAULT */ + __IM uint32_t : 7; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000010) Interupt Status Reg */ + + struct { + __IM uint32_t HSIRDY : 1; /*!< [0..0] desc HSIRDY */ + __IM uint32_t HSERDY : 1; /*!< [1..1] desc HSERDY */ + __IM uint32_t PLLRDY : 1; /*!< [2..2] desc PLLRDY */ + __IM uint32_t LSIRDY : 1; /*!< [3..3] desc LSIRDY */ + __IM uint32_t LSERDY : 1; /*!< [4..4] desc LSERDY */ + __IM uint32_t LSEFAIL : 1; /*!< [5..5] desc LSEFAIL */ + __IM uint32_t HSEFAIL : 1; /*!< [6..6] desc HSEFAIL */ + __IM uint32_t LSEFAULT : 1; /*!< [7..7] desc LSEFAULT */ + __IM uint32_t HSEFAULT : 1; /*!< [8..8] desc HSEFAULT */ + __IM uint32_t : 2; + __IM uint32_t HSISTABLE : 1; /*!< [11..11] desc HSISTABLE */ + __IM uint32_t HSESTABLE : 1; /*!< [12..12] desc HSESTABLE */ + __IM uint32_t PLLSTABLE : 1; /*!< [13..13] desc PLLSTABLE */ + __IM uint32_t LSISTABLE : 1; /*!< [14..14] desc LSISTABLE */ + __IM uint32_t LSESTABLE : 1; /*!< [15..15] desc LSESTABLE */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000014) Interupt Clear Reg */ + + struct { + __IOM uint32_t HSIRDY : 1; /*!< [0..0] desc HSIRDY */ + __IOM uint32_t HSERDY : 1; /*!< [1..1] desc HSERDY */ + __IOM uint32_t PLLRDY : 1; /*!< [2..2] desc PLLRDY */ + __IOM uint32_t LSIRDY : 1; /*!< [3..3] desc LSIRDY */ + __IOM uint32_t LSERDY : 1; /*!< [4..4] desc LSERDY */ + __IOM uint32_t LSEFAIL : 1; /*!< [5..5] desc LSEFAIL */ + __IOM uint32_t HSEFAIL : 1; /*!< [6..6] desc HSEFAIL */ + __IOM uint32_t LSEFAULT : 1; /*!< [7..7] desc LSEFAULT */ + __IOM uint32_t HSEFAULT : 1; /*!< [8..8] desc HSEFAULT */ + } ICR_f; + } ; + + union { + __IOM uint32_t HSI; /*!< (@ 0x00000018) HSI Control Reg */ + + struct { + __IOM uint32_t TRIM : 11; /*!< [10..0] desc TRIM */ + __IOM uint32_t DIV : 4; /*!< [14..11] desc DIV */ + __IM uint32_t STABLE : 1; /*!< [15..15] desc STABLE */ + } HSI_f; + } ; + + union { + __IOM uint32_t HSE; /*!< (@ 0x0000001C) HSE Control Reg */ + + struct { + __IOM uint32_t DRIVER : 2; /*!< [1..0] desc DRIVER */ + __IOM uint32_t FREQ : 2; /*!< [3..2] desc FREQ */ + __IOM uint32_t WAITCYCLE : 2; /*!< [5..4] desc WAITCYCLE */ + __IOM uint32_t MODE : 1; /*!< [6..6] desc MODE */ + __IOM uint32_t FLT : 1; /*!< [7..7] desc FLT */ + __IOM uint32_t DETCNT : 11; /*!< [18..8] desc DETCNT */ + __IM uint32_t STABLE : 1; /*!< [19..19] desc STABLE */ + } HSE_f; + } ; + + union { + __IOM uint32_t LSI; /*!< (@ 0x00000020) LSI Control Reg */ + + struct { + __IOM uint32_t TRIM : 10; /*!< [9..0] desc TRIM */ + __IOM uint32_t WAITCYCLE : 2; /*!< [11..10] desc WAITCYCLE */ + __IM uint32_t : 3; + __IM uint32_t STABLE : 1; /*!< [15..15] desc STABLE */ + } LSI_f; + } ; + + union { + __IOM uint32_t LSE; /*!< (@ 0x00000024) LSE Control Reg */ + + struct { + __IOM uint32_t DRIVER : 2; /*!< [1..0] desc DRIVER */ + __IOM uint32_t AMP : 2; /*!< [3..2] desc AMP */ + __IOM uint32_t WAITCYCLE : 2; /*!< [5..4] desc WAITCYCLE */ + __IOM uint32_t MODE : 1; /*!< [6..6] desc MODE */ + __IM uint32_t : 8; + __IM uint32_t STABLE : 1; /*!< [15..15] desc STABLE */ + } LSE_f; + } ; + + union { + __IOM uint32_t PLL; /*!< (@ 0x00000028) PLL Control Reg */ + + struct { + __IOM uint32_t SOURCE : 2; /*!< [1..0] desc SOURCE */ + __IOM uint32_t FREQIN : 2; /*!< [3..2] desc FREQIN */ + __IOM uint32_t MUL : 5; /*!< [8..4] desc MUL */ + __IOM uint32_t FREQOUT : 3; /*!< [11..9] desc FREQOUT */ + __IOM uint32_t WAITCYCLE : 3; /*!< [14..12] desc WAITCYCLE */ + __IM uint32_t STABLE : 1; /*!< [15..15] desc STABLE */ + __IOM uint32_t RFU : 4; /*!< [19..16] desc RFU */ + } PLL_f; + } ; + + union { + __IOM uint32_t DEBUG; /*!< (@ 0x0000002C) Debug Control Reg */ + + struct { + __IOM uint32_t ATIM : 1; /*!< [0..0] desc ATIM */ + __IOM uint32_t GTIM1 : 1; /*!< [1..1] desc GTIM1 */ + __IOM uint32_t GTIM2 : 1; /*!< [2..2] desc GTIM2 */ + __IOM uint32_t GTIM3 : 1; /*!< [3..3] desc GTIM3 */ + __IOM uint32_t GTIM4 : 1; /*!< [4..4] desc GTIM4 */ + __IOM uint32_t BTIM123 : 1; /*!< [5..5] desc BTIM123 */ + __IOM uint32_t AWT : 1; /*!< [6..6] desc AWT */ + __IM uint32_t : 1; + __IOM uint32_t RTC : 1; /*!< [8..8] desc RTC */ + __IOM uint32_t IWDT : 1; /*!< [9..9] desc IWDT */ + __IOM uint32_t WWDT : 1; /*!< [10..10] desc WWDT */ + } DEBUG_f; + } ; + + union { + __IOM uint32_t AHBEN; /*!< (@ 0x00000030) AHB Clock Control Reg */ + + struct { + __IOM uint32_t DMA : 1; /*!< [0..0] desc DMA */ + __IOM uint32_t FLASH : 1; /*!< [1..1] desc FLASH */ + __IOM uint32_t CRC : 1; /*!< [2..2] desc CRC */ + __IM uint32_t : 1; + __IOM uint32_t GPIOA : 1; /*!< [4..4] desc GPIOA */ + __IOM uint32_t GPIOB : 1; /*!< [5..5] desc GPIOB */ + __IOM uint32_t GPIOC : 1; /*!< [6..6] desc GPIOC */ + __IM uint32_t : 2; + __IOM uint32_t GPIOF : 1; /*!< [9..9] desc GPIOF */ + } AHBEN_f; + } ; + + union { + __IOM uint32_t APBEN2; /*!< (@ 0x00000034) APB Clock Control Reg2 */ + + struct { + __IM uint32_t : 2; + __IOM uint32_t ADC : 1; /*!< [2..2] desc ADC */ + __IM uint32_t : 1; + __IOM uint32_t VC : 1; /*!< [4..4] desc VC */ + __IM uint32_t : 2; + __IOM uint32_t ATIM : 1; /*!< [7..7] desc ATIM */ + __IOM uint32_t SPI1 : 1; /*!< [8..8] desc SPI1 */ + __IOM uint32_t UART1 : 1; /*!< [9..9] desc UART1 */ + __IOM uint32_t GTIM3 : 1; /*!< [10..10] desc GTIM3 */ + __IOM uint32_t GTIM4 : 1; /*!< [11..11] desc GTIM4 */ + __IOM uint32_t BTIM : 1; /*!< [12..12] desc BTIM */ + __IOM uint32_t AWT : 1; /*!< [13..13] desc AWT */ + } APBEN2_f; + } ; + + union { + __IOM uint32_t APBEN1; /*!< (@ 0x00000038) APB Clock Control Reg1 */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t GTIM1 : 1; /*!< [1..1] desc GTIM1 */ + __IOM uint32_t GTIM2 : 1; /*!< [2..2] desc GTIM2 */ + __IOM uint32_t RTC : 1; /*!< [3..3] desc RTC */ + __IOM uint32_t WWDT : 1; /*!< [4..4] desc WWDT */ + __IOM uint32_t IWDT : 1; /*!< [5..5] desc IWDT */ + __IOM uint32_t SPI2 : 1; /*!< [6..6] desc SPI2 */ + __IOM uint32_t UART2 : 1; /*!< [7..7] desc UART2 */ + __IOM uint32_t UART3 : 1; /*!< [8..8] desc UART3 */ + __IM uint32_t : 2; + __IOM uint32_t I2C1 : 1; /*!< [11..11] desc I2C1 */ + __IOM uint32_t I2C2 : 1; /*!< [12..12] desc I2C2 */ + } APBEN1_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t AHBRST; /*!< (@ 0x00000040) AHB Reset Control Reg */ + + struct { + __IOM uint32_t DMA : 1; /*!< [0..0] desc DMA */ + __IOM uint32_t FLASH : 1; /*!< [1..1] desc FLASH */ + __IOM uint32_t CRC : 1; /*!< [2..2] desc CRC */ + __IM uint32_t : 1; + __IOM uint32_t GPIOA : 1; /*!< [4..4] desc GPIOA */ + __IOM uint32_t GPIOB : 1; /*!< [5..5] desc GPIOB */ + __IOM uint32_t GPIOC : 1; /*!< [6..6] desc GPIOC */ + __IM uint32_t : 2; + __IOM uint32_t GPIOF : 1; /*!< [9..9] desc GPIOF */ + } AHBRST_f; + } ; + + union { + __IOM uint32_t APBRST2; /*!< (@ 0x00000044) APB Reset Control Reg2 */ + + struct { + __IM uint32_t : 2; + __IOM uint32_t ADC : 1; /*!< [2..2] desc ADC */ + __IM uint32_t : 1; + __IOM uint32_t VC : 1; /*!< [4..4] desc VC */ + __IM uint32_t : 2; + __IOM uint32_t ATIM : 1; /*!< [7..7] desc ATIM */ + __IOM uint32_t SPI1 : 1; /*!< [8..8] desc SPI1 */ + __IOM uint32_t UART1 : 1; /*!< [9..9] desc UART1 */ + __IOM uint32_t GTIM3 : 1; /*!< [10..10] desc GTIM3 */ + __IOM uint32_t GTIM4 : 1; /*!< [11..11] desc GTIM4 */ + __IOM uint32_t BTIM : 1; /*!< [12..12] desc BTIM */ + __IOM uint32_t AWT : 1; /*!< [13..13] desc AWT */ + } APBRST2_f; + } ; + + union { + __IOM uint32_t APBRST1; /*!< (@ 0x00000048) APB Reset Control Reg1 */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t GTIM1 : 1; /*!< [1..1] desc GTIM1 */ + __IOM uint32_t GTIM2 : 1; /*!< [2..2] desc GTIM2 */ + __IOM uint32_t RTC : 1; /*!< [3..3] desc RTC */ + __IOM uint32_t WWDT : 1; /*!< [4..4] desc WWDT */ + __IOM uint32_t IWDT : 1; /*!< [5..5] desc IWDT */ + __IOM uint32_t SPI2 : 1; /*!< [6..6] desc SPI2 */ + __IOM uint32_t UART2 : 1; /*!< [7..7] desc UART2 */ + __IOM uint32_t UART3 : 1; /*!< [8..8] desc UART3 */ + __IM uint32_t : 2; + __IOM uint32_t I2C1 : 1; /*!< [11..11] desc I2C1 */ + __IOM uint32_t I2C2 : 1; /*!< [12..12] desc I2C2 */ + } APBRST1_f; + } ; + + union { + __IOM uint32_t RESETFLAG; /*!< (@ 0x0000004C) Reset Status Reg */ + + struct { + __IOM uint32_t POR : 1; /*!< [0..0] desc POR */ + __IM uint32_t : 2; + __IOM uint32_t LVD : 1; /*!< [3..3] desc LVD */ + __IOM uint32_t IWDT : 1; /*!< [4..4] desc IWDT */ + __IOM uint32_t WWDT : 1; /*!< [5..5] desc WWDT */ + __IOM uint32_t RSTB : 1; /*!< [6..6] desc RSTB */ + __IM uint32_t : 1; + __IOM uint32_t LOCKUP : 1; /*!< [8..8] desc LOCKUP */ + __IOM uint32_t SYSRESETREQ : 1; /*!< [9..9] desc SYSRESETREQ */ + } RESETFLAG_f; + } ; + + union { + __IOM uint32_t GTIM1CAP; /*!< (@ 0x00000050) GTIM1 CAP Control Reg */ + + struct { + __IOM uint32_t CH1 : 3; /*!< [2..0] desc CH1 */ + __IM uint32_t : 1; + __IOM uint32_t CH2 : 3; /*!< [6..4] desc CH2 */ + __IM uint32_t : 1; + __IOM uint32_t CH3 : 3; /*!< [10..8] desc CH3 */ + __IM uint32_t : 1; + __IOM uint32_t CH4 : 3; /*!< [14..12] desc CH4 */ + } GTIM1CAP_f; + } ; + + union { + __IOM uint32_t GTIM2CAP; /*!< (@ 0x00000054) GTIM2 CAP Control Reg */ + + struct { + __IOM uint32_t CH1 : 3; /*!< [2..0] desc CH1 */ + __IM uint32_t : 1; + __IOM uint32_t CH2 : 3; /*!< [6..4] desc CH2 */ + __IM uint32_t : 1; + __IOM uint32_t CH3 : 3; /*!< [10..8] desc CH3 */ + __IM uint32_t : 1; + __IOM uint32_t CH4 : 3; /*!< [14..12] desc CH4 */ + } GTIM2CAP_f; + } ; + + union { + __IOM uint32_t GTIM3CAP; /*!< (@ 0x00000058) GTIM3 CAP Control Reg */ + + struct { + __IOM uint32_t CH1 : 3; /*!< [2..0] desc CH1 */ + __IM uint32_t : 1; + __IOM uint32_t CH2 : 3; /*!< [6..4] desc CH2 */ + __IM uint32_t : 1; + __IOM uint32_t CH3 : 3; /*!< [10..8] desc CH3 */ + __IM uint32_t : 1; + __IOM uint32_t CH4 : 3; /*!< [14..12] desc CH4 */ + } GTIM3CAP_f; + } ; + + union { + __IOM uint32_t GTIM4CAP; /*!< (@ 0x0000005C) GTIM4 CAP Control Reg */ + + struct { + __IOM uint32_t CH1 : 3; /*!< [2..0] desc CH1 */ + __IM uint32_t : 1; + __IOM uint32_t CH2 : 3; /*!< [6..4] desc CH2 */ + __IM uint32_t : 1; + __IOM uint32_t CH3 : 3; /*!< [10..8] desc CH3 */ + __IM uint32_t : 1; + __IOM uint32_t CH4 : 3; /*!< [14..12] desc CH4 */ + } GTIM4CAP_f; + } ; + + union { + __IOM uint32_t ATIMETR; /*!< (@ 0x00000060) ATIM ETR Control Reg */ + + struct { + __IOM uint32_t ATIMETR : 3; /*!< [2..0] desc ATIMETR */ + } ATIMETR_f; + } ; + + union { + __IOM uint32_t GTIMETR; /*!< (@ 0x00000064) GTIM1-4 ETR Control Reg */ + + struct { + __IOM uint32_t GTIM1ETR : 3; /*!< [2..0] desc GTIM1ETR */ + __IM uint32_t : 1; + __IOM uint32_t GTIM2ETR : 3; /*!< [6..4] desc GTIM2ETR */ + __IM uint32_t : 1; + __IOM uint32_t GTIM3ETR : 3; /*!< [10..8] desc GTIM3ETR */ + __IM uint32_t : 1; + __IOM uint32_t GTIM4ETR : 3; /*!< [14..12] desc GTIM4ETR */ + } GTIMETR_f; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t TIMITR; /*!< (@ 0x0000006C) BTIMx GTIMx ATIM ITR Control Reg */ + + struct { + __IOM uint32_t ATIMITR : 3; /*!< [2..0] desc ATIMITR */ + __IOM uint32_t GTIM1ITR : 3; /*!< [5..3] desc GTIM1ITR */ + __IOM uint32_t GTIM2ITR : 3; /*!< [8..6] desc GTIM2ITR */ + __IOM uint32_t GTIM3ITR : 3; /*!< [11..9] desc GTIM3ITR */ + __IOM uint32_t GTIM4ITR : 3; /*!< [14..12] desc GTIM4ITR */ + __IOM uint32_t BTIM1ITR : 3; /*!< [17..15] desc BTIM1ITR */ + __IOM uint32_t BTIM2ITR : 3; /*!< [20..18] desc BTIM2ITR */ + __IOM uint32_t BTIM3ITR : 3; /*!< [23..21] desc BTIM3ITR */ + } TIMITR_f; + } ; + + union { + __IOM uint32_t MCO; /*!< (@ 0x00000070) Master Clock Output Control Reg */ + + struct { + __IOM uint32_t SOURCE : 4; /*!< [3..0] desc SOURCE */ + __IOM uint32_t DIV : 3; /*!< [6..4] desc DIV */ + } MCO_f; + } ; + + union { + __IOM uint32_t IRMOD; /*!< (@ 0x00000074) IR MOD Control Reg */ + + struct { + __IOM uint32_t MOD : 4; /*!< [3..0] desc MOD */ + } IRMOD_f; + } ; +} SYSCTRL_TypeDef; /*!< Size = 120 (0x78) */ + + + +/* =========================================================================================================================== */ +/* ================ UART1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc UART1 (UART1) + */ + +typedef struct { /*!< (@ 0x40013800) UART1 Structure */ + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t TXEN : 1; /*!< [0..0] desc TXEN */ + __IOM uint32_t RXEN : 1; /*!< [1..1] desc RXEN */ + __IOM uint32_t PARITY : 2; /*!< [3..2] desc PARITY */ + __IOM uint32_t STOP : 2; /*!< [5..4] desc STOP */ + __IOM uint32_t SYNC : 1; /*!< [6..6] desc SYNC */ + __IM uint32_t : 1; + __IOM uint32_t START : 1; /*!< [8..8] desc START */ + __IOM uint32_t OVER : 2; /*!< [10..9] desc OVER */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000004) Control register2 */ + + struct { + __IOM uint32_t ADDREN : 1; /*!< [0..0] desc ADDREN */ + __IOM uint32_t SIGNAL : 1; /*!< [1..1] desc SIGNAL */ + __IOM uint32_t CTSEN : 1; /*!< [2..2] desc CTSEN */ + __IOM uint32_t RTSEN : 1; /*!< [3..3] desc RTSEN */ + __IOM uint32_t RXINV : 1; /*!< [4..4] desc RXINV */ + __IOM uint32_t TXINV : 1; /*!< [5..5] desc TXINV */ + __IOM uint32_t DMARX : 1; /*!< [6..6] desc DMARX */ + __IOM uint32_t DMATX : 1; /*!< [7..7] desc DMATX */ + __IOM uint32_t SOURCE : 2; /*!< [9..8] desc SOURCE */ + } CR2_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000008) Interrupt enable register */ + + struct { + __IOM uint32_t TXE : 1; /*!< [0..0] TxBuf empty */ + __IOM uint32_t TC : 1; /*!< [1..1] Transmit complete */ + __IOM uint32_t RC : 1; /*!< [2..2] Receive complete */ + __IOM uint32_t FE : 1; /*!< [3..3] Frame error */ + __IOM uint32_t PE : 1; /*!< [4..4] Parity error */ + __IM uint32_t : 1; + __IOM uint32_t CTS : 1; /*!< [6..6] CTS change */ + } IER_f; + } ; + + union { + __IOM uint32_t BRRI; /*!< (@ 0x0000000C) desc BRRI */ + + struct { + __IOM uint32_t BRRI : 16; /*!< [15..0] desc BRRI */ + } BRRI_f; + } ; + + union { + __IOM uint32_t BRRF; /*!< (@ 0x00000010) desc BRRF */ + + struct { + __IOM uint32_t BRRF : 4; /*!< [3..0] desc BRRF */ + } BRRF_f; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IM uint32_t ISR; /*!< (@ 0x0000001C) Interrupt status register */ + + struct { + __IM uint32_t TXE : 1; /*!< [0..0] TxBuf empty */ + __IM uint32_t TC : 1; /*!< [1..1] Transmit complete */ + __IM uint32_t RC : 1; /*!< [2..2] Receive complete */ + __IM uint32_t FE : 1; /*!< [3..3] Frame error */ + __IM uint32_t PE : 1; /*!< [4..4] Parity error */ + __IM uint32_t MATCH : 1; /*!< [5..5] Slave addr match */ + __IM uint32_t CTS : 1; /*!< [6..6] CTS change */ + __IM uint32_t CTSLV : 1; /*!< [7..7] CTS PIN level */ + __IM uint32_t TXBUSY : 1; /*!< [8..8] desc TXBUSY */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000020) Interrupt flag clear register */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t TC : 1; /*!< [1..1] Transmit complete */ + __IOM uint32_t RC : 1; /*!< [2..2] Receive complete */ + __IOM uint32_t FE : 1; /*!< [3..3] Frame error */ + __IOM uint32_t PE : 1; /*!< [4..4] Parity error */ + __IM uint32_t : 1; + __IOM uint32_t CTS : 1; /*!< [6..6] CTS change */ + } ICR_f; + } ; + + union { + __IM uint32_t RDR; /*!< (@ 0x00000024) Data reg for read */ + + struct { + __IM uint32_t RDR : 9; /*!< [8..0] desc RDR */ + } RDR_f; + } ; + + union { + __OM uint32_t TDR; /*!< (@ 0x00000028) Data reg for write */ + + struct { + __OM uint32_t TDR : 9; /*!< [8..0] desc TDR */ + } TDR_f; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t ADDR; /*!< (@ 0x00000030) Slave addr */ + + struct { + __IOM uint32_t ADDR : 8; /*!< [7..0] desc ADDR */ + } ADDR_f; + } ; + + union { + __IOM uint32_t MASK; /*!< (@ 0x00000034) Slave addr mask */ + + struct { + __IOM uint32_t MASK : 8; /*!< [7..0] desc MASK */ + } MASK_f; + } ; +} UART_TypeDef; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ VC1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc VC1 (VC1) + */ + +typedef struct { /*!< (@ 0x40012A00) VC1 Structure */ + + union { + __IOM uint32_t DIV; /*!< (@ 0x00000000) desc DIV */ + + struct { + __IOM uint32_t DIV : 6; /*!< [5..0] desc DIV */ + __IOM uint32_t EN : 1; /*!< [6..6] desc EN */ + __IOM uint32_t VIN : 1; /*!< [7..7] desc VIN */ + } DIV_f; + } ; + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000004) Control register0 */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t RESP : 2; /*!< [2..1] desc RESP */ + __IOM uint32_t HYS : 2; /*!< [4..3] desc HYS */ + __IOM uint32_t IE : 1; /*!< [5..5] desc IE */ + __IOM uint32_t POL : 1; /*!< [6..6] desc POL */ + __IOM uint32_t WINDOW : 1; /*!< [7..7] desc WINDOW */ + __IOM uint32_t INP : 4; /*!< [11..8] desc INP */ + __IOM uint32_t INN : 4; /*!< [15..12] desc INN */ + } CR0_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000008) Control register1 */ + + struct { + __IOM uint32_t FLTEN : 1; /*!< [0..0] desc FLTEN */ + __IOM uint32_t FLTTIME : 3; /*!< [3..1] desc FLTTIME */ + __IOM uint32_t FLTCLK : 1; /*!< [4..4] desc FLTCLK */ + __IOM uint32_t FALLIE : 1; /*!< [5..5] desc FALLIE */ + __IOM uint32_t RISEIE : 1; /*!< [6..6] desc RISEIE */ + __IOM uint32_t HIGHIE : 1; /*!< [7..7] desc HIGHIE */ + __IOM uint32_t ATIMCLR : 1; /*!< [8..8] desc ATIMCLR */ + __IOM uint32_t ATIMBK : 1; /*!< [9..9] desc ATIMBK */ + __IOM uint32_t BLANKCH1B : 1; /*!< [10..10] desc BLANKCH1B */ + __IOM uint32_t BLANKCH2B : 1; /*!< [11..11] desc BLANKCH2B */ + __IOM uint32_t BLANKCH3B : 1; /*!< [12..12] desc BLANKCH3B */ + __IOM uint32_t BLANKFLT : 3; /*!< [15..13] desc BLANKFLT */ + } CR1_f; + } ; + + union { + __IOM uint32_t SR; /*!< (@ 0x0000000C) Status register */ + + struct { + __IOM uint32_t INTF : 1; /*!< [0..0] desc INTF */ + __IM uint32_t FLTV : 1; /*!< [1..1] desc FLTV */ + __IM uint32_t READY : 1; /*!< [2..2] desc READY */ + } SR_f; + } ; +} VC_TypeDef; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ WWDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc WWDT (WWDT) + */ + +typedef struct { /*!< (@ 0x40002C00) WWDT Structure */ + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t WCNT : 7; /*!< [6..0] desc WCNT */ + __IOM uint32_t EN : 1; /*!< [7..7] desc EN */ + } CR0_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000004) Control register2 */ + + struct { + __IOM uint32_t WINR : 7; /*!< [6..0] desc WINR */ + __IOM uint32_t PRS : 3; /*!< [9..7] desc PRS */ + __IOM uint32_t IE : 1; /*!< [10..10] desc IE */ + } CR1_f; + } ; + + union { + __IOM uint32_t SR; /*!< (@ 0x00000008) Status register */ + + struct { + __IOM uint32_t POV : 1; /*!< [0..0] desc POV */ + } SR_f; + } ; +} WWDT_TypeDef; /*!< Size = 12 (0xc) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define ADC_BASE 0x40012400UL +#define ATIM_BASE 0x40012C00UL +#define AWT_BASE 0x40014C00UL +#define BTIM1_BASE 0x40014800UL +#define BTIM2_BASE 0x40014900UL +#define BTIM3_BASE 0x40014A00UL +#define CRC_BASE 0x40023000UL +#define DMA_BASE 0x40020000UL +#define DMACHANNEL1_BASE 0x40020020UL +#define DMACHANNEL2_BASE 0x40020040UL +#define DMACHANNEL3_BASE 0x40020060UL +#define DMACHANNEL4_BASE 0x40020080UL +#define DMACHANNEL5_BASE 0x400200A0UL +#define FLASH_BASE 0x40022000UL +#define GPIOA_BASE 0x48000000UL +#define GPIOB_BASE 0x48000400UL +#define GPIOC_BASE 0x48000800UL +#define GPIOF_BASE 0x48001400UL +#define GTIM1_BASE 0x40000400UL +#define GTIM2_BASE 0x40001000UL +#define GTIM3_BASE 0x40014000UL +#define GTIM4_BASE 0x40014400UL +#define I2C1_BASE 0x40005400UL +#define I2C2_BASE 0x40005800UL +#define IWDT_BASE 0x40003000UL +#define LVD_BASE 0x40012A80UL +#define RAM_BASE 0x40022400UL +#define RTC_BASE 0x40002800UL +#define SPI1_BASE 0x40013000UL +#define SPI2_BASE 0x40003800UL +#define SYSCTRL_BASE 0x40010000UL +#define UART1_BASE 0x40013800UL +#define UART2_BASE 0x40004400UL +#define UART3_BASE 0x40004800UL +#define VC1_BASE 0x40012A00UL +#define VC2_BASE 0x40012A10UL +#define WWDT_BASE 0x40002C00UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define M0P_ADC ((ADC_TypeDef*) ADC_BASE) +#define M0P_ATIM ((ATIM_TypeDef*) ATIM_BASE) +#define M0P_AWT ((AWT_TypeDef*) AWT_BASE) +#define M0P_BTIM1 ((BTIM_TypeDef*) BTIM1_BASE) +#define M0P_BTIM2 ((BTIM_TypeDef*) BTIM2_BASE) +#define M0P_BTIM3 ((BTIM_TypeDef*) BTIM3_BASE) +#define M0P_CRC ((CRC_TypeDef*) CRC_BASE) +#define M0P_DMA ((DMA_TypeDef*) DMA_BASE) +#define M0P_DMACHANNEL1 ((DMACHANNEL_TypeDef*) DMACHANNEL1_BASE) +#define M0P_DMACHANNEL2 ((DMACHANNEL_TypeDef*) DMACHANNEL2_BASE) +#define M0P_DMACHANNEL3 ((DMACHANNEL_TypeDef*) DMACHANNEL3_BASE) +#define M0P_DMACHANNEL4 ((DMACHANNEL_TypeDef*) DMACHANNEL4_BASE) +#define M0P_DMACHANNEL5 ((DMACHANNEL_TypeDef*) DMACHANNEL5_BASE) +#define M0P_FLASH ((FLASH_TypeDef*) FLASH_BASE) +#define M0P_GPIOA ((GPIO_TypeDef*) GPIOA_BASE) +#define M0P_GPIOB ((GPIO_TypeDef*) GPIOB_BASE) +#define M0P_GPIOC ((GPIO_TypeDef*) GPIOC_BASE) +#define M0P_GPIOF ((GPIO_TypeDef*) GPIOF_BASE) +#define M0P_GTIM1 ((GTIM_TypeDef*) GTIM1_BASE) +#define M0P_GTIM2 ((GTIM_TypeDef*) GTIM2_BASE) +#define M0P_GTIM3 ((GTIM_TypeDef*) GTIM3_BASE) +#define M0P_GTIM4 ((GTIM_TypeDef*) GTIM4_BASE) +#define M0P_I2C1 ((I2C_TypeDef*) I2C1_BASE) +#define M0P_I2C2 ((I2C_TypeDef*) I2C2_BASE) +#define M0P_IWDT ((IWDT_TypeDef*) IWDT_BASE) +#define M0P_LVD ((LVD_TypeDef*) LVD_BASE) +#define M0P_RAM ((RAM_TypeDef*) RAM_BASE) +#define M0P_RTC ((RTC_TypeDef*) RTC_BASE) +#define M0P_SPI1 ((SPI_TypeDef*) SPI1_BASE) +#define M0P_SPI2 ((SPI_TypeDef*) SPI2_BASE) +#define M0P_SYSCTRL ((SYSCTRL_TypeDef*) SYSCTRL_BASE) +#define M0P_UART1 ((UART_TypeDef*) UART1_BASE) +#define M0P_UART2 ((UART_TypeDef*) UART2_BASE) +#define M0P_UART3 ((UART_TypeDef*) UART3_BASE) +#define M0P_VC1 ((VC_TypeDef*) VC1_BASE) +#define M0P_VC2 ((VC_TypeDef*) VC2_BASE) +#define M0P_WWDT ((WWDT_TypeDef*) WWDT_BASE) + +#define CW_ADC M0P_ADC +#define CW_ATIM M0P_ATIM +#define CW_AWT M0P_AWT +#define CW_BTIM1 M0P_BTIM1 +#define CW_BTIM2 M0P_BTIM2 +#define CW_BTIM3 M0P_BTIM3 +#define CW_CRC M0P_CRC +#define CW_DMA M0P_DMA +#define CW_DMACHANNEL1 M0P_DMACHANNEL1 +#define CW_DMACHANNEL2 M0P_DMACHANNEL2 +#define CW_DMACHANNEL3 M0P_DMACHANNEL3 +#define CW_DMACHANNEL4 M0P_DMACHANNEL4 +#define CW_DMACHANNEL5 M0P_DMACHANNEL5 +#define CW_FLASH M0P_FLASH +#define CW_GPIOA M0P_GPIOA +#define CW_GPIOB M0P_GPIOB +#define CW_GPIOC M0P_GPIOC +#define CW_GPIOF M0P_GPIOF +#define CW_GTIM1 M0P_GTIM1 +#define CW_GTIM2 M0P_GTIM2 +#define CW_GTIM3 M0P_GTIM3 +#define CW_GTIM4 M0P_GTIM4 +#define CW_I2C1 M0P_I2C1 +#define CW_I2C2 M0P_I2C2 +#define CW_IWDT M0P_IWDT +#define CW_LVD M0P_LVD +#define CW_RAM M0P_RAM +#define CW_RTC M0P_RTC +#define CW_SPI1 M0P_SPI1 +#define CW_SPI2 M0P_SPI2 +#define CW_SYSCTRL M0P_SYSCTRL +#define CW_UART1 M0P_UART1 +#define CW_UART2 M0P_UART2 +#define CW_UART3 M0P_UART3 +#define CW_VC1 M0P_VC1 +#define CW_VC2 M0P_VC2 +#define CW_WWDT M0P_WWDT + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define ADC_CR0_BIAS_Pos (14UL) /*!< BIAS (Bit 14) */ +#define ADC_CR0_BIAS_Msk (0xc000UL) /*!< BIAS (Bitfield-Mask: 0x03) */ +#define ADC_CR0_BUF_Pos (13UL) /*!< BUF (Bit 13) */ +#define ADC_CR0_BUF_Msk (0x2000UL) /*!< BUF (Bitfield-Mask: 0x01) */ +#define ADC_CR0_SAM_Pos (11UL) /*!< SAM (Bit 11) */ +#define ADC_CR0_SAM_Msk (0x1800UL) /*!< SAM (Bitfield-Mask: 0x03) */ +#define ADC_CR0_CLK_Pos (8UL) /*!< CLK (Bit 8) */ +#define ADC_CR0_CLK_Msk (0x700UL) /*!< CLK (Bitfield-Mask: 0x07) */ +#define ADC_CR0_REF_Pos (6UL) /*!< REF (Bit 6) */ +#define ADC_CR0_REF_Msk (0xc0UL) /*!< REF (Bitfield-Mask: 0x03) */ +#define ADC_CR0_TSEN_Pos (5UL) /*!< TSEN (Bit 5) */ +#define ADC_CR0_TSEN_Msk (0x20UL) /*!< TSEN (Bitfield-Mask: 0x01) */ +#define ADC_CR0_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ +#define ADC_CR0_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +#define ADC_CR0_MODE_Pos (1UL) /*!< MODE (Bit 1) */ +#define ADC_CR0_MODE_Msk (0xeUL) /*!< MODE (Bitfield-Mask: 0x07) */ +#define ADC_CR0_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define ADC_CR0_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ +#define ADC_CR1_WDTALL_Pos (13UL) /*!< WDTALL (Bit 13) */ +#define ADC_CR1_WDTALL_Msk (0x2000UL) /*!< WDTALL (Bitfield-Mask: 0x01) */ +#define ADC_CR1_WDTCH_Pos (8UL) /*!< WDTCH (Bit 8) */ +#define ADC_CR1_WDTCH_Msk (0xf00UL) /*!< WDTCH (Bitfield-Mask: 0x0f) */ +#define ADC_CR1_DMAEN_Pos (7UL) /*!< DMAEN (Bit 7) */ +#define ADC_CR1_DMAEN_Msk (0x80UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +#define ADC_CR1_ALIGN_Pos (6UL) /*!< ALIGN (Bit 6) */ +#define ADC_CR1_ALIGN_Msk (0x40UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ +#define ADC_CR1_DISCARD_Pos (5UL) /*!< DISCARD (Bit 5) */ +#define ADC_CR1_DISCARD_Msk (0x20UL) /*!< DISCARD (Bitfield-Mask: 0x01) */ +#define ADC_CR1_CHMUX_Pos (0UL) /*!< CHMUX (Bit 0) */ +#define ADC_CR1_CHMUX_Msk (0xfUL) /*!< CHMUX (Bitfield-Mask: 0x0f) */ +/* ========================================================= START ========================================================= */ +#define ADC_START_AUTOSTOP_Pos (1UL) /*!< AUTOSTOP (Bit 1) */ +#define ADC_START_AUTOSTOP_Msk (0x2UL) /*!< AUTOSTOP (Bitfield-Mask: 0x01) */ +#define ADC_START_START_Pos (0UL) /*!< START (Bit 0) */ +#define ADC_START_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================== SQR ========================================================== */ +#define ADC_SQR_ENS_Pos (16UL) /*!< ENS (Bit 16) */ +#define ADC_SQR_ENS_Msk (0x30000UL) /*!< ENS (Bitfield-Mask: 0x03) */ +#define ADC_SQR_SQR3_Pos (12UL) /*!< SQR3 (Bit 12) */ +#define ADC_SQR_SQR3_Msk (0xf000UL) /*!< SQR3 (Bitfield-Mask: 0x0f) */ +#define ADC_SQR_SQR2_Pos (8UL) /*!< SQR2 (Bit 8) */ +#define ADC_SQR_SQR2_Msk (0xf00UL) /*!< SQR2 (Bitfield-Mask: 0x0f) */ +#define ADC_SQR_SQR1_Pos (4UL) /*!< SQR1 (Bit 4) */ +#define ADC_SQR_SQR1_Msk (0xf0UL) /*!< SQR1 (Bitfield-Mask: 0x0f) */ +#define ADC_SQR_SQR0_Pos (0UL) /*!< SQR0 (Bit 0) */ +#define ADC_SQR_SQR0_Msk (0xfUL) /*!< SQR0 (Bitfield-Mask: 0x0f) */ +/* ========================================================== CR2 ========================================================== */ +#define ADC_CR2_ACCRST_Pos (9UL) /*!< ACCRST (Bit 9) */ +#define ADC_CR2_ACCRST_Msk (0x200UL) /*!< ACCRST (Bitfield-Mask: 0x01) */ +#define ADC_CR2_ACCEN_Pos (8UL) /*!< ACCEN (Bit 8) */ +#define ADC_CR2_ACCEN_Msk (0x100UL) /*!< ACCEN (Bitfield-Mask: 0x01) */ +#define ADC_CR2_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define ADC_CR2_CNT_Msk (0xffUL) /*!< CNT (Bitfield-Mask: 0xff) */ +/* ========================================================== VTH ========================================================== */ +#define ADC_VTH_VTH_Pos (0UL) /*!< VTH (Bit 0) */ +#define ADC_VTH_VTH_Msk (0xfffUL) /*!< VTH (Bitfield-Mask: 0xfff) */ +/* ========================================================== VTL ========================================================== */ +#define ADC_VTL_VTL_Pos (0UL) /*!< VTL (Bit 0) */ +#define ADC_VTL_VTL_Msk (0xfffUL) /*!< VTL (Bitfield-Mask: 0xfff) */ +/* ======================================================== TRIGGER ======================================================== */ +#define ADC_TRIGGER_DMA_Pos (15UL) /*!< DMA (Bit 15) */ +#define ADC_TRIGGER_DMA_Msk (0x8000UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_I2C2_Pos (14UL) /*!< I2C2 (Bit 14) */ +#define ADC_TRIGGER_I2C2_Msk (0x4000UL) /*!< I2C2 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_I2C1_Pos (13UL) /*!< I2C1 (Bit 13) */ +#define ADC_TRIGGER_I2C1_Msk (0x2000UL) /*!< I2C1 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_SPI2_Pos (12UL) /*!< SPI2 (Bit 12) */ +#define ADC_TRIGGER_SPI2_Msk (0x1000UL) /*!< SPI2 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_SPI1_Pos (11UL) /*!< SPI1 (Bit 11) */ +#define ADC_TRIGGER_SPI1_Msk (0x800UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_UART3_Pos (10UL) /*!< UART3 (Bit 10) */ +#define ADC_TRIGGER_UART3_Msk (0x400UL) /*!< UART3 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_UART2_Pos (9UL) /*!< UART2 (Bit 9) */ +#define ADC_TRIGGER_UART2_Msk (0x200UL) /*!< UART2 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_UART1_Pos (8UL) /*!< UART1 (Bit 8) */ +#define ADC_TRIGGER_UART1_Msk (0x100UL) /*!< UART1 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_BTIM3_Pos (7UL) /*!< BTIM3 (Bit 7) */ +#define ADC_TRIGGER_BTIM3_Msk (0x80UL) /*!< BTIM3 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_BTIM2_Pos (6UL) /*!< BTIM2 (Bit 6) */ +#define ADC_TRIGGER_BTIM2_Msk (0x40UL) /*!< BTIM2 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_BTIM1_Pos (5UL) /*!< BTIM1 (Bit 5) */ +#define ADC_TRIGGER_BTIM1_Msk (0x20UL) /*!< BTIM1 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_GTIM4_Pos (4UL) /*!< GTIM4 (Bit 4) */ +#define ADC_TRIGGER_GTIM4_Msk (0x10UL) /*!< GTIM4 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_GTIM3_Pos (3UL) /*!< GTIM3 (Bit 3) */ +#define ADC_TRIGGER_GTIM3_Msk (0x8UL) /*!< GTIM3 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_GTIM2_Pos (2UL) /*!< GTIM2 (Bit 2) */ +#define ADC_TRIGGER_GTIM2_Msk (0x4UL) /*!< GTIM2 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_GTIM1_Pos (1UL) /*!< GTIM1 (Bit 1) */ +#define ADC_TRIGGER_GTIM1_Msk (0x2UL) /*!< GTIM1 (Bitfield-Mask: 0x01) */ +#define ADC_TRIGGER_ATIM_Pos (0UL) /*!< ATIM (Bit 0) */ +#define ADC_TRIGGER_ATIM_Msk (0x1UL) /*!< ATIM (Bitfield-Mask: 0x01) */ +/* ======================================================== RESULT0 ======================================================== */ +#define ADC_RESULT0_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADC_RESULT0_RESULT_Msk (0xffffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT1 ======================================================== */ +#define ADC_RESULT1_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADC_RESULT1_RESULT_Msk (0xffffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT2 ======================================================== */ +#define ADC_RESULT2_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADC_RESULT2_RESULT_Msk (0xffffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT3 ======================================================== */ +#define ADC_RESULT3_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADC_RESULT3_RESULT_Msk (0xffffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================= RESULTACC ======================================================= */ +#define ADC_RESULTACC_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADC_RESULTACC_RESULT_Msk (0xffffffUL) /*!< RESULT (Bitfield-Mask: 0xffffff) */ +/* ========================================================== IER ========================================================== */ +#define ADC_IER_OVW_Pos (6UL) /*!< OVW (Bit 6) */ +#define ADC_IER_OVW_Msk (0x40UL) /*!< OVW (Bitfield-Mask: 0x01) */ +#define ADC_IER_WDTR_Pos (5UL) /*!< WDTR (Bit 5) */ +#define ADC_IER_WDTR_Msk (0x20UL) /*!< WDTR (Bitfield-Mask: 0x01) */ +#define ADC_IER_WDTH_Pos (4UL) /*!< WDTH (Bit 4) */ +#define ADC_IER_WDTH_Msk (0x10UL) /*!< WDTH (Bitfield-Mask: 0x01) */ +#define ADC_IER_WDTL_Pos (3UL) /*!< WDTL (Bit 3) */ +#define ADC_IER_WDTL_Msk (0x8UL) /*!< WDTL (Bitfield-Mask: 0x01) */ +#define ADC_IER_EOA_Pos (2UL) /*!< EOA (Bit 2) */ +#define ADC_IER_EOA_Msk (0x4UL) /*!< EOA (Bitfield-Mask: 0x01) */ +#define ADC_IER_EOS_Pos (1UL) /*!< EOS (Bit 1) */ +#define ADC_IER_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */ +#define ADC_IER_EOC_Pos (0UL) /*!< EOC (Bit 0) */ +#define ADC_IER_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define ADC_ISR_READY_Pos (7UL) /*!< READY (Bit 7) */ +#define ADC_ISR_READY_Msk (0x80UL) /*!< READY (Bitfield-Mask: 0x01) */ +#define ADC_ISR_OVW_Pos (6UL) /*!< OVW (Bit 6) */ +#define ADC_ISR_OVW_Msk (0x40UL) /*!< OVW (Bitfield-Mask: 0x01) */ +#define ADC_ISR_WDTR_Pos (5UL) /*!< WDTR (Bit 5) */ +#define ADC_ISR_WDTR_Msk (0x20UL) /*!< WDTR (Bitfield-Mask: 0x01) */ +#define ADC_ISR_WDTH_Pos (4UL) /*!< WDTH (Bit 4) */ +#define ADC_ISR_WDTH_Msk (0x10UL) /*!< WDTH (Bitfield-Mask: 0x01) */ +#define ADC_ISR_WDTL_Pos (3UL) /*!< WDTL (Bit 3) */ +#define ADC_ISR_WDTL_Msk (0x8UL) /*!< WDTL (Bitfield-Mask: 0x01) */ +#define ADC_ISR_EOA_Pos (2UL) /*!< EOA (Bit 2) */ +#define ADC_ISR_EOA_Msk (0x4UL) /*!< EOA (Bitfield-Mask: 0x01) */ +#define ADC_ISR_EOS_Pos (1UL) /*!< EOS (Bit 1) */ +#define ADC_ISR_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */ +#define ADC_ISR_EOC_Pos (0UL) /*!< EOC (Bit 0) */ +#define ADC_ISR_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define ADC_ICR_OVW_Pos (6UL) /*!< OVW (Bit 6) */ +#define ADC_ICR_OVW_Msk (0x40UL) /*!< OVW (Bitfield-Mask: 0x01) */ +#define ADC_ICR_WDTR_Pos (5UL) /*!< WDTR (Bit 5) */ +#define ADC_ICR_WDTR_Msk (0x20UL) /*!< WDTR (Bitfield-Mask: 0x01) */ +#define ADC_ICR_WDTH_Pos (4UL) /*!< WDTH (Bit 4) */ +#define ADC_ICR_WDTH_Msk (0x10UL) /*!< WDTH (Bitfield-Mask: 0x01) */ +#define ADC_ICR_WDTL_Pos (3UL) /*!< WDTL (Bit 3) */ +#define ADC_ICR_WDTL_Msk (0x8UL) /*!< WDTL (Bitfield-Mask: 0x01) */ +#define ADC_ICR_EOA_Pos (2UL) /*!< EOA (Bit 2) */ +#define ADC_ICR_EOA_Msk (0x4UL) /*!< EOA (Bitfield-Mask: 0x01) */ +#define ADC_ICR_EOS_Pos (1UL) /*!< EOS (Bit 1) */ +#define ADC_ICR_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */ +#define ADC_ICR_EOC_Pos (0UL) /*!< EOC (Bit 0) */ +#define ADC_ICR_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */ +/* ======================================================= RESULT140 ======================================================= */ +#define ADC_RESULT140_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADC_RESULT140_RESULT_Msk (0xffffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================= RESULT141 ======================================================= */ +#define ADC_RESULT141_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADC_RESULT141_RESULT_Msk (0xffffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================= RESULT142 ======================================================= */ +#define ADC_RESULT142_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADC_RESULT142_RESULT_Msk (0xffffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================= RESULT143 ======================================================= */ +#define ADC_RESULT143_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADC_RESULT143_RESULT_Msk (0xffffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================= ENABLE14 ======================================================== */ +#define ADC_ENABLE14_KEY_Pos (0UL) /*!< KEY (Bit 0) */ +#define ADC_ENABLE14_KEY_Msk (0xffffUL) /*!< KEY (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ ATIM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ARR ========================================================== */ +#define ATIM_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define ATIM_ARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ========================================================== CNT ========================================================== */ +#define ATIM_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define ATIM_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== CR =========================================================== */ +#define ATIM_CR_UNDE_Pos (29UL) /*!< UNDE (Bit 29) */ +#define ATIM_CR_UNDE_Msk (0x20000000UL) /*!< UNDE (Bitfield-Mask: 0x01) */ +#define ATIM_CR_OVE_Pos (28UL) /*!< OVE (Bit 28) */ +#define ATIM_CR_OVE_Msk (0x10000000UL) /*!< OVE (Bitfield-Mask: 0x01) */ +#define ATIM_CR_DIR_Pos (27UL) /*!< DIR (Bit 27) */ +#define ATIM_CR_DIR_Msk (0x8000000UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define ATIM_CR_BG_Pos (26UL) /*!< BG (Bit 26) */ +#define ATIM_CR_BG_Msk (0x4000000UL) /*!< BG (Bitfield-Mask: 0x01) */ +#define ATIM_CR_UG_Pos (25UL) /*!< UG (Bit 25) */ +#define ATIM_CR_UG_Msk (0x2000000UL) /*!< UG (Bitfield-Mask: 0x01) */ +#define ATIM_CR_TG_Pos (24UL) /*!< TG (Bit 24) */ +#define ATIM_CR_TG_Msk (0x1000000UL) /*!< TG (Bitfield-Mask: 0x01) */ +#define ATIM_CR_OCCE_Pos (23UL) /*!< OCCE (Bit 23) */ +#define ATIM_CR_OCCE_Msk (0x800000UL) /*!< OCCE (Bitfield-Mask: 0x01) */ +#define ATIM_CR_CISA_Pos (21UL) /*!< CISA (Bit 21) */ +#define ATIM_CR_CISA_Msk (0x600000UL) /*!< CISA (Bitfield-Mask: 0x03) */ +#define ATIM_CR_BIE_Pos (20UL) /*!< BIE (Bit 20) */ +#define ATIM_CR_BIE_Msk (0x100000UL) /*!< BIE (Bitfield-Mask: 0x01) */ +#define ATIM_CR_TIE_Pos (19UL) /*!< TIE (Bit 19) */ +#define ATIM_CR_TIE_Msk (0x80000UL) /*!< TIE (Bitfield-Mask: 0x01) */ +#define ATIM_CR_URS_Pos (17UL) /*!< URS (Bit 17) */ +#define ATIM_CR_URS_Msk (0x20000UL) /*!< URS (Bitfield-Mask: 0x01) */ +#define ATIM_CR_OCCS_Pos (16UL) /*!< OCCS (Bit 16) */ +#define ATIM_CR_OCCS_Msk (0x10000UL) /*!< OCCS (Bitfield-Mask: 0x01) */ +#define ATIM_CR_ONESHOT_Pos (14UL) /*!< ONESHOT (Bit 14) */ +#define ATIM_CR_ONESHOT_Msk (0x4000UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ +#define ATIM_CR_MODE_Pos (12UL) /*!< MODE (Bit 12) */ +#define ATIM_CR_MODE_Msk (0x3000UL) /*!< MODE (Bitfield-Mask: 0x03) */ +#define ATIM_CR_UIE_Pos (10UL) /*!< UIE (Bit 10) */ +#define ATIM_CR_UIE_Msk (0x400UL) /*!< UIE (Bitfield-Mask: 0x01) */ +#define ATIM_CR_BUFPEN_Pos (7UL) /*!< BUFPEN (Bit 7) */ +#define ATIM_CR_BUFPEN_Msk (0x80UL) /*!< BUFPEN (Bitfield-Mask: 0x01) */ +#define ATIM_CR_PRS_Pos (4UL) /*!< PRS (Bit 4) */ +#define ATIM_CR_PRS_Msk (0x70UL) /*!< PRS (Bitfield-Mask: 0x07) */ +#define ATIM_CR_PWM2S_Pos (3UL) /*!< PWM2S (Bit 3) */ +#define ATIM_CR_PWM2S_Msk (0x8UL) /*!< PWM2S (Bitfield-Mask: 0x01) */ +#define ATIM_CR_CT_Pos (2UL) /*!< CT (Bit 2) */ +#define ATIM_CR_CT_Msk (0x4UL) /*!< CT (Bitfield-Mask: 0x01) */ +#define ATIM_CR_COMP_Pos (1UL) /*!< COMP (Bit 1) */ +#define ATIM_CR_COMP_Msk (0x2UL) /*!< COMP (Bitfield-Mask: 0x01) */ +#define ATIM_CR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define ATIM_CR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define ATIM_ISR_C4AF_Pos (18UL) /*!< C4AF (Bit 18) */ +#define ATIM_ISR_C4AF_Msk (0x40000UL) /*!< C4AF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_UNDF_Pos (17UL) /*!< UNDF (Bit 17) */ +#define ATIM_ISR_UNDF_Msk (0x20000UL) /*!< UNDF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_OVF_Pos (16UL) /*!< OVF (Bit 16) */ +#define ATIM_ISR_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_TIF_Pos (15UL) /*!< TIF (Bit 15) */ +#define ATIM_ISR_TIF_Msk (0x8000UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_BIF_Pos (14UL) /*!< BIF (Bit 14) */ +#define ATIM_ISR_BIF_Msk (0x4000UL) /*!< BIF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C3BE_Pos (13UL) /*!< C3BE (Bit 13) */ +#define ATIM_ISR_C3BE_Msk (0x2000UL) /*!< C3BE (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C2BE_Pos (12UL) /*!< C2BE (Bit 12) */ +#define ATIM_ISR_C2BE_Msk (0x1000UL) /*!< C2BE (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C1BE_Pos (11UL) /*!< C1BE (Bit 11) */ +#define ATIM_ISR_C1BE_Msk (0x800UL) /*!< C1BE (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C3AE_Pos (10UL) /*!< C3AE (Bit 10) */ +#define ATIM_ISR_C3AE_Msk (0x400UL) /*!< C3AE (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C2AE_Pos (9UL) /*!< C2AE (Bit 9) */ +#define ATIM_ISR_C2AE_Msk (0x200UL) /*!< C2AE (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C1AE_Pos (8UL) /*!< C1AE (Bit 8) */ +#define ATIM_ISR_C1AE_Msk (0x100UL) /*!< C1AE (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C3BF_Pos (7UL) /*!< C3BF (Bit 7) */ +#define ATIM_ISR_C3BF_Msk (0x80UL) /*!< C3BF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C2BF_Pos (6UL) /*!< C2BF (Bit 6) */ +#define ATIM_ISR_C2BF_Msk (0x40UL) /*!< C2BF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C1BF_Pos (5UL) /*!< C1BF (Bit 5) */ +#define ATIM_ISR_C1BF_Msk (0x20UL) /*!< C1BF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C3AF_Pos (4UL) /*!< C3AF (Bit 4) */ +#define ATIM_ISR_C3AF_Msk (0x10UL) /*!< C3AF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C2AF_Pos (3UL) /*!< C2AF (Bit 3) */ +#define ATIM_ISR_C2AF_Msk (0x8UL) /*!< C2AF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_C1AF_Pos (2UL) /*!< C1AF (Bit 2) */ +#define ATIM_ISR_C1AF_Msk (0x4UL) /*!< C1AF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_UIF_Pos (0UL) /*!< UIF (Bit 0) */ +#define ATIM_ISR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define ATIM_ICR_C4AF_Pos (18UL) /*!< C4AF (Bit 18) */ +#define ATIM_ICR_C4AF_Msk (0x40000UL) /*!< C4AF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_UNDF_Pos (17UL) /*!< UNDF (Bit 17) */ +#define ATIM_ICR_UNDF_Msk (0x20000UL) /*!< UNDF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_OVF_Pos (16UL) /*!< OVF (Bit 16) */ +#define ATIM_ICR_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_TIF_Pos (15UL) /*!< TIF (Bit 15) */ +#define ATIM_ICR_TIF_Msk (0x8000UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_BIF_Pos (14UL) /*!< BIF (Bit 14) */ +#define ATIM_ICR_BIF_Msk (0x4000UL) /*!< BIF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C3BE_Pos (13UL) /*!< C3BE (Bit 13) */ +#define ATIM_ICR_C3BE_Msk (0x2000UL) /*!< C3BE (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C2BE_Pos (12UL) /*!< C2BE (Bit 12) */ +#define ATIM_ICR_C2BE_Msk (0x1000UL) /*!< C2BE (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C1BE_Pos (11UL) /*!< C1BE (Bit 11) */ +#define ATIM_ICR_C1BE_Msk (0x800UL) /*!< C1BE (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C3AE_Pos (10UL) /*!< C3AE (Bit 10) */ +#define ATIM_ICR_C3AE_Msk (0x400UL) /*!< C3AE (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C2AE_Pos (9UL) /*!< C2AE (Bit 9) */ +#define ATIM_ICR_C2AE_Msk (0x200UL) /*!< C2AE (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C1AE_Pos (8UL) /*!< C1AE (Bit 8) */ +#define ATIM_ICR_C1AE_Msk (0x100UL) /*!< C1AE (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C3BF_Pos (7UL) /*!< C3BF (Bit 7) */ +#define ATIM_ICR_C3BF_Msk (0x80UL) /*!< C3BF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C2BF_Pos (6UL) /*!< C2BF (Bit 6) */ +#define ATIM_ICR_C2BF_Msk (0x40UL) /*!< C2BF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C1BF_Pos (5UL) /*!< C1BF (Bit 5) */ +#define ATIM_ICR_C1BF_Msk (0x20UL) /*!< C1BF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C3AF_Pos (4UL) /*!< C3AF (Bit 4) */ +#define ATIM_ICR_C3AF_Msk (0x10UL) /*!< C3AF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C2AF_Pos (3UL) /*!< C2AF (Bit 3) */ +#define ATIM_ICR_C2AF_Msk (0x8UL) /*!< C2AF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_C1AF_Pos (2UL) /*!< C1AF (Bit 2) */ +#define ATIM_ICR_C1AF_Msk (0x4UL) /*!< C1AF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_UIF_Pos (0UL) /*!< UIF (Bit 0) */ +#define ATIM_ICR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */ +/* ========================================================= MSCR ========================================================== */ +#define ATIM_MSCR_IB1S_Pos (12UL) /*!< IB1S (Bit 12) */ +#define ATIM_MSCR_IB1S_Msk (0x1000UL) /*!< IB1S (Bitfield-Mask: 0x01) */ +#define ATIM_MSCR_IA1S_Pos (11UL) /*!< IA1S (Bit 11) */ +#define ATIM_MSCR_IA1S_Msk (0x800UL) /*!< IA1S (Bitfield-Mask: 0x01) */ +#define ATIM_MSCR_SMS_Pos (8UL) /*!< SMS (Bit 8) */ +#define ATIM_MSCR_SMS_Msk (0x700UL) /*!< SMS (Bitfield-Mask: 0x07) */ +#define ATIM_MSCR_TS_Pos (5UL) /*!< TS (Bit 5) */ +#define ATIM_MSCR_TS_Msk (0xe0UL) /*!< TS (Bitfield-Mask: 0x07) */ +#define ATIM_MSCR_CCDS_Pos (3UL) /*!< CCDS (Bit 3) */ +#define ATIM_MSCR_CCDS_Msk (0x8UL) /*!< CCDS (Bitfield-Mask: 0x01) */ +#define ATIM_MSCR_MMS_Pos (0UL) /*!< MMS (Bit 0) */ +#define ATIM_MSCR_MMS_Msk (0x7UL) /*!< MMS (Bitfield-Mask: 0x07) */ +/* ========================================================= FLTR ========================================================== */ +#define ATIM_FLTR_ETP_Pos (31UL) /*!< ETP (Bit 31) */ +#define ATIM_FLTR_ETP_Msk (0x80000000UL) /*!< ETP (Bitfield-Mask: 0x01) */ +#define ATIM_FLTR_FLTET_Pos (28UL) /*!< FLTET (Bit 28) */ +#define ATIM_FLTR_FLTET_Msk (0x70000000UL) /*!< FLTET (Bitfield-Mask: 0x07) */ +#define ATIM_FLTR_BKP_Pos (27UL) /*!< BKP (Bit 27) */ +#define ATIM_FLTR_BKP_Msk (0x8000000UL) /*!< BKP (Bitfield-Mask: 0x01) */ +#define ATIM_FLTR_FLTBK_Pos (24UL) /*!< FLTBK (Bit 24) */ +#define ATIM_FLTR_FLTBK_Msk (0x7000000UL) /*!< FLTBK (Bitfield-Mask: 0x07) */ +#define ATIM_FLTR_CCP3B_Pos (23UL) /*!< CCP3B (Bit 23) */ +#define ATIM_FLTR_CCP3B_Msk (0x800000UL) /*!< CCP3B (Bitfield-Mask: 0x01) */ +#define ATIM_FLTR_OCM3BFLT3B_Pos (20UL) /*!< OCM3BFLT3B (Bit 20) */ +#define ATIM_FLTR_OCM3BFLT3B_Msk (0x700000UL) /*!< OCM3BFLT3B (Bitfield-Mask: 0x07) */ +#define ATIM_FLTR_CCP3A_Pos (19UL) /*!< CCP3A (Bit 19) */ +#define ATIM_FLTR_CCP3A_Msk (0x80000UL) /*!< CCP3A (Bitfield-Mask: 0x01) */ +#define ATIM_FLTR_OCM3AFLT3A_Pos (16UL) /*!< OCM3AFLT3A (Bit 16) */ +#define ATIM_FLTR_OCM3AFLT3A_Msk (0x70000UL) /*!< OCM3AFLT3A (Bitfield-Mask: 0x07) */ +#define ATIM_FLTR_CCP2B_Pos (15UL) /*!< CCP2B (Bit 15) */ +#define ATIM_FLTR_CCP2B_Msk (0x8000UL) /*!< CCP2B (Bitfield-Mask: 0x01) */ +#define ATIM_FLTR_OCM2BFLT2B_Pos (12UL) /*!< OCM2BFLT2B (Bit 12) */ +#define ATIM_FLTR_OCM2BFLT2B_Msk (0x7000UL) /*!< OCM2BFLT2B (Bitfield-Mask: 0x07) */ +#define ATIM_FLTR_CCP2A_Pos (11UL) /*!< CCP2A (Bit 11) */ +#define ATIM_FLTR_CCP2A_Msk (0x800UL) /*!< CCP2A (Bitfield-Mask: 0x01) */ +#define ATIM_FLTR_OCM2AFLT2A_Pos (8UL) /*!< OCM2AFLT2A (Bit 8) */ +#define ATIM_FLTR_OCM2AFLT2A_Msk (0x700UL) /*!< OCM2AFLT2A (Bitfield-Mask: 0x07) */ +#define ATIM_FLTR_CCP1B_Pos (7UL) /*!< CCP1B (Bit 7) */ +#define ATIM_FLTR_CCP1B_Msk (0x80UL) /*!< CCP1B (Bitfield-Mask: 0x01) */ +#define ATIM_FLTR_OCM1BFLT1B_Pos (4UL) /*!< OCM1BFLT1B (Bit 4) */ +#define ATIM_FLTR_OCM1BFLT1B_Msk (0x70UL) /*!< OCM1BFLT1B (Bitfield-Mask: 0x07) */ +#define ATIM_FLTR_CCP1A_Pos (3UL) /*!< CCP1A (Bit 3) */ +#define ATIM_FLTR_CCP1A_Msk (0x8UL) /*!< CCP1A (Bitfield-Mask: 0x01) */ +#define ATIM_FLTR_OCM1AFLT1A_Pos (0UL) /*!< OCM1AFLT1A (Bit 0) */ +#define ATIM_FLTR_OCM1AFLT1A_Msk (0x7UL) /*!< OCM1AFLT1A (Bitfield-Mask: 0x07) */ +/* ========================================================= TRIG ========================================================== */ +#define ATIM_TRIG_ADTE_Pos (7UL) /*!< ADTE (Bit 7) */ +#define ATIM_TRIG_ADTE_Msk (0x80UL) /*!< ADTE (Bitfield-Mask: 0x01) */ +#define ATIM_TRIG_CM3BE_Pos (6UL) /*!< CM3BE (Bit 6) */ +#define ATIM_TRIG_CM3BE_Msk (0x40UL) /*!< CM3BE (Bitfield-Mask: 0x01) */ +#define ATIM_TRIG_CM2BE_Pos (5UL) /*!< CM2BE (Bit 5) */ +#define ATIM_TRIG_CM2BE_Msk (0x20UL) /*!< CM2BE (Bitfield-Mask: 0x01) */ +#define ATIM_TRIG_CM1BE_Pos (4UL) /*!< CM1BE (Bit 4) */ +#define ATIM_TRIG_CM1BE_Msk (0x10UL) /*!< CM1BE (Bitfield-Mask: 0x01) */ +#define ATIM_TRIG_CM3AE_Pos (3UL) /*!< CM3AE (Bit 3) */ +#define ATIM_TRIG_CM3AE_Msk (0x8UL) /*!< CM3AE (Bitfield-Mask: 0x01) */ +#define ATIM_TRIG_CM2AE_Pos (2UL) /*!< CM2AE (Bit 2) */ +#define ATIM_TRIG_CM2AE_Msk (0x4UL) /*!< CM2AE (Bitfield-Mask: 0x01) */ +#define ATIM_TRIG_CM1AE_Pos (1UL) /*!< CM1AE (Bit 1) */ +#define ATIM_TRIG_CM1AE_Msk (0x2UL) /*!< CM1AE (Bitfield-Mask: 0x01) */ +#define ATIM_TRIG_UEVE_Pos (0UL) /*!< UEVE (Bit 0) */ +#define ATIM_TRIG_UEVE_Msk (0x1UL) /*!< UEVE (Bitfield-Mask: 0x01) */ +/* ========================================================= CH1CR ========================================================= */ +#define ATIM_CH1CR_CCGB_Pos (15UL) /*!< CCGB (Bit 15) */ +#define ATIM_CH1CR_CCGB_Msk (0x8000UL) /*!< CCGB (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_CCGA_Pos (14UL) /*!< CCGA (Bit 14) */ +#define ATIM_CH1CR_CCGA_Msk (0x4000UL) /*!< CCGA (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_CISB_Pos (12UL) /*!< CISB (Bit 12) */ +#define ATIM_CH1CR_CISB_Msk (0x3000UL) /*!< CISB (Bitfield-Mask: 0x03) */ +#define ATIM_CH1CR_CDEB_Pos (11UL) /*!< CDEB (Bit 11) */ +#define ATIM_CH1CR_CDEB_Msk (0x800UL) /*!< CDEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_CDEA_Pos (10UL) /*!< CDEA (Bit 10) */ +#define ATIM_CH1CR_CDEA_Msk (0x400UL) /*!< CDEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_CIEB_Pos (9UL) /*!< CIEB (Bit 9) */ +#define ATIM_CH1CR_CIEB_Msk (0x200UL) /*!< CIEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_CIEA_Pos (8UL) /*!< CIEA (Bit 8) */ +#define ATIM_CH1CR_CIEA_Msk (0x100UL) /*!< CIEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_BUFEB_Pos (7UL) /*!< BUFEB (Bit 7) */ +#define ATIM_CH1CR_BUFEB_Msk (0x80UL) /*!< BUFEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_BUFEA_Pos (6UL) /*!< BUFEA (Bit 6) */ +#define ATIM_CH1CR_BUFEA_Msk (0x40UL) /*!< BUFEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_CSB_Pos (5UL) /*!< CSB (Bit 5) */ +#define ATIM_CH1CR_CSB_Msk (0x20UL) /*!< CSB (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_CSA_Pos (4UL) /*!< CSA (Bit 4) */ +#define ATIM_CH1CR_CSA_Msk (0x10UL) /*!< CSA (Bitfield-Mask: 0x01) */ +#define ATIM_CH1CR_BKSB_Pos (2UL) /*!< BKSB (Bit 2) */ +#define ATIM_CH1CR_BKSB_Msk (0xcUL) /*!< BKSB (Bitfield-Mask: 0x03) */ +#define ATIM_CH1CR_BKSA_Pos (0UL) /*!< BKSA (Bit 0) */ +#define ATIM_CH1CR_BKSA_Msk (0x3UL) /*!< BKSA (Bitfield-Mask: 0x03) */ +/* ========================================================= CH2CR ========================================================= */ +#define ATIM_CH2CR_CCGB_Pos (15UL) /*!< CCGB (Bit 15) */ +#define ATIM_CH2CR_CCGB_Msk (0x8000UL) /*!< CCGB (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_CCGA_Pos (14UL) /*!< CCGA (Bit 14) */ +#define ATIM_CH2CR_CCGA_Msk (0x4000UL) /*!< CCGA (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_CISB_Pos (12UL) /*!< CISB (Bit 12) */ +#define ATIM_CH2CR_CISB_Msk (0x3000UL) /*!< CISB (Bitfield-Mask: 0x03) */ +#define ATIM_CH2CR_CDEB_Pos (11UL) /*!< CDEB (Bit 11) */ +#define ATIM_CH2CR_CDEB_Msk (0x800UL) /*!< CDEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_CDEA_Pos (10UL) /*!< CDEA (Bit 10) */ +#define ATIM_CH2CR_CDEA_Msk (0x400UL) /*!< CDEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_CIEB_Pos (9UL) /*!< CIEB (Bit 9) */ +#define ATIM_CH2CR_CIEB_Msk (0x200UL) /*!< CIEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_CIEA_Pos (8UL) /*!< CIEA (Bit 8) */ +#define ATIM_CH2CR_CIEA_Msk (0x100UL) /*!< CIEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_BUFEB_Pos (7UL) /*!< BUFEB (Bit 7) */ +#define ATIM_CH2CR_BUFEB_Msk (0x80UL) /*!< BUFEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_BUFEA_Pos (6UL) /*!< BUFEA (Bit 6) */ +#define ATIM_CH2CR_BUFEA_Msk (0x40UL) /*!< BUFEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_CSB_Pos (5UL) /*!< CSB (Bit 5) */ +#define ATIM_CH2CR_CSB_Msk (0x20UL) /*!< CSB (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_CSA_Pos (4UL) /*!< CSA (Bit 4) */ +#define ATIM_CH2CR_CSA_Msk (0x10UL) /*!< CSA (Bitfield-Mask: 0x01) */ +#define ATIM_CH2CR_BKSB_Pos (2UL) /*!< BKSB (Bit 2) */ +#define ATIM_CH2CR_BKSB_Msk (0xcUL) /*!< BKSB (Bitfield-Mask: 0x03) */ +#define ATIM_CH2CR_BKSA_Pos (0UL) /*!< BKSA (Bit 0) */ +#define ATIM_CH2CR_BKSA_Msk (0x3UL) /*!< BKSA (Bitfield-Mask: 0x03) */ +/* ========================================================= CH3CR ========================================================= */ +#define ATIM_CH3CR_CCGB_Pos (15UL) /*!< CCGB (Bit 15) */ +#define ATIM_CH3CR_CCGB_Msk (0x8000UL) /*!< CCGB (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_CCGA_Pos (14UL) /*!< CCGA (Bit 14) */ +#define ATIM_CH3CR_CCGA_Msk (0x4000UL) /*!< CCGA (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_CISB_Pos (12UL) /*!< CISB (Bit 12) */ +#define ATIM_CH3CR_CISB_Msk (0x3000UL) /*!< CISB (Bitfield-Mask: 0x03) */ +#define ATIM_CH3CR_CDEB_Pos (11UL) /*!< CDEB (Bit 11) */ +#define ATIM_CH3CR_CDEB_Msk (0x800UL) /*!< CDEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_CDEA_Pos (10UL) /*!< CDEA (Bit 10) */ +#define ATIM_CH3CR_CDEA_Msk (0x400UL) /*!< CDEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_CIEB_Pos (9UL) /*!< CIEB (Bit 9) */ +#define ATIM_CH3CR_CIEB_Msk (0x200UL) /*!< CIEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_CIEA_Pos (8UL) /*!< CIEA (Bit 8) */ +#define ATIM_CH3CR_CIEA_Msk (0x100UL) /*!< CIEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_BUFEB_Pos (7UL) /*!< BUFEB (Bit 7) */ +#define ATIM_CH3CR_BUFEB_Msk (0x80UL) /*!< BUFEB (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_BUFEA_Pos (6UL) /*!< BUFEA (Bit 6) */ +#define ATIM_CH3CR_BUFEA_Msk (0x40UL) /*!< BUFEA (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_CSB_Pos (5UL) /*!< CSB (Bit 5) */ +#define ATIM_CH3CR_CSB_Msk (0x20UL) /*!< CSB (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_CSA_Pos (4UL) /*!< CSA (Bit 4) */ +#define ATIM_CH3CR_CSA_Msk (0x10UL) /*!< CSA (Bitfield-Mask: 0x01) */ +#define ATIM_CH3CR_BKSB_Pos (2UL) /*!< BKSB (Bit 2) */ +#define ATIM_CH3CR_BKSB_Msk (0xcUL) /*!< BKSB (Bitfield-Mask: 0x03) */ +#define ATIM_CH3CR_BKSA_Pos (0UL) /*!< BKSA (Bit 0) */ +#define ATIM_CH3CR_BKSA_Msk (0x3UL) /*!< BKSA (Bitfield-Mask: 0x03) */ +/* ========================================================= CH4CR ========================================================= */ +#define ATIM_CH4CR_C4EN_Pos (5UL) /*!< C4EN (Bit 5) */ +#define ATIM_CH4CR_C4EN_Msk (0x20UL) /*!< C4EN (Bitfield-Mask: 0x01) */ +#define ATIM_CH4CR_CIS_Pos (3UL) /*!< CIS (Bit 3) */ +#define ATIM_CH4CR_CIS_Msk (0x18UL) /*!< CIS (Bitfield-Mask: 0x03) */ +#define ATIM_CH4CR_CDE_Pos (2UL) /*!< CDE (Bit 2) */ +#define ATIM_CH4CR_CDE_Msk (0x4UL) /*!< CDE (Bitfield-Mask: 0x01) */ +#define ATIM_CH4CR_CIE_Pos (1UL) /*!< CIE (Bit 1) */ +#define ATIM_CH4CR_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ +#define ATIM_CH4CR_BUFE_Pos (0UL) /*!< BUFE (Bit 0) */ +#define ATIM_CH4CR_BUFE_Msk (0x1UL) /*!< BUFE (Bitfield-Mask: 0x01) */ +/* ========================================================== DTR ========================================================== */ +#define ATIM_DTR_VCE_Pos (14UL) /*!< VCE (Bit 14) */ +#define ATIM_DTR_VCE_Msk (0x4000UL) /*!< VCE (Bitfield-Mask: 0x01) */ +#define ATIM_DTR_SAFEEN_Pos (13UL) /*!< SAFEEN (Bit 13) */ +#define ATIM_DTR_SAFEEN_Msk (0x2000UL) /*!< SAFEEN (Bitfield-Mask: 0x01) */ +#define ATIM_DTR_MOE_Pos (12UL) /*!< MOE (Bit 12) */ +#define ATIM_DTR_MOE_Msk (0x1000UL) /*!< MOE (Bitfield-Mask: 0x01) */ +#define ATIM_DTR_AOE_Pos (11UL) /*!< AOE (Bit 11) */ +#define ATIM_DTR_AOE_Msk (0x800UL) /*!< AOE (Bitfield-Mask: 0x01) */ +#define ATIM_DTR_BKE_Pos (10UL) /*!< BKE (Bit 10) */ +#define ATIM_DTR_BKE_Msk (0x400UL) /*!< BKE (Bitfield-Mask: 0x01) */ +#define ATIM_DTR_DTEN_Pos (9UL) /*!< DTEN (Bit 9) */ +#define ATIM_DTR_DTEN_Msk (0x200UL) /*!< DTEN (Bitfield-Mask: 0x01) */ +#define ATIM_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */ +#define ATIM_DTR_DTR_Msk (0xffUL) /*!< DTR (Bitfield-Mask: 0xff) */ +/* ========================================================== RCR ========================================================== */ +#define ATIM_RCR_UD_Pos (9UL) /*!< UD (Bit 9) */ +#define ATIM_RCR_UD_Msk (0x200UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define ATIM_RCR_OV_Pos (8UL) /*!< OV (Bit 8) */ +#define ATIM_RCR_OV_Msk (0x100UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define ATIM_RCR_RCR_Pos (0UL) /*!< RCR (Bit 0) */ +#define ATIM_RCR_RCR_Msk (0xffUL) /*!< RCR (Bitfield-Mask: 0xff) */ +/* ======================================================== CH1CCRA ======================================================== */ +#define ATIM_CH1CCRA_CCR1A_Pos (0UL) /*!< CCR1A (Bit 0) */ +#define ATIM_CH1CCRA_CCR1A_Msk (0xffffUL) /*!< CCR1A (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH1CCRB ======================================================== */ +#define ATIM_CH1CCRB_CCR1B_Pos (0UL) /*!< CCR1B (Bit 0) */ +#define ATIM_CH1CCRB_CCR1B_Msk (0xffffUL) /*!< CCR1B (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH2CCRA ======================================================== */ +#define ATIM_CH2CCRA_CCR2A_Pos (0UL) /*!< CCR2A (Bit 0) */ +#define ATIM_CH2CCRA_CCR2A_Msk (0xffffUL) /*!< CCR2A (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH2CCRB ======================================================== */ +#define ATIM_CH2CCRB_CCR2B_Pos (0UL) /*!< CCR2B (Bit 0) */ +#define ATIM_CH2CCRB_CCR2B_Msk (0xffffUL) /*!< CCR2B (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH3CCRA ======================================================== */ +#define ATIM_CH3CCRA_CCR3A_Pos (0UL) /*!< CCR3A (Bit 0) */ +#define ATIM_CH3CCRA_CCR3A_Msk (0xffffUL) /*!< CCR3A (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH3CCRB ======================================================== */ +#define ATIM_CH3CCRB_CCR3B_Pos (0UL) /*!< CCR3B (Bit 0) */ +#define ATIM_CH3CCRB_CCR3B_Msk (0xffffUL) /*!< CCR3B (Bitfield-Mask: 0xffff) */ +/* ======================================================== CH4CCR ========================================================= */ +#define ATIM_CH4CCR_CCR4_Pos (0UL) /*!< CCR4 (Bit 0) */ +#define ATIM_CH4CCR_CCR4_Msk (0xffffUL) /*!< CCR4 (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ AWT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define AWT_CR_SRC_Pos (8UL) /*!< SRC (Bit 8) */ +#define AWT_CR_SRC_Msk (0x700UL) /*!< SRC (Bitfield-Mask: 0x07) */ +#define AWT_CR_PRS_Pos (4UL) /*!< PRS (Bit 4) */ +#define AWT_CR_PRS_Msk (0xf0UL) /*!< PRS (Bitfield-Mask: 0x0f) */ +#define AWT_CR_MD_Pos (1UL) /*!< MD (Bit 1) */ +#define AWT_CR_MD_Msk (0x6UL) /*!< MD (Bitfield-Mask: 0x03) */ +#define AWT_CR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define AWT_CR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== ARR ========================================================== */ +#define AWT_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define AWT_ARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ========================================================== CNT ========================================================== */ +#define AWT_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define AWT_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== IER ========================================================== */ +#define AWT_IER_UD_Pos (3UL) /*!< UD (Bit 3) */ +#define AWT_IER_UD_Msk (0x8UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define AWT_ISR_UD_Pos (3UL) /*!< UD (Bit 3) */ +#define AWT_ISR_UD_Msk (0x8UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define AWT_ICR_UD_Pos (3UL) /*!< UD (Bit 3) */ +#define AWT_ICR_UD_Msk (0x8UL) /*!< UD (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ BTIM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ARR ========================================================== */ +#define BTIMx_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define BTIMx_ARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ========================================================== CNT ========================================================== */ +#define BTIMx_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define BTIMx_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== ACR ========================================================== */ +#define BTIMx_ACR_ETRFLT_Pos (4UL) /*!< ETRFLT (Bit 4) */ +#define BTIMx_ACR_ETRFLT_Msk (0x70UL) /*!< ETRFLT (Bitfield-Mask: 0x07) */ +/* ========================================================== BCR ========================================================== */ +#define BTIMx_BCR_PRSSTATUS_Pos (11UL) /*!< PRSSTATUS (Bit 11) */ +#define BTIMx_BCR_PRSSTATUS_Msk (0x7800UL) /*!< PRSSTATUS (Bitfield-Mask: 0x0f) */ +#define BTIMx_BCR_PRS_Pos (7UL) /*!< PRS (Bit 7) */ +#define BTIMx_BCR_PRS_Msk (0x780UL) /*!< PRS (Bitfield-Mask: 0x0f) */ +#define BTIMx_BCR_TOGEN_Pos (6UL) /*!< TOGEN (Bit 6) */ +#define BTIMx_BCR_TOGEN_Msk (0x40UL) /*!< TOGEN (Bitfield-Mask: 0x01) */ +#define BTIMx_BCR_ONESHOT_Pos (5UL) /*!< ONESHOT (Bit 5) */ +#define BTIMx_BCR_ONESHOT_Msk (0x20UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ +#define BTIMx_BCR_POL_Pos (4UL) /*!< POL (Bit 4) */ +#define BTIMx_BCR_POL_Msk (0x10UL) /*!< POL (Bitfield-Mask: 0x01) */ +#define BTIMx_BCR_TRS_Pos (3UL) /*!< TRS (Bit 3) */ +#define BTIMx_BCR_TRS_Msk (0x8UL) /*!< TRS (Bitfield-Mask: 0x01) */ +#define BTIMx_BCR_MODE_Pos (1UL) /*!< MODE (Bit 1) */ +#define BTIMx_BCR_MODE_Msk (0x6UL) /*!< MODE (Bitfield-Mask: 0x03) */ +#define BTIMx_BCR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define BTIMx_BCR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define BTIMx_IER_TOP_Pos (2UL) /*!< TOP (Bit 2) */ +#define BTIMx_IER_TOP_Msk (0x4UL) /*!< TOP (Bitfield-Mask: 0x01) */ +#define BTIMx_IER_TI_Pos (1UL) /*!< TI (Bit 1) */ +#define BTIMx_IER_TI_Msk (0x2UL) /*!< TI (Bitfield-Mask: 0x01) */ +#define BTIMx_IER_OV_Pos (0UL) /*!< OV (Bit 0) */ +#define BTIMx_IER_OV_Msk (0x1UL) /*!< OV (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define BTIMx_ISR_TOP_Pos (2UL) /*!< TOP (Bit 2) */ +#define BTIMx_ISR_TOP_Msk (0x4UL) /*!< TOP (Bitfield-Mask: 0x01) */ +#define BTIMx_ISR_TI_Pos (1UL) /*!< TI (Bit 1) */ +#define BTIMx_ISR_TI_Msk (0x2UL) /*!< TI (Bitfield-Mask: 0x01) */ +#define BTIMx_ISR_OV_Pos (0UL) /*!< OV (Bit 0) */ +#define BTIMx_ISR_OV_Msk (0x1UL) /*!< OV (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define BTIMx_ICR_TOP_Pos (2UL) /*!< TOP (Bit 2) */ +#define BTIMx_ICR_TOP_Msk (0x4UL) /*!< TOP (Bitfield-Mask: 0x01) */ +#define BTIMx_ICR_TI_Pos (1UL) /*!< TI (Bit 1) */ +#define BTIMx_ICR_TI_Msk (0x2UL) /*!< TI (Bitfield-Mask: 0x01) */ +#define BTIMx_ICR_OV_Pos (0UL) /*!< OV (Bit 0) */ +#define BTIMx_ICR_OV_Msk (0x1UL) /*!< OV (Bitfield-Mask: 0x01) */ +/* ========================================================== DMA ========================================================== */ +#define BTIMx_DMA_TRS_Pos (1UL) /*!< TRS (Bit 1) */ +#define BTIMx_DMA_TRS_Msk (0x2UL) /*!< TRS (Bitfield-Mask: 0x01) */ +#define BTIMx_DMA_OV_Pos (0UL) /*!< OV (Bit 0) */ +#define BTIMx_DMA_OV_Msk (0x1UL) /*!< OV (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ CRC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define CRC_CR_MODE_Pos (0UL) /*!< MODE (Bit 0) */ +#define CRC_CR_MODE_Msk (0xfUL) /*!< MODE (Bitfield-Mask: 0x0f) */ +/* ========================================================= DR32 ========================================================== */ +#define CRC_DR32_DR32_Pos (0UL) /*!< DR32 (Bit 0) */ +#define CRC_DR32_DR32_Msk (0xffffffffUL) /*!< DR32 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DR16 ========================================================== */ +#define CRC_DR16_DR16_Pos (0UL) /*!< DR16 (Bit 0) */ +#define CRC_DR16_DR16_Msk (0xffffUL) /*!< DR16 (Bitfield-Mask: 0xffff) */ +/* ========================================================== DR8 ========================================================== */ +#define CRC_DR8_DR8_Pos (0UL) /*!< DR8 (Bit 0) */ +#define CRC_DR8_DR8_Msk (0xffUL) /*!< DR8 (Bitfield-Mask: 0xff) */ +/* ======================================================= RESULT32 ======================================================== */ +#define CRC_RESULT32_RESULT32_Pos (0UL) /*!< RESULT32 (Bit 0) */ +#define CRC_RESULT32_RESULT32_Msk (0xffffffffUL) /*!< RESULT32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= RESULT16 ======================================================== */ +#define CRC_RESULT16_RESULT16_Pos (0UL) /*!< RESULT16 (Bit 0) */ +#define CRC_RESULT16_RESULT16_Msk (0xffffUL) /*!< RESULT16 (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ISR ========================================================== */ +#define DMA_ISR_TE5_Pos (17UL) /*!< TE5 (Bit 17) */ +#define DMA_ISR_TE5_Msk (0x20000UL) /*!< TE5 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC5_Pos (16UL) /*!< TC5 (Bit 16) */ +#define DMA_ISR_TC5_Msk (0x10000UL) /*!< TC5 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TE4_Pos (13UL) /*!< TE4 (Bit 13) */ +#define DMA_ISR_TE4_Msk (0x2000UL) /*!< TE4 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC4_Pos (12UL) /*!< TC4 (Bit 12) */ +#define DMA_ISR_TC4_Msk (0x1000UL) /*!< TC4 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TE3_Pos (9UL) /*!< TE3 (Bit 9) */ +#define DMA_ISR_TE3_Msk (0x200UL) /*!< TE3 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC3_Pos (8UL) /*!< TC3 (Bit 8) */ +#define DMA_ISR_TC3_Msk (0x100UL) /*!< TC3 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TE2_Pos (5UL) /*!< TE2 (Bit 5) */ +#define DMA_ISR_TE2_Msk (0x20UL) /*!< TE2 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC2_Pos (4UL) /*!< TC2 (Bit 4) */ +#define DMA_ISR_TC2_Msk (0x10UL) /*!< TC2 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TE1_Pos (1UL) /*!< TE1 (Bit 1) */ +#define DMA_ISR_TE1_Msk (0x2UL) /*!< TE1 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC1_Pos (0UL) /*!< TC1 (Bit 0) */ +#define DMA_ISR_TC1_Msk (0x1UL) /*!< TC1 (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define DMA_ICR_TE5_Pos (17UL) /*!< TE5 (Bit 17) */ +#define DMA_ICR_TE5_Msk (0x20000UL) /*!< TE5 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC5_Pos (16UL) /*!< TC5 (Bit 16) */ +#define DMA_ICR_TC5_Msk (0x10000UL) /*!< TC5 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TE4_Pos (13UL) /*!< TE4 (Bit 13) */ +#define DMA_ICR_TE4_Msk (0x2000UL) /*!< TE4 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC4_Pos (12UL) /*!< TC4 (Bit 12) */ +#define DMA_ICR_TC4_Msk (0x1000UL) /*!< TC4 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TE3_Pos (9UL) /*!< TE3 (Bit 9) */ +#define DMA_ICR_TE3_Msk (0x200UL) /*!< TE3 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC3_Pos (8UL) /*!< TC3 (Bit 8) */ +#define DMA_ICR_TC3_Msk (0x100UL) /*!< TC3 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TE2_Pos (5UL) /*!< TE2 (Bit 5) */ +#define DMA_ICR_TE2_Msk (0x20UL) /*!< TE2 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC2_Pos (4UL) /*!< TC2 (Bit 4) */ +#define DMA_ICR_TC2_Msk (0x10UL) /*!< TC2 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TE1_Pos (1UL) /*!< TE1 (Bit 1) */ +#define DMA_ICR_TE1_Msk (0x2UL) /*!< TE1 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC1_Pos (0UL) /*!< TC1 (Bit 0) */ +#define DMA_ICR_TC1_Msk (0x1UL) /*!< TC1 (Bitfield-Mask: 0x01) */ +/* ========================================================= CSR1 ========================================================== */ +#define DMA_CSR1_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR1_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR1_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR1_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR1_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR1_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR1_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR1_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR1_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR1_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR1_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT1 ========================================================== */ +#define DMA_CNT1_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT1_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT1_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT1_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR1 ======================================================== */ +#define DMA_SRCADDR1_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR1_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR1 ======================================================== */ +#define DMA_DSTADDR1_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR1_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG1 ========================================================= */ +#define DMA_TRIG1_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG1_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG1_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG1_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG1_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG1_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CSR2 ========================================================== */ +#define DMA_CSR2_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR2_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR2_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR2_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR2_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR2_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR2_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR2_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR2_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR2_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR2_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT2 ========================================================== */ +#define DMA_CNT2_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT2_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT2_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT2_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR2 ======================================================== */ +#define DMA_SRCADDR2_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR2_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR2 ======================================================== */ +#define DMA_DSTADDR2_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR2_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG2 ========================================================= */ +#define DMA_TRIG2_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG2_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG2_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG2_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG2_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG2_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CSR3 ========================================================== */ +#define DMA_CSR3_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR3_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR3_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR3_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR3_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR3_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR3_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR3_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR3_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR3_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR3_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT3 ========================================================== */ +#define DMA_CNT3_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT3_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT3_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT3_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR3 ======================================================== */ +#define DMA_SRCADDR3_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR3_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR3 ======================================================== */ +#define DMA_DSTADDR3_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR3_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG3 ========================================================= */ +#define DMA_TRIG3_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG3_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG3_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG3_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG3_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG3_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CSR4 ========================================================== */ +#define DMA_CSR4_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR4_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR4_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR4_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR4_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR4_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR4_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR4_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR4_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR4_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR4_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT4 ========================================================== */ +#define DMA_CNT4_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT4_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT4_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT4_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR4 ======================================================== */ +#define DMA_SRCADDR4_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR4_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR4 ======================================================== */ +#define DMA_DSTADDR4_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR4_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG4 ========================================================= */ +#define DMA_TRIG4_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG4_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG4_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG4_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG4_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG4_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CSR5 ========================================================== */ +#define DMA_CSR5_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR5_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR5_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR5_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR5_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR5_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR5_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR5_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR5_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR5_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR5_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR5_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR5_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR5_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR5_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR5_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT5 ========================================================== */ +#define DMA_CNT5_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT5_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT5_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT5_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR5 ======================================================== */ +#define DMA_SRCADDR5_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR5_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR5 ======================================================== */ +#define DMA_DSTADDR5_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR5_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG5 ========================================================= */ +#define DMA_TRIG5_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG5_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG5_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG5_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG5_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG5_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ DMACHANNEL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CSR ========================================================== */ +#define DMACHx_CSR_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMACHx_CSR_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMACHx_CSR_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMACHx_CSR_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMACHx_CSR_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMACHx_CSR_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMACHx_CSR_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMACHx_CSR_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMACHx_CSR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMACHx_CSR_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMACHx_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +#define DMACHx_CNT_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMACHx_CNT_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMACHx_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMACHx_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================== SRCADDR ======================================================== */ +#define DMACHx_SRCADDR_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMACHx_SRCADDR_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DSTADDR ======================================================== */ +#define DMACHx_DSTADDR_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMACHx_DSTADDR_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG ========================================================== */ +#define DMACHx_TRIG_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMACHx_TRIG_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMACHx_TRIG_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMACHx_TRIG_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMACHx_TRIG_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMACHx_TRIG_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ FLASH ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define FLASH_CR1_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define FLASH_CR1_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define FLASH_CR1_SECURITY_Pos (6UL) /*!< SECURITY (Bit 6) */ +#define FLASH_CR1_SECURITY_Msk (0xc0UL) /*!< SECURITY (Bitfield-Mask: 0x03) */ +#define FLASH_CR1_BUSY_Pos (5UL) /*!< BUSY (Bit 5) */ +#define FLASH_CR1_BUSY_Msk (0x20UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define FLASH_CR1_STANDBY_Pos (4UL) /*!< STANDBY (Bit 4) */ +#define FLASH_CR1_STANDBY_Msk (0x10UL) /*!< STANDBY (Bitfield-Mask: 0x01) */ +#define FLASH_CR1_MODE_Pos (0UL) /*!< MODE (Bit 0) */ +#define FLASH_CR1_MODE_Msk (0x3UL) /*!< MODE (Bitfield-Mask: 0x03) */ +/* ========================================================== CR2 ========================================================== */ +#define FLASH_CR2_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define FLASH_CR2_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define FLASH_CR2_CACHE_Pos (4UL) /*!< CACHE (Bit 4) */ +#define FLASH_CR2_CACHE_Msk (0x10UL) /*!< CACHE (Bitfield-Mask: 0x01) */ +#define FLASH_CR2_FETCH_Pos (3UL) /*!< FETCH (Bit 3) */ +#define FLASH_CR2_FETCH_Msk (0x8UL) /*!< FETCH (Bitfield-Mask: 0x01) */ +#define FLASH_CR2_WAIT_Pos (0UL) /*!< WAIT (Bit 0) */ +#define FLASH_CR2_WAIT_Msk (0x7UL) /*!< WAIT (Bitfield-Mask: 0x07) */ +/* ======================================================= PAGELOCK ======================================================== */ +#define FLASH_PAGELOCK_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define FLASH_PAGELOCK_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define FLASH_PAGELOCK_LOCK15_Pos (15UL) /*!< LOCK15 (Bit 15) */ +#define FLASH_PAGELOCK_LOCK15_Msk (0x8000UL) /*!< LOCK15 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK14_Pos (14UL) /*!< LOCK14 (Bit 14) */ +#define FLASH_PAGELOCK_LOCK14_Msk (0x4000UL) /*!< LOCK14 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK13_Pos (13UL) /*!< LOCK13 (Bit 13) */ +#define FLASH_PAGELOCK_LOCK13_Msk (0x2000UL) /*!< LOCK13 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK12_Pos (12UL) /*!< LOCK12 (Bit 12) */ +#define FLASH_PAGELOCK_LOCK12_Msk (0x1000UL) /*!< LOCK12 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK11_Pos (11UL) /*!< LOCK11 (Bit 11) */ +#define FLASH_PAGELOCK_LOCK11_Msk (0x800UL) /*!< LOCK11 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK10_Pos (10UL) /*!< LOCK10 (Bit 10) */ +#define FLASH_PAGELOCK_LOCK10_Msk (0x400UL) /*!< LOCK10 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK9_Pos (9UL) /*!< LOCK9 (Bit 9) */ +#define FLASH_PAGELOCK_LOCK9_Msk (0x200UL) /*!< LOCK9 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK8_Pos (8UL) /*!< LOCK8 (Bit 8) */ +#define FLASH_PAGELOCK_LOCK8_Msk (0x100UL) /*!< LOCK8 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK7_Pos (7UL) /*!< LOCK7 (Bit 7) */ +#define FLASH_PAGELOCK_LOCK7_Msk (0x80UL) /*!< LOCK7 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK6_Pos (6UL) /*!< LOCK6 (Bit 6) */ +#define FLASH_PAGELOCK_LOCK6_Msk (0x40UL) /*!< LOCK6 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK5_Pos (5UL) /*!< LOCK5 (Bit 5) */ +#define FLASH_PAGELOCK_LOCK5_Msk (0x20UL) /*!< LOCK5 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK4_Pos (4UL) /*!< LOCK4 (Bit 4) */ +#define FLASH_PAGELOCK_LOCK4_Msk (0x10UL) /*!< LOCK4 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK3_Pos (3UL) /*!< LOCK3 (Bit 3) */ +#define FLASH_PAGELOCK_LOCK3_Msk (0x8UL) /*!< LOCK3 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK2_Pos (2UL) /*!< LOCK2 (Bit 2) */ +#define FLASH_PAGELOCK_LOCK2_Msk (0x4UL) /*!< LOCK2 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK1_Pos (1UL) /*!< LOCK1 (Bit 1) */ +#define FLASH_PAGELOCK_LOCK1_Msk (0x2UL) /*!< LOCK1 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK0_Pos (0UL) /*!< LOCK0 (Bit 0) */ +#define FLASH_PAGELOCK_LOCK0_Msk (0x1UL) /*!< LOCK0 (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define FLASH_IER_PROG_Pos (4UL) /*!< PROG (Bit 4) */ +#define FLASH_IER_PROG_Msk (0x10UL) /*!< PROG (Bitfield-Mask: 0x01) */ +#define FLASH_IER_PAGELOCK_Pos (1UL) /*!< PAGELOCK (Bit 1) */ +#define FLASH_IER_PAGELOCK_Msk (0x2UL) /*!< PAGELOCK (Bitfield-Mask: 0x01) */ +#define FLASH_IER_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define FLASH_IER_PC_Msk (0x1UL) /*!< PC (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define FLASH_ISR_PROG_Pos (4UL) /*!< PROG (Bit 4) */ +#define FLASH_ISR_PROG_Msk (0x10UL) /*!< PROG (Bitfield-Mask: 0x01) */ +#define FLASH_ISR_PAGELOCK_Pos (1UL) /*!< PAGELOCK (Bit 1) */ +#define FLASH_ISR_PAGELOCK_Msk (0x2UL) /*!< PAGELOCK (Bitfield-Mask: 0x01) */ +#define FLASH_ISR_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define FLASH_ISR_PC_Msk (0x1UL) /*!< PC (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define FLASH_ICR_PROG_Pos (4UL) /*!< PROG (Bit 4) */ +#define FLASH_ICR_PROG_Msk (0x10UL) /*!< PROG (Bitfield-Mask: 0x01) */ +#define FLASH_ICR_PAGELOCK_Pos (1UL) /*!< PAGELOCK (Bit 1) */ +#define FLASH_ICR_PAGELOCK_Msk (0x2UL) /*!< PAGELOCK (Bitfield-Mask: 0x01) */ +#define FLASH_ICR_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define FLASH_ICR_PC_Msk (0x1UL) /*!< PC (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DIR ========================================================== */ +#define GPIOx_DIR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_DIR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_DIR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_DIR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_DIR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_DIR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_DIR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_DIR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_DIR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_DIR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_DIR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_DIR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_DIR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_DIR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_DIR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_DIR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_DIR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================= OPENDRAIN ======================================================= */ +#define GPIOx_OPENDRAIN_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_OPENDRAIN_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_OPENDRAIN_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_OPENDRAIN_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_OPENDRAIN_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_OPENDRAIN_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_OPENDRAIN_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_OPENDRAIN_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_OPENDRAIN_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_OPENDRAIN_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_OPENDRAIN_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_OPENDRAIN_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_OPENDRAIN_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_OPENDRAIN_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_OPENDRAIN_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_OPENDRAIN_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_OPENDRAIN_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SPEED ========================================================= */ +#define GPIOx_SPEED_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_SPEED_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_SPEED_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_SPEED_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_SPEED_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_SPEED_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_SPEED_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_SPEED_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_SPEED_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_SPEED_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_SPEED_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_SPEED_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_SPEED_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_SPEED_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_SPEED_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_SPEED_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_SPEED_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_SPEED_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ +#define GPIOx_PDR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_PDR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_PDR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_PDR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_PDR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_PDR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_PDR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_PDR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_PDR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_PDR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_PDR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_PDR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_PDR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_PDR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_PDR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_PDR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_PDR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_PDR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== PUR ========================================================== */ +#define GPIOx_PUR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_PUR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_PUR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_PUR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_PUR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_PUR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_PUR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_PUR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_PUR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_PUR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_PUR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_PUR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_PUR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_PUR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_PUR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_PUR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_PUR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= AFRH ========================================================== */ +#define GPIOx_AFRH_AFR15_Pos (28UL) /*!< AFR15 (Bit 28) */ +#define GPIOx_AFRH_AFR15_Msk (0xf0000000UL) /*!< AFR15 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_AFR14_Pos (24UL) /*!< AFR14 (Bit 24) */ +#define GPIOx_AFRH_AFR14_Msk (0xf000000UL) /*!< AFR14 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_AFR13_Pos (20UL) /*!< AFR13 (Bit 20) */ +#define GPIOx_AFRH_AFR13_Msk (0xf00000UL) /*!< AFR13 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_AFR12_Pos (16UL) /*!< AFR12 (Bit 16) */ +#define GPIOx_AFRH_AFR12_Msk (0xf0000UL) /*!< AFR12 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_AFR11_Pos (12UL) /*!< AFR11 (Bit 12) */ +#define GPIOx_AFRH_AFR11_Msk (0xf000UL) /*!< AFR11 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_AFR10_Pos (8UL) /*!< AFR10 (Bit 8) */ +#define GPIOx_AFRH_AFR10_Msk (0xf00UL) /*!< AFR10 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_AFR9_Pos (4UL) /*!< AFR9 (Bit 4) */ +#define GPIOx_AFRH_AFR9_Msk (0xf0UL) /*!< AFR9 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_AFR8_Pos (0UL) /*!< AFR8 (Bit 0) */ +#define GPIOx_AFRH_AFR8_Msk (0xfUL) /*!< AFR8 (Bitfield-Mask: 0x0f) */ +/* ========================================================= AFRL ========================================================== */ +#define GPIOx_AFRL_AFR7_Pos (28UL) /*!< AFR7 (Bit 28) */ +#define GPIOx_AFRL_AFR7_Msk (0xf0000000UL) /*!< AFR7 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_AFR6_Pos (24UL) /*!< AFR6 (Bit 24) */ +#define GPIOx_AFRL_AFR6_Msk (0xf000000UL) /*!< AFR6 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_AFR5_Pos (20UL) /*!< AFR5 (Bit 20) */ +#define GPIOx_AFRL_AFR5_Msk (0xf00000UL) /*!< AFR5 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_AFR4_Pos (16UL) /*!< AFR4 (Bit 16) */ +#define GPIOx_AFRL_AFR4_Msk (0xf0000UL) /*!< AFR4 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_AFR3_Pos (12UL) /*!< AFR3 (Bit 12) */ +#define GPIOx_AFRL_AFR3_Msk (0xf000UL) /*!< AFR3 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_AFR2_Pos (8UL) /*!< AFR2 (Bit 8) */ +#define GPIOx_AFRL_AFR2_Msk (0xf00UL) /*!< AFR2 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_AFR1_Pos (4UL) /*!< AFR1 (Bit 4) */ +#define GPIOx_AFRL_AFR1_Msk (0xf0UL) /*!< AFR1 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_AFR0_Pos (0UL) /*!< AFR0 (Bit 0) */ +#define GPIOx_AFRL_AFR0_Msk (0xfUL) /*!< AFR0 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ANALOG ========================================================= */ +#define GPIOx_ANALOG_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_ANALOG_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_ANALOG_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_ANALOG_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_ANALOG_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_ANALOG_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_ANALOG_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_ANALOG_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_ANALOG_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_ANALOG_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_ANALOG_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_ANALOG_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_ANALOG_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_ANALOG_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_ANALOG_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_ANALOG_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_ANALOG_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DRIVER ========================================================= */ +#define GPIOx_DRIVER_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_DRIVER_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_DRIVER_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_DRIVER_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_DRIVER_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_DRIVER_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_DRIVER_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_DRIVER_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_DRIVER_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_DRIVER_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_DRIVER_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_DRIVER_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_DRIVER_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_DRIVER_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_DRIVER_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_DRIVER_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_DRIVER_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_DRIVER_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== RISEIE ========================================================= */ +#define GPIOx_RISEIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_RISEIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_RISEIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_RISEIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_RISEIE_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_RISEIE_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_RISEIE_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_RISEIE_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_RISEIE_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_RISEIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_RISEIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_RISEIE_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_RISEIE_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_RISEIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_RISEIE_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_RISEIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_RISEIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FALLIE ========================================================= */ +#define GPIOx_FALLIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_FALLIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_FALLIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_FALLIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_FALLIE_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_FALLIE_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_FALLIE_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_FALLIE_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_FALLIE_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_FALLIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_FALLIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_FALLIE_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_FALLIE_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_FALLIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_FALLIE_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_FALLIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_FALLIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== HIGHIE ========================================================= */ +#define GPIOx_HIGHIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_HIGHIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_HIGHIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_HIGHIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_HIGHIE_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_HIGHIE_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_HIGHIE_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_HIGHIE_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_HIGHIE_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_HIGHIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_HIGHIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_HIGHIE_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_HIGHIE_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_HIGHIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_HIGHIE_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_HIGHIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_HIGHIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_HIGHIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= LOWIE ========================================================= */ +#define GPIOx_LOWIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_LOWIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_LOWIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_LOWIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_LOWIE_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_LOWIE_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_LOWIE_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_LOWIE_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_LOWIE_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_LOWIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_LOWIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_LOWIE_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_LOWIE_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_LOWIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_LOWIE_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_LOWIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOWIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_LOWIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define GPIOx_ISR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_ISR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_ISR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_ISR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_ISR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_ISR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_ISR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_ISR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_ISR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_ISR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_ISR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_ISR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_ISR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_ISR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_ISR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_ISR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_ISR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define GPIOx_ICR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_ICR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_ICR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_ICR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_ICR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_ICR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_ICR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_ICR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_ICR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_ICR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_ICR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_ICR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_ICR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_ICR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_ICR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_ICR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_ICR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= LOCK ========================================================== */ +#define GPIOx_LOCK_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define GPIOx_LOCK_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define GPIOx_LOCK_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_LOCK_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_LOCK_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_LOCK_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_LOCK_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_LOCK_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_LOCK_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_LOCK_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_LOCK_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_LOCK_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_LOCK_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_LOCK_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_LOCK_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_LOCK_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_LOCK_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_LOCK_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_LOCK_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_LOCK_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FILTER ========================================================= */ +#define GPIOx_FILTER_FLTCLK_Pos (16UL) /*!< FLTCLK (Bit 16) */ +#define GPIOx_FILTER_FLTCLK_Msk (0x70000UL) /*!< FLTCLK (Bitfield-Mask: 0x07) */ +#define GPIOx_FILTER_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_FILTER_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_FILTER_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_FILTER_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_FILTER_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_FILTER_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_FILTER_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_FILTER_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_FILTER_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_FILTER_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_FILTER_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_FILTER_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_FILTER_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_FILTER_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_FILTER_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_FILTER_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_FILTER_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== IDR ========================================================== */ +#define GPIOx_IDR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_IDR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_IDR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_IDR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_IDR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_IDR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_IDR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_IDR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_IDR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_IDR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_IDR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_IDR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_IDR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_IDR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_IDR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_IDR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_IDR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ODR ========================================================== */ +#define GPIOx_ODR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_ODR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_ODR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_ODR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_ODR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_ODR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_ODR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_ODR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_ODR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_ODR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_ODR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_ODR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_ODR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_ODR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_ODR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_ODR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_ODR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ====================================================== ODRLOWBYTE ======================================================= */ +#define GPIOx_ODRLOWBYTE_LOWBYTE_Pos (0UL) /*!< LOWBYTE (Bit 0) */ +#define GPIOx_ODRLOWBYTE_LOWBYTE_Msk (0xffUL) /*!< LOWBYTE (Bitfield-Mask: 0xff) */ +/* ====================================================== ODRHIGHBYTE ====================================================== */ +#define GPIOx_ODRHIGHBYTE_HIGHBYTE_Pos (0UL) /*!< HIGHBYTE (Bit 0) */ +#define GPIOx_ODRHIGHBYTE_HIGHBYTE_Msk (0xffUL) /*!< HIGHBYTE (Bitfield-Mask: 0xff) */ +/* ========================================================== BRR ========================================================== */ +#define GPIOx_BRR_BRR15_Pos (15UL) /*!< BRR15 (Bit 15) */ +#define GPIOx_BRR_BRR15_Msk (0x8000UL) /*!< BRR15 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR14_Pos (14UL) /*!< BRR14 (Bit 14) */ +#define GPIOx_BRR_BRR14_Msk (0x4000UL) /*!< BRR14 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR13_Pos (13UL) /*!< BRR13 (Bit 13) */ +#define GPIOx_BRR_BRR13_Msk (0x2000UL) /*!< BRR13 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR12_Pos (12UL) /*!< BRR12 (Bit 12) */ +#define GPIOx_BRR_BRR12_Msk (0x1000UL) /*!< BRR12 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR11_Pos (11UL) /*!< BRR11 (Bit 11) */ +#define GPIOx_BRR_BRR11_Msk (0x800UL) /*!< BRR11 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR10_Pos (10UL) /*!< BRR10 (Bit 10) */ +#define GPIOx_BRR_BRR10_Msk (0x400UL) /*!< BRR10 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR9_Pos (9UL) /*!< BRR9 (Bit 9) */ +#define GPIOx_BRR_BRR9_Msk (0x200UL) /*!< BRR9 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR8_Pos (8UL) /*!< BRR8 (Bit 8) */ +#define GPIOx_BRR_BRR8_Msk (0x100UL) /*!< BRR8 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR7_Pos (7UL) /*!< BRR7 (Bit 7) */ +#define GPIOx_BRR_BRR7_Msk (0x80UL) /*!< BRR7 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR6_Pos (6UL) /*!< BRR6 (Bit 6) */ +#define GPIOx_BRR_BRR6_Msk (0x40UL) /*!< BRR6 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR5_Pos (5UL) /*!< BRR5 (Bit 5) */ +#define GPIOx_BRR_BRR5_Msk (0x20UL) /*!< BRR5 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR4_Pos (4UL) /*!< BRR4 (Bit 4) */ +#define GPIOx_BRR_BRR4_Msk (0x10UL) /*!< BRR4 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR3_Pos (3UL) /*!< BRR3 (Bit 3) */ +#define GPIOx_BRR_BRR3_Msk (0x8UL) /*!< BRR3 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR2_Pos (2UL) /*!< BRR2 (Bit 2) */ +#define GPIOx_BRR_BRR2_Msk (0x4UL) /*!< BRR2 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR1_Pos (1UL) /*!< BRR1 (Bit 1) */ +#define GPIOx_BRR_BRR1_Msk (0x2UL) /*!< BRR1 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR0_Pos (0UL) /*!< BRR0 (Bit 0) */ +#define GPIOx_BRR_BRR0_Msk (0x1UL) /*!< BRR0 (Bitfield-Mask: 0x01) */ +/* ========================================================= BSRR ========================================================== */ +#define GPIOx_BSRR_BRR15_Pos (31UL) /*!< BRR15 (Bit 31) */ +#define GPIOx_BSRR_BRR15_Msk (0x80000000UL) /*!< BRR15 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR14_Pos (30UL) /*!< BRR14 (Bit 30) */ +#define GPIOx_BSRR_BRR14_Msk (0x40000000UL) /*!< BRR14 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR13_Pos (29UL) /*!< BRR13 (Bit 29) */ +#define GPIOx_BSRR_BRR13_Msk (0x20000000UL) /*!< BRR13 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR12_Pos (28UL) /*!< BRR12 (Bit 28) */ +#define GPIOx_BSRR_BRR12_Msk (0x10000000UL) /*!< BRR12 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR11_Pos (27UL) /*!< BRR11 (Bit 27) */ +#define GPIOx_BSRR_BRR11_Msk (0x8000000UL) /*!< BRR11 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR10_Pos (26UL) /*!< BRR10 (Bit 26) */ +#define GPIOx_BSRR_BRR10_Msk (0x4000000UL) /*!< BRR10 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR9_Pos (25UL) /*!< BRR9 (Bit 25) */ +#define GPIOx_BSRR_BRR9_Msk (0x2000000UL) /*!< BRR9 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR8_Pos (24UL) /*!< BRR8 (Bit 24) */ +#define GPIOx_BSRR_BRR8_Msk (0x1000000UL) /*!< BRR8 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR7_Pos (23UL) /*!< BRR7 (Bit 23) */ +#define GPIOx_BSRR_BRR7_Msk (0x800000UL) /*!< BRR7 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR6_Pos (22UL) /*!< BRR6 (Bit 22) */ +#define GPIOx_BSRR_BRR6_Msk (0x400000UL) /*!< BRR6 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR5_Pos (21UL) /*!< BRR5 (Bit 21) */ +#define GPIOx_BSRR_BRR5_Msk (0x200000UL) /*!< BRR5 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR4_Pos (20UL) /*!< BRR4 (Bit 20) */ +#define GPIOx_BSRR_BRR4_Msk (0x100000UL) /*!< BRR4 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR3_Pos (19UL) /*!< BRR3 (Bit 19) */ +#define GPIOx_BSRR_BRR3_Msk (0x80000UL) /*!< BRR3 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR2_Pos (18UL) /*!< BRR2 (Bit 18) */ +#define GPIOx_BSRR_BRR2_Msk (0x40000UL) /*!< BRR2 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR1_Pos (17UL) /*!< BRR1 (Bit 17) */ +#define GPIOx_BSRR_BRR1_Msk (0x20000UL) /*!< BRR1 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR0_Pos (16UL) /*!< BRR0 (Bit 16) */ +#define GPIOx_BSRR_BRR0_Msk (0x10000UL) /*!< BRR0 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS15_Pos (15UL) /*!< BSS15 (Bit 15) */ +#define GPIOx_BSRR_BSS15_Msk (0x8000UL) /*!< BSS15 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS14_Pos (14UL) /*!< BSS14 (Bit 14) */ +#define GPIOx_BSRR_BSS14_Msk (0x4000UL) /*!< BSS14 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS13_Pos (13UL) /*!< BSS13 (Bit 13) */ +#define GPIOx_BSRR_BSS13_Msk (0x2000UL) /*!< BSS13 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS12_Pos (12UL) /*!< BSS12 (Bit 12) */ +#define GPIOx_BSRR_BSS12_Msk (0x1000UL) /*!< BSS12 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS11_Pos (11UL) /*!< BSS11 (Bit 11) */ +#define GPIOx_BSRR_BSS11_Msk (0x800UL) /*!< BSS11 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS10_Pos (10UL) /*!< BSS10 (Bit 10) */ +#define GPIOx_BSRR_BSS10_Msk (0x400UL) /*!< BSS10 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS9_Pos (9UL) /*!< BSS9 (Bit 9) */ +#define GPIOx_BSRR_BSS9_Msk (0x200UL) /*!< BSS9 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS8_Pos (8UL) /*!< BSS8 (Bit 8) */ +#define GPIOx_BSRR_BSS8_Msk (0x100UL) /*!< BSS8 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS7_Pos (7UL) /*!< BSS7 (Bit 7) */ +#define GPIOx_BSRR_BSS7_Msk (0x80UL) /*!< BSS7 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS6_Pos (6UL) /*!< BSS6 (Bit 6) */ +#define GPIOx_BSRR_BSS6_Msk (0x40UL) /*!< BSS6 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS5_Pos (5UL) /*!< BSS5 (Bit 5) */ +#define GPIOx_BSRR_BSS5_Msk (0x20UL) /*!< BSS5 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS4_Pos (4UL) /*!< BSS4 (Bit 4) */ +#define GPIOx_BSRR_BSS4_Msk (0x10UL) /*!< BSS4 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS3_Pos (3UL) /*!< BSS3 (Bit 3) */ +#define GPIOx_BSRR_BSS3_Msk (0x8UL) /*!< BSS3 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS2_Pos (2UL) /*!< BSS2 (Bit 2) */ +#define GPIOx_BSRR_BSS2_Msk (0x4UL) /*!< BSS2 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS1_Pos (1UL) /*!< BSS1 (Bit 1) */ +#define GPIOx_BSRR_BSS1_Msk (0x2UL) /*!< BSS1 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS0_Pos (0UL) /*!< BSS0 (Bit 0) */ +#define GPIOx_BSRR_BSS0_Msk (0x1UL) /*!< BSS0 (Bitfield-Mask: 0x01) */ +/* ========================================================== TOG ========================================================== */ +#define GPIOx_TOG_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_TOG_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_TOG_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_TOG_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_TOG_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_TOG_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_TOG_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_TOG_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_TOG_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_TOG_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_TOG_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_TOG_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_TOG_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_TOG_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_TOG_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_TOG_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_TOG_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GPIOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DIR ========================================================== */ +#define GPIOC_DIR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_DIR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_DIR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_DIR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_DIR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_DIR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ======================================================= OPENDRAIN ======================================================= */ +#define GPIOC_OPENDRAIN_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_OPENDRAIN_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_OPENDRAIN_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_OPENDRAIN_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_OPENDRAIN_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_OPENDRAIN_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================= SPEED ========================================================= */ +#define GPIOC_SPEED_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_SPEED_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_SPEED_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_SPEED_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_SPEED_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_SPEED_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ +#define GPIOC_PDR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_PDR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_PDR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_PDR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_PDR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_PDR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================== PUR ========================================================== */ +#define GPIOC_PUR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_PUR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_PUR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_PUR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_PUR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_PUR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================= AFRH ========================================================== */ +#define GPIOC_AFRH_AFR15_Pos (28UL) /*!< AFR15 (Bit 28) */ +#define GPIOC_AFRH_AFR15_Msk (0xf0000000UL) /*!< AFR15 (Bitfield-Mask: 0x0f) */ +#define GPIOC_AFRH_AFR14_Pos (24UL) /*!< AFR14 (Bit 24) */ +#define GPIOC_AFRH_AFR14_Msk (0xf000000UL) /*!< AFR14 (Bitfield-Mask: 0x0f) */ +#define GPIOC_AFRH_AFR13_Pos (20UL) /*!< AFR13 (Bit 20) */ +#define GPIOC_AFRH_AFR13_Msk (0xf00000UL) /*!< AFR13 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ANALOG ========================================================= */ +#define GPIOC_ANALOG_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_ANALOG_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_ANALOG_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_ANALOG_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_ANALOG_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_ANALOG_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ======================================================== DRIVER ========================================================= */ +#define GPIOC_DRIVER_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_DRIVER_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_DRIVER_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_DRIVER_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_DRIVER_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_DRIVER_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ======================================================== RISEIE ========================================================= */ +#define GPIOC_RISEIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_RISEIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_RISEIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_RISEIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_RISEIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_RISEIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ======================================================== FALLIE ========================================================= */ +#define GPIOC_FALLIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_FALLIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_FALLIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_FALLIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_FALLIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_FALLIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ======================================================== HIGHIE ========================================================= */ +#define GPIOC_HIGHIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_HIGHIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_HIGHIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_HIGHIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_HIGHIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_HIGHIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================= LOWIE ========================================================= */ +#define GPIOC_LOWIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_LOWIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_LOWIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_LOWIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_LOWIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_LOWIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define GPIOC_ISR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_ISR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_ISR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_ISR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_ISR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_ISR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define GPIOC_ICR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_ICR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_ICR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_ICR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_ICR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_ICR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================= LOCK ========================================================== */ +#define GPIOC_LOCK_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define GPIOC_LOCK_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define GPIOC_LOCK_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_LOCK_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_LOCK_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_LOCK_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_LOCK_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_LOCK_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ======================================================== FILTER ========================================================= */ +#define GPIOC_FILTER_FLTCLK_Pos (16UL) /*!< FLTCLK (Bit 16) */ +#define GPIOC_FILTER_FLTCLK_Msk (0x70000UL) /*!< FLTCLK (Bitfield-Mask: 0x07) */ +#define GPIOC_FILTER_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_FILTER_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_FILTER_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_FILTER_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_FILTER_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_FILTER_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================== IDR ========================================================== */ +#define GPIOC_IDR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_IDR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_IDR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_IDR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_IDR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_IDR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ========================================================== ODR ========================================================== */ +#define GPIOC_ODR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_ODR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_ODR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_ODR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_ODR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_ODR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +/* ====================================================== ODRLOWBYTE ======================================================= */ +#define GPIOC_ODRLOWBYTE_LOWBYTE_Pos (0UL) /*!< LOWBYTE (Bit 0) */ +#define GPIOC_ODRLOWBYTE_LOWBYTE_Msk (0xffUL) /*!< LOWBYTE (Bitfield-Mask: 0xff) */ +/* ====================================================== ODRHIGHBYTE ====================================================== */ +#define GPIOC_ODRHIGHBYTE_HIGHBYTE_Pos (0UL) /*!< HIGHBYTE (Bit 0) */ +#define GPIOC_ODRHIGHBYTE_HIGHBYTE_Msk (0xffUL) /*!< HIGHBYTE (Bitfield-Mask: 0xff) */ +/* ========================================================== BRR ========================================================== */ +#define GPIOC_BRR_BRR15_Pos (15UL) /*!< BRR15 (Bit 15) */ +#define GPIOC_BRR_BRR15_Msk (0x8000UL) /*!< BRR15 (Bitfield-Mask: 0x01) */ +#define GPIOC_BRR_BRR14_Pos (14UL) /*!< BRR14 (Bit 14) */ +#define GPIOC_BRR_BRR14_Msk (0x4000UL) /*!< BRR14 (Bitfield-Mask: 0x01) */ +#define GPIOC_BRR_BRR13_Pos (13UL) /*!< BRR13 (Bit 13) */ +#define GPIOC_BRR_BRR13_Msk (0x2000UL) /*!< BRR13 (Bitfield-Mask: 0x01) */ +/* ========================================================= BSRR ========================================================== */ +#define GPIOC_BSRR_BRR15_Pos (31UL) /*!< BRR15 (Bit 31) */ +#define GPIOC_BSRR_BRR15_Msk (0x80000000UL) /*!< BRR15 (Bitfield-Mask: 0x01) */ +#define GPIOC_BSRR_BRR14_Pos (30UL) /*!< BRR14 (Bit 30) */ +#define GPIOC_BSRR_BRR14_Msk (0x40000000UL) /*!< BRR14 (Bitfield-Mask: 0x01) */ +#define GPIOC_BSRR_BRR13_Pos (29UL) /*!< BRR13 (Bit 29) */ +#define GPIOC_BSRR_BRR13_Msk (0x20000000UL) /*!< BRR13 (Bitfield-Mask: 0x01) */ +#define GPIOC_BSRR_BSS15_Pos (15UL) /*!< BSS15 (Bit 15) */ +#define GPIOC_BSRR_BSS15_Msk (0x8000UL) /*!< BSS15 (Bitfield-Mask: 0x01) */ +#define GPIOC_BSRR_BSS14_Pos (14UL) /*!< BSS14 (Bit 14) */ +#define GPIOC_BSRR_BSS14_Msk (0x4000UL) /*!< BSS14 (Bitfield-Mask: 0x01) */ +#define GPIOC_BSRR_BSS13_Pos (13UL) /*!< BSS13 (Bit 13) */ +#define GPIOC_BSRR_BSS13_Msk (0x2000UL) /*!< BSS13 (Bitfield-Mask: 0x01) */ +/* ========================================================== TOG ========================================================== */ +#define GPIOC_TOG_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOC_TOG_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOC_TOG_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOC_TOG_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOC_TOG_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOC_TOG_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GPIOF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DIR ========================================================== */ +#define GPIOF_DIR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_DIR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_DIR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_DIR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_DIR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_DIR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_DIR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_DIR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_DIR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_DIR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================= OPENDRAIN ======================================================= */ +#define GPIOF_OPENDRAIN_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_OPENDRAIN_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_OPENDRAIN_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_OPENDRAIN_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_OPENDRAIN_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_OPENDRAIN_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_OPENDRAIN_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_OPENDRAIN_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_OPENDRAIN_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_OPENDRAIN_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SPEED ========================================================= */ +#define GPIOF_SPEED_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_SPEED_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_SPEED_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_SPEED_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_SPEED_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_SPEED_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_SPEED_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_SPEED_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_SPEED_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_SPEED_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ +#define GPIOF_PDR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_PDR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_PDR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_PDR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_PDR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_PDR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_PDR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_PDR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_PDR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_PDR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== PUR ========================================================== */ +#define GPIOF_PUR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_PUR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_PUR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_PUR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_PUR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_PUR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_PUR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_PUR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_PUR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_PUR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= AFRL ========================================================== */ +#define GPIOF_AFRL_AFR7_Pos (28UL) /*!< AFR7 (Bit 28) */ +#define GPIOF_AFRL_AFR7_Msk (0xf0000000UL) /*!< AFR7 (Bitfield-Mask: 0x0f) */ +#define GPIOF_AFRL_AFR6_Pos (24UL) /*!< AFR6 (Bit 24) */ +#define GPIOF_AFRL_AFR6_Msk (0xf000000UL) /*!< AFR6 (Bitfield-Mask: 0x0f) */ +#define GPIOF_AFRL_AFR3_Pos (12UL) /*!< AFR3 (Bit 12) */ +#define GPIOF_AFRL_AFR3_Msk (0xf000UL) /*!< AFR3 (Bitfield-Mask: 0x0f) */ +#define GPIOF_AFRL_AFR1_Pos (4UL) /*!< AFR1 (Bit 4) */ +#define GPIOF_AFRL_AFR1_Msk (0xf0UL) /*!< AFR1 (Bitfield-Mask: 0x0f) */ +#define GPIOF_AFRL_AFR0_Pos (0UL) /*!< AFR0 (Bit 0) */ +#define GPIOF_AFRL_AFR0_Msk (0xfUL) /*!< AFR0 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ANALOG ========================================================= */ +#define GPIOF_ANALOG_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_ANALOG_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_ANALOG_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_ANALOG_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_ANALOG_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_ANALOG_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_ANALOG_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_ANALOG_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_ANALOG_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_ANALOG_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DRIVER ========================================================= */ +#define GPIOF_DRIVER_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_DRIVER_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_DRIVER_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_DRIVER_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_DRIVER_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_DRIVER_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_DRIVER_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_DRIVER_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_DRIVER_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_DRIVER_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== RISEIE ========================================================= */ +#define GPIOF_RISEIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_RISEIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_RISEIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_RISEIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_RISEIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_RISEIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_RISEIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_RISEIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_RISEIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_RISEIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FALLIE ========================================================= */ +#define GPIOF_FALLIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_FALLIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_FALLIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_FALLIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_FALLIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_FALLIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_FALLIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_FALLIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_FALLIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_FALLIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== HIGHIE ========================================================= */ +#define GPIOF_HIGHIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_HIGHIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_HIGHIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_HIGHIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_HIGHIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_HIGHIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_HIGHIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_HIGHIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_HIGHIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_HIGHIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= LOWIE ========================================================= */ +#define GPIOF_LOWIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_LOWIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_LOWIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_LOWIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_LOWIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_LOWIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_LOWIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_LOWIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_LOWIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_LOWIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define GPIOF_ISR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_ISR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_ISR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_ISR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_ISR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_ISR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_ISR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_ISR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_ISR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_ISR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define GPIOF_ICR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_ICR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_ICR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_ICR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_ICR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_ICR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_ICR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_ICR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_ICR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_ICR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= LOCK ========================================================== */ +#define GPIOF_LOCK_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define GPIOF_LOCK_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define GPIOF_LOCK_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_LOCK_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_LOCK_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_LOCK_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_LOCK_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_LOCK_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_LOCK_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_LOCK_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_LOCK_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_LOCK_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FILTER ========================================================= */ +#define GPIOF_FILTER_FLTCLK_Pos (16UL) /*!< FLTCLK (Bit 16) */ +#define GPIOF_FILTER_FLTCLK_Msk (0x70000UL) /*!< FLTCLK (Bitfield-Mask: 0x07) */ +#define GPIOF_FILTER_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_FILTER_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_FILTER_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_FILTER_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_FILTER_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_FILTER_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_FILTER_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_FILTER_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_FILTER_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_FILTER_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== IDR ========================================================== */ +#define GPIOF_IDR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_IDR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_IDR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_IDR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_IDR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_IDR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_IDR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_IDR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_IDR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_IDR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ODR ========================================================== */ +#define GPIOF_ODR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_ODR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_ODR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_ODR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_ODR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_ODR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_ODR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_ODR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_ODR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_ODR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ====================================================== ODRLOWBYTE ======================================================= */ +#define GPIOF_ODRLOWBYTE_LOWBYTE_Pos (0UL) /*!< LOWBYTE (Bit 0) */ +#define GPIOF_ODRLOWBYTE_LOWBYTE_Msk (0xffUL) /*!< LOWBYTE (Bitfield-Mask: 0xff) */ +/* ========================================================== BRR ========================================================== */ +#define GPIOF_BRR_BRR7_Pos (7UL) /*!< BRR7 (Bit 7) */ +#define GPIOF_BRR_BRR7_Msk (0x80UL) /*!< BRR7 (Bitfield-Mask: 0x01) */ +#define GPIOF_BRR_BRR6_Pos (6UL) /*!< BRR6 (Bit 6) */ +#define GPIOF_BRR_BRR6_Msk (0x40UL) /*!< BRR6 (Bitfield-Mask: 0x01) */ +#define GPIOF_BRR_BRR3_Pos (3UL) /*!< BRR3 (Bit 3) */ +#define GPIOF_BRR_BRR3_Msk (0x8UL) /*!< BRR3 (Bitfield-Mask: 0x01) */ +#define GPIOF_BRR_BRR1_Pos (1UL) /*!< BRR1 (Bit 1) */ +#define GPIOF_BRR_BRR1_Msk (0x2UL) /*!< BRR1 (Bitfield-Mask: 0x01) */ +#define GPIOF_BRR_BRR0_Pos (0UL) /*!< BRR0 (Bit 0) */ +#define GPIOF_BRR_BRR0_Msk (0x1UL) /*!< BRR0 (Bitfield-Mask: 0x01) */ +/* ========================================================= BSRR ========================================================== */ +#define GPIOF_BSRR_BSS7_Pos (7UL) /*!< BSS7 (Bit 7) */ +#define GPIOF_BSRR_BSS7_Msk (0x80UL) /*!< BSS7 (Bitfield-Mask: 0x01) */ +#define GPIOF_BSRR_BSS6_Pos (6UL) /*!< BSS6 (Bit 6) */ +#define GPIOF_BSRR_BSS6_Msk (0x40UL) /*!< BSS6 (Bitfield-Mask: 0x01) */ +#define GPIOF_BSRR_BSS3_Pos (3UL) /*!< BSS3 (Bit 3) */ +#define GPIOF_BSRR_BSS3_Msk (0x8UL) /*!< BSS3 (Bitfield-Mask: 0x01) */ +#define GPIOF_BSRR_BSS1_Pos (1UL) /*!< BSS1 (Bit 1) */ +#define GPIOF_BSRR_BSS1_Msk (0x2UL) /*!< BSS1 (Bitfield-Mask: 0x01) */ +#define GPIOF_BSRR_BSS0_Pos (0UL) /*!< BSS0 (Bit 0) */ +#define GPIOF_BSRR_BSS0_Msk (0x1UL) /*!< BSS0 (Bitfield-Mask: 0x01) */ +/* ========================================================== TOG ========================================================== */ +#define GPIOF_TOG_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOF_TOG_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOF_TOG_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOF_TOG_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOF_TOG_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOF_TOG_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOF_TOG_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOF_TOG_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOF_TOG_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOF_TOG_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GTIM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ARR ========================================================== */ +#define GTIMx_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define GTIMx_ARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ========================================================== CNT ========================================================== */ +#define GTIMx_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define GTIMx_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================= CMMR ========================================================== */ +#define GTIMx_CMMR_CC4M_Pos (12UL) /*!< CC4M (Bit 12) */ +#define GTIMx_CMMR_CC4M_Msk (0xf000UL) /*!< CC4M (Bitfield-Mask: 0x0f) */ +#define GTIMx_CMMR_CC3M_Pos (8UL) /*!< CC3M (Bit 8) */ +#define GTIMx_CMMR_CC3M_Msk (0xf00UL) /*!< CC3M (Bitfield-Mask: 0x0f) */ +#define GTIMx_CMMR_CC2M_Pos (4UL) /*!< CC2M (Bit 4) */ +#define GTIMx_CMMR_CC2M_Msk (0xf0UL) /*!< CC2M (Bitfield-Mask: 0x0f) */ +#define GTIMx_CMMR_CC1M_Pos (0UL) /*!< CC1M (Bit 0) */ +#define GTIMx_CMMR_CC1M_Msk (0xfUL) /*!< CC1M (Bitfield-Mask: 0x0f) */ +/* ========================================================== ETR ========================================================== */ +#define GTIMx_ETR_ETRFLT_Pos (4UL) /*!< ETRFLT (Bit 4) */ +#define GTIMx_ETR_ETRFLT_Msk (0x70UL) /*!< ETRFLT (Bitfield-Mask: 0x07) */ +/* ========================================================== CR0 ========================================================== */ +#define GTIMx_CR0_ENCRELOAD_Pos (19UL) /*!< ENCRELOAD (Bit 19) */ +#define GTIMx_CR0_ENCRELOAD_Msk (0x180000UL) /*!< ENCRELOAD (Bitfield-Mask: 0x03) */ +#define GTIMx_CR0_ENCRESET_Pos (17UL) /*!< ENCRESET (Bit 17) */ +#define GTIMx_CR0_ENCRESET_Msk (0x60000UL) /*!< ENCRESET (Bitfield-Mask: 0x03) */ +#define GTIMx_CR0_ENCMODE_Pos (15UL) /*!< ENCMODE (Bit 15) */ +#define GTIMx_CR0_ENCMODE_Msk (0x18000UL) /*!< ENCMODE (Bitfield-Mask: 0x03) */ +#define GTIMx_CR0_PRSSTATUS_Pos (11UL) /*!< PRSSTATUS (Bit 11) */ +#define GTIMx_CR0_PRSSTATUS_Msk (0x7800UL) /*!< PRSSTATUS (Bitfield-Mask: 0x0f) */ +#define GTIMx_CR0_PRS_Pos (7UL) /*!< PRS (Bit 7) */ +#define GTIMx_CR0_PRS_Msk (0x780UL) /*!< PRS (Bitfield-Mask: 0x0f) */ +#define GTIMx_CR0_TOGEN_Pos (6UL) /*!< TOGEN (Bit 6) */ +#define GTIMx_CR0_TOGEN_Msk (0x40UL) /*!< TOGEN (Bitfield-Mask: 0x01) */ +#define GTIMx_CR0_ONESHOT_Pos (5UL) /*!< ONESHOT (Bit 5) */ +#define GTIMx_CR0_ONESHOT_Msk (0x20UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ +#define GTIMx_CR0_POL_Pos (4UL) /*!< POL (Bit 4) */ +#define GTIMx_CR0_POL_Msk (0x10UL) /*!< POL (Bitfield-Mask: 0x01) */ +#define GTIMx_CR0_TRS_Pos (3UL) /*!< TRS (Bit 3) */ +#define GTIMx_CR0_TRS_Msk (0x8UL) /*!< TRS (Bitfield-Mask: 0x01) */ +#define GTIMx_CR0_MODE_Pos (1UL) /*!< MODE (Bit 1) */ +#define GTIMx_CR0_MODE_Msk (0x6UL) /*!< MODE (Bitfield-Mask: 0x03) */ +#define GTIMx_CR0_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define GTIMx_CR0_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define GTIMx_IER_DIRCHANGE_Pos (9UL) /*!< DIRCHANGE (Bit 9) */ +#define GTIMx_IER_DIRCHANGE_Msk (0x200UL) /*!< DIRCHANGE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC4_Pos (6UL) /*!< CC4 (Bit 6) */ +#define GTIMx_IER_CC4_Msk (0x40UL) /*!< CC4 (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC3_Pos (5UL) /*!< CC3 (Bit 5) */ +#define GTIMx_IER_CC3_Msk (0x20UL) /*!< CC3 (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC2_Pos (4UL) /*!< CC2 (Bit 4) */ +#define GTIMx_IER_CC2_Msk (0x10UL) /*!< CC2 (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC1_Pos (3UL) /*!< CC1 (Bit 3) */ +#define GTIMx_IER_CC1_Msk (0x8UL) /*!< CC1 (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_UD_Pos (2UL) /*!< UD (Bit 2) */ +#define GTIMx_IER_UD_Msk (0x4UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_TI_Pos (1UL) /*!< TI (Bit 1) */ +#define GTIMx_IER_TI_Msk (0x2UL) /*!< TI (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_OV_Pos (0UL) /*!< OV (Bit 0) */ +#define GTIMx_IER_OV_Msk (0x1UL) /*!< OV (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define GTIMx_ISR_DIR_Pos (10UL) /*!< DIR (Bit 10) */ +#define GTIMx_ISR_DIR_Msk (0x400UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_DIRCHANGE_Pos (9UL) /*!< DIRCHANGE (Bit 9) */ +#define GTIMx_ISR_DIRCHANGE_Msk (0x200UL) /*!< DIRCHANGE (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC4_Pos (6UL) /*!< CC4 (Bit 6) */ +#define GTIMx_ISR_CC4_Msk (0x40UL) /*!< CC4 (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC3_Pos (5UL) /*!< CC3 (Bit 5) */ +#define GTIMx_ISR_CC3_Msk (0x20UL) /*!< CC3 (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC2_Pos (4UL) /*!< CC2 (Bit 4) */ +#define GTIMx_ISR_CC2_Msk (0x10UL) /*!< CC2 (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC1_Pos (3UL) /*!< CC1 (Bit 3) */ +#define GTIMx_ISR_CC1_Msk (0x8UL) /*!< CC1 (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_UD_Pos (2UL) /*!< UD (Bit 2) */ +#define GTIMx_ISR_UD_Msk (0x4UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_TI_Pos (1UL) /*!< TI (Bit 1) */ +#define GTIMx_ISR_TI_Msk (0x2UL) /*!< TI (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_OV_Pos (0UL) /*!< OV (Bit 0) */ +#define GTIMx_ISR_OV_Msk (0x1UL) /*!< OV (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define GTIMx_ICR_DIRCHANGE_Pos (9UL) /*!< DIRCHANGE (Bit 9) */ +#define GTIMx_ICR_DIRCHANGE_Msk (0x200UL) /*!< DIRCHANGE (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC4_Pos (6UL) /*!< CC4 (Bit 6) */ +#define GTIMx_ICR_CC4_Msk (0x40UL) /*!< CC4 (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC3_Pos (5UL) /*!< CC3 (Bit 5) */ +#define GTIMx_ICR_CC3_Msk (0x20UL) /*!< CC3 (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC2_Pos (4UL) /*!< CC2 (Bit 4) */ +#define GTIMx_ICR_CC2_Msk (0x10UL) /*!< CC2 (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC1_Pos (3UL) /*!< CC1 (Bit 3) */ +#define GTIMx_ICR_CC1_Msk (0x8UL) /*!< CC1 (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_UD_Pos (2UL) /*!< UD (Bit 2) */ +#define GTIMx_ICR_UD_Msk (0x4UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_TI_Pos (1UL) /*!< TI (Bit 1) */ +#define GTIMx_ICR_TI_Msk (0x2UL) /*!< TI (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_OV_Pos (0UL) /*!< OV (Bit 0) */ +#define GTIMx_ICR_OV_Msk (0x1UL) /*!< OV (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR1 ========================================================== */ +#define GTIMx_CCR1_CCR_Pos (0UL) /*!< CCR (Bit 0) */ +#define GTIMx_CCR1_CCR_Msk (0xffffUL) /*!< CCR (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR2 ========================================================== */ +#define GTIMx_CCR2_CCR_Pos (0UL) /*!< CCR (Bit 0) */ +#define GTIMx_CCR2_CCR_Msk (0xffffUL) /*!< CCR (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR3 ========================================================== */ +#define GTIMx_CCR3_CCR_Pos (0UL) /*!< CCR (Bit 0) */ +#define GTIMx_CCR3_CCR_Msk (0xffffUL) /*!< CCR (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR4 ========================================================== */ +#define GTIMx_CCR4_CCR_Pos (0UL) /*!< CCR (Bit 0) */ +#define GTIMx_CCR4_CCR_Msk (0xffffUL) /*!< CCR (Bitfield-Mask: 0xffff) */ +/* ========================================================== CR1 ========================================================== */ +#define GTIMx_CR1_CH4POL_Pos (15UL) /*!< CH4POL (Bit 15) */ +#define GTIMx_CR1_CH4POL_Msk (0x8000UL) /*!< CH4POL (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_CH4FLT_Pos (12UL) /*!< CH4FLT (Bit 12) */ +#define GTIMx_CR1_CH4FLT_Msk (0x7000UL) /*!< CH4FLT (Bitfield-Mask: 0x07) */ +#define GTIMx_CR1_CH3POL_Pos (11UL) /*!< CH3POL (Bit 11) */ +#define GTIMx_CR1_CH3POL_Msk (0x800UL) /*!< CH3POL (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_CH3FLT_Pos (8UL) /*!< CH3FLT (Bit 8) */ +#define GTIMx_CR1_CH3FLT_Msk (0x700UL) /*!< CH3FLT (Bitfield-Mask: 0x07) */ +#define GTIMx_CR1_CH2POL_Pos (7UL) /*!< CH2POL (Bit 7) */ +#define GTIMx_CR1_CH2POL_Msk (0x80UL) /*!< CH2POL (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_CH2FLT_Pos (4UL) /*!< CH2FLT (Bit 4) */ +#define GTIMx_CR1_CH2FLT_Msk (0x70UL) /*!< CH2FLT (Bitfield-Mask: 0x07) */ +#define GTIMx_CR1_CH1POL_Pos (3UL) /*!< CH1POL (Bit 3) */ +#define GTIMx_CR1_CH1POL_Msk (0x8UL) /*!< CH1POL (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_CH1FLT_Pos (0UL) /*!< CH1FLT (Bit 0) */ +#define GTIMx_CR1_CH1FLT_Msk (0x7UL) /*!< CH1FLT (Bitfield-Mask: 0x07) */ +/* ========================================================== DMA ========================================================== */ +#define GTIMx_DMA_CC4_Pos (5UL) /*!< CC4 (Bit 5) */ +#define GTIMx_DMA_CC4_Msk (0x20UL) /*!< CC4 (Bitfield-Mask: 0x01) */ +#define GTIMx_DMA_CC3_Pos (4UL) /*!< CC3 (Bit 4) */ +#define GTIMx_DMA_CC3_Msk (0x10UL) /*!< CC3 (Bitfield-Mask: 0x01) */ +#define GTIMx_DMA_CC2_Pos (3UL) /*!< CC2 (Bit 3) */ +#define GTIMx_DMA_CC2_Msk (0x8UL) /*!< CC2 (Bitfield-Mask: 0x01) */ +#define GTIMx_DMA_CC1_Pos (2UL) /*!< CC1 (Bit 2) */ +#define GTIMx_DMA_CC1_Msk (0x4UL) /*!< CC1 (Bitfield-Mask: 0x01) */ +#define GTIMx_DMA_TRS_Pos (1UL) /*!< TRS (Bit 1) */ +#define GTIMx_DMA_TRS_Msk (0x2UL) /*!< TRS (Bitfield-Mask: 0x01) */ +#define GTIMx_DMA_OV_Pos (0UL) /*!< OV (Bit 0) */ +#define GTIMx_DMA_OV_Msk (0x1UL) /*!< OV (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ I2C ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= BRREN ========================================================= */ +#define I2Cx_BRREN_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define I2Cx_BRREN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== BRR ========================================================== */ +#define I2Cx_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ +#define I2Cx_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== CR =========================================================== */ +#define I2Cx_CR_EN_Pos (6UL) /*!< EN (Bit 6) */ +#define I2Cx_CR_EN_Msk (0x40UL) /*!< EN (Bitfield-Mask: 0x01) */ +#define I2Cx_CR_STA_Pos (5UL) /*!< STA (Bit 5) */ +#define I2Cx_CR_STA_Msk (0x20UL) /*!< STA (Bitfield-Mask: 0x01) */ +#define I2Cx_CR_STO_Pos (4UL) /*!< STO (Bit 4) */ +#define I2Cx_CR_STO_Msk (0x10UL) /*!< STO (Bitfield-Mask: 0x01) */ +#define I2Cx_CR_SI_Pos (3UL) /*!< SI (Bit 3) */ +#define I2Cx_CR_SI_Msk (0x8UL) /*!< SI (Bitfield-Mask: 0x01) */ +#define I2Cx_CR_AA_Pos (2UL) /*!< AA (Bit 2) */ +#define I2Cx_CR_AA_Msk (0x4UL) /*!< AA (Bitfield-Mask: 0x01) */ +#define I2Cx_CR_FLT_Pos (0UL) /*!< FLT (Bit 0) */ +#define I2Cx_CR_FLT_Msk (0x1UL) /*!< FLT (Bitfield-Mask: 0x01) */ +/* ========================================================== DR =========================================================== */ +#define I2Cx_DR_DR_Pos (0UL) /*!< DR (Bit 0) */ +#define I2Cx_DR_DR_Msk (0xffUL) /*!< DR (Bitfield-Mask: 0xff) */ +/* ========================================================= ADDR0 ========================================================= */ +#define I2Cx_ADDR0_ADDR0_Pos (1UL) /*!< ADDR0 (Bit 1) */ +#define I2Cx_ADDR0_ADDR0_Msk (0xfeUL) /*!< ADDR0 (Bitfield-Mask: 0x7f) */ +#define I2Cx_ADDR0_GC_Pos (0UL) /*!< GC (Bit 0) */ +#define I2Cx_ADDR0_GC_Msk (0x1UL) /*!< GC (Bitfield-Mask: 0x01) */ +/* ========================================================= STAT ========================================================== */ +#define I2Cx_STAT_STAT_Pos (0UL) /*!< STAT (Bit 0) */ +#define I2Cx_STAT_STAT_Msk (0xffUL) /*!< STAT (Bitfield-Mask: 0xff) */ +/* ========================================================= ADDR1 ========================================================= */ +#define I2Cx_ADDR1_ADDR1_Pos (1UL) /*!< ADDR1 (Bit 1) */ +#define I2Cx_ADDR1_ADDR1_Msk (0xfeUL) /*!< ADDR1 (Bitfield-Mask: 0x7f) */ +/* ========================================================= ADDR2 ========================================================= */ +#define I2Cx_ADDR2_ADDR2_Pos (1UL) /*!< ADDR2 (Bit 1) */ +#define I2Cx_ADDR2_ADDR2_Msk (0xfeUL) /*!< ADDR2 (Bitfield-Mask: 0x7f) */ +/* ========================================================= MATCH ========================================================= */ +#define I2Cx_MATCH_ADDR2_Pos (2UL) /*!< ADDR2 (Bit 2) */ +#define I2Cx_MATCH_ADDR2_Msk (0x4UL) /*!< ADDR2 (Bitfield-Mask: 0x01) */ +#define I2Cx_MATCH_ADDR1_Pos (1UL) /*!< ADDR1 (Bit 1) */ +#define I2Cx_MATCH_ADDR1_Msk (0x2UL) /*!< ADDR1 (Bitfield-Mask: 0x01) */ +#define I2Cx_MATCH_ADDR0_Pos (0UL) /*!< ADDR0 (Bit 0) */ +#define I2Cx_MATCH_ADDR0_Msk (0x1UL) /*!< ADDR0 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ IWDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== KR =========================================================== */ +#define IWDT_KR_KR_Pos (0UL) /*!< KR (Bit 0) */ +#define IWDT_KR_KR_Msk (0xffffUL) /*!< KR (Bitfield-Mask: 0xffff) */ +/* ========================================================== CR =========================================================== */ +#define IWDT_CR_PAUSE_Pos (5UL) /*!< PAUSE (Bit 5) */ +#define IWDT_CR_PAUSE_Msk (0x20UL) /*!< PAUSE (Bitfield-Mask: 0x01) */ +#define IWDT_CR_IE_Pos (4UL) /*!< IE (Bit 4) */ +#define IWDT_CR_IE_Msk (0x10UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define IWDT_CR_ACTION_Pos (3UL) /*!< ACTION (Bit 3) */ +#define IWDT_CR_ACTION_Msk (0x8UL) /*!< ACTION (Bitfield-Mask: 0x01) */ +#define IWDT_CR_PRS_Pos (0UL) /*!< PRS (Bit 0) */ +#define IWDT_CR_PRS_Msk (0x7UL) /*!< PRS (Bitfield-Mask: 0x07) */ +/* ========================================================== ARR ========================================================== */ +#define IWDT_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define IWDT_ARR_ARR_Msk (0xfffUL) /*!< ARR (Bitfield-Mask: 0xfff) */ +/* ========================================================== SR =========================================================== */ +#define IWDT_SR_RELOAD_Pos (5UL) /*!< RELOAD (Bit 5) */ +#define IWDT_SR_RELOAD_Msk (0x20UL) /*!< RELOAD (Bitfield-Mask: 0x01) */ +#define IWDT_SR_RUN_Pos (4UL) /*!< RUN (Bit 4) */ +#define IWDT_SR_RUN_Msk (0x10UL) /*!< RUN (Bitfield-Mask: 0x01) */ +#define IWDT_SR_OV_Pos (3UL) /*!< OV (Bit 3) */ +#define IWDT_SR_OV_Msk (0x8UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define IWDT_SR_WINRF_Pos (2UL) /*!< WINRF (Bit 2) */ +#define IWDT_SR_WINRF_Msk (0x4UL) /*!< WINRF (Bitfield-Mask: 0x01) */ +#define IWDT_SR_ARRF_Pos (1UL) /*!< ARRF (Bit 1) */ +#define IWDT_SR_ARRF_Msk (0x2UL) /*!< ARRF (Bitfield-Mask: 0x01) */ +#define IWDT_SR_CRF_Pos (0UL) /*!< CRF (Bit 0) */ +#define IWDT_SR_CRF_Msk (0x1UL) /*!< CRF (Bitfield-Mask: 0x01) */ +/* ========================================================= WINR ========================================================== */ +#define IWDT_WINR_WINR_Pos (0UL) /*!< WINR (Bit 0) */ +#define IWDT_WINR_WINR_Msk (0xfffUL) /*!< WINR (Bitfield-Mask: 0xfff) */ +/* ========================================================== CNT ========================================================== */ +#define IWDT_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define IWDT_CNT_CNT_Msk (0xfffUL) /*!< CNT (Bitfield-Mask: 0xfff) */ + + +/* =========================================================================================================================== */ +/* ================ LVD ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define LVD_CR0_IE_Pos (9UL) /*!< IE (Bit 9) */ +#define LVD_CR0_IE_Msk (0x200UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define LVD_CR0_VTH_Pos (4UL) /*!< VTH (Bit 4) */ +#define LVD_CR0_VTH_Msk (0xf0UL) /*!< VTH (Bitfield-Mask: 0x0f) */ +#define LVD_CR0_SOURCE_Pos (2UL) /*!< SOURCE (Bit 2) */ +#define LVD_CR0_SOURCE_Msk (0xcUL) /*!< SOURCE (Bitfield-Mask: 0x03) */ +#define LVD_CR0_ACTION_Pos (1UL) /*!< ACTION (Bit 1) */ +#define LVD_CR0_ACTION_Msk (0x2UL) /*!< ACTION (Bitfield-Mask: 0x01) */ +#define LVD_CR0_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define LVD_CR0_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ +#define LVD_CR1_LEVEL_Pos (7UL) /*!< LEVEL (Bit 7) */ +#define LVD_CR1_LEVEL_Msk (0x80UL) /*!< LEVEL (Bitfield-Mask: 0x01) */ +#define LVD_CR1_FALL_Pos (6UL) /*!< FALL (Bit 6) */ +#define LVD_CR1_FALL_Msk (0x40UL) /*!< FALL (Bitfield-Mask: 0x01) */ +#define LVD_CR1_RISE_Pos (5UL) /*!< RISE (Bit 5) */ +#define LVD_CR1_RISE_Msk (0x20UL) /*!< RISE (Bitfield-Mask: 0x01) */ +#define LVD_CR1_FLTCLK_Pos (4UL) /*!< FLTCLK (Bit 4) */ +#define LVD_CR1_FLTCLK_Msk (0x10UL) /*!< FLTCLK (Bitfield-Mask: 0x01) */ +#define LVD_CR1_FLTTIME_Pos (1UL) /*!< FLTTIME (Bit 1) */ +#define LVD_CR1_FLTTIME_Msk (0xeUL) /*!< FLTTIME (Bitfield-Mask: 0x07) */ +#define LVD_CR1_FLTEN_Pos (0UL) /*!< FLTEN (Bit 0) */ +#define LVD_CR1_FLTEN_Msk (0x1UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ +/* ========================================================== SR =========================================================== */ +#define LVD_SR_FLTV_Pos (1UL) /*!< FLTV (Bit 1) */ +#define LVD_SR_FLTV_Msk (0x2UL) /*!< FLTV (Bitfield-Mask: 0x01) */ +#define LVD_SR_INTF_Pos (0UL) /*!< INTF (Bit 0) */ +#define LVD_SR_INTF_Msk (0x1UL) /*!< INTF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ RAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== IER ========================================================== */ +#define RAM_IER_PARITY_Pos (1UL) /*!< PARITY (Bit 1) */ +#define RAM_IER_PARITY_Msk (0x2UL) /*!< PARITY (Bitfield-Mask: 0x01) */ +#define RAM_IER_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define RAM_IER_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADDR ========================================================== */ +#define RAM_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define RAM_ADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== ISR ========================================================== */ +#define RAM_ISR_PARITY_Pos (0UL) /*!< PARITY (Bit 0) */ +#define RAM_ISR_PARITY_Msk (0x1UL) /*!< PARITY (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define RAM_ICR_PARITY_Pos (0UL) /*!< PARITY (Bit 0) */ +#define RAM_ICR_PARITY_Msk (0x1UL) /*!< PARITY (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== KEY ========================================================== */ +#define RTC_KEY_KEY_Pos (0UL) /*!< KEY (Bit 0) */ +#define RTC_KEY_KEY_Msk (0xffUL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================== CR0 ========================================================== */ +#define RTC_CR0_START_Pos (7UL) /*!< START (Bit 7) */ +#define RTC_CR0_START_Msk (0x80UL) /*!< START (Bitfield-Mask: 0x01) */ +#define RTC_CR0_RTC1HZ_Pos (5UL) /*!< RTC1HZ (Bit 5) */ +#define RTC_CR0_RTC1HZ_Msk (0x60UL) /*!< RTC1HZ (Bitfield-Mask: 0x03) */ +#define RTC_CR0_H24_Pos (3UL) /*!< H24 (Bit 3) */ +#define RTC_CR0_H24_Msk (0x8UL) /*!< H24 (Bitfield-Mask: 0x01) */ +#define RTC_CR0_INTERVAL_Pos (0UL) /*!< INTERVAL (Bit 0) */ +#define RTC_CR0_INTERVAL_Msk (0x7UL) /*!< INTERVAL (Bitfield-Mask: 0x07) */ +/* ========================================================== CR1 ========================================================== */ +#define RTC_CR1_SOURCE_Pos (8UL) /*!< SOURCE (Bit 8) */ +#define RTC_CR1_SOURCE_Msk (0x700UL) /*!< SOURCE (Bitfield-Mask: 0x07) */ +#define RTC_CR1_WINDOW_Pos (1UL) /*!< WINDOW (Bit 1) */ +#define RTC_CR1_WINDOW_Msk (0x2UL) /*!< WINDOW (Bitfield-Mask: 0x01) */ +#define RTC_CR1_ACCESS_Pos (0UL) /*!< ACCESS (Bit 0) */ +#define RTC_CR1_ACCESS_Msk (0x1UL) /*!< ACCESS (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define RTC_CR2_ALARMBEN_Pos (10UL) /*!< ALARMBEN (Bit 10) */ +#define RTC_CR2_ALARMBEN_Msk (0x400UL) /*!< ALARMBEN (Bitfield-Mask: 0x01) */ +#define RTC_CR2_ALARMAEN_Pos (9UL) /*!< ALARMAEN (Bit 9) */ +#define RTC_CR2_ALARMAEN_Msk (0x200UL) /*!< ALARMAEN (Bitfield-Mask: 0x01) */ +#define RTC_CR2_AWTEN_Pos (7UL) /*!< AWTEN (Bit 7) */ +#define RTC_CR2_AWTEN_Msk (0x80UL) /*!< AWTEN (Bitfield-Mask: 0x01) */ +#define RTC_CR2_TAMPEN_Pos (6UL) /*!< TAMPEN (Bit 6) */ +#define RTC_CR2_TAMPEN_Msk (0x40UL) /*!< TAMPEN (Bitfield-Mask: 0x01) */ +#define RTC_CR2_RTCOUT_Pos (4UL) /*!< RTCOUT (Bit 4) */ +#define RTC_CR2_RTCOUT_Msk (0x30UL) /*!< RTCOUT (Bitfield-Mask: 0x03) */ +#define RTC_CR2_TAMPEDGE_Pos (3UL) /*!< TAMPEDGE (Bit 3) */ +#define RTC_CR2_TAMPEDGE_Msk (0x8UL) /*!< TAMPEDGE (Bitfield-Mask: 0x01) */ +#define RTC_CR2_AWTSRC_Pos (0UL) /*!< AWTSRC (Bit 0) */ +#define RTC_CR2_AWTSRC_Msk (0x7UL) /*!< AWTSRC (Bitfield-Mask: 0x07) */ +/* ======================================================== COMPEN ========================================================= */ +#define RTC_COMPEN_FREQ_Pos (16UL) /*!< FREQ (Bit 16) */ +#define RTC_COMPEN_FREQ_Msk (0xf0000UL) /*!< FREQ (Bitfield-Mask: 0x0f) */ +#define RTC_COMPEN_EN_Pos (15UL) /*!< EN (Bit 15) */ +#define RTC_COMPEN_EN_Msk (0x8000UL) /*!< EN (Bitfield-Mask: 0x01) */ +#define RTC_COMPEN_SIGN_Pos (14UL) /*!< SIGN (Bit 14) */ +#define RTC_COMPEN_SIGN_Msk (0x4000UL) /*!< SIGN (Bitfield-Mask: 0x01) */ +#define RTC_COMPEN_STEP_Pos (12UL) /*!< STEP (Bit 12) */ +#define RTC_COMPEN_STEP_Msk (0x3000UL) /*!< STEP (Bitfield-Mask: 0x03) */ +#define RTC_COMPEN_COMP_Pos (0UL) /*!< COMP (Bit 0) */ +#define RTC_COMPEN_COMP_Msk (0xfffUL) /*!< COMP (Bitfield-Mask: 0xfff) */ +/* ========================================================= DATE ========================================================== */ +#define RTC_DATE_WEEK_Pos (24UL) /*!< WEEK (Bit 24) */ +#define RTC_DATE_WEEK_Msk (0x7000000UL) /*!< WEEK (Bitfield-Mask: 0x07) */ +#define RTC_DATE_YEAR_Pos (16UL) /*!< YEAR (Bit 16) */ +#define RTC_DATE_YEAR_Msk (0xff0000UL) /*!< YEAR (Bitfield-Mask: 0xff) */ +#define RTC_DATE_MONTH_Pos (8UL) /*!< MONTH (Bit 8) */ +#define RTC_DATE_MONTH_Msk (0xff00UL) /*!< MONTH (Bitfield-Mask: 0xff) */ +#define RTC_DATE_DAY_Pos (0UL) /*!< DAY (Bit 0) */ +#define RTC_DATE_DAY_Msk (0xffUL) /*!< DAY (Bitfield-Mask: 0xff) */ +/* ========================================================= TIME ========================================================== */ +#define RTC_TIME_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */ +#define RTC_TIME_HOUR_Msk (0x3f0000UL) /*!< HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_TIME_MINUTE_Pos (8UL) /*!< MINUTE (Bit 8) */ +#define RTC_TIME_MINUTE_Msk (0x7f00UL) /*!< MINUTE (Bitfield-Mask: 0x7f) */ +#define RTC_TIME_SECOND_Pos (0UL) /*!< SECOND (Bit 0) */ +#define RTC_TIME_SECOND_Msk (0x7fUL) /*!< SECOND (Bitfield-Mask: 0x7f) */ +/* ======================================================== ALARMA ========================================================= */ +#define RTC_ALARMA_WEEK_Pos (24UL) /*!< WEEK (Bit 24) */ +#define RTC_ALARMA_WEEK_Msk (0x7f000000UL) /*!< WEEK (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMA_HOURMASK_Pos (23UL) /*!< HOURMASK (Bit 23) */ +#define RTC_ALARMA_HOURMASK_Msk (0x800000UL) /*!< HOURMASK (Bitfield-Mask: 0x01) */ +#define RTC_ALARMA_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */ +#define RTC_ALARMA_HOUR_Msk (0x3f0000UL) /*!< HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_ALARMA_MINUTEMASK_Pos (15UL) /*!< MINUTEMASK (Bit 15) */ +#define RTC_ALARMA_MINUTEMASK_Msk (0x8000UL) /*!< MINUTEMASK (Bitfield-Mask: 0x01) */ +#define RTC_ALARMA_MINUTE_Pos (8UL) /*!< MINUTE (Bit 8) */ +#define RTC_ALARMA_MINUTE_Msk (0x7f00UL) /*!< MINUTE (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMA_SECONDMASK_Pos (7UL) /*!< SECONDMASK (Bit 7) */ +#define RTC_ALARMA_SECONDMASK_Msk (0x80UL) /*!< SECONDMASK (Bitfield-Mask: 0x01) */ +#define RTC_ALARMA_SECOND_Pos (0UL) /*!< SECOND (Bit 0) */ +#define RTC_ALARMA_SECOND_Msk (0x7fUL) /*!< SECOND (Bitfield-Mask: 0x7f) */ +/* ======================================================== ALARMB ========================================================= */ +#define RTC_ALARMB_WEEK_Pos (24UL) /*!< WEEK (Bit 24) */ +#define RTC_ALARMB_WEEK_Msk (0x7f000000UL) /*!< WEEK (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMB_HOURMASK_Pos (23UL) /*!< HOURMASK (Bit 23) */ +#define RTC_ALARMB_HOURMASK_Msk (0x800000UL) /*!< HOURMASK (Bitfield-Mask: 0x01) */ +#define RTC_ALARMB_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */ +#define RTC_ALARMB_HOUR_Msk (0x3f0000UL) /*!< HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_ALARMB_MINUTEMASK_Pos (15UL) /*!< MINUTEMASK (Bit 15) */ +#define RTC_ALARMB_MINUTEMASK_Msk (0x8000UL) /*!< MINUTEMASK (Bitfield-Mask: 0x01) */ +#define RTC_ALARMB_MINUTE_Pos (8UL) /*!< MINUTE (Bit 8) */ +#define RTC_ALARMB_MINUTE_Msk (0x7f00UL) /*!< MINUTE (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMB_SECONDMASK_Pos (7UL) /*!< SECONDMASK (Bit 7) */ +#define RTC_ALARMB_SECONDMASK_Msk (0x80UL) /*!< SECONDMASK (Bitfield-Mask: 0x01) */ +#define RTC_ALARMB_SECOND_Pos (0UL) /*!< SECOND (Bit 0) */ +#define RTC_ALARMB_SECOND_Msk (0x7fUL) /*!< SECOND (Bitfield-Mask: 0x7f) */ +/* ======================================================= TAMPDATE ======================================================== */ +#define RTC_TAMPDATE_WEEK_Pos (13UL) /*!< WEEK (Bit 13) */ +#define RTC_TAMPDATE_WEEK_Msk (0xe000UL) /*!< WEEK (Bitfield-Mask: 0x07) */ +#define RTC_TAMPDATE_MONTH_Pos (8UL) /*!< MONTH (Bit 8) */ +#define RTC_TAMPDATE_MONTH_Msk (0x1f00UL) /*!< MONTH (Bitfield-Mask: 0x1f) */ +#define RTC_TAMPDATE_DAY_Pos (0UL) /*!< DAY (Bit 0) */ +#define RTC_TAMPDATE_DAY_Msk (0x3fUL) /*!< DAY (Bitfield-Mask: 0x3f) */ +/* ======================================================= TAMPTIME ======================================================== */ +#define RTC_TAMPTIME_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */ +#define RTC_TAMPTIME_HOUR_Msk (0x3f0000UL) /*!< HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_TAMPTIME_MINUTE_Pos (8UL) /*!< MINUTE (Bit 8) */ +#define RTC_TAMPTIME_MINUTE_Msk (0x7f00UL) /*!< MINUTE (Bitfield-Mask: 0x7f) */ +#define RTC_TAMPTIME_SECOND_Pos (0UL) /*!< SECOND (Bit 0) */ +#define RTC_TAMPTIME_SECOND_Msk (0x7fUL) /*!< SECOND (Bitfield-Mask: 0x7f) */ +/* ======================================================== AWTARR ========================================================= */ +#define RTC_AWTARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define RTC_AWTARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ========================================================== IER ========================================================== */ +#define RTC_IER_INTERVAL_Pos (6UL) /*!< INTERVAL (Bit 6) */ +#define RTC_IER_INTERVAL_Msk (0x40UL) /*!< INTERVAL (Bitfield-Mask: 0x01) */ +#define RTC_IER_TAMPOV_Pos (4UL) /*!< TAMPOV (Bit 4) */ +#define RTC_IER_TAMPOV_Msk (0x10UL) /*!< TAMPOV (Bitfield-Mask: 0x01) */ +#define RTC_IER_TAMP_Pos (3UL) /*!< TAMP (Bit 3) */ +#define RTC_IER_TAMP_Msk (0x8UL) /*!< TAMP (Bitfield-Mask: 0x01) */ +#define RTC_IER_AWTIMER_Pos (2UL) /*!< AWTIMER (Bit 2) */ +#define RTC_IER_AWTIMER_Msk (0x4UL) /*!< AWTIMER (Bitfield-Mask: 0x01) */ +#define RTC_IER_ALARMB_Pos (1UL) /*!< ALARMB (Bit 1) */ +#define RTC_IER_ALARMB_Msk (0x2UL) /*!< ALARMB (Bitfield-Mask: 0x01) */ +#define RTC_IER_ALARMA_Pos (0UL) /*!< ALARMA (Bit 0) */ +#define RTC_IER_ALARMA_Msk (0x1UL) /*!< ALARMA (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define RTC_ISR_INTERVAL_Pos (6UL) /*!< INTERVAL (Bit 6) */ +#define RTC_ISR_INTERVAL_Msk (0x40UL) /*!< INTERVAL (Bitfield-Mask: 0x01) */ +#define RTC_ISR_TAMPOV_Pos (4UL) /*!< TAMPOV (Bit 4) */ +#define RTC_ISR_TAMPOV_Msk (0x10UL) /*!< TAMPOV (Bitfield-Mask: 0x01) */ +#define RTC_ISR_TAMP_Pos (3UL) /*!< TAMP (Bit 3) */ +#define RTC_ISR_TAMP_Msk (0x8UL) /*!< TAMP (Bitfield-Mask: 0x01) */ +#define RTC_ISR_AWTIMER_Pos (2UL) /*!< AWTIMER (Bit 2) */ +#define RTC_ISR_AWTIMER_Msk (0x4UL) /*!< AWTIMER (Bitfield-Mask: 0x01) */ +#define RTC_ISR_ALARMB_Pos (1UL) /*!< ALARMB (Bit 1) */ +#define RTC_ISR_ALARMB_Msk (0x2UL) /*!< ALARMB (Bitfield-Mask: 0x01) */ +#define RTC_ISR_ALARMA_Pos (0UL) /*!< ALARMA (Bit 0) */ +#define RTC_ISR_ALARMA_Msk (0x1UL) /*!< ALARMA (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define RTC_ICR_INTERVAL_Pos (6UL) /*!< INTERVAL (Bit 6) */ +#define RTC_ICR_INTERVAL_Msk (0x40UL) /*!< INTERVAL (Bitfield-Mask: 0x01) */ +#define RTC_ICR_TAMPOV_Pos (4UL) /*!< TAMPOV (Bit 4) */ +#define RTC_ICR_TAMPOV_Msk (0x10UL) /*!< TAMPOV (Bitfield-Mask: 0x01) */ +#define RTC_ICR_TAMP_Pos (3UL) /*!< TAMP (Bit 3) */ +#define RTC_ICR_TAMP_Msk (0x8UL) /*!< TAMP (Bitfield-Mask: 0x01) */ +#define RTC_ICR_AWTIMER_Pos (2UL) /*!< AWTIMER (Bit 2) */ +#define RTC_ICR_AWTIMER_Msk (0x4UL) /*!< AWTIMER (Bitfield-Mask: 0x01) */ +#define RTC_ICR_ALARMB_Pos (1UL) /*!< ALARMB (Bit 1) */ +#define RTC_ICR_ALARMB_Msk (0x2UL) /*!< ALARMB (Bitfield-Mask: 0x01) */ +#define RTC_ICR_ALARMA_Pos (0UL) /*!< ALARMA (Bit 0) */ +#define RTC_ICR_ALARMA_Msk (0x1UL) /*!< ALARMA (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define SPIx_CR1_MISOHD_Pos (18UL) /*!< MISOHD (Bit 18) */ +#define SPIx_CR1_MISOHD_Msk (0x40000UL) /*!< MISOHD (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_DMATX_Pos (17UL) /*!< DMATX (Bit 17) */ +#define SPIx_CR1_DMATX_Msk (0x20000UL) /*!< DMATX (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_DMARX_Pos (16UL) /*!< DMARX (Bit 16) */ +#define SPIx_CR1_DMARX_Msk (0x10000UL) /*!< DMARX (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_MODE_Pos (14UL) /*!< MODE (Bit 14) */ +#define SPIx_CR1_MODE_Msk (0xc000UL) /*!< MODE (Bitfield-Mask: 0x03) */ +#define SPIx_CR1_WIDTH_Pos (10UL) /*!< WIDTH (Bit 10) */ +#define SPIx_CR1_WIDTH_Msk (0x3c00UL) /*!< WIDTH (Bitfield-Mask: 0x0f) */ +#define SPIx_CR1_SSM_Pos (9UL) /*!< SSM (Bit 9) */ +#define SPIx_CR1_SSM_Msk (0x200UL) /*!< SSM (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_SMP_Pos (8UL) /*!< SMP (Bit 8) */ +#define SPIx_CR1_SMP_Msk (0x100UL) /*!< SMP (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_LSBF_Pos (7UL) /*!< LSBF (Bit 7) */ +#define SPIx_CR1_LSBF_Msk (0x80UL) /*!< LSBF (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_EN_Pos (6UL) /*!< EN (Bit 6) */ +#define SPIx_CR1_EN_Msk (0x40UL) /*!< EN (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_BR_Pos (3UL) /*!< BR (Bit 3) */ +#define SPIx_CR1_BR_Msk (0x38UL) /*!< BR (Bitfield-Mask: 0x07) */ +#define SPIx_CR1_MSTR_Pos (2UL) /*!< MSTR (Bit 2) */ +#define SPIx_CR1_MSTR_Msk (0x4UL) /*!< MSTR (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ +#define SPIx_CR1_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ +#define SPIx_CR1_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define SPIx_IER_MODF_Pos (7UL) /*!< MODF (Bit 7) */ +#define SPIx_IER_MODF_Msk (0x80UL) /*!< MODF (Bitfield-Mask: 0x01) */ +#define SPIx_IER_SSERR_Pos (6UL) /*!< SSERR (Bit 6) */ +#define SPIx_IER_SSERR_Msk (0x40UL) /*!< SSERR (Bitfield-Mask: 0x01) */ +#define SPIx_IER_OV_Pos (5UL) /*!< OV (Bit 5) */ +#define SPIx_IER_OV_Msk (0x20UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define SPIx_IER_UD_Pos (4UL) /*!< UD (Bit 4) */ +#define SPIx_IER_UD_Msk (0x10UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define SPIx_IER_SSR_Pos (3UL) /*!< SSR (Bit 3) */ +#define SPIx_IER_SSR_Msk (0x8UL) /*!< SSR (Bitfield-Mask: 0x01) */ +#define SPIx_IER_SSF_Pos (2UL) /*!< SSF (Bit 2) */ +#define SPIx_IER_SSF_Msk (0x4UL) /*!< SSF (Bitfield-Mask: 0x01) */ +#define SPIx_IER_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define SPIx_IER_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define SPIx_IER_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define SPIx_IER_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define SPIx_CR2_HDOE_Pos (0UL) /*!< HDOE (Bit 0) */ +#define SPIx_CR2_HDOE_Msk (0x1UL) /*!< HDOE (Bitfield-Mask: 0x01) */ +/* ========================================================== SSI ========================================================== */ +#define SPIx_SSI_SSI_Pos (0UL) /*!< SSI (Bit 0) */ +#define SPIx_SSI_SSI_Msk (0x1UL) /*!< SSI (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define SPIx_ISR_SSLVL_Pos (9UL) /*!< SSLVL (Bit 9) */ +#define SPIx_ISR_SSLVL_Msk (0x200UL) /*!< SSLVL (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_BUSY_Pos (8UL) /*!< BUSY (Bit 8) */ +#define SPIx_ISR_BUSY_Msk (0x100UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_MODF_Pos (7UL) /*!< MODF (Bit 7) */ +#define SPIx_ISR_MODF_Msk (0x80UL) /*!< MODF (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_SSERR_Pos (6UL) /*!< SSERR (Bit 6) */ +#define SPIx_ISR_SSERR_Msk (0x40UL) /*!< SSERR (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_OV_Pos (5UL) /*!< OV (Bit 5) */ +#define SPIx_ISR_OV_Msk (0x20UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_UD_Pos (4UL) /*!< UD (Bit 4) */ +#define SPIx_ISR_UD_Msk (0x10UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_SSR_Pos (3UL) /*!< SSR (Bit 3) */ +#define SPIx_ISR_SSR_Msk (0x8UL) /*!< SSR (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_SSF_Pos (2UL) /*!< SSF (Bit 2) */ +#define SPIx_ISR_SSF_Msk (0x4UL) /*!< SSF (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define SPIx_ISR_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define SPIx_ISR_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define SPIx_ICR_MODF_Pos (7UL) /*!< MODF (Bit 7) */ +#define SPIx_ICR_MODF_Msk (0x80UL) /*!< MODF (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_SSERR_Pos (6UL) /*!< SSERR (Bit 6) */ +#define SPIx_ICR_SSERR_Msk (0x40UL) /*!< SSERR (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_OV_Pos (5UL) /*!< OV (Bit 5) */ +#define SPIx_ICR_OV_Msk (0x20UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_UD_Pos (4UL) /*!< UD (Bit 4) */ +#define SPIx_ICR_UD_Msk (0x10UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_SSR_Pos (3UL) /*!< SSR (Bit 3) */ +#define SPIx_ICR_SSR_Msk (0x8UL) /*!< SSR (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_SSF_Pos (2UL) /*!< SSF (Bit 2) */ +#define SPIx_ICR_SSF_Msk (0x4UL) /*!< SSF (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define SPIx_ICR_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_FLUSH_Pos (0UL) /*!< FLUSH (Bit 0) */ +#define SPIx_ICR_FLUSH_Msk (0x1UL) /*!< FLUSH (Bitfield-Mask: 0x01) */ +/* ========================================================== DR =========================================================== */ +#define SPIx_DR_DR_Pos (0UL) /*!< DR (Bit 0) */ +#define SPIx_DR_DR_Msk (0xffffUL) /*!< DR (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ SYSCTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define SYSCTRL_CR0_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_CR0_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_CR0_HCLKPRS_Pos (5UL) /*!< HCLKPRS (Bit 5) */ +#define SYSCTRL_CR0_HCLKPRS_Msk (0xe0UL) /*!< HCLKPRS (Bitfield-Mask: 0x07) */ +#define SYSCTRL_CR0_PCLKPRS_Pos (3UL) /*!< PCLKPRS (Bit 3) */ +#define SYSCTRL_CR0_PCLKPRS_Msk (0x18UL) /*!< PCLKPRS (Bitfield-Mask: 0x03) */ +#define SYSCTRL_CR0_SYSCLK_Pos (0UL) /*!< SYSCLK (Bit 0) */ +#define SYSCTRL_CR0_SYSCLK_Msk (0x7UL) /*!< SYSCLK (Bitfield-Mask: 0x07) */ +/* ========================================================== CR1 ========================================================== */ +#define SYSCTRL_CR1_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_CR1_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_CR1_CLKCCS_Pos (8UL) /*!< CLKCCS (Bit 8) */ +#define SYSCTRL_CR1_CLKCCS_Msk (0x100UL) /*!< CLKCCS (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_HSECCS_Pos (7UL) /*!< HSECCS (Bit 7) */ +#define SYSCTRL_CR1_HSECCS_Msk (0x80UL) /*!< HSECCS (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_LSECCS_Pos (6UL) /*!< LSECCS (Bit 6) */ +#define SYSCTRL_CR1_LSECCS_Msk (0x40UL) /*!< LSECCS (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_LSELOCK_Pos (5UL) /*!< LSELOCK (Bit 5) */ +#define SYSCTRL_CR1_LSELOCK_Msk (0x20UL) /*!< LSELOCK (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_LSEEN_Pos (4UL) /*!< LSEEN (Bit 4) */ +#define SYSCTRL_CR1_LSEEN_Msk (0x10UL) /*!< LSEEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_LSIEN_Pos (3UL) /*!< LSIEN (Bit 3) */ +#define SYSCTRL_CR1_LSIEN_Msk (0x8UL) /*!< LSIEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_PLLEN_Pos (2UL) /*!< PLLEN (Bit 2) */ +#define SYSCTRL_CR1_PLLEN_Msk (0x4UL) /*!< PLLEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_HSEEN_Pos (1UL) /*!< HSEEN (Bit 1) */ +#define SYSCTRL_CR1_HSEEN_Msk (0x2UL) /*!< HSEEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_HSIEN_Pos (0UL) /*!< HSIEN (Bit 0) */ +#define SYSCTRL_CR1_HSIEN_Msk (0x1UL) /*!< HSIEN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define SYSCTRL_CR2_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_CR2_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_CR2_WAKEUPCLK_Pos (3UL) /*!< WAKEUPCLK (Bit 3) */ +#define SYSCTRL_CR2_WAKEUPCLK_Msk (0x8UL) /*!< WAKEUPCLK (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_LOCKUP_Pos (2UL) /*!< LOCKUP (Bit 2) */ +#define SYSCTRL_CR2_LOCKUP_Msk (0x4UL) /*!< LOCKUP (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_SWDIO_Pos (1UL) /*!< SWDIO (Bit 1) */ +#define SYSCTRL_CR2_SWDIO_Msk (0x2UL) /*!< SWDIO (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define SYSCTRL_IER_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_IER_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_IER_HSEFAULT_Pos (8UL) /*!< HSEFAULT (Bit 8) */ +#define SYSCTRL_IER_HSEFAULT_Msk (0x100UL) /*!< HSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_LSEFAULT_Pos (7UL) /*!< LSEFAULT (Bit 7) */ +#define SYSCTRL_IER_LSEFAULT_Msk (0x80UL) /*!< LSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_HSEFAIL_Pos (6UL) /*!< HSEFAIL (Bit 6) */ +#define SYSCTRL_IER_HSEFAIL_Msk (0x40UL) /*!< HSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_LSEFAIL_Pos (5UL) /*!< LSEFAIL (Bit 5) */ +#define SYSCTRL_IER_LSEFAIL_Msk (0x20UL) /*!< LSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_LSERDY_Pos (4UL) /*!< LSERDY (Bit 4) */ +#define SYSCTRL_IER_LSERDY_Msk (0x10UL) /*!< LSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_LSIRDY_Pos (3UL) /*!< LSIRDY (Bit 3) */ +#define SYSCTRL_IER_LSIRDY_Msk (0x8UL) /*!< LSIRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_PLLRDY_Pos (2UL) /*!< PLLRDY (Bit 2) */ +#define SYSCTRL_IER_PLLRDY_Msk (0x4UL) /*!< PLLRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_HSERDY_Pos (1UL) /*!< HSERDY (Bit 1) */ +#define SYSCTRL_IER_HSERDY_Msk (0x2UL) /*!< HSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_HSIRDY_Pos (0UL) /*!< HSIRDY (Bit 0) */ +#define SYSCTRL_IER_HSIRDY_Msk (0x1UL) /*!< HSIRDY (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define SYSCTRL_ISR_LSESTABLE_Pos (15UL) /*!< LSESTABLE (Bit 15) */ +#define SYSCTRL_ISR_LSESTABLE_Msk (0x8000UL) /*!< LSESTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSISTABLE_Pos (14UL) /*!< LSISTABLE (Bit 14) */ +#define SYSCTRL_ISR_LSISTABLE_Msk (0x4000UL) /*!< LSISTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_PLLSTABLE_Pos (13UL) /*!< PLLSTABLE (Bit 13) */ +#define SYSCTRL_ISR_PLLSTABLE_Msk (0x2000UL) /*!< PLLSTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSESTABLE_Pos (12UL) /*!< HSESTABLE (Bit 12) */ +#define SYSCTRL_ISR_HSESTABLE_Msk (0x1000UL) /*!< HSESTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSISTABLE_Pos (11UL) /*!< HSISTABLE (Bit 11) */ +#define SYSCTRL_ISR_HSISTABLE_Msk (0x800UL) /*!< HSISTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSEFAULT_Pos (8UL) /*!< HSEFAULT (Bit 8) */ +#define SYSCTRL_ISR_HSEFAULT_Msk (0x100UL) /*!< HSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSEFAULT_Pos (7UL) /*!< LSEFAULT (Bit 7) */ +#define SYSCTRL_ISR_LSEFAULT_Msk (0x80UL) /*!< LSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSEFAIL_Pos (6UL) /*!< HSEFAIL (Bit 6) */ +#define SYSCTRL_ISR_HSEFAIL_Msk (0x40UL) /*!< HSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSEFAIL_Pos (5UL) /*!< LSEFAIL (Bit 5) */ +#define SYSCTRL_ISR_LSEFAIL_Msk (0x20UL) /*!< LSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSERDY_Pos (4UL) /*!< LSERDY (Bit 4) */ +#define SYSCTRL_ISR_LSERDY_Msk (0x10UL) /*!< LSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSIRDY_Pos (3UL) /*!< LSIRDY (Bit 3) */ +#define SYSCTRL_ISR_LSIRDY_Msk (0x8UL) /*!< LSIRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_PLLRDY_Pos (2UL) /*!< PLLRDY (Bit 2) */ +#define SYSCTRL_ISR_PLLRDY_Msk (0x4UL) /*!< PLLRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSERDY_Pos (1UL) /*!< HSERDY (Bit 1) */ +#define SYSCTRL_ISR_HSERDY_Msk (0x2UL) /*!< HSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSIRDY_Pos (0UL) /*!< HSIRDY (Bit 0) */ +#define SYSCTRL_ISR_HSIRDY_Msk (0x1UL) /*!< HSIRDY (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define SYSCTRL_ICR_HSEFAULT_Pos (8UL) /*!< HSEFAULT (Bit 8) */ +#define SYSCTRL_ICR_HSEFAULT_Msk (0x100UL) /*!< HSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_LSEFAULT_Pos (7UL) /*!< LSEFAULT (Bit 7) */ +#define SYSCTRL_ICR_LSEFAULT_Msk (0x80UL) /*!< LSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_HSEFAIL_Pos (6UL) /*!< HSEFAIL (Bit 6) */ +#define SYSCTRL_ICR_HSEFAIL_Msk (0x40UL) /*!< HSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_LSEFAIL_Pos (5UL) /*!< LSEFAIL (Bit 5) */ +#define SYSCTRL_ICR_LSEFAIL_Msk (0x20UL) /*!< LSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_LSERDY_Pos (4UL) /*!< LSERDY (Bit 4) */ +#define SYSCTRL_ICR_LSERDY_Msk (0x10UL) /*!< LSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_LSIRDY_Pos (3UL) /*!< LSIRDY (Bit 3) */ +#define SYSCTRL_ICR_LSIRDY_Msk (0x8UL) /*!< LSIRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_PLLRDY_Pos (2UL) /*!< PLLRDY (Bit 2) */ +#define SYSCTRL_ICR_PLLRDY_Msk (0x4UL) /*!< PLLRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_HSERDY_Pos (1UL) /*!< HSERDY (Bit 1) */ +#define SYSCTRL_ICR_HSERDY_Msk (0x2UL) /*!< HSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_HSIRDY_Pos (0UL) /*!< HSIRDY (Bit 0) */ +#define SYSCTRL_ICR_HSIRDY_Msk (0x1UL) /*!< HSIRDY (Bitfield-Mask: 0x01) */ +/* ========================================================== HSI ========================================================== */ +#define SYSCTRL_HSI_STABLE_Pos (15UL) /*!< STABLE (Bit 15) */ +#define SYSCTRL_HSI_STABLE_Msk (0x8000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSI_DIV_Pos (11UL) /*!< DIV (Bit 11) */ +#define SYSCTRL_HSI_DIV_Msk (0x7800UL) /*!< DIV (Bitfield-Mask: 0x0f) */ +#define SYSCTRL_HSI_TRIM_Pos (0UL) /*!< TRIM (Bit 0) */ +#define SYSCTRL_HSI_TRIM_Msk (0x7ffUL) /*!< TRIM (Bitfield-Mask: 0x7ff) */ +/* ========================================================== HSE ========================================================== */ +#define SYSCTRL_HSE_STABLE_Pos (19UL) /*!< STABLE (Bit 19) */ +#define SYSCTRL_HSE_STABLE_Msk (0x80000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSE_DETCNT_Pos (8UL) /*!< DETCNT (Bit 8) */ +#define SYSCTRL_HSE_DETCNT_Msk (0x7ff00UL) /*!< DETCNT (Bitfield-Mask: 0x7ff) */ +#define SYSCTRL_HSE_FLT_Pos (7UL) /*!< FLT (Bit 7) */ +#define SYSCTRL_HSE_FLT_Msk (0x80UL) /*!< FLT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSE_MODE_Pos (6UL) /*!< MODE (Bit 6) */ +#define SYSCTRL_HSE_MODE_Msk (0x40UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSE_WAITCYCLE_Pos (4UL) /*!< WAITCYCLE (Bit 4) */ +#define SYSCTRL_HSE_WAITCYCLE_Msk (0x30UL) /*!< WAITCYCLE (Bitfield-Mask: 0x03) */ +#define SYSCTRL_HSE_FREQ_Pos (2UL) /*!< FREQ (Bit 2) */ +#define SYSCTRL_HSE_FREQ_Msk (0xcUL) /*!< FREQ (Bitfield-Mask: 0x03) */ +#define SYSCTRL_HSE_DRIVER_Pos (0UL) /*!< DRIVER (Bit 0) */ +#define SYSCTRL_HSE_DRIVER_Msk (0x3UL) /*!< DRIVER (Bitfield-Mask: 0x03) */ +/* ========================================================== LSI ========================================================== */ +#define SYSCTRL_LSI_STABLE_Pos (15UL) /*!< STABLE (Bit 15) */ +#define SYSCTRL_LSI_STABLE_Msk (0x8000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_LSI_WAITCYCLE_Pos (10UL) /*!< WAITCYCLE (Bit 10) */ +#define SYSCTRL_LSI_WAITCYCLE_Msk (0xc00UL) /*!< WAITCYCLE (Bitfield-Mask: 0x03) */ +#define SYSCTRL_LSI_TRIM_Pos (0UL) /*!< TRIM (Bit 0) */ +#define SYSCTRL_LSI_TRIM_Msk (0x3ffUL) /*!< TRIM (Bitfield-Mask: 0x3ff) */ +/* ========================================================== LSE ========================================================== */ +#define SYSCTRL_LSE_STABLE_Pos (15UL) /*!< STABLE (Bit 15) */ +#define SYSCTRL_LSE_STABLE_Msk (0x8000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_LSE_MODE_Pos (6UL) /*!< MODE (Bit 6) */ +#define SYSCTRL_LSE_MODE_Msk (0x40UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_LSE_WAITCYCLE_Pos (4UL) /*!< WAITCYCLE (Bit 4) */ +#define SYSCTRL_LSE_WAITCYCLE_Msk (0x30UL) /*!< WAITCYCLE (Bitfield-Mask: 0x03) */ +#define SYSCTRL_LSE_AMP_Pos (2UL) /*!< AMP (Bit 2) */ +#define SYSCTRL_LSE_AMP_Msk (0xcUL) /*!< AMP (Bitfield-Mask: 0x03) */ +#define SYSCTRL_LSE_DRIVER_Pos (0UL) /*!< DRIVER (Bit 0) */ +#define SYSCTRL_LSE_DRIVER_Msk (0x3UL) /*!< DRIVER (Bitfield-Mask: 0x03) */ +/* ========================================================== PLL ========================================================== */ +#define SYSCTRL_PLL_RFU_Pos (16UL) /*!< RFU (Bit 16) */ +#define SYSCTRL_PLL_RFU_Msk (0xf0000UL) /*!< RFU (Bitfield-Mask: 0x0f) */ +#define SYSCTRL_PLL_STABLE_Pos (15UL) /*!< STABLE (Bit 15) */ +#define SYSCTRL_PLL_STABLE_Msk (0x8000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_PLL_WAITCYCLE_Pos (12UL) /*!< WAITCYCLE (Bit 12) */ +#define SYSCTRL_PLL_WAITCYCLE_Msk (0x7000UL) /*!< WAITCYCLE (Bitfield-Mask: 0x07) */ +#define SYSCTRL_PLL_FREQOUT_Pos (9UL) /*!< FREQOUT (Bit 9) */ +#define SYSCTRL_PLL_FREQOUT_Msk (0xe00UL) /*!< FREQOUT (Bitfield-Mask: 0x07) */ +#define SYSCTRL_PLL_MUL_Pos (4UL) /*!< MUL (Bit 4) */ +#define SYSCTRL_PLL_MUL_Msk (0x1f0UL) /*!< MUL (Bitfield-Mask: 0x1f) */ +#define SYSCTRL_PLL_FREQIN_Pos (2UL) /*!< FREQIN (Bit 2) */ +#define SYSCTRL_PLL_FREQIN_Msk (0xcUL) /*!< FREQIN (Bitfield-Mask: 0x03) */ +#define SYSCTRL_PLL_SOURCE_Pos (0UL) /*!< SOURCE (Bit 0) */ +#define SYSCTRL_PLL_SOURCE_Msk (0x3UL) /*!< SOURCE (Bitfield-Mask: 0x03) */ +/* ========================================================= DEBUG ========================================================= */ +#define SYSCTRL_DEBUG_WWDT_Pos (10UL) /*!< WWDT (Bit 10) */ +#define SYSCTRL_DEBUG_WWDT_Msk (0x400UL) /*!< WWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_IWDT_Pos (9UL) /*!< IWDT (Bit 9) */ +#define SYSCTRL_DEBUG_IWDT_Msk (0x200UL) /*!< IWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_RTC_Pos (8UL) /*!< RTC (Bit 8) */ +#define SYSCTRL_DEBUG_RTC_Msk (0x100UL) /*!< RTC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_AWT_Pos (6UL) /*!< AWT (Bit 6) */ +#define SYSCTRL_DEBUG_AWT_Msk (0x40UL) /*!< AWT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_BTIM123_Pos (5UL) /*!< BTIM123 (Bit 5) */ +#define SYSCTRL_DEBUG_BTIM123_Msk (0x20UL) /*!< BTIM123 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_GTIM4_Pos (4UL) /*!< GTIM4 (Bit 4) */ +#define SYSCTRL_DEBUG_GTIM4_Msk (0x10UL) /*!< GTIM4 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_GTIM3_Pos (3UL) /*!< GTIM3 (Bit 3) */ +#define SYSCTRL_DEBUG_GTIM3_Msk (0x8UL) /*!< GTIM3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_GTIM2_Pos (2UL) /*!< GTIM2 (Bit 2) */ +#define SYSCTRL_DEBUG_GTIM2_Msk (0x4UL) /*!< GTIM2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_GTIM1_Pos (1UL) /*!< GTIM1 (Bit 1) */ +#define SYSCTRL_DEBUG_GTIM1_Msk (0x2UL) /*!< GTIM1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_ATIM_Pos (0UL) /*!< ATIM (Bit 0) */ +#define SYSCTRL_DEBUG_ATIM_Msk (0x1UL) /*!< ATIM (Bitfield-Mask: 0x01) */ +/* ========================================================= AHBEN ========================================================= */ +#define SYSCTRL_AHBEN_GPIOF_Pos (9UL) /*!< GPIOF (Bit 9) */ +#define SYSCTRL_AHBEN_GPIOF_Msk (0x200UL) /*!< GPIOF (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_GPIOC_Pos (6UL) /*!< GPIOC (Bit 6) */ +#define SYSCTRL_AHBEN_GPIOC_Msk (0x40UL) /*!< GPIOC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_GPIOB_Pos (5UL) /*!< GPIOB (Bit 5) */ +#define SYSCTRL_AHBEN_GPIOB_Msk (0x20UL) /*!< GPIOB (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_GPIOA_Pos (4UL) /*!< GPIOA (Bit 4) */ +#define SYSCTRL_AHBEN_GPIOA_Msk (0x10UL) /*!< GPIOA (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_CRC_Pos (2UL) /*!< CRC (Bit 2) */ +#define SYSCTRL_AHBEN_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_FLASH_Pos (1UL) /*!< FLASH (Bit 1) */ +#define SYSCTRL_AHBEN_FLASH_Msk (0x2UL) /*!< FLASH (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_DMA_Pos (0UL) /*!< DMA (Bit 0) */ +#define SYSCTRL_AHBEN_DMA_Msk (0x1UL) /*!< DMA (Bitfield-Mask: 0x01) */ +/* ======================================================== APBEN2 ========================================================= */ +#define SYSCTRL_APBEN2_AWT_Pos (13UL) /*!< AWT (Bit 13) */ +#define SYSCTRL_APBEN2_AWT_Msk (0x2000UL) /*!< AWT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_BTIM_Pos (12UL) /*!< BTIM (Bit 12) */ +#define SYSCTRL_APBEN2_BTIM_Msk (0x1000UL) /*!< BTIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_GTIM4_Pos (11UL) /*!< GTIM4 (Bit 11) */ +#define SYSCTRL_APBEN2_GTIM4_Msk (0x800UL) /*!< GTIM4 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_GTIM3_Pos (10UL) /*!< GTIM3 (Bit 10) */ +#define SYSCTRL_APBEN2_GTIM3_Msk (0x400UL) /*!< GTIM3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_UART1_Pos (9UL) /*!< UART1 (Bit 9) */ +#define SYSCTRL_APBEN2_UART1_Msk (0x200UL) /*!< UART1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_SPI1_Pos (8UL) /*!< SPI1 (Bit 8) */ +#define SYSCTRL_APBEN2_SPI1_Msk (0x100UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_ATIM_Pos (7UL) /*!< ATIM (Bit 7) */ +#define SYSCTRL_APBEN2_ATIM_Msk (0x80UL) /*!< ATIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_VC_Pos (4UL) /*!< VC (Bit 4) */ +#define SYSCTRL_APBEN2_VC_Msk (0x10UL) /*!< VC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_ADC_Pos (2UL) /*!< ADC (Bit 2) */ +#define SYSCTRL_APBEN2_ADC_Msk (0x4UL) /*!< ADC (Bitfield-Mask: 0x01) */ +/* ======================================================== APBEN1 ========================================================= */ +#define SYSCTRL_APBEN1_I2C2_Pos (12UL) /*!< I2C2 (Bit 12) */ +#define SYSCTRL_APBEN1_I2C2_Msk (0x1000UL) /*!< I2C2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_I2C1_Pos (11UL) /*!< I2C1 (Bit 11) */ +#define SYSCTRL_APBEN1_I2C1_Msk (0x800UL) /*!< I2C1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_UART3_Pos (8UL) /*!< UART3 (Bit 8) */ +#define SYSCTRL_APBEN1_UART3_Msk (0x100UL) /*!< UART3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_UART2_Pos (7UL) /*!< UART2 (Bit 7) */ +#define SYSCTRL_APBEN1_UART2_Msk (0x80UL) /*!< UART2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_SPI2_Pos (6UL) /*!< SPI2 (Bit 6) */ +#define SYSCTRL_APBEN1_SPI2_Msk (0x40UL) /*!< SPI2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_IWDT_Pos (5UL) /*!< IWDT (Bit 5) */ +#define SYSCTRL_APBEN1_IWDT_Msk (0x20UL) /*!< IWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_WWDT_Pos (4UL) /*!< WWDT (Bit 4) */ +#define SYSCTRL_APBEN1_WWDT_Msk (0x10UL) /*!< WWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_RTC_Pos (3UL) /*!< RTC (Bit 3) */ +#define SYSCTRL_APBEN1_RTC_Msk (0x8UL) /*!< RTC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_GTIM2_Pos (2UL) /*!< GTIM2 (Bit 2) */ +#define SYSCTRL_APBEN1_GTIM2_Msk (0x4UL) /*!< GTIM2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_GTIM1_Pos (1UL) /*!< GTIM1 (Bit 1) */ +#define SYSCTRL_APBEN1_GTIM1_Msk (0x2UL) /*!< GTIM1 (Bitfield-Mask: 0x01) */ +/* ======================================================== AHBRST ========================================================= */ +#define SYSCTRL_AHBRST_GPIOF_Pos (9UL) /*!< GPIOF (Bit 9) */ +#define SYSCTRL_AHBRST_GPIOF_Msk (0x200UL) /*!< GPIOF (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_GPIOC_Pos (6UL) /*!< GPIOC (Bit 6) */ +#define SYSCTRL_AHBRST_GPIOC_Msk (0x40UL) /*!< GPIOC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_GPIOB_Pos (5UL) /*!< GPIOB (Bit 5) */ +#define SYSCTRL_AHBRST_GPIOB_Msk (0x20UL) /*!< GPIOB (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_GPIOA_Pos (4UL) /*!< GPIOA (Bit 4) */ +#define SYSCTRL_AHBRST_GPIOA_Msk (0x10UL) /*!< GPIOA (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_CRC_Pos (2UL) /*!< CRC (Bit 2) */ +#define SYSCTRL_AHBRST_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_FLASH_Pos (1UL) /*!< FLASH (Bit 1) */ +#define SYSCTRL_AHBRST_FLASH_Msk (0x2UL) /*!< FLASH (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_DMA_Pos (0UL) /*!< DMA (Bit 0) */ +#define SYSCTRL_AHBRST_DMA_Msk (0x1UL) /*!< DMA (Bitfield-Mask: 0x01) */ +/* ======================================================== APBRST2 ======================================================== */ +#define SYSCTRL_APBRST2_AWT_Pos (13UL) /*!< AWT (Bit 13) */ +#define SYSCTRL_APBRST2_AWT_Msk (0x2000UL) /*!< AWT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_BTIM_Pos (12UL) /*!< BTIM (Bit 12) */ +#define SYSCTRL_APBRST2_BTIM_Msk (0x1000UL) /*!< BTIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_GTIM4_Pos (11UL) /*!< GTIM4 (Bit 11) */ +#define SYSCTRL_APBRST2_GTIM4_Msk (0x800UL) /*!< GTIM4 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_GTIM3_Pos (10UL) /*!< GTIM3 (Bit 10) */ +#define SYSCTRL_APBRST2_GTIM3_Msk (0x400UL) /*!< GTIM3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_UART1_Pos (9UL) /*!< UART1 (Bit 9) */ +#define SYSCTRL_APBRST2_UART1_Msk (0x200UL) /*!< UART1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_SPI1_Pos (8UL) /*!< SPI1 (Bit 8) */ +#define SYSCTRL_APBRST2_SPI1_Msk (0x100UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_ATIM_Pos (7UL) /*!< ATIM (Bit 7) */ +#define SYSCTRL_APBRST2_ATIM_Msk (0x80UL) /*!< ATIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_VC_Pos (4UL) /*!< VC (Bit 4) */ +#define SYSCTRL_APBRST2_VC_Msk (0x10UL) /*!< VC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_ADC_Pos (2UL) /*!< ADC (Bit 2) */ +#define SYSCTRL_APBRST2_ADC_Msk (0x4UL) /*!< ADC (Bitfield-Mask: 0x01) */ +/* ======================================================== APBRST1 ======================================================== */ +#define SYSCTRL_APBRST1_I2C2_Pos (12UL) /*!< I2C2 (Bit 12) */ +#define SYSCTRL_APBRST1_I2C2_Msk (0x1000UL) /*!< I2C2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_I2C1_Pos (11UL) /*!< I2C1 (Bit 11) */ +#define SYSCTRL_APBRST1_I2C1_Msk (0x800UL) /*!< I2C1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_UART3_Pos (8UL) /*!< UART3 (Bit 8) */ +#define SYSCTRL_APBRST1_UART3_Msk (0x100UL) /*!< UART3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_UART2_Pos (7UL) /*!< UART2 (Bit 7) */ +#define SYSCTRL_APBRST1_UART2_Msk (0x80UL) /*!< UART2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_SPI2_Pos (6UL) /*!< SPI2 (Bit 6) */ +#define SYSCTRL_APBRST1_SPI2_Msk (0x40UL) /*!< SPI2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_IWDT_Pos (5UL) /*!< IWDT (Bit 5) */ +#define SYSCTRL_APBRST1_IWDT_Msk (0x20UL) /*!< IWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_WWDT_Pos (4UL) /*!< WWDT (Bit 4) */ +#define SYSCTRL_APBRST1_WWDT_Msk (0x10UL) /*!< WWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_RTC_Pos (3UL) /*!< RTC (Bit 3) */ +#define SYSCTRL_APBRST1_RTC_Msk (0x8UL) /*!< RTC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_GTIM2_Pos (2UL) /*!< GTIM2 (Bit 2) */ +#define SYSCTRL_APBRST1_GTIM2_Msk (0x4UL) /*!< GTIM2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_GTIM1_Pos (1UL) /*!< GTIM1 (Bit 1) */ +#define SYSCTRL_APBRST1_GTIM1_Msk (0x2UL) /*!< GTIM1 (Bitfield-Mask: 0x01) */ +/* ======================================================= RESETFLAG ======================================================= */ +#define SYSCTRL_RESETFLAG_SYSRESETREQ_Pos (9UL) /*!< SYSRESETREQ (Bit 9) */ +#define SYSCTRL_RESETFLAG_SYSRESETREQ_Msk (0x200UL) /*!< SYSRESETREQ (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_LOCKUP_Pos (8UL) /*!< LOCKUP (Bit 8) */ +#define SYSCTRL_RESETFLAG_LOCKUP_Msk (0x100UL) /*!< LOCKUP (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_RSTB_Pos (6UL) /*!< RSTB (Bit 6) */ +#define SYSCTRL_RESETFLAG_RSTB_Msk (0x40UL) /*!< RSTB (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_WWDT_Pos (5UL) /*!< WWDT (Bit 5) */ +#define SYSCTRL_RESETFLAG_WWDT_Msk (0x20UL) /*!< WWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_IWDT_Pos (4UL) /*!< IWDT (Bit 4) */ +#define SYSCTRL_RESETFLAG_IWDT_Msk (0x10UL) /*!< IWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_LVD_Pos (3UL) /*!< LVD (Bit 3) */ +#define SYSCTRL_RESETFLAG_LVD_Msk (0x8UL) /*!< LVD (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_POR_Pos (0UL) /*!< POR (Bit 0) */ +#define SYSCTRL_RESETFLAG_POR_Msk (0x1UL) /*!< POR (Bitfield-Mask: 0x01) */ +/* ======================================================= GTIM1CAP ======================================================== */ +#define SYSCTRL_GTIM1CAP_CH4_Pos (12UL) /*!< CH4 (Bit 12) */ +#define SYSCTRL_GTIM1CAP_CH4_Msk (0x7000UL) /*!< CH4 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM1CAP_CH3_Pos (8UL) /*!< CH3 (Bit 8) */ +#define SYSCTRL_GTIM1CAP_CH3_Msk (0x700UL) /*!< CH3 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM1CAP_CH2_Pos (4UL) /*!< CH2 (Bit 4) */ +#define SYSCTRL_GTIM1CAP_CH2_Msk (0x70UL) /*!< CH2 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM1CAP_CH1_Pos (0UL) /*!< CH1 (Bit 0) */ +#define SYSCTRL_GTIM1CAP_CH1_Msk (0x7UL) /*!< CH1 (Bitfield-Mask: 0x07) */ +/* ======================================================= GTIM2CAP ======================================================== */ +#define SYSCTRL_GTIM2CAP_CH4_Pos (12UL) /*!< CH4 (Bit 12) */ +#define SYSCTRL_GTIM2CAP_CH4_Msk (0x7000UL) /*!< CH4 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM2CAP_CH3_Pos (8UL) /*!< CH3 (Bit 8) */ +#define SYSCTRL_GTIM2CAP_CH3_Msk (0x700UL) /*!< CH3 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM2CAP_CH2_Pos (4UL) /*!< CH2 (Bit 4) */ +#define SYSCTRL_GTIM2CAP_CH2_Msk (0x70UL) /*!< CH2 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM2CAP_CH1_Pos (0UL) /*!< CH1 (Bit 0) */ +#define SYSCTRL_GTIM2CAP_CH1_Msk (0x7UL) /*!< CH1 (Bitfield-Mask: 0x07) */ +/* ======================================================= GTIM3CAP ======================================================== */ +#define SYSCTRL_GTIM3CAP_CH4_Pos (12UL) /*!< CH4 (Bit 12) */ +#define SYSCTRL_GTIM3CAP_CH4_Msk (0x7000UL) /*!< CH4 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM3CAP_CH3_Pos (8UL) /*!< CH3 (Bit 8) */ +#define SYSCTRL_GTIM3CAP_CH3_Msk (0x700UL) /*!< CH3 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM3CAP_CH2_Pos (4UL) /*!< CH2 (Bit 4) */ +#define SYSCTRL_GTIM3CAP_CH2_Msk (0x70UL) /*!< CH2 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM3CAP_CH1_Pos (0UL) /*!< CH1 (Bit 0) */ +#define SYSCTRL_GTIM3CAP_CH1_Msk (0x7UL) /*!< CH1 (Bitfield-Mask: 0x07) */ +/* ======================================================= GTIM4CAP ======================================================== */ +#define SYSCTRL_GTIM4CAP_CH4_Pos (12UL) /*!< CH4 (Bit 12) */ +#define SYSCTRL_GTIM4CAP_CH4_Msk (0x7000UL) /*!< CH4 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM4CAP_CH3_Pos (8UL) /*!< CH3 (Bit 8) */ +#define SYSCTRL_GTIM4CAP_CH3_Msk (0x700UL) /*!< CH3 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM4CAP_CH2_Pos (4UL) /*!< CH2 (Bit 4) */ +#define SYSCTRL_GTIM4CAP_CH2_Msk (0x70UL) /*!< CH2 (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIM4CAP_CH1_Pos (0UL) /*!< CH1 (Bit 0) */ +#define SYSCTRL_GTIM4CAP_CH1_Msk (0x7UL) /*!< CH1 (Bitfield-Mask: 0x07) */ +/* ======================================================== ATIMETR ======================================================== */ +#define SYSCTRL_ATIMETR_ATIMETR_Pos (0UL) /*!< ATIMETR (Bit 0) */ +#define SYSCTRL_ATIMETR_ATIMETR_Msk (0x7UL) /*!< ATIMETR (Bitfield-Mask: 0x07) */ +/* ======================================================== GTIMETR ======================================================== */ +#define SYSCTRL_GTIMETR_GTIM4ETR_Pos (12UL) /*!< GTIM4ETR (Bit 12) */ +#define SYSCTRL_GTIMETR_GTIM4ETR_Msk (0x7000UL) /*!< GTIM4ETR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIMETR_GTIM3ETR_Pos (8UL) /*!< GTIM3ETR (Bit 8) */ +#define SYSCTRL_GTIMETR_GTIM3ETR_Msk (0x700UL) /*!< GTIM3ETR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIMETR_GTIM2ETR_Pos (4UL) /*!< GTIM2ETR (Bit 4) */ +#define SYSCTRL_GTIMETR_GTIM2ETR_Msk (0x70UL) /*!< GTIM2ETR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_GTIMETR_GTIM1ETR_Pos (0UL) /*!< GTIM1ETR (Bit 0) */ +#define SYSCTRL_GTIMETR_GTIM1ETR_Msk (0x7UL) /*!< GTIM1ETR (Bitfield-Mask: 0x07) */ +/* ======================================================== TIMITR ========================================================= */ +#define SYSCTRL_TIMITR_BTIM3ITR_Pos (21UL) /*!< BTIM3ITR (Bit 21) */ +#define SYSCTRL_TIMITR_BTIM3ITR_Msk (0xe00000UL) /*!< BTIM3ITR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_TIMITR_BTIM2ITR_Pos (18UL) /*!< BTIM2ITR (Bit 18) */ +#define SYSCTRL_TIMITR_BTIM2ITR_Msk (0x1c0000UL) /*!< BTIM2ITR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_TIMITR_BTIM1ITR_Pos (15UL) /*!< BTIM1ITR (Bit 15) */ +#define SYSCTRL_TIMITR_BTIM1ITR_Msk (0x38000UL) /*!< BTIM1ITR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_TIMITR_GTIM4ITR_Pos (12UL) /*!< GTIM4ITR (Bit 12) */ +#define SYSCTRL_TIMITR_GTIM4ITR_Msk (0x7000UL) /*!< GTIM4ITR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_TIMITR_GTIM3ITR_Pos (9UL) /*!< GTIM3ITR (Bit 9) */ +#define SYSCTRL_TIMITR_GTIM3ITR_Msk (0xe00UL) /*!< GTIM3ITR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_TIMITR_GTIM2ITR_Pos (6UL) /*!< GTIM2ITR (Bit 6) */ +#define SYSCTRL_TIMITR_GTIM2ITR_Msk (0x1c0UL) /*!< GTIM2ITR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_TIMITR_GTIM1ITR_Pos (3UL) /*!< GTIM1ITR (Bit 3) */ +#define SYSCTRL_TIMITR_GTIM1ITR_Msk (0x38UL) /*!< GTIM1ITR (Bitfield-Mask: 0x07) */ +#define SYSCTRL_TIMITR_ATIMITR_Pos (0UL) /*!< ATIMITR (Bit 0) */ +#define SYSCTRL_TIMITR_ATIMITR_Msk (0x7UL) /*!< ATIMITR (Bitfield-Mask: 0x07) */ +/* ========================================================== MCO ========================================================== */ +#define SYSCTRL_MCO_DIV_Pos (4UL) /*!< DIV (Bit 4) */ +#define SYSCTRL_MCO_DIV_Msk (0x70UL) /*!< DIV (Bitfield-Mask: 0x07) */ +#define SYSCTRL_MCO_SOURCE_Pos (0UL) /*!< SOURCE (Bit 0) */ +#define SYSCTRL_MCO_SOURCE_Msk (0xfUL) /*!< SOURCE (Bitfield-Mask: 0x0f) */ +/* ========================================================= IRMOD ========================================================= */ +#define SYSCTRL_IRMOD_MOD_Pos (0UL) /*!< MOD (Bit 0) */ +#define SYSCTRL_IRMOD_MOD_Msk (0xfUL) /*!< MOD (Bitfield-Mask: 0x0f) */ + + +/* =========================================================================================================================== */ +/* ================ UART ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define UARTx_CR1_OVER_Pos (9UL) /*!< OVER (Bit 9) */ +#define UARTx_CR1_OVER_Msk (0x600UL) /*!< OVER (Bitfield-Mask: 0x03) */ +#define UARTx_CR1_START_Pos (8UL) /*!< START (Bit 8) */ +#define UARTx_CR1_START_Msk (0x100UL) /*!< START (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_SYNC_Pos (6UL) /*!< SYNC (Bit 6) */ +#define UARTx_CR1_SYNC_Msk (0x40UL) /*!< SYNC (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_STOP_Pos (4UL) /*!< STOP (Bit 4) */ +#define UARTx_CR1_STOP_Msk (0x30UL) /*!< STOP (Bitfield-Mask: 0x03) */ +#define UARTx_CR1_PARITY_Pos (2UL) /*!< PARITY (Bit 2) */ +#define UARTx_CR1_PARITY_Msk (0xcUL) /*!< PARITY (Bitfield-Mask: 0x03) */ +#define UARTx_CR1_RXEN_Pos (1UL) /*!< RXEN (Bit 1) */ +#define UARTx_CR1_RXEN_Msk (0x2UL) /*!< RXEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_TXEN_Pos (0UL) /*!< TXEN (Bit 0) */ +#define UARTx_CR1_TXEN_Msk (0x1UL) /*!< TXEN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define UARTx_CR2_SOURCE_Pos (8UL) /*!< SOURCE (Bit 8) */ +#define UARTx_CR2_SOURCE_Msk (0x300UL) /*!< SOURCE (Bitfield-Mask: 0x03) */ +#define UARTx_CR2_DMATX_Pos (7UL) /*!< DMATX (Bit 7) */ +#define UARTx_CR2_DMATX_Msk (0x80UL) /*!< DMATX (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_DMARX_Pos (6UL) /*!< DMARX (Bit 6) */ +#define UARTx_CR2_DMARX_Msk (0x40UL) /*!< DMARX (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_TXINV_Pos (5UL) /*!< TXINV (Bit 5) */ +#define UARTx_CR2_TXINV_Msk (0x20UL) /*!< TXINV (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_RXINV_Pos (4UL) /*!< RXINV (Bit 4) */ +#define UARTx_CR2_RXINV_Msk (0x10UL) /*!< RXINV (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_RTSEN_Pos (3UL) /*!< RTSEN (Bit 3) */ +#define UARTx_CR2_RTSEN_Msk (0x8UL) /*!< RTSEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_CTSEN_Pos (2UL) /*!< CTSEN (Bit 2) */ +#define UARTx_CR2_CTSEN_Msk (0x4UL) /*!< CTSEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_SIGNAL_Pos (1UL) /*!< SIGNAL (Bit 1) */ +#define UARTx_CR2_SIGNAL_Msk (0x2UL) /*!< SIGNAL (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_ADDREN_Pos (0UL) /*!< ADDREN (Bit 0) */ +#define UARTx_CR2_ADDREN_Msk (0x1UL) /*!< ADDREN (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define UARTx_IER_CTS_Pos (6UL) /*!< CTS (Bit 6) */ +#define UARTx_IER_CTS_Msk (0x40UL) /*!< CTS (Bitfield-Mask: 0x01) */ +#define UARTx_IER_PE_Pos (4UL) /*!< PE (Bit 4) */ +#define UARTx_IER_PE_Msk (0x10UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UARTx_IER_FE_Pos (3UL) /*!< FE (Bit 3) */ +#define UARTx_IER_FE_Msk (0x8UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UARTx_IER_RC_Pos (2UL) /*!< RC (Bit 2) */ +#define UARTx_IER_RC_Msk (0x4UL) /*!< RC (Bitfield-Mask: 0x01) */ +#define UARTx_IER_TC_Pos (1UL) /*!< TC (Bit 1) */ +#define UARTx_IER_TC_Msk (0x2UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define UARTx_IER_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define UARTx_IER_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define UARTx_ISR_TXBUSY_Pos (8UL) /*!< TXBUSY (Bit 8) */ +#define UARTx_ISR_TXBUSY_Msk (0x100UL) /*!< TXBUSY (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_CTSLV_Pos (7UL) /*!< CTSLV (Bit 7) */ +#define UARTx_ISR_CTSLV_Msk (0x80UL) /*!< CTSLV (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_CTS_Pos (6UL) /*!< CTS (Bit 6) */ +#define UARTx_ISR_CTS_Msk (0x40UL) /*!< CTS (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_MATCH_Pos (5UL) /*!< MATCH (Bit 5) */ +#define UARTx_ISR_MATCH_Msk (0x20UL) /*!< MATCH (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_PE_Pos (4UL) /*!< PE (Bit 4) */ +#define UARTx_ISR_PE_Msk (0x10UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_FE_Pos (3UL) /*!< FE (Bit 3) */ +#define UARTx_ISR_FE_Msk (0x8UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_RC_Pos (2UL) /*!< RC (Bit 2) */ +#define UARTx_ISR_RC_Msk (0x4UL) /*!< RC (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_TC_Pos (1UL) /*!< TC (Bit 1) */ +#define UARTx_ISR_TC_Msk (0x2UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define UARTx_ISR_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define UARTx_ICR_CTS_Pos (6UL) /*!< CTS (Bit 6) */ +#define UARTx_ICR_CTS_Msk (0x40UL) /*!< CTS (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_PE_Pos (4UL) /*!< PE (Bit 4) */ +#define UARTx_ICR_PE_Msk (0x10UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_FE_Pos (3UL) /*!< FE (Bit 3) */ +#define UARTx_ICR_FE_Msk (0x8UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_RC_Pos (2UL) /*!< RC (Bit 2) */ +#define UARTx_ICR_RC_Msk (0x4UL) /*!< RC (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_TC_Pos (1UL) /*!< TC (Bit 1) */ +#define UARTx_ICR_TC_Msk (0x2UL) /*!< TC (Bitfield-Mask: 0x01) */ +/* ========================================================= BRRI ========================================================== */ +#define UARTx_BRRI_BRRI_Pos (0UL) /*!< BRRI (Bit 0) */ +#define UARTx_BRRI_BRRI_Msk (0xffffUL) /*!< BRRI (Bitfield-Mask: 0xffff) */ +/* ========================================================= BRRF ========================================================== */ +#define UARTx_BRRF_BRRF_Pos (0UL) /*!< BRRF (Bit 0) */ +#define UARTx_BRRF_BRRF_Msk (0xfUL) /*!< BRRF (Bitfield-Mask: 0x0f) */ +/* ========================================================== RDR ========================================================== */ +#define UARTx_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ +#define UARTx_RDR_RDR_Msk (0x1ffUL) /*!< RDR (Bitfield-Mask: 0x1ff) */ +/* ========================================================== TDR ========================================================== */ +#define UARTx_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ +#define UARTx_TDR_TDR_Msk (0x1ffUL) /*!< TDR (Bitfield-Mask: 0x1ff) */ +/* ========================================================= ADDR ========================================================== */ +#define UARTx_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define UARTx_ADDR_ADDR_Msk (0xffUL) /*!< ADDR (Bitfield-Mask: 0xff) */ +/* ========================================================= MASK ========================================================== */ +#define UARTx_MASK_MASK_Pos (0UL) /*!< MASK (Bit 0) */ +#define UARTx_MASK_MASK_Msk (0xffUL) /*!< MASK (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ VC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DIV ========================================================== */ +#define VCx_DIV_VIN_Pos (7UL) /*!< VIN (Bit 7) */ +#define VCx_DIV_VIN_Msk (0x80UL) /*!< VIN (Bitfield-Mask: 0x01) */ +#define VCx_DIV_EN_Pos (6UL) /*!< EN (Bit 6) */ +#define VCx_DIV_EN_Msk (0x40UL) /*!< EN (Bitfield-Mask: 0x01) */ +#define VCx_DIV_DIV_Pos (0UL) /*!< DIV (Bit 0) */ +#define VCx_DIV_DIV_Msk (0x3fUL) /*!< DIV (Bitfield-Mask: 0x3f) */ +/* ========================================================== CR0 ========================================================== */ +#define VCx_CR0_INN_Pos (12UL) /*!< INN (Bit 12) */ +#define VCx_CR0_INN_Msk (0xf000UL) /*!< INN (Bitfield-Mask: 0x0f) */ +#define VCx_CR0_INP_Pos (8UL) /*!< INP (Bit 8) */ +#define VCx_CR0_INP_Msk (0xf00UL) /*!< INP (Bitfield-Mask: 0x0f) */ +#define VCx_CR0_WINDOW_Pos (7UL) /*!< WINDOW (Bit 7) */ +#define VCx_CR0_WINDOW_Msk (0x80UL) /*!< WINDOW (Bitfield-Mask: 0x01) */ +#define VCx_CR0_POL_Pos (6UL) /*!< POL (Bit 6) */ +#define VCx_CR0_POL_Msk (0x40UL) /*!< POL (Bitfield-Mask: 0x01) */ +#define VCx_CR0_IE_Pos (5UL) /*!< IE (Bit 5) */ +#define VCx_CR0_IE_Msk (0x20UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define VCx_CR0_HYS_Pos (3UL) /*!< HYS (Bit 3) */ +#define VCx_CR0_HYS_Msk (0x18UL) /*!< HYS (Bitfield-Mask: 0x03) */ +#define VCx_CR0_RESP_Pos (1UL) /*!< RESP (Bit 1) */ +#define VCx_CR0_RESP_Msk (0x6UL) /*!< RESP (Bitfield-Mask: 0x03) */ +#define VCx_CR0_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define VCx_CR0_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ +#define VCx_CR1_BLANKFLT_Pos (13UL) /*!< BLANKFLT (Bit 13) */ +#define VCx_CR1_BLANKFLT_Msk (0xe000UL) /*!< BLANKFLT (Bitfield-Mask: 0x07) */ +#define VCx_CR1_BLANKCH3B_Pos (12UL) /*!< BLANKCH3B (Bit 12) */ +#define VCx_CR1_BLANKCH3B_Msk (0x1000UL) /*!< BLANKCH3B (Bitfield-Mask: 0x01) */ +#define VCx_CR1_BLANKCH2B_Pos (11UL) /*!< BLANKCH2B (Bit 11) */ +#define VCx_CR1_BLANKCH2B_Msk (0x800UL) /*!< BLANKCH2B (Bitfield-Mask: 0x01) */ +#define VCx_CR1_BLANKCH1B_Pos (10UL) /*!< BLANKCH1B (Bit 10) */ +#define VCx_CR1_BLANKCH1B_Msk (0x400UL) /*!< BLANKCH1B (Bitfield-Mask: 0x01) */ +#define VCx_CR1_ATIMBK_Pos (9UL) /*!< ATIMBK (Bit 9) */ +#define VCx_CR1_ATIMBK_Msk (0x200UL) /*!< ATIMBK (Bitfield-Mask: 0x01) */ +#define VCx_CR1_ATIMCLR_Pos (8UL) /*!< ATIMCLR (Bit 8) */ +#define VCx_CR1_ATIMCLR_Msk (0x100UL) /*!< ATIMCLR (Bitfield-Mask: 0x01) */ +#define VCx_CR1_HIGHIE_Pos (7UL) /*!< HIGHIE (Bit 7) */ +#define VCx_CR1_HIGHIE_Msk (0x80UL) /*!< HIGHIE (Bitfield-Mask: 0x01) */ +#define VCx_CR1_RISEIE_Pos (6UL) /*!< RISEIE (Bit 6) */ +#define VCx_CR1_RISEIE_Msk (0x40UL) /*!< RISEIE (Bitfield-Mask: 0x01) */ +#define VCx_CR1_FALLIE_Pos (5UL) /*!< FALLIE (Bit 5) */ +#define VCx_CR1_FALLIE_Msk (0x20UL) /*!< FALLIE (Bitfield-Mask: 0x01) */ +#define VCx_CR1_FLTCLK_Pos (4UL) /*!< FLTCLK (Bit 4) */ +#define VCx_CR1_FLTCLK_Msk (0x10UL) /*!< FLTCLK (Bitfield-Mask: 0x01) */ +#define VCx_CR1_FLTTIME_Pos (1UL) /*!< FLTTIME (Bit 1) */ +#define VCx_CR1_FLTTIME_Msk (0xeUL) /*!< FLTTIME (Bitfield-Mask: 0x07) */ +#define VCx_CR1_FLTEN_Pos (0UL) /*!< FLTEN (Bit 0) */ +#define VCx_CR1_FLTEN_Msk (0x1UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ +/* ========================================================== SR =========================================================== */ +#define VCx_SR_READY_Pos (2UL) /*!< READY (Bit 2) */ +#define VCx_SR_READY_Msk (0x4UL) /*!< READY (Bitfield-Mask: 0x01) */ +#define VCx_SR_FLTV_Pos (1UL) /*!< FLTV (Bit 1) */ +#define VCx_SR_FLTV_Msk (0x2UL) /*!< FLTV (Bitfield-Mask: 0x01) */ +#define VCx_SR_INTF_Pos (0UL) /*!< INTF (Bit 0) */ +#define VCx_SR_INTF_Msk (0x1UL) /*!< INTF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ WWDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define WWDT_CR0_EN_Pos (7UL) /*!< EN (Bit 7) */ +#define WWDT_CR0_EN_Msk (0x80UL) /*!< EN (Bitfield-Mask: 0x01) */ +#define WWDT_CR0_WCNT_Pos (0UL) /*!< WCNT (Bit 0) */ +#define WWDT_CR0_WCNT_Msk (0x7fUL) /*!< WCNT (Bitfield-Mask: 0x7f) */ +/* ========================================================== CR1 ========================================================== */ +#define WWDT_CR1_IE_Pos (10UL) /*!< IE (Bit 10) */ +#define WWDT_CR1_IE_Msk (0x400UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define WWDT_CR1_PRS_Pos (7UL) /*!< PRS (Bit 7) */ +#define WWDT_CR1_PRS_Msk (0x380UL) /*!< PRS (Bitfield-Mask: 0x07) */ +#define WWDT_CR1_WINR_Pos (0UL) /*!< WINR (Bit 0) */ +#define WWDT_CR1_WINR_Msk (0x7fUL) /*!< WINR (Bitfield-Mask: 0x7f) */ +/* ========================================================== SR =========================================================== */ +#define WWDT_SR_POV_Pos (0UL) /*!< POV (Bit 0) */ +#define WWDT_SR_POV_Msk (0x1UL) /*!< POV (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + +#ifdef __cplusplus +} +#endif + +#endif /* CW32F030_H */ + + +/** @} */ /* End of group cw32f030 */ + +/** @} */ /* End of group CW Co.Ltd */ diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_adc.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_adc.h new file mode 100644 index 0000000..8373cf7 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_adc.h @@ -0,0 +1,810 @@ +/** +* @file cw32f030_lvd.h +* @author P&S (you@domain.com) +* @brief +* @version 0.1 +* @date 2021-07-01 +* +* @copyright Copyright (c) 2021 +* +*/ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +#ifndef __CW32F030_ADC_H +#define __CW32F030_ADC_H + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "base_types.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup AdcGroup AD Converter (ADC) + ** + ******************************************************************************/ + +//@{ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define ADC_INT_PRIORITY ((uint32_t)3) /*ADC interrupt priority (lowest by default) */ + +#define COEFF_TS (0.0924f) +#define ADDR_TRIM_1P5 (0x0001260A) +#define ADDR_TRIM_2P5 (0x0001260C) +#define ADDR_T0 (0x00012609) +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition + * @{ + */ +#define ADC_IT_READY ((uint16_t)0x0080) +#define ADC_IT_OVW ((uint16_t)0x0040) +#define ADC_IT_WDTR ((uint16_t)0x0020) +#define ADC_IT_WDTH ((uint16_t)0x0010) +#define ADC_IT_WDTL ((uint16_t)0x0008) +#define ADC_IT_EOA ((uint16_t)0x0004) +#define ADC_IT_EOS ((uint16_t)0x0002) +#define ADC_IT_EOC ((uint16_t)0x0001) + +#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x00) && ((IT) != 0x00)) +#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_READY) || \ + ((IT) == ADC_IT_OVW) || \ + ((IT) == ADC_IT_WDTR)|| \ + ((IT) == ADC_IT_WDTH)|| \ + ((IT) == ADC_IT_WDTL)|| \ + ((IT) == ADC_IT_EOA)|| \ + ((IT) == ADC_IT_EOS)|| \ + ((IT) == ADC_IT_EOC)) + + +/** @defgroup ADC external interrupts_definition + * @{ + */ +#define ADC_TRIG_DMA ((uint16_t)0x8000) +#define ADC_TRIG_I2C2 ((uint16_t)0x4000) +#define ADC_TRIG_I2C1 ((uint16_t)0x2000) +#define ADC_TRIG_SPI2 ((uint16_t)0x1000) +#define ADC_TRIG_SPI1 ((uint16_t)0x0800) +#define ADC_TRIG_UART3 ((uint16_t)0x0400) +#define ADC_TRIG_UART2 ((uint16_t)0x0200) +#define ADC_TRIG_UART1 ((uint16_t)0x0100) +#define ADC_TRIG_BTIM3 ((uint16_t)0x0080) +#define ADC_TRIG_BTIM2 ((uint16_t)0x0040) +#define ADC_TRIG_BTIM1 ((uint16_t)0x0020) +#define ADC_TRIG_GTIM4 ((uint16_t)0x0010) +#define ADC_TRIG_GTIM3 ((uint16_t)0x0008) +#define ADC_TRIG_GTIM2 ((uint16_t)0x0004) +#define ADC_TRIG_GTIM1 ((uint16_t)0x0002) +#define ADC_TRIG_ATIM ((uint16_t)0x0001) + +#define IS_ADC_TRIG(TRIG) ((((TRIG) & (uint16_t)0x0000) == 0x00) && ((TRIG) != 0x00)) +#define IS_ADC_GET_TRIG(TRIG) (((TRIG) == ADC_TRIG_DMA) || \ + ((TRIG) == ADC_TRIG_I2C2) || \ + ((TRIG) == ADC_TRIG_I2C1)|| \ + ((TRIG) == ADC_TRIG_SPI2)|| \ + ((TRIG) == ADC_TRIG_SPI1)|| \ + ((TRIG) == ADC_TRIG_UART3)|| \ + ((TRIG) == ADC_TRIG_UART2)|| \ + ((TRIG) == ADC_TRIG_UART1) || \ + ((TRIG) == ADC_TRIG_BTIM3)|| \ + ((TRIG) == ADC_TRIG_BTIM2)|| \ + ((TRIG) == ADC_TRIG_BTIM1)|| \ + ((TRIG) == ADC_TRIG_GTIM4)|| \ + ((TRIG) == ADC_TRIG_GTIM3)|| \ + ((TRIG) == ADC_TRIG_GTIM2)|| \ + ((TRIG) == ADC_TRIG_GTIM1)|| \ + ((TRIG) == ADC_TRIG_ATIM)) + + +/****************************************************************************** + ** Global type definitions + *****************************************************************************/ + +/** @defgroup ADC_OpMode + * @{ + */ +#define ADC_SingleChOneMode ((uint32_t)0x00000000) +#define ADC_SingleChMoreMode ((uint32_t)0x00000002) +#define ADC_SingleChContinuousMode ((uint32_t)0x00000004) +#define ADC_SerialChContinuousMode ((uint32_t)0x00000006) +#define ADC_SerialChScanMode ((uint32_t)0x00000008) +#define ADC_SerialChMoreMode ((uint32_t)0x0000000A) +#define ADC_SerialChBreakMode ((uint32_t)0x0000000C) + + +#define IS_ADC_OP_MODE(OP_MODE) (((OP_MODE) == ADC_SingleChOneMode) || \ + ((OP_MODE) == ADC_SingleChMoreMode) || \ + ((OP_MODE) == ADC_SingleChContinuousMode) || \ + ((OP_MODE) == ADC_SerialChContinuousMode) || \ + ((OP_MODE) == ADC_SerialChScanMode) || \ + ((OP_MODE) == ADC_SerialChMoreMode) || \ + ((OP_MODE) == ADC_SerialChBreakMode)) + + +/** @defgroup ADC_ClkDiv + * @{ + */ +#define ADC_Clk_Div1 ((uint32_t)0x00000000) +#define ADC_Clk_Div2 ((uint32_t)0x00000100) +#define ADC_Clk_Div4 ((uint32_t)0x00000200) +#define ADC_Clk_Div8 ((uint32_t)0x00000300) +#define ADC_Clk_Div16 ((uint32_t)0x00000400) +#define ADC_Clk_Div32 ((uint32_t)0x00000500) +#define ADC_Clk_Div64 ((uint32_t)0x00000600) +#define ADC_Clk_Div128 ((uint32_t)0x00000700) + +#define IS_ADC_CLK_DIV(CLK_DIV) (((CLK_DIV) == ADC_Clk_Div1) || \ + ((CLK_DIV) == ADC_Clk_Div2) || \ + ((CLK_DIV) == ADC_Clk_Div4) || \ + ((CLK_DIV) == ADC_Clk_Div8) || \ + ((CLK_DIV) == ADC_Clk_Div16) || \ + ((CLK_DIV) == ADC_Clk_Div32) || \ + ((CLK_DIV) == ADC_Clk_Div64) || \ + ((CLK_DIV) == ADC_Clk_Div128)) + + + +/** @defgroup ADC_VrefSel + * @{ + */ +#define ADC_Vref_BGR1p5 ((uint32_t)0x00000000) +#define ADC_Vref_BGR2p5 ((uint32_t)0x00000040) +#define ADC_Vref_Extern1 ((uint32_t)0x00000080) +#define ADC_Vref_VDDA ((uint32_t)0x000000C0) + +#define IS_ADC_VREF_SEL(VREF_SEL) (((VREF_SEL) == ADC_Vref_BGR1p5) || \ + ((VREF_SEL) == ADC_Vref_BGR2p5) || \ + ((VREF_SEL) == ADC_Vref_Extern1) || \ + ((VREF_SEL) == ADC_Vref_VDDA)) + + + +/** @defgroup ADC_ChSel + * @{ + * ͨ0PA00 + * ͨ1PA01 + * ͨ2PA02 + * ͨ3PA03 + * ͨ4PA04 + * ͨ5PA05 + * ͨ6PA06 + * ͨ7PA07 + * ͨ8PB00 + * ͨ9PB01 + * ͨ10PB02 + * ͨ11PB10 + * ͨ12PB11 + * 1/3 VDDA(ʹ) + * BGR_TS(ʹ) + * Vref1P2(ʹ) + */ +#define ADC_ExInputCH0 ((uint32_t)0x00000000) +#define ADC_ExInputCH1 ((uint32_t)0x00000001) +#define ADC_ExInputCH2 ((uint32_t)0x00000002) +#define ADC_ExInputCH3 ((uint32_t)0x00000003) +#define ADC_ExInputCH4 ((uint32_t)0x00000004) +#define ADC_ExInputCH5 ((uint32_t)0x00000005) +#define ADC_ExInputCH6 ((uint32_t)0x00000006) +#define ADC_ExInputCH7 ((uint32_t)0x00000007) +#define ADC_ExInputCH8 ((uint32_t)0x00000008) +#define ADC_ExInputCH9 ((uint32_t)0x00000009) +#define ADC_ExInputCH10 ((uint32_t)0x0000000A) +#define ADC_ExInputCH11 ((uint32_t)0x0000000B) +#define ADC_ExInputCH12 ((uint32_t)0x0000000C) +#define ADC_VddaDiV3Input ((uint32_t)0x0000000D) +#define ADC_TsInput ((uint32_t)0x0000000E) +#define ADC_Vref1P2Input ((uint32_t)0x0000000F) + +#define IS_ADC_CH_SEL(CH_SEL) (((CH_SEL) == ADC_ExInputCH0) || \ + ((CH_SEL) == ADC_ExInputCH1) || \ + ((CH_SEL) == ADC_ExInputCH2) || \ + ((CH_SEL) == ADC_ExInputCH3) || \ + ((CH_SEL) == ADC_ExInputCH4) || \ + ((CH_SEL) == ADC_ExInputCH5) || \ + ((CH_SEL) == ADC_ExInputCH6) || \ + ((CH_SEL) == ADC_ExInputCH7) || \ + ((CH_SEL) == ADC_ExInputCH8) || \ + ((CH_SEL) == ADC_ExInputCH9) || \ + ((CH_SEL) == ADC_ExInputCH10) || \ + ((CH_SEL) == ADC_ExInputCH11) || \ + ((CH_SEL) == ADC_ExInputCH12) || \ + ((CH_SEL) == ADC_VddaDiV3Input) || \ + ((CH_SEL) == ADC_TsInput) || \ + ((CH_SEL) == ADC_Vref1P2Input)) + +/** @defgroup ADC_SampleTime + * @{ + */ +#define ADC_SampTime5Clk ((uint32_t)0x00000000) +#define ADC_SampTime6Clk ((uint32_t)0x00000800) +#define ADC_SampTime8Clk ((uint32_t)0x00001000) +#define ADC_SampTime10Clk ((uint32_t)0x00001800) + +#define IS_ADC_SAMPLE_TIME(SAMPLE_TIME) (((SAMPLE_TIME) == ADC_SampTime5Clk) || \ + ((SAMPLE_TIME) == ADC_SampTime6Clk) || \ + ((SAMPLE_TIME) == ADC_SampTime8Clk) || \ + ((SAMPLE_TIME) == ADC_SampTime10Clk)) + + + +/** @defgroup ADC_TrigSel + * @{ + */ +#define ADC_TrigATimerDisable ((uint32_t)0x00000000) +#define ADC_TrigATimerEnable ((uint32_t)0x00000001) + +#define ADC_TrigGTimer1Disable ((uint32_t)0x00000000) +#define ADC_TrigGTimer1Enable ((uint32_t)0x00000002) + +#define ADC_TrigGTimer2Disable ((uint32_t)0x00000000) +#define ADC_TrigGTimer2Enable ((uint32_t)0x00000004) + +#define ADC_TrigGTimer3Disable ((uint32_t)0x00000000) +#define ADC_TrigGTimer3Enable ((uint32_t)0x00000008) + +#define ADC_TrigGTimer4Disable ((uint32_t)0x00000000) +#define ADC_TrigGTimer4Enable ((uint32_t)0x00000010) + +#define ADC_TrigBTimer1Disable ((uint32_t)0x00000000) +#define ADC_TrigBTimer1Enable ((uint32_t)0x00000020) + +#define ADC_TrigBTimer2Disable ((uint32_t)0x00000000) +#define ADC_TrigBTimer2Enable ((uint32_t)0x00000040) + +#define ADC_TrigBTimer3Disable ((uint32_t)0x00000000) +#define ADC_TrigBTimer3Enable ((uint32_t)0x00000080) + +#define ADC_TrigUart1Disable ((uint32_t)0x00000000) +#define ADC_TrigUart1Enable ((uint32_t)0x00000100) + +#define ADC_TrigUart2Disable ((uint32_t)0x00000000) +#define ADC_TrigUart2Enable ((uint32_t)0x00000200) + +#define ADC_TrigUart3Disable ((uint32_t)0x00000000) +#define ADC_TrigUart3Enable ((uint32_t)0x00000400) + +#define ADC_TrigSPI1Disable ((uint32_t)0x00000000) +#define ADC_TrigSPI1Enable ((uint32_t)0x00000800) + +#define ADC_TrigSPI2Disable ((uint32_t)0x00000000) +#define ADC_TrigSPI2Enable ((uint32_t)0x00001000) + +#define ADC_TrigI2C1Disable ((uint32_t)0x00000000) +#define ADC_TrigI2C1Enable ((uint32_t)0x00002000) + +#define ADC_TrigI2C2Disable ((uint32_t)0x00000000) +#define ADC_TrigI2C2Enable ((uint32_t)0x00004000) + +#define ADC_TrigDMADisable ((uint32_t)0x00000000) +#define ADC_TrigDMAEnable ((uint32_t)0x00008000) + +#define IS_ADC_TRIG_SEL(TRIG_SEL) (((TRIG_SEL) == ADC_TrigATimerDisable) || \ + ((TRIG_SEL) == ADC_TrigATimerEnable) || \ + ((TRIG_SEL) == ADC_TrigGTimer1Disable) || \ + ((TRIG_SEL) == ADC_TrigGTimer1Enable) || \ + ((TRIG_SEL) == ADC_TrigGTimer2Disable) || \ + ((TRIG_SEL) == ADC_TrigGTimer2Enable) || \ + ((TRIG_SEL) == ADC_TrigGTimer3Disable) || \ + ((TRIG_SEL) == ADC_TrigGTimer3Enable) || \ + ((TRIG_SEL) == ADC_TrigGTimer4Disable) || \ + ((TRIG_SEL) == ADC_TrigGTimer4Enable) || \ + ((TRIG_SEL) == ADC_TrigBTimer1Disable) || \ + ((TRIG_SEL) == ADC_TrigBTimer1Enable) || \ + ((TRIG_SEL) == ADC_TrigBTimer2Disable) || \ + ((TRIG_SEL) == ADC_TrigBTimer2Enable) || \ + ((TRIG_SEL) == ADC_TrigBTimer3Disable) || \ + ((TRIG_SEL) == ADC_TrigBTimer3Enable) || \ + ((TRIG_SEL) == ADC_TrigUart1Disable) || \ + ((TRIG_SEL) == ADC_TrigUart1Enable) || \ + ((TRIG_SEL) == ADC_TrigUart2Disable) || \ + ((TRIG_SEL) == ADC_TrigUart2Enable) || \ + ((TRIG_SEL) == ADC_TrigUart3Disable) || \ + ((TRIG_SEL) == ADC_TrigUart3Enable) || \ + ((TRIG_SEL) == ADC_TrigSPI1Disable) || \ + ((TRIG_SEL) == ADC_TrigSPI1Enable) || \ + ((TRIG_SEL) == ADC_TrigSPI2Disable) || \ + ((TRIG_SEL) == ADC_TrigSPI2Enable) || \ + ((TRIG_SEL) == ADC_TrigI2C1Disable) || \ + ((TRIG_SEL) == ADC_TrigI2C1Enable) || \ + ((TRIG_SEL) == ADC_TrigI2C2Disable) || \ + ((TRIG_SEL) == ADC_TrigI2C2Enable) || \ + ((TRIG_SEL) == ADC_TrigDMADisable) || \ + ((TRIG_SEL) == ADC_TrigDMAEnable)) + + + +/** @defgroup ADC_SqrEns + * @{ + */ +#define ADC_SqrEns0 ((uint32_t)0x00000000) +#define ADC_SqrEns01 ((uint32_t)0x00010000) +#define ADC_SqrEns02 ((uint32_t)0x00020000) +#define ADC_SqrEns03 ((uint32_t)0x00030000) + +#define IS_ADC_SQR_ENS(SQR_ENS) (((SQR_ENS) == ADC_SqrEns0) || \ + ((SQR_ENS) == ADC_SqrEns01) || \ + ((SQR_ENS) == ADC_SqrEns02) || \ + ((SQR_ENS) == ADC_SqrEns03)) + + + +/** @defgroup ADC_SqrChmux + * @{ + * ͨ0PA00 + * ͨ1PA01 + * ͨ2PA02 + * ͨ3PA03 + * ͨ4PA04 + * ͨ5PA05 + * ͨ6PA06 + * ͨ7PA07 + * ͨ8PB00 + * ͨ9PB01 + * ͨ10PB02 + * ͨ11PB10 + * ͨ12PB11 + * 1/3 VDDA(ʹ) + * BGR_TS(ʹ) + * Vref1P2(ʹ) + */ +#define ADC_SqrCh0 ((uint32_t)0x00000000) +#define ADC_SqrCh1 ((uint32_t)0x00000001) +#define ADC_SqrCh2 ((uint32_t)0x00000002) +#define ADC_SqrCh3 ((uint32_t)0x00000003) +#define ADC_SqrCh4 ((uint32_t)0x00000004) +#define ADC_SqrCh5 ((uint32_t)0x00000005) +#define ADC_SqrCh6 ((uint32_t)0x00000006) +#define ADC_SqrCh7 ((uint32_t)0x00000007) +#define ADC_SqrCh8 ((uint32_t)0x00000008) +#define ADC_SqrCh9 ((uint32_t)0x00000009) +#define ADC_SqrCh10 ((uint32_t)0x0000000A) +#define ADC_SqrCh11 ((uint32_t)0x0000000B) +#define ADC_SqrCh12 ((uint32_t)0x0000000C) +#define ADC_SqrVddaDiV3 ((uint32_t)0x0000000D) +#define ADC_SqrTs ((uint32_t)0x0000000E) +#define ADC_SqrVref1P2 ((uint32_t)0x0000000F) + +#define IS_ADC_SQR_CH(SQR_CH) (((SQR_CH) == ADC_SqrCh0) || \ + ((SQR_CH) == ADC_SqrCh1) || \ + ((SQR_CH) == ADC_SqrCh2) || \ + ((SQR_CH) == ADC_SqrCh3) || \ + ((SQR_CH) == ADC_SqrCh4) || \ + ((SQR_CH) == ADC_SqrCh5) || \ + ((SQR_CH) == ADC_SqrCh6) || \ + ((SQR_CH) == ADC_SqrCh7) || \ + ((SQR_CH) == ADC_SqrCh8) || \ + ((SQR_CH) == ADC_SqrCh9) || \ + ((SQR_CH) == ADC_SqrCh10) || \ + ((SQR_CH) == ADC_SqrCh11) || \ + ((SQR_CH) == ADC_SqrCh12) || \ + ((SQR_CH) == ADC_SqrVddaDiV3) || \ + ((SQR_CH) == ADC_SqrTs) || \ + ((SQR_CH) == ADC_SqrVref1P2)) + + + +/** @defgroup ADC_WdtChmux + * @{ + * ͨ0PA00 + * ͨ1PA01 + * ͨ2PA02 + * ͨ3PA03 + * ͨ4PA04 + * ͨ5PA05 + * ͨ6PA06 + * ͨ7PA07 + * ͨ8PB00 + * ͨ9PB01 + * ͨ10PB02 + * ͨ11PB10 + * ͨ12PB11 + * 1/3 VDDA(ʹ) + * BGR_TS(ʹ) + * Vref1P2(ʹ) + */ +#define ADC_WdtCh0 ((uint32_t)0x00000000) +#define ADC_WdtCh1 ((uint32_t)0x00000100) +#define ADC_WdtCh2 ((uint32_t)0x00000200) +#define ADC_WdtCh3 ((uint32_t)0x00000300) +#define ADC_WdtCh4 ((uint32_t)0x00000400) +#define ADC_WdtCh5 ((uint32_t)0x00000500) +#define ADC_WdtCh6 ((uint32_t)0x00000600) +#define ADC_WdtCh7 ((uint32_t)0x00000700) +#define ADC_WdtCh8 ((uint32_t)0x00000800) +#define ADC_WdtCh9 ((uint32_t)0x00000900) +#define ADC_WdtCh10 ((uint32_t)0x00000A00) +#define ADC_WdtCh11 ((uint32_t)0x00000B00) +#define ADC_WdtCh12 ((uint32_t)0x00000C00) +#define ADC_WdtVddaDiV3 ((uint32_t)0x00000D00) +#define ADC_WdtTs ((uint32_t)0x00000E00) +#define ADC_WdtVref1P2 ((uint32_t)0x00000F00) + +#define IS_ADC_WDT_CH(WDT_CH) (((WDT_CH) == ADC_WdtCh0) || \ + ((WDT_CH) == ADC_WdtCh1) || \ + ((WDT_CH) == ADC_WdtCh2) || \ + ((WDT_CH) == ADC_WdtCh3) || \ + ((WDT_CH) == ADC_WdtCh4) || \ + ((WDT_CH) == ADC_WdtCh5) || \ + ((WDT_CH) == ADC_WdtCh6) || \ + ((WDT_CH) == ADC_WdtCh7) || \ + ((WDT_CH) == ADC_WdtCh8) || \ + ((WDT_CH) == ADC_WdtCh9) || \ + ((WDT_CH) == ADC_WdtCh10) || \ + ((WDT_CH) == ADC_WdtCh11) || \ + ((WDT_CH) == ADC_WdtCh12) || \ + ((WDT_CH) == ADC_WdtVddaDiV3) || \ + ((WDT_CH) == ADC_WdtTs) || \ + ((WDT_CH) == ADC_WdtVref1P2)) + + +/** @defgroup ADC_WdtAll + * @{ + */ +#define ADC_WdtDisable ((uint32_t)0x00000000) +#define ADC_WdtEnable ((uint32_t)0x00002000) + +#define IS_ADC_WDT_EN(WDT_EN) (((WDT_EN) == ADC_WdtDisable) || \ + ((WDT_EN) == ADC_WdtEnable)) + +/** @defgroup ADC_WdtrIrq + * @{ + */ +#define ADC_WdtrDisable ((uint32_t)0x00000000) +#define ADC_WdtrEnable ((uint32_t)0x00000020) + +#define IS_ADC_WDTR_EN(WDTR_EN) (((WDTR_EN) == ADC_WdtrDisable) || \ + ((WDTR_EN) == ADC_WdtrEnable)) + +/** @defghoup ADC_WdthIrq + * @{ + */ +#define ADC_WdthDisable ((uint32_t)0x00000000) +#define ADC_WdthEnable ((uint32_t)0x00000010) + +#define IS_ADC_WDTH_EN(WDTH_EN) (((WDTH_EN) == ADC_WdthDisable) || \ + ((WDTH_EN) == ADC_WdthEnable)) + +/** @defgloup ADC_WdtlIrq + * @{ + */ +#define ADC_WdtlDisable ((uint32_t)0x00000000) +#define ADC_WdtlEnable ((uint32_t)0x00000008) + +#define IS_ADC_WDTL_EN(WDTL_EN) (((WDTL_EN) == ADC_WdtlDisable) || \ + ((WDTL_EN) == ADC_WdtlEnable)) + + + +/** @defgroup ADC_Align + * @{ + */ +#define ADC_AlignRight ((uint32_t)0x00000000) +#define ADC_AlignLeft ((uint32_t)0x00000040) + +#define IS_ADC_DATA_ALIGN(DATA_ALIGN) (((DATA_ALIGN) == ADC_AlignRight) || \ + ((DATA_ALIGN) == ADC_AlignLeft)) + + + +/** @defgroup ADC_DataDiscard + * @{ + */ +#define ADC_DiscardNull ((uint32_t)0x00000000) +#define ADC_DiscardEnable ((uint32_t)0x00000020) + +#define IS_ADC_DATA_DISCARD(DATA_DISCARD) (((DATA_DISCARD) == ADC_DiscardNull) || \ + ((DATA_DISCARD) == ADC_DiscardEnable)) + + + +/** @defgroup ADC_TsEn + * @{ + */ +#define ADC_TsDisable ((uint32_t)0x00000000) +#define ADC_TsEnable ((uint32_t)0x00000020) + +#define IS_ADC_TS_ENABLE(TS_ENABLE) (((TS_ENABLE) == ADC_TsDisable) || \ + ((TS_ENABLE) == ADC_TsEnable)) + +/** @defgroup ADC_InBufEn + * @{ + */ +#define ADC_BufDisable ((uint32_t)0x00000000) +#define ADC_BufEnable ((uint32_t)0x00002000) + +#define IS_ADC_BUF_ENABLE(BUF_ENABLE) (((BUF_ENABLE) == ADC_BufDisable) || \ + ((BUF_ENABLE) == ADC_BufEnable)) + +/** @defgroup ADC_DMAEn + * @{ + */ +#define ADC_DmaDisable ((uint32_t)0x00000000) +#define ADC_DmaEnable ((uint32_t)0x00000080) + +#define IS_ADC_DMA_ENABLE(DMA_ENABLE) (((DMA_ENABLE) == ADC_DmaDisable) || \ + ((DMA_ENABLE) == ADC_DmaEnable)) + +/** @defgroup ADC_AccEn + * @{ + */ +#define ADC_AccDisable ((uint32_t)0x00000000) +#define ADC_AccEnable ((uint32_t)0x00000100) + +#define IS_ADC_ACC_ENABLE(ACC_ENABLE) (((ACC_ENABLE) == ADC_AccDisable) || \ + ((ACC_ENABLE) == ADC_AccEnable)) + + + +/** @defgroup ADC_AutoStop + * @{ + */ +#define ADC_AutoStopDisable ((uint32_t)0x00000000) +#define ADC_AutoStopEnable ((uint32_t)0x00000002) + +#define IS_ADC_AUTO_STOP(AUTO_STOP) (((AUTO_STOP) == ADC_AutoStopDisable) || \ + ((AUTO_STOP) == ADC_AutoStopEnable)) + +/****************************************************************************** + * Extern type definitions ('typedef') * + ******************************************************************************/ + +/** + ****************************************************************************** + ** @brief ADC + *****************************************************************************/ +typedef struct +{ + uint32_t ADC_OpMode; /*ADCģʽ*/ + + uint32_t ADC_ClkDiv; /*ADCʱѡ*/ + + uint32_t ADC_SampleTime; /*ADCʱ*/ + + uint32_t ADC_VrefSel; /*ADCοѹ*/ + + uint32_t ADC_InBufEn; /*ADCʹ*/ + + uint32_t ADC_TsEn; /*¶ȴʹ*/ + + uint32_t ADC_DMAEn; /*ADCתɴDMAʹ*/ + + uint32_t ADC_Align; /*ADCת뷽ʽ*/ + + uint32_t ADC_AccEn; /*תۼʹ*/ +}ADC_InitTypeDef; + +/** + ****************************************************************************** + ** @brief ADCģ⿴Ź + *****************************************************************************/ +typedef struct +{ + uint32_t ADC_WdtCh; /*ADCģ⿴Źͨ*/ + + uint32_t ADC_WdtAll; /*ADCģ⿴Źʹ*/ + + uint32_t ADC_WdtrIrq; /*ADCģ⿴Źʹ*/ + + uint32_t ADC_WdthIrq; /*ADCϳģ⿴Źʹ*/ + + uint32_t ADC_WdtlIrq; /*ADC³ģ⿴Źʹ*/ + + uint32_t ADC_Vth; /*ADCģ⿴Źֵ*/ + + uint32_t ADC_Vtl; /*ADCģ⿴Źֵ*/ +}ADC_WdtTypeDef; + +/** + ****************************************************************************** + ** @brief ADCͨ + *****************************************************************************/ +typedef struct +{ + uint32_t ADC_Chmux; /*ADCͨתģʽתͨ*/ + + uint32_t ADC_DiscardEn; /*ͨADCת*/ + + ADC_InitTypeDef ADC_InitStruct; /*ADCʼ*/ + + ADC_WdtTypeDef ADC_WdtStruct; /*ADCģ⿴Ź*/ +}ADC_SingleChTypeDef; + +/** + ****************************************************************************** + ** @brief ADC + *****************************************************************************/ +typedef struct +{ + uint32_t ADC_SqrEns; /*ADCת*/ + + uint32_t ADC_Sqr3Chmux; /*ADC3תͨ*/ + + uint32_t ADC_Sqr2Chmux; /*ADC2תͨ*/ + + uint32_t ADC_Sqr1Chmux; /*ADC1תͨ*/ + + uint32_t ADC_Sqr0Chmux; /*ADC0תͨ*/ + + ADC_InitTypeDef ADC_InitStruct; /*ADCʼ*/ +}ADC_SerialChTypeDef; + + +/** + ****************************************************************************** + ** @brief ADCж + *****************************************************************************/ +typedef struct +{ + boolean_t ADC_ReadyFlag; /*ADCʼɱ־*/ + + boolean_t ADC_OvwIrq; /*ADCתж*/ + + boolean_t ADC_WdtrIrq; /*ADCģ⿴Źж*/ + + boolean_t ADC_WdthIrq; /*ADCģ⿴Źֵж*/ + + boolean_t ADC_WdtlIrq; /*ADCģ⿴Źֵж*/ + + boolean_t ADC_EoaIrq; /*ADCתж*/ + + boolean_t ADC_EosIrq; /*ADCתж*/ + + boolean_t ADC_EocIrq; /*ADCתж*/ +}ADC_IrqTypeDef; + + + + + +/****************************************************************************** + * Global variable definitions ('extern') + ******************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + ******************************************************************************/ +//ADCȥʼ +void ADC_DeInit(void); +//ADCʼ +void ADC_Init(ADC_InitTypeDef* ADC_InitStruct); +//ADCĬֵʼ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +//ADCģ⿴ŹĬֵʼ +void ADC_WdtInit(ADC_WdtTypeDef* ADC_WdtStruct); +//ADCʹ +void ADC_Enable(void); +//ADC +void ADC_Disable(void); + +//DMAȡ +void ADC_DMACmd(FunctionalState NewState); +//DMAȡʹ +void ADC_DMAEnable(void); +//DMAȡֹ +void ADC_DMADisable(void); + +//ADCת +void ADC_SoftwareStartConvCmd(FunctionalState NewState); +//ADCⲿжϴԴ +void ADC_ExtTrigCfg(uint16_t ADC_TRIG, FunctionalState NewState); + +//ͨתģʽ +void ADC_SingleChCommon(ADC_SingleChTypeDef* ADC_SingleChStruct); +//ADCͨתģʽ +void ADC_SingleChOneModeCfg(ADC_SingleChTypeDef* ADC_SingleChStruct); +//ADCͨתģʽ +void ADC_SingleChMoreModeCfg(ADC_SingleChTypeDef* ADC_SingleChStruct, uint8_t cntAdcSample); +//ADCͨתģʽ +void ADC_SingleChContinuousModeCfg(ADC_SingleChTypeDef* ADC_SingleChStruct); +//ADCתģʽ +void ADC_SerialChCommon(ADC_SerialChTypeDef* ADC_SerialChStruct); +//ADCתģʽ +void ADC_SerialChContinuousModeCfg(ADC_SerialChTypeDef* ADC_SerialChStruct); +//ADCɨתģʽ +void ADC_SerialChScanModeCfg(ADC_SerialChTypeDef* ADC_SerialChStruct); +//ADCжתģʽ +void ADC_SerialChMoreModeCfg(ADC_SerialChTypeDef* ADC_SerialChStruct, uint8_t cntAdcSample); +//ADCжתģʽ +void ADC_SerialChBreakModeCfg(ADC_SerialChTypeDef* ADC_SerialChStruct); + +//SQR0תͨ +void ADC_Sqr0ChannelCfg(ADC_SerialChTypeDef* ADC_SerialChStruct); +//SQR0/SQR1תͨ +void ADC_Sqr01ChannelCfg(ADC_SerialChTypeDef* ADC_SerialChStruct); +//SQR0~SQR2תͨ +void ADC_Sqr02ChannelCfg(ADC_SerialChTypeDef* ADC_SerialChStruct); +//SQR0~SQR3תͨ +void ADC_Sqr03ChannelCfg(ADC_SerialChTypeDef* ADC_SerialChStruct); + +//ͨģʽøʹ +void ADC_BufEnSingleCh( uint32_t enAdcSampCh); +//ģʽøʹ +void ADC_BufEnSerialCh( uint32_t enAdcSampCh); + +//ADCģ⿴Ź +void ADC_WdtConfig(ADC_WdtTypeDef* ADC_WdtStruct); + +//ADCж +void ADC_ITConfig(uint16_t ADC_IT, FunctionalState NewState); +//ADCжʹ +void ADC_EnableIrq(uint8_t intPriority); +//ADCжϽֹ +void ADC_DisableIrq(void); +//ʹNVICADCж +void ADC_EnableNvic(uint8_t intPriority); +//NVICADCж +void ADC_DisableNvic(void); +//ȡADCж״̬ +void ADC_GetITStatusAll(volatile uint8_t* pFlagAdcIrq); +//ȡADCָж״̬ +ITStatus ADC_GetITStatus(uint16_t ADC_IT); +//ADCж״̬ +void ADC_ClearITPendingAll(void); +//ADCָж״̬ +void ADC_ClearITPendingBit(uint16_t ADC_IT); + +//ȡתֵ +uint16_t ADC_GetConversionValue(void); +//ȡSQR0ֵͨ +void ADC_GetSqr0Result(uint16_t* pAdcResult); +//ȡSQR1ֵͨ +void ADC_GetSqr1Result(uint16_t* pAdcResult); +//ȡSQR2ֵͨ +void ADC_GetSqr2Result(uint16_t* pAdcResult); +//ȡSQR3ֵͨ +void ADC_GetSqr3Result(uint16_t* pAdcResult); +//ȡۼӲֵ +void ADC_GetAccResult(uint32_t* pAdcAccResult); +//ۼӲֵ +void ADC_ClrAccResult(void); + +//òοѹ +void ADC_SetVref(uint32_t ADC_VrefSel); +//ý뷽ʽ +void ADC_SetAlign(uint32_t enAlign); +//õͨADCת +void ADC_SetDiscard(uint32_t enDiscard); +//¶ȴʹܿ +void ADC_SetTs(uint32_t enTs); +//ȡADCοѹ1.5Vʱ¶ȴIJ¶ +void ADC_GetTsVref1V5(float* fAdcTsDegree); +//ȡADCοѹ2.5Vʱ¶ȴIJ¶ +void ADC_GetTsVref2V5(float* fAdcTsDegree); +//ADCתԶֹͣ +void ADC_AutoStop(uint32_t enAutoStop); +//@} +#ifdef __cplusplus +} +#endif + +#endif /* __CW32F030_ADC_H */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_atim.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_atim.h new file mode 100644 index 0000000..3acd42e --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_atim.h @@ -0,0 +1,356 @@ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_ATIM_H +#define __CW32F030_ATIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" + +/****************************************************************************** + * type definitions ('typedef') + ******************************************************************************/ +typedef struct +{ + uint32_t CounterDirection; /*!< */ + + uint32_t CounterOPMode; /*!< ģʽλظ */ + + uint32_t CounterAlignedMode; /*!< ģʽ: ػ */ + + FunctionalState BufferState; /*!< ARRʹ */ + + uint32_t Prescaler; /*!< ԤƵϵ */ + + uint32_t ClockSelect; /*!< ʱѡ */ + + uint32_t ReloadValue; /*!< ARRֵȡֵΧ0x0000~0xFFFF */ + + uint32_t RepetitionCounter; /*!< ظڼֵRCRĴ */ + + FunctionalState UnderFlowMask; /*!< ʹ */ + + FunctionalState OverFlowMask; /*!< ʹ */ + + } ATIM_InitTypeDef; + + typedef struct +{ + uint32_t ICPolarity; /*!< 벶ԣ½˫ */ + + uint32_t ICFilter; /*!< ˲ */ +} ATIM_ICInitTypeDef; + +typedef struct +{ + uint32_t OCPolarity; /*!< ˿ڼѡ򡢷 */ + + uint32_t OCMode; /*!< Ƚģʽ */ + + uint32_t OCInterruptSelect; /*!< Ƚжģʽ */ + + FunctionalState OCDMAState; /*!< Ƚƥ䴥DMAʹ״̬ */ + + FunctionalState OCInterruptState; /*!< Ƚƥ䴥жʹ״̬ */ + + FunctionalState BufferState; /*!< Ƚϻʹ״̬ */ +} ATIM_OCInitTypeDef; +/****************************************************************************** + * pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define ATIM_COUNTING_UP (0UL) +#define ATIM_COUNTING_DOWN (1UL << 27) +#define IS_ATIM_COUNTING_DIRECTION(DIR) (((DIR) == ATIM_COUNTING_UP) || \ + ((DIR) == ATIM_COUNTING_DOWN)) + +#define ATIM_OP_MODE_SINGLE (1UL << 14) +#define ATIM_OP_MODE_REPETITIVE (0UL) +#define IS_ATIM_OP_MODE(MODE) (((MODE) == ATIM_OP_MODE_SINGLE) || \ + ((MODE) == ATIM_OP_MODE_REPETITIVE)) + + +#define ATIM_COUNT_MODE_EDGE_ALIGN (2UL << 12) +#define ATIM_COUNT_MODE_CENTER_ALIGN (3UL << 12) +#define IS_ATIM_COUNT_MODE(MODE) (((MODE) == ATIM_COUNT_MODE_EDGE_ALIGN) || \ + ((MODE) == ATIM_COUNT_MODE_CENTER_ALIGN)) + +#define ATIM_CR_IT_UNDE (1UL << 29) +#define ATIM_CR_IT_OVE (1UL << 28) +#define ATIM_CR_IT_BIE (1UL << 20) +#define ATIM_CR_IT_TIE (1UL << 19) +#define ATIM_CR_IT_UIE (1UL << 10) + +#define ATIM_BUFFER_ENABLE (1UL << 7) +#define ATIM_BUFFER_DISABLE (0UL) + +#define ATIM_Prescaler_DIV1 (0UL) +#define ATIM_Prescaler_DIV2 (1UL << 4) +#define ATIM_Prescaler_DIV4 (2UL << 4) +#define ATIM_Prescaler_DIV8 (3UL << 4) +#define ATIM_Prescaler_DIV16 (4UL << 4) +#define ATIM_Prescaler_DIV32 (5UL << 4) +#define ATIM_Prescaler_DIV64 (6UL << 4) +#define ATIM_Prescaler_DIV256 (7UL << 4) +#define IS_ATIM_PRESCALER(PRESCALER) (((PRESCALER) == ATIM_Prescaler_DIV1) ||\ + ((PRESCALER) == ATIM_Prescaler_DIV2) ||\ + ((PRESCALER) == ATIM_Prescaler_DIV4) ||\ + ((PRESCALER) == ATIM_Prescaler_DIV8) ||\ + ((PRESCALER) == ATIM_Prescaler_DIV16) ||\ + ((PRESCALER) == ATIM_Prescaler_DIV64) ||\ + ((PRESCALER) == ATIM_Prescaler_DIV256)) + +#define ATIM_CLOCK_PCLK (0UL) +#define ATIM_CLOCK_ETR (1UL << 2) +#define IS_ATIM_CLOCK(CLK) (((CLK) == ATIM_CLOCK_PCLK) || \ + ((CLK) == ATIM_CLOCK_ETR)) + +#define ATIM_IT_UIF (1UL) +#define ATIM_IT_C1AF (1UL << 2) +#define ATIM_IT_C2AF (1UL << 3) +#define ATIM_IT_C3AF (1UL << 4) +#define ATIM_IT_C1BF (1UL << 5) +#define ATIM_IT_C2BF (1UL << 6) +#define ATIM_IT_C3BF (1UL << 7) +#define ATIM_IT_C1AE (1UL << 8) +#define ATIM_IT_C2AE (1UL << 9) +#define ATIM_IT_C3AE (1UL << 10) +#define ATIM_IT_C1BE (1UL << 11) +#define ATIM_IT_C2BE (1UL << 12) +#define ATIM_IT_C3BE (1UL << 13) +#define ATIM_IT_BIF (1UL << 14) +#define ATIM_IT_TIF (1UL << 15) +#define ATIM_IT_OVF (1UL << 16) +#define ATIM_IT_UNDF (1UL << 17) +#define ATIM_IT_C4AF (1UL << 18) + +#define ATIM_CH_A_IC (1UL << 4) +#define ATIM_CH_A_OC (0UL) + +#define ATIM_CH_B_IC (1UL << 5) +#define ATIM_CH_B_OC (0UL) + +#define ATIM_CHxA_BUFF (1UL << 6) +#define ATIM_CHxA_CIE (1UL << 8) +#define ATIM_CHxA_CDE (1UL << 10) +#define ATIM_CHxB_BUFF (1UL << 7) +#define ATIM_CHxB_CIE (1UL << 9) +#define ATIM_CHxB_CDE (1UL << 11) + +#define ATIM_CH4_BUFF (1UL) +#define ATIM_CH4_CIE (1UL << 1) +#define ATIM_CH4_CDE (1UL << 2) + +#define ATIM_ICPOLOARITY_DISABLE (0UL) +#define ATIM_ICPOLARITY_RISING (1UL) +#define ATIM_ICPOLARITY_FALLING (2UL) +#define ATIM_ICPOLARITY_BOTHEDGE (3UL) +#define IS_ATIM_IC_POLARITY(POLARITY) (((POLARITY) == ATIM_ICPOLOARITY_DISABLE) || \ + ((POLARITY) == ATIM_ICPOLARITY_RISING) || \ + ((POLARITY) == ATIM_ICPOLARITY_FALLING)|| \ + ((POLARITY) == ATIM_ICPOLARITY_BOTHEDGE)) + +#define ATIM_ICFILTER_NONE (0UL) +#define ATIM_ICFILTER_PCLK_N3 (4UL) +#define ATIM_ICFILTER_PCLKDIV4_N3 (5UL) +#define ATIM_ICFILTER_PCLKDIV16_N3 (6UL) +#define ATIM_ICFILTER_PCLKDIV64_N3 (7UL) +#define IS_ATIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 7UL) + +#define ATIM_OCPOLARITY_NONINVERT (0UL) +#define ATIM_OCPOLARITY_INVERT (1UL) +#define IS_ATIM_OC_POLARITY(POLARITY) (((POLARITY) == ATIM_OCPOLARITY_NONINVERT) || \ + ((POLARITY) == ATIM_OCPOLARITY_INVERT)) + +#define ATIM_OCMODE_FORCED_INACTIVE (0UL) +#define ATIM_OCMODE_FORCED_ACTIVE (1UL) +#define ATIM_OCMODE_INACTIVE (2UL) +#define ATIM_OCMODE_ACTIVE (3UL) +#define ATIM_OCMODE_TOGGLE (4UL) +#define ATIM_OCMODE_ONE_PLUSE (5UL) +#define ATIM_OCMODE_PWM1 (6UL) +#define ATIM_OCMODE_PWM2 (7UL) +#define IS_ATIM_OC_MODE(MODE) ((MODE) <= 7UL) + +#define ATIM_OC_IT_NONE (0UL) +#define ATIM_OC_IT_UP_COUNTER (1UL) +#define ATIM_OC_IT_DOWN_COUNTER (2UL) +#define ATIM_OC_IT_BOTH_COUNTER (3UL) +#define IS_ATIM_OC_IT(SELECT) ((SELECT) <= 3UL) + +#define ATIM_ETR_POLARITY_NONINVERT (0UL) +#define ATIM_ETR_POLARITY_INVERT (1UL << 31) +#define IS_ATIM_ETR_POLARITY(POLARITY) (((POLARITY) == ATIM_ETR_POLARITY_INVERT) || \ + ((POLARITY) == ATIM_ETR_POLARITY_NONINVERT)) + +#define ATIM_ETR_FILTER_NONE (0UL) +#define ATIM_ETR_FILTER_PCLK_N3 (4UL << 28) +#define ATIM_ETR_FILTER_PCLKDIV4_N3 (5UL << 28) +#define ATIM_ETR_FILTER_PCLKDIV16_N3 (6UL << 28) +#define ATIM_ETR_FILTER_PCLKDIV64_N3 (7UL << 28) +#define IS_ATIM_ETR_FILTER(FILTER) (((FILTER) == ATIM_ETR_FILTER_NONE) ||\ + ((FILTER) == ATIM_ETR_FILTER_PCLK_N3) || \ + ((FILTER) == ATIM_ETR_FILTER_PCLKDIV4_N3) || \ + ((FILTER) == ATIM_ETR_FILTER_PCLKDIV16_N3) || \ + ((FILTER) == ATIM_ETR_FILTER_PCLKDIV64_N3)) + +#define ATIM_BRAKE_POLARITY_NONINVERT (0UL) +#define ATIM_BRAKE_POLARITY_INVERT (1UL << 27) +#define IS_ATIM_BRAKE_POLARITY(POLARITY) (((POLARITY) == ATIM_BRAKE_POLARITY_INVERT) || \ + ((POLARITY) == ATIM_BRAKE_POLARITY_NONINVERT)) + +#define ATIM_BRAKE_FILTER_NONE (0UL) +#define ATIM_BRAKE_FILTER_PCLK_N3 (4UL << 24) +#define ATIM_BRAKE_FILTER_PCLKDIV4_N3 (5UL << 24) +#define ATIM_BRAKE_FILTER_PCLKDIV16_N3 (6UL << 24) +#define ATIM_BRAKE_FILTER_PCLKDIV64_N3 (7UL << 24) +#define IS_ATIM_BRAKE_FILTER(FILTER) (((FILTER) == ATIM_BRAKE_FILTER_NONE) ||\ + ((FILTER) == ATIM_BRAKE_FILTER_PCLK_N3) || \ + ((FILTER) == ATIM_BRAKE_FILTER_PCLKDIV4_N3) || \ + ((FILTER) == ATIM_BRAKE_FILTER_PCLKDIV16_N3) || \ + ((FILTER) == ATIM_BRAKE_FILTER_PCLKDIV64_N3)) + +#define ATIM_ADC_TRIGGER_GLOBAL (1UL << 7) +#define ATIM_ADC_TRIGGER_CH3B (1UL << 6) +#define ATIM_ADC_TRIGGER_CH2B (1UL << 5) +#define ATIM_ADC_TRIGGER_CH1B (1UL << 4) +#define ATIM_ADC_TRIGGER_CH3A (1UL << 3) +#define ATIM_ADC_TRIGGER_CH2A (1UL << 2) +#define ATIM_ADC_TRIGGER_CH1A (1UL << 1) +#define ATIM_ADC_TRIGGER_UPDATA_EVENT (1UL) +#define IS_ATIM_ADC_TRIGGER(SOURCE) ((SOURCE) <= 0x000000FF) + +#define OCREFA_TYPE_DOUBLE (0UL) +#define OCREFA_TYPE_SINGLE (1UL << 3) +#define IS_ATIM_OCREFA_TYPE(TYPE) ((TYPE) == OCREFA_TYPE_DOUBLE || (TYPE) == OCREFA_TYPE_SINGLE) +#define OUTPUT_TYPE_ALONE (0UL) +#define OUTPUT_TYPE_COMP (1UL << 1) +#define IS_ATIM_OUTPUT_TYPE(TYPE) ((TYPE) == OUTPUT_TYPE_ALONE || (TYPE) == OUTPUT_TYPE_COMP) +#define IS_ATIM_DEADTIME(VAL) ((VAL)<= 0xFF) + +#define ATIM_MASTER_OUTPUT_UG 0x00 // UG +#define ATIM_MASTER_OUTPUT_CTEN 0x01 // ʱʹCTEN +#define ATIM_MASTER_OUTPUT_UEV 0x02 // ʱʱUEV +#define ATIM_MASTER_OUTPUT_CMPSO 0x03 // ȽƥѡCMPSO +#define ATIM_MASTER_OUTPUT_OCREF1A 0x04 // ʱȽOCREF1A +#define ATIM_MASTER_OUTPUT_OCREF2A 0x05 // ʱȽOCREF2A +#define ATIM_MASTER_OUTPUT_OCREF3A 0x06 // ʱȽOCREF3A +#define ATIM_MASTER_OUTPUT_OCREF1B 0x07 // ʱȽOCREF1B +#define IS_ATIM_MASTER_OUTPUT(OUTPUT) ((OUTPUT) <= 0x07) + +#define ATIM_SLAVER_TYPE_PCLK 0x00 // ڲʱ +#define ATIM_SLAVER_TYPE_RESET 0x01 // λ +#define ATIM_SLAVER_TYPE_TRIGGER 0x02 // ģʽ +#define ATIM_SLAVER_TYPE_EXT 0x03 // ⲿʱ +#define ATIM_SLAVER_TYPE_ENCODE1 0x04 // ģʽ1 +#define ATIM_SLAVER_TYPE_ENCODE2 0x05 // ģʽ2 +#define ATIM_SLAVER_TYPE_ENCODE3 0x06 // ģʽ3 +#define ATIM_SLAVER_TYPE_GATE 0x07 // ſع +#define IS_ATIM_SLAVER_TYPE(TYPE) ((TYPE) <= 0x07) + +#define ATIM_TRIGGER_SOURCE_ETFP 0x00 // ˿ETR˲λѡźETFP +#define ATIM_TRIGGER_SOURCE_ITR 0x01 // ڲźITR +#define ATIM_TRIGGER_SOURCE_CH1A 0x05 // ˿CH1Aıź +#define ATIM_TRIGGER_SOURCE_IAFP 0x06 // ˿CH1A˲λѡźIAFP +#define ATIM_TRIGGER_SOURCE_IBFP 0x07 // ˿CH1B˲λѡźIBFP +#define IS_ATIM_TRIGGER_SOURCE(SRC) ((SRC) == ATIM_TRIGGER_SOURCE_ETFP || \ + (SRC) == ATIM_TRIGGER_SOURCE_ITR || \ + (SRC) == ATIM_TRIGGER_SOURCE_CH1A || \ + (SRC) == ATIM_TRIGGER_SOURCE_IAFP || \ + (SRC) == ATIM_TRIGGER_SOURCE_IBFP) + +#define ATIM_UPDATE_EVENT_NORMAL 0x01 // / +#define ATIM_UPDATE_EVENT_EXTENSION 0x00 // ///ģʽλ +#define IS_ATIM_UPDATE_EVENT(EVENT) ((EVENT) == ATIM_UPDATE_EVENT_NORMAL || \ + (EVENT) == ATIM_UPDATE_EVENT_EXTENSION) + /****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + /****************************************************************************** + * Global function prototypes + ******************************************************************************/ + void ATIM_DeInit(void); + + void ATIM_Init(ATIM_InitTypeDef *ATIM_InitStruct); + void ATIM_Cmd(FunctionalState NewState); + + void ATIM_ITConfig(uint32_t ATIM_IT, FunctionalState NewState); + ITStatus ATIM_GetITStatus(uint32_t ATIM_IT); + void ATIM_ClearITPendingBit(uint32_t ATIM_IT); + void ATIM_SetReloadValue(uint32_t Value); + + void ATIM_CH1Config(uint32_t Function, FunctionalState NewState); + void ATIM_CH2Config(uint32_t Function, FunctionalState NewState); + void ATIM_CH3Config(uint32_t Function, FunctionalState NewState); + void ATIM_CH4Config(uint32_t Function, FunctionalState NewState); + + void ATIM_IC1AInit(ATIM_ICInitTypeDef *TIM_ICInitStruct); + void ATIM_IC1BInit(ATIM_ICInitTypeDef *TIM_ICInitStruct); + void ATIM_IC2AInit(ATIM_ICInitTypeDef *TIM_ICInitStruct); + void ATIM_IC2BInit(ATIM_ICInitTypeDef *TIM_ICInitStruct); + void ATIM_IC3AInit(ATIM_ICInitTypeDef *TIM_ICInitStruct); + void ATIM_IC3BInit(ATIM_ICInitTypeDef *TIM_ICInitStruct); + + void ATIM_OC1AInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct); + void ATIM_OC2AInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct); + void ATIM_OC3AInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct); + void ATIM_OC1BInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct); + void ATIM_OC2BInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct); + void ATIM_OC3BInit(ATIM_OCInitTypeDef *ATIM_OCInitStruct); + + void ATIM_OC4Init(FunctionalState NewState, uint32_t ITSelect, FunctionalState DMAState, + FunctionalState ITState, FunctionalState BufferState); + void ATIM_PWMOutputConfig(uint32_t OCREFAType, uint32_t OutputType, int16_t Deadtime); + void ATIM_CtrlPWMOutputs(FunctionalState NewState); + void ATIM_ETRConfig(uint32_t ATIM_ETRPolarity, uint32_t ATIM_ETRFilter); + void ATIM_BrakeConfig(uint32_t ATIM_BrakePolarity, uint32_t ATIM_BrakeFilter); + + void ATIM_ADCTriggerConfig(uint32_t ATIM_ADCTriggerSource, FunctionalState NewState); + + uint16_t ATIM_GetCapture1A(void); + uint16_t ATIM_GetCapture2A(void); + uint16_t ATIM_GetCapture3A(void); + uint16_t ATIM_GetCapture1B(void); + uint16_t ATIM_GetCapture2B(void); + uint16_t ATIM_GetCapture3B(void); + uint16_t ATIM_GetCapture4(void); + + void ATIM_SetCompare1A(uint16_t Compare); + void ATIM_SetCompare2A(uint16_t Compare); + void ATIM_SetCompare3A(uint16_t Compare); + void ATIM_SetCompare1B(uint16_t Compare); + void ATIM_SetCompare2B(uint16_t Compare); + void ATIM_SetCompare3B(uint16_t Compare); + void ATIM_SetCompare4(uint16_t Compare); + + void ATIM_MasterModeConfig(uint8_t ATIM_MasterOutput); + void ATIM_SlaverModeConfig(uint8_t ATIM_SlaverType); + void ATIM_TriggerSelect(uint8_t ATIM_TriggerSource); + void ATIM_UpdateEventSelect(uint8_t ATIM_UpdateEvent); + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32F030_ATIM_H */ +/** + * @} + */ diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_awt.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_awt.h new file mode 100644 index 0000000..f1875a3 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_awt.h @@ -0,0 +1,120 @@ +/** + * @file cw32f030_awt.h + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-18 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_AWT_H +#define __CW32F030_AWT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" + +typedef struct +{ + uint32_t AWT_ClkSource; /* ʱԴѡֵ0 - 4 */ + uint32_t AWT_Prescaler; /* Ԥϵֵ1 - 15ӦȡֵΧ2nݣn=1,215 */ + uint32_t AWT_Period; /* ڣȡֵΧ0x0000 0xFFFF. */ + uint32_t AWT_Mode; /* AWTģʽ̶Ϊ11 */ +} AWT_TimeCntInitTypeDef; + +#define AWT_CLKSOURCE_HSIOSC ( uint32_t )(0x00UL << 8) +#define AWT_CLKSOURCE_LSI ( uint32_t )(0x01UL << 8) +#define AWT_CLKSOURCE_HSE ( uint32_t )(0x02UL << 8) +#define AWT_CLKSOURCE_LSE ( uint32_t )(0x03UL << 8) +#define AWT_CLKSOURCE_ETR ( uint32_t )(0x04UL << 8) +#define IS_AWT_CLKSOURCE(SOURCE) (((SOURCE) == AWT_CLKSOURCE_HSIOSC) || \ + ((SOURCE) == AWT_CLKSOURCE_LSI) || \ + ((SOURCE) == AWT_CLKSOURCE_HSE) || \ + ((SOURCE) == AWT_CLKSOURCE_LSE) || \ + ((SOURCE) == AWT_CLKSOURCE_ETR)) + +#define AWT_PRS_DIV2 ( uint32_t )(0x01UL << 4) +#define AWT_PRS_DIV4 ( uint32_t )(0x02UL << 4) +#define AWT_PRS_DIV8 ( uint32_t )(0x03UL << 4) +#define AWT_PRS_DIV16 ( uint32_t )(0x04UL << 4) +#define AWT_PRS_DIV32 ( uint32_t )(0x05UL << 4) +#define AWT_PRS_DIV64 ( uint32_t )(0x06UL << 4) +#define AWT_PRS_DIV128 ( uint32_t )(0x07UL << 4) +#define AWT_PRS_DIV256 ( uint32_t )(0x08UL << 4) +#define AWT_PRS_DIV512 ( uint32_t )(0x09UL << 4) +#define AWT_PRS_DIV1024 ( uint32_t )(0x0AUL << 4) +#define AWT_PRS_DIV2048 ( uint32_t )(0x0BUL << 4) +#define AWT_PRS_DIV4096 ( uint32_t )(0x0CUL << 4) +#define AWT_PRS_DIV8192 ( uint32_t )(0x0DUL << 4) +#define AWT_PRS_DIV16384 ( uint32_t )(0x0EUL << 4) +#define AWT_PRS_DIV32768 ( uint32_t )(0x0FUL << 4) +#define IS_AWT_PRS_DIV(DIV) (((DIV) == AWT_PRS_DIV2) || \ + ((DIV) == AWT_PRS_DIV4) || \ + ((DIV) == AWT_PRS_DIV8) || \ + ((DIV) == AWT_PRS_DIV16) || \ + ((DIV) == AWT_PRS_DIV32) || \ + ((DIV) == AWT_PRS_DIV64) || \ + ((DIV) == AWT_PRS_DIV128) || \ + ((DIV) == AWT_PRS_DIV256) || \ + ((DIV) == AWT_PRS_DIV512) || \ + ((DIV) == AWT_PRS_DIV1024) || \ + ((DIV) == AWT_PRS_DIV2048) || \ + ((DIV) == AWT_PRS_DIV4096) || \ + ((DIV) == AWT_PRS_DIV8192) || \ + ((DIV) == AWT_PRS_DIV16384) || \ + ((DIV) == AWT_PRS_DIV32768)) + +#define AWT_MODE_TIMECNT ( uint32_t )(0x03UL << 1) +#define IS_AWT_MODE(MODE) ((MODE) == AWT_MODE_TIMECNT) +#define AWT_CR_EN bv0 + +#define IS_AWT_ARR(ARR) ((ARR) <= 65535) + +#define AWT_IT_UD ((uint32_t)0x08) +#define IS_AWT_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF7) == 0x0000) && ((IT) != 0x0000)) +#define IS_AWT_GET_IT(IT) (((IT) == AWT_IT_UD) + + +void AWT_DeInit(void); +void AWT_TimeCntInit(AWT_TimeCntInitTypeDef* AWT_TimeCntInitStruct); +void AWT_TimeCntStructInit(AWT_TimeCntInitTypeDef* AWT_TimeCntInitStruct); +void AWT_Cmd(FunctionalState NewState); +void AWT_ITConfig(uint32_t AWT_IT, FunctionalState NewState); +ITStatus AWT_GetITStatus(uint32_t AWT_IT); +void AWT_ClearITPendingBit(uint32_t AWT_IT); +void AWT_ClkSourceConfig(uint32_t AWT_ClkSource); +void AWT_PrescalerConfig(uint32_t AWT_Prescaler); +uint16_t AWT_GetCounter(void); +uint16_t AWT_GetAutoreload(void); +uint32_t AWT_GetClkSource(void); +uint32_t AWT_GetPrescaler(void); + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_btim.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_btim.h new file mode 100644 index 0000000..a3d8fad --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_btim.h @@ -0,0 +1,276 @@ +/** + * @file cw32f030_btim.h + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-27 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_BTIM_H +#define __CW32F030_BTIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup BTIM + * @{ + */ + +/** @defgroup BTIM_Exported_Types + * @{ + */ + +/** + * @brief BTIM Time Base Init structure definition + * @note This structure is used with all BTIMx except for BTIM6 and BTIM7. + */ + +typedef struct +{ + uint16_t BTIM_Prescaler; /* ԤϵȡֵΧ2nݣn=0,1,215 */ + + uint16_t BTIM_Mode; /* ģʽ00ʱģʽ + 01ģʽ + 10ģʽ + 11ſؼģʽ */ + + uint16_t BTIM_Period; /* ڣȡֵΧ0x0000 0xFFFF. */ + + uint16_t BTIM_OPMode; /* κģʽ */ + +} BTIM_TimeBaseInitTypeDef; + +/** @defgroup BTIM_Exported_constants + * @{ + */ + +#define IS_BTIM_ALL_PERIPH(PERIPH) (((PERIPH) == CW_BTIM1) || \ + ((PERIPH) == CW_BTIM2) || \ + ((PERIPH) == CW_BTIM3)) + +/** + * @} + */ + +/** @defgroup BTIM_One_Pulse_Mode + * @{ + */ + +#define BTIM_OPMode_Single ((uint16_t)0x0020) +#define BTIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_BTIM_OPM_MODE(MODE) (((MODE) == BTIM_OPMode_Single) || \ + ((MODE) == BTIM_OPMode_Repetitive)) +/** + * @} + */ + + + +/** @defgroup BTIM_Prescaler_Division + * @{ + */ + +#define BTIM_PRS_DIV1 ((uint16_t)0x0000) +#define BTIM_PRS_DIV2 ((uint16_t)0x0080) +#define BTIM_PRS_DIV4 ((uint16_t)0x0100) +#define BTIM_PRS_DIV8 ((uint16_t)0x0180) +#define BTIM_PRS_DIV16 ((uint16_t)0x0200) +#define BTIM_PRS_DIV32 ((uint16_t)0x0280) +#define BTIM_PRS_DIV64 ((uint16_t)0x0300) +#define BTIM_PRS_DIV128 ((uint16_t)0x0380) +#define BTIM_PRS_DIV256 ((uint16_t)0x0400) +#define BTIM_PRS_DIV512 ((uint16_t)0x0480) +#define BTIM_PRS_DIV1024 ((uint16_t)0x0500) +#define BTIM_PRS_DIV2048 ((uint16_t)0x0580) +#define BTIM_PRS_DIV4096 ((uint16_t)0x0600) +#define BTIM_PRS_DIV8192 ((uint16_t)0x0680) +#define BTIM_PRS_DIV16384 ((uint16_t)0x0700) +#define BTIM_PRS_DIV32768 ((uint16_t)0x0780) +#define IS_BTIM_PRS_DIV(DIV) (((DIV) == BTIM_PRS_DIV1) || \ + ((DIV) == BTIM_PRS_DIV2) || \ + ((DIV) == BTIM_PRS_DIV4) || \ + ((DIV) == BTIM_PRS_DIV8) || \ + ((DIV) == BTIM_PRS_DIV16) || \ + ((DIV) == BTIM_PRS_DIV32) || \ + ((DIV) == BTIM_PRS_DIV64) || \ + ((DIV) == BTIM_PRS_DIV128) || \ + ((DIV) == BTIM_PRS_DIV256) || \ + ((DIV) == BTIM_PRS_DIV512) || \ + ((DIV) == BTIM_PRS_DIV1024) || \ + ((DIV) == BTIM_PRS_DIV2048) || \ + ((DIV) == BTIM_PRS_DIV4096) || \ + ((DIV) == BTIM_PRS_DIV8192) || \ + ((DIV) == BTIM_PRS_DIV16384) || \ + ((DIV) == BTIM_PRS_DIV32768)) +/** + * @} + */ + +/** @defgroup BTIM_Mode + * @{ + */ + +#define BTIM_Mode_TIMER ((uint16_t)0x0000) +#define BTIM_Mode_COUNTER ((uint16_t)0x0002) +#define BTIM_Mode_TRIGGER ((uint16_t)0x00004) +#define BTIM_Mode_GATE ((uint16_t)0x0006) +#define IS_BTIM_MODE(MODE) (((MODE) == BTIM_Mode_TIMER) || \ + ((MODE) == BTIM_Mode_COUNTER) || \ + ((MODE) == BTIM_Mode_TRIGGER) || \ + ((MODE) == BTIM_Mode_GATE)) + + + +/** @defgroup BTIM_interrupt_sources + * @{ + */ + +#define BTIM_IT_OV ((uint16_t)0x0001) +#define BTIM_IT_TI ((uint16_t)0x0002) +#define BTIM_IT_TOP ((uint16_t)0x0004) +#define IS_BTIM_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x0000) && ((IT) != 0x0000)) + +#define IS_BTIM_GET_IT(IT) (((IT) == BTIM_IT_OV) || \ + ((IT) == BTIM_IT_TI) || \ + ((IT) == BTIM_IT_TOP)) +/** + * @} + */ + +/** @defgroup BTIM_DMA_sources + * @{ + */ + +#define BTIM_DMA_OV ((uint16_t)0x0001) +#define BTIM_DMA_TRS ((uint16_t)0x0002) +#define IS_BTIM_DMA_SOURCE(SOURCE) (((SOURCE) == BTIM_DMA_OV) ||\ + ((SOURCE) == BTIM_DMA_TRS)) + +/** + * @} + */ + + +/** @defgroup BTIM_Internal_Trigger_Selection + * @{ + */ + +#define BTIM_TS_ITR ((uint16_t)0x0008) +#define BTIM_TS_ETR ((uint16_t)0x0000) +#define IS_BTIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == BTIM_TS_ITR) || \ + ((SELECTION) == BTIM_TS_ETR)) + +/** + * @} + */ + +/** @defgroup BTIM_ETR_Polarity + * @{ + */ + +#define BTIM_ETR_Polarity_Positive ((uint16_t)0x0000) +#define BTIM_ETR_Polarity_Negative ((uint16_t)0x0010) +#define IS_BTIM_ETR_POLARITY(MODE) (((MODE) == BTIM_ETR_Polarity_Positive) || \ + ((MODE) == BTIM_ETR_Polarity_Negative)) +/** + * @} + */ + +/** @defgroup BTIM_Prescaler_Reload_Mode + * @{ + */ + +#define BTIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define BTIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_BTIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == BTIM_PSCReloadMode_Update) || \ + ((RELOAD) == BTIM_PSCReloadMode_Immediate)) +/** + * @} + */ + + +/** @defgroup BTIM_External_Trigger_Filter + * @{ + */ +#define BTIM_EXT_FILTER_NONE 0x0000 +#define BTIM_EXT_FILTER_PCLK_N2 0x0010 +#define BTIM_EXT_FILTER_PCLK_N4 0x0020 +#define BTIM_EXT_FILTER_PCLK_N6 0x0030 +#define BTIM_EXT_FILTER_PCLKDIV4_N4 0x0040 +#define BTIM_EXT_FILTER_PCLKDIV4_N6 0x0050 +#define BTIM_EXT_FILTER_PCLKDIV16_N4 0x0060 +#define BTIM_EXT_FILTER_PCLKDIV16_N6 0x0070 +#define IS_BTIM_EXT_FILTER(EXTFILTER) (((EXTFILTER) == BTIM_EXT_FILTER_NONE) || \ + ((EXTFILTER) == BTIM_EXT_FILTER_PCLK_N2) || \ + ((EXTFILTER) == BTIM_EXT_FILTER_PCLK_N4) || \ + ((EXTFILTER) == BTIM_EXT_FILTER_PCLK_N6) || \ + ((EXTFILTER) == BTIM_EXT_FILTER_PCLKDIV4_N4) || \ + ((EXTFILTER) == BTIM_EXT_FILTER_PCLKDIV4_N6) || \ + ((EXTFILTER) == BTIM_EXT_FILTER_PCLKDIV16_N4) || \ + ((EXTFILTER) == BTIM_EXT_FILTER_PCLKDIV16_N6)) +/** + * @} + */ + + +/** @defgroup BTIM_Exported_Functions + * @{ + */ + +void BTIM_DeInit(BTIM_TypeDef* BTIMx); +void BTIM_TimeBaseInit(BTIM_TypeDef* BTIMx, BTIM_TimeBaseInitTypeDef* BTIM_TimeBaseInitStruct); +void BTIM_TimeBaseStructInit(BTIM_TimeBaseInitTypeDef* BTIM_TimeBaseInitStruct); +void BTIM_Cmd(BTIM_TypeDef* BTIMx, FunctionalState NewState); +void BTIM_ITConfig(BTIM_TypeDef* BTIMx, uint16_t BTIM_IT, FunctionalState NewState); +void BTIM_DMACmd(BTIM_TypeDef* BTIMx, uint16_t BTIM_DMASource, FunctionalState NewState); +void BTIM_PrescalerConfig(BTIM_TypeDef* BTIMx, uint16_t Prescaler, uint16_t BTIM_PSCReloadMode); +void BTIM_ModeConfig(BTIM_TypeDef* BTIMx, uint16_t BTIM_Mode); +void BTIM_SelectInputTrigger(BTIM_TypeDef* BTIMx, uint16_t BTIM_InputTriggerSource); +void BTIM_SelectOnePulseMode(BTIM_TypeDef* BTIMx, uint16_t BTIM_OPMode); +void BTIM_OutputToggleCmd(BTIM_TypeDef* BTIMx, FunctionalState NewState); +void BTIM_ETRConfig(BTIM_TypeDef* BTIMx, uint16_t BTIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void BTIM_SetCounter(BTIM_TypeDef* BTIMx, uint16_t Counter); +void BTIM_SetAutoreload(BTIM_TypeDef* BTIMx, uint16_t Autoreload); +uint16_t BTIM_GetCounter(BTIM_TypeDef* BTIMx); +uint16_t BTIM_GetAutoreload(BTIM_TypeDef* BTIMx); +uint16_t BTIM_GetPrescaler(BTIM_TypeDef* BTIMx); +FlagStatus BTIM_GetFlagStatus(BTIM_TypeDef* BTIMx, uint16_t BTIM_FLAG); +void BTIM_ClearFlag(BTIM_TypeDef* BTIMx, uint16_t BTIM_FLAG); +ITStatus BTIM_GetITStatus(BTIM_TypeDef* BTIMx, uint16_t BTIM_IT); +void BTIM_ClearITPendingBit(BTIM_TypeDef* BTIMx, uint16_t BTIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_BTIM_H */ +/** + * @} + */ diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_crc.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_crc.h new file mode 100644 index 0000000..9c47c54 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_crc.h @@ -0,0 +1,91 @@ +/** + * @file cw32f030_crc.h + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-13 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F03x_CRC_H__ +#define __CW32F03x_CRC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#include "base_types.h" +#include "cw32f030.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +//============================================================ + + +uint16_t CRC16_Calc_8bit( uint8_t CrcMode , uint8_t *pByteBuf , uint16_t ByteCnt ); +uint16_t CRC16_Calc_16bit( uint8_t CrcMode , uint16_t *pHWBuf , uint16_t HalfWordCnt ); +uint16_t CRC16_Calc_32bit( uint8_t CrcMode , uint32_t *pWBuf , uint16_t WordCnt ); + +uint32_t CRC32_Calc_8bit( uint8_t CrcMode , uint8_t *pByteBuf , uint16_t ByteCnt ); +uint32_t CRC32_Calc_16bit( uint8_t CrcMode , uint16_t *pHWBuf , uint16_t HalfWordCnt ); +uint32_t CRC32_Calc_32bit( uint8_t CrcMode , uint32_t *pWBuf , uint16_t WordCnt ); + + +//============================================================ + +#define CRC16_IBM 0x00UL +#define CRC16_MAXIM 0x01UL +#define CRC16_USB 0x02UL +#define CRC16_MODBUS 0x03UL +#define CRC16_CCITT 0x04UL +#define CRC16_CCITTFALSE 0x05UL +#define CRC16_X25 0x06UL +#define CRC16_XMODEM 0x07UL +#define CRC32_DEFAULT 0x08UL +#define CRC32_MPEG2 0x09UL + + +#define IS_CRC_CRC16_MODE(MODE) (((MODE) == CRC16_IBM) || \ + ((MODE) == CRC16_MAXIM) || \ + ((MODE) == CRC16_USB) || \ + ((MODE) == CRC16_MODBUS) || \ + ((MODE) == CRC16_CCITT) || \ + ((MODE) == CRC16_CCITTFALSE) || \ + ((MODE) == CRC16_X25) || \ + ((MODE) == CRC16_XMODEM)) +#define IS_CRC_CRC32_MODE(MODE) (((MODE) == CRC32_DEFAULT) || \ + ((MODE) == CRC32_MPEG2)) + +//============================================================ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_debug.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_debug.h new file mode 100644 index 0000000..7344709 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_debug.h @@ -0,0 +1,71 @@ +/** + * @file cw32f030_debug.h + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-13 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F03x_DEBUG_H__ +#define __CW32F03x_DEBUG_H__ + + +#ifdef __cplusplus + extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#include "base_types.h" +#include "cw32f030.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +//============================================================ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); + + +#define DBGMCU_ATIM_STOP ((uint32_t)0x00000001) +#define DBGMCU_GTIM1_STOP ((uint32_t)0x00000002) +#define DBGMCU_GTIM2_STOP ((uint32_t)0x00000004) +#define DBGMCU_GTIM3_STOP ((uint32_t)0x00000008) +#define DBGMCU_GTIM4_STOP ((uint32_t)0x00000010) +#define DBGMCU_BTIM123_STOP ((uint32_t)0x00000020) +#define DBGMCU_AWT_STOP ((uint32_t)0x00000040) +#define DBGMCU_RTC_STOP ((uint32_t)0x00000100) +#define DBGMCU_IWDT_STOP ((uint32_t)0x00000200) +#define DBGMCU_WWDT_STOP ((uint32_t)0x00000400) +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFF880) == 0x00) && ((PERIPH) != 0x00)) + + +//============================================================ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_digitalsign.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_digitalsign.h new file mode 100644 index 0000000..b31d43f --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_digitalsign.h @@ -0,0 +1,79 @@ +/** + * @file cw32f030_digitalsign.h + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-14 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F03x_DIGITALSIGN_H__ +#define __CW32F03x_DIGITALSIGN_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "base_types.h" +#include "cw32f030.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +//============================================================ + +#define DIGITALSIGN_BASE 0x00012610UL + +#define CHIP_TYPE_BASE 0x00012610UL +#define PIN_COUNT_BASE 0x00012626UL +#define FLASH_SIZE_BASE 0x00012628UL +#define RAM_SIZE_BASE 0x0001262CUL + +#define CHIP_UID_BASE 0x001007E8UL + +#define CHIP_TYPE_LENGTH 22 +#define CHIP_UID_LENGTH 10 +//============================================================ + +//ȡоƬͺ// +void DIGITALSIGN_GetChipType(uint8_t *pChipType); +//ȡܽ// +uint16_t DIGITALSIGN_GetPinCount(void); +//ȡFLASH// +uint32_t DIGITALSIGN_GetFlashSize(void); +//ȡRAM// +uint32_t DIGITALSIGN_GetRamSize(void); +//ȡоƬUID// +void DIGITALSIGN_GetChipUid(uint8_t *pChipUid); + +//============================================================ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_dma.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_dma.h new file mode 100644 index 0000000..230046e --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_dma.h @@ -0,0 +1,257 @@ +/** + * @file cw32f030_dma.h + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-17 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F03x_DMA_H__ +#define __CW32F03x_DMA_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +//============================================================ +typedef struct +{ + uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of */ + uint32_t DMA_TransferWidth; ///transfer data width + uint32_t DMA_SrcInc; /*!< Specifies whether the SRC address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + uint32_t DMA_DstInc; /*!< Specifies whether the DST address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + uint32_t TrigMode ; + + uint32_t HardTrigSource ; + + uint32_t DMA_TransferCnt; ///< Transfer counter + + uint32_t DMA_SrcAddress; ///< Source address> + + uint32_t DMA_DstAddress; ///< Dest address> + +}DMA_InitTypeDef; + + +#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == CW_DMACHANNEL1) || \ + ((PERIPH) == CW_DMACHANNEL2) || \ + ((PERIPH) == CW_DMACHANNEL3) || \ + ((PERIPH) == CW_DMACHANNEL4) || \ + ((PERIPH) == CW_DMACHANNEL5)) + +#define DMA_MODE_BULK 0x00UL +#define DMA_MODE_BLOCK 0x08UL +#define IS_DMA_MODE(MODE) (((MODE) == DMA_MODE_BULK) || \ + ((MODE) == DMA_MODE_BLOCK)) + +#define DMA_SrcAddress_Fix 0x00UL +#define DMA_SrcAddress_Increase 0x10UL +#define IS_DMA_SRCADDRESS_INC(INSTRANCE) (((INSTRANCE) == DMA_SrcAddress_Increase) || \ + ((INSTRANCE) == DMA_SrcAddress_Fix)) + +#define DMA_DstAddress_Fix 0x00UL +#define DMA_DstAddress_Increase 0x20UL +#define IS_DMA_DSTADDRESS_INC(INSTRANCE) (((INSTRANCE) == DMA_DstAddress_Increase) || \ + ((INSTRANCE) == DMA_DstAddress_Fix)) + +#define DMA_TRANSFER_WIDTH_8BIT 0x00UL +#define DMA_TRANSFER_WIDTH_16BIT 0x40UL +#define DMA_TRANSFER_WIDTH_32BIT 0x80UL +#define IS_DMA_TRANSFER_WIDTH(INSTRANCE) (((INSTRANCE) == DMA_TRANSFER_WIDTH_8BIT) || \ + ((INSTRANCE) == DMA_TRANSFER_WIDTH_16BIT) || \ + ((INSTRANCE) == DMA_TRANSFER_WIDTH_32BIT)) + +#define IS_DMA_TRANSFERCNT(CNT) (((CNT)>= 1) && ((CNT)<= 65535)) + +#define DMA_SWTrig 0x00UL +#define DMA_HardTrig 0x01UL +#define IS_DMA_TRIG(TRIG) (((TRIG) == DMA_SWTrig) || \ + ((TRIG) == DMA_HardTrig)) + +#define DMA_HardTrig_UART1_RXBufferNE (uint32_t)(0x00UL << 2) +#define DMA_HardTrig_UART1_TXBufferE (uint32_t)(0x01UL << 2) +#define DMA_HardTrig_UART2_RXBufferNE (uint32_t)(0x02UL << 2) +#define DMA_HardTrig_UART2_TXBufferE (uint32_t)(0x03UL << 2) +#define DMA_HardTrig_UART3_RXBufferNE (uint32_t)(0x04UL << 2) +#define DMA_HardTrig_UART3_TXBufferE (uint32_t)(0x05UL << 2) + +#define DMA_HardTrig_SPI1_RXBufferNE (uint32_t)(0x06UL << 2) +#define DMA_HardTrig_SPI1_TXBufferE (uint32_t)(0x07UL << 2) +#define DMA_HardTrig_SPI2_RXBufferNE (uint32_t)(0x08UL << 2) +#define DMA_HardTrig_SPI2_TXBufferE (uint32_t)(0x09UL << 2) + +#define DMA_HardTrig_ADC_TRANSCOMPLETE (uint32_t)(0x0AUL << 2) + +#define DMA_HardTrig_BTIM1_OVERINT (uint32_t)(0x0BUL << 2) +#define DMA_HardTrig_BTIM1_TRIGINT (uint32_t)(0x0CUL << 2) +#define DMA_HardTrig_BTIM2_OVERINT (uint32_t)(0x0DUL << 2) +#define DMA_HardTrig_BTIM2_TRIGINT (uint32_t)(0x0EUL << 2) +#define DMA_HardTrig_BTIM3_OVERINT (uint32_t)(0x0FUL << 2) +#define DMA_HardTrig_BTIM3_TRIGINT (uint32_t)(0x10UL << 2) + +#define DMA_HardTrig_ATIM_CH1A2A3A4 (uint32_t)(0x11UL << 2) +#define DMA_HardTrig_ATIM_CH1B2B3B (uint32_t)(0x12UL << 2) + +#define DMA_HardTrig_GTIM1_OVERINT (uint32_t)(0x13UL << 2) +#define DMA_HardTrig_GTIM1_TRIGINT (uint32_t)(0x14UL << 2) +#define DMA_HardTrig_GTIM1_CH1COMINT (uint32_t)(0x15UL << 2) +#define DMA_HardTrig_GTIM1_CH2COMINT (uint32_t)(0x16UL << 2) +#define DMA_HardTrig_GTIM1_CH3COMINT (uint32_t)(0x17UL << 2) +#define DMA_HardTrig_GTIM1_CH4COMINT (uint32_t)(0x18UL << 2) + +#define DMA_HardTrig_GTIM2_OVERINT (uint32_t)(0x19UL << 2) +#define DMA_HardTrig_GTIM2_TRIGINT (uint32_t)(0x1AUL << 2) +#define DMA_HardTrig_GTIM2_CH1COMINT (uint32_t)(0x1BUL << 2) +#define DMA_HardTrig_GTIM2_CH2COMINT (uint32_t)(0x1CUL << 2) +#define DMA_HardTrig_GTIM2_CH3COMINT (uint32_t)(0x1DUL << 2) +#define DMA_HardTrig_GTIM2_CH4COMINT (uint32_t)(0x1EUL << 2) + +#define DMA_HardTrig_GTIM3_OVERINT (uint32_t)(0x1FUL << 2) +#define DMA_HardTrig_GTIM3_TRIGINT (uint32_t)(0x20UL << 2) +#define DMA_HardTrig_GTIM3_CH1COMINT (uint32_t)(0x21UL << 2) +#define DMA_HardTrig_GTIM3_CH2COMINT (uint32_t)(0x22UL << 2) +#define DMA_HardTrig_GTIM3_CH3COMINT (uint32_t)(0x23UL << 2) +#define DMA_HardTrig_GTIM3_CH4COMINT (uint32_t)(0x24UL << 2) + +#define DMA_HardTrig_GTIM4_OVERINT (uint32_t)(0x25UL << 2) +#define DMA_HardTrig_GTIM4_TRIGINT (uint32_t)(0x26UL << 2) +#define DMA_HardTrig_GTIM4_CH1COMINT (uint32_t)(0x27UL << 2) +#define DMA_HardTrig_GTIM4_CH2COMINT (uint32_t)(0x28UL << 2) +#define DMA_HardTrig_GTIM4_CH3COMINT (uint32_t)(0x29UL << 2) +#define DMA_HardTrig_GTIM4_CH4COMINT (uint32_t)(0x2AUL << 2) + +#define IS_DMA_HARD_TRIGSRC(TRIGSRC) (((TRIGSRC) == DMA_HardTrig_UART1_RXBufferNE)|| \ + ((TRIGSRC) == DMA_HardTrig_UART1_TXBufferE)|| \ + ((TRIGSRC) == DMA_HardTrig_UART2_RXBufferNE)|| \ + ((TRIGSRC) == DMA_HardTrig_UART2_TXBufferE)|| \ + ((TRIGSRC) == DMA_HardTrig_UART3_RXBufferNE)|| \ + ((TRIGSRC) == DMA_HardTrig_UART3_TXBufferE)|| \ + ((TRIGSRC) == DMA_HardTrig_SPI1_RXBufferNE)|| \ + ((TRIGSRC) == DMA_HardTrig_SPI1_TXBufferE)|| \ + ((TRIGSRC) == DMA_HardTrig_SPI2_RXBufferNE)|| \ + ((TRIGSRC) == DMA_HardTrig_SPI2_TXBufferE)|| \ + ((TRIGSRC) == DMA_HardTrig_ADC_TRANSCOMPLETE)|| \ + ((TRIGSRC) == DMA_HardTrig_BTIM1_OVERINT)|| \ + ((TRIGSRC) == DMA_HardTrig_BTIM1_TRIGINT)|| \ + ((TRIGSRC) == DMA_HardTrig_BTIM2_OVERINT)|| \ + ((TRIGSRC) == DMA_HardTrig_BTIM2_TRIGINT)|| \ + ((TRIGSRC) == DMA_HardTrig_BTIM3_OVERINT)|| \ + ((TRIGSRC) == DMA_HardTrig_BTIM3_TRIGINT)|| \ + ((TRIGSRC) == DMA_HardTrig_ATIM_CH1A2A3A4)|| \ + ((TRIGSRC) == DMA_HardTrig_ATIM_CH1B2B3B)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM1_OVERINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM1_TRIGINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM1_CH1COMINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM1_CH2COMINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM1_CH3COMINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM1_CH4COMINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM2_OVERINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM2_TRIGINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM2_CH1COMINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM2_CH2COMINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM2_CH3COMINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM2_CH4COMINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM3_OVERINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM3_TRIGINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM3_CH1COMINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM3_CH2COMINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM3_CH3COMINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM3_CH4COMINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM4_OVERINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM4_TRIGINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM4_CH1COMINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM4_CH2COMINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM4_CH3COMINT)|| \ + ((TRIGSRC) == DMA_HardTrig_GTIM4_CH4COMINT)) + + +#define DMA_CHANNEL_EN bv0 //DMA CHANNEL ENABLE +#define DMA_SOFTTRIG_EN bv1 //Soft Trig Trans Start Now +#define CSR_CLEAR_Mask (uint32_t)0xFFFFFF07 +#define TRIG_CLEAR_Mask (uint32_t)0xFFFFFF00 +#define CNT_CLEAR_Mask (uint32_t)0xFFFF0000 + +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_TE ((uint32_t)0x00000004) +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF9) == 0x00) && ((IT) != 0x00)) + +#define DMA_IT_TC1 ((uint32_t)0x00000001) +#define DMA_IT_TE1 ((uint32_t)0x00000002) +#define DMA_IT_TC2 ((uint32_t)0x00000010) +#define DMA_IT_TE2 ((uint32_t)0x00000020) +#define DMA_IT_TC3 ((uint32_t)0x00000100) +#define DMA_IT_TE3 ((uint32_t)0x00000200) +#define DMA_IT_TC4 ((uint32_t)0x00001000) +#define DMA_IT_TE4 ((uint32_t)0x00002000) +#define DMA_IT_TC5 ((uint32_t)0x00010000) +#define DMA_IT_TE5 ((uint32_t)0x00020000) +#define DMA_IT_ALL ((uint32_t)0x00033333) + +#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xFFFCCCCC) == 0x00) && ((IT) != 0x00)) +#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TC1) || ((IT) == DMA_IT_TE1) || \ + ((IT) == DMA_IT_TC2) || ((IT) == DMA_IT_TE2) || \ + ((IT) == DMA_IT_TC3) || ((IT) == DMA_IT_TE3) || \ + ((IT) == DMA_IT_TC4) || ((IT) == DMA_IT_TE4) || \ + ((IT) == DMA_IT_TC5) || ((IT) == DMA_IT_TE5)) + + +#define DMA_CHANNEL_STATUS_INIT ((uint8_t)0x00) +#define DMA_CHANNEL_STATUS_ADDRESSOUTRANGE ((uint8_t)0x01) +#define DMA_CHANNEL_STATUS_STOPREQ ((uint8_t)0x02) +#define DMA_CHANNEL_STATUS_SRCADDERR ((uint8_t)0x03) +#define DMA_CHANNEL_STATUS_DSTADDERR ((uint8_t)0x04) +#define DMA_CHANNEL_STATUS_TRANSCOMPLETE ((uint8_t)0x05) + +//============================================================ + +void DMA_DeInit(DMACHANNEL_TypeDef* DMAy_Channelx); +void DMA_Init(DMACHANNEL_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMACHANNEL_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_SWTrigCmd(DMACHANNEL_TypeDef* DMAy_Channelx); +void DMA_ITConfig(DMACHANNEL_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); +uint8_t DMA_GetFlagStatus(DMACHANNEL_TypeDef* DMAy_Channelx); + +//============================================================ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_flash.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_flash.h new file mode 100644 index 0000000..adc402f --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_flash.h @@ -0,0 +1,162 @@ +/** + * @file cw32f030_flash.h + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-13 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F03x_FLASH_H__ +#define __CW32F03x_FLASH_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "base_types.h" +#include "cw32f030.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +//============================================================ + +/** @defgroup FLASH״̬ + * @{ + */ +#define FLASH_FLAG_OK (0UL) +#define FLASH_FLAG_BSY (bv5) /*!< FLASH Busy flag */ +#define FLASH_FLAG_PGERR (bv4) /*!< FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR (bv1) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PCERR (bv0) /*!< FLASH PC error flag */ +#define FLASH_ERROR_ADDR 0x80 + +/** @defgroup ʱ + * @{ + */ +#define FLASH_Latency_1 ((uint32_t)0x00000000) /*!< FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000001) /*!< FLASH Two Latency cycles */ +#define FLASH_Latency_3 ((uint32_t)0x00000002) /*!< FLASH THREE Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2) || \ + ((LATENCY) == FLASH_Latency_3)) + +/** @defgroup FETCH + * @{ + */ +#define FLASH_Prefetch_Enable ((uint32_t)0x00000008) /*!< FLASH Prefetch Enable */ +#define FLASH_Prefetch_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Disable */ +#define IS_FLASH_PREFETCH_STATE(STATE) (((STATE) == FLASH_Prefetch_Enable) || \ + ((STATE) == FLASH_Prefetch_Disable)) + +/** @defgroup CACHE + * @{ + */ +#define FLASH_Cache_Enable ((uint32_t)0x00000010) /*!< FLASH Buffer Enable */ +#define FLASH_Cache_Disable ((uint32_t)0x00000000) /*!< FLASH Buffer Disable */ +#define IS_FLASH_CACHE_STATE(STATE) (((STATE) == FLASH_Cache_Enable) || \ + ((STATE) == FLASH_Cache_Disable)) + +/** @defgroup ȼ + * @{ + */ +#define FLASH_RDLEVEL0 ((uint16_t)0x00) +#define FLASH_RDLEVEL1 ((uint16_t)0x01) +#define FLASH_RDLEVEL2 ((uint16_t)0x02) +#define FLASH_RDLEVEL3 ((uint16_t)0x03) +#define IS_FLASH_RDLEVEL(LEVEL) (((LEVEL) == FLASH_RDLEVEL0) || \ + ((LEVEL) == FLASH_RDLEVEL1) || \ + ((LEVEL) == FLASH_RDLEVEL2) || \ + ((LEVEL) == FLASH_RDLEVEL3)) + +/** @defgroup жϱ־λ + * @{ + */ +#define FLASH_IT_PROG (bv4) +#define FLASH_IT_PAGELOCK (bv1) +#define FLASH_IT_PC (bv0) +#define IS_FLASH_IT(IT) (((IT) & 0xFFFFFFEC == 0x0UL) && ((IT) != 0x0UL)) +#define IS_FLASH_GET_IT(IT) (((IT) == FLASH_IT_PROG) || \ + ((IT) == FLASH_IT_PAGELOCK) || \ + ((IT) == FLASH_IT_PC)) + + /** @defgroup FLASHҳ + * @{ + */ +#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Pages */ +#define IS_FLASH_PAGE_Number(PAGENUMBER) (((PAGENUMBER) >= 0) && ((PAGENUMBER) <= 127)) +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x00000000) && ((ADDRESS) < 0x00010000)) + +//============================================================ +//FLASH +void FLASH_SetLatency( uint32_t FLASH_Latency ); +//Ԥȡʹ +void FLASH_PrefetchCmd(uint32_t FLASH_Prefetch); +//BUFFERʹ +void FLASH_CacheCmd(uint32_t FLASH_Buffer); +//ȡFLASHFetch״̬ +FlagStatus FLASH_GetPrefetchStatus(void); +//ȡFLASHCache״̬ +FlagStatus FLASH_GetCacheStatus(void); +//ȡFLASHĶȼ +uint8_t FLASH_GetReadOutLevel( void ); +//FLASHĶȼ +void FLASH_SetReadOutLevel( uint16_t RdLevel ); +//FLASHҳ +void FLASH_UnlockAllPages(void); +//FLASHҳ +void FLASH_LockAllPages( void ); +//FLASHָҳ棺ҳŽ0~127 +uint8_t FLASH_UnlockPage( uint8_t Page_Number ); +//FLASHָҳ棺ʼַֹ +uint8_t FLASH_UnlockPages( uint32_t StartAddr , uint32_t EndAddr ); +//FLASHָҳ棺ҳŲ0~127 +uint8_t FLASH_ErasePage( uint8_t Page_Number ); +//FLASHָҳ棺ʼַֹ +uint8_t FLASH_ErasePages( uint32_t StartAddr , uint32_t EndAddr ); +//ַָʼдһȵݣֽд +uint8_t FLASH_WirteBytes( uint32_t WriteAddr, uint8_t *pWrBuf , uint16_t WrByteCnt ); +//FLASHָҳ棺ҳ0~127 +uint8_t FLASH_LockPage( uint8_t Page_Number ); +//FLASHָҳ棺ʼַֹ +uint8_t FLASH_LockPages( uint32_t StartAddr , uint32_t EndAddr ); +//FLASHָжʹ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +//ȡָFLASHжϱ־λ +ITStatus FLASH_GetITStatus(uint32_t FLASH_IT); +//ָFLASHжϱ־λ +void FLASH_ClearITPendingBit(uint32_t FLASH_IT); +//ȡFLASHģ鵱ǰ״̬// +uint32_t FLASH_GetStatus(void); + +//============================================================ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_gpio.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_gpio.h new file mode 100644 index 0000000..4785f0f --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_gpio.h @@ -0,0 +1,1082 @@ +#ifndef __CW32F03x_GPIO_H__ +#define __CW32F03x_GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + /*****************************************************************************/ + /* Include files */ + /*****************************************************************************/ + +#include "base_types.h" +#include "cw32f030.h" + + /*****************************************************************************/ + /* Global pre-processor symbols/macros ('#define') */ + /*****************************************************************************/ + + typedef struct + { + uint32_t Pins; + uint32_t Mode; + uint32_t IT; + uint32_t Speed; + } GPIO_InitTypeDef; + + typedef enum + { + GPIO_Pin_RESET = 0, + GPIO_Pin_SET + } GPIO_PinState; + + //============================================================ + + void GPIO_SWD2GPIO(void); + void GPIO_GPIO2SWD(void); + void GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pins); + void GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pins); + void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); + void GPIO_ConfigFilter(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pins, uint32_t FltClk); + void GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pins, GPIO_PinState PinState); + void GPIO_HighByte_Write(GPIO_TypeDef *GPIOx, uint8_t Value); + void GPIO_LowByte_Write(GPIO_TypeDef *GPIOx, uint8_t Value); + void GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pins); + GPIO_PinState GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); + + //============================================================ + +#define GPIO_MODE_ANALOG (0X00) +#define GPIO_MODE_INPUT (0x10) +#define GPIO_MODE_INPUT_PULLUP (0x11) +#define GPIO_MODE_INPUT_PULLDOWN (0x12) +#define GPIO_MODE_OUTPUT_PP (0x20) +#define GPIO_MODE_OUTPUT_OD (0x21) + +#define GPIO_IT_NONE (0x80) +#define GPIO_IT_RISING (0x81) +#define GPIO_IT_FALLING (0x82) +#define GPIO_IT_HIGH (0x84) +#define GPIO_IT_LOW (0x88) + +#define GPIO_SPEED_LOW (0x0000) +#define GPIO_SPEED_HIGH (0xFFFF) + + //============================================================ + +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +//============================================================ +//˿˲ +#define GPIO_FLTCLK_HCLK2 (((uint32_t)0) << 16) +#define GPIO_FLTCLK_HCLK4 (((uint32_t)1) << 16) +#define GPIO_FLTCLK_HCLK8 (((uint32_t)2) << 16) +#define GPIO_FLTCLK_BTIM1OV (((uint32_t)3) << 16) +#define GPIO_FLTCLK_RC150K (((uint32_t)4) << 16) +#define GPIO_FLTCLK_LSI (((uint32_t)5) << 16) +#define GPIO_FLTCLK_RC10K (((uint32_t)6) << 16) + +//============================================================ +//CW_GPIOжϱ־ +#define GPIOA_INTFLAG_CLR(Mask) ((CW_GPIOA->ICR) = (~((uint32_t)(Mask)))) +#define GPIOB_INTFLAG_CLR(Mask) ((CW_GPIOB->ICR) = (~((uint32_t)(Mask)))) +#define GPIOC_INTFLAG_CLR(Mask) ((CW_GPIOC->ICR) = (~((uint32_t)(Mask)))) +#define GPIOF_INTFLAG_CLR(Mask) ((CW_GPIOF->ICR) = (~((uint32_t)(Mask)))) + +//============================================================ +//ANALOG OR DIGTAL +#define PA00_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN0 = 0) +#define PA00_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN0 = 1) +#define PA01_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN1 = 0) +#define PA01_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN1 = 1) +#define PA02_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN2 = 0) +#define PA02_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN2 = 1) +#define PA03_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN3 = 0) +#define PA03_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN3 = 1) +#define PA04_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN4 = 0) +#define PA04_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN4 = 1) +#define PA05_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN5 = 0) +#define PA05_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN5 = 1) +#define PA06_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN6 = 0) +#define PA06_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN6 = 1) +#define PA07_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN7 = 0) +#define PA07_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN7 = 1) +#define PA08_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN8 = 0) +#define PA08_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN8 = 1) +#define PA09_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN9 = 0) +#define PA09_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN9 = 1) +#define PA10_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN10 = 0) +#define PA10_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN10 = 1) +#define PA11_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN11 = 0) +#define PA11_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN11 = 1) +#define PA12_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN12 = 0) +#define PA12_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN12 = 1) +#define PA13_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN13 = 0) +#define PA13_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN13 = 1) +#define PA14_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN14 = 0) +#define PA14_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN14 = 1) +#define PA15_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN15 = 0) +#define PA15_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN15 = 1) +#define PB00_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN0 = 0) +#define PB00_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN0 = 1) +#define PB01_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN1 = 0) +#define PB01_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN1 = 1) +#define PB02_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN2 = 0) +#define PB02_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN2 = 1) +#define PB03_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN3 = 0) +#define PB03_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN3 = 1) +#define PB04_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN4 = 0) +#define PB04_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN4 = 1) +#define PB05_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN5 = 0) +#define PB05_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN5 = 1) +#define PB06_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN6 = 0) +#define PB06_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN6 = 1) +#define PB07_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN7 = 0) +#define PB07_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN7 = 1) +#define PB08_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN8 = 0) +#define PB08_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN8 = 1) +#define PB09_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN9 = 0) +#define PB09_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN9 = 1) +#define PB10_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN10 = 0) +#define PB10_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN10 = 1) +#define PB11_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN11 = 0) +#define PB11_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN11 = 1) +#define PB12_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN12 = 0) +#define PB12_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN12 = 1) +#define PB13_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN13 = 0) +#define PB13_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN13 = 1) +#define PB14_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN14 = 0) +#define PB14_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN14 = 1) +#define PB15_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN15 = 0) +#define PB15_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN15 = 1) +#define PC13_DIGTAL_ENABLE() (CW_GPIOC->ANALOG_f.PIN13 = 0) +#define PC13_ANALOG_ENABLE() (CW_GPIOC->ANALOG_f.PIN13 = 1) +#define PC14_DIGTAL_ENABLE() (CW_GPIOC->ANALOG_f.PIN14 = 0) +#define PC14_ANALOG_ENABLE() (CW_GPIOC->ANALOG_f.PIN14 = 1) +#define PC15_DIGTAL_ENABLE() (CW_GPIOC->ANALOG_f.PIN15 = 0) +#define PC15_ANALOG_ENABLE() (CW_GPIOC->ANALOG_f.PIN15 = 1) +#define PF00_DIGTAL_ENABLE() (CW_GPIOF->ANALOG_f.PIN0 = 0) +#define PF00_ANALOG_ENABLE() (CW_GPIOF->ANALOG_f.PIN0 = 1) +#define PF01_DIGTAL_ENABLE() (CW_GPIOF->ANALOG_f.PIN1 = 0) +#define PF01_ANALOG_ENABLE() (CW_GPIOF->ANALOG_f.PIN1 = 1) +#define PF06_DIGTAL_ENABLE() (CW_GPIOF->ANALOG_f.PIN6 = 0) +#define PF06_ANALOG_ENABLE() (CW_GPIOF->ANALOG_f.PIN6 = 1) +#define PF07_DIGTAL_ENABLE() (CW_GPIOF->ANALOG_f.PIN7 = 0) +#define PF07_ANALOG_ENABLE() (CW_GPIOF->ANALOG_f.PIN7 = 1) +#define PF03_DIGTAL_ENABLE() (CW_GPIOF->ANALOG_f.PIN3 = 0) +#define PF03_ANALOG_ENABLE() (CW_GPIOF->ANALOG_f.PIN3 = 1) + +//============================================================ +// INPUTAND OUTPUT +#define PA00_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN0 = 0) +#define PA00_DIR_INPUT() (CW_GPIOA->DIR_f.PIN0 = 1) +#define PA01_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN1 = 0) +#define PA01_DIR_INPUT() (CW_GPIOA->DIR_f.PIN1 = 1) +#define PA02_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN2 = 0) +#define PA02_DIR_INPUT() (CW_GPIOA->DIR_f.PIN2 = 1) +#define PA03_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN3 = 0) +#define PA03_DIR_INPUT() (CW_GPIOA->DIR_f.PIN3 = 1) +#define PA04_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN4 = 0) +#define PA04_DIR_INPUT() (CW_GPIOA->DIR_f.PIN4 = 1) +#define PA05_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN5 = 0) +#define PA05_DIR_INPUT() (CW_GPIOA->DIR_f.PIN5 = 1) +#define PA06_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN6 = 0) +#define PA06_DIR_INPUT() (CW_GPIOA->DIR_f.PIN6 = 1) +#define PA07_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN7 = 0) +#define PA07_DIR_INPUT() (CW_GPIOA->DIR_f.PIN7 = 1) +#define PA08_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN8 = 0) +#define PA08_DIR_INPUT() (CW_GPIOA->DIR_f.PIN8 = 1) +#define PA09_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN9 = 0) +#define PA09_DIR_INPUT() (CW_GPIOA->DIR_f.PIN9 = 1) +#define PA10_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN10 = 0) +#define PA10_DIR_INPUT() (CW_GPIOA->DIR_f.PIN10 = 1) +#define PA11_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN11 = 0) +#define PA11_DIR_INPUT() (CW_GPIOA->DIR_f.PIN11 = 1) +#define PA12_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN12 = 0) +#define PA12_DIR_INPUT() (CW_GPIOA->DIR_f.PIN12 = 1) +#define PA13_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN13 = 0) +#define PA13_DIR_INPUT() (CW_GPIOA->DIR_f.PIN13 = 1) +#define PA14_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN14 = 0) +#define PA14_DIR_INPUT() (CW_GPIOA->DIR_f.PIN14 = 1) +#define PA15_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN15 = 0) +#define PA15_DIR_INPUT() (CW_GPIOA->DIR_f.PIN15 = 1) +#define PB00_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN0 = 0) +#define PB00_DIR_INPUT() (CW_GPIOB->DIR_f.PIN0 = 1) +#define PB01_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN1 = 0) +#define PB01_DIR_INPUT() (CW_GPIOB->DIR_f.PIN1 = 1) +#define PB02_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN2 = 0) +#define PB02_DIR_INPUT() (CW_GPIOB->DIR_f.PIN2 = 1) +#define PB03_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN3 = 0) +#define PB03_DIR_INPUT() (CW_GPIOB->DIR_f.PIN3 = 1) +#define PB04_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN4 = 0) +#define PB04_DIR_INPUT() (CW_GPIOB->DIR_f.PIN4 = 1) +#define PB05_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN5 = 0) +#define PB05_DIR_INPUT() (CW_GPIOB->DIR_f.PIN5 = 1) +#define PB06_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN6 = 0) +#define PB06_DIR_INPUT() (CW_GPIOB->DIR_f.PIN6 = 1) +#define PB07_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN7 = 0) +#define PB07_DIR_INPUT() (CW_GPIOB->DIR_f.PIN7 = 1) +#define PB08_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN8 = 0) +#define PB08_DIR_INPUT() (CW_GPIOB->DIR_f.PIN8 = 1) +#define PB09_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN9 = 0) +#define PB09_DIR_INPUT() (CW_GPIOB->DIR_f.PIN9 = 1) +#define PB10_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN10 = 0) +#define PB10_DIR_INPUT() (CW_GPIOB->DIR_f.PIN10 = 1) +#define PB11_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN11 = 0) +#define PB11_DIR_INPUT() (CW_GPIOB->DIR_f.PIN11 = 1) +#define PB12_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN12 = 0) +#define PB12_DIR_INPUT() (CW_GPIOB->DIR_f.PIN12 = 1) +#define PB13_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN13 = 0) +#define PB13_DIR_INPUT() (CW_GPIOB->DIR_f.PIN13 = 1) +#define PB14_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN14 = 0) +#define PB14_DIR_INPUT() (CW_GPIOB->DIR_f.PIN14 = 1) +#define PB15_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN15 = 0) +#define PB15_DIR_INPUT() (CW_GPIOB->DIR_f.PIN15 = 1) +#define PC13_DIR_OUTPUT() (CW_GPIOC->DIR_f.PIN13 = 0) +#define PC13_DIR_INPUT() (CW_GPIOC->DIR_f.PIN13 = 1) +#define PC14_DIR_OUTPUT() (CW_GPIOC->DIR_f.PIN14 = 0) +#define PC14_DIR_INPUT() (CW_GPIOC->DIR_f.PIN14 = 1) +#define PC15_DIR_OUTPUT() (CW_GPIOC->DIR_f.PIN15 = 0) +#define PC15_DIR_INPUT() (CW_GPIOC->DIR_f.PIN15 = 1) +#define PF00_DIR_OUTPUT() (CW_GPIOF->DIR_f.PIN0 = 0) +#define PF00_DIR_INPUT() (CW_GPIOF->DIR_f.PIN0 = 1) +#define PF01_DIR_OUTPUT() (CW_GPIOF->DIR_f.PIN1 = 0) +#define PF01_DIR_INPUT() (CW_GPIOF->DIR_f.PIN1 = 1) +#define PF06_DIR_OUTPUT() (CW_GPIOF->DIR_f.PIN6 = 0) +#define PF06_DIR_INPUT() (CW_GPIOF->DIR_f.PIN6 = 1) +#define PF07_DIR_OUTPUT() (CW_GPIOF->DIR_f.PIN7 = 0) +#define PF07_DIR_INPUT() (CW_GPIOF->DIR_f.PIN7 = 1) +#define PF03_DIR_OUTPUT() (CW_GPIOF->DIR_f.PIN3 = 0) +#define PF03_DIR_INPUT() (CW_GPIOF->DIR_f.PIN3 = 1) + +//============================================================ +//push-pull or opendrain +#define PA00_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN0 = 0) +#define PA00_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN0 = 1) +#define PA01_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN1 = 0) +#define PA01_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN1 = 1) +#define PA02_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN2 = 0) +#define PA02_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN2 = 1) +#define PA03_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN3 = 0) +#define PA03_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN3 = 1) +#define PA04_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN4 = 0) +#define PA04_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN4 = 1) +#define PA05_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN5 = 0) +#define PA05_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN5 = 1) +#define PA06_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN6 = 0) +#define PA06_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN6 = 1) +#define PA07_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN7 = 0) +#define PA07_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN7 = 1) +#define PA08_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN8 = 0) +#define PA08_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN8 = 1) +#define PA09_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN9 = 0) +#define PA09_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN9 = 1) +#define PA10_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN10 = 0) +#define PA10_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN10 = 1) +#define PA11_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN11 = 0) +#define PA11_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN11 = 1) +#define PA12_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN12 = 0) +#define PA12_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN12 = 1) +#define PA13_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN13 = 0) +#define PA13_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN13 = 1) +#define PA14_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN14 = 0) +#define PA14_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN14 = 1) +#define PA15_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN15 = 0) +#define PA15_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN15 = 1) +#define PB00_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN0 = 0) +#define PB00_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN0 = 1) +#define PB01_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN1 = 0) +#define PB01_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN1 = 1) +#define PB02_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN2 = 0) +#define PB02_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN2 = 1) +#define PB03_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN3 = 0) +#define PB03_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN3 = 1) +#define PB04_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN4 = 0) +#define PB04_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN4 = 1) +#define PB05_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN5 = 0) +#define PB05_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN5 = 1) +#define PB06_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN6 = 0) +#define PB06_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN6 = 1) +#define PB07_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN7 = 0) +#define PB07_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN7 = 1) +#define PB08_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN8 = 0) +#define PB08_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN8 = 1) +#define PB09_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN9 = 0) +#define PB09_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN9 = 1) +#define PB10_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN10 = 0) +#define PB10_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN10 = 1) +#define PB11_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN11 = 0) +#define PB11_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN11 = 1) +#define PB12_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN12 = 0) +#define PB12_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN12 = 1) +#define PB13_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN13 = 0) +#define PB13_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN13 = 1) +#define PB14_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN14 = 0) +#define PB14_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN14 = 1) +#define PB15_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN15 = 0) +#define PB15_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN15 = 1) +#define PC13_PUSHPULL_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN13 = 0) +#define PC13_OPENDRAIN_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN13 = 1) +#define PC14_PUSHPULL_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN14 = 0) +#define PC14_OPENDRAIN_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN14 = 1) +#define PC15_PUSHPULL_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN15 = 0) +#define PC15_OPENDRAIN_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN15 = 1) +#define PF00_PUSHPULL_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN0 = 0) +#define PF00_OPENDRAIN_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN0 = 1) +#define PF01_PUSHPULL_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN1 = 0) +#define PF01_OPENDRAIN_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN1 = 1) +#define PF06_PUSHPULL_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN6 = 0) +#define PF06_OPENDRAIN_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN6 = 1) +#define PF07_PUSHPULL_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN7 = 0) +#define PF07_OPENDRAIN_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN7 = 1) +#define PF03_PUSHPULL_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN3 = 0) +#define PF03_OPENDRAIN_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN3 = 1) + +//============================================================ +// SPEED +#define PA00_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN0 = 0) +#define PA00_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN0 = 1) +#define PA01_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN1 = 0) +#define PA01_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN1 = 1) +#define PA02_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN2 = 0) +#define PA02_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN2 = 1) +#define PA03_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN3 = 0) +#define PA03_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN3 = 1) +#define PA04_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN4 = 0) +#define PA04_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN4 = 1) +#define PA05_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN5 = 0) +#define PA05_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN5 = 1) +#define PA06_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN6 = 0) +#define PA06_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN6 = 1) +#define PA07_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN7 = 0) +#define PA07_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN7 = 1) +#define PA08_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN8 = 0) +#define PA08_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN8 = 1) +#define PA09_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN9 = 0) +#define PA09_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN9 = 1) +#define PA10_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN10 = 0) +#define PA10_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN10 = 1) +#define PA11_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN11 = 0) +#define PA11_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN11 = 1) +#define PA12_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN12 = 0) +#define PA12_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN12 = 1) +#define PA13_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN13 = 0) +#define PA13_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN13 = 1) +#define PA14_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN14 = 0) +#define PA14_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN14 = 1) +#define PA15_SPEED_LOW() (CW_GPIOA->SPEED_f.PIN15 = 0) +#define PA15_SPEED_HIGH() (CW_GPIOA->SPEED_f.PIN15 = 1) +#define PB00_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN0 = 0) +#define PB00_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN0 = 1) +#define PB01_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN1 = 0) +#define PB01_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN1 = 1) +#define PB02_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN2 = 0) +#define PB02_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN2 = 1) +#define PB03_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN3 = 0) +#define PB03_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN3 = 1) +#define PB04_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN4 = 0) +#define PB04_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN4 = 1) +#define PB05_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN5 = 0) +#define PB05_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN5 = 1) +#define PB06_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN6 = 0) +#define PB06_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN6 = 1) +#define PB07_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN7 = 0) +#define PB07_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN7 = 1) +#define PB08_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN8 = 0) +#define PB08_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN8 = 1) +#define PB09_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN9 = 0) +#define PB09_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN9 = 1) +#define PB10_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN10 = 0) +#define PB10_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN10 = 1) +#define PB11_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN11 = 0) +#define PB11_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN11 = 1) +#define PB12_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN12 = 0) +#define PB12_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN12 = 1) +#define PB13_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN13 = 0) +#define PB13_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN13 = 1) +#define PB14_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN14 = 0) +#define PB14_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN14 = 1) +#define PB15_SPEED_LOW() (CW_GPIOB->SPEED_f.PIN15 = 0) +#define PB15_SPEED_HIGH() (CW_GPIOB->SPEED_f.PIN15 = 1) +#define PC13_SPEED_LOW() (CW_GPIOC->SPEED_f.PIN13 = 0) +#define PC13_SPEED_HIGH() (CW_GPIOC->SPEED_f.PIN13 = 1) +#define PC14_SPEED_LOW() (CW_GPIOC->SPEED_f.PIN14 = 0) +#define PC14_SPEED_HIGH() (CW_GPIOC->SPEED_f.PIN14 = 1) +#define PC15_SPEED_LOW() (CW_GPIOC->SPEED_f.PIN15 = 0) +#define PC15_SPEED_HIGH() (CW_GPIOC->SPEED_f.PIN15 = 1) +#define PF00_SPEED_LOW() (CW_GPIOF->SPEED_f.PIN0 = 0) +#define PF00_SPEED_HIGH() (CW_GPIOF->SPEED_f.PIN0 = 1) +#define PF01_SPEED_LOW() (CW_GPIOF->SPEED_f.PIN1 = 0) +#define PF01_SPEED_HIGH() (CW_GPIOF->SPEED_f.PIN1 = 1) +#define PF06_SPEED_LOW() (CW_GPIOF->SPEED_f.PIN6 = 0) +#define PF06_SPEED_HIGH() (CW_GPIOF->SPEED_f.PIN6 = 1) +#define PF07_SPEED_LOW() (CW_GPIOF->SPEED_f.PIN7 = 0) + +//============================================================ +//PUR +#define PA00_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN0 = 1) +#define PA00_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN0 = 0) +#define PA01_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN1 = 1) +#define PA01_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN1 = 0) +#define PA02_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN2 = 1) +#define PA02_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN2 = 0) +#define PA03_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN3 = 1) +#define PA03_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN3 = 0) +#define PA04_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN4 = 1) +#define PA04_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN4 = 0) +#define PA05_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN5 = 1) +#define PA05_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN5 = 0) +#define PA06_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN6 = 1) +#define PA06_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN6 = 0) +#define PA07_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN7 = 1) +#define PA07_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN7 = 0) +#define PA08_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN8 = 1) +#define PA08_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN8 = 0) +#define PA09_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN9 = 1) +#define PA09_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN9 = 0) +#define PA10_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN10 = 1) +#define PA10_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN10 = 0) +#define PA11_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN11 = 1) +#define PA11_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN11 = 0) +#define PA12_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN12 = 1) +#define PA12_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN12 = 0) +#define PA13_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN13 = 1) +#define PA13_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN13 = 0) +#define PA14_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN14 = 1) +#define PA14_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN14 = 0) +#define PA15_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN15 = 1) +#define PA15_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN15 = 0) +#define PB00_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN0 = 1) +#define PB00_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN0 = 0) +#define PB01_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN1 = 1) +#define PB01_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN1 = 0) +#define PB02_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN2 = 1) +#define PB02_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN2 = 0) +#define PB03_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN3 = 1) +#define PB03_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN3 = 0) +#define PB04_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN4 = 1) +#define PB04_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN4 = 0) +#define PB05_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN5 = 1) +#define PB05_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN5 = 0) +#define PB06_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN6 = 1) +#define PB06_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN6 = 0) +#define PB07_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN7 = 1) +#define PB07_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN7 = 0) +#define PB08_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN8 = 1) +#define PB08_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN8 = 0) +#define PB09_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN9 = 1) +#define PB09_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN9 = 0) +#define PB10_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN10 = 1) +#define PB10_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN10 = 0) +#define PB11_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN11 = 1) +#define PB11_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN11 = 0) +#define PB12_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN12 = 1) +#define PB12_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN12 = 0) +#define PB13_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN13 = 1) +#define PB13_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN13 = 0) +#define PB14_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN14 = 1) +#define PB14_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN14 = 0) +#define PB15_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN15 = 1) +#define PB15_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN15 = 0) +#define PC13_PUR_ENABLE() (CW_GPIOC->PUR_f.PIN13 = 1) +#define PC13_PUR_DISABLE() (CW_GPIOC->PUR_f.PIN13 = 0) +#define PC14_PUR_ENABLE() (CW_GPIOC->PUR_f.PIN14 = 1) +#define PC14_PUR_DISABLE() (CW_GPIOC->PUR_f.PIN14 = 0) +#define PC15_PUR_ENABLE() (CW_GPIOC->PUR_f.PIN15 = 1) +#define PC15_PUR_DISABLE() (CW_GPIOC->PUR_f.PIN15 = 0) +#define PF00_PUR_ENABLE() (CW_GPIOF->PUR_f.PIN0 = 1) +#define PF00_PUR_DISABLE() (CW_GPIOF->PUR_f.PIN0 = 0) +#define PF01_PUR_ENABLE() (CW_GPIOF->PUR_f.PIN1 = 1) +#define PF01_PUR_DISABLE() (CW_GPIOF->PUR_f.PIN1 = 0) +#define PF06_PUR_ENABLE() (CW_GPIOF->PUR_f.PIN6 = 1) +#define PF06_PUR_DISABLE() (CW_GPIOF->PUR_f.PIN6 = 0) +#define PF07_PUR_ENABLE() (CW_GPIOF->PUR_f.PIN7 = 1) +#define PF07_PUR_DISABLE() (CW_GPIOF->PUR_f.PIN7 = 0) +#define PF03_PUR_ENABLE() (CW_GPIOF->PUR_f.PIN3 = 1) +#define PF03_PUR_DISABLE() (CW_GPIOF->PUR_f.PIN3 = 0) + +//============================================================ +//PDR +#define PA00_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN0 = 1) +#define PA00_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN0 = 0) +#define PA01_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN1 = 1) +#define PA01_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN1 = 0) +#define PA02_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN2 = 1) +#define PA02_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN2 = 0) +#define PA03_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN3 = 1) +#define PA03_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN3 = 0) +#define PA04_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN4 = 1) +#define PA04_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN4 = 0) +#define PA05_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN5 = 1) +#define PA05_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN5 = 0) +#define PA06_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN6 = 1) +#define PA06_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN6 = 0) +#define PA07_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN7 = 1) +#define PA07_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN7 = 0) +#define PA08_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN8 = 1) +#define PA08_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN8 = 0) +#define PA09_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN9 = 1) +#define PA09_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN9 = 0) +#define PA10_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN10 = 1) +#define PA10_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN10 = 0) +#define PA11_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN11 = 1) +#define PA11_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN11 = 0) +#define PA12_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN12 = 1) +#define PA12_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN12 = 0) +#define PA13_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN13 = 1) +#define PA13_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN13 = 0) +#define PA14_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN14 = 1) +#define PA14_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN14 = 0) +#define PA15_PDR_ENABLE() (CW_GPIOA->PDR_f.PIN15 = 1) +#define PA15_PDR_DISABLE() (CW_GPIOA->PDR_f.PIN15 = 0) +#define PB00_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN0 = 1) +#define PB00_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN0 = 0) +#define PB01_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN1 = 1) +#define PB01_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN1 = 0) +#define PB02_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN2 = 1) +#define PB02_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN2 = 0) +#define PB03_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN3 = 1) +#define PB03_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN3 = 0) +#define PB04_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN4 = 1) +#define PB04_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN4 = 0) +#define PB05_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN5 = 1) +#define PB05_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN5 = 0) +#define PB06_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN6 = 1) +#define PB06_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN6 = 0) +#define PB07_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN7 = 1) +#define PB07_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN7 = 0) +#define PB08_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN8 = 1) +#define PB08_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN8 = 0) +#define PB09_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN9 = 1) +#define PB09_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN9 = 0) +#define PB10_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN10 = 1) +#define PB10_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN10 = 0) +#define PB11_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN11 = 1) +#define PB11_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN11 = 0) +#define PB12_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN12 = 1) +#define PB12_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN12 = 0) +#define PB13_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN13 = 1) +#define PB13_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN13 = 0) +#define PB14_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN14 = 1) +#define PB14_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN14 = 0) +#define PB15_PDR_ENABLE() (CW_GPIOB->PDR_f.PIN15 = 1) +#define PB15_PDR_DISABLE() (CW_GPIOB->PDR_f.PIN15 = 0) +#define PC13_PDR_ENABLE() (CW_GPIOC->PDR_f.PIN13 = 1) +#define PC13_PDR_DISABLE() (CW_GPIOC->PDR_f.PIN13 = 0) +#define PC14_PDR_ENABLE() (CW_GPIOC->PDR_f.PIN14 = 1) +#define PC14_PDR_DISABLE() (CW_GPIOC->PDR_f.PIN14 = 0) +#define PC15_PDR_ENABLE() (CW_GPIOC->PDR_f.PIN15 = 1) +#define PC15_PDR_DISABLE() (CW_GPIOC->PDR_f.PIN15 = 0) +#define PF00_PDR_ENABLE() (CW_GPIOF->PDR_f.PIN0 = 1) +#define PF00_PDR_DISABLE() (CW_GPIOF->PDR_f.PIN0 = 0) +#define PF01_PDR_ENABLE() (CW_GPIOF->PDR_f.PIN1 = 1) +#define PF01_PDR_DISABLE() (CW_GPIOF->PDR_f.PIN1 = 0) +#define PF06_PDR_ENABLE() (CW_GPIOF->PDR_f.PIN6 = 1) +#define PF06_PDR_DISABLE() (CW_GPIOF->PDR_f.PIN6 = 0) +#define PF07_PDR_ENABLE() (CW_GPIOF->PDR_f.PIN7 = 1) +#define PF07_PDR_DISABLE() (CW_GPIOF->PDR_f.PIN7 = 0) +#define PF03_PDR_ENABLE() (CW_GPIOF->PDR_f.PIN3 = 1) +#define PF03_PDR_DISABLE() (CW_GPIOF->PDR_f.PIN3 = 0) + +//============================================================ +// GETVALUE +#define PA00_GETVALUE() (CW_GPIOA->IDR & bv0) +#define PA01_GETVALUE() (CW_GPIOA->IDR & bv1) +#define PA02_GETVALUE() (CW_GPIOA->IDR & bv2) +#define PA03_GETVALUE() (CW_GPIOA->IDR & bv3) +#define PA04_GETVALUE() (CW_GPIOA->IDR & bv4) +#define PA05_GETVALUE() (CW_GPIOA->IDR & bv5) +#define PA06_GETVALUE() (CW_GPIOA->IDR & bv6) +#define PA07_GETVALUE() (CW_GPIOA->IDR & bv7) +#define PA08_GETVALUE() (CW_GPIOA->IDR & bv8) +#define PA09_GETVALUE() (CW_GPIOA->IDR & bv9) +#define PA10_GETVALUE() (CW_GPIOA->IDR & bv10) +#define PA11_GETVALUE() (CW_GPIOA->IDR & bv11) +#define PA12_GETVALUE() (CW_GPIOA->IDR & bv12) +#define PA13_GETVALUE() (CW_GPIOA->IDR & bv13) +#define PA14_GETVALUE() (CW_GPIOA->IDR & bv14) +#define PA15_GETVALUE() (CW_GPIOA->IDR & bv15) +#define PB00_GETVALUE() (CW_GPIOB->IDR & bv0) +#define PB01_GETVALUE() (CW_GPIOB->IDR & bv1) +#define PB02_GETVALUE() (CW_GPIOB->IDR & bv2) +#define PB03_GETVALUE() (CW_GPIOB->IDR & bv3) +#define PB04_GETVALUE() (CW_GPIOB->IDR & bv4) +#define PB05_GETVALUE() (CW_GPIOB->IDR & bv5) +#define PB06_GETVALUE() (CW_GPIOB->IDR & bv6) +#define PB07_GETVALUE() (CW_GPIOB->IDR & bv7) +#define PB08_GETVALUE() (CW_GPIOB->IDR & bv8) +#define PB09_GETVALUE() (CW_GPIOB->IDR & bv9) +#define PB10_GETVALUE() (CW_GPIOB->IDR & bv10) +#define PB11_GETVALUE() (CW_GPIOB->IDR & bv11) +#define PB12_GETVALUE() (CW_GPIOB->IDR & bv12) +#define PB13_GETVALUE() (CW_GPIOB->IDR & bv13) +#define PB14_GETVALUE() (CW_GPIOB->IDR & bv14) +#define PB15_GETVALUE() (CW_GPIOB->IDR & bv15) +#define PC13_GETVALUE() (CW_GPIOC->IDR & bv13) +#define PC14_GETVALUE() (CW_GPIOC->IDR & bv14) +#define PC15_GETVALUE() (CW_GPIOC->IDR & bv15) +#define PF00_GETVALUE() (CW_GPIOF->IDR & bv0) +#define PF01_GETVALUE() (CW_GPIOF->IDR & bv1) +#define PF06_GETVALUE() (CW_GPIOF->IDR & bv6) +#define PF07_GETVALUE() (CW_GPIOF->IDR & bv7) +#define PF03_GETVALUE() (CW_GPIOF->IDR & bv3) + +//============================================================ +// SET HIGH AND LOW +#define PA00_SETHIGH() (CW_GPIOA->BSRR = bv0) +#define PA00_SETLOW() (CW_GPIOA->BRR = bv0) +#define PA01_SETHIGH() (CW_GPIOA->BSRR = bv1) +#define PA01_SETLOW() (CW_GPIOA->BRR = bv1) +#define PA02_SETHIGH() (CW_GPIOA->BSRR = bv2) +#define PA02_SETLOW() (CW_GPIOA->BRR = bv2) +#define PA03_SETHIGH() (CW_GPIOA->BSRR = bv3) +#define PA03_SETLOW() (CW_GPIOA->BRR = bv3) +#define PA04_SETHIGH() (CW_GPIOA->BSRR = bv4) +#define PA04_SETLOW() (CW_GPIOA->BRR = bv4) +#define PA05_SETHIGH() (CW_GPIOA->BSRR = bv5) +#define PA05_SETLOW() (CW_GPIOA->BRR = bv5) +#define PA06_SETHIGH() (CW_GPIOA->BSRR = bv6) +#define PA06_SETLOW() (CW_GPIOA->BRR = bv6) +#define PA07_SETHIGH() (CW_GPIOA->BSRR = bv7) +#define PA07_SETLOW() (CW_GPIOA->BRR = bv7) +#define PA08_SETHIGH() (CW_GPIOA->BSRR = bv8) +#define PA08_SETLOW() (CW_GPIOA->BRR = bv8) +#define PA09_SETHIGH() (CW_GPIOA->BSRR = bv9) +#define PA09_SETLOW() (CW_GPIOA->BRR = bv9) +#define PA10_SETHIGH() (CW_GPIOA->BSRR = bv10) +#define PA10_SETLOW() (CW_GPIOA->BRR = bv10) +#define PA11_SETHIGH() (CW_GPIOA->BSRR = bv11) +#define PA11_SETLOW() (CW_GPIOA->BRR = bv11) +#define PA12_SETHIGH() (CW_GPIOA->BSRR = bv12) +#define PA12_SETLOW() (CW_GPIOA->BRR = bv12) +#define PA13_SETHIGH() (CW_GPIOA->BSRR = bv13) +#define PA13_SETLOW() (CW_GPIOA->BRR = bv13) +#define PA14_SETHIGH() (CW_GPIOA->BSRR = bv14) +#define PA14_SETLOW() (CW_GPIOA->BRR = bv14) +#define PA15_SETHIGH() (CW_GPIOA->BSRR = bv15) +#define PA15_SETLOW() (CW_GPIOA->BRR = bv15) +#define PB00_SETHIGH() (CW_GPIOB->BSRR = bv0) +#define PB00_SETLOW() (CW_GPIOB->BRR = bv0) +#define PB01_SETHIGH() (CW_GPIOB->BSRR = bv1) +#define PB01_SETLOW() (CW_GPIOB->BRR = bv1) +#define PB02_SETHIGH() (CW_GPIOB->BSRR = bv2) +#define PB02_SETLOW() (CW_GPIOB->BRR = bv2) +#define PB03_SETHIGH() (CW_GPIOB->BSRR = bv3) +#define PB03_SETLOW() (CW_GPIOB->BRR = bv3) +#define PB04_SETHIGH() (CW_GPIOB->BSRR = bv4) +#define PB04_SETLOW() (CW_GPIOB->BRR = bv4) +#define PB05_SETHIGH() (CW_GPIOB->BSRR = bv5) +#define PB05_SETLOW() (CW_GPIOB->BRR = bv5) +#define PB06_SETHIGH() (CW_GPIOB->BSRR = bv6) +#define PB06_SETLOW() (CW_GPIOB->BRR = bv6) +#define PB07_SETHIGH() (CW_GPIOB->BSRR = bv7) +#define PB07_SETLOW() (CW_GPIOB->BRR = bv7) +#define PB08_SETHIGH() (CW_GPIOB->BSRR = bv8) +#define PB08_SETLOW() (CW_GPIOB->BRR = bv8) +#define PB09_SETHIGH() (CW_GPIOB->BSRR = bv9) +#define PB09_SETLOW() (CW_GPIOB->BRR = bv9) +#define PB10_SETHIGH() (CW_GPIOB->BSRR = bv10) +#define PB10_SETLOW() (CW_GPIOB->BRR = bv10) +#define PB11_SETHIGH() (CW_GPIOB->BSRR = bv11) +#define PB11_SETLOW() (CW_GPIOB->BRR = bv11) +#define PB12_SETHIGH() (CW_GPIOB->BSRR = bv12) +#define PB12_SETLOW() (CW_GPIOB->BRR = bv12) +#define PB13_SETHIGH() (CW_GPIOB->BSRR = bv13) +#define PB13_SETLOW() (CW_GPIOB->BRR = bv13) +#define PB14_SETHIGH() (CW_GPIOB->BSRR = bv14) +#define PB14_SETLOW() (CW_GPIOB->BRR = bv14) +#define PB15_SETHIGH() (CW_GPIOB->BSRR = bv15) +#define PB15_SETLOW() (CW_GPIOB->BRR = bv15) +#define PC13_SETHIGH() (CW_GPIOC->BSRR = bv13) +#define PC13_SETLOW() (CW_GPIOC->BRR = bv13) +#define PC14_SETHIGH() (CW_GPIOC->BSRR = bv14) +#define PC14_SETLOW() (CW_GPIOC->BRR = bv14) +#define PC15_SETHIGH() (CW_GPIOC->BSRR = bv15) +#define PC15_SETLOW() (CW_GPIOC->BRR = bv15) +#define PF00_SETHIGH() (CW_GPIOF->BSRR = bv0) +#define PF00_SETLOW() (CW_GPIOF->BRR = bv0) +#define PF01_SETHIGH() (CW_GPIOF->BSRR = bv1) +#define PF01_SETLOW() (CW_GPIOF->BRR = bv1) +#define PF06_SETHIGH() (CW_GPIOF->BSRR = bv6) +#define PF06_SETLOW() (CW_GPIOF->BRR = bv6) +#define PF07_SETHIGH() (CW_GPIOF->BSRR = bv7) +#define PF07_SETLOW() (CW_GPIOF->BRR = bv7) +#define PF03_SETHIGH() (CW_GPIOF->BSRR = bv3) +#define PF03_SETLOW() (CW_GPIOF->BRR = bv3) + +//============================================================ +// TOG +#define PA00_TOG() (CW_GPIOA->TOG = bv0) +#define PA01_TOG() (CW_GPIOA->TOG = bv1) +#define PA02_TOG() (CW_GPIOA->TOG = bv2) +#define PA03_TOG() (CW_GPIOA->TOG = bv3) +#define PA04_TOG() (CW_GPIOA->TOG = bv4) +#define PA05_TOG() (CW_GPIOA->TOG = bv5) +#define PA06_TOG() (CW_GPIOA->TOG = bv6) +#define PA07_TOG() (CW_GPIOA->TOG = bv7) +#define PA08_TOG() (CW_GPIOA->TOG = bv8) +#define PA09_TOG() (CW_GPIOA->TOG = bv9) +#define PA10_TOG() (CW_GPIOA->TOG = bv10) +#define PA11_TOG() (CW_GPIOA->TOG = bv11) +#define PA12_TOG() (CW_GPIOA->TOG = bv12) +#define PA13_TOG() (CW_GPIOA->TOG = bv13) +#define PA14_TOG() (CW_GPIOA->TOG = bv14) +#define PA15_TOG() (CW_GPIOA->TOG = bv15) +#define PB00_TOG() (CW_GPIOB->TOG = bv0) +#define PB01_TOG() (CW_GPIOB->TOG = bv1) +#define PB02_TOG() (CW_GPIOB->TOG = bv2) +#define PB03_TOG() (CW_GPIOB->TOG = bv3) +#define PB04_TOG() (CW_GPIOB->TOG = bv4) +#define PB05_TOG() (CW_GPIOB->TOG = bv5) +#define PB06_TOG() (CW_GPIOB->TOG = bv6) +#define PB07_TOG() (CW_GPIOB->TOG = bv7) +#define PB08_TOG() (CW_GPIOB->TOG = bv8) +#define PB09_TOG() (CW_GPIOB->TOG = bv9) +#define PB10_TOG() (CW_GPIOB->TOG = bv10) +#define PB11_TOG() (CW_GPIOB->TOG = bv11) +#define PB12_TOG() (CW_GPIOB->TOG = bv12) +#define PB13_TOG() (CW_GPIOB->TOG = bv13) +#define PB14_TOG() (CW_GPIOB->TOG = bv14) +#define PB15_TOG() (CW_GPIOB->TOG = bv15) +#define PC13_TOG() (CW_GPIOC->TOG = bv13) +#define PC14_TOG() (CW_GPIOC->TOG = bv14) +#define PC15_TOG() (CW_GPIOC->TOG = bv15) +#define PF00_TOG() (CW_GPIOF->TOG = bv0) +#define PF01_TOG() (CW_GPIOF->TOG = bv1) +#define PF06_TOG() (CW_GPIOF->TOG = bv6) +#define PF07_TOG() (CW_GPIOF->TOG = bv7) +#define PF03_TOG() (CW_GPIOF->TOG = bv3) + +//============================================================ +// AF0 - AF7 +#define PA00_AFx_GPIO() (CW_GPIOA->AFRL_f.AFR0 = 0) +#define PA00_AFx_UART3CTS() (CW_GPIOA->AFRL_f.AFR0 = 1) +#define PA00_AFx_UART2CTS() (CW_GPIOA->AFRL_f.AFR0 = 2) +#define PA00_AFx_RTCTAMP() (CW_GPIOA->AFRL_f.AFR0 = 3) +#define PA00_AFx_VC1OUT() (CW_GPIOA->AFRL_f.AFR0 = 4) +#define PA00_AFx_SPI2MISO() (CW_GPIOA->AFRL_f.AFR0 = 5) +#define PA00_AFx_GTIM2CH1() (CW_GPIOA->AFRL_f.AFR0 = 6) +#define PA00_AFx_GTIM2ETR() (CW_GPIOA->AFRL_f.AFR0 = 7) +#define PA01_AFx_GPIO() (CW_GPIOA->AFRL_f.AFR1 = 0) +#define PA01_AFx_UART3RTS() (CW_GPIOA->AFRL_f.AFR1 = 1) +#define PA01_AFx_UART2RTS() (CW_GPIOA->AFRL_f.AFR1 = 2) +#define PA01_AFx_I2C2SCL() (CW_GPIOA->AFRL_f.AFR1 = 3) +#define PA01_AFx_LVDOUT() (CW_GPIOA->AFRL_f.AFR1 = 4) +#define PA01_AFx_SPI2MOSI() (CW_GPIOA->AFRL_f.AFR1 = 5) +#define PA01_AFx_GTIM2CH2() (CW_GPIOA->AFRL_f.AFR1 = 6) +#define PA01_AFx_RTCTAMP() (CW_GPIOA->AFRL_f.AFR1 = 7) +#define PA02_AFx_GPIO() (CW_GPIOA->AFRL_f.AFR2 = 0) +#define PA02_AFx_UART3TXD() (CW_GPIOA->AFRL_f.AFR2 = 1) +#define PA02_AFx_UART2TXD() (CW_GPIOA->AFRL_f.AFR2 = 2) +#define PA02_AFx_I2C2SDA() (CW_GPIOA->AFRL_f.AFR2 = 3) +#define PA02_AFx_VC2OUT() (CW_GPIOA->AFRL_f.AFR2 = 4) +#define PA02_AFx_SPI2SCK() (CW_GPIOA->AFRL_f.AFR2 = 5) +#define PA02_AFx_GTIM2CH3() (CW_GPIOA->AFRL_f.AFR2 = 6) +#define PA02_AFx_AWTETR() (CW_GPIOA->AFRL_f.AFR2 = 7) +#define PA03_AFx_GPIO() (CW_GPIOA->AFRL_f.AFR3 = 0) +#define PA03_AFx_UART3RXD() (CW_GPIOA->AFRL_f.AFR3 = 1) +#define PA03_AFx_UART2RXD() (CW_GPIOA->AFRL_f.AFR3 = 2) +#define PA03_AFx_GTIM2CH2() (CW_GPIOA->AFRL_f.AFR3 = 3) +#define PA03_AFx_PCLKOUT() (CW_GPIOA->AFRL_f.AFR3 = 4) +#define PA03_AFx_SPI2CS() (CW_GPIOA->AFRL_f.AFR3 = 5) +#define PA03_AFx_GTIM2CH4() (CW_GPIOA->AFRL_f.AFR3 = 6) +#define PA03_AFx_ATIMCH3A() (CW_GPIOA->AFRL_f.AFR3 = 7) +#define PA04_AFx_GPIO() (CW_GPIOA->AFRL_f.AFR4 = 0) +#define PA04_AFx_UART2CTS() (CW_GPIOA->AFRL_f.AFR4 = 2) +#define PA04_AFx_I2C2SCL() (CW_GPIOA->AFRL_f.AFR4 = 3) +#define PA04_AFx_HCLKOUT() (CW_GPIOA->AFRL_f.AFR4 = 4) +#define PA04_AFx_SPI1CS() (CW_GPIOA->AFRL_f.AFR4 = 5) +#define PA04_AFx_GTIM2ETR() (CW_GPIOA->AFRL_f.AFR4 = 6) +#define PA04_AFx_ATIMCH2A() (CW_GPIOA->AFRL_f.AFR4 = 7) +#define PA05_AFx_GPIO() (CW_GPIOA->AFRL_f.AFR5 = 0) +#define PA05_AFx_GTIM2ETR() (CW_GPIOA->AFRL_f.AFR5 = 1) +#define PA05_AFx_UART2RTS() (CW_GPIOA->AFRL_f.AFR5 = 2) +#define PA05_AFx_I2C2SDA() (CW_GPIOA->AFRL_f.AFR5 = 3) +#define PA05_AFx_BTIM2TOGP() (CW_GPIOA->AFRL_f.AFR5 = 4) +#define PA05_AFx_SPI1SCK() (CW_GPIOA->AFRL_f.AFR5 = 5) +#define PA05_AFx_GTIM2CH1() (CW_GPIOA->AFRL_f.AFR5 = 6) +#define PA05_AFx_ATIMCH1A() (CW_GPIOA->AFRL_f.AFR5 = 7) +#define PA06_AFx_GPIO() (CW_GPIOA->AFRL_f.AFR6 = 0) +#define PA06_AFx_GTIM3CH1() (CW_GPIOA->AFRL_f.AFR6 = 1) +#define PA06_AFx_UART2TXD() (CW_GPIOA->AFRL_f.AFR6 = 2) +#define PA06_AFx_VC1OUT() (CW_GPIOA->AFRL_f.AFR6 = 3) +#define PA06_AFx_BTIM2TOGN() (CW_GPIOA->AFRL_f.AFR6 = 4) +#define PA06_AFx_SPI1MISO() (CW_GPIOA->AFRL_f.AFR6 = 5) +#define PA06_AFx_GTIM1CH1() (CW_GPIOA->AFRL_f.AFR6 = 6) +#define PA06_AFx_ATIMBK() (CW_GPIOA->AFRL_f.AFR6 = 7) +#define PA07_AFx_GPIO() (CW_GPIOA->AFRL_f.AFR7 = 0) +#define PA07_AFx_GTIM4CH1() (CW_GPIOA->AFRL_f.AFR7 = 1) +#define PA07_AFx_UART2RXD() (CW_GPIOA->AFRL_f.AFR7 = 2) +#define PA07_AFx_VC2OUT() (CW_GPIOA->AFRL_f.AFR7 = 3) +#define PA07_AFx_BTIM1TOGP() (CW_GPIOA->AFRL_f.AFR7 = 4) +#define PA07_AFx_SPI1MOSI() (CW_GPIOA->AFRL_f.AFR7 = 5) +#define PA07_AFx_GTIM1CH2() (CW_GPIOA->AFRL_f.AFR7 = 6) +#define PA07_AFx_ATIMCH1B() (CW_GPIOA->AFRL_f.AFR7 = 7) +#define PA08_AFx_GPIO() (CW_GPIOA->AFRH_f.AFR8 = 0) +#define PA08_AFx_UART1TXD() (CW_GPIOA->AFRH_f.AFR8 = 2) +#define PA08_AFx_BTIM2TOGN() (CW_GPIOA->AFRH_f.AFR8 = 3) +#define PA08_AFx_MCO() (CW_GPIOA->AFRH_f.AFR8 = 4) +#define PA08_AFx_LVDOUT() (CW_GPIOA->AFRH_f.AFR8 = 5) +#define PA08_AFx_GTIM3ETR() (CW_GPIOA->AFRH_f.AFR8 = 6) +#define PA08_AFx_ATIMCH1A() (CW_GPIOA->AFRH_f.AFR8 = 7) +#define PA09_AFx_GPIO() (CW_GPIOA->AFRH_f.AFR9 = 0) +#define PA09_AFx_UART3TXD() (CW_GPIOA->AFRH_f.AFR9 = 1) +#define PA09_AFx_UART1RXD() (CW_GPIOA->AFRH_f.AFR9 = 2) +#define PA09_AFx_I2C1SCL() (CW_GPIOA->AFRH_f.AFR9 = 3) +#define PA09_AFx_BTIM1TOGP() (CW_GPIOA->AFRH_f.AFR9 = 4) +#define PA09_AFx_SPI1CS() (CW_GPIOA->AFRH_f.AFR9 = 5) +#define PA09_AFx_GTIM3CH1() (CW_GPIOA->AFRH_f.AFR9 = 6) +#define PA09_AFx_ATIMCH2A() (CW_GPIOA->AFRH_f.AFR9 = 7) +#define PA10_AFx_GPIO() (CW_GPIOA->AFRH_f.AFR10 = 0) +#define PA10_AFx_UART3RXD() (CW_GPIOA->AFRH_f.AFR10 = 1) +#define PA10_AFx_UART1CTS() (CW_GPIOA->AFRH_f.AFR10 = 2) +#define PA10_AFx_I2C1SDA() (CW_GPIOA->AFRH_f.AFR10 = 3) +#define PA10_AFx_BTIM1TOGN() (CW_GPIOA->AFRH_f.AFR10 = 4) +#define PA10_AFx_SPI1SCK() (CW_GPIOA->AFRH_f.AFR10 = 5) +#define PA10_AFx_GTIM3CH2() (CW_GPIOA->AFRH_f.AFR10 = 6) +#define PA10_AFx_ATIMCH3A() (CW_GPIOA->AFRH_f.AFR10 = 7) +#define PA11_AFx_GPIO() (CW_GPIOA->AFRH_f.AFR11 = 0) +#define PA11_AFx_UART3CTS() (CW_GPIOA->AFRH_f.AFR11 = 1) +#define PA11_AFx_UART1RTS() (CW_GPIOA->AFRH_f.AFR11 = 2) +#define PA11_AFx_I2C2SCL() (CW_GPIOA->AFRH_f.AFR11 = 3) +#define PA11_AFx_VC1OUT() (CW_GPIOA->AFRH_f.AFR11 = 4) +#define PA11_AFx_SPI1MISO() (CW_GPIOA->AFRH_f.AFR11 = 5) +#define PA11_AFx_GTIM3CH3() (CW_GPIOA->AFRH_f.AFR11 = 6) +#define PA11_AFx_ATIMGATE() (CW_GPIOA->AFRH_f.AFR11 = 7) +#define PA12_AFx_GPIO() (CW_GPIOA->AFRH_f.AFR12 = 0) +#define PA12_AFx_UART3RTS() (CW_GPIOA->AFRH_f.AFR12 = 1) +#define PA12_AFx_BTIMETR() (CW_GPIOA->AFRH_f.AFR12 = 2) +#define PA12_AFx_I2C2SDA() (CW_GPIOA->AFRH_f.AFR12 = 3) +#define PA12_AFx_VC2OUT() (CW_GPIOA->AFRH_f.AFR12 = 4) +#define PA12_AFx_SPI1MOSI() (CW_GPIOA->AFRH_f.AFR12 = 5) +#define PA12_AFx_GTIM3CH4() (CW_GPIOA->AFRH_f.AFR12 = 6) +#define PA12_AFx_ATIMETR() (CW_GPIOA->AFRH_f.AFR12 = 7) +#define PA13_AFx_GPIO() (CW_GPIOA->AFRH_f.AFR13 = 0) +#define PA13_AFx_I2C1SDA() (CW_GPIOA->AFRH_f.AFR13 = 2) +#define PA13_AFx_UART1RXD() (CW_GPIOA->AFRH_f.AFR13 = 3) +#define PA13_AFx_UART2RXD() (CW_GPIOA->AFRH_f.AFR13 = 4) +#define PA13_AFx_I2C2SCL() (CW_GPIOA->AFRH_f.AFR13 = 5) +#define PA13_AFx_IROUT() (CW_GPIOA->AFRH_f.AFR13 = 6) +#define PA14_AFx_GPIO() (CW_GPIOA->AFRH_f.AFR14 = 0) +#define PA14_AFx_UART3TXD() (CW_GPIOA->AFRH_f.AFR14 = 1) +#define PA14_AFx_I2C1SCL() (CW_GPIOA->AFRH_f.AFR14 = 2) +#define PA14_AFx_UART1TXD() (CW_GPIOA->AFRH_f.AFR14 = 3) +#define PA14_AFx_UART2TXD() (CW_GPIOA->AFRH_f.AFR14 = 4) +#define PA14_AFx_I2C2SDA() (CW_GPIOA->AFRH_f.AFR14 = 5) +#define PA15_AFx_GPIO() (CW_GPIOA->AFRH_f.AFR15 = 0) +#define PA15_AFx_UART3RXD() (CW_GPIOA->AFRH_f.AFR15 = 1) +#define PA15_AFx_GTIM2CH1() (CW_GPIOA->AFRH_f.AFR15 = 2) +#define PA15_AFx_UART1RXD() (CW_GPIOA->AFRH_f.AFR15 = 3) +#define PA15_AFx_UART2RXD() (CW_GPIOA->AFRH_f.AFR15 = 4) +#define PA15_AFx_SPI1CS() (CW_GPIOA->AFRH_f.AFR15 = 5) +#define PA15_AFx_GTIM2ETR() (CW_GPIOA->AFRH_f.AFR15 = 6) +#define PA15_AFx_ATIMCH1B() (CW_GPIOA->AFRH_f.AFR15 = 7) +#define PB00_AFx_GPIO() (CW_GPIOB->AFRL_f.AFR0 = 0) +#define PB00_AFx_UART2RXD() (CW_GPIOB->AFRL_f.AFR0 = 1) +#define PB00_AFx_UART1CTS() (CW_GPIOB->AFRL_f.AFR0 = 2) +#define PB00_AFx_I2C2SCL() (CW_GPIOB->AFRL_f.AFR0 = 3) +#define PB00_AFx_BTIM1TOGN() (CW_GPIOB->AFRL_f.AFR0 = 4) +#define PB00_AFx_HSIOUT() (CW_GPIOB->AFRL_f.AFR0 = 5) +#define PB00_AFx_GTIM1CH3() (CW_GPIOB->AFRL_f.AFR0 = 6) +#define PB00_AFx_ATIMCH2B() (CW_GPIOB->AFRL_f.AFR0 = 7) +#define PB01_AFx_GPIO() (CW_GPIOB->AFRL_f.AFR1 = 0) +#define PB01_AFx_UART2TXD() (CW_GPIOB->AFRL_f.AFR1 = 1) +#define PB01_AFx_UART1RTS() (CW_GPIOB->AFRL_f.AFR1 = 2) +#define PB01_AFx_I2C2SDA() (CW_GPIOB->AFRL_f.AFR1 = 3) +#define PB01_AFx_GTIM4TOGN() (CW_GPIOB->AFRL_f.AFR1 = 4) +#define PB01_AFx_BTIM3TOGP() (CW_GPIOB->AFRL_f.AFR1 = 5) +#define PB01_AFx_GTIM1CH4() (CW_GPIOB->AFRL_f.AFR1 = 6) +#define PB01_AFx_ATIMCH3B() (CW_GPIOB->AFRL_f.AFR1 = 7) +#define PB02_AFx_GPIO() (CW_GPIOB->AFRL_f.AFR2 = 0) +#define PB02_AFx_UART2CTS() (CW_GPIOB->AFRL_f.AFR2 = 1) +#define PB02_AFx_UART1TXD() (CW_GPIOB->AFRL_f.AFR2 = 2) +#define PB02_AFx_HSEOUT() (CW_GPIOB->AFRL_f.AFR2 = 3) +#define PB02_AFx_GTIM4TOGP() (CW_GPIOB->AFRL_f.AFR2 = 4) +#define PB02_AFx_BTIM3TOGN() (CW_GPIOB->AFRL_f.AFR2 = 5) +#define PB02_AFx_GTIM1ETR() (CW_GPIOB->AFRL_f.AFR2 = 6) +#define PB02_AFx_ATIMCH1A() (CW_GPIOB->AFRL_f.AFR2 = 7) +#define PB03_AFx_GPIO() (CW_GPIOB->AFRL_f.AFR3 = 0) +#define PB03_AFx_UART3RTS() (CW_GPIOB->AFRL_f.AFR3 = 1) +#define PB03_AFx_GTIM2CH2() (CW_GPIOB->AFRL_f.AFR3 = 2) +#define PB03_AFx_UART1CTS() (CW_GPIOB->AFRL_f.AFR3 = 3) +#define PB03_AFx_UART2TXD() (CW_GPIOB->AFRL_f.AFR3 = 4) +#define PB03_AFx_SPI1SCK() (CW_GPIOB->AFRL_f.AFR3 = 5) +#define PB03_AFx_GTIM1ETR() (CW_GPIOB->AFRL_f.AFR3 = 6) +#define PB03_AFx_ATIMCH2B() (CW_GPIOB->AFRL_f.AFR3 = 7) +#define PB04_AFx_GPIO() (CW_GPIOB->AFRL_f.AFR4 = 0) +#define PB04_AFx_UART3CTS() (CW_GPIOB->AFRL_f.AFR4 = 1) +#define PB04_AFx_GTIM4ETR() (CW_GPIOB->AFRL_f.AFR4 = 2) +#define PB04_AFx_UART1RTS() (CW_GPIOB->AFRL_f.AFR4 = 3) +#define PB04_AFx_UART2CTS() (CW_GPIOB->AFRL_f.AFR4 = 4) +#define PB04_AFx_SPI1MISO() (CW_GPIOB->AFRL_f.AFR4 = 5) +#define PB04_AFx_GTIM1CH1() (CW_GPIOB->AFRL_f.AFR4 = 6) +#define PB04_AFx_ATIMCH3B() (CW_GPIOB->AFRL_f.AFR4 = 7) +#define PB05_AFx_GPIO() (CW_GPIOB->AFRL_f.AFR5 = 0) +#define PB05_AFx_GTIM3CH4() (CW_GPIOB->AFRL_f.AFR5 = 2) +#define PB05_AFx_AWTETR() (CW_GPIOB->AFRL_f.AFR5 = 3) +#define PB05_AFx_UART2RTS() (CW_GPIOB->AFRL_f.AFR5 = 4) +#define PB05_AFx_SPI1MOSI() (CW_GPIOB->AFRL_f.AFR5 = 5) +#define PB05_AFx_GTIM1CH2() (CW_GPIOB->AFRL_f.AFR5 = 6) +#define PB05_AFx_ATIMCH1A() (CW_GPIOB->AFRL_f.AFR5 = 7) +#define PB06_AFx_GPIO() (CW_GPIOB->AFRL_f.AFR6 = 0) +#define PB06_AFx_UART3TXD() (CW_GPIOB->AFRL_f.AFR6 = 1) +#define PB06_AFx_GTIM3CH3() (CW_GPIOB->AFRL_f.AFR6 = 2) +#define PB06_AFx_I2C1SCL() (CW_GPIOB->AFRL_f.AFR6 = 3) +#define PB06_AFx_GTIM4CH4() (CW_GPIOB->AFRL_f.AFR6 = 4) +#define PB06_AFx_SPI2MOSI() (CW_GPIOB->AFRL_f.AFR6 = 5) +#define PB06_AFx_GTIM1TOGN() (CW_GPIOB->AFRL_f.AFR6 = 6) +#define PB06_AFx_ATIMCH2A() (CW_GPIOB->AFRL_f.AFR6 = 7) +#define PB07_AFx_GPIO() (CW_GPIOB->AFRL_f.AFR7 = 0) +#define PB07_AFx_UART3RXD() (CW_GPIOB->AFRL_f.AFR7 = 1) +#define PB07_AFx_GTIM3CH2() (CW_GPIOB->AFRL_f.AFR7 = 2) +#define PB07_AFx_I2C1SDA() (CW_GPIOB->AFRL_f.AFR7 = 3) +#define PB07_AFx_GTIM4CH3() (CW_GPIOB->AFRL_f.AFR7 = 4) +#define PB07_AFx_SPI2MISO() (CW_GPIOB->AFRL_f.AFR7 = 5) +#define PB07_AFx_GTIM1TOGP() (CW_GPIOB->AFRL_f.AFR7 = 6) +#define PB07_AFx_ATIMCH3A() (CW_GPIOB->AFRL_f.AFR7 = 7) +#define PB08_AFx_GPIO() (CW_GPIOB->AFRH_f.AFR8 = 0) +#define PB08_AFx_I2C1SCL() (CW_GPIOB->AFRH_f.AFR8 = 1) +#define PB08_AFx_GTIM3CH1() (CW_GPIOB->AFRH_f.AFR8 = 2) +#define PB08_AFx_UART1TXD() (CW_GPIOB->AFRH_f.AFR8 = 3) +#define PB08_AFx_GTIM4CH2() (CW_GPIOB->AFRH_f.AFR8 = 4) +#define PB08_AFx_SPI2SCK() (CW_GPIOB->AFRH_f.AFR8 = 5) +#define PB08_AFx_GTIM1CH3() (CW_GPIOB->AFRH_f.AFR8 = 6) +#define PB08_AFx_ATIMETR() (CW_GPIOB->AFRH_f.AFR8 = 7) +#define PB09_AFx_GPIO() (CW_GPIOB->AFRH_f.AFR9 = 0) +#define PB09_AFx_I2C1SDA() (CW_GPIOB->AFRH_f.AFR9 = 1) +#define PB09_AFx_GTIM4CH1() (CW_GPIOB->AFRH_f.AFR9 = 2) +#define PB09_AFx_UART1RXD() (CW_GPIOB->AFRH_f.AFR9 = 3) +#define PB09_AFx_IROUT() (CW_GPIOB->AFRH_f.AFR9 = 4) +#define PB09_AFx_SPI2CS() (CW_GPIOB->AFRH_f.AFR9 = 5) +#define PB09_AFx_GTIM1CH4() (CW_GPIOB->AFRH_f.AFR9 = 6) +#define PB09_AFx_ATIMBK() (CW_GPIOB->AFRH_f.AFR9 = 7) +#define PB10_AFx_GPIO() (CW_GPIOB->AFRH_f.AFR10 = 0) +#define PB10_AFx_UART2RTS() (CW_GPIOB->AFRH_f.AFR10 = 1) +#define PB10_AFx_UART1RXD() (CW_GPIOB->AFRH_f.AFR10 = 2) +#define PB10_AFx_I2C1SCL() (CW_GPIOB->AFRH_f.AFR10 = 3) +#define PB10_AFx_I2C2SCL() (CW_GPIOB->AFRH_f.AFR10 = 4) +#define PB10_AFx_SPI2SCK() (CW_GPIOB->AFRH_f.AFR10 = 5) +#define PB10_AFx_GTIM2CH3() (CW_GPIOB->AFRH_f.AFR10 = 6) +#define PB10_AFx_ATIMCH2A() (CW_GPIOB->AFRH_f.AFR10 = 7) +#define PB11_AFx_GPIO() (CW_GPIOB->AFRH_f.AFR11 = 0) +#define PB11_AFx_LSIOUT() (CW_GPIOB->AFRH_f.AFR11 = 1) +#define PB11_AFx_GTIM4ETR() (CW_GPIOB->AFRH_f.AFR11 = 2) +#define PB11_AFx_I2C1SDA() (CW_GPIOB->AFRH_f.AFR11 = 3) +#define PB11_AFx_I2C2SDA() (CW_GPIOB->AFRH_f.AFR11 = 4) +#define PB11_AFx_BTIMETR() (CW_GPIOB->AFRH_f.AFR11 = 5) +#define PB11_AFx_GTIM2CH4() (CW_GPIOB->AFRH_f.AFR11 = 6) +#define PB11_AFx_ATIMCH3A() (CW_GPIOB->AFRH_f.AFR11 = 7) +#define PB12_AFx_GPIO() (CW_GPIOB->AFRH_f.AFR12 = 0) +#define PB12_AFx_GTIM2TOGN() (CW_GPIOB->AFRH_f.AFR12 = 1) +#define PB12_AFx_GTIM4CH4() (CW_GPIOB->AFRH_f.AFR12 = 2) +#define PB12_AFx_LSEOUT() (CW_GPIOB->AFRH_f.AFR12 = 3) +#define PB12_AFx_SPI2CS() (CW_GPIOB->AFRH_f.AFR12 = 4) +#define PB12_AFx_SPI1CS() (CW_GPIOB->AFRH_f.AFR12 = 5) +#define PB12_AFx_GTIM1TOGN() (CW_GPIOB->AFRH_f.AFR12 = 6) +#define PB12_AFx_ATIMBK() (CW_GPIOB->AFRH_f.AFR12 = 7) +#define PB13_AFx_GPIO() (CW_GPIOB->AFRH_f.AFR13 = 0) +#define PB13_AFx_GTIM2TOGP() (CW_GPIOB->AFRH_f.AFR13 = 1) +#define PB13_AFx_GTIM4CH3() (CW_GPIOB->AFRH_f.AFR13 = 2) +#define PB13_AFx_I2C2SCL() (CW_GPIOB->AFRH_f.AFR13 = 3) +#define PB13_AFx_SPI2SCK() (CW_GPIOB->AFRH_f.AFR13 = 4) +#define PB13_AFx_SPI1SCK() (CW_GPIOB->AFRH_f.AFR13 = 5) +#define PB13_AFx_GTIM1TOGP() (CW_GPIOB->AFRH_f.AFR13 = 6) +#define PB13_AFx_ATIMCH1B() (CW_GPIOB->AFRH_f.AFR13 = 7) +#define PB14_AFx_GPIO() (CW_GPIOB->AFRH_f.AFR14 = 0) +#define PB14_AFx_GTIM2CH1() (CW_GPIOB->AFRH_f.AFR14 = 1) +#define PB14_AFx_GTIM4CH2() (CW_GPIOB->AFRH_f.AFR14 = 2) +#define PB14_AFx_I2C2SDA() (CW_GPIOB->AFRH_f.AFR14 = 3) +#define PB14_AFx_SPI2MISO() (CW_GPIOB->AFRH_f.AFR14 = 4) +#define PB14_AFx_SPI1MISO() (CW_GPIOB->AFRH_f.AFR14 = 5) +#define PB14_AFx_RTCOUT() (CW_GPIOB->AFRH_f.AFR14 = 6) +#define PB14_AFx_ATIMCH2B() (CW_GPIOB->AFRH_f.AFR14 = 7) +#define PB15_AFx_GPIO() (CW_GPIOB->AFRH_f.AFR15 = 0) +#define PB15_AFx_GTIM2CH2() (CW_GPIOB->AFRH_f.AFR15 = 1) +#define PB15_AFx_GTIM4CH1() (CW_GPIOB->AFRH_f.AFR15 = 2) +#define PB15_AFx_BTIM2TOGP() (CW_GPIOB->AFRH_f.AFR15 = 3) +#define PB15_AFx_SPI2MOSI() (CW_GPIOB->AFRH_f.AFR15 = 4) +#define PB15_AFx_SPI1MOSI() (CW_GPIOB->AFRH_f.AFR15 = 5) +#define PB15_AFx_RTC1Hz() (CW_GPIOB->AFRH_f.AFR15 = 6) +#define PB15_AFx_ATIMCH3B() (CW_GPIOB->AFRH_f.AFR15 = 7) +#define PC13_AFx_GPIO() (CW_GPIOC->AFRH_f.AFR13 = 0) +#define PC13_AFx_PLLOUT() (CW_GPIOC->AFRH_f.AFR13 = 1) +#define PC13_AFx_RTC1Hz() (CW_GPIOC->AFRH_f.AFR13 = 2) +#define PC13_AFx_UART1CTS() (CW_GPIOC->AFRH_f.AFR13 = 3) +#define PC13_AFx_RTCOUT() (CW_GPIOC->AFRH_f.AFR13 = 4) +#define PC13_AFx_BTIMETR() (CW_GPIOC->AFRH_f.AFR13 = 5) +#define PC13_AFx_GTIM3ETR() (CW_GPIOC->AFRH_f.AFR13 = 6) +#define PC13_AFx_RTCTAMP() (CW_GPIOC->AFRH_f.AFR13 = 7) +#define PC14_AFx_GPIO() (CW_GPIOC->AFRH_f.AFR14 = 0) +#define PC14_AFx_AWTETR() (CW_GPIOC->AFRH_f.AFR14 = 1) +#define PC14_AFx_GTIM4CH4() (CW_GPIOC->AFRH_f.AFR14 = 2) +#define PC14_AFx_UART1RTS() (CW_GPIOC->AFRH_f.AFR14 = 3) +#define PC14_AFx_BTIM2TOGP() (CW_GPIOC->AFRH_f.AFR14 = 4) +#define PC14_AFx_SPI2MISO() (CW_GPIOC->AFRH_f.AFR14 = 5) +#define PC14_AFx_GTIM3TOGN() (CW_GPIOC->AFRH_f.AFR14 = 6) +#define PC14_AFx_GTIM3CH1() (CW_GPIOC->AFRH_f.AFR14 = 7) +#define PC15_AFx_GPIO() (CW_GPIOC->AFRH_f.AFR15 = 0) +#define PC15_AFx_HSEOUT() (CW_GPIOC->AFRH_f.AFR15 = 1) +#define PC15_AFx_GTIM4CH3() (CW_GPIOC->AFRH_f.AFR15 = 2) +#define PC15_AFx_GTIM4ETR() (CW_GPIOC->AFRH_f.AFR15 = 3) +#define PC15_AFx_BTIM2TOGN() (CW_GPIOC->AFRH_f.AFR15 = 4) +#define PC15_AFx_SPI2MOSI() (CW_GPIOC->AFRH_f.AFR15 = 5) +#define PC15_AFx_GTIM3TOGP() (CW_GPIOC->AFRH_f.AFR15 = 6) +#define PC15_AFx_GTIM3CH2() (CW_GPIOC->AFRH_f.AFR15 = 7) +#define PF00_AFx_GPIO() (CW_GPIOF->AFRL_f.AFR0 = 0) +#define PF00_AFx_AWTETR() (CW_GPIOF->AFRL_f.AFR0 = 1) +#define PF00_AFx_GTIM4CH2() (CW_GPIOF->AFRL_f.AFR0 = 2) +#define PF00_AFx_I2C1SDA() (CW_GPIOF->AFRL_f.AFR0 = 3) +#define PF00_AFx_BTIM1TOGP() (CW_GPIOF->AFRL_f.AFR0 = 4) +#define PF00_AFx_SPI2SCK() (CW_GPIOF->AFRL_f.AFR0 = 5) +#define PF00_AFx_GTIM2TOGN() (CW_GPIOF->AFRL_f.AFR0 = 6) +#define PF00_AFx_GTIM3CH3() (CW_GPIOF->AFRL_f.AFR0 = 7) +#define PF01_AFx_GPIO() (CW_GPIOF->AFRL_f.AFR1 = 0) +#define PF01_AFx_LSEOUT() (CW_GPIOF->AFRL_f.AFR1 = 1) +#define PF01_AFx_GTIM4CH1() (CW_GPIOF->AFRL_f.AFR1 = 2) +#define PF01_AFx_I2C1SCL() (CW_GPIOF->AFRL_f.AFR1 = 3) +#define PF01_AFx_BTIM1TOGN() (CW_GPIOF->AFRL_f.AFR1 = 4) +#define PF01_AFx_SPI2CS() (CW_GPIOF->AFRL_f.AFR1 = 5) +#define PF01_AFx_GTIM2TOGP() (CW_GPIOF->AFRL_f.AFR1 = 6) +#define PF01_AFx_GTIM3CH4() (CW_GPIOF->AFRL_f.AFR1 = 7) +#define PF06_AFx_GPIO() (CW_GPIOF->AFRL_f.AFR6 = 0) +#define PF06_AFx_UART3CTS() (CW_GPIOF->AFRL_f.AFR6 = 1) +#define PF06_AFx_I2C1SCL() (CW_GPIOF->AFRL_f.AFR6 = 2) +#define PF06_AFx_GTIM4TOGN() (CW_GPIOF->AFRL_f.AFR6 = 3) +#define PF06_AFx_UART2CTS() (CW_GPIOF->AFRL_f.AFR6 = 4) +#define PF06_AFx_I2C2SCL() (CW_GPIOF->AFRL_f.AFR6 = 5) +#define PF06_AFx_GTIM3TOGN() (CW_GPIOF->AFRL_f.AFR6 = 6) +#define PF06_AFx_BTIM3TOGP() (CW_GPIOF->AFRL_f.AFR6 = 7) +#define PF07_AFx_GPIO() (CW_GPIOF->AFRL_f.AFR7 = 0) +#define PF07_AFx_UART3RTS() (CW_GPIOF->AFRL_f.AFR7 = 1) +#define PF07_AFx_I2C1SDA() (CW_GPIOF->AFRL_f.AFR7 = 2) +#define PF07_AFx_GTIM4TOGP() (CW_GPIOF->AFRL_f.AFR7 = 3) +#define PF07_AFx_UART2RTS() (CW_GPIOF->AFRL_f.AFR7 = 4) +#define PF07_AFx_I2C2SDA() (CW_GPIOF->AFRL_f.AFR7 = 5) +#define PF07_AFx_GTIM3TOGP() (CW_GPIOF->AFRL_f.AFR7 = 6) +#define PF07_AFx_BTIM3TOGN() (CW_GPIOF->AFRL_f.AFR7 = 7) +#define PF03_AFx_GPIO() (CW_GPIOF->AFRL_f.AFR3 = 0) + + //============================================================ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_gtim.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_gtim.h new file mode 100644 index 0000000..5f1ff7a --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_gtim.h @@ -0,0 +1,333 @@ +/** + * @file cw32f030_gtim.h + * @author P&S (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-04-26 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_GTIM_H +#define __CW32F030_GTIM_H + + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" + +/****************************************************************************** + * type definitions ('typedef') + ******************************************************************************/ + +/** + * @brief GTIM ʼ + */ +typedef struct +{ + uint32_t Mode; /*!< GTIMģʽѡ */ + uint32_t OneShotMode; /*!< GTIMĵ/ģʽѡ */ + FunctionalState ToggleOutState; /*!< GTIMķתʹѡ */ + uint32_t Prescaler; /*!< GTIMԤƵϵ */ + uint32_t ReloadValue; /*!< GTIMֵ */ +} GTIM_InitTypeDef; + +/** + * @brief GTIM ģʽµijʼ + */ + +typedef struct +{ + uint32_t EncodeMode; + uint32_t EncodeResetMode; + uint32_t EncodeReloadMode; + uint32_t CH1Filter; + uint32_t CH2Filter; + uint32_t CH3Filter; + uint32_t CH1Invert; + uint32_t CH2Invert; + uint32_t CH3Invert; +}GTIM_EncodeInitTypeDef; + +/** + * @brief GTIM 벶ò + */ +typedef struct +{ + uint32_t CHx; + uint32_t ICPolarity; + uint32_t ICFilter; + uint32_t ICInvert; +}GTIM_ICInitTypeDef; + +/****************************************************************************** + * pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_GTIM_DEFINE(GTIMx) (((GTIMx) == CW_GTIM1) || \ + ((GTIMx) == CW_GTIM2) || \ + ((GTIMx) == CW_GTIM3) || \ + ((GTIMx) == CW_GTIM4)) + + +#define GTIM_MODE_TIME (0UL) +#define GTIM_MODE_COUNTER (1UL << 1) +#define GTIM_MODE_TRIGGER (2UL << 1) +#define GTIM_MODE_GATE (3UL << 1) +#define IS_GTIM_MODE(MODE) (((MODE) == GTIM_MODE_TIME) || \ + ((MODE) == GTIM_MODE_COUNTER) || \ + ((MODE) == GTIM_MODE_TRIGGER) || \ + ((MODE) == GTIM_MODE_GATE)) + +#define GTIM_TRIGGER_ETR (0UL) +#define GTIM_TRIGGER_ITR (1UL <<3) +#define IS_GTIM_TRS(MODE) (((MODE) == GTIM_TRIGGER_ETR) || \ + ((MODE) == GTIM_TRIGGER_ITR)) + +#define ITR_SOURCE_BTIM1 (0UL) +#define ITR_SOURCE_BTIM2 (1UL) +#define ITR_SOURCE_BTIM3 (2UL) +#define ITR_SOURCE_GTIM1 (3UL) +#define ITR_SOURCE_GTIM2 (4UL) +#define ITR_SOURCE_GTIM3 (5UL) +#define ITR_SOURCE_GTIM4 (6UL) +#define ITR_SOURCE_ATIM (7UL) +#define IS_ITR_SOURCE(ITR) (((ITR) == ITR_SOURCE_BTIM1) || \ + ((ITR) == ITR_SOURCE_BTIM2) || \ + ((ITR) == ITR_SOURCE_BTIM3) || \ + ((ITR) == ITR_SOURCE_GTIM1) || \ + ((ITR) == ITR_SOURCE_GTIM2) || \ + ((ITR) == ITR_SOURCE_GTIM3) || \ + ((ITR) == ITR_SOURCE_GTIM4) || \ + ((ITR) == ITR_SOURCE_ATIM)) + +#define GTIM_ETR_POL_RISE_HIGH (0UL) +#define GTIM_ETR_POL_FALL_LOW (1UL << 4) +#define IS_GTIM_ETR_POL(MODE) (((MODE) == GTIM_ETR_POL_RISE_HIGH) || \ + ((MODE) == GTIM_ETR_POL_FALL_LOW)) + +#define GTIM_COUNT_CONTINUE (0UL) +#define GTIM_COUNT_ONESHOT (1UL << 5) +#define IS_GTIM_ONESHOT(MODE) (((MODE) == GTIM_COUNT_CONTINUE) || \ + ((MODE) == GTIM_COUNT_ONESHOT)) + +#define GTIM_PRESCALER_DIV1 (0UL) +#define GTIM_PRESCALER_DIV2 (1UL << 7) +#define GTIM_PRESCALER_DIV4 (2UL << 7) +#define GTIM_PRESCALER_DIV8 (3UL << 7) +#define GTIM_PRESCALER_DIV16 (4UL << 7) +#define GTIM_PRESCALER_DIV32 (5UL << 7) +#define GTIM_PRESCALER_DIV64 (6UL << 7) +#define GTIM_PRESCALER_DIV128 (7UL << 7) +#define GTIM_PRESCALER_DIV256 (8UL << 7) +#define GTIM_PRESCALER_DIV512 (9UL << 7) +#define GTIM_PRESCALER_DIV1024 (10UL << 7) +#define GTIM_PRESCALER_DIV2048 (11UL << 7) +#define GTIM_PRESCALER_DIV4096 (12UL << 7) +#define GTIM_PRESCALER_DIV8192 (13UL << 7) +#define GTIM_PRESCALER_DIV16384 (14UL << 7) +#define GTIM_PRESCALER_DIV32768 (15UL << 7) +#define IS_GTIM_PRESCALER(DIV) (((DIV) == GTIM_PRESCALER_DIV1) || \ + ((DIV) == GTIM_PRESCALER_DIV2) || \ + ((DIV) == GTIM_PRESCALER_DIV4) || \ + ((DIV) == GTIM_PRESCALER_DIV8) || \ + ((DIV) == GTIM_PRESCALER_DIV16) || \ + ((DIV) == GTIM_PRESCALER_DIV32) || \ + ((DIV) == GTIM_PRESCALER_DIV64) || \ + ((DIV) == GTIM_PRESCALER_DIV128) || \ + ((DIV) == GTIM_PRESCALER_DIV256) || \ + ((DIV) == GTIM_PRESCALER_DIV512) || \ + ((DIV) == GTIM_PRESCALER_DIV1024) || \ + ((DIV) == GTIM_PRESCALER_DIV2048) || \ + ((DIV) == GTIM_PRESCALER_DIV4096) || \ + ((DIV) == GTIM_PRESCALER_DIV8192) || \ + ((DIV) == GTIM_PRESCALER_DIV16384) || \ + ((DIV) == GTIM_PRESCALER_DIV32768)) + +#define GTIM_ENCODE_MODE0 (0UL) +#define GTIM_ENCODE_MODE1 (1UL << 15) +#define GTIM_ENCODE_MODE2 (2UL << 15) +#define GTIM_ENCODE_MODE3 (3UL << 15) +#define IS_GTIM_ENCODE_MODE(MODE) (((MODE) == GTIM_ENCODE_MODE0) || \ + ((MODE) == GTIM_ENCODE_MODE1) || \ + ((MODE) == GTIM_ENCODE_MODE2) || \ + ((MODE) == GTIM_ENCODE_MODE3)) + +#define GTIM_ENCODE_RESET_NONE (0UL) +#define GTIM_ENCODE_RESET_RISE (1UL << 17) +#define GTIM_ENCODE_RESET_FALL (2UL << 17) +#define IS_GTIM_ENCODE_RESET(MODE) (((MODE) == GTIM_ENCODE_RESET_NONE) || \ + ((MODE) == GTIM_ENCODE_RESET_RISE) || \ + ((MODE) == GTIM_ENCODE_RESET_FALL)) + +#define GTIM_ENCODE_RELOAD_NONE (0UL) +#define GTIM_ENCODE_RELOAD_RISE (1UL << 19) +#define GTIM_ENCODE_RELOAD_FALL (2UL << 19) +#define IS_GTIM_ENCODE_RELOAD(MODE) (((MODE) == GTIM_ENCODE_RELOAD_NONE) || \ + ((MODE) == GTIM_ENCODE_RELOAD_RISE) || \ + ((MODE) == GTIM_ENCODE_RELOAD_FALL)) + +#define GTIM_CHx_FILTER_NONE (0UL) +#define GTIM_CHx_FILTER_PCLK_N2 (1UL) +#define GTIM_CHx_FILTER_PCLK_N4 (2UL) +#define GTIM_CHx_FILTER_PCLK_N6 (3UL) +#define GTIM_CHx_FILTER_PCLKDIV4_N4 (4UL) +#define GTIM_CHx_FILTER_PCLKDIV4_N6 (5UL) +#define GTIM_CHx_FILTER_PCLKDIV8_N4 (6UL) +#define GTIM_CHx_FILTER_PCLKDIV8_N6 (7UL) +#define IS_GTIM_CHx_FILTER(MODE) (((MODE) == GTIM_CHx_FILTER_NONE) || \ + ((MODE) == GTIM_CHx_FILTER_PCLK_N2) || \ + ((MODE) == GTIM_CHx_FILTER_PCLK_N4) || \ + ((MODE) == GTIM_CHx_FILTER_PCLK_N6) || \ + ((MODE) == GTIM_CHx_FILTER_PCLKDIV4_N4) || \ + ((MODE) == GTIM_CHx_FILTER_PCLKDIV4_N6) || \ + ((MODE) == GTIM_CHx_FILTER_PCLKDIV8_N4) || \ + ((MODE) == GTIM_CHx_FILTER_PCLKDIV8_N6)) + +#define GTIM_CHx_INVERT_OFF (1UL) +#define GTIM_CHx_INVERT_ON (0UL) +#define IS_GTIM_CHx_INVERT(VAL) (((VAL) == GTIM_CHx_INVERT_OFF) || \ + ((VAL) == GTIM_CHx_INVERT_ON)) + +#define GTIM_ETR_FILTER_NONE (0UL) +#define GTIM_ETR_FILTER_PCLK_N2 (1UL << 4) +#define GTIM_ETR_FILTER_PCLK_N4 (2UL << 4) +#define GTIM_ETR_FILTER_PCLK_N6 (3UL << 4) +#define GTIM_ETR_FILTER_PCLKDIV4_N4 (4UL << 4) +#define GTIM_ETR_FILTER_PCLKDIV4_N6 (5UL << 4) +#define GTIM_ETR_FILTER_PCLKDIV8_N4 (6UL << 4) +#define GTIM_ETR_FILTER_PCLKDIV8_N6 (7UL << 4) +#define IS_GTIM_ETR_FILTER(MODE) (((MODE) == GTIM_ETR_FILTER_NONE) || \ + ((MODE) == GTIM_ETR_FILTER_PCLK_N2) || \ + ((MODE) == GTIM_ETR_FILTER_PCLK_N4) || \ + ((MODE) == GTIM_ETR_FILTER_PCLK_N6) || \ + ((MODE) == GTIM_ETR_FILTER_PCLKDIV4_N4) || \ + ((MODE) == GTIM_ETR_FILTER_PCLKDIV4_N6) || \ + ((MODE) == GTIM_ETR_FILTER_PCLKDIV8_N4) || \ + ((MODE) == GTIM_ETR_FILTER_PCLKDIV8_N6)) + + +#define GTIM_ICPolarity_Rising (1UL) +#define GTIM_ICPolarity_Falling (2UL) +#define GTIM_ICPolarity_BothEdge (3UL) +#define IS_GTIM_ICPolarity(MODE) (((MODE) == GTIM_ICPolarity_Rising) || \ + ((MODE) == GTIM_ICPolarity_Falling) || \ + ((MODE) == GTIM_ICPolarity_BothEdge)) + +#define GTIM_OC_OUTPUT_FORCE_LOW (8UL) +#define GTIM_OC_OUTPUT_FORCE_HIGH (9UL) +#define GTIM_OC_OUTPUT_MATCH_LOW (10UL) +#define GTIM_OC_OUTPUT_MATCH_HIGH (11UL) +#define GTIM_OC_OUTPUT_MATHC_TOGGLE (13UL) +#define GTIM_OC_OUTPUT_PWM_HIGH (14UL) +#define GTIM_OC_OUTPUT_PWM_LOW (15UL) +#define IS_GTIM_OC_OUTPUT(MODE) (((MODE) == GTIM_OC_OUTPUT_FORCE_LOW) || \ + ((MODE) == GTIM_OC_OUTPUT_FORCE_HIGH) || \ + ((MODE) == GTIM_OC_OUTPUT_MATCH_LOW) || \ + ((MODE) == GTIM_OC_OUTPUT_MATCH_HIGH) || \ + ((MODE) == GTIM_OC_OUTPUT_MATHC_TOGGLE) || \ + ((MODE) == GTIM_OC_OUTPUT_PWM_HIGH) || \ + ((MODE) == GTIM_OC_OUTPUT_PWM_LOW)) + +#define GTIM_CHANNEL1 (0UL) +#define GTIM_CHANNEL2 (4UL) +#define GTIM_CHANNEL3 (8UL) +#define GTIM_CHANNEL4 (12UL) +#define IS_GTIM_CHANNEL(CHANNEL) (((CHANNEL) == GTIM_CHANNEL1) || \ + ((CHANNEL) == GTIM_CHANNEL2) || \ + ((CHANNEL) == GTIM_CHANNEL3) || \ + ((CHANNEL) == GTIM_CHANNEL4)) + +#define GTIM_IT_OV (1UL) +#define GTIM_IT_TI (1UL<<1) +#define GTIM_IT_UD (1UL<<2) +#define GTIM_IT_CC1 (1UL<<3) +#define GTIM_IT_CC2 (1UL<<4) +#define GTIM_IT_CC3 (1UL<<5) +#define GTIM_IT_CC4 (1UL<<6) +#define GTIM_IT_DIRCHANGE (1UL<<9) +#define IS_GTIM_IT(IT) (((IT) & 0xFFFFFD80 == 0x0UL) && ((IT) != 0x0UL)) +#define IS_GTIM_GET_IT(IT) (((IT) == GTIM_IT_OV) || \ + ((IT) == GTIM_IT_TI) || \ + ((IT) == GTIM_IT_UD) || \ + ((IT) == GTIM_IT_CC1) || \ + ((IT) == GTIM_IT_CC2) || \ + ((IT) == GTIM_IT_CC3) || \ + ((IT) == GTIM_IT_CC4) || \ + ((IT) == GTIM_IT_DIRCHANGE)) + +#define GTIM_DMA_OV (1UL) +#define GTIM_DMA_TRS (1UL<<1) +#define GTIM_DMA_CC1 (1UL<<2) +#define GTIM_DMA_CC2 (1UL<<3) +#define GTIM_DMA_CC3 (1UL<<4) +#define GTIM_DMA_CC4 (1UL<<5) +#define IS_GTIM_DMA(DMA) (((DMA) & 0xFFFFFFC0 == 0x0UL) && (DMA) != 0x0UL) + + + /****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + + /****************************************************************************** + * Global function prototypes + ******************************************************************************/ +void GTIM1_DeInit(void); +void GTIM2_DeInit(void); +void GTIM3_DeInit(void); +void GTIM4_DeInit(void); +void GTIM_TimeBaseInit(GTIM_TypeDef* GTIMx, GTIM_InitTypeDef *GTIM_InitStruct); + +void GTIM_EncodeInit(GTIM_TypeDef* GTIMx, GTIM_EncodeInitTypeDef *GTIM_EncodeInitStruct); +void GTIM_OCInit(GTIM_TypeDef* GTIMx, uint32_t CHx, uint32_t OCMode); +void GTIM_ICInit(GTIM_TypeDef* GTIMx, GTIM_ICInitTypeDef *GTIM_ICInitStruct); +void GTIM_Cmd(GTIM_TypeDef* GTIMx, FunctionalState NewState); + +void GTIM_ETRConfig(GTIM_TypeDef* GTIMx, uint32_t ETRPolarity, uint32_t ETRFilter); +void GTIM_ICChannelConfig(GTIM_TypeDef* GTIMx, uint32_t CHx, uint32_t CHxFilter,uint32_t CHxInvert); +void GTIM_SetPrescaler(GTIM_TypeDef* GTIMx, uint32_t GTIMPrescaler); +void GTIM_SetReloadValue(GTIM_TypeDef* GTIMx, uint32_t ReloadValue); +void GTIM_SetCounterValue(GTIM_TypeDef* GTIMx, uint32_t Value); +void GTIM_SetCompare1(GTIM_TypeDef* GTIMx, uint32_t Value); +void GTIM_SetCompare2(GTIM_TypeDef* GTIMx, uint32_t Value); +void GTIM_SetCompare3(GTIM_TypeDef* GTIMx, uint32_t Value); +void GTIM_SetCompare4(GTIM_TypeDef* GTIMx, uint32_t Value); +uint32_t GTIM_GetCapture1(GTIM_TypeDef* GTIMx); +uint32_t GTIM_GetCapture2(GTIM_TypeDef* GTIMx); +uint32_t GTIM_GetCapture3(GTIM_TypeDef* GTIMx); +uint32_t GTIM_GetCapture4(GTIM_TypeDef* GTIMx); +void GTIM_ITConfig(GTIM_TypeDef* GTIMx, uint32_t GTIM_IT, FunctionalState NewState); +ITStatus GTIM_GetITStatus(GTIM_TypeDef* GTIMx, uint32_t GTIM_IT); +void GTIM_ClearITPendingBit(GTIM_TypeDef* GTIMx, uint32_t GTIM_IT); +void GTIM_DMAConfig(GTIM_TypeDef* GTIMx, uint32_t GTIM_DMA,FunctionalState NewState); +void GTIM1_ITRConfig(uint32_t ITRSouce); +void GTIM2_ITRConfig(uint32_t ITRSouce); +void GTIM3_ITRConfig(uint32_t ITRSouce); +void GTIM4_ITRConfig(uint32_t ITRSouce); + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32F030_GTIM_H */ diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_i2c.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_i2c.h new file mode 100644 index 0000000..51c4308 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_i2c.h @@ -0,0 +1,164 @@ +/** + * @file cw32f030_i2c.h + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-04-27 + * + * @copyright Copyright (c) 2021 + * x + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F03x_I2C_H +#define __CW32F03x_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" +#include "base_types.h" +#include "cw32f030_rcc.h" +/** + * @brief I2Cͨѡ + * + */ + typedef enum en_i2c_channel + { + I2C1 = 0,///<ͨ1 + I2C2 = 1,///<ͨ2 + }en_i2c_channel_t; + +/** + ****************************************************************************** + ** \brief I2Cʼýṹ + *****************************************************************************/ +typedef struct +{ + FunctionalState I2C_BaudEn; ///<ʼʹ + uint8_t I2C_Baud; ///<ʼ + uint8_t I2C_OwnSlaveAddr0; ///<ӻַ0 + FunctionalState I2C_OwnGc; ///<㲥Ӧʹ + uint8_t I2C_OwnSlaveAddr1; ///<ӻַ1 + uint8_t I2C_OwnSlaveAddr2; ///<ӻַ2 + FunctionalState I2C_FLT; ///KR = IWDT_RUN_KEY) +#define __IWDT_REFRESH() (CW_IWDT->KR = IWDT_REFRESH_KEY) +#define __IWDT_STOP() do{ \ + CW_IWDT->KR = IWDT_STOP_KEY1;\ + CW_IWDT->KR = IWDT_STOP_KEY2;\ + } while(0) +#define __IWDT_UNLOCK() (CW_IWDT->KR = IWDT_UNLOCK_KEY) +#define __IWDT_LOCK() (CW_IWDT->KR = IWDT_LOCK_KEY) + + + /****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + + /****************************************************************************** + * Global function prototypes + ******************************************************************************/ +void IWDT_DeInit(void); +void IWDT_Init(IWDT_InitTypeDef *IWDT_InitStruct); + +void IWDT_Cmd(void); +void IWDT_Refresh(void); + +void IWDT_Unlock(void); +void IWDT_Lock(void); +void IWDT_Stop(void); + +void IWDT_SetPrescaler(uint32_t WWDT_Prescaler); +void IWDT_SetWindowValue(uint32_t WindowValue); +void IWDT_SetReloadValue(uint32_t ReloadValue); +void IWDT_ITConfig(FunctionalState NewState); +FlagStatus IWDT_GetFlagStatus(uint32_t StatusBit); +void IWDT_ClearOVFlag(void); +uint32_t IWDT_GetCounterValue(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32F030_IWDT_H */ +/** + * @} + */ diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_lvd.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_lvd.h new file mode 100644 index 0000000..1153d64 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_lvd.h @@ -0,0 +1,248 @@ +/** + * @file cw32f030_lvd.h + * @author P&S (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-06-21 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +#ifndef __CW32F030_LVD_H +#define __CW32F030_LVD_H + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "base_types.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup LvdGroup Low Voltage Detector (LVD) + ** + ******************************************************************************/ +//@{ +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define LVD_INT_PRIORITY ((uint32_t)3) /*VC interrupt priority (lowest by default) */ + +/** + * @} + */ +/** @defgroup LVD_interrupts_definition + * @{ + */ +#define LVD_TRIG_LEVEL ((uint16_t)0x0080) +#define LVD_TRIG_FALL ((uint16_t)0x0040) +#define LVD_TRIG_RISE ((uint16_t)0x0020) + + +#define IS_LVD_TRIG(TRIG) ((((TRIG) & (uint16_t)0xFF00) == 0x00) && ((TRIG) != 0x00)) +#define IS_LVD_GET_TRIG(TRIG) (((TRIG) == LVD_TRIG_LEVEL) || \ + ((TRIG) == LVD_TRIG_FALL) || \ + ((TRIG) == LVD_TRIG_RISE)) + +/** @defgroup LVD_flags_definition + * @{ + */ +#define LVD_FLAG_FLTV ((uint16_t)0x0002) +#define LVD_FLAG_INTF ((uint16_t)0x0001) + +#define IS_LVD_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFF00) == 0x00) && ((FLAG) != 0x00)) +#define IS_LVD_GET_FLAG(FLAG) (((FLAG) == LVD_FLAG_FLTV) || \ + ((FLAG) == LVD_FLAG_INTF)) + + +/** @defgroup LVD_Action + * @{ + */ +#define LVD_Action_Irq ((uint32_t)0x00000000) +#define LVD_Action_Reset ((uint32_t)0x00000002) + +#define IS_LVD_ACTION(ACTION) (((ACTION) == LVD_Action_Irq) || \ + ((ACTION) == LVD_Action_Reset)) + +/** @defgroup LVD_Source + * @{ + */ +#define LVD_Source_VDDA ((uint32_t)0x00000000) +#define LVD_Source_PA00 ((uint32_t)0x00000004) +#define LVD_Source_PB00 ((uint32_t)0x00000008) +#define LVD_Source_PB11 ((uint32_t)0x0000000C) + +#define IS_LVD_SOURCE(SOURCE) (((SOURCE) == LVD_Source_VDDA) || \ + ((SOURCE) == LVD_Source_PA00) || \ + ((SOURCE) == LVD_Source_PB00) || \ + ((SOURCE) == LVD_Source_PB11)) + +/** @defgroup LVD_Threshold + * @{ + */ +#define LVD_Threshold_2p0V ((uint32_t)0x00000000) +#define LVD_Threshold_2p11V ((uint32_t)0x00000010) +#define LVD_Threshold_2p22V ((uint32_t)0x00000020) +#define LVD_Threshold_2p33V ((uint32_t)0x00000030) +#define LVD_Threshold_2p44V ((uint32_t)0x00000040) +#define LVD_Threshold_2p55V ((uint32_t)0x00000050) +#define LVD_Threshold_2p66V ((uint32_t)0x00000060) +#define LVD_Threshold_2p77V ((uint32_t)0x00000070) +#define LVD_Threshold_2p88V ((uint32_t)0x00000080) +#define LVD_Threshold_2p99V ((uint32_t)0x00000090) +#define LVD_Threshold_3p1V ((uint32_t)0x000000A0) +#define LVD_Threshold_3p21V ((uint32_t)0x000000B0) +#define LVD_Threshold_3p32V ((uint32_t)0x000000C0) +#define LVD_Threshold_3p43V ((uint32_t)0x000000D0) +#define LVD_Threshold_3p54V ((uint32_t)0x000000E0) +#define LVD_Threshold_3p65V ((uint32_t)0x000000F0) + +#define IS_LVD_THRESHOLD(THRESHOLD) (((THRESHOLD) == LVD_Threshold_2p0V) || \ + ((THRESHOLD) == LVD_Threshold_2p11V) || \ + ((THRESHOLD) == LVD_Threshold_2p22V) || \ + ((THRESHOLD) == LVD_Threshold_2p33V) || \ + ((THRESHOLD) == LVD_Threshold_2p44V) || \ + ((THRESHOLD) == LVD_Threshold_2p55V) || \ + ((THRESHOLD) == LVD_Threshold_2p66V) || \ + ((THRESHOLD) == LVD_Threshold_2p77V) || \ + ((THRESHOLD) == LVD_Threshold_2p88V) || \ + ((THRESHOLD) == LVD_Threshold_2p99V) || \ + ((THRESHOLD) == LVD_Threshold_3p1V) || \ + ((THRESHOLD) == LVD_Threshold_3p21V) || \ + ((THRESHOLD) == LVD_Threshold_3p32V) || \ + ((THRESHOLD) == LVD_Threshold_3p43V) || \ + ((THRESHOLD) == LVD_Threshold_3p54V) || \ + ((THRESHOLD) == LVD_Threshold_3p65V)) + +/** @defgroup LVD_Filter + * @{ + */ +#define LVD_Filter_Disable ((uint32_t)0x00000000) +#define LVD_Filter_Enable ((uint32_t)0x00000001) + +#define IS_LVD_FILTER(FILTER) (((FILTER) == LVD_Filter_Disable) || \ + ((FILTER) == LVD_Filter_Enable)) + +/** @defgroup LVD_FilterClk + * @{ + */ +#define LVD_FilterClk_RC150K ((uint32_t)0x00000000) +#define LVD_FilterClk_HSI ((uint32_t)0x00000010) + +#define IS_LVD_FILTER_CLK(FILTER_CLK) (((FILTER_CLK) == LVD_FilterClk_RC150K) || \ + ((FILTER_CLK) == LVD_FilterClk_HSI)) + +/** @defgroup LVD_FilterTime + * @{ + */ +#define LVD_FilterTime_1Clk ((uint32_t)0x00000000) +#define LVD_FilterTime_3Clk ((uint32_t)0x00000002) +#define LVD_FilterTime_7Clk ((uint32_t)0x00000004) +#define LVD_FilterTime_15Clk ((uint32_t)0x00000006) +#define LVD_FilterTime_63Clk ((uint32_t)0x00000008) +#define LVD_FilterTime_255Clk ((uint32_t)0x0000000A) +#define LVD_FilterTime_1023Clk ((uint32_t)0x0000000C) +#define LVD_FilterTime_4095Clk ((uint32_t)0x0000000E) + +#define IS_LVD_FILTER_TIME(FILTER_TIME) (((FILTER_TIME) == LVD_FilterTime_1Clk) || \ + ((FILTER_TIME) == LVD_FilterTime_3Clk) || \ + ((FILTER_TIME) == LVD_FilterTime_7Clk) || \ + ((FILTER_TIME) == LVD_FilterTime_15Clk) || \ + ((FILTER_TIME) == LVD_FilterTime_63Clk) || \ + ((FILTER_TIME) == LVD_FilterTime_255Clk) || \ + ((FILTER_TIME) == LVD_FilterTime_1023Clk) || \ + ((FILTER_TIME) == LVD_FilterTime_4095Clk)) + +/** + ****************************************************************************** + ** @brief LVD + ** \note + ******************************************************************************/ +typedef struct +{ + uint32_t LVD_Action; // LVD + uint32_t LVD_Source; // LVDѹԴ + uint32_t LVD_Threshold; // LVDֵѹ + uint32_t LVD_FilterEn; // Ƿʹ˲ + uint32_t LVD_FilterClk; // ˲ʱԴ + uint32_t LVD_FilterTime; // ˲ʱ +}LVD_InitTypeDef; + +/****************************************************************************** + * Global definitions + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions ('extern') + ******************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + ******************************************************************************/ +//ʹNVICLVDж +void LVD_EnableNvic(uint8_t intPriority); +//ֹNVICLVDж +void LVD_DisableNvic(void); +//LVDж/ϵͳλʽ +void LVD_TrigConfig(uint16_t LVD_TRIG, FunctionalState NewState); +//ʹLVDж +void LVD_EnableIrq(uint8_t intPriority); +//ֹLVDж +void LVD_DisableIrq(void); + +//LVDжϱ־ +void LVD_ClearIrq(void); +//ȡLVDжϱ־ +boolean_t LVD_GetIrqStatus(void); +//ȡLVDָ״̬λ +FlagStatus LVD_GetFlagStatus(uint16_t LVD_FLAG); +//ȡFilter +boolean_t LVD_GetFilterResult(void); + +//LVDʼ +void LVD_Init(LVD_InitTypeDef* LVD_InitStruct); +//LVDȥʼ +void LVD_DeInit(void); + +//ʹLVD +void LVD_Enable(void); +//ֹͣLVD +void LVD_Disable(void); + +//@} // LvdGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __CW32F030_LVD_H */ +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_pwr.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_pwr.h new file mode 100644 index 0000000..b80bdba --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_pwr.h @@ -0,0 +1,119 @@ +/** + * @file cw32f030_pwr.h + * @author P&S (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-06-21 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +#ifndef __CW32F030_PWR_H +#define __CW32F030_PWR_H + +/***************************************************************************** + * Include files + *****************************************************************************/ +#include "base_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup LpmGroup Low Power Management (LPM) + ** + ** + ******************************************************************************/ +//@{ + +/****************************************************************************** + ** Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** @defgroup PWR_Sevonpend + * @{ + */ +#define PWR_Sevonpend_Disable ((uint32_t)0x00000000) +#define PWR_Sevonpend_Enable ((uint32_t)0x00000010) + +#define IS_PWR_SEVONPEND(SEVONPEND) (((SEVONPEND) == PWR_Sevonpend_Disable) || \ + ((SEVONPEND) == PWR_Sevonpend_Enable)) + +/** @defgroup PWR_SleepDeep + * @{ + */ +#define PWR_SleepDeep_Disable ((uint32_t)0x00000000) +#define PWR_SleepDeep_Enable ((uint32_t)0x00000004) + +#define IS_PWR_SLEEPDEEP(SLEEPDEEP) (((SLEEPDEEP) == PWR_SleepDeep_Disable) || \ + ((SLEEPDEEP) == PWR_SleepDeep_Enable)) + +/** @defgroup PWR_SleepOnExit + * @{ + */ +#define PWR_SleepOnExit_Disable ((uint32_t)0x00000000) +#define PWR_SleepOnExit_Enable ((uint32_t)0x00000002) + +#define IS_PWR_SLEEPONEXIT(SLEEPONEXIT) (((SLEEPONEXIT) == PWR_SleepOnExit_Disable) || \ + ((SLEEPONEXIT) == PWR_SleepOnExit_Enable)) + +/** + ****************************************************************************** + ** @brief Low Power Mode ýṹ嶨 + *****************************************************************************/ +typedef struct +{ + uint32_t PWR_Sevonpend; // ʹ:ÿжϻһ¼,ʹWFE,ڻѴ. + uint32_t PWR_SleepDeep; // ʹ:ִWFI;ʹ:ִWFI. + uint32_t PWR_SleepOnExit; // ʹ:˳쳣ʱ,Զģʽ;ʹ:Խֹ. +}PWR_InitTypeDef; + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + *****************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + *****************************************************************************/ +//ü +//͹ģʽ +void PWR_Config(PWR_InitTypeDef* PWR_InitTypeDef); +//͹ģʽ +void PWR_GotoLpmMode(void); + +//@} // PWRGroup + +#ifdef __cplusplus +#endif + + +#endif /* __CW32F030_PWR_H */ +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ + + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_ram.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_ram.h new file mode 100644 index 0000000..f4a8f93 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_ram.h @@ -0,0 +1,72 @@ +/** + * @file cw32f030_ram.h + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-14 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F03x_RAM_H__ +#define __CW32F03x_RAM_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "base_types.h" +#include "cw32f030.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +//============================================================ + +/** @defgroup жϱ־λ + * @{ + */ +#define RAM_IT_PARITY (bv1) +#define IS_RAM_IT(IT) (((IT) & 0xFFFFFFFD == 0x0UL) && ((IT) != 0x0UL)) +#define IS_RAM_GET_IT(IT) ((IT) == RAM_IT_PARITY) + +//============================================================ + +//RAM PARITYжʹ +void RAM_ITConfig(uint32_t RAM_IT, FunctionalState NewState); +//ȡRAM PARITYжϱ־λ +ITStatus RAM_GetITStatus(uint32_t RAM_IT); +//RAM PARITYϱ־λ +void RAM_ClearITPendingBit(uint32_t RAM_IT); +//ȡżУRAMַ// +uint32_t RAM_GetErrorAddress(void); + +//============================================================ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_rcc.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_rcc.h new file mode 100644 index 0000000..91c7e88 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_rcc.h @@ -0,0 +1,538 @@ +/** + * @file cw32f030_rcc.h + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-13 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_RCC_H +#define __CW32F030_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" + +//================================================================================== +#ifdef __PRIVATE_DEBUG +#define HSIOSC_VALUE ((uint32_t)24000000) /*!< Value of the Internal oscillator in Hz*/ +#define HSE_VALUE ((uint32_t)32000000) /*!< Value of the External oscillator in Hz */ +#else +#define HSIOSC_VALUE ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/ +#define HSE_VALUE ((uint32_t)16000000) /*!< Value of the External oscillator in Hz */ +#endif + +#define LSI_VALUE ((uint32_t)32800) /*!< Value of the External oscillator in Hz */ +#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz */ +/* SYSCTRL CR0 --------------------------------------------------------*/ +#define SYSCTRL_BYPASS (0x5A5A0000U) +#define SYSCTRL_BYPASS_MASK (0xFFFF0000U) + +#define RCC_HCLK_DIV1 (0x0UL << SYSCTRL_CR0_HCLKPRS_Pos) /*!< SYSCLK not divided */ +#define RCC_HCLK_DIV2 (0x1UL << SYSCTRL_CR0_HCLKPRS_Pos) /*!< SYSCLK divided by 2 */ +#define RCC_HCLK_DIV4 (0x2UL << SYSCTRL_CR0_HCLKPRS_Pos) /*!< SYSCLK divided by 4 */ +#define RCC_HCLK_DIV8 (0x3UL << SYSCTRL_CR0_HCLKPRS_Pos) /*!< SYSCLK divided by 8 */ +#define RCC_HCLK_DIV16 (0x4UL << SYSCTRL_CR0_HCLKPRS_Pos) /*!< SYSCLK divided by 16 */ +#define RCC_HCLK_DIV32 (0x5UL << SYSCTRL_CR0_HCLKPRS_Pos) /*!< SYSCLK divided by 32 */ +#define RCC_HCLK_DIV64 (0x6UL << SYSCTRL_CR0_HCLKPRS_Pos) /*!< SYSCLK divided by 64 */ +#define RCC_HCLK_DIV128 (0x7ul << SYSCTRL_CR0_HCLKPRS_Pos) /*!< SYSCLK divided by 128 */ +#define IS_RCC_HCLKPRS(INSTANCE) (((INSTANCE) == RCC_HCLK_DIV1) ||\ + ((INSTANCE) == RCC_HCLK_DIV2) ||\ + ((INSTANCE) == RCC_HCLK_DIV4) ||\ + ((INSTANCE) == RCC_HCLK_DIV8) ||\ + ((INSTANCE) == RCC_HCLK_DIV16) ||\ + ((INSTANCE) == RCC_HCLK_DIV32) ||\ + ((INSTANCE) == RCC_HCLK_DIV64) ||\ + ((INSTANCE) == RCC_HCLK_DIV128)) + +#define RCC_PCLK_DIV1 (0x0UL << SYSCTRL_CR0_PCLKPRS_Pos) /*!< HCLK not divided */ +#define RCC_PCLK_DIV2 (0x1UL << SYSCTRL_CR0_PCLKPRS_Pos) /*!< HCLK divided by 2 */ +#define RCC_PCLK_DIV4 (0x2UL << SYSCTRL_CR0_PCLKPRS_Pos) /*!< HCLK divided by 4 */ +#define RCC_PCLK_DIV8 (0x3UL << SYSCTRL_CR0_PCLKPRS_Pos) /*!< HCLK divided by 8 */ +#define IS_RCC_PCLKPRS(INSTANCE) (((INSTANCE) == RCC_PCLK_DIV1) ||\ + ((INSTANCE) == RCC_PCLK_DIV2) ||\ + ((INSTANCE) == RCC_PCLK_DIV4) ||\ + ((INSTANCE) == RCC_PCLK_DIV8) + +#define RCC_SYSCLKSRC_HSI (0x00000000U) /*!< HSI selected as system clock */ +#define RCC_SYSCLKSRC_HSE (0x00000001U) /*!< HSE selected as system clock */ +#define RCC_SYSCLKSRC_PLL (0x00000002U) /*!< PLL selected as system clock */ +#define RCC_SYSCLKSRC_LSI (0x00000003U) /*!< LSI selected as system clock */ +#define RCC_SYSCLKSRC_LSE (0x00000004U) /*!< LSE selected as system clock */ +#define IS_RCC_SYSCLKSRC(INSTANCE) (((INSTANCE) == RCC_SYSCLKSRC_HSI) ||\ + ((INSTANCE) == RCC_SYSCLKSRC_HSE) ||\ + ((INSTANCE) == RCC_SYSCLKSRC_PLL) ||\ + ((INSTANCE) == RCC_SYSCLKSRC_LSI) ||\ + ((INSTANCE) == RCC_SYSCLKSRC_LSE)) + +// #define RCC_OLDCLK_OFF (0x00000000U) +// #define RCC_OLDCLK_ON (0x00000001U) + +// #define IS_RCC_OLDCLK_STATE(INSTANCE) (((INSTANCE) == RCC_OLDCLK_OFF) ||\ +// ((INSTANCE) == RCC_OLDCLK_ON)) + + +/* SYSCTRL CR1 --------------------------------------------------------*/ +#define RCC_SYSCTRL_HSIEN bv0 +#define RCC_SYSCTRL_HSEEN bv1 +#define RCC_SYSCTRL_PLLEN bv2 +#define RCC_SYSCTRL_LSIEN bv3 +#define RCC_SYSCTRL_LSEEN bv4 + +#define RCC_SYSCTRL_LSELOCKEN bv5 +#define RCC_SYSCTRL_LSELOCKDIS 0x00UL +#define IS_RCC_LSELOCK_STATUS(INSTANCE) (((INSTANCE) == RCC_SYSCTRL_LSELOCKEN) ||\ + ((INSTANCE) == RCC_SYSCTRL_LSELOCKDIS)) + +#define RCC_SYSCTRL_LSECCS bv6 +#define RCC_SYSCTRL_HSECCS bv7 +#define RCC_SYSCTRL_CLKCCS bv8 +#define IS_RCC_CCS_STATUS(INSTANCE) (((INSTANCE) == RCC_SYSCTRL_LSECCS) ||\ + ((INSTANCE) == RCC_SYSCTRL_HSECCS) ||\ + ((INSTANCE) == RCC_SYSCTRL_CLKCCS)) + +/* SYSCTRL CR2 --------------------------------------------------------*/ +#define RCC_SYSCTRL_SWDIOEN 0x00UL +#define RCC_SYSCTRL_SWDIODIS bv1 +#define IS_RCC_SWDIO_STATUS(INSTANCE) (((INSTANCE) == RCC_SYSCTRL_SWDIOEN) ||\ + ((INSTANCE) == RCC_SYSCTRL_SWDIODIS)) + +#define RCC_SYSCTRL_LOCKUPEN bv2 +#define RCC_SYSCTRL_LOCKUPDIS 0x00UL +#define IS_RCC_LOCKUP_STATUS(INSTANCE) (((INSTANCE) == RCC_SYSCTRL_LOCKUPEN) ||\ + ((INSTANCE) == RCC_SYSCTRL_LOCKUPDIS)) + +#define RCC_SYSCTRL_WAKEUPCLKEN bv3 +#define RCC_SYSCTRL_WAKEUPCLKDIS 0x00UL +#define IS_RCC_WAKEUPCLK_STATUS(INSTANCE) (((INSTANCE) == RCC_SYSCTRL_WAKEUPCLKEN) ||\ + ((INSTANCE) == RCC_SYSCTRL_WAKEUPCLKDIS)) +/* SYSCTRL HSI --------------------------------------------------------*/ +#ifdef __PRIVATE_DEBUG +#define RCC_HSI_TRIMCODEADDR (0x001007ACU) //CHIP1 +#else +#define RCC_HSI_TRIMCODEADDR (0x00012600U) //CHIP2 +#endif + +#define RCC_HSIOSC_DIV6 (0x5U) +#define RCC_HSIOSC_DIV1 (0x6U) +#define RCC_HSIOSC_DIV2 (0x8U) +#define RCC_HSIOSC_DIV3 (0x7U) +#define RCC_HSIOSC_DIV4 (0x9U) +//#define RCC_HSIOSC_DIV6 (0xAU) +#define RCC_HSIOSC_DIV8 (0xBU) +#define RCC_HSIOSC_DIV10 (0xCU) +#define RCC_HSIOSC_DIV12 (0xDU) +#define RCC_HSIOSC_DIV14 (0xEU) +#define RCC_HSIOSC_DIV16 (0xFU) + +#define IS_RCC_HSIOSC_DIV(INSTANCE) (((INSTANCE) == RCC_HSIOSC_DIV1) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV2) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV3) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV4) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV6) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV8) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV10) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV12) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV14) ||\ + ((INSTANCE) == RCC_HSIOSC_DIV16)) + +/* SYSCTRL LSI --------------------------------------------------------*/ +#ifdef __PRIVATE_DEBUG +#define RCC_LSI_TRIMCODEADDR (0x001007B2U) //CHIP1 +#else +#define RCC_LSI_TRIMCODEADDR (0x00012602U) //CHIP2 +#endif + +#define RCC_LSI_WAITCYCLE_6 ((uint32_t)(0x0UL << SYSCTRL_LSI_WAITCYCLE_Pos)) +#define RCC_LSI_WAITCYCLE_18 ((uint32_t)(0x1UL << SYSCTRL_LSI_WAITCYCLE_Pos)) +#define RCC_LSI_WAITCYCLE_66 ((uint32_t)(0x2UL << SYSCTRL_LSI_WAITCYCLE_Pos)) +#define RCC_LSI_WAITCYCLE_258 ((uint32_t)(0x3UL << SYSCTRL_LSI_WAITCYCLE_Pos)) + + +/* SYSCTRL HSE --------------------------------------------------------*/ +#define RCC_HSE_FLT_CLOSE (0x00000000U) +#define RCC_HSE_FLT_OPEN SYSCTRL_HSE_FLT_Msk //(0x80UL) +#define IS_RCC_HSE_FLT(INSTANCE) (((INSTANCE) == RCC_HSE_FLT_CLOSE) ||\ + ((INSTANCE) == RCC_HSE_FLT_OPEN)) + +#define RCC_HSE_MODE_OSC (0x00000000U) +#define RCC_HSE_MODE_CLK SYSCTRL_HSE_MODE_Msk //(0x40UL) +#define IS_RCC_HSE_MODE(INSTANCE) (((INSTANCE) == RCC_HSE_MODE_OSC) ||\ + ((INSTANCE) == RCC_HSE_MODE_CLK)) + +#define RCC_HSE_WAITCYCLE_8192 (0x00000000U) +#define RCC_HSE_WAITCYCLE_32768 ((uint32_t)(0x1UL << SYSCTRL_HSE_WAITCYCLE_Pos)) +#define RCC_HSE_WAITCYCLE_131072 ((uint32_t)(0x2UL << SYSCTRL_HSE_WAITCYCLE_Pos)) +#define RCC_HSE_WAITCYCLE_262144 ((uint32_t)(0x3UL << SYSCTRL_HSE_WAITCYCLE_Pos)) + +#define RCC_HSE_FREQ_GT4M (0x00000000U) +#define RCC_HSE_FREQ_GT8M ((uint32_t)(0x1UL << SYSCTRL_HSE_FREQ_Pos)) +#define RCC_HSE_FREQ_GT16M ((uint32_t)(0x2UL << SYSCTRL_HSE_FREQ_Pos)) +#define RCC_HSE_FREQ_GT24M ((uint32_t)(0x3UL << SYSCTRL_HSE_FREQ_Pos)) +#define IS_RCC_HSE_FREQIN(INSTANCE) (((INSTANCE) >=4000000) && ((INSTANCE) <=32000000)) + +#define RCC_HSE_DRIVER_LEAST 0x00U +#define RCC_HSE_DRIVER_SMALL 0x01U +#define RCC_HSE_DRIVER_NORMAL 0x02U +#define RCC_HSE_DRIVER_LARGER 0x03U +#define IS_RCC_HSE_DRIVER(INSTANCE) (((INSTANCE) == RCC_HSE_DRIVER_LEAST) ||\ + ((INSTANCE) == RCC_HSE_DRIVER_SMALL) ||\ + ((INSTANCE) == RCC_HSE_DRIVER_NORMAL) ||\ + ((INSTANCE) == RCC_HSE_DRIVER_LARGER)) + +/* SYSCTRL LSE --------------------------------------------------------*/ +#define RCC_LSE_MODE_OSC (0x00000000U) +#define RCC_LSE_MODE_CLK SYSCTRL_LSE_MODE_Msk + +#define IS_RCC_LSE_MODE(INSTANCE) (((INSTANCE) == RCC_LSE_MODE_OSC) ||\ + ((INSTANCE) == RCC_LSE_MODE_CLK)) + +#define RCC_LSE_AMP_LEAST (0x00000000U) +#define RCC_LSE_AMP_SMALL ((uint32_t)(0x1UL << SYSCTRL_LSE_AMP_Pos)) +#define RCC_LSE_AMP_NORMAL ((uint32_t)(0x2UL << SYSCTRL_LSE_AMP_Pos)) +#define RCC_LSE_AMP_LARGER ((uint32_t)(0x3UL << SYSCTRL_LSE_AMP_Pos)) +#define IS_RCC_LSE_AMP(AMP) (((AMP) == RCC_LSE_AMP_LEAST) ||\ + ((AMP) == RCC_LSE_AMP_SMALL) ||\ + ((AMP) == RCC_LSE_AMP_NORMAL) ||\ + ((AMP) == RCC_LSE_AMP_LARGER)) + +#define RCC_LSE_DRIVER_LEAST (0x00000000U) +#define RCC_LSE_DRIVER_SMALL (0x00000001U) +#define RCC_LSE_DRIVER_NORMAL (0x00000002U) +#define RCC_LSE_DRIVER_LARGER (0x00000003U) + +#define IS_RCC_LSE_DRIVER(DRIVER) (((DRIVER) == RCC_LSE_DRIVER_LEAST) ||\ + ((DRIVER) == RCC_LSE_DRIVER_SMALL) ||\ + ((DRIVER) == RCC_LSE_DRIVER_NORMAL) ||\ + ((DRIVER) == RCC_LSE_DRIVER_LARGER)) + +#define RCC_LSE_WAITCYCLE_256 (0x00000000U) +#define RCC_LSE_WAITCYCLE_1024 ((uint32_t)(0x1UL << SYSCTRL_LSE_WAITCYCLE_Pos)) +#define RCC_LSE_WAITCYCLE_4096 ((uint32_t)(0x2UL << SYSCTRL_LSE_WAITCYCLE_Pos)) +#define RCC_LSE_WAITCYCLE_16384 ((uint32_t)(0x3UL << SYSCTRL_LSE_WAITCYCLE_Pos)) + + + +/* SYSCTRL PLL --------------------------------------------------------*/ +#define RCC_PLLSOURCE_HSEOSC (0x00000000U) /*!< HSE oscillator clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSECLK (0x00000001U) /*!< HSE input clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSI (0x00000003U) /*!< HSI clock selected as PLL entry clock source */ + +#define IS_RCC_PLLSOURCE(INSTANCE) (((INSTANCE) == RCC_PLLSOURCE_HSEOSC) ||\ + ((INSTANCE) == RCC_PLLSOURCE_HSECLK) ||\ + ((INSTANCE) == RCC_PLLSOURCE_HSI)) + +#define RCC_PLL_WAITCYCLE_128 (0x00000000U) +#define RCC_PLL_WAITCYCLE_256 ((uint32_t)(0x1UL << SYSCTRL_PLL_WAITCYCLE_Pos)) +#define RCC_PLL_WAITCYCLE_512 ((uint32_t)(0x2UL << SYSCTRL_PLL_WAITCYCLE_Pos)) +#define RCC_PLL_WAITCYCLE_1024 ((uint32_t)(0x3UL << SYSCTRL_PLL_WAITCYCLE_Pos)) +#define RCC_PLL_WAITCYCLE_2048 ((uint32_t)(0x4UL << SYSCTRL_PLL_WAITCYCLE_Pos)) +#define RCC_PLL_WAITCYCLE_4096 ((uint32_t)(0x5UL << SYSCTRL_PLL_WAITCYCLE_Pos)) +#define RCC_PLL_WAITCYCLE_8192 ((uint32_t)(0x6UL << SYSCTRL_PLL_WAITCYCLE_Pos)) +#define RCC_PLL_WAITCYCLE_16384 ((uint32_t)(0x7UL << SYSCTRL_PLL_WAITCYCLE_Pos)) + +#define RCC_PLL_FREQOUT_GT12M (0x00000000U) +#define RCC_PLL_FREQOUT_GT18M ((uint32_t)(0x1UL << SYSCTRL_PLL_FREQOUT_Pos)) +#define RCC_PLL_FREQOUT_GT24M ((uint32_t)(0x2UL << SYSCTRL_PLL_FREQOUT_Pos)) +#define RCC_PLL_FREQOUT_GT36M ((uint32_t)(0x3UL << SYSCTRL_PLL_FREQOUT_Pos)) +#define RCC_PLL_FREQOUT_GT48M ((uint32_t)(0x4UL << SYSCTRL_PLL_FREQOUT_Pos)) +#define IS_RCC_PLL_FREQIN(INSTANCE) (INSTANCE >=4000000) && (INSTANCE <=24000000) + + +#define RCC_PLL_MUL_2 (0x2U) +#define RCC_PLL_MUL_3 (0x3U) +#define RCC_PLL_MUL_4 (0x4U) +#define RCC_PLL_MUL_5 (0x5U) +#define RCC_PLL_MUL_6 (0x6U) +#define RCC_PLL_MUL_7 (0x7U) +#define RCC_PLL_MUL_8 (0x8U) +#define RCC_PLL_MUL_9 (0x9U) +#define RCC_PLL_MUL_10 (0xAU) +#define RCC_PLL_MUL_11 (0xBU) +#define RCC_PLL_MUL_12 (0xCU) +#define IS_RCC_PLL_MUL(INSTANCE) (((INSTANCE) == RCC_PLL_MUL_2) ||\ + ((INSTANCE) == RCC_PLL_MUL_3) ||\ + ((INSTANCE) == RCC_PLL_MUL_4) ||\ + ((INSTANCE) == RCC_PLL_MUL_5) ||\ + ((INSTANCE) == RCC_PLL_MUL_6) ||\ + ((INSTANCE) == RCC_PLL_MUL_7) ||\ + ((INSTANCE) == RCC_PLL_MUL_8) ||\ + ((INSTANCE) == RCC_PLL_MUL_9) ||\ + ((INSTANCE) == RCC_PLL_MUL_10) ||\ + ((INSTANCE) == RCC_PLL_MUL_11) ||\ + ((INSTANCE) == RCC_PLL_MUL_12)) + + +#define RCC_IT_HSEFAULT (bv8) +#define RCC_IT_LSEFAULT (bv7) +#define RCC_IT_HSEFAIL (bv6) +#define RCC_IT_LSEFAIL (bv5) +#define RCC_IT_LSERDY (bv4) +#define RCC_IT_LSIRDY (bv3) +#define RCC_IT_PLLRDY (bv2) +#define RCC_IT_HSERDY (bv1) +#define RCC_IT_HSIRDY (bv0) +#define IS_RCC_IT(IT) (((IT) & 0xFFFFFFE0 == 0x0UL) && ((IT) != 0x0UL)) +#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_HSEFAULT) || \ + ((IT) == RCC_IT_LSEFAULT) || \ + ((IT) == RCC_IT_HSEFAIL) || \ + ((IT) == RCC_IT_LSEFAIL) ||\ + ((IT) == RCC_IT_LSERDY) ||\ + ((IT) == RCC_IT_LSIRDY) ||\ + ((IT) == RCC_IT_PLLRDY) ||\ + ((IT) == RCC_IT_HSERDY) ||\ + ((IT) == RCC_IT_HSIRDY)) + + +#define RCC_FLAG_HSISTABLE bv11 +#define RCC_FLAG_HSESTABLE bv12 +#define RCC_FLAG_PLLSTABLE bv13 +#define RCC_FLAG_LSESTABLE bv15 +#define RCC_FLAG_LSISTABLE bv14 +#define IS_RCC_STABLEFLAG(FLAG) (((FLAG) == RCC_FLAG_HSISTABLE) || ((FLAG) == RCC_FLAG_HSESTABLE) || \ + ((FLAG) == RCC_FLAG_PLLSTABLE) || ((FLAG) == RCC_FLAG_LSESTABLE) || \ + ((FLAG) == RCC_FLAG_LSISTABLE)) + +#define RCC_FLAG_PINRST bv6 +#define RCC_FLAG_PORRST bv0 +#define RCC_FLAG_LVDRST bv3 +#define RCC_FLAG_LOCKUPRST bv8 +#define RCC_FLAG_IWDTRST bv4 +#define RCC_FLAG_WWDTRST bv5 +#define RCC_FLAG_SYSRESETREQRST bv9 +#define RCC_FLAG_ALLRST ((uint32_t)0x00000379) +#define IS_RCC_RSTFLAG(FLAG) (((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_LVDRST) || ((FLAG) == RCC_FLAG_IWDTRST) || \ + ((FLAG) == RCC_FLAG_WWDTRST) || ((FLAG) == RCC_FLAG_LOCKUPRST) || \ + ((FLAG) == RCC_FLAG_SYSRESETREQRST) || ((FLAG) == RCC_FLAG_ALLRST)) + + +#define RCC_AHB_PERIPH_GPIOF bv9 +#define RCC_AHB_PERIPH_GPIOC bv6 +#define RCC_AHB_PERIPH_GPIOB bv5 +#define RCC_AHB_PERIPH_GPIOA bv4 +#define RCC_AHB_PERIPH_CRC bv2 +#define RCC_AHB_PERIPH_FLASH bv1 +#define RCC_AHB_PERIPH_DMA bv0 +#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFD88 ) == 0x00) && ((PERIPH) != 0x00)) + +#define __RCC_GPIOF_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, RCC_AHB_PERIPH_GPIOF) +#define __RCC_GPIOC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, RCC_AHB_PERIPH_GPIOC) +#define __RCC_GPIOB_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, RCC_AHB_PERIPH_GPIOB) +#define __RCC_GPIOA_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, RCC_AHB_PERIPH_GPIOA) +#define __RCC_CRC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, RCC_AHB_PERIPH_CRC) +#define __RCC_FLASH_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, RCC_AHB_PERIPH_FLASH) +#define __RCC_DMA_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, RCC_AHB_PERIPH_DMA) + +#define __RCC_GPIOF_CLK_DISABLE() (CW_SYSCTRL->AHBEN &= ~(RCC_AHB_PERIPH_GPIOF)) +#define __RCC_GPIOC_CLK_DISABLE() (CW_SYSCTRL->AHBEN &= ~(RCC_AHB_PERIPH_GPIOC)) +#define __RCC_GPIOB_CLK_DISABLE() (CW_SYSCTRL->AHBEN &= ~(RCC_AHB_PERIPH_GPIOB)) +#define __RCC_GPIOA_CLK_DISABLE() (CW_SYSCTRL->AHBEN &= ~(RCC_AHB_PERIPH_GPIOA)) +#define __RCC_CRC_CLK_DISABLE() (CW_SYSCTRL->AHBEN &= ~(RCC_AHB_PERIPH_CRC)) +#define __RCC_FLASH_CLK_DISABLE() (CW_SYSCTRL->AHBEN &= ~(RCC_AHB_PERIPH_FLASH)) +#define __RCC_DMA_CLK_DISABLE() (CW_SYSCTRL->AHBEN &= ~(RCC_AHB_PERIPH_DMA)) + +#define RCC_APB1_PERIPH_I2C2 bv12 +#define RCC_APB1_PERIPH_I2C1 bv11 +#define RCC_APB1_PERIPH_UART3 bv8 +#define RCC_APB1_PERIPH_UART2 bv7 +#define RCC_APB1_PERIPH_SPI2 bv6 +#define RCC_APB1_PERIPH_IWDT bv5 +#define RCC_APB1_PERIPH_WWDT bv4 +#define RCC_APB1_PERIPH_RTC bv3 +#define RCC_APB1_PERIPH_GTIM2 bv2 +#define RCC_APB1_PERIPH_GTIM1 bv1 +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFE601 ) == 0x00) && ((PERIPH) != 0x00)) + +#define __RCC_I2C2_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_I2C2) +#define __RCC_I2C1_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_I2C1) +#define __RCC_UART3_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_UART3) +#define __RCC_UART2_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_UART2) +#define __RCC_SPI2_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_SPI2) +#define __RCC_IWDT_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_IWDT) +#define __RCC_WWDT_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_WWDT) +#define __RCC_RTC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_RTC) +#define __RCC_GTIM2_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_GTIM2) +#define __RCC_GTIM1_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, RCC_APB1_PERIPH_GTIM1) + +#define __RCC_I2C2_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_I2C2)) +#define __RCC_I2C1_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_I2C1)) +#define __RCC_UART3_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_UART3)) +#define __RCC_UART2_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_UART2)) +#define __RCC_SPI2_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_SPI2)) +#define __RCC_IWDT_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_IWDT)) +#define __RCC_WWDT_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_WWDT)) +#define __RCC_RTC_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_RTC)) +#define __RCC_GTIM2_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_GTIM2)) +#define __RCC_GTIM1_CLK_DISABLE() (CW_SYSCTRL->APBEN1 &= ~(RCC_APB1_PERIPH_GTIM1)) + +#define RCC_APB2_PERIPH_AWT bv13 +#define RCC_APB2_PERIPH_BTIM bv12 +#define RCC_APB2_PERIPH_GTIM4 bv11 +#define RCC_APB2_PERIPH_GTIM3 bv10 +#define RCC_APB2_PERIPH_UART1 bv9 +#define RCC_APB2_PERIPH_SPI1 bv8 +#define RCC_APB2_PERIPH_ATIM bv7 +#define RCC_APB2_PERIPH_VC bv4 +#define RCC_APB2_PERIPH_ADC bv2 +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFC06D ) == 0x00) && ((PERIPH) != 0x00)) + +#define __RCC_AWT_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_AWT) +#define __RCC_BTIM_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_BTIM) +#define __RCC_GTIM4_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_GTIM4) +#define __RCC_GTIM3_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_GTIM3) +#define __RCC_UART1_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_UART1) +#define __RCC_SPI1_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_SPI1) +#define __RCC_ATIM_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_ATIM) +#define __RCC_VC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_VC) +#define __RCC_ADC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, RCC_APB2_PERIPH_ADC) + + +#define __RCC_AWT_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_AWT)) +#define __RCC_BTIM_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_BTIM)) +#define __RCC_GTIM4_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_GTIM4)) +#define __RCC_GTIM3_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_GTIM3)) +#define __RCC_UART1_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_UART1)) +#define __RCC_SPI1_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_SPI1)) +#define __RCC_ATIM_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_ATIM)) +#define __RCC_VC_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_VC)) +#define __RCC_ADC_CLK_DISABLE() (CW_SYSCTRL->APBEN2 &= ~(RCC_APB2_PERIPH_ADC)) + +#define RCC_MCO_DIV1 (0x00U) +#define RCC_MCO_DIV2 ((uint8_t)(0x01U << SYSCTRL_MCO_DIV_Pos)) +#define RCC_MCO_DIV8 ((uint8_t)(0x02U << SYSCTRL_MCO_DIV_Pos)) +#define RCC_MCO_DIV64 ((uint8_t)(0x03U << SYSCTRL_MCO_DIV_Pos)) +#define RCC_MCO_DIV128 ((uint8_t)(0x04U << SYSCTRL_MCO_DIV_Pos)) +#define RCC_MCO_DIV256 ((uint8_t)(0x05U << SYSCTRL_MCO_DIV_Pos)) +#define RCC_MCO_DIV512 ((uint8_t)(0x06U << SYSCTRL_MCO_DIV_Pos)) +#define RCC_MCO_DIV1024 ((uint8_t)(0x07U << SYSCTRL_MCO_DIV_Pos)) + +#define IS_RCC_MCO_DIV(INSTANCE) (((INSTANCE) == RCC_MCO_DIV1) ||\ + ((INSTANCE) == RCC_MCO_DIV2) ||\ + ((INSTANCE) == RCC_MCO_DIV8) ||\ + ((INSTANCE) == RCC_MCO_DIV64) ||\ + ((INSTANCE) == RCC_MCO_DIV128) ||\ + ((INSTANCE) == RCC_MCO_DIV256) ||\ + ((INSTANCE) == RCC_MCO_DIV512) ||\ + ((INSTANCE) == RCC_MCO_DIV1024)) + +#define RCC_MCO_SRC_NONE (0x00U) +#define RCC_MCO_SRC_HCLK (0x01U) +#define RCC_MCO_SRC_PCLK (0x02U) +#define RCC_MCO_SRC_HSI (0x03U) +#define RCC_MCO_SRC_LSI (0x04U) +#define RCC_MCO_SRC_HSE (0x05U) +#define RCC_MCO_SRC_LSE (0x06U) +#define RCC_MCO_SRC_PLL (0x07U) +#define RCC_MCO_SRC_RC150K (0x08U) +#define RCC_MCO_SRC_RC10K (0x09U) + +#define IS_RCC_MCO_SRC(INSTANCE) (((INSTANCE) == RCC_MCO_SRC_NONE) || \ + ((INSTANCE) == RCC_MCO_SRC_HCLK) || \ + ((INSTANCE) == RCC_MCO_SRC_PCLK) || \ + ((INSTANCE) == RCC_MCO_SRC_HSI) || \ + ((INSTANCE) == RCC_MCO_SRC_LSI) || \ + ((INSTANCE) == RCC_MCO_SRC_HSE) || \ + ((INSTANCE) == RCC_MCO_SRC_LSE) || \ + ((INSTANCE) == RCC_MCO_SRC_PLL) || \ + ((INSTANCE) == RCC_MCO_SRC_RC150K) || \ + ((INSTANCE) == RCC_MCO_SRC_RC10K)) + +#define RCC_TIMITR_BTIM1 (0UL) +#define RCC_TIMITR_BTIM2 (1UL) +#define RCC_TIMITR_BTIM3 (2UL) +#define RCC_TIMITR_GTIM1 (3UL) +#define RCC_TIMITR_GTIM2 (4UL) +#define RCC_TIMITR_GTIM3 (5UL) +#define RCC_TIMITR_GTIM4 (6UL) +#define RCC_TIMITR_ATIM (7UL) + +#define IS_RCC_TIMITR_SOURCE(SRC) ((SRC) < 8) + +//================================================================================== +extern void RCC_HCLKPRS_Config(uint32_t HCLKPRS); +extern void RCC_PCLKPRS_Config(uint32_t PCLKPRS); +extern void RCC_SYSCLKSRC_Config(uint32_t SYSCLKSRC); +extern void RCC_CCS_Config(uint32_t CCS,FunctionalState NewState); +extern void RCC_LSELOCK_Config(uint32_t LSELOCK); +extern void RCC_WAKEUPCLK_Config(uint32_t WAKEUPCLK); +extern void RCC_LOCKUP_Config(uint32_t LOCKUP); +extern void RCC_SWDIO_Config(uint32_t SWDIO); +extern void RCC_DeInit(void); +extern void RCC_SystemCoreClockUpdate(uint32_t NewFreq); +extern void RCC_HSI_Enable(uint32_t HSIDiv ); +extern void RCC_HSI_Disable(void); +extern void RCC_LSI_Enable(void); +extern void RCC_LSI_Disable(void); +extern void RCC_HSE_Enable(uint32_t Mode, uint32_t FreqIn, uint8_t Driver,uint32_t Flt); +extern void RCC_HSE_Disable(void); +extern void RCC_LSE_Enable(uint32_t Mode,uint8_t Amp,uint8_t Driver); +extern void RCC_LSE_Disable(void); +extern void RCC_PLL_Enable(uint32_t PLLSource, uint32_t FreqIn, uint32_t PLLMul); +extern void RCC_PLL_Disable(void); +extern uint8_t RCC_SysClk_Switch(uint32_t NewClk); +extern void RCC_ITConfig(uint32_t RCC_IT, FunctionalState NewState); +extern ITStatus RCC_GetITStatus(uint32_t RCC_IT); +extern void RCC_ClearITPendingBit(uint32_t RCC_IT); +extern FlagStatus RCC_GetStableFlag(uint32_t RCC_STABLEFLAG); +extern uint32_t RCC_GetAllStableFlag( void ); +extern void RCC_AHBPeriphClk_Enable(uint32_t Periph,FunctionalState NewState); +extern void RCC_APBPeriphClk_Enable1(uint32_t Periph,FunctionalState NewState); +extern void RCC_APBPeriphClk_Enable2(uint32_t Periph,FunctionalState NewState); +extern void RCC_AHBPeriphReset(uint32_t Periph,FunctionalState NewState); +extern void RCC_APBPeriphReset1(uint32_t Periph,FunctionalState NewState); +extern void RCC_APBPeriphReset2(uint32_t Periph,FunctionalState NewState); +extern FlagStatus RCC_GetRstFlag(uint32_t RCC_RSTFLAG); +extern uint32_t RCC_GetAllRstFlag( void ); +extern void RCC_ClearRstFlag(uint32_t RCC_RSTFLAG); +extern void RCC_HCLK_OUT(void); +extern void RCC_PCLK_OUT(void); +extern void RCC_HSE_OUT(void); +extern void RCC_HSI_OUT(void); +extern void RCC_LSE_OUT(void); +extern void RCC_LSI_OUT(void); +extern void RCC_PLL_OUT(void); +extern void RCC_MCO_OUT(uint8_t Source, uint8_t Div); + +extern uint32_t RCC_Sysctrl_GetHClkFreq(void); +extern uint32_t RCC_Sysctrl_GetPClkFreq(void); + +void RCC_BTIM3ITRSelect(uint32_t Source); +void RCC_BTIM2ITRSelect(uint32_t Source); +void RCC_BTIM1ITRSelect(uint32_t Source); +void RCC_GTIM1ITRSelect(uint32_t Source); +void RCC_GTIM2ITRSelect(uint32_t Source); +void RCC_GTIM3ITRSelect(uint32_t Source); +void RCC_GTIM4ITRSelect(uint32_t Source); +void RCC_ATIMITRSelect(uint32_t Source); + +#ifdef __cplusplus +} +#endif + +#endif /* __CW32F030_RCC_H */ diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_rtc.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_rtc.h new file mode 100644 index 0000000..17d0669 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_rtc.h @@ -0,0 +1,584 @@ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_RTC_H +#define __CW32F030_RTC_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" + + +typedef struct +{ + uint8_t Day; + uint8_t Month; + uint8_t Year; + uint8_t Week; +} RTC_DateTypeDef; + +typedef struct +{ + uint8_t Second; + uint8_t Minute; + uint8_t Hour; + uint8_t AMPM; + uint8_t H24; //RTC_HOUR24(1),RTC_HOUR12(0) +} RTC_TimeTypeDef; + +typedef struct +{ + uint32_t RTC_ClockSource; + RTC_TimeTypeDef TimeStruct; + RTC_DateTypeDef DateStruct; + +} RTC_InitTypeDef; + + +typedef struct +{ + RTC_TimeTypeDef RTC_AlarmTime; + uint32_t RTC_AlarmMask; /*!< @ref RTC_AlarmMask_Definitions */ +}RTC_AlarmTypeDef; + +typedef struct +{ + uint8_t AWT_ClockSource; + uint16_t AWT_ARRValue; +} RTC_AWTTypeDef; + +typedef struct +{ + uint32_t Freq; + uint32_t Sign; + uint32_t Step; + uint32_t CompensationValue; +}RTC_CalibTypeDef; + + + + +#define RTC_Alarm_A ((uint32_t)0x00000200) +#define RTC_Alarm_B ((uint32_t)0x00000400) +#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) +#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) + + /** @defgroup RTC_ACCESS_TIMEOUT + * @{ + * RTCĴRTC_CR1->WINDOWλδ⵽1жRTCĴʧ + */ + +#define RTC_ACCESS_MAXTIMES ((uint32_t)200U) + + + /** @defgroup RTC_RTC1HZ_source + * @{ + */ + +#define RTC_RTC1HZ_NONE (0UL) +#define RTC_RTC1HZ_FROM_LSE (1UL << 5) +#define RTC_RTC1HZ_FROM_PCLK (3UL << 5) + +#define IS_RTC_RTC1HZ_SOURCE(src) (((src) == RTC_RTC1HZ_NONE) || \ + ((src) == RTC_RTC1HZ_FROM_PCLK) || \ + ((src) == RTC_RTC1HZ_FROM_LSE)) + + +#define RTC_HOUR24 (1UL << 3) +#define RTC_HOUR12 (0UL) +#define IS_RTC_HOUR_FORMAT(fmt) (((fmt) == RTC_HOUR24) || ((fmt) == RTC_HOUR12)) +#define IS_RTC_HOUR12_FORMAT(fmt) ((fmt) == RTC_HOUR12) + + + /** @defgroup RTC_Interval_Value + * @{ + */ + +#define RTC_INTERVAL_NONE (0X00) +#define RTC_INTERVAL_EVERY_0_5S (0x01) +#define RTC_INTERVAL_EVERY_1S (0x02) +#define RTC_INTERVAL_EVERY_1M (0x03) +#define RTC_INTERVAL_EVERY_1H (0x04) +#define RTC_INTERVAL_EVERY_1D (0x05) +#define RTC_INTERVAL_EVERY_1MO (0x06) + +#define IS_RTC_INTERVAL_PERIOD(per) (per < 7) + + /** @defgroup RTC_Clock_source + * 000ⲿʱLSE + * 010õƵʱLSI + * 100ⲿʱHSE / 128 + * 101ⲿʱHSE / 256 + * 110ⲿʱHSE / 512 + * 111ⲿʱHSE / 1024 + * @{ + */ + +#define RTC_RTCCLK_FROM_LSE (0UL) +#define RTC_RTCCLK_FROM_LSI (2UL << 8) +#define RTC_RTCCLK_FROM_HSE_128 (4UL << 8) +#define RTC_RTCCLK_FROM_HSE_256 (5UL << 8) +#define RTC_RTCCLK_FROM_HSE_512 (6UL << 8) +#define RTC_RTCCLK_FROM_HSE_1024 (7UL << 8) + +#define IS_RTC_RTCCLK_SOURCE(src) (((src) == RTC_RTCCLK_FROM_LSE) || \ + ((src) == RTC_RTCCLK_FROM_LSI) || \ + ((src) == RTC_RTCCLK_FROM_HSE_128) || \ + ((src) == RTC_RTCCLK_FROM_HSE_256) || \ + ((src) == RTC_RTCCLK_FROM_HSE_512) || \ + ((src) == RTC_RTCCLK_FROM_HSE_1024)) + +#define RTC_IT_INTERVAL (1UL << 6) +#define RTC_IT_TAMPOV (1UL << 4) +#define RTC_IT_TAMP (1UL << 3) +#define RTC_IT_AWTIMER (1UL << 2) +#define RTC_IT_ALARMB (1UL << 1) +#define RTC_IT_ALARMA (1UL) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_INTERVAL) || \ + ((IT) == RTC_IT_TAMPOV) || \ + ((IT) == RTC_IT_TAMP) || \ + ((IT) == RTC_IT_AWTIMER) || \ + ((IT) == RTC_IT_ALARMB) || \ + ((IT) == RTC_IT_ALARMA)) +#define IS_RTC_CONFIG_IT(IT) ((((uint8_t)(IT) & 0x20) == 0) && \ + ((uint8_t)(IT) < 0x40)) +#define IS_RTC_CLAER_IT(IT) ((((uint8_t)(IT) & 0x20) == 0) && \ + ((uint8_t)(IT) < 0x40)) + +/** @defgroup RTC_AlarmMask_Definitions + * @{ + */ +#define RTC_AlarmMask_None ((uint32_t)0x00000000) +#define RTC_AlarmMask_WeekSAT ((uint32_t)0x40000000) +#define RTC_AlarmMask_WeekFRI ((uint32_t)0x20000000) +#define RTC_AlarmMask_WeekTHU ((uint32_t)0x10000000) +#define RTC_AlarmMask_WeekWED ((uint32_t)0x08000000) +#define RTC_AlarmMask_WeekTUE ((uint32_t)0x04000000) +#define RTC_AlarmMask_WeekMON ((uint32_t)0x02000000) +#define RTC_AlarmMask_WeekSun ((uint32_t)0x01000000) +#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) +#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) +#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) +#define RTC_AlarmMask_All ((uint32_t)0x7F808080) +#define IS_ALARM_MASK(MASK) (((MASK) & 0x807F7F7F) == (uint32_t)RESET) + + +#define RTC_TamperTrigger_RisingEdge (0UL) +#define RTC_TamperTrigger_FallingEdge (1UL) +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_FallingEdge)) + + +/** @defgroup RTC_Compen_step + * @{ + */ +#define RTC_RTCOUT_AS_LOW (0x0) +#define RTC_RTCOUT_AS_ALARM_A (0x1) +#define RTC_RTCOUT_AS_ALARM_B (0x2) +#define RTC_RTCOUT_AS_AWT (0x3) + +#define IS_RTC_RTCOUT_SOURCE(src) (src < 4) + /* +#define IS_RTC_RTCOUT_SOURCE(src) (((src) == RTC_RTCOUT_AS_LOW) || \ + ((src) == RTC_RTCOUT_AS_ALARM_A) || \ + ((src) == RTC_RTCOUT_AS_ALARM_B) || \ + ((src) == RTC_RTCOUT_AS_AWT)) ) +*/ + + /** @defgroup RTC_TimerSrc_Value + * @{ + */ + +#define RTC_AWTSOURCE_FROM_RTCCLK_2 (0x0) +#define RTC_AWTSOURCE_FROM_RTCCLK_4 (0x1) +#define RTC_AWTSOURCE_FROM_RTCCLK_8 (0x2) +#define RTC_AWTSOURCE_FROM_RTCCLK_16 (0x3) +#define RTC_AWTSOURCE_FROM_RTC1HZ_1 (0x4) +#define RTC_AWTSOURCE_FROM_RTC1HZ_2 (0x5) +#define RTC_AWTSOURCE_FROM_RTC1HZ_4 (0x6) +#define RTC_AWTSOURCE_FROM_RTC1HZ_8 (0x7) + +#define IS_RTC_AWTTIMER_SOURCE(clk) (clk < 8) +/* +#define IS_RTC_AWTTIMER_SOURCE(clk) (((clk) == RTC_AWTSOURCE_FROM_RTCCLK_2) || \ + ((clk) == RTC_AWTSOURCE_FROM_RTCCLK_4) || \ + ((clk) == RTC_AWTSOURCE_FROM_RTCCLK_8) || \ + ((clk) == RTC_AWTSOURCE_FROM_RTCCLK_16) || \ + ((clk) == RTC_AWTSOURCE_FROM_RTC1HZ_1) || \ + ((clk) == RTC_AWTSOURCE_FROM_RTC1HZ_2) || \ + ((clk) == RTC_AWTSOURCE_FROM_RTC1HZ_4) || \ + ((clk) == RTC_AWTSOURCE_FROM_RTC1HZ_8)) +*/ + +/** + * @} + */ + +/** @defgroup RTC_Compen_Freq + * @{ + */ +#define RTC_COMPENFREQ_AS_4MHZ (0x0UL) +#define RTC_COMPENFREQ_AS_6MHZ (0x1UL) +#define RTC_COMPENFREQ_AS_8MHZ (0x2UL) +#define RTC_COMPENFREQ_AS_12MHZ (0x3UL) +#define RTC_COMPENFREQ_AS_16MHZ (0x4UL) +#define RTC_COMPENFREQ_AS_20MHZ (0x5UL) +#define RTC_COMPENFREQ_AS_24MHZ (0x6UL) +#define RTC_COMPENFREQ_AS_30MHZ (0x7UL) +#define RTC_COMPENFREQ_AS_48MHZ (0x8UL) + +#define IS_RTC_COMPEN_FREQ(clk) (clk < 9) +/* +#define IS_RTC_COMPEN_FREQ(clk) (((clk) == RTC_COMPENFREQ_AS_4MHZ) || \ + ((clk) == RTC_COMPENFREQ_AS_6MHZ) || \ + ((clk) == RTC_COMPENFREQ_AS_8MHZ) || \ + ((clk) == RTC_COMPENFREQ_AS_12MHZ) || \ + ((clk) == RTC_COMPENFREQ_AS_16MHZ) || \ + ((clk) == RTC_COMPENFREQ_AS_20MHZ) || \ + ((clk) == RTC_COMPENFREQ_AS_24MHZ) || \ + ((clk) == RTC_COMPENFREQ_AS_30MHZ) || \ + ((clk) == RTC_COMPENFREQ_AS_48MHZ)) +*/ + +/** + * @} + */ + +/** @defgroup RTC_Compen_step + * @{ + */ +#define RTC_COMPENSTEP_0_950PPM (0x0UL) +#define RTC_COMPENSTEP_0_238PPM (0x1UL) +#define RTC_COMPENSTEP_0_119PPM (0x2UL) + +#define IS_RTC_COMPEN_STEP(stp) ((stp) < 3) +/* +#define IS_RTC_COMPEN_STEP(stp) (((stp) == RTC_COMPENSTEP_0_950PPM) || \ + ((stp) == RTC_COMPENSTEP_0_238PPM) || \ + ((stp) == RTC_COMPENSTEP_0_119PPM)) ) +*/ + +/** + * @} + */ + + #define RTC_COMPEN_SIGN_UP (0UL) + #define RTC_COMPEN_SIGN_DOWN (1UL) + #define IS_RTC_COMPEN_SIGN(SIGN) ((SIGN) < 2) + + #define IS_RTC_COMPEN_VALUE(VAL) ((VAL) & 0xFFFFF000 == RESET) + +/** @defgroup RTC_Month_Day_Definitions + * @{ + */ +#define RTC_Month_January ((uint8_t)0x01) +#define RTC_Month_February ((uint8_t)0x02) +#define RTC_Month_March ((uint8_t)0x03) +#define RTC_Month_April ((uint8_t)0x04) +#define RTC_Month_May ((uint8_t)0x05) +#define RTC_Month_June ((uint8_t)0x06) +#define RTC_Month_July ((uint8_t)0x07) +#define RTC_Month_August ((uint8_t)0x08) +#define RTC_Month_September ((uint8_t)0x09) +#define RTC_Month_October ((uint8_t)0x10) +#define RTC_Month_November ((uint8_t)0x11) +#define RTC_Month_December ((uint8_t)0x12) +#define IS_RTC_MONTH(MON) (((MON) >= 1) && ((MON) <= 12)) +#define IS_RTC_DAY(DAY) (((DAY) >= 1) && ((DAY) <= 31)) + + /** + * @} + */ + + /** @defgroup RTC_WeekDay_Definitions + * @{ + */ + +#define RTC_Weekday_Sunday ((uint8_t)0x00) +#define RTC_Weekday_Monday ((uint8_t)0x01) +#define RTC_Weekday_Tuesday ((uint8_t)0x02) +#define RTC_Weekday_Wednesday ((uint8_t)0x03) +#define RTC_Weekday_Thursday ((uint8_t)0x04) +#define RTC_Weekday_Friday ((uint8_t)0x05) +#define RTC_Weekday_Saturday ((uint8_t)0x06) + +#define IS_RTC_WEEKDAY(wek) (wek < 7) + +/* +#define IS_RTC_WEEKDAY(wek) (((wek) == RTC_Weekday_Monday) || \ + ((wek) == RTC_Weekday_Tuesday) || \ + ((wek) == RTC_Weekday_Wednesday) || \ + ((wek) == RTC_Weekday_Thursday) || \ + ((wek) == RTC_Weekday_Friday) || \ + ((wek) == RTC_Weekday_Saturday) || \ + ((wek) == RTC_Weekday_Sunday)) +*/ + +/** + * @} + */ + +/** @defgroup RTC_Alarm_Definitions + * @{ + */ +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(dat) (((dat) > 0) && ((dat) <= 31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(wek) (((wek) == RTC_Weekday_Monday) || \ + ((wek) == RTC_Weekday_Tuesday) || \ + ((wek) == RTC_Weekday_Wednesday) || \ + ((wek) == RTC_Weekday_Thursday) || \ + ((wek) == RTC_Weekday_Friday) || \ + ((wek) == RTC_Weekday_Saturday) || \ + ((wek) == RTC_Weekday_Sunday)) + +/** + * @} + */ + + + +/** @defgroup RTC_Time_Definitions + * @{ + */ +#define IS_RTC_HOUR12(hor) (((hor) >= 1) && ((hor) <= 12)) +#define IS_RTC_HOUR24(hor) ((hor) <= 23) +#define IS_RTC_MINUTES(min) ((min) <= 59) +#define IS_RTC_SECONDS(sec) ((sec) <= 59) + +/** + * @} + */ + +/** @defgroup RTC_AM_PM_Definitions + * @{ + */ +#define RTC_H12_AM (0UL) +#define RTC_H12_PM (1UL) +#define IS_RTC_H12_AMPM(apm) (((apm) == RTC_H12_AM) || ((apm) == RTC_H12_PM)) + +/** + * @} + */ + +/** @defgroup RTC_Year_Date_Definitions + * @{ + */ +#define IS_RTC_YEAR(yer) ((yer) <= 99) + +/** + * @} + */ + +/** @defgroup RTC_KEY_WORD + * @{ + */ +#define RTC_KEY_WORD1 ((uint8_t)0xCA) +#define RTC_KEY_WORD2 ((uint8_t)0x53) + +#define RTC_KEY_LOCKW ((uint8_t)0x55) + +#define IS_RTC_KEYWORD(kwd) (((kwd) == RTC_KEY_WORD1) || ((kwd) == RTC_KEY_WORD2)) + +#define RTC_UNLOCK() do{ CW_RTC->KEY_f.KEY = RTC_KEY_WORD1;\ + CW_RTC->KEY_f.KEY = RTC_KEY_WORD2; }while (0) +#define RTC_LOCK() do{ CW_RTC->KEY_f.KEY = RTC_KEY_WORD1; \ + CW_RTC->KEY_f.KEY = RTC_KEY_WORD1;}while (0) + + +/** + * @} + */ +#define RTC_DATE_RESET_VALUE ((uint32_t) 0x00000000) +#define RTC_TIME_RESET_VALUE ((uint32_t) 0x12000000) +#define RTC_ALARMA_RESET_VALUE ((uint32_t) 0x12000000) +#define RTC_ALARMB_RESET_VALUE ((uint32_t) 0x12000000) +#define RTC_TAMPDATA_RESET_VALUE ((uint32_t) 0x00000000) +#define RTC_TAMPTIME_RESET_VALUE ((uint32_t) 0x00000000) +#define RTC_AWTARR_RESET_VALUE ((uint32_t) 0x0000FFFF) +#define RTC_IER_RESET_VALUE ((uint32_t) 0x00000000) + + +//============================================================ + +//RTC CONTROLLER REGSITER0 +#define RTC_START_ENABLE() (CW_RTC->CR0_f.START = 1) +#define RTC_START_DISABLE() (CW_RTC->CR0_f.START = 0) + +#define RTC_RTC1HZ_PCLK() (CW_RTC->CR0_f.RTC1HZ = RTC_RTC1HZ_FROM_PCLK) +#define RTC_RTC1HZ_LSE() (CW_RTC->CR0_f.RTC1HZ = RTC_RTC1HZ_FROM_LSE) + +#define RTC_AMPM_12HOUR() (CW_RTC->CR0_f.AMPM = 0) +#define RTC_AMPM_24HOUR() (CW_RTC->CR0_f.AMPM = 1) + +#define RTC_INTERVAL_0_5S() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_0_5S) +#define RTC_INTERVAL_1S() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_1S) +#define RTC_INTERVAL_1M() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_1M) +#define RTC_INTERVAL_1H() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_1H) +#define RTC_INTERVAL_1D() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_1D) +#define RTC_INTERVAL_1MO() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_1MO) + +#define IS_RTC_START() (CW_RTC->CR0 & bv7) + +//============================================================ +//RTC CONTROLLER REGSITER1 +#define RTC_RTCCLK_LSE() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_LSE) +#define RTC_RTCCLK_LSI() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_LIE) +#define RTC_RTCCLK_HSE128() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_HSE_128) +#define RTC_RTCCLK_HSE256() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_HSE_256) +#define RTC_RTCCLK_HSE512() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_HSE_512) +#define RTC_RTCCLK_HSE1024() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_HSE_1024) + +#define RTC_WINDOW_GETVALUE() (CW_RTC->CR1_f.WINDOW) +#define RTC_ACCESS_GETVALUE() (CW_RTC->CR1_f.ACCESS) +#define RTC_ACCESS_SET() (CW_RTC->CR1_f.ACCESS = 1) +#define RTC_ACCESS_RESET() (CW_RTC->CR1_f.ACCESS = 0) + +//============================================================ +//RTC CONTROLLER REGSITER2 +#define RTC_ALARM_A_ENABLE() (CW_RTC->CR2_f.ALARMAEN = 1) +#define RTC_ALARM_A_DISABLE() (CW_RTC->CR2_f.ALARMAEN = 0) + +#define RTC_ALARM_B_ENABLE() (CW_RTC->CR2_f.ALARMBEN = 1) +#define RTC_ALARM_B_DISABLE() (CW_RTC->CR2_f.ALARMBEN = 0) + +#define RTC_AWT_ENABLE() (CW_RTC->CR2_f.AWTEN = 1) +#define RTC_AWT_DISABLE() (CW_RTC->CR2_f.AWTEN = 0) + +#define RTC_TAMP_ENABLE() (CW_RTC->CR2_f.TAMPEN = 1) +#define RTC_TAMP_DISABLE() (CW_RTC->CR2_f.TAMPEN = 0) + +#define RTC_RTCOUT_LOW() (CW_RTC->CR2_f.RTCOUT = RTC_RTCOUT_AS_LOW) +#define RTC_RTCOUT_ALARM_A() (CW_RTC->CR2_f.RTCOUT = RTC_RTCOUT_AS_ALARM_A) +#define RTC_RTCOUT_ALARM_B() (CW_RTC->CR2_f.RTCOUT = RTC_RTCOUT_AS_ALARM_B) +#define RTC_RTCOUT_AWT() (CW_RTC->CR2_f.RTCOUT = RTC_RTCOUT_AS_AWT) + +#define RTC_TAMPEDGE_FALL() (CW_RTC->CR2_f.TAMPEDGE = 1) +#define RTC_TAMPEDGE_RISE() (CW_RTC->CR2_f.TAMPEDGE = 0) + +#define RTC_AWTSOURCE_RTCLK_2() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTCCLK_2) +#define RTC_AWTSOURCE_RTCLK_4() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTCCLK_4) +#define RTC_AWTSOURCE_RTCLK_8() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTCCLK_8) +#define RTC_AWTSOURCE_RTCLK_16() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTCCLK_16) +#define RTC_AWTSOURCE_RTC1HZ_1() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTC1HZ_1) +#define RTC_AWTSOURCE_RTC1HZ_2() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTC1HZ_2) +#define RTC_AWTSOURCE_RTC1HZ_4() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTC1HZ_4) +#define RTC_AWTSOURCE_RTC1HZ_8() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTC1HZ_8) + +//============================================================ +//RTC COMPEN REGSITER +#define RTC_COMPEN_ENABLE() (CW_RTC->COMPEN_f.EN = 1) +#define RTC_COMPEN_DISABLE() (CW_RTC->COMPEN_f.EN = 0) + +#define RTC_COMPEN_STEP_0_950PPM() (CW_RTC->COMPEN_f.STEP = RTC_COMPENSTEP_0_950PPM) +#define RTC_COMPEN_STEP_0_238PPM() (CW_RTC->COMPEN_f.STEP = RTC_COMPENSTEP_0_238PPM) +#define RTC_COMPEN_STEP_0_119PPM() (CW_RTC->COMPEN_f.STEP = RTC_COMPENSTEP_0_119PPM) + +//============================================================ +//RTC ALARM A CONTROLLER REGSITER +#define RTC_ALARMA_HOURMASK_ENABLE() (CW_RTC->ALARMA_f.HOURMASK = 1) +#define RTC_ALARMA_HOURMASK_DISABLE() (CW_RTC->ALARMA_f.HOURMASK = 0) + +#define RTC_ALARMA_MINUTEMASK_ENABLE() (CW_RTC->ALARMA_f.MINUTEMASK = 1) +#define RTC_ALARMA_MINUTEMASK_DISABLE() (CW_RTC->ALARMA_f.MINUTEMASK = 0) + +#define RTC_ALARMA_SECONDMASK_ENABLE() (CW_RTC->ALARMA_f.SECONDMASK = 1) +#define RTC_ALARMA_SECONDMASK_DISABLE() (CW_RTC->ALARMA_f.SECONDMASK = 0) + +//============================================================ +//RTC ALARM B CONTROLLER REGSITER +#define RTC_ALARMB_HOURMASK_ENABLE() (CW_RTC->ALARMB_f.HOURMASK = 1) +#define RTC_ALARMB_HOURMASK_DISABLE() (CW_RTC->ALARMB_f.HOURMASK = 0) + +#define RTC_ALARMB_MINUTEMASK_ENABLE() (CW_RTC->ALARMB_f.MINUTEMASK = 1) +#define RTC_ALARMB_MINUTEMASK_DISABLE() (CW_RTC->ALARMB_f.MINUTEMASK = 0) + +#define RTC_ALARMB_SECONDMASK_ENABLE() (CW_RTC->ALARMB_f.SECONDMASK = 1) +#define RTC_ALARMB_SECONDMASK_DISABLE() (CW_RTC->ALARMB_f.SECONDMASK = 0) + +//============================================================ +//RTC INTERRUPT ENABLE REGSITER +#define RTC_IE_INTERVAL_ENABLE() (CW_RTC->IER_f.INTERVAL = 1) +#define RTC_IE_INTERVAL_DISABLE() (CW_RTC->IER_f.INTERVAL = 0) + +#define RTC_IE_TAMPOV_ENABLE() (CW_RTC->IER_f.TAMPOV = 1) +#define RTC_IE_TAMPOV_DISABLE() (CW_RTC->IER_f.TAMPOV = 0) + +#define RTC_IE_TAMP_ENABLE() (CW_RTC->IER_f.TAMP = 1) +#define RTC_IE_TAMP_DISABLE() (CW_RTC->IER_f.TAMP = 0) + +#define RTC_IE_AWTIMER_ENABLE() (CW_RTC->IER_f.AWTIMER = 1) +#define RTC_IE_AWTIMER_DISABLE() (CW_RTC->IER_f.AWTIMER = 0) + +#define RTC_IE_ALARMA_ENABLE() (CW_RTC->IER_f.ALARMA = 1) +#define RTC_IE_ALARMA_DISABLE() (CW_RTC->IER_f.ALARMA = 0) + +#define RTC_IE_ALARMB_ENABLE() (CW_RTC->IER_f.ALARMB = 1) +#define RTC_IE_ALARMB_DISABLE() (CW_RTC->IER_f.ALARMB = 0) + +//============================================================ +//RTC INTERRUPT CLEAR REGSITER +#define RTC_IE_INTERVAL_CLEAR() (CW_RTC->ICR_f.INTERVAL = 0) +#define RTC_IE_TAMPOV_CLEAR() (CW_RTC->ICR_f.TAMPOV = 0) +#define RTC_IE_TAMP_CLEAR() (CW_RTC->ICR_f.TAMP = 0) +#define RTC_IE_AWTIMER_CLEAR() (CW_RTC->ICR_f.AWTIMER = 0) +#define RTC_IE_ALARMA_CLEAR() (CW_RTC->ICR_f.ALARMA = 0) +#define RTC_IE_ALARMB_CLEAR() (CW_RTC->ICR_f.ALARMB = 0) + + + +//============================================================ +// CW32F030 RTC HAL API FunctionTotal 14λĺ +//============================================================ +void RTC_DeInit(void); +ErrorStatus RTC_Init(RTC_InitTypeDef *RTC_InitStruct); +void RTC_Cmd(FunctionalState NewState); +ITStatus RTC_GetITState(uint32_t RTC_ITState); +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); +void RTC_ClearITPendingBit(uint32_t RTC_IT); +void RTC_SetTime(RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_SetDate(RTC_DateTypeDef *RTC_Date); +void RTC_GetTime(RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_GetDate(RTC_DateTypeDef *RTC_Date); +void RTC_SetAlarm(uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_GetAlarm(uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); +void RTC_TamperTriggerConfig(uint32_t RTC_TamperTrigger); +void RTC_TamperCmd(FunctionalState NewState); +void RTC_GetTamperDate(RTC_DateTypeDef *RTC_Date); +void RTC_GetTamperTime(RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_OutputConfig(uint8_t RTC_Output); +void RTC_AWTConfig(RTC_AWTTypeDef *RCT_AWTStruct); +void RTC_AWTCmd(FunctionalState NewState); +void RTC_SetInterval(uint8_t Period); +void RTC_SetClockSource(uint32_t RTC_ClockSource); +void RTC_CalibrationConfig(RTC_CalibTypeDef *RTC_CalibStruct); +void RTC_CalibrationCmd(FunctionalState NewState); +uint8_t RTC_BinToBCD(uint8_t Value); +uint8_t RTC_BCDToBin(uint8_t Value); + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32F030_RTC_H */ +/** + * @} + */ diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_spi.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_spi.h new file mode 100644 index 0000000..eb80a20 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_spi.h @@ -0,0 +1,306 @@ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_SPI_H +#define __CW32F030_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" + +/****************************************************************************** + * type definitions ('typedef') + ******************************************************************************/ +typedef struct +{ + uint16_t SPI_Direction; /*!< ͨģʽȫ˫գ߰˫ + ȡֵ @ref SPI_Data_Direction */ + + uint16_t SPI_Mode; /*!< SPIģʽ + ȡֵ @ref SPI_Mode */ + + uint16_t SPI_DataSize; /*!< ֡ݿ + ȡֵ @ref SPI_Data_Size */ + + uint16_t SPI_CPOL; /*!< ʱӴ + ȡֵ @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /*!< ʱλ + ȡֵ @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /*!< CSܽ + ȡֵ @ref SPI_Slave_Select_Management */ + + uint16_t SPI_BaudRatePrescaler; /*!< ģʽSCK + ȡֵ @ref SPI_BaudRate_Prescaler */ + + uint16_t SPI_FirstBit; /*!< ֡ߵλ˳ѡ + ȡֵ @ref SPI_MSB_LSB_Transmission */ + + uint16_t SPI_Speed; /*!< SPIIJǷӺ󣬸Ӻ²Ӻ + ȡֵ @ref SPI_Speed */ +} SPI_InitTypeDef; + +/****************************************************************************** + * pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** @defgroup SPI_Data_Direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) //˫ȫ˫ +#define SPI_Direction_1Line_TxOnly ((uint16_t)0x4000) // +#define SPI_Direction_1Line_RxOnly ((uint16_t)0x8000) // +#define SPI_Direction_1Lines_HalfDuplex ((uint16_t)0xC000) //߰˫ +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_1Lines_HalfDuplex) || \ + ((MODE) == SPI_Direction_1Line_TxOnly) || \ + ((MODE) == SPI_Direction_1Line_RxOnly)) + +/** @defgroup SPI_Mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0004) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) + +/** @defgroup SPI_Data_Size + * @{ + */ + +#define SPI_DataSize_4b ((uint16_t)0x0C00) +#define SPI_DataSize_5b ((uint16_t)0x1000) +#define SPI_DataSize_6b ((uint16_t)0x1400) +#define SPI_DataSize_7b ((uint16_t)0x1800) +#define SPI_DataSize_8b ((uint16_t)0x1C00) +#define SPI_DataSize_9b ((uint16_t)0x2000) +#define SPI_DataSize_10b ((uint16_t)0x2400) +#define SPI_DataSize_11b ((uint16_t)0x2800) +#define SPI_DataSize_12b ((uint16_t)0x2C00) +#define SPI_DataSize_13b ((uint16_t)0x3000) +#define SPI_DataSize_14b ((uint16_t)0x3400) +#define SPI_DataSize_15b ((uint16_t)0x3800) +#define SPI_DataSize_16b ((uint16_t)0x3C00) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_4b) || \ + ((DATASIZE) == SPI_DataSize_5b) || \ + ((DATASIZE) == SPI_DataSize_6b) || \ + ((DATASIZE) == SPI_DataSize_7b) || \ + ((DATASIZE) == SPI_DataSize_8b) || \ + ((DATASIZE) == SPI_DataSize_9b) || \ + ((DATASIZE) == SPI_DataSize_10b) || \ + ((DATASIZE) == SPI_DataSize_11b) || \ + ((DATASIZE) == SPI_DataSize_12b) || \ + ((DATASIZE) == SPI_DataSize_13b) || \ + ((DATASIZE) == SPI_DataSize_14b) || \ + ((DATASIZE) == SPI_DataSize_15b) ||\ + ((DATASIZE) == SPI_DataSize_16b)) + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) + +/** @defgroup SPI_Slave_Select_Management + * @{ + */ + +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) + +/** @defgroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128)) + +/** @defgroup SPI_MSB_LSB_Transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) + +/** @defgroup SPI_Speed + * @{ + */ + +#define SPI_Speed_Low ((uint16_t)0x0000) +#define SPI_Speed_High ((uint16_t)0x0100) +#define IS_SPI_SPEED(SPEED) (((SPEED) == SPI_Speed_Low) || \ + ((SPEED) == SPI_Speed_High)) + +/** @defgroup SPI_Direction_Transmit_Receive + * @{ + */ + +#define SPI_Direction_Tx ((uint8_t)0x01) +#define SPI_Direction_Rx ((uint8_t)0x00) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Tx) || \ + ((DIRECTION) == SPI_Direction_Rx)) + +/** @defgroup SPI_DMA_Requests + * @{ + */ + +#define SPI_DMAReq_Tx ((uint32_t)0x00020000) +#define SPI_DMAReq_Rx ((uint32_t)0x00010000) +#define IS_SPI_DMAREQ(DMAREQ) (((DMAREQ) == SPI_DMAReq_Tx) || \ + ((DMAREQ) == SPI_DMAReq_Rx) || \ + ((DMAREQ) == (SPI_DMAReq_Tx | SPI_DMAReq_Rx))) + +/** @defgroup SPI_NSS_Internal_Software_Management + * @{ + */ + +#define SPI_NSSInternalSoft_Set ((uint8_t)0x01) +#define SPI_NSSInternalSoft_Reset ((uint8_t)0x00) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) + +/** @defgroup SPI_MISO_Output_config + * @{ + */ + +#define SPI_MISOOutput_HD ((uint8_t)0x01) +#define SPI_MISOOutput_CMOS ((uint8_t)0x00) +#define IS_SPI_MISOOUTPUT(MISOOUTPUT) (((MISOOUTPUT) == SPI_MISOOutput_HD) || \ + ((MISOOUTPUT) == SPI_MISOOutput_CMOS)) + +/** @defgroup SPI_Interrupts + * @{ + */ + +#define SPI_IT_MODF ((uint8_t)0x80) +#define SPI_IT_SSERR ((uint8_t)0x40) +#define SPI_IT_OV ((uint8_t)0x20) +#define SPI_IT_UD ((uint8_t)0x10) +#define SPI_IT_SSR ((uint8_t)0x08) +#define SPI_IT_SSF ((uint8_t)0x04) +#define SPI_IT_RXNE ((uint8_t)0x02) +#define SPI_IT_TXE ((uint8_t)0x01) +#define IS_SPI_IT(IT) ((IT) <= 0xFF && ((IT) != (uint8_t)0x00)) +#define IS_SPI_CLEAR_IT(IT) ((((IT) & (uint8_t)0x01) == 0x00) && ((IT) != (uint8_t)0x00)) + +/** @defgroup SPI_Flags + * @{ + */ + +#define SPI_FLAG_SSLVL ((uint16_t)0x0200) +#define SPI_FLAG_BUSY ((uint16_t)0x0100) +#define SPI_FLAG_MODF ((uint16_t)0x0080) +#define SPI_FLAG_SSERR ((uint16_t)0x0040) +#define SPI_FLAG_OV ((uint16_t)0x0020) +#define SPI_FLAG_UD ((uint16_t)0x0010) +#define SPI_FLAG_SSR ((uint16_t)0x0008) +#define SPI_FLAG_SSF ((uint16_t)0x0004) +#define SPI_FLAG_RXNE ((uint16_t)0x0002) +#define SPI_FLAG_TXE ((uint16_t)0x0001) +#define IS_SPI_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC00) == 0x00) && ((FLAG) != (uint16_t)0x00)) +#define IS_SPI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFF01) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == CW_SPI1) || \ + ((PERIPH) == CW_SPI2)) + + /****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + + /****************************************************************************** + * Global function prototypes + ******************************************************************************/ + +/* շ */ +void SPI_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_ReceiveData(SPI_TypeDef* SPIx); + +/* ʼ */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void SPI1_DeInit(void); +void SPI2_DeInit(void); + +/* ʹֹܻSPIx */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); + +/* жϼ־ */ +void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG); +void SPI_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_FLAG); + +/* ߰˫ݴ䷽ */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint8_t SPI_Direction); + +/* DMA */ +void SPI_DMACmd(SPI_TypeDef* SPIx, uint32_t SPI_DMAReq, FunctionalState NewState); + +/* ڲNSS */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint8_t SPI_NSSInternalSoft); + +/* ֡λ */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); + +/* ģʽMISO*/ +void SPI_MISOOutputConfig(SPI_TypeDef* SPIx, uint8_t SPI_MISOOutput); + +/* շͻλĴ */ +void SPI_FlushSendBuff(SPI_TypeDef* SPIx); + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32F030_SPI_H */ + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_systick.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_systick.h new file mode 100644 index 0000000..11e4bc3 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_systick.h @@ -0,0 +1,77 @@ +/** + * @file cw32f030_systick.h + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-13 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_HAL_H +#define __CW32F030_HAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32f030.h" + +/* Exported types ------------------------------------------------------------*/ + +typedef enum +{ + TICK_FREQ_10HZ = 100U, + TICK_FREQ_100HZ = 10U, + TICK_FREQ_1KHZ = 1U, + TICK_FREQ_DEFAULT = TICK_FREQ_1KHZ +} TickFreqTypeDef; + +#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */ +#define MAX_SYSTICK_DELAY 0xFFFFFFFFU +#define IS_TICKFREQ(FREQ) (((FREQ) == TICK_FREQ_10HZ) || \ + ((FREQ) == TICK_FREQ_100HZ) || \ + ((FREQ) == TICK_FREQ_1KHZ)) + +/* Exported functions --------------------------------------------------------*/ +void InitTick(uint32_t HclkFreq); +void SysTickDelay(uint32_t Delay); +uint32_t GetTick(void); +void SuspendTick(void); +void ResumeTick(void); + +/* Exported variables ---------------------------------------------------------*/ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern TickFreqTypeDef uwTickFreq; + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CW32F030_HAL_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_uart.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_uart.h new file mode 100644 index 0000000..3718481 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_uart.h @@ -0,0 +1,291 @@ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_UART_H +#define __CW32F030_UART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" + +/****************************************************************************** + * type definitions ('typedef') + ******************************************************************************/ + + /** + * @brief USART Init Structure definition + */ + +typedef struct +{ + uint32_t USART_BaudRate; /*!< + 㹫ʽ: + - USART_Over = 00 BaudRate = UCLK / (16 * BRRI + BRRF) + - USART_Over = 01 BaudRate = UCLK / (8 * BRRI) + - USART_Over = 10 BaudRate = UCLK / (4 * BRRI) + - USART_Over = 11 BaudRate = (256 * UCLK) / BRRI */ + + uint16_t USART_Over; /*!< ʽ + ȡֵ @ref USART_Over */ + + uint16_t USART_Source; /*!< ʱԴUCLK + ȡֵ @ref USART_Source */ + + uint32_t USART_UclkFreq; /*!< ʱUCLKƵ Hz */ + + uint16_t USART_StartBit; /*!< ʼλжʽ + ȡֵ @ref USART_Start_Bit */ + + uint16_t USART_StopBits; /*!< ֹͣλ + ȡֵ @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /*!< У鷽ʽ + ȡֵ @ref USART_Parity + @note ΪУʱֳΪ8λ + ΪУʱֳԶΪ9λ */ + + uint16_t USART_Mode; /*!< /ʹ + ȡֵ @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /*!< Ӳ + ȡֵ @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + + uint16_t USART_Clock; /*!< USARTͬģʽʹ/ʧ + ȡֵ @ref USART_Clock */ + + uint16_t USART_Source; /*!< ʱԴUCLK + ȡֵ @ref USART_Source */ +} USART_ClockInitTypeDef; + +/****************************************************************************** + * pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** @defgroup USART_Over + * @{ + */ + +#define USART_Over_16 ((uint16_t)0x0000) +#define USART_Over_8 ((uint16_t)0x0200) +#define USART_Over_4 ((uint16_t)0x0400) +#define USART_Over_sp ((uint16_t)0x0600) +#define IS_USART_Over(Over) (((Over) == USART_Over_16) || \ + ((Over) == USART_Over_8) || \ + ((Over) == USART_Over_4) || \ + ((Over) == USART_Over_sp)) + +/** @defgroup USART_Source + * @{ + */ + +#define USART_Source_PCLK ((uint16_t)0x0000) +#define USART_Source_LSE ((uint16_t)0x0200) +#define USART_Source_LSI ((uint16_t)0x0300) +#define IS_USART_Source(Source) (((Source) == USART_Source_PCLK) || \ + ((Source) == USART_Source_LSE) || \ + ((Source) == USART_Source_LSI)) + +/** @defgroup USART_Start_Bit + * @{ + */ + +#define USART_StartBit_FE ((uint16_t)0x0000) //RXD½ +#define USART_StartBit_LL ((uint16_t)0x0100) //RXD͵ƽ +#define IS_USART_StartBit(StartBit) (((StartBit) == USART_StartBit_FE) || \ + ((StartBit) == USART_StartBit_LL)) + +/** @defgroup USART_Stop_Bits + * @{ + */ + +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_2 ((uint16_t)0x0020) +#define USART_StopBits_1_5 ((uint16_t)0x0010) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) + +/** @defgroup USART_Parity + * @{ + */ + +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0008) +#define USART_Parity_Odd ((uint16_t)0x000C) +#define USART_Parity_User ((uint16_t)0x0004) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd) || \ + ((PARITY) == USART_Parity_User)) + +/** @defgroup USART_Mode + * @{ + */ + +#define USART_Mode_Tx ((uint16_t)0x0001) +#define USART_Mode_Rx ((uint16_t)0x0002) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFFC) == 0x00) && ((MODE) != (uint16_t)0x00)) + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ + +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0008) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0004) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x000C) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) + +/** @defgroup USART_Clock + * @{ + */ + +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0040) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) + +/** @defgroup USART_EN + * @{ + */ + +#define USART_EN_Tx ((uint16_t)0x0001) +#define USART_EN_Rx ((uint16_t)0x0002) +#define IS_USART_TxRxEN(USART_EN) ((((USART_EN) & (uint16_t)0xFFFC) == 0x00) && ((USART_EN) != (uint16_t)0x00)) + +/** @defgroup USART_INV + * @{ + */ + +#define USART_INV_Tx ((uint16_t)0x0020) +#define USART_INV_Rx ((uint16_t)0x0010) +#define IS_USART_TxRxINV(USART_INV) ((((USART_INV) & (uint16_t)0xFFCF) == 0x00) && ((USART_INV) != (uint16_t)0x00)) + +/** @defgroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** @defgroup USART_Interrupt + * @{ + */ + +#define USART_IT_CTS ((uint16_t)0x0040) +#define USART_IT_PE ((uint16_t)0x0010) +#define USART_IT_FE ((uint16_t)0x0008) +#define USART_IT_RC ((uint16_t)0x0004) +#define USART_IT_TC ((uint16_t)0x0002) +#define USART_IT_TXE ((uint16_t)0x0001) +#define IS_USART_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x00) && ((IT) != (uint16_t)0x00)) +#define IS_USART_CLEAR_IT(IT) ((((IT) & (uint16_t)0xFFA1) == 0x00) && ((IT) != (uint16_t)0x00)) + +/** @defgroup USART_Flags + * @{ + */ + +#define USART_FLAG_TXBUSY ((uint16_t)0x0100) +#define USART_FLAG_CTSLV ((uint16_t)0x0080) +#define USART_FLAG_CTS ((uint16_t)0x0040) +#define USART_FLAG_MATCH ((uint16_t)0x0020) +#define USART_FLAG_PE ((uint16_t)0x0010) +#define USART_FLAG_FE ((uint16_t)0x0008) +#define USART_FLAG_RC ((uint16_t)0x0004) +#define USART_FLAG_TC ((uint16_t)0x0002) +#define USART_FLAG_TXE ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFE00) == 0x00) && ((FLAG) != (uint16_t)0x00)) +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFA1) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) <= 0x00F42400)) +#define IS_USART_UCLKFREQ(UCLKFREQ) (((UCLKFREQ) > 0) && ((UCLKFREQ) <= 0x03D09000)) +#define IS_USART_DATA_16BIT(DATA) ((DATA) <= 0x1FF) +#define IS_USART_DATA_8BIT(DATA) ((DATA) <= 0xFF) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xFF) +#define IS_USART_ADDRESSMSK(ADDRESSMSK) ((ADDRESSMSK) <= 0xFF) +#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == CW_UART1) || \ + ((PERIPH) == CW_UART2) || \ + ((PERIPH) == CW_UART3)) + + /****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + + /****************************************************************************** + * Global function prototypes + ******************************************************************************/ + +/* շ */ +void USART_SendData(UART_TypeDef* UARTx, uint16_t Data); +void USART_SendData_8bit(UART_TypeDef* UARTx, uint8_t Data); +uint16_t USART_ReceiveData(UART_TypeDef* USARTx); +uint8_t USART_ReceiveData_8bit(UART_TypeDef* USARTx); + +/* ʼ */ +void USART_Init(UART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(UART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void UART1_DeInit(void); +void UART2_DeInit(void); +void UART3_DeInit(void); + +/* жϼ־ */ +void USART_ITConfig(UART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); +ITStatus USART_GetITStatus(UART_TypeDef* USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(UART_TypeDef* USARTx, uint16_t USART_IT); +FlagStatus USART_GetFlagStatus(UART_TypeDef* USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(UART_TypeDef* USARTx, uint16_t USART_FLAG); + +/* ͺͽտ */ +void USART_TxRxEN(UART_TypeDef* USARTx, uint16_t USART_EN, FunctionalState NewState); +void USART_TxRxINV(UART_TypeDef* USARTx, uint16_t USART_INV, FunctionalState NewState); + +/* ˫ͨ */ +void USART_HalfDuplexCmd(UART_TypeDef* USARTx, FunctionalState NewState); + +/* DMA */ +void USART_DMACmd(UART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); + +/* ͨ */ +void USART_SetMultiMode(UART_TypeDef* USARTx, uint8_t USART_Address, uint8_t USART_AddressMsK); + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32F030_UART_H */ +/** + * @} + */ diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_vc.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_vc.h new file mode 100644 index 0000000..0cf83aa --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_vc.h @@ -0,0 +1,489 @@ +/** + * @file cw32f030_vc.h + * @author P&S (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-06-21 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +#ifndef __CW32F030_VC_H +#define __CW32F030_VC_H + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "base_types.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup VcGroup Voltage Comparator (VC) + ** + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +#define VC_INT_PRIORITY ((uint32_t)3) /*VC interrupt priority (lowest by default) */ + +/** @defgroup VC_interrupts_definition + * @{ + */ +#define VC_IT_HIGH ((uint16_t)0x0080) +#define VC_IT_RISE ((uint16_t)0x0040) +#define VC_IT_FALL ((uint16_t)0x0020) + + +#define IS_VC_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x00) && ((IT) != 0x00)) +#define IS_VC_GET_IT(IT) (((IT) == VC_IT_HIGH) || \ + ((IT) == VC_IT_RISE) || \ + ((IT) == VC_IT_FALL)) + +/** @defgroup VC_flags_definition + * @{ + */ +#define VC_FLAG_READY ((uint16_t)0x0004) +#define VC_FLAG_FLTV ((uint16_t)0x0002) +#define VC_FLAG_INTF ((uint16_t)0x0001) + +#define IS_VC_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFF00) == 0x00) && ((FLAG) != 0x00)) +#define IS_VC_GET_FLAG(FLAG) (((FLAG) == VC_FLAG_READY) || \ + ((FLAG) == VC_FLAG_FLTV) || \ + ((FLAG) == VC_FLAG_INTF)) + +/** @defgroup VC_DivEn + * @{ + */ +#define VC_Div_Disable ((uint32_t)0x00000000) +#define VC_Div_Enable ((uint32_t)0x00000040) + +#define IS_VC_DIV_EN(DIV_EN) (((DIV_EN) == VC_Div_Disable) || \ + ((DIV_EN) == VC_Div_Enable)) + +/** @defgroup VC_DivVref + * @{ + */ +#define VC_DivVref_VDDA ((uint32_t)0x00000000) +#define VC_DivVref_ADC ((uint32_t)0x00000080) + +#define IS_VC_DIV_VREF(DIV_VREF) (((DIV_VREF) == VC_DivVref_VDDA) || \ + ((DIV_VREF) == VC_DivVref_ADC)) + +/** @defgroup VC_InputP + * @{ + * VC1 VC2 + * ͨ0 PA00 ͨ0 PA05 + * ͨ1 PA01 ͨ1 PA06 + * ͨ2 PA02 ͨ2 PA07 + * ͨ3 PA03 ͨ3 PB00 + * ͨ4 PA04 ͨ4 PB01 + * ͨ5 PA05 ͨ5 PB02 + * ͨ6 PA06 ͨ6 PB10 + * ͨ7 PA07 ͨ7 PB11 + */ +#define VC_InputP_Ch0 ((uint32_t)0x00000000) +#define VC_InputP_Ch1 ((uint32_t)0x00000100) +#define VC_InputP_Ch2 ((uint32_t)0x00000200) +#define VC_InputP_Ch3 ((uint32_t)0x00000300) +#define VC_InputP_Ch4 ((uint32_t)0x00000400) +#define VC_InputP_Ch5 ((uint32_t)0x00000500) +#define VC_InputP_Ch6 ((uint32_t)0x00000600) +#define VC_InputP_Ch7 ((uint32_t)0x00000700) + + +#define IS_VC_INPUT_P(INPUT_P) (((INPUT_P) == VC_InputP_Ch0) || \ + ((INPUT_P) == VC_InputP_Ch1) || \ + ((INPUT_P) == VC_InputP_Ch2) || \ + ((INPUT_P) == VC_InputP_Ch3) || \ + ((INPUT_P) == VC_InputP_Ch4) || \ + ((INPUT_P) == VC_InputP_Ch5) || \ + ((INPUT_P) == VC_InputP_Ch6) || \ + ((INPUT_P) == VC_InputP_Ch7)) + +/** @defgroup VC_InputN + * @{ + * VC1 VC2 + * ͨ0 PA00 ͨ0 PA05 + * ͨ1 PA01 ͨ1 PA06 + * ͨ2 PA02 ͨ2 PA07 + * ͨ3 PA03 ͨ3 PB00 + * ͨ4 PA04 ͨ4 PB01 + * ͨ5 PA05 ͨ5 PB02 + * ͨ6 PA06 ͨ6 PB10 + * ͨ7 PA07 ͨ7 PB11 + * VDDAѹ VDDAѹ + * ADC VREF ADC VREF + * BGR 1.2V BGR 1.2V + * ¶ȴ ¶ȴ + */ +#define VC_InputN_Ch0 ((uint32_t)0x00000000) +#define VC_InputN_Ch1 ((uint32_t)0x00001000) +#define VC_InputN_Ch2 ((uint32_t)0x00002000) +#define VC_InputN_Ch3 ((uint32_t)0x00003000) +#define VC_InputN_Ch4 ((uint32_t)0x00004000) +#define VC_InputN_Ch5 ((uint32_t)0x00005000) +#define VC_InputN_Ch6 ((uint32_t)0x00006000) +#define VC_InputN_Ch7 ((uint32_t)0x00007000) +#define VC_InputN_DivOut ((uint32_t)0x00008000) +#define VC_InputN_AdcVref ((uint32_t)0x00009000) +#define VC_InputN_Bgr1P2 ((uint32_t)0x0000A000) +#define VC_InputN_Ts ((uint32_t)0x0000B000) + +#define IS_VC_INPUT_N(INPUT_N) (((INPUT_N) == VC_InputN_Ch0) || \ + ((INPUT_N) == VC_InputN_Ch1) || \ + ((INPUT_N) == VC_InputN_Ch2) || \ + ((INPUT_N) == VC_InputN_Ch3) || \ + ((INPUT_N) == VC_InputN_Ch4) || \ + ((INPUT_N) == VC_InputN_Ch5) || \ + ((INPUT_N) == VC_InputN_Ch6) || \ + ((INPUT_N) == VC_InputN_Ch7) || \ + ((INPUT_N) == VC_InputN_DivOut) || \ + ((INPUT_N) == VC_InputN_AdcVref) || \ + ((INPUT_N) == VC_InputN_Bgr1P2) || \ + ((INPUT_N) == VC_InputN_Ts)) + +/** @defgroup VC_Hys + * @{ + */ +#define VC_Hys_Off ((uint32_t)0x00000000) +#define VC_Hys_10mV ((uint32_t)0x00000008) +#define VC_Hys_20mV ((uint32_t)0x00000010) +#define VC_Hys_30mV ((uint32_t)0x00000018) + +#define IS_VC_HYS(HYS) (((HYS) == VC_Hys_Off) || \ + ((HYS) == VC_Hys_10mV) || \ + ((HYS) == VC_Hys_20mV) || \ + ((HYS) == VC_Hys_30mV)) + +/** @defgroup VC_Resp + * @{ + */ +#define VC_Resp_ExtraLow ((uint32_t)0x00000000) +#define VC_Resp_Low ((uint32_t)0x00000002) +#define VC_Resp_Medium ((uint32_t)0x00000004) +#define VC_Resp_High ((uint32_t)0x00000006) + +#define IS_VC_RESP(RESP) (((RESP) == VC_Resp_ExtraLow) || \ + ((RESP) == VC_Resp_Low) || \ + ((RESP) == VC_Resp_Medium) || \ + ((RESP) == VC_Resp_High)) + +/** @defgroup VC_FilterEn + * @{ + */ +#define VC_Filter_Disable ((uint32_t)0x00000000) +#define VC_Filter_Enable ((uint32_t)0x00000001) + +#define IS_VC_FILTER(FILTER) (((FILTER) == VC_Filter_Disable) || \ + ((FILTER) == VC_Filter_Enable)) + +/** @defgroup VC_FilterClk + * @{ + */ +#define VC_FltClk_RC150K ((uint32_t)0x00000000) +#define VC_FltClk_PCLK ((uint32_t)0x00000010) + +#define IS_VC_FLT_CLK(FLT_CLK) (((FLT_CLK) == VC_FltClk_RC150K) || \ + ((FLT_CLK) == VC_FltClk_PCLK)) + +/** @defgroup VC_FilterTime + * @{ + */ +#define VC_FltTime_1Clk ((uint32_t)0x00000000) +#define VC_FltTime_3Clk ((uint32_t)0x00000002) +#define VC_FltTime_7Clk ((uint32_t)0x00000004) +#define VC_FltTime_15Clk ((uint32_t)0x00000006) +#define VC_FltTime_63Clk ((uint32_t)0x00000008) +#define VC_FltTime_255Clk ((uint32_t)0x0000000A) +#define VC_FltTime_1023Clk ((uint32_t)0x0000000C) +#define VC_FltTime_4095Clk ((uint32_t)0x0000000E) + + +#define IS_VC_FLT_TIME(FLT_TIME) (((FLT_TIME) == VC_FltTime_1Clk) || \ + ((FLT_TIME) == VC_FltTime_3Clk) || \ + ((FLT_TIME) == VC_FltTime_7Clk) || \ + ((FLT_TIME) == VC_FltTime_15Clk) || \ + ((FLT_TIME) == VC_FltTime_63Clk) || \ + ((FLT_TIME) == VC_FltTime_255Clk) || \ + ((FLT_TIME) == VC_FltTime_1023Clk) || \ + ((FLT_TIME) == VC_FltTime_4095Clk)) + +/** @defgroup VC_WindowEn + * @{ + */ +#define VC_Window_Disable ((uint32_t)0x00000000) +#define VC_Window_Enable ((uint32_t)0x00000080) + +#define IS_VC_WINDOW(WINDOW) (((WINDOW) == VC_Window_Disable) || \ + ((WINDOW) == VC_Window_Enable)) + +/** @defgroup VC_Polarity + * @{ + */ +#define VC_Polarity_Low ((uint32_t)0x00000000) +#define VC_Polarity_High ((uint32_t)0x00000040) + +#define IS_VC_POLARITY(POLARITY) (((POLARITY) == VC_Polarity_Low) || \ + ((POLARITY) == VC_Polarity_High)) + +/** @defgroup VC_BlankFlt + * @{ + */ +#define VC_BlankFlt_4Clk ((uint32_t)0x00000000) +#define VC_BlankFlt_8Clk ((uint32_t)0x00002000) +#define VC_BlankFlt_16Clk ((uint32_t)0x00004000) +#define VC_BlankFlt_32Clk ((uint32_t)0x00006000) +#define VC_BlankFlt_64Clk ((uint32_t)0x00008000) +#define VC_BlankFlt_128Clk ((uint32_t)0x0000A000) +#define VC_BlankFlt_256Clk ((uint32_t)0x0000C000) +#define VC_BlankFlt_512Clk ((uint32_t)0x0000E000) + +#define IS_VC_BLANK_FLT(BLANK_FLT) (((BLANK_FLT) == VC_BlankFlt_4Clk) || \ + ((BLANK_FLT) == VC_BlankFlt_8Clk) || \ + ((BLANK_FLT) == VC_BlankFlt_16Clk) || \ + ((BLANK_FLT) == VC_BlankFlt_32Clk) || \ + ((BLANK_FLT) == VC_BlankFlt_64Clk) || \ + ((BLANK_FLT) == VC_BlankFlt_128Clk) || \ + ((BLANK_FLT) == VC_BlankFlt_256Clk) || \ + ((BLANK_FLT) == VC_BlankFlt_512Clk)) + +/** @defgroup VC_BlankCh3B + * @{ + */ +#define VC_BlankCh3B_Disable ((uint32_t)0x00000000) +#define VC_BlankCh3B_Enable ((uint32_t)0x00001000) + +#define IS_VC_BLANK_CH3B(BLANK_CH3B) (((BLANK_CH3B) == VC_BlankCh3B_Disable) || \ + ((BLANK_CH3B) == VC_BlankCh3B_Enable)) + +/** @defgroup VC_BlankCh2B + * @{ + */ +#define VC_BlankCh2B_Disable ((uint32_t)0x00000000) +#define VC_BlankCh2B_Enable ((uint32_t)0x00000800) + +#define IS_VC_BLANK_CH2B(BLANK_CH2B) (((BLANK_CH2B) == VC_BlankCh2B_Disable) || \ + ((BLANK_CH2B) == VC_BlankCh2B_Enable)) + +/** @defgroup VC_BlankCh1B + * @{ + */ +#define VC_BlankCh1B_Disable ((uint32_t)0x00000000) +#define VC_BlankCh1B_Enable ((uint32_t)0x00000400) + +#define IS_VC_BLANK_CH1B(BLANK_CH1B) (((BLANK_CH1B) == VC_BlankCh1B_Disable) || \ + ((BLANK_CH1B) == VC_BlankCh1B_Enable)) + + +/** @defgroup VC_ATIMBk + * @{ + */ +#define VC_ATIMBk_Disable ((uint32_t)0x00000000) +#define VC_ATIMBk_Enable ((uint32_t)0x00000200) + +#define IS_VC_ATIMBK(ATIMBK) (((ATIMBK) == VC_ATIMBk_Disable) || \ + ((ATIMBK) == VC_ATIMBk_Enable)) + +/** @defgroup VC_ATIMClr + * @{ + */ +#define VC_ATIMClr_Disable ((uint32_t)0x00000000) +#define VC_ATIMClr_Enable ((uint32_t)0x00000100) + +#define IS_VC_ATIMCLR(ATIMCLR) (((ATIMCLR) == VC_ATIMClr_Disable) || \ + ((ATIMCLR) == VC_ATIMClr_Enable)) + + +/** + ****************************************************************************** + ** @brief VCģ + *****************************************************************************/ +typedef struct +{ + uint32_t VC_DivVref; // 6-bit VDDA dividerοѹѡ + uint32_t VC_DivEn; // ʹ6-bit VDDA divider + uint8_t VC_DivValue; // 6-bit VDDA dividerֵ +}VC_DivTypeDef; + +/** + ****************************************************************************** + ** @brief VCͨ + *****************************************************************************/ +typedef struct +{ + uint32_t VC_InputP; // P + uint32_t VC_InputN; // N + uint32_t VC_Hys; // VC + uint32_t VC_Resp; // VCӦٶ + uint32_t VC_FilterEn; // VC˲ʹ + uint32_t VC_FilterClk; // ˲ʱԴ + uint32_t VC_FilterTime; // ˲ʱ + uint32_t VC_Window; // VCڱȽϹʹ + uint32_t VC_Polarity; // VCźż +}VC_InitTypeDef; + +/** + ****************************************************************************** + ** @brief VCģBlank + *****************************************************************************/ +typedef struct +{ + uint32_t VC_BlankFlt; /*Blankڳʱ*/ + + uint32_t VC_BlankCh3B; /*ATIMCH3VCxBlank*/ + + uint32_t VC_BlankCh2B; /*ATIMCH2VCxBlank*/ + + uint32_t VC_BlankCh1B; /*ATIMCH1VCxBlank*/ +}VC_BlankTypeDef; + +/** + ****************************************************************************** + ** @brief VCӵATIMBK/CLRź + *****************************************************************************/ +typedef struct +{ + uint32_t VC_ATIMBk; /*VCxӵATIMBKź*/ + + uint32_t VC_OutAtimClr; /*VCxӵATIMCLRź*/ +}VC_OutTypeDef; + +/****************************************************************************** + * Global definitions + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions ('extern') + ******************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + ******************************************************************************/ +//VC1/VC2ģVCxźųʼ +void VC1VC2_INNInit(VC_InitTypeDef* VC_InitStruct); + +//VCͨ1ʼ +void VC1_ChannelInit(VC_InitTypeDef* VC_InitStruct); +//VCͨ2ʼ +void VC2_ChannelInit(VC_InitTypeDef* VC_InitStruct); +//VCͨ1ȥʼ +void VC1_ChannelDeInit(void); +//VCͨ2ȥʼ +void VC2_ChannelDeInit(void); +//VCģȥʼ +void VC_DeInit(void); + +//VC1/VC2ģDIVοѹʼ +void VC1VC2_DIVInit(VC_DivTypeDef* VC_DivStruct); +//VC1/VC2ģDIVοѹȥʼ +void VC1VC2_DIVDeInit(void); + +//VC1ͨʹ +void VC1_EnableChannel(void); +//VC2ͨʹ +void VC2_EnableChannel(void); +//VC1ͨ +void VC1_DisableChannel(void); +//VC2ͨ +void VC2_DisableChannel(void); + +//VC1˲ʹ +void VC1_EnableFilter(void); +//VC2˲ʹ +void VC2_EnableFilter(void); +//VC1˲ +void VC1_DisableFilter(void); +//VC2˲ +void VC2_DisableFilter(void); + +//VCͨ1/2 Ĭֵʼ +void VC1VC2_OutInit(VC_OutTypeDef* VC_OutStruct); +//VCͨ1 +void VC1_OutputCfg(VC_OutTypeDef* VC_OutStruct); +//VCͨ2 +void VC2_OutputCfg(VC_OutTypeDef* VC_OutStruct); + +//VCͨ1/2 BlanKĬֵʼ +void VC1VC2_BlankInit(VC_BlankTypeDef* VC_BlankStruct); +//VCͨ1 BlanK +void VC1_BlankCfg(VC_BlankTypeDef* VC_BlankStruct); +//VCͨ2 BlanK +void VC2_BlankCfg(VC_BlankTypeDef* VC_BlankStruct); + +//VCͨ1ڱȽϹ +void VC1_WindowEnable(boolean_t bWindow); +//VCͨ2ڱȽϹ +void VC2_WindowEnable(boolean_t bWindow); + +//VCͨ1źż +void VC1_PolarityCfg(boolean_t bPolarity); +//VCͨ2źż +void VC2_PolarityCfg(boolean_t bPolarity); + +//ʹNVICVCxж +void VC_EnableNvic(IRQn_Type enIrqn, uint8_t intPriority); +//ֹNVICVCж +void VC_DisableNvic(IRQn_Type enIrqn); +//VCͨ1жϽ +void VC1_DisableIrq(void); +//VCͨ2жϽ +void VC2_DisableIrq(void); +//VCͨ1жʹ +void VC1_EnableIrq(uint8_t intPriority); +//VCͨ2жʹ +void VC2_EnableIrq(uint8_t intPriority); +//VC1жϴʽ +void VC1_ITConfig(uint16_t VC_IT, FunctionalState NewState); +//VC2жϴʽ +void VC2_ITConfig(uint16_t VC_IT, FunctionalState NewState); + +//VC1жϱ־ +void VC1_ClearIrq(void); +//VC2жϱ־ +void VC2_ClearIrq(void); + +//ȡVC1״̬ +FlagStatus VC1_GetFlagStatus(uint16_t VC_FLAG); +//ȡVC2״̬ +FlagStatus VC2_GetFlagStatus(uint16_t VC_FLAG); + +//@} // VcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __CW32F030_VC_H */ +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_wwdt.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_wwdt.h new file mode 100644 index 0000000..7243f19 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/cw32f030_wwdt.h @@ -0,0 +1,99 @@ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32F030_WWDT_H +#define __CW32F030_WWDT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030.h" + +/****************************************************************************** + * type definitions ('typedef') + ******************************************************************************/ +typedef struct +{ + uint32_t WWDT_Prescaler; /* ԤϵȡֵΧ2nݣn=12,13..19 */ + + uint32_t WWDT_WindowValue; /* ŹֵȡֵΧС0x80*/ + + uint8_t WWDT_CounterValue; /* ŹֵȡֵΧ0x40 0x7F. */ + + FunctionalState WWDT_ITState; /* Źж״̬ȡֵΧENABLEDISABLE */ +} WWDT_InitTypeDef; +/****************************************************************************** + * pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define WWDT_Prescaler_DIV4096 ((uint32_t)0x00000000) +#define WWDT_Prescaler_DIV8192 ((uint32_t)0x00000080) +#define WWDT_Prescaler_DIV16384 ((uint32_t)0x00000100) +#define WWDT_Prescaler_DIV32768 ((uint32_t)0x00000180) +#define WWDT_Prescaler_DIV65536 ((uint32_t)0x00000200) +#define WWDT_Prescaler_DIV131072 ((uint32_t)0x00000280) +#define WWDT_Prescaler_DIV262144 ((uint32_t)0x00000300) +#define WWDT_Prescaler_DIV524288 ((uint32_t)0x00000380) +#define IS_WWDT_PRESCALER(PRESCALER) (((PRESCALER) == WWDT_Prescaler_DIV4096) || \ + ((PRESCALER) == WWDT_Prescaler_DIV8192) || \ + ((PRESCALER) == WWDT_Prescaler_DIV16384) || \ + ((PRESCALER) == WWDT_Prescaler_DIV32768) || \ + ((PRESCALER) == WWDT_Prescaler_DIV65536) || \ + ((PRESCALER) == WWDT_Prescaler_DIV131072) || \ + ((PRESCALER) == WWDT_Prescaler_DIV262144) || \ + ((PRESCALER) == WWDT_Prescaler_DIV524288)) +#define IS_WWDT_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDT_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + + +#define WWDT_GET_POV_STATUS(VALUE) {(VALUE) = (FlagStatus)(CW_WWDT->SR);} +#define WWDT_CLR_POV_STATUS() {REGBITS_CLR(CW_WWDT->SR, WWDT_SR_POV_Msk);} +#define WWDT_ENABLE_IT() {REGBITS_SET(CW_WWDT->CR1,WWDT_CR1_IE_Msk);} +#define WWDT_FEED(VALUE) {REGBITS_MODIFY(CW_WWDT->CR0, WWDT_CR0_WCNT_Msk,(VALUE));} + + /****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + + /****************************************************************************** + * Global function prototypes + ******************************************************************************/ +void WWDT_DeInit(void); +void WWDT_Init(WWDT_InitTypeDef* WWDT_InitStruct); +void WWDT_Refresh(uint8_t Counter); + + +void WWDT_Cmd(void); +void WWDT_SetPrescaler(uint32_t WWDT_Prescaler); +void WWDT_SetWindowValue(uint8_t WindowValue); +uint8_t WWDT_GetCounterValue(void); +uint8_t WWDT_GetWindowValue(void); +void WWDT_EnableIT(void); +FlagStatus WWDT_GetFlagStatus(void); +void WWDT_ClearFlag(void); + + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32F030_WWDT_H */ +/** + * @} + */ diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/inc/system_cw32f030.h b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/system_cw32f030.h new file mode 100644 index 0000000..ee66b29 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/inc/system_cw32f030.h @@ -0,0 +1,76 @@ + + +#ifndef __SYSTEM_PS030_H +#define __SYSTEM_PS030_H + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include +#include "base_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/******************************************************************************/ +#define HWWD_DISABLE (1) + +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u + + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern void SystemInit (void); // Initialize the system +//extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable + +/** + ******************************************************************************* + ** This hook is part of wait loops. + ******************************************************************************/ +//extern void delay1ms(uint32_t u32Cnt); +//extern void delay100us(uint32_t u32Cnt); +//extern void delay10us(uint32_t u32Cnt); +extern void FirmwareDelay(uint32_t DlyCnt ); + +extern void memclr(void* pu8Address, uint32_t u32Count); + +void SetBit(uint32_t addr, uint32_t offset, boolean_t bFlag); +void ClrBit(uint32_t addr, uint32_t offset); +boolean_t GetBit(uint32_t addr, uint32_t offset); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_PS030 _H__ */ + + + + + + + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_adc.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_adc.c new file mode 100644 index 0000000..507d221 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_adc.c @@ -0,0 +1,1038 @@ +/** + * @file cw32f030_adc.c + * @author P&S (you@domain.com) + * @brief + * @version 0.1 + * @file cw32f030_adc.c + * @author P&S (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-07-12 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* + * + * ɺϢ + * 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ + * ɸضҪƵƹܡݲܱųκη֤人Դ + * ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ + * ı֤ڰйԡijض;ͷȨı֤ + * + * ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и + * ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ + * ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ + * ʧ + * ijЩ˾ϽֱӵġĻԵκεųƣijЩ + * ȫųƿܲ + * + *******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "cw32f030.h" +#include "cw32f030_adc.h" + +/** + ****************************************************************************** + ** \addtogroup AdcGroup + ******************************************************************************/ +//@{ +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** + * @brief + * ȡADCж״̬ + * + * @param pFlagAdcIrq + */ +void ADC_GetITStatusAll(volatile uint8_t* pFlagAdcIrq) +{ + *pFlagAdcIrq = (uint8_t) (CW_ADC->ISR); +} + +/** + * @brief + * ȡADCָж״̬ + * + * @param ADC_IT: + * @arg ADC_IT_READY + * @arg ADC_IT_OVW + * @arg ADC_IT_WDTR + * @arg ADC_IT_WDTH + * @arg ADC_IT_WDTL + * @arg ADC_IT_EOA + * @arg ADC_IT_EOS + * @arg ADC_IT_EOC + * + * @return ITStatus: SET or RESET + */ +ITStatus ADC_GetITStatus(uint16_t ADC_IT) +{ + assert_param(IS_ADC_GET_IT(IT)(ADC_IT)); + return (REGBITS_GET(CW_ADC->ISR, ADC_IT) ? SET : RESET); +} + +/** + * @brief + * ADCж״̬ + */ +void ADC_ClearITPendingAll(void) +{ + REGBITS_CLR(CW_ADC->ICR, + (ADC_ISR_OVW_Msk | ADC_ISR_WDTR_Msk |\ + ADC_ISR_WDTH_Msk | ADC_ISR_WDTL_Msk | ADC_ISR_EOA_Msk |\ + ADC_ISR_EOS_Msk | ADC_ISR_EOC_Msk)); +} + +/** + * @brief + * ADCָж״̬ + * + * @param ADC_IT + * @arg ADC_IT_OVW + * @arg ADC_IT_WDTR + * @arg ADC_IT_WDTH + * @arg ADC_IT_WDTL + * @arg ADC_IT_EOA + * @arg ADC_IT_EOS + * @arg ADC_IT_EOC + */ +void ADC_ClearITPendingBit(uint16_t ADC_IT) +{ + assert_param(IS_ADC_GET_IT(IT)(ADC_IT)); + REGBITS_CLR(CW_ADC->ICR, ADC_IT); +} + +/** + * @brief + * ADCжʹ + * + * @param intPriority + */ +void ADC_EnableIrq(uint8_t intPriority) +{ + ADC_EnableNvic(intPriority); +} + +/** + * @brief + * ADCжϽֹ + */ +void ADC_DisableIrq(void) +{ + REGBITS_CLR(CW_ADC->IER, + ADC_IER_OVW_Msk | ADC_IER_WDTR_Msk | ADC_IER_WDTH_Msk |\ + ADC_IER_WDTL_Msk | ADC_IER_EOA_Msk | ADC_IER_EOS_Msk |\ + ADC_IER_EOC_Msk); + ADC_DisableNvic(); +} + +/** + * @brief + * ADCģ⿴Ź + * + * @param ADC_WdtStruct + */ +void ADC_WdtConfig(ADC_WdtTypeDef *ADC_WdtStruct) +{ + ASSERT(NULL != ADC_WdtStruct); + assert_param(IS_ADC_WDT_CH(ADC_WdtStruct->ADC_WdtCh )); + assert_param(IS_ADC_WDT_EN(ADC_WdtStruct->ADC_WdtAll )); + assert_param(IS_ADC_WDTR_EN(ADC_WdtStruct->ADC_WdtrIrq )); + assert_param(IS_ADC_WDTH_EN(ADC_WdtStruct->ADC_WdthIrq )); + assert_param(IS_ADC_WDTL_EN(ADC_WdtStruct->ADC_WdtlIrq )); + + //ͨģ⿴Źʹܿ + //ֵȽͨѡ + REGBITS_MODIFY(CW_ADC->CR1, ADC_CR1_WDTALL_Msk | ADC_CR1_WDTCH_Msk, + ADC_WdtStruct->ADC_WdtAll |\ + ADC_WdtStruct->ADC_WdtCh); + + REGBITS_MODIFY(CW_ADC->IER, + ADC_IER_WDTR_Msk | ADC_IER_WDTH_Msk | ADC_IER_WDTL_Msk, + ADC_WdtStruct->ADC_WdtrIrq |\ + ADC_WdtStruct->ADC_WdthIrq |\ + ADC_WdtStruct->ADC_WdtlIrq); + CW_ADC->VTH = ADC_WdtStruct->ADC_Vth; //ģ⿴Źֵ + CW_ADC->VTL = ADC_WdtStruct->ADC_Vtl; //ģ⿴Źֵ + + if (ADC_WdtStruct->ADC_WdtCh == ADC_WdtVref1P2) + { + REGBITS_SET(CW_ADC->CR0, ADC_CR0_BGREN_Msk); + } +} + +/** + * @brief + * ADCʼ + * + * @param ADC_InitStruct + */ +void ADC_Init(ADC_InitTypeDef *ADC_InitStruct) +{ + ASSERT(NULL != ADC_InitStruct); + assert_param(IS_ADC_OP_MODE(ADC_InitStruct->ADC_OpMode )); + assert_param(IS_ADC_CLK_DIV(ADC_InitStruct->ADC_ClkDiv )); + assert_param(IS_ADC_SAMPLE_TIME(ADC_InitStruct->ADC_SampleTime )); + assert_param(IS_ADC_VREF_SEL(ADC_InitStruct->ADC_VrefSel )); + assert_param(IS_ADC_BUF_ENABLE(ADC_InitStruct->ADC_InBufEn )); + assert_param(IS_ADC_TS_ENABLE(ADC_InitStruct->ADC_TsEn )); + assert_param(IS_ADC_DMA_ENABLE(ADC_InitStruct->ADC_DMAEn )); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_Align )); + assert_param(IS_ADC_ACC_ENABLE(ADC_InitStruct->ADC_AccEn )); + +/* if (NULL == ADC_InitStruct) + { + return; + }*/ + + REGBITS_MODIFY(CW_ADC->CR0, + ADC_CR0_BUF_Msk | ADC_CR0_SAM_Msk | ADC_CR0_CLK_Msk |\ + ADC_CR0_REF_Msk | ADC_CR0_TSEN_Msk | ADC_CR0_MODE_Msk, + ADC_InitStruct->ADC_InBufEn |\ + ADC_InitStruct->ADC_SampleTime |\ + ADC_InitStruct->ADC_ClkDiv |\ + ADC_InitStruct->ADC_VrefSel |\ + ADC_InitStruct->ADC_TsEn |\ + ADC_InitStruct->ADC_OpMode); + + REGBITS_MODIFY(CW_ADC->CR1, ADC_CR1_DMAEN_Msk | ADC_CR1_ALIGN_Msk, + ADC_InitStruct->ADC_DMAEn |\ + ADC_InitStruct->ADC_Align); + + if (ADC_InitStruct->ADC_AccEn) + { + REGBITS_MODIFY(CW_ADC->CR2, ADC_CR2_ACCEN_Msk | ADC_CR2_ACCRST_Msk, + ADC_InitStruct->ADC_AccEn |\ + 1u << ADC_CR2_ACCRST_Pos); + } +} + +/** + * @brief + * ADCĬֵʼ + * + * @param ADC_InitStruct + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + ADC_InitStruct->ADC_OpMode = ADC_SingleChOneMode; //ͨתģʽ + ADC_InitStruct->ADC_ClkDiv = ADC_Clk_Div1; //PCLK + ADC_InitStruct->ADC_SampleTime = ADC_SampTime5Clk; //5ADCʱ + ADC_InitStruct->ADC_VrefSel = ADC_Vref_VDDA; //VDDAοѹ + ADC_InitStruct->ADC_InBufEn = ADC_BufDisable; //رո + ADC_InitStruct->ADC_TsEn = ADC_TsDisable; //ر¶ȴ + ADC_InitStruct->ADC_DMAEn = ADC_DmaDisable; //DMA + ADC_InitStruct->ADC_Align = ADC_AlignRight; //ADCתҶ + ADC_InitStruct->ADC_AccEn = ADC_AccDisable; //תۼӲʹ +} + +/** + * @brief + * ADCģ⿴ŹĬֵʼ + * + * @param ADC_WdtStruct + */ +void ADC_WdtInit(ADC_WdtTypeDef *ADC_WdtStruct) +{ + ADC_WdtStruct->ADC_WdtCh = ADC_WdtCh0; + ADC_WdtStruct->ADC_WdtAll = ADC_WdtDisable; + ADC_WdtStruct->ADC_WdtrIrq = ADC_WdtrDisable; + ADC_WdtStruct->ADC_WdthIrq = ADC_WdthDisable; + ADC_WdtStruct->ADC_WdtlIrq = ADC_WdtlDisable; + ADC_WdtStruct->ADC_Vth = 0x0FFF; + ADC_WdtStruct->ADC_Vtl = 0x00; +} + +/** + * @brief + * ADCⲿжϴԴ + * + * @param ADC_TRIG: + * @arg ADC_TRIG_DMA + * @arg ADC_TRIG_I2C2 + * @arg ADC_TRIG_I2C1 + * @arg ADC_TRIG_SPI2 + * @arg ADC_TRIG_SPI1 + * @arg ADC_TRIG_UART3 + * @arg ADC_TRIG_UART2 + * @arg ADC_TRIG_UART1 + * @arg ADC_TRIG_BTIM3 + * @arg ADC_TRIG_BTIM2 + * @arg ADC_TRIG_BTIM1 + * @arg ADC_TRIG_GTIM4 + * @arg ADC_TRIG_GTIM3 + * @arg ADC_TRIG_GTIM2 + * @arg ADC_TRIG_GTIM1 + * @arg ADC_TRIG_ATIM + * @param NewState: + * @arg DISABLE + * @arg ENABLE + */ +void ADC_ExtTrigCfg(uint16_t ADC_TRIG, FunctionalState NewState) +{ + uint16_t trigMask = 0; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_TRIG(ADC_TRIG)); + /* Get the ADC TRIG index */ + trigMask = ADC_TRIG; + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + CW_ADC->TRIGGER |= trigMask; + } + else + { + /* Disable the selected ADC interrupts */ + CW_ADC->TRIGGER &= (~(uint32_t) trigMask); + } +} + +/** + * @brief + * ADCȥʼ + */ +void ADC_DeInit(void) +{ + // Enable ADC reset state + REGBITS_CLR(CW_SYSCTRL->APBRST2, SYSCTRL_APBRST2_ADC_Msk); + // Release ADC from reset state + REGBITS_SET(CW_SYSCTRL->APBRST2, SYSCTRL_APBRST2_ADC_Msk); +} + +/** + * @brief + * ADCת + * + * @param NewState + * @arg DISABLE + * @arg ENABLE + */ +void ADC_SoftwareStartConvCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + REGBITS_SET(CW_ADC->START, ADC_START_START_Msk); + } + else + { + REGBITS_CLR(CW_ADC->START, ADC_START_START_Msk); + } +} + +/** + * @brief + * ADCʹ + */ +void ADC_Enable(void) +{ + REGBITS_SET(CW_ADC->CR0, ADC_CR0_EN_Msk); + //ȴ ADC ģ + while (!ADC_GetITStatus(ADC_IT_READY)); +} + +/** + * @brief + * ADC + */ +void ADC_Disable(void) +{ + REGBITS_CLR(CW_ADC->CR0, ADC_CR0_EN_Msk); +} + +/** + * @brief + * ͨתģʽ + * + * @param ADC_SingleChStruct + */ +void ADC_SingleChCommon(ADC_SingleChTypeDef *ADC_SingleChStruct) +{ + ASSERT(NULL != ADC_SingleChStruct); + assert_param(IS_ADC_CH_SEL(ADC_SingleChStruct->ADC_Chmux )); + assert_param(IS_ADC_DATA_DISCARD(ADC_SingleChStruct->ADC_DiscardEn )); + +/* if (NULL == ADC_SingleChStruct) + { + return; + }*/ + + ADC_Init(&ADC_SingleChStruct->ADC_InitStruct); + ADC_BufEnSingleCh(ADC_SingleChStruct->ADC_Chmux); + if (ADC_SingleChStruct->ADC_WdtStruct.ADC_WdtAll == ADC_WdtEnable) + { + ADC_WdtConfig(&ADC_SingleChStruct->ADC_WdtStruct); + } + + REGBITS_MODIFY(CW_ADC->CR1, ADC_CR1_DISCARD_Msk | ADC_CR1_CHMUX_Msk, + ADC_SingleChStruct->ADC_DiscardEn |\ + ADC_SingleChStruct->ADC_Chmux); +} + +/** + * @brief + * ADCͨתģʽ + * + * @param ADC_SingleChStruct + */ +void ADC_SingleChOneModeCfg(ADC_SingleChTypeDef *ADC_SingleChStruct) +{ + ADC_SingleChCommon(ADC_SingleChStruct); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_MODE_Msk, ADC_SingleChOneMode); +} + +/** + * @brief + * ADCͨתģʽ + * + * @param ADC_SingleChStruct + * @param cntAdcSample: 0 ~ 255 + */ +void ADC_SingleChMoreModeCfg(ADC_SingleChTypeDef *ADC_SingleChStruct, + uint8_t cntAdcSample) +{ + ADC_SingleChStruct->ADC_InitStruct.ADC_AccEn = ADC_AccEnable; //Must be added + + ADC_SingleChCommon(ADC_SingleChStruct); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_MODE_Msk, ADC_SingleChMoreMode); + CW_ADC->CR2_f.CNT = cntAdcSample; +} + +/** + * @brief + * ADCͨתģʽ + * + * @param ADC_SingleChStruct + */ +void ADC_SingleChContinuousModeCfg(ADC_SingleChTypeDef *ADC_SingleChStruct) +{ + ADC_SingleChCommon(ADC_SingleChStruct); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_MODE_Msk, ADC_SingleChContinuousMode); +} + +/** + * @brief + * ADCתģʽ + * + * @param ADC_SerialChStruct + */ +void ADC_SerialChCommon(ADC_SerialChTypeDef *ADC_SerialChStruct) +{ + if (NULL == ADC_SerialChStruct) + { + return; + } + + ADC_Init(&ADC_SerialChStruct->ADC_InitStruct); + + switch (ADC_SerialChStruct->ADC_SqrEns) + { + case ADC_SqrEns0: + ADC_Sqr0ChannelCfg(ADC_SerialChStruct); + break; + case ADC_SqrEns01: + ADC_Sqr01ChannelCfg(ADC_SerialChStruct); + break; + case ADC_SqrEns02: + ADC_Sqr02ChannelCfg(ADC_SerialChStruct); + break; + case ADC_SqrEns03: + ADC_Sqr03ChannelCfg(ADC_SerialChStruct); + break; + + default: + break; + } + +} + +/** + * @brief + * ADCתģʽ + * + * @param ADC_SerialChStruct + */ +void ADC_SerialChContinuousModeCfg(ADC_SerialChTypeDef *ADC_SerialChStruct) +{ + ADC_SerialChCommon(ADC_SerialChStruct); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_MODE_Msk, ADC_SerialChContinuousMode); +} + +/** + * @brief + * ADCɨתģʽ + * + * @param ADC_SerialChStruct + */ +void ADC_SerialChScanModeCfg(ADC_SerialChTypeDef *ADC_SerialChStruct) +{ + ADC_SerialChCommon(ADC_SerialChStruct); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_MODE_Msk, ADC_SerialChScanMode); +} + +/** + * @brief + * ADCжתģʽ + * + * @param ADC_SerialChStruct + * @param cntAdcSample: 0 ~ 255 + */ +void ADC_SerialChMoreModeCfg(ADC_SerialChTypeDef *ADC_SerialChStruct, + uint8_t cntAdcSample) +{ + ADC_SerialChStruct->ADC_InitStruct.ADC_AccEn = ADC_AccEnable; //Must be added + + ADC_SerialChCommon(ADC_SerialChStruct); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_MODE_Msk, ADC_SerialChMoreMode); + + CW_ADC->CR2_f.CNT = cntAdcSample; +} + +/** + * @brief + * ADCжתģʽ + * + * @param ADC_SerialChStruct + */ +void ADC_SerialChBreakModeCfg(ADC_SerialChTypeDef *ADC_SerialChStruct) +{ + ADC_SerialChCommon(ADC_SerialChStruct); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_MODE_Msk, ADC_SerialChBreakMode); +} + +/** + * @brief + * ͨģʽøʹ + * + * @param enAdcSampCh: + * @arg ADC_ExInputCH0 + * @arg ADC_ExInputCH1 + * @arg ADC_ExInputCH2 + * @arg ADC_ExInputCH3 + * @arg ADC_ExInputCH4 + * @arg ADC_ExInputCH5 + * @arg ADC_ExInputCH6 + * @arg ADC_ExInputCH7 + * @arg ADC_ExInputCH8 + * @arg ADC_ExInputCH9 + * @arg ADC_ExInputCH10 + * @arg ADC_ExInputCH11 + * @arg ADC_ExInputCH12 + * @arg ADC_VddaDiV3Input + * @arg ADC_TsInput + * @arg ADC_Vref1P2Input + */ +void ADC_BufEnSingleCh(uint32_t enAdcSampCh) +{ + if ((enAdcSampCh == ADC_VddaDiV3Input) || (enAdcSampCh == ADC_TsInput) + || (enAdcSampCh == ADC_Vref1P2Input)) + { + REGBITS_SET(CW_ADC->CR0, ADC_CR0_BUF_Msk); + } + + if (enAdcSampCh == ADC_Vref1P2Input) + { + REGBITS_SET(CW_ADC->CR0, ADC_CR0_BGREN_Msk); + } + + //ADCͨѡ¶ȴѹҪʹ¶ȴ + else if (enAdcSampCh == ADC_TsInput) + { + //ʹ¶ȴ + REGBITS_SET(CW_ADC->CR0, ADC_CR0_TSEN_Msk); + } +} + +/** + * @brief + * ģʽøʹ + * + * @param enAdcSampCh: + * @arg ADC_SqrCh0 + * @arg ADC_SqrCh1 + * @arg ADC_SqrCh2 + * @arg ADC_SqrCh3 + * @arg ADC_SqrCh4 + * @arg ADC_SqrCh5 + * @arg ADC_SqrCh6 + * @arg ADC_SqrCh7 + * @arg ADC_SqrCh8 + * @arg ADC_SqrCh9 + * @arg ADC_SqrCh10 + * @arg ADC_SqrCh11 + * @arg ADC_SqrCh12 + * @arg ADC_SqrVddaDiV3 + * @arg ADC_SqrTs + * @arg ADC_SqrVref1P2 + */ +void ADC_BufEnSerialCh(uint32_t enAdcSampCh) +{ + if ((enAdcSampCh == ADC_SqrVddaDiV3) || (enAdcSampCh == ADC_SqrTs) + || (enAdcSampCh == ADC_SqrVref1P2)) + { + REGBITS_SET(CW_ADC->CR0, ADC_CR0_BUF_Msk); + } + + if (enAdcSampCh == ADC_SqrVref1P2) + { + REGBITS_SET(CW_ADC->CR0, ADC_CR0_BGREN_Msk); + } + + //ADCͨѡ¶ȴѹҪʹ¶ȴ + else if (enAdcSampCh == ADC_SqrTs) + { + //ʹ¶ȴ + REGBITS_SET(CW_ADC->CR0, ADC_CR0_TSEN_Msk); + } +} + +/** + * @brief + * SQR0תͨ + * + * @param ADC_SerialChStruct + */ +void ADC_Sqr0ChannelCfg(ADC_SerialChTypeDef *ADC_SerialChStruct) +{ + ASSERT(NULL != ADC_SerialChStruct); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr0Chmux )); + assert_param(IS_ADC_SQR_ENS(ADC_SerialChStruct->ADC_SqrEns )); + + //ADC_SerialChStruct->ADC_SqrEns = ADC_SqrEns0; + REGBITS_MODIFY(CW_ADC->SQR, ADC_SQR_ENS_Msk | ADC_SQR_SQR0_Msk, + ADC_SerialChStruct->ADC_SqrEns |\ + ADC_SerialChStruct->ADC_Sqr0Chmux); + + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr0Chmux); +} + +/** + * @brief + * SQR0/SQR1תͨ + * + * @param ADC_SerialChStruct + */ +void ADC_Sqr01ChannelCfg(ADC_SerialChTypeDef *ADC_SerialChStruct) +{ + ASSERT(NULL != ADC_SerialChStruct); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr0Chmux )); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr1Chmux )); + assert_param(IS_ADC_SQR_ENS(ADC_SerialChStruct->ADC_SqrEns )); + + //ADC_SerialChStruct->ADC_SqrEns = ADC_SqrEns01; + REGBITS_MODIFY(CW_ADC->SQR, + ADC_SQR_ENS_Msk | ADC_SQR_SQR0_Msk | ADC_SQR_SQR1_Msk, + ADC_SerialChStruct->ADC_SqrEns |\ + (ADC_SerialChStruct->ADC_Sqr1Chmux << ADC_SQR_SQR1_Pos) |\ + ADC_SerialChStruct->ADC_Sqr0Chmux); + + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr0Chmux); + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr1Chmux); +} + +/** + * @brief + * SQR0~SQR2תͨ + * + * @param ADC_SerialChStruct + */ +void ADC_Sqr02ChannelCfg(ADC_SerialChTypeDef *ADC_SerialChStruct) +{ + ASSERT(NULL != ADC_SerialChStruct); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr0Chmux )); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr1Chmux )); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr2Chmux )); + assert_param(IS_ADC_SQR_ENS(ADC_SerialChStruct->ADC_SqrEns )); + + //ADC_SerialChStruct->ADC_SqrEns = ADC_SqrEns02; + REGBITS_MODIFY(CW_ADC->SQR, + ADC_SQR_ENS_Msk | ADC_SQR_SQR0_Msk |\ + ADC_SQR_SQR1_Msk | ADC_SQR_SQR2_Msk, + ADC_SerialChStruct->ADC_SqrEns |\ + (ADC_SerialChStruct->ADC_Sqr2Chmux << ADC_SQR_SQR2_Pos) |\ + (ADC_SerialChStruct->ADC_Sqr1Chmux << ADC_SQR_SQR1_Pos) |\ + ADC_SerialChStruct->ADC_Sqr0Chmux); + + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr0Chmux); + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr1Chmux); + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr2Chmux); +} + +/** + * @brief + * SQR0~SQR2תͨ + * + * @param ADC_SerialChStruct + */ +void ADC_Sqr03ChannelCfg(ADC_SerialChTypeDef *ADC_SerialChStruct) +{ + ASSERT(NULL != ADC_SerialChStruct); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr0Chmux )); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr1Chmux )); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr2Chmux )); + assert_param(IS_ADC_SQR_CH(ADC_SerialChStruct->ADC_Sqr3Chmux )); + assert_param(IS_ADC_SQR_ENS(ADC_SerialChStruct->ADC_SqrEns )); + + //ADC_SerialChStruct->ADC_SqrEns = ADC_SqrEns03; + REGBITS_MODIFY(CW_ADC->SQR, + ADC_SQR_ENS_Msk | ADC_SQR_SQR0_Msk |\ + ADC_SQR_SQR1_Msk | ADC_SQR_SQR2_Msk | ADC_SQR_SQR3_Msk, + ADC_SerialChStruct->ADC_SqrEns |\ + (ADC_SerialChStruct->ADC_Sqr3Chmux << ADC_SQR_SQR3_Pos) |\ + (ADC_SerialChStruct->ADC_Sqr2Chmux << ADC_SQR_SQR2_Pos) |\ + (ADC_SerialChStruct->ADC_Sqr1Chmux << ADC_SQR_SQR1_Pos) |\ + ADC_SerialChStruct->ADC_Sqr0Chmux); + + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr0Chmux); + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr1Chmux); + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr2Chmux); + ADC_BufEnSerialCh(ADC_SerialChStruct->ADC_Sqr3Chmux); +} + +/** + * @brief + * DMAȡ + * + * @param NewState: + * @arg DISABLE + * @arg ENABLE + */ +void ADC_DMACmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + REGBITS_SET(CW_ADC->CR1, ADC_CR1_DMAEN_Msk); + } + else + { + REGBITS_CLR(CW_ADC->CR1, ADC_CR1_DMAEN_Msk); + } +} + +/** + * @brief + * DMAȡʹ + * + */ +void ADC_DMAEnable(void) +{ + REGBITS_SET(CW_ADC->CR1, ADC_CR1_DMAEN_Msk); +} + +/** + * @brief + * DMAȡֹ + * + */ +void ADC_DMADisable(void) +{ + REGBITS_CLR(CW_ADC->CR1, ADC_CR1_DMAEN_Msk); +} + +/** + * @brief + * ȡתֵ + * + * @param + * + * @return uint16_t + */ +uint16_t ADC_GetConversionValue(void) +{ + return (uint16_t)(CW_ADC->RESULT0); +} + +/** + * @brief + * ȡSQR0ֵͨ + * + * @param pAdcResult + */ +void ADC_GetSqr0Result(uint16_t* pAdcResult) +{ + if (NULL == pAdcResult) + { + return; + } + *pAdcResult = (uint16_t)(CW_ADC->RESULT0); +} + +/** + * @brief + * ȡSQR1ֵͨ + * + * @param pAdcResult + */ +void ADC_GetSqr1Result(uint16_t* pAdcResult) +{ + if (NULL == pAdcResult) + { + return; + } + *pAdcResult = (uint16_t)(CW_ADC->RESULT1); +} + +/** + * @brief + * ȡSQR2ֵͨ + * + * @param pAdcResult + */ +void ADC_GetSqr2Result(uint16_t* pAdcResult) +{ + if (NULL == pAdcResult) + { + return; + } + *pAdcResult = (uint16_t)(CW_ADC->RESULT2); +} + +/** + * @brief + * ȡSQR3ֵͨ + * + * @param pAdcResult + */ +void ADC_GetSqr3Result(uint16_t* pAdcResult) +{ + if (NULL == pAdcResult) + { + return; + } + *pAdcResult = (uint16_t)(CW_ADC->RESULT3); +} + +/** + * @brief + * ȡۼӲֵ + * + * @param pAdcAccResult + */ +void ADC_GetAccResult(uint32_t* pAdcAccResult) +{ + if (NULL == pAdcAccResult) + { + return; + } + + *pAdcAccResult = (uint32_t)(CW_ADC->RESULTACC); +} + +/** + * @brief + * ۼӲֵ + */ +void ADC_ClrAccResult(void) +{ + REGBITS_SET(CW_ADC->CR2, ADC_CR2_ACCRST_Msk); +} + +/** + * @brief + * ADCοѹ + * + * @param ADC_VrefSel: + * @arg ADC_Vref_BGR1p5 + * @arg ADC_Vref_BGR2p5 + * @arg ADC_Vref_Extern1 + * @arg ADC_Vref_VDDA + */ +void ADC_SetVref(uint32_t ADC_VrefSel) +{ + assert_param(IS_ADC_VREF_SEL(ADC_VrefSel )); + + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_REF_Msk, + ADC_VrefSel); +} +/** + * @brief + * ADC뷽ʽ + * + * @param enAlign: + * @arg ADC_AlignRight + * @arg ADC_AlignLeft + */ +void ADC_SetAlign(uint32_t enAlign) +{ + REGBITS_MODIFY(CW_ADC->CR1, ADC_CR1_ALIGN_Msk, enAlign); +} + +/** + * @brief + * õͨADCת + * + * @param enDiscard: + * @arg ADC_DiscardNull + * @arg ADC_DiscardEnable + */ +void ADC_SetDiscard(uint32_t enDiscard) +{ + assert_param(IS_ADC_DATA_DISCARD(enDiscard)); + REGBITS_MODIFY(CW_ADC->CR1, ADC_CR1_DISCARD_Msk, enDiscard); +} + +/** + * @brief + * ¶ȴʹܿ + * + * @param enTs: + * @arg ADC_TsDisable + * @arg ADC_TsEnable + */ +void ADC_SetTs(uint32_t enTs) +{ + assert_param(IS_ADC_TS_ENABLE(enTs)); + REGBITS_MODIFY(CW_ADC->CR0, ADC_CR0_TSEN_Msk, enTs); + +} + +/** + * @brief + * ȡADCοѹ1.5Vʱ¶ȴIJ¶ + * + * @param fAdcTsDegree + */ +void ADC_GetTsVref1V5(float *fAdcTsDegree) +{ + volatile unsigned int u16AdcResult; + unsigned int temp1; + unsigned int temp2; + temp1 = *((uint8_t*) (ADDR_T0)); + temp2 = *((uint16_t*) (ADDR_TRIM_1P5)); + u16AdcResult = ADC_GetConversionValue(); + *fAdcTsDegree = temp1 * 0.5f + COEFF_TS * 1.5f * (u16AdcResult - temp2); +} + +/** + * @brief + * ȡADCοѹ2.5Vʱ¶ȴIJ¶ + * + * @param fAdcTsDegree + */ +void ADC_GetTsVref2V5(float *fAdcTsDegree) +{ + volatile uint16_t u16AdcResult; + uint8_t temp1; + uint16_t temp2; + temp1 = *((uint8_t*) (ADDR_T0)); + temp2 = *((uint16_t*) (ADDR_TRIM_2P5)); + u16AdcResult = ADC_GetConversionValue(); + *fAdcTsDegree = temp1 * 0.5f + COEFF_TS * 2.5f * (u16AdcResult - temp2); +} + +/** + * @brief + * ADCԶֹͣ + * + * @param enAutoStop: + * @arg ADC_AutoStopDisable + * @arg ADC_AutoStopEnable + */ +void ADC_AutoStop(uint32_t enAutoStop) +{ + REGBITS_MODIFY(CW_ADC->START, ADC_START_AUTOSTOP_Msk, enAutoStop); +} + +/** + * @brief + * ADCж + * + * @param ADC_IT: + * @arg ADC_IT_READY + * @arg ADC_IT_OVW + * @arg ADC_IT_WDTR + * @arg ADC_IT_WDTH + * @arg ADC_IT_WDTL + * @arg ADC_IT_EOA + * @arg ADC_IT_EOS + * @arg ADC_IT_EOC + * @param NewState: + * @arg DISABLE + * @arg ENABLE + */ +void ADC_ITConfig(uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itMask = 0; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itMask = (uint8_t) ADC_IT; + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + CW_ADC->IER |= itMask; + } + else + { + /* Disable the selected ADC interrupts */ + CW_ADC->IER &= (~(uint32_t) itMask); + } +} + +/** + * @brief + * ʹNVICADCж + * + * @param intPriority: + * @arg 0 ~ 3 + */ +void ADC_EnableNvic(uint8_t intPriority) +{ + if (intPriority < (1UL << __NVIC_PRIO_BITS)) + { + NVIC_ClearPendingIRQ(ADC_IRQn); + NVIC_EnableIRQ(ADC_IRQn); + NVIC_SetPriority(ADC_IRQn, intPriority); + } +} + +/** + * @brief + * NVICADCж + * + * @param + * + */ +void ADC_DisableNvic(void) +{ + NVIC_ClearPendingIRQ(ADC_IRQn); + NVIC_DisableIRQ(ADC_IRQn); + NVIC_SetPriority(ADC_IRQn, ADC_INT_PRIORITY); +} +//@} // AdcGroup + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_atim.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_atim.c new file mode 100644 index 0000000..ac935b6 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_atim.c @@ -0,0 +1,636 @@ +/** + * @file cw32f030_atim.c + * @author P&S (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-04-29 + * + * @copyright Copyright (c) 2021 + * + */ +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_atim.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ +/** + * @brief ATIMλĴָΪĬֵ + */ +void ATIM_DeInit(void) +{ + CW_SYSCTRL->APBRST2_f.ATIM = 0; + CW_SYSCTRL->APBRST2_f.ATIM = 1; +} + + +/** + * @brief ATIM ʼ + * @param ATIM_InitStruct ATIM_InitTypeDefĶ + */ +void ATIM_Init(ATIM_InitTypeDef *ATIM_InitStruct) +{ + assert_param(IS_ATIM_COUNTING_DIRECTION(ATIM_InitStruct->CounterDirection)); + assert_param(IS_ATIM_OP_MODE(ATIM_InitStruct->CounterOPMode)); + assert_param(IS_ATIM_COUNT_MODE(ATIM_InitStruct->CounterAlignedMode)); + assert_param(IS_ATIM_PRESCALER(ATIM_InitStruct->Prescaler)); + assert_param(IS_ATIM_CLOCK(ATIM_InitStruct->ClockSelect)); + + REGBITS_MODIFY(CW_ATIM->CR, ATIM_CR_DIR_Msk | ATIM_CR_ONESHOT_Msk |\ + ATIM_CR_PRS_Msk | ATIM_CR_MODE_Msk |\ + ATIM_CR_BUFPEN_Msk | ATIM_CR_CT_Msk \ + ,\ + ATIM_InitStruct->CounterDirection | ATIM_InitStruct->CounterOPMode | + ATIM_InitStruct->Prescaler | ATIM_InitStruct->CounterAlignedMode | + (ATIM_InitStruct->BufferState ? ATIM_BUFFER_ENABLE : ATIM_BUFFER_DISABLE) | + ATIM_InitStruct->ClockSelect); + + CW_ATIM->ARR = ATIM_InitStruct->ReloadValue; + + CW_ATIM->RCR = ATIM_InitStruct->RepetitionCounter | (ATIM_InitStruct->OverFlowMask? 1UL<<8 : 0) | \ + (ATIM_InitStruct->UnderFlowMask ? 1UL<<9 : 0); +} + + +/** + * @brief ATIM + * + * @param NewState ENABLE or DISABLE + */ +void ATIM_Cmd(FunctionalState NewState) +{ + CW_ATIM->CR_f.EN = NewState; +} + +/** + * @brief ATIMж + * @param ATIM_IT жԴ + * @param NewState ENABLE DISABLE + */ +void ATIM_ITConfig(uint32_t ATIM_IT, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CW_ATIM->CR |= ATIM_IT; + } + else + { + CW_ATIM->CR &= ~ATIM_IT; + } +} + +/** + * @brief ȡATIMжϱ־λ + * @param ATIM_IT жԴ + * @return ITStatus + */ +ITStatus ATIM_GetITStatus(uint32_t ATIM_IT) +{ + return (CW_ATIM->ISR & ATIM_IT) ? SET : RESET; + +} + +/** + * @brief ATIMжϱ־λ + */ +void ATIM_ClearITPendingBit(uint32_t ATIM_IT) +{ + CW_ATIM->ICR = ~ATIM_IT; +} + +/** + * @brief ATIMֵ + * @param Value + */ +void ATIM_SetReloadValue(uint32_t Value) +{ + CW_ATIM->ARR = Value; +} + +/** + * @brief ͨ1Ĺ + * + * @param Function ATIM_CHxA_BUFF ATIM_CHxA_CIE ATIM_CHxA_CDE + * ATIM_CHxB_BUFF ATIM_CHxB_CIE ATIM_CHxB_CDE + * @param NewState ENABLE DISABLE + */ +void ATIM_CH1Config(uint32_t Function, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CW_ATIM->CH1CR |= Function; + } + else + { + CW_ATIM->CH1CR &= ~(Function); + } +} + +/** + * @brief ͨ2Ĺ + * + * @param Function ATIM_CHxA_BUFF ATIM_CHxA_CIE ATIM_CHxA_CDE + * ATIM_CHxB_BUFF ATIM_CHxB_CIE ATIM_CHxB_CDE + * @param NewState ENABLE DISABLE + */ +void ATIM_CH2Config(uint32_t Function, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CW_ATIM->CH2CR |= Function; + } + else + { + CW_ATIM->CH2CR &= ~(Function); + } +} + +/** + * @brief ͨ3Ĺ + * + * @param Function ATIM_CHxA_BUFF ATIM_CHxA_CIE ATIM_CHxA_CDE + * ATIM_CHxB_BUFF ATIM_CHxB_CIE ATIM_CHxB_CDE + * @param NewState ENABLE DISABLE + */ +void ATIM_CH3Config(uint32_t Function, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CW_ATIM->CH3CR |= Function; + } + else + { + CW_ATIM->CH3CR &= ~(Function); + } +} + +/** + * @brief ͨ4Ĺ + * + * @param Function ATIM_CH4_BUFF ATIM_CH4_CIE ATIM_CH4_CDE * + * @param NewState ENABLE DISABLE + */ +void ATIM_CH4Config(uint32_t Function, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CW_ATIM->CH4CR |= Function; + } + else + { + CW_ATIM->CH4CR &= ~(Function); + } +} + +/** + * @brief 벶ͨ1A + * @param ATIM_ICInitStruct + */ +void ATIM_IC1AInit(ATIM_ICInitTypeDef* ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + REGBITS_MODIFY(CW_ATIM->CH1CR, (ATIM_CH1CR_BKSA_Msk | ATIM_CH1CR_CSA_Msk), + (ATIM_ICInitStruct->ICPolarity | ATIM_CH_A_IC)); + CW_ATIM->FLTR_f.OCM1AFLT1A = ATIM_ICInitStruct->ICFilter; +} + +/** + * @brief 벶ͨ1B + * @param ATIM_ICInitStruct + */ +void ATIM_IC1BInit(ATIM_ICInitTypeDef* ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + + REGBITS_MODIFY(CW_ATIM->CH1CR, (ATIM_CH1CR_BKSB_Msk | ATIM_CH1CR_CSB_Msk), + (ATIM_ICInitStruct->ICPolarity << 2 | ATIM_CH_B_IC)); + CW_ATIM->FLTR_f.OCM1BFLT1B = ATIM_ICInitStruct->ICFilter; +} + + +/** + * @brief 벶ͨ2A + * @param ATIM_ICInitStruct + */ +void ATIM_IC2AInit(ATIM_ICInitTypeDef* ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + + REGBITS_MODIFY(CW_ATIM->CH2CR, (ATIM_CH2CR_BKSA_Msk | ATIM_CH2CR_CSA_Msk), + (ATIM_ICInitStruct->ICPolarity | ATIM_CH_A_IC)); + CW_ATIM->FLTR_f.OCM2AFLT2A = ATIM_ICInitStruct->ICFilter; +} + +/** + * @brief 벶ͨ2B + * @param ATIM_ICInitStruct + */ +void ATIM_IC2BInit(ATIM_ICInitTypeDef* ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + + REGBITS_MODIFY(CW_ATIM->CH2CR, (ATIM_CH2CR_BKSB_Msk | ATIM_CH2CR_CSB_Msk), + (ATIM_ICInitStruct->ICPolarity << 2 | ATIM_CH_B_IC)); + CW_ATIM->FLTR_f.OCM2BFLT2B = ATIM_ICInitStruct->ICFilter; +} + +/** + * @brief 벶ͨ3A + * @param ATIM_ICInitStruct + */ +void ATIM_IC3AInit(ATIM_ICInitTypeDef* ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + + REGBITS_MODIFY(CW_ATIM->CH3CR, (ATIM_CH3CR_BKSA_Msk | ATIM_CH3CR_CSA_Msk), + (ATIM_ICInitStruct->ICPolarity | ATIM_CH_A_IC)); + CW_ATIM->FLTR_f.OCM3AFLT3A = ATIM_ICInitStruct->ICFilter; +} + +/** + * @brief 벶ͨ3B + * @param ATIM_ICInitStruct + */ +void ATIM_IC3BInit(ATIM_ICInitTypeDef* ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + + REGBITS_MODIFY(CW_ATIM->CH3CR, (ATIM_CH3CR_BKSB_Msk | ATIM_CH3CR_CSB_Msk), + (ATIM_ICInitStruct->ICPolarity << 2 | ATIM_CH_B_IC)); + CW_ATIM->FLTR_f.OCM3BFLT3B = ATIM_ICInitStruct->ICFilter; +} + +/** + * @brief CH1AȽ + * @param ATIM_OCInitStruct + */ +void ATIM_OC1AInit(ATIM_OCInitTypeDef * ATIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_MODE(ATIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_POLARITY(ATIM_OCInitStruct->OCPolarity)); + assert_param(IS_ATIM_OC_IT(ATIM_OCInitStruct->OCInterruptSelect)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->BufferState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCDMAState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCInterruptState)); + + REGBITS_MODIFY(CW_ATIM->FLTR, ATIM_FLTR_OCM1AFLT1A_Msk | ATIM_FLTR_CCP1A_Msk, + ATIM_OCInitStruct->OCMode | (ATIM_OCInitStruct->OCPolarity << 3)); + CW_ATIM->CR_f.CISA = ATIM_OCInitStruct->OCInterruptSelect; + REGBITS_MODIFY(CW_ATIM->CH1CR, ATIM_CH1CR_BUFEA_Msk | ATIM_CH1CR_CDEA_Msk | ATIM_CH1CR_CIEA_Msk, + (ATIM_OCInitStruct->BufferState ? ATIM_CH1CR_BUFEA_Msk:0)|\ + (ATIM_OCInitStruct->OCDMAState ? ATIM_CH1CR_CDEA_Msk:0) |\ + (ATIM_OCInitStruct->OCInterruptState ? ATIM_CH1CR_CIEA_Msk:0)); +} + +/** + * @brief CH1BȽ + * @param ATIM_OCInitStruct + */ +void ATIM_OC1BInit(ATIM_OCInitTypeDef * ATIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_MODE(ATIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_POLARITY(ATIM_OCInitStruct->OCPolarity)); + assert_param(IS_ATIM_OC_IT(ATIM_OCInitStruct->OCInterruptSelect)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->BufferState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCDMAState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCInterruptState)); + + REGBITS_MODIFY(CW_ATIM->FLTR, ATIM_FLTR_OCM1BFLT1B_Msk | ATIM_FLTR_CCP1B_Msk, + (ATIM_OCInitStruct->OCMode << 4) | (ATIM_OCInitStruct->OCPolarity << 7)); + + + REGBITS_MODIFY(CW_ATIM->CH1CR, ATIM_CH1CR_CISB_Msk | ATIM_CH1CR_BUFEB_Msk | ATIM_CH1CR_CDEB_Msk | ATIM_CH1CR_CIEB_Msk, + (ATIM_OCInitStruct->OCInterruptSelect << 12) | \ + (ATIM_OCInitStruct->BufferState ? ATIM_CH1CR_BUFEB_Msk:0)|\ + (ATIM_OCInitStruct->OCDMAState ? ATIM_CH1CR_CDEB_Msk:0) |\ + (ATIM_OCInitStruct->OCInterruptState ? ATIM_CH1CR_CIEB_Msk:0)); +} + +/** + * @brief CH2AȽ + * @param ATIM_OCInitStruct + */ +void ATIM_OC2AInit(ATIM_OCInitTypeDef * ATIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_MODE(ATIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_POLARITY(ATIM_OCInitStruct->OCPolarity)); + + REGBITS_MODIFY(CW_ATIM->FLTR, ATIM_FLTR_OCM2AFLT2A_Msk | ATIM_FLTR_CCP2A_Msk, + (ATIM_OCInitStruct->OCMode << 8) | (ATIM_OCInitStruct->OCPolarity << 11)); + + CW_ATIM->CR_f.CISA = ATIM_OCInitStruct->OCInterruptSelect; + REGBITS_MODIFY(CW_ATIM->CH2CR, ATIM_CH2CR_BUFEA_Msk | ATIM_CH2CR_CDEA_Msk | ATIM_CH2CR_CIEA_Msk, + (ATIM_OCInitStruct->BufferState ? ATIM_CH2CR_BUFEA_Msk:0)|\ + (ATIM_OCInitStruct->OCDMAState ? ATIM_CH2CR_CDEA_Msk:0) |\ + (ATIM_OCInitStruct->OCInterruptState ? ATIM_CH2CR_CIEA_Msk:0)); +} + +/** + * @brief CH2BȽ + * @param ATIM_OCInitStruct + */ +void ATIM_OC2BInit(ATIM_OCInitTypeDef * ATIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_MODE(ATIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_POLARITY(ATIM_OCInitStruct->OCPolarity)); + assert_param(IS_ATIM_OC_IT(ATIM_OCInitStruct->OCInterruptSelect)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->BufferState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCDMAState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCInterruptState)); + + REGBITS_MODIFY(CW_ATIM->FLTR, ATIM_FLTR_OCM2BFLT2B_Msk | ATIM_FLTR_CCP2B_Msk, + (ATIM_OCInitStruct->OCMode << 12) | (ATIM_OCInitStruct->OCPolarity << 15)); + + REGBITS_MODIFY(CW_ATIM->CH2CR, ATIM_CH2CR_CISB_Msk | ATIM_CH2CR_BUFEB_Msk | ATIM_CH2CR_CDEB_Msk | ATIM_CH1CR_CIEB_Msk, + (ATIM_OCInitStruct->OCInterruptSelect << 12) | \ + (ATIM_OCInitStruct->BufferState ? ATIM_CH2CR_BUFEB_Msk:0)|\ + (ATIM_OCInitStruct->OCDMAState ? ATIM_CH2CR_CDEB_Msk:0) |\ + (ATIM_OCInitStruct->OCInterruptState ? ATIM_CH2CR_CIEB_Msk:0)); +} + +/** + * @brief CH3AȽ + * @param ATIM_OCInitStruct + */ +void ATIM_OC3AInit(ATIM_OCInitTypeDef * ATIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_MODE(ATIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_POLARITY(ATIM_OCInitStruct->OCPolarity)); + assert_param(IS_ATIM_OC_IT(ATIM_OCInitStruct->OCInterruptSelect)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->BufferState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCDMAState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCInterruptState)); + + REGBITS_MODIFY(CW_ATIM->FLTR, ATIM_FLTR_OCM3AFLT3A_Msk | ATIM_FLTR_CCP3A_Msk, + (ATIM_OCInitStruct->OCMode << 16) | (ATIM_OCInitStruct->OCPolarity << 19)); + + CW_ATIM->CR_f.CISA = ATIM_OCInitStruct->OCInterruptSelect; + REGBITS_MODIFY(CW_ATIM->CH3CR, ATIM_CH3CR_BUFEA_Msk | ATIM_CH3CR_CDEA_Msk | ATIM_CH3CR_CIEA_Msk, + (ATIM_OCInitStruct->BufferState ? ATIM_CH3CR_BUFEA_Msk:0)|\ + (ATIM_OCInitStruct->OCDMAState ? ATIM_CH3CR_CDEA_Msk:0) |\ + (ATIM_OCInitStruct->OCInterruptState ? ATIM_CH3CR_CIEA_Msk:0)); +} + +/** + * @brief CH3BȽ + * @param ATIM_OCInitStruct + */ +void ATIM_OC3BInit(ATIM_OCInitTypeDef * ATIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_MODE(ATIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_POLARITY(ATIM_OCInitStruct->OCPolarity)); + assert_param(IS_ATIM_OC_IT(ATIM_OCInitStruct->OCInterruptSelect)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->BufferState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCDMAState)); + assert_param(IS_FUNCTIONAL_STATE(ATIM_OCInitStruct->OCInterruptState)); + + REGBITS_MODIFY(CW_ATIM->FLTR, ATIM_FLTR_OCM3BFLT3B_Msk | ATIM_FLTR_CCP3B_Msk, + (ATIM_OCInitStruct->OCMode << 20) | (ATIM_OCInitStruct->OCPolarity << 23)); + + REGBITS_MODIFY(CW_ATIM->CH3CR, ATIM_CH3CR_CISB_Msk | ATIM_CH3CR_BUFEB_Msk | ATIM_CH3CR_CDEB_Msk | ATIM_CH1CR_CIEB_Msk, + (ATIM_OCInitStruct->OCInterruptSelect << 12) | \ + (ATIM_OCInitStruct->BufferState ? ATIM_CH3CR_BUFEB_Msk:0)|\ + (ATIM_OCInitStruct->OCDMAState ? ATIM_CH3CR_CDEB_Msk:0) |\ + (ATIM_OCInitStruct->OCInterruptState ? ATIM_CH3CR_CIEB_Msk:0)); +} + + +/** + * @brief ͨ4ıȽ + * @param NewState ͨȽʹ + * @param ITSelect жϲѡ񣬲Ϊв֮һ + * @arg ATIM_OC_IT_NONE + * @arg ATIM_OC_IT_UP_COUNTER + * @arg ATIM_OC_IT_DOWN_COUNTER + * @arg ATIM_OC_IT_BOTH_COUNTER + * @param DMAState ȽϴDMAʹ + * @param ITState Ƚϴжʹ + * @param BufferState Ƚϻʹܿ + */ +void ATIM_OC4Init(FunctionalState NewState, uint32_t ITSelect, FunctionalState DMAState, + FunctionalState ITState, FunctionalState BufferState) +{ + assert_param(IS_ATIM_OC_IT(ITSelect)); + + CW_ATIM->CH4CR = (NewState ? 1UL << 5 :0 ) | (ITSelect << 3) | (DMAState ? 1UL << 2 : 0) | \ + (ITState ? 1UL << 1 : 0) | (BufferState ? 1 : 0); + +} + +/** + * @brief PWMIJ + * + * @param OCREFAType ȽAȽϻ˫Ƚ OCREFA_TYPE_SINGLE OCREFA_TYPE_DOUBLE + * @param OutputType PWMͶ򻥲 OUTPUT_TYPE_ALONE OUTPUT_TYPE_COMP + * @param Deadtime ʱ䣬λΪʱļʱ϶-1ֹ 0~0xFFʱ϶ + * ȡֵΧ + */ +void ATIM_PWMOutputConfig(uint32_t OCREFAType, uint32_t OutputType, int16_t Deadtime) +{ + assert_param(IS_ATIM_OCREFA_TYPE(OCREFAType)); + assert_param(IS_ATIM_OUTPUT_TYPE(OutputType)); + assert_param(IS_ATIM_DEADTIME(Deadtime)); + + REGBITS_MODIFY(CW_ATIM->CR, ATIM_CR_COMP_Msk | ATIM_CR_PWM2S_Msk, OCREFAType | OutputType); + if (Deadtime >= 0 ) + { + CW_ATIM->DTR_f.DTEN = 1; + CW_ATIM->DTR_f.DTR = Deadtime; + } + else + { + CW_ATIM->DTR_f.DTEN = 0; + } +} + +void ATIM_CtrlPWMOutputs(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + CW_ATIM->DTR_f.MOE = NewState; +} + +/** + * @brief ⲿ + * @param ATIM_ETRPolarity ⲿźЧ Ϊв֮һ + * @arg ATIM_ETR_POLARITY_NONINVERT: ͬ + * @arg ATIM_ETR_POLARITY_INVERT: + * @param ETRFilter ⲿͨ˲ Ϊв֮һ + * @arg ATIM_ETR_FILTER_NONE: ˲ + * @arg ATIM_ETR_FILTER_PCLK_N3: PCLKʱӲ3Ч + * @arg ATIM_ETR_FILTER_PCLKDIV4_N3: PCLK/4ʱӲ3Ч + * @arg ATIM_ETR_FILTER_PCLKDIV16_N3: PCLK/16ʱӲ3Ч + * @arg ATIM_ETR_FILTER_PCLKDIV64_N3: PCLK/64ʱӲ3Ч + */ +void ATIM_ETRConfig(uint32_t ATIM_ETRPolarity, uint32_t ATIM_ETRFilter) +{ + assert_param(IS_ATIM_ETR_POLARITY(ATIM_ETRPolarity)); + assert_param(IS_ATIM_ETR_FILTER(ATIM_ETRFilter)); + + REGBITS_MODIFY(CW_ATIM->FLTR, + ATIM_FLTR_ETP_Msk | ATIM_FLTR_FLTET_Msk, + ATIM_ETRPolarity | ATIM_ETRFilter); +} + +/** + * @brief BrakeźŵIJ + * @param ATIM_BrakePolarity źżԣΪв֮һ + * @arg ATIM_BRAKE_POLARITY_NONINVERT: ͬ + * @arg ATIM_BRAKE_POLARITY_INVERT: + * @param ATIM_BrakeFilter + * @arg ATIM_BRAKE_FILTER_NONE: ˲ + * @arg ATIM_BRAKE_FILTER_PCLK_N3: PCLKʱӲ3Ч + * @arg ATIM_BRAKE_FILTER_PCLKDIV4_N3: PCLK/4ʱӲ3Ч + * @arg ATIM_BRAKE_FILTER_PCLKDIV16_N3: PCLK/16ʱӲ3Ч + * @arg ATIM_BRAKE_FILTER_PCLKDIV64_N3: PCLK/64ʱӲ3Ч + */ +void ATIM_BrakeConfig(uint32_t ATIM_BrakePolarity, uint32_t ATIM_BrakeFilter) +{ + assert_param(IS_ATIM_BRAKE_POLARITY(ATIM_BrakePolarity)); + assert_param(IS_ATIM_BRAKE_FILTER(ATIM_BrakeFilter)); + + REGBITS_MODIFY(CW_ATIM->FLTR, + ATIM_FLTR_BKP_Msk | ATIM_FLTR_FLTBK_Msk, + ATIM_BrakePolarity | ATIM_BrakeFilter); +} + +/** + * @brief ATIMADCIJĴԴ + * @param ATIM_ADCTriggerSource Ϊв֮һ + * @arg ATIM_ADC_TRIGGER_CH3B + * @arg ATIM_ADC_TRIGGER_CH2B + * @arg ATIM_ADC_TRIGGER_CH1B + * @arg ATIM_ADC_TRIGGER_CH3A + * @arg ATIM_ADC_TRIGGER_CH2A + * @arg ATIM_ADC_TRIGGER_CH1A + * @arg ATIM_ADC_TRIGGER_UPDATA_EVENT + * @param NewState DISABLEENABLE + */ +void ATIM_ADCTriggerConfig(uint32_t ATIM_ADCTriggerSource, FunctionalState NewState) +{ + assert_param(IS_ATIM_ADC_TRIGGER(ATIM_ADCTriggerSource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + + CW_ATIM->TRIG |= (ATIM_ADCTriggerSource | ATIM_ADC_TRIGGER_GLOBAL); + } + else + { + CW_ATIM->TRIG &= ~ATIM_ADCTriggerSource; + } +} + +uint16_t ATIM_GetCapture1A(void) +{ + return (uint16_t) CW_ATIM->CH1CCRA; +} + + +uint16_t ATIM_GetCapture2A(void) +{ + return (uint16_t) CW_ATIM->CH2CCRA; +} + + +uint16_t ATIM_GetCapture3A(void) +{ + return (uint16_t) CW_ATIM->CH3CCRA; +} + + +uint16_t ATIM_GetCapture1B(void) +{ + return (uint16_t) CW_ATIM->CH1CCRB; +} + + +uint16_t ATIM_GetCapture2B(void) +{ + return (uint16_t) CW_ATIM->CH2CCRB; +} + + +uint16_t ATIM_GetCapture3B(void) +{ + return (uint16_t) CW_ATIM->CH3CCRB; +} + + +void ATIM_SetCompare1A(uint16_t Compare) +{ + CW_ATIM->CH1CCRA = (uint32_t)Compare; +} + +void ATIM_SetCompare2A(uint16_t Compare) +{ + CW_ATIM->CH2CCRA = (uint32_t)Compare; +} + +void ATIM_SetCompare3A(uint16_t Compare) +{ + CW_ATIM->CH3CCRA = (uint32_t)Compare; +} + +void ATIM_SetCompare1B(uint16_t Compare) +{ + CW_ATIM->CH1CCRB = (uint32_t)Compare; +} + +void ATIM_SetCompare2B(uint16_t Compare) +{ + CW_ATIM->CH2CCRB = (uint32_t)Compare; +} + +void ATIM_SetCompare3B(uint16_t Compare) +{ + CW_ATIM->CH3CCRB = (uint32_t)Compare; +} + +void ATIM_SetCompare4(uint16_t Compare) +{ + CW_ATIM->CH4CCR = (uint32_t) Compare; +} + +void ATIM_MasterModeConfig(uint8_t ATIM_MasterOutput) +{ + assert_param(IS_ATIM_MASTER_OUTPUT(ATIM_MasterOutput)); + + CW_ATIM->MSCR_f.MMS = ATIM_MasterOutput; +} + +void ATIM_SlaverModeConfig(uint8_t ATIM_SlaverType) +{ + assert_param(IS_ATIM_SLAVER_TYPE(ATIM_SlaverType)); + + CW_ATIM->MSCR_f.SMS = ATIM_SlaverType; +} + +void ATIM_TriggerSelect(uint8_t ATIM_TriggerSource) +{ + assert_param(IS_ATIM_TRIGGER_SOURCE(ATIM_TriggerSource)); + + CW_ATIM->MSCR_f.TS = ATIM_TriggerSource; +} + +void ATIM_UpdateEventSelect(uint8_t ATIM_UpdateEvent) +{ + assert_param(IS_ATIM_UPDATE_EVENT(ATIM_UpdateEvent)); + + CW_ATIM->CR_f.URS = ATIM_UpdateEvent; +} diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_awt.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_awt.c new file mode 100644 index 0000000..ee482ce --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_awt.c @@ -0,0 +1,224 @@ +/** + * @file cw32f030_awt.c + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-18 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_awt.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief AWT ȥʼ + * + */ +void AWT_DeInit(void) +{ + CW_AWT->CR = 0UL; + CW_AWT->ARR = 0x0000FFFFUL; + CW_AWT->IER = 0UL; + CW_AWT->ICR = 0UL; +} + +/** + * @brief AWTʱʼ + * + * @param AWT_TimeCntInitStruct + */ +void AWT_TimeCntInit(AWT_TimeCntInitTypeDef* AWT_TimeCntInitStruct) +{ + assert_param(IS_AWT_CLKSOURCE(AWT_TimeCntInitStruct->AWT_ClkSource)); + assert_param(IS_AWT_PRS_DIV(AWT_TimeCntInitStruct->AWT_Prescaler)); + assert_param(IS_AWT_ARR(AWT_TimeCntInitStruct->AWT_Period)); + assert_param(IS_AWT_MODE(AWT_TimeCntInitStruct->AWT_Mode)); + + REGBITS_MODIFY(CW_AWT->CR, AWT_CR_SRC_Msk |\ + AWT_CR_PRS_Msk |\ + AWT_CR_MD_Msk + ,\ + AWT_TimeCntInitStruct->AWT_ClkSource |\ + AWT_TimeCntInitStruct->AWT_Prescaler |\ + AWT_TimeCntInitStruct->AWT_Mode); + + CW_AWT->ARR = AWT_TimeCntInitStruct->AWT_Period; +} + +/** + * @brief ṹAWT_TimeCntInitStructʼ + * + * @param AWT_TimeCntInitStruct + */ +void AWT_TimeCntStructInit(AWT_TimeCntInitTypeDef * AWT_TimeCntInitStruct) +{ + AWT_TimeCntInitStruct->AWT_ClkSource = AWT_CLKSOURCE_HSIOSC; + AWT_TimeCntInitStruct->AWT_Prescaler = AWT_PRS_DIV2; + AWT_TimeCntInitStruct->AWT_Mode = AWT_MODE_TIMECNT; + AWT_TimeCntInitStruct->AWT_Period = (uint32_t)0x0000FFFF; +} + +/** + * @brief ʹAWTʱ + * + * @param NewState + */ +void AWT_Cmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + CW_AWT->CR |= AWT_CR_EN; + } + else + { + CW_AWT->CR &= (~AWT_CR_EN); + } + +} + +/** + * @brief AWTж + * + * @param AWT_IT + * @param NewState + */ +void AWT_ITConfig(uint32_t AWT_IT, FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_AWT_IT(AWT_IT)); + + if (NewState != DISABLE) + { + CW_AWT->IER |= AWT_IT; + } + else + { + CW_AWT->IER &= (~AWT_IT); + } +} + + +/** + * @brief ȡAWTжϱ־ + * + * @param AWT_IT + * @return FlagStatus + */ +FlagStatus AWT_GetITStatus(uint32_t AWT_IT) +{ + assert_param(IS_AWT_IT(AWT_IT)); + + return (CW_AWT->ISR & AWT_IT) ? SET : RESET; +} + +/** + * @brief AWTжϱ־ + * + * @param AWT_IT + */ +void AWT_ClearITPendingBit(uint32_t AWT_IT) +{ + assert_param(IS_AWT_IT(AWT_IT)); + + CW_AWT->ICR &= (~AWT_IT); + +} + +/** + * @brief AWTʱԴ + * + * @param AWT_ClkSrouce + */ +void AWT_ClkSourceConfig(uint32_t AWT_ClkSource) +{ + assert_param(IS_AWT_CLKSOURCE(AWT_ClkSource)); + + REGBITS_MODIFY(CW_AWT->CR, AWT_CR_SRC_Msk, AWT_ClkSource); +} + +/** + * @brief AWTʱӷƵϵ + * + * @param Prescaler + */ +void AWT_PrescalerConfig(uint32_t AWT_Prescaler) +{ + assert_param(IS_AWT_PRS_DIV(AWT_Prescaler)); + + REGBITS_MODIFY(CW_AWT->CR, AWT_CR_PRS_Msk, AWT_Prescaler); +} + +/** + * @brief ȡAWTCNTĴֵ + * + * @return uint16_t + */ +uint16_t AWT_GetCounter(void) +{ + return (uint16_t)(CW_AWT->CNT); +} + +/** + * @brief ȡAWTֵĴARRֵ + * + * @return uint16_t + */ +uint16_t AWT_GetAutoreload(void) +{ + return (uint16_t)(CW_AWT->ARR); +} + +/** + * @brief ȡAWTʱԴ + * + * @return uint32_t + */ +uint32_t AWT_GetClkSource(void) +{ + return (uint32_t)((CW_AWT->CR_f.SRC) ); +} + +/** + * @brief ȡAWTʱӷƵϵ + * + * @return uint32_t + */ +uint32_t AWT_GetPrescaler(void) +{ + return (uint32_t)((CW_AWT->CR_f.PRS) ); +} + + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_btim.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_btim.c new file mode 100644 index 0000000..392ba28 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_btim.c @@ -0,0 +1,354 @@ +/** + * @file cw32f030_btim.c + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-04-22 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_btim.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/******************************************************************************* +// ˵ȥʼ +// BTIMx xΪ1~3 +// ֵ +*******************************************************************************/ + +void BTIM_DeInit(BTIM_TypeDef* BTIMx) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + + BTIMx->BCR = 0UL; + BTIMx->ARR = 0x0000FFFF; + BTIMx->CNT = 0UL; + BTIMx->ACR = 0UL; + BTIMx->IER = 0UL; + BTIMx->ICR = 0UL; + BTIMx->DMA = 0UL; +} + +/******************************************************************************* +// ˵BTIMʱʼ +// BTIMx CW_BTIM1~3 +// BTIM_TimeBaseInitStruct ָBTIM_TimeBaseInitTypeDefͽṹָ +// ֵ +*******************************************************************************/ +void BTIM_TimeBaseInit(BTIM_TypeDef* BTIMx, BTIM_TimeBaseInitTypeDef* BTIM_TimeBaseInitStruct) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_MODE(BTIM_TimeBaseInitStruct->BTIM_Mode)); + assert_param(IS_BTIM_PRS_DIV(BTIM_TimeBaseInitStruct->BTIM_Prescaler)); + REGBITS_MODIFY(BTIMx->BCR, BTIMx_BCR_MODE_Msk| BTIMx_BCR_PRS_Msk | BTIMx_BCR_ONESHOT_Msk, + BTIM_TimeBaseInitStruct->BTIM_Mode | BTIM_TimeBaseInitStruct->BTIM_Prescaler | + BTIM_TimeBaseInitStruct->BTIM_OPMode); + BTIMx->ARR = BTIM_TimeBaseInitStruct->BTIM_Period; +} + +/******************************************************************************* +// ˵ṹBTIM_TimeBaseInitStructʼ +// BTIM_TimeBaseInitStruct +// ֵ +*******************************************************************************/ + +void BTIM_TimeBaseStructInit(BTIM_TimeBaseInitTypeDef* BTIM_TimeBaseInitStruct) +{ + BTIM_TimeBaseInitStruct->BTIM_Prescaler = BTIM_PRS_DIV1; + BTIM_TimeBaseInitStruct->BTIM_Mode = BTIM_Mode_TIMER; + BTIM_TimeBaseInitStruct->BTIM_Period = 0xFFFF; +} + +/******************************************************************************* +// ˵ʹBTIMxʱ +// BTIM_TimeBaseInitStruct +// ֵ +*******************************************************************************/ +void BTIM_Cmd(BTIM_TypeDef* BTIMx, FunctionalState NewState) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + NewState ? (BTIMx->BCR |= BTIMx_BCR_EN_Msk) : (BTIMx->BCR &= ~BTIMx_BCR_EN_Msk); +} + + +/******************************************************************************* +// ˵BTIMxж +// BTIMx CW_BTIM1~3 +// BTIM_IT ж¼ +// NewState ж¼͵״̬ENABLE DISABLE +// ֵ +*******************************************************************************/ +void BTIM_ITConfig(BTIM_TypeDef* BTIMx, uint16_t BTIM_IT, FunctionalState NewState) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_BTIM_IT(BTIM_IT)); + + NewState ? ( BTIMx->IER |= BTIM_IT) : (BTIMx->IER &= ~BTIM_IT); +} + + +/******************************************************************************* +// ˵BTIMxDMA +// BTIMx CW_BTIM1~3 +// BTIM_DMASource DMA¼ +// NewState ж¼͵״̬ENABLE DISABLE +// ֵ +*******************************************************************************/ +void BTIM_DMACmd(BTIM_TypeDef* BTIMx, uint16_t BTIM_DMASource, FunctionalState NewState) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_BTIM_DMA_SOURCE(BTIM_DMASource)); + + NewState ? (BTIMx->DMA |= BTIM_DMASource) : (BTIMx->DMA &= ~BTIM_DMASource); +} + +/******************************************************************************* +// ˵BTIMxԤϵ +// BTIMx CW_BTIM1~3 +// Prescaler Ԥϵ +// BTIM_PSCReloadMode Ԥϵ»ʱ,ȡֵΧ +// BTIM_PSCReloadMode_Update Ԥϵʱ +// BTIM_PSCReloadMode_Immediate Ԥϵ +// ֵ +*******************************************************************************/ +void BTIM_PrescalerConfig(BTIM_TypeDef* BTIMx, uint16_t Prescaler, uint16_t BTIM_PSCReloadMode) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_PRS_DIV(Prescaler)); + assert_param(IS_BTIM_PRESCALER_RELOAD(BTIM_PSCReloadMode)); + + REGBITS_MODIFY(BTIMx->BCR, BTIMx_BCR_PRS_Msk, Prescaler); + + if (BTIM_PSCReloadMode ==BTIM_PSCReloadMode_Immediate) + { + BTIMx->BCR &= ~BTIMx_BCR_EN_Msk; + BTIMx->BCR |= BTIMx_BCR_EN_Msk; + } +} + +/******************************************************************************* +// ˵BTIMxĹģʽ +// BTIMx CW_BTIM1~3 +// BTIM_Mode ģʽ +// BTIM_Mode_TIMER ʱģʽ +// BTIM_Mode_COUNTER ģʽ +// BTIM_Mode_TRIGGER ģʽ +// BTIM_Mode_GATE ſģʽ +// ֵ +*******************************************************************************/ +void BTIM_ModeConfig(BTIM_TypeDef* BTIMx, uint16_t BTIM_Mode) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_MODE(BTIM_Mode)); + + REGBITS_MODIFY(BTIMx->BCR, BTIMx_BCR_MODE_Msk, BTIM_Mode); +} + +/******************************************************************************* +// ˵BTIMxĴźԴ +// BTIMx CW_BTIM1~3 +// BTIM_InputTriggerSource Դ +// BTIM_TS_ITR ڲITRź +// BTIM_TS_ETR ⲿETRź +// ֵ +*******************************************************************************/ +void BTIM_SelectInputTrigger(BTIM_TypeDef* BTIMx, uint16_t BTIM_InputTriggerSource) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_TRIGGER_SELECTION(BTIM_InputTriggerSource)); + + REGBITS_MODIFY(BTIMx->BCR, BTIMx_BCR_TRS_Msk, BTIM_InputTriggerSource); +} + +/******************************************************************************* +// ˵BTIMxⲿETRźŵļ +// BTIMx CW_BTIM1~3 +// BTIM_ETR_Polarity +// BTIM_ETR_Polarity_Positive +// BTIM_ETR_Polarity_Negative +// ֵ +*******************************************************************************/ +void BTIM_SelectETRInputPolarity(BTIM_TypeDef* BTIMx, uint16_t BTIM_ETR_Polarity) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_ETR_POLARITY(BTIM_ETR_Polarity)); + + REGBITS_MODIFY(BTIMx->BCR, BTIMx_BCR_POL_Msk, BTIM_ETR_Polarity); +} + +/******************************************************************************* +// ˵BTIMxĵģʽ +// BTIMx CW_BTIM1~3 +// BTIM_OPMode +// BTIM_OPMode_Single +// BTIM_OPMode_Repetitive +// ֵ +*******************************************************************************/ +void BTIM_SelectOnePulseMode(BTIM_TypeDef* BTIMx, uint16_t BTIM_OPMode) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_OPM_MODE(BTIM_OPMode)); + + REGBITS_MODIFY(BTIMx->BCR, BTIMx_BCR_ONESHOT_Msk, BTIM_OPMode); +} + +/******************************************************************************* +// ˵BTIMxķת +// BTIMx CW_BTIM1~3 +// NewState ENABLE DISABLE +// ֵ +*******************************************************************************/ +void BTIM_OutputToggleCmd(BTIM_TypeDef* BTIMx, FunctionalState NewState) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + NewState ? (BTIMx->BCR |= BTIMx_BCR_TOGEN_Msk) : (BTIMx->BCR &= ~BTIMx_BCR_TOGEN_Msk); +} + +/******************************************************************************* +// ˵BTIMxⲿETR +// BTIMx CW_BTIM1~3 +// BTIM_ExtTRGPolarity ETRźŵļ BTIM_ETR_Polarity_Positive +// BTIM_ETR_Polarity_Negative +// ExtTRGFilter ETR˲ +// ֵ +*******************************************************************************/ +void BTIM_ETRConfig(BTIM_TypeDef* BTIMx, uint16_t BTIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_ETR_POLARITY(BTIM_ExtTRGPolarity)); + assert_param(IS_BTIM_EXT_FILTER(ExtTRGFilter)); + + REGBITS_MODIFY(BTIMx->BCR, BTIMx_BCR_POL_Msk, BTIM_ExtTRGPolarity); + REGBITS_MODIFY(BTIMx->ACR, BTIMx_ACR_ETRFLT_Msk, ExtTRGFilter); +} + +/******************************************************************************* +// ˵BTIMļֵ +// BTIMx CW_BTIM1~3 +// Counter Χ0x0000~0xFFFF +// ֵ +*******************************************************************************/ +void BTIM_SetCounter(BTIM_TypeDef* BTIMx, uint16_t Counter) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + + BTIMx->CNT = Counter; +} + +/******************************************************************************* +// ˵BTIMԶֵ +// BTIMx CW_BTIM1~3 +// Autoreload Χ0x0000~0xFFFF +// ֵ +*******************************************************************************/ +void BTIM_SetAutoreload(BTIM_TypeDef* BTIMx, uint16_t Autoreload) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + + BTIMx->ARR = Autoreload; +} + +/******************************************************************************* +// ˵ȡBTIMĵǰֵ +// BTIMx CW_BTIM1~3 +// ֵCNTĴֵ +*******************************************************************************/ +uint16_t BTIM_GetCounter(BTIM_TypeDef* BTIMx) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + + return BTIMx->CNT; +} + +/******************************************************************************* +// ˵ȡBTIMĵǰԶֵ +// BTIMx CW_BTIM1~3 +// ֵARRĴֵ +*******************************************************************************/ +uint16_t BTIM_GetAutoreload(BTIM_TypeDef* BTIMx) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + + return BTIMx->ARR; +} + +/******************************************************************************* +// ˵ȡBTIMĵǰԤϵ +// BTIMx CW_BTIM1~3 +// ֵԤƵǰʹõķƵϵ +*******************************************************************************/ +uint16_t BTIM_GetPrescaler(BTIM_TypeDef* BTIMx) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + + return BTIMx->BCR_f.PRSSTATUS; +} +/******************************************************************************* +// ˵ BTIM״̬Ĵĸ״̬λǷλ +// BTIMx CW_BTIM1~3 +// BTIM_FLAG ָ״̬λ Χ BTIM_IT_OV +// BTIM_IT_TI +// BTIM_IT_TOP +// +// ֵ ԤƵǰʹõķƵϵ +*******************************************************************************/ +FlagStatus BTIM_GetITStatus(BTIM_TypeDef* BTIMx, uint16_t BTIM_FLAG) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_IT(BTIM_FLAG)); + + return (REGBITS_GET(BTIMx->ISR, BTIM_FLAG) ? SET : RESET); +} + +/******************************************************************************* +// ˵ BTIM״̬Ĵĸ״̬λ +// BTIMx CW_BTIM1~3 +// BTIM_FLAG ָ״̬λ Χ BTIM_IT_OV +// BTIM_IT_TI +// BTIM_IT_TOP +// +// ֵ ԤƵǰʹõķƵϵ +*******************************************************************************/ +void BTIM_ClearITPendingBit(BTIM_TypeDef* BTIMx, uint16_t BTIM_FLAG) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_IT(BTIM_FLAG)); + + REGBITS_CLR(BTIMx->ICR, BTIM_FLAG); +} diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_crc.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_crc.c new file mode 100644 index 0000000..43238b6 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_crc.c @@ -0,0 +1,195 @@ +/** + * @file cw32f030_crc.c + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-08 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_crc.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief 8bitʽCRC16 + * + * @param CrcMode : CRC16_IBM CRC16_MAXIM + * CRC16_USB CRC16_MODBUS + * CRC16_CCITT CRC16_CCITTFALSE + * CRC16_X25 CRC16_XMODEM + * @param pByteBuf : uint8_tBufferָ + * @param ByteCnt 0x01 - 0xFFFF + * @return uint16_t 0x00 - 0xFFFF + */ +uint16_t CRC16_Calc_8bit( uint8_t CrcMode , uint8_t *pByteBuf , uint16_t ByteCnt ) +{ + /* Check the parameters */ + assert_param(IS_CRC_CRC16_MODE(CrcMode)); + CW_CRC->CR = CrcMode; + while ( ByteCnt ) + { + CW_CRC->DR8 = *pByteBuf; + pByteBuf++; + ByteCnt--; + } + return( CW_CRC->RESULT16 ); +} + + +/** + * @brief 16bitʽCRC16 + * + * @param CrcMode : CRC16_IBM CRC16_MAXIM + * CRC16_USB CRC16_MODBUS + * CRC16_CCITT CRC16_CCITTFALSE + * CRC16_X25 CRC16_XMODEM + * @param pHWBuf : uint16_tBufferָ + * @param HalfWordCnt 0x01 - 0xFFFF + * @return uint16_t 0x00 - 0xFFFF + */ +uint16_t CRC16_Calc_16bit( uint8_t CrcMode , uint16_t *pHWBuf , uint16_t HalfWordCnt ) +{ + /* Check the parameters */ + assert_param(IS_CRC_CRC16_MODE(CrcMode)); + + CW_CRC->CR = CrcMode; + while ( HalfWordCnt ) + { + CW_CRC->DR16 = *pHWBuf; + pHWBuf++; + HalfWordCnt--; + } + return( CW_CRC->RESULT16 ); +} + + +/** + * @brief 32bitʽCRC16 + * + * @param CrcMode : CRC16_IBM CRC16_MAXIM + * CRC16_USB CRC16_MODBUS + * CRC16_CCITT CRC16_CCITTFALSE + * CRC16_X25 CRC16_XMODEM + * @param pWBuf : uint32_tBufferָ + * @param WordCnt 0x01 - 0xFFFF + * @return uint16_t 0x00 - 0xFFFF + */ +uint16_t CRC16_Calc_32bit( uint8_t CrcMode , uint32_t *pWBuf , uint16_t WordCnt ) +{ + /* Check the parameters */ + assert_param(IS_CRC_CRC16_MODE(CrcMode)); + + CW_CRC->CR = CrcMode; + while ( WordCnt ) + { + CW_CRC->DR32 = *pWBuf; + pWBuf++; + WordCnt--; + } + return( CW_CRC->RESULT16 ); +} + +/** + * @brief 8bitʽCRC32 + * + * @param CrcMode : CRC32_DEFAULT CRC32_MPEG2 + * @param pByteBuf : uint8_tBufferָ + * @param ByteCnt 0x01 - 0xFFFF + * @return uint32_t 0x00 - 0xFFFF FFFF + */ +uint32_t CRC32_Calc_8bit( uint8_t CrcMode , uint8_t *pByteBuf , uint16_t ByteCnt ) +{ + /* Check the parameters */ + assert_param(IS_CRC_CRC32_MODE(CrcMode)); + + CW_CRC->CR = CrcMode; + while ( ByteCnt ) + { + CW_CRC->DR8 = *pByteBuf; + pByteBuf++; + ByteCnt--; + } + return( CW_CRC->RESULT32 ); +} + + +/** + * @brief 16bitʽCRC32 + * + * @param CrcMode : CRC32_DEFAULT CRC32_MPEG2 + * @param pHWBuf : uint16_tBufferָ + * @param HalfWordCnt 0x01 - 0xFFFF + * @return uint32_t 0x00 - 0xFFFF FFFF + */ +uint32_t CRC32_Calc_16bit( uint8_t CrcMode , uint16_t *pHWBuf , uint16_t HalfWordCnt ) +{ + /* Check the parameters */ + assert_param(IS_CRC_CRC32_MODE(CrcMode)); + + CW_CRC->CR = CrcMode; + while ( HalfWordCnt ) + { + CW_CRC->DR16 = *pHWBuf; + pHWBuf++; + HalfWordCnt--; + } + return( CW_CRC->RESULT32 ); +} + + +/** + * @brief 32bitʽCRC16 + * + * @param CrcMode : CRC32_DEFAULT CRC32_MPEG2 + * @param pWBuf : uint32_tBufferָ + * @param WordCnt 0x01 - 0xFFFF + * @return uint32_t 0x00 - 0xFFFF FFFF + */ +uint32_t CRC32_Calc_32bit( uint8_t CrcMode , uint32_t *pWBuf , uint16_t WordCnt ) +{ + /* Check the parameters */ + assert_param(IS_CRC_CRC32_MODE(CrcMode)); + + CW_CRC->CR = CrcMode; + while ( WordCnt ) + { + CW_CRC->DR32 = *pWBuf; + pWBuf++; + WordCnt--; + } + return( CW_CRC->RESULT32 ); +} + +//============================================================================= + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_debug.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_debug.c new file mode 100644 index 0000000..c423658 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_debug.c @@ -0,0 +1,69 @@ +/** + * @file cw32f030_debug.c + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-13 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_debug.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief + * + * @param DBGMCU_Periph : DBGMCU_ATIM_STOP DBGMCU_GTIM1_STOP + * DBGMCU_GTIM2_STOP DBGMCU_GTIM3_STOP + * DBGMCU_GTIM4_STOP DBGMCU_BTIM123_STOP + * DBGMCU_AWT_STOP DBGMCU_RTC_STOP + * DBGMCU_IWDT_STOP DBGMCU_WWDT_STOP + * @param NewState : ENABLE DISABLE + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + CW_SYSCTRL->DEBUG |= DBGMCU_Periph; + } + else + { + CW_SYSCTRL->DEBUG &= ~DBGMCU_Periph; + } +} + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_digitalsign.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_digitalsign.c new file mode 100644 index 0000000..1536348 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_digitalsign.c @@ -0,0 +1,106 @@ +/** + * @file cw32f030_digitalsign.c + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-14 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_digitalsign.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief ȡоƬͺ + * + * @param pChipType : оƬ͵Buffer22ֽ + */ +void DIGITALSIGN_GetChipType(uint8_t *pChipType) +{ + uint8_t tmpcnt = 0; + + while( tmpcnt < CHIP_TYPE_LENGTH ) + { + * (uint8_t *)(pChipType + tmpcnt) = *( (uint8_t *) (CHIP_TYPE_BASE + tmpcnt ) ); + tmpcnt ++; + } +} + +/** + * @brief ȡоƬ + * + * @return uint16_t + */ +uint16_t DIGITALSIGN_GetPinCount(void) +{ + return ( *( (uint16_t *) PIN_COUNT_BASE ) ); +} + +/** + * @brief //ȡFLASH// + * + * @return uint32_t + */ +uint32_t DIGITALSIGN_GetFlashSize(void) +{ + return ( *( (uint32_t *) FLASH_SIZE_BASE ) ); +} + +/** + * @brief //ȡRAM// + * + * @return uint32_t + */ +uint32_t DIGITALSIGN_GetRamSize(void) +{ + return ( *( (uint32_t *) RAM_SIZE_BASE ) ); +} + +/** + * @brief ȡоƬUID + * + * @param pChipUid : оƬUIDBuffer10ֽ + */ +void DIGITALSIGN_GetChipUid(uint8_t *pChipUid) +{ + uint8_t tmpcnt = 0; + + while( tmpcnt < CHIP_UID_LENGTH ) + { + * (uint8_t *)(pChipUid + tmpcnt) = *( (uint8_t *) (CHIP_UID_BASE + tmpcnt ) ); + tmpcnt ++; + } +} + + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_dma.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_dma.c new file mode 100644 index 0000000..e16fc5d --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_dma.c @@ -0,0 +1,258 @@ +/** + * @file cw32f030_dma.c + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-17 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_dma.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +void DMA_DeInit(DMACHANNEL_TypeDef* DMA_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx)); + + /* Disable the selected DMAy Channelx */ + DMA_Channelx->CSR &= (~DMA_CHANNEL_EN); ///disable DMA Channel + DMA_Channelx->CSR = 0x00UL; ///reset CSR register + DMA_Channelx->TRIG = 0x00UL; ///reset the trig register + DMA_Channelx->CNT = 0x00010000UL; ///reset the CNT register + DMA_Channelx->SRCADDR = 0x00UL; ///reset srcaddr register + DMA_Channelx->DSTADDR = 0x00UL; ///reset dstaddr register +} + +/** + * @brief DMAͨʼ + * + * @param DMA_Channelx + * @param DMA_InitStruct + */ +void DMA_Init(DMACHANNEL_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_TRANSFER_WIDTH(DMA_InitStruct->DMA_TransferWidth)); + assert_param(IS_DMA_SRCADDRESS_INC(DMA_InitStruct->DMA_SrcInc)); + assert_param(IS_DMA_DSTADDRESS_INC(DMA_InitStruct->DMA_DstInc)); + + assert_param(IS_DMA_TRIG(DMA_InitStruct->TrigMode)); + assert_param(IS_DMA_HARD_TRIGSRC(DMA_InitStruct->HardTrigSource)); + + assert_param(IS_DMA_TRANSFERCNT(DMA_InitStruct->DMA_TransferCnt)); + + DMA_Channelx->CSR = ( (DMA_Channelx->CSR & CSR_CLEAR_Mask) | \ + DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_TransferWidth | \ + DMA_InitStruct->DMA_SrcInc | DMA_InitStruct->DMA_DstInc ); + + DMA_Channelx->TRIG = ( (DMA_Channelx->TRIG & TRIG_CLEAR_Mask) | DMA_InitStruct->TrigMode | \ + DMA_InitStruct->HardTrigSource ) ; + + DMA_Channelx->CNT= bv16 | DMA_InitStruct->DMA_TransferCnt ; + + DMA_Channelx->SRCADDR = DMA_InitStruct->DMA_SrcAddress ; + + DMA_Channelx->DSTADDR = DMA_InitStruct->DMA_DstAddress ; + +} + + +/** + * @brief DMAṹʼ + * + * @param DMA_InitStruct + */ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ +/*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_Mode */ + DMA_InitStruct->DMA_Mode = DMA_MODE_BLOCK; + + /* Initialize the DMA_TransferWidth */ + DMA_InitStruct->DMA_TransferWidth = DMA_TRANSFER_WIDTH_8BIT; + + /* Initialize the DMA_SrcInc */ + DMA_InitStruct->DMA_SrcInc = DMA_SrcAddress_Fix; + + /* Initialize the DMA_DstInc */ + DMA_InitStruct->DMA_DstInc = DMA_DstAddress_Fix; + + /* Initialize the TrigMode */ + DMA_InitStruct->TrigMode = DMA_SWTrig; + + /* Initialize the HardTrigSource, if we use softtrig ,we can not config it*/ + DMA_InitStruct->HardTrigSource = DMA_HardTrig_UART1_RXBufferNE; + + /* Initialize the DMA_TransferCnt */ + DMA_InitStruct->DMA_TransferCnt = 0x00; + + /* Initialize the DMA_SrcAddress */ + DMA_InitStruct->DMA_SrcAddress = 0x00; + + /* Initialize the DMA_DstAddress */ + DMA_InitStruct->DMA_DstAddress = 0x00; +} + +/** + * @brief ʹDMAy_Channelx DMA + * + * @param DMA_Channelx + * @param NewState + */ +void DMA_Cmd(DMACHANNEL_TypeDef* DMA_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMA_Channelx->CSR |= DMA_CHANNEL_EN; + } + else + { + /* Disable the selected DMAy Channelx */ + DMA_Channelx->CSR &= ~DMA_CHANNEL_EN; + } +} + + +/** + * @brief ͨ1ͨ + * + * @param DMA_Channelx + */ +void DMA_SWTrigCmd(DMACHANNEL_TypeDef* DMA_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx)); + + DMA_Channelx->TRIG |= DMA_SOFTTRIG_EN; +} + + +/** + * @brief DMA_Channelx ָжʹ + * + * @param DMA_Channelx CW_DMACHANNEL1/2/3/4/5 + * @param DMA_IT DMA_IT_TC DMA_IT_TE + * @param NewState ENABLE DISABLE + */ +void DMA_ITConfig(DMACHANNEL_TypeDef* DMA_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMA_Channelx->CSR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMA_Channelx->CSR &= ~DMA_IT; + } +} + +/** + * @brief ȡDMA_Channelx's ָжϱ־ + * @param DMAy_IT: specifies the DMAy interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @retval The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMA_IT)); + + return (CW_DMA->ISR & DMA_IT) ? SET : RESET; +} + +/** + * @brief DMA_Channelx's ָжϱ־ + * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @retval None + */ +void DMA_ClearITPendingBit(uint32_t DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_IT(DMA_IT)); + + CW_DMA->ICR &= (~DMA_IT); + +} + +/** + * @brief ȡDMAy Channelx״̬ + * + * @param DMA_Channelx CW_DMACHANNEL1/2/3/4/5 + * @return uint8_t : DMA_CHANNEL_STATUS_INIT DMA_CHANNEL_STATUS_ADDRESSOUTRANGE + * DMA_CHANNEL_STATUS_STOPREQ DMA_CHANNEL_STATUS_SRCADDERR + * DMA_CHANNEL_STATUS_DSTADDERR DMA_CHANNEL_STATUS_TRANSCOMPLETE + */ +uint8_t DMA_GetFlagStatus(DMACHANNEL_TypeDef* DMA_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx)); + + return ( (uint8_t)(DMA_Channelx->CSR >> 8) ); +} + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_flash.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_flash.c new file mode 100644 index 0000000..57fa62e --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_flash.c @@ -0,0 +1,445 @@ +/** + * @file cw32f030_flash.c + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-08 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_flash.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief FLASHĶȴ + * + * @param FLASH_Latency FLASH_Latency_1 FLASH_Latency_2 FLASH_Latency_3 + */ +void FLASH_SetLatency( uint32_t FLASH_Latency ) +{ + uint32_t tmp8; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + tmp8 = FLASH_Latency>0 ? ( FLASH_Latency|bv3|bv4 ) : 0; //WAITΪ0ʱҪFETCHCACHE + CW_FLASH->CR2 = 0x5A5A0000 | tmp8; +} + +/** + * @brief Ԥȡ + * + * @param FLASH_Prefetch FLASH_Prefetch_Enable FLASH_Prefetch_Disable + */ +void FLASH_PrefetchCmd(uint32_t FLASH_Prefetch) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PREFETCH_STATE(FLASH_Prefetch)); + + /* Enable or disable the Prefetch Buffer */ + REGBITS_MODIFY(CW_FLASH->CR2,bv3,FLASH_Prefetch); +} + +/** + * @brief CACHE + * + * @param FLASH_Cache :FLASH_Cache_Enable FLASH_Cache_Disable + */ +void FLASH_CacheCmd(uint32_t FLASH_Cache) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CACHE_STATE(FLASH_Cache)); + + /* Enable or disable the Prefetch Buffer */ + REGBITS_MODIFY(CW_FLASH->CR2,bv4,FLASH_Cache); +} + +/** + * @brief ȡPrefetch + * + * @return FlagStatus SET RESET + */ +FlagStatus FLASH_GetPrefetchStatus(void) +{ + return( CW_FLASH->CR2_f.FETCH ? SET : RESET); +} + +/** + * @brief ȡBuffer + * + * @return FlagStatus SET RESET + */ +FlagStatus FLASH_GetCacheStatus(void) +{ + /* Get the status */ + return( CW_FLASH->CR2_f.CACHE ? SET : RESET); +} + +/** + * @brief ȡǰĶȼ + * + * @return uint8_t 0/1/2/3 + */ +uint8_t FLASH_GetReadOutLevel( void ) +{ + return( CW_FLASH->CR1_f.SECURITY ); +} + +/** + * @brief MCUĶȼ,RdLevelЧȡֵΧΪ0,1,2,3 + * //ȼдMCUMCUԶɶȼ޸ + * //ӷ0ȼΪȼ0MCUFLASHڵ + * //Level0ISPɶдSWDɶд + * //Level1ISPɽSWDɽݲɶ + * //Level2ISPɽSWD޹ܣݲɶ + * //Level3ISP޹ܣSWD޹ܣݲɶ + * @param RdLevel : FLASH_RDLEVEL0 FLASH_RDLEVEL1 + * : FLASH_RDLEVEL2 FLASH_RDLEVEL3 + */ +void FLASH_SetReadOutLevel( uint16_t RdLevel ) +{ + assert_param(IS_FLASH_RDLEVEL(RdLevel) ); + + if( FLASH_GetReadOutLevel() != RdLevel ) + { + RdLevel = 0x5A50 | ( RdLevel & 0x03u ); + *((volatile uint32_t *)(0x4001031C)) = RdLevel; + *((volatile uint32_t *)(0x40010370)) = 0x5A5AABCD; //MCUԸ¶ȼ + while(1); //MCUԸ±ȼ + } +} + +/** + * @brief ҳ + * + */ +void FLASH_UnlockAllPages(void) +{ + CW_FLASH->PAGELOCK = 0x5A5Affff; //ҳ +} + +/** + * @brief ҳ + * + */ +void FLASH_LockAllPages( void ) +{ + CW_FLASH->PAGELOCK = 0x5A5A0000; +} + +/** + * @brief ָҳ + * + * @param Page_Number : 0 - 127 + * @return uint8_t : 0x00 + */ +uint8_t FLASH_UnlockPage( uint8_t Page_Number ) +{ + uint16_t Currentlockstatus; + + assert_param(IS_FLASH_PAGE_Number(Page_Number)); + + Currentlockstatus = CW_FLASH->PAGELOCK; //ȡǰλ + CW_FLASH->PAGELOCK = 0x5A5A0000 | Currentlockstatus | ( 1UL<<(Page_Number/8)); //ָҳ + return( 0x00 ); +} + +/** + * @brief ַָΧҳ,0x00ɹ0ʧ + * + * @param StartAddr : 0x00000000 - 0x0000FFFF + * @param EndAddr : 0x00000000 - 0x0000FFFF + * @return uint8_t 󷵻0x80ȷ0x00 + */ +uint8_t FLASH_UnlockPages( uint32_t StartAddr , uint32_t EndAddr ) +{ + uint16_t Currentlockstatus; + uint16_t UnlockMask, UnlockIdx; + + UnlockMask = 0x00; + while( StartAddr <= EndAddr ) + { + UnlockIdx = StartAddr / 512 / 8; + UnlockMask |= (1UL<PAGELOCK; //ȡǰλ + CW_FLASH->PAGELOCK = 0x5A5A0000 | Currentlockstatus | UnlockMask; //ҳڵ + return( 0x00 ); +} + +/** + * @brief ָҳ + * + * @param Page_Number : 0 - 127 + * @return uint8_t 󷵻0x80ȷ0x00 + */ +uint8_t FLASH_ErasePage( uint8_t Page_Number ) +{ + uint16_t CR1BAK,CR2BAK; + + if( ( Page_Number > 127 ) ) + { + return( FLASH_ERROR_ADDR ); + } + + while( CW_FLASH->CR1 & bv5 ); //ȴ1βɣδʱ + CW_FLASH->ICR = 0x00; //clear all int flag + CR2BAK = CW_FLASH->CR2; + CR1BAK = CW_FLASH->CR1; + CW_FLASH->CR2 = 0x5A5A0000 | ( CR2BAK & 0xffe7 ); //صFETCHBUFFER + CW_FLASH->CR1 = 0x5A5A0000 | ( CR1BAK | 0x02u ); // Ϊҳģʽ + + *((volatile uint8_t *)(Page_Number * 512)) = 0x00; //erase page + while( CW_FLASH->CR1 & bv5 ); //ȴ + + CW_FLASH->CR1 = 0x5A5A0000 | CR1BAK; + CW_FLASH->CR2 = 0x5A5A0000 | CR2BAK; + return( CW_FLASH->ISR ); +} + + +/** + * @brief STARTADDRENDADDRڵҳ,0x00ɹ0ʧ + * + * @param StartAddr : 0x00000000 - 0x0000FFFF + * @param EndAddr : 0x00000000 - 0x0000FFFF + * @return uint8_t 󷵻0x80ȷ0x00 + */ +uint8_t FLASH_ErasePages( uint32_t StartAddr , uint32_t EndAddr ) +{ + uint16_t CR1BAK,CR2BAK; + + if( ( StartAddr > 65535 ) || ( EndAddr > 65535 ) ) + { + return( FLASH_ERROR_ADDR ); + } + + while( CW_FLASH->CR1 & bv5 ); //ȴ1βɣδʱ + CW_FLASH->ICR = 0x00; //clear all int flag + CR2BAK = CW_FLASH->CR2; + CR1BAK = CW_FLASH->CR1; + CW_FLASH->CR2 = 0x5A5A0000 | ( CR2BAK & 0xffe7 ); //صFETCHBUFFER + CW_FLASH->CR1 = 0x5A5A0000 | ( CR1BAK | 0x02u ); // Ϊҳģʽ + while( StartAddr <= EndAddr ) + { + *((volatile uint8_t *)(StartAddr)) = 0x00; //erase page + while( CW_FLASH->CR1 & bv5 ); //ȴ + StartAddr += 512; + } + + CW_FLASH->CR1 = 0x5A5A0000 | CR1BAK; + CW_FLASH->CR2 = 0x5A5A0000 | CR2BAK; + return( CW_FLASH->ISR ); +} + + +/** + * @brief WriteAddrΪʼַдpWrBufڵWrByteCntֽڵ + * //дʼַͽַҪλͬһҳ + * //дַҳ + * //0x00ɹ0ʧ + * @param WriteAddr : 0x00000000 - 0x0000FFFF + * @param pWrBuf + * @param WrByteCnt 1 - 512 + * @return uint8_t 󷵻0x80ȷ0x00 + */ +uint8_t FLASH_WirteBytes( uint32_t WriteAddr, uint8_t *pWrBuf , uint16_t WrByteCnt ) +{ + uint16_t CR1BAK,CR2BAK; + + if( WriteAddr + WrByteCnt > 65535 ) + { + return( FLASH_ERROR_ADDR ); + } + + while( CW_FLASH->CR1 & bv5 ); //ȴ1βɣδʱ + CW_FLASH->ICR = 0x00; //clear all int flag + CR2BAK = CW_FLASH->CR2; + CR1BAK = CW_FLASH->CR1; + CW_FLASH->CR2 = 0x5A5A0000 | ( CR2BAK & 0xffe7u ); //صFETCHBUFFER + CW_FLASH->CR1 = 0x5A5A0000 | ( CR1BAK | 0x01u ); // Ϊҳдģʽ + while( WrByteCnt ) + { + *((volatile uint8_t *)(WriteAddr)) = *pWrBuf; //write byte + while( CW_FLASH->CR1 & bv5 ); //ȴ + WriteAddr++; + WrByteCnt--; + pWrBuf++; + } + CW_FLASH->CR1 = 0x5A5A0000 | CR1BAK; + CW_FLASH->CR2 = 0x5A5A0000 | CR2BAK; + return( CW_FLASH->ISR ); +} + +/** + * @brief ָҳ,0x00ɹ0ʧ + * + * @param Page_Number : 0 - 127 + * @return uint8_t : 0x00 + */ +uint8_t FLASH_LockPage( uint8_t Page_Number ) +{ + uint16_t Currentlockstatus; + + assert_param(IS_FLASH_PAGE_Number(Page_Number)); + + Currentlockstatus = CW_FLASH->PAGELOCK; //ȡǰλ + CW_FLASH->PAGELOCK = ( (0x5A5A0000 | Currentlockstatus) & ( ~(1UL<<(Page_Number/8))) ); //ָҳ + return( 0x00 ); +} + +/** + * @brief ַָΧҳ,0x00ɹ0ʧ + * + * @param StartAddr : 0x00000000 - 0x0000FFFF + * @param EndAddr : 0x00000000 - 0x0000FFFF + * @return uint8_t : 󷵻0x800x00 + */ +uint8_t FLASH_LockPages( uint32_t StartAddr , uint32_t EndAddr ) +{ + uint16_t UnlockMask, UnlockIdx; + uint16_t Currentlockstatus; + + UnlockMask = 0x00; + while( StartAddr <= EndAddr ) + { + UnlockIdx = StartAddr / 512 / 8; + UnlockMask |= (1UL<PAGELOCK; //ȡǰλ + CW_FLASH->PAGELOCK = ( (0x5A5A0000 | Currentlockstatus) & (~UnlockMask) ); //ҳڵ + return( 0x00 ); +} + + +/** + * @brief FLASHж + * + * @param FLASH_IT : FLASH_IT_PROG + * FLASH_IT_PAGELOCK + * FLASH_IT_PC + * @param NewState : ENABLE DISABLE + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + CW_FLASH->IER |= FLASH_IT; + } + else + { + CW_FLASH->IER &= (~FLASH_IT); + } +} + +/** + * @brief ȡFLASHָж״̬ + * + * @param FLASH_IT : FLASH_IT_PROG + * FLASH_IT_PAGELOCK + * FLASH_IT_PC + * @return ITStatus : SET RESET + */ +ITStatus FLASH_GetITStatus(uint32_t FLASH_IT) +{ + assert_param(IS_FLASH_GET_IT(FLASH_IT)); + + return (CW_FLASH->ISR & FLASH_IT) ? SET : RESET; +} + + +/** + * @brief FLASHָжϱ־ + * + * @param FLASH_IT : FLASH_IT_PROG + * FLASH_IT_PAGELOCK + * FLASH_IT_PC + */ +void FLASH_ClearITPendingBit(uint32_t FLASH_IT) +{ + assert_param(IS_FLASH_IT(FLASH_IT)); + + CW_FLASH->ICR &= (~FLASH_IT); +} + +/** + * @brief ȡFLASHģ״̬ + * + * @return uint8_t 00: + * FLASH_FLAG_BSY æ + * FLASH_FLAG_PCERR дPCָҳ + * FLASH_FLAG_WRPRTERR дδҳ + * FLASH_FLAG_PGERR ĿַݲȫΪ0XFF + */ +uint32_t FLASH_GetStatus(void) +{ + uint32_t flashstatus; + if(1 == CW_FLASH->CR1_f.BUSY) + { + return FLASH_FLAG_BSY; + } + + flashstatus = CW_FLASH->ISR; + + if (flashstatus & FLASH_FLAG_PCERR) + { + return FLASH_FLAG_PCERR; + } + + if (flashstatus & FLASH_FLAG_WRPRTERR) + { + return FLASH_FLAG_WRPRTERR; + } + + if (flashstatus & FLASH_FLAG_PGERR) + { + return FLASH_FLAG_PGERR; + } + + return FLASH_FLAG_OK; +} + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_gpio.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_gpio.c new file mode 100644 index 0000000..6791ac2 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_gpio.c @@ -0,0 +1,268 @@ +/** + ****************************************************************************** + * @file CW030xx_gpio.c + * @author + * @version + * @date 2021-03-16 + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * +***/ + + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_gpio.h" + + + +//============================================================================= +//GPIO ʼ +/** + * @brief GPIO ʼͬʱöŻ򵥸 + * + * @param GPIOx Ϊв֮һ + * @arg CW_GPIOA CW_GPIOB CW_GPIOC CW_GPIOF + * @param GPIO_Init μGPIO_InitTypeDefĶ + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + if( GPIO_Init->Mode == GPIO_MODE_ANALOG ) //ģ⹦ + { + REGBITS_SET( GPIOx->ANALOG , GPIO_Init->Pins ); + } + else + { + REGBITS_CLR( GPIOx->ANALOG , GPIO_Init->Pins ); //ֹ + if( (GPIO_Init->Mode & GPIO_MODE_INPUT) == GPIO_MODE_INPUT ) //ģʽ + { + REGBITS_SET( GPIOx->DIR , GPIO_Init->Pins ); + if( GPIO_Init->Mode == GPIO_MODE_INPUT_PULLUP ) + { + REGBITS_SET( GPIOx->PUR , GPIO_Init->Pins ); + REGBITS_CLR( GPIOx->PDR , GPIO_Init->Pins ); + } + if( GPIO_Init->Mode == GPIO_MODE_INPUT_PULLDOWN ) + { + REGBITS_SET( GPIOx->PDR , GPIO_Init->Pins ); + REGBITS_CLR( GPIOx->PUR , GPIO_Init->Pins ); + } + + REGBITS_CLR( GPIOx->RISEIE , GPIO_Init->Pins ); + REGBITS_CLR( GPIOx->FALLIE , GPIO_Init->Pins ); + REGBITS_CLR( GPIOx->HIGHIE , GPIO_Init->Pins ); + REGBITS_CLR( GPIOx->LOWIE , GPIO_Init->Pins ); + if( ( GPIO_Init->IT & GPIO_IT_RISING ) == GPIO_IT_RISING ) + { + REGBITS_SET( GPIOx->RISEIE , GPIO_Init->Pins ); + } + if( ( GPIO_Init->IT & GPIO_IT_FALLING ) == GPIO_IT_FALLING ) + { + REGBITS_SET( GPIOx->FALLIE , GPIO_Init->Pins ); + } + if( ( GPIO_Init->IT & GPIO_IT_HIGH ) == GPIO_IT_HIGH ) + { + REGBITS_SET( GPIOx->HIGHIE , GPIO_Init->Pins ); + } + if( ( GPIO_Init->IT & GPIO_IT_LOW ) == GPIO_IT_LOW ) + { + REGBITS_SET( GPIOx->LOWIE , GPIO_Init->Pins ); + } + } + else //ģʽ + { + REGBITS_CLR( GPIOx->DIR , GPIO_Init->Pins ); + if( GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP ) + { + REGBITS_CLR( GPIOx->OPENDRAIN , GPIO_Init->Pins ); + } + else + { + REGBITS_SET( GPIOx->OPENDRAIN , GPIO_Init->Pins ); + } + if( GPIO_Init->Speed == GPIO_SPEED_HIGH ) + { + REGBITS_SET( GPIOx->SPEED , GPIO_Init->Pins ); + } + else + { + REGBITS_CLR( GPIOx->SPEED , GPIO_Init->Pins ); + } + } + } +} + +//============================================================================= +//GPIO ʼ +/** + * @brief GPIO ȥʼͬʱöŻ򵥸 + * + * @param GPIOx Ϊв֮һ + * @arg CW_GPIOA CW_GPIOB CW_GPIOC CW_GPIOF + * + * @param GPIO_Pins ȡֵ + * @arg GPIO_PIN_0/1/2.../15/ALL ͨͬʱ + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pins) +{ + REGBITS_SET( GPIOx->ANALOG , GPIO_Pins ); + REGBITS_SET( GPIOx->DIR , GPIO_Pins ); + REGBITS_CLR( GPIOx->PUR , GPIO_Pins ); + REGBITS_CLR( GPIOx->PDR , GPIO_Pins ); + REGBITS_CLR( GPIOx->RISEIE , GPIO_Pins ); + REGBITS_CLR( GPIOx->FALLIE , GPIO_Pins ); + REGBITS_CLR( GPIOx->HIGHIE , GPIO_Pins ); + REGBITS_CLR( GPIOx->LOWIE , GPIO_Pins ); + REGBITS_CLR( GPIOx->OPENDRAIN , GPIO_Pins ); +} +//============================================================================= +//ȡָŵƽһ +//ע⣺ú꺯ȡŵƽPA00_GETVALUE() +/** + * @brief ȡһŵĵƽ + * + * @param GPIOx Ϊв֮һ + * @arg CW_GPIOA CW_GPIOB CW_GPIOC CW_GPIOF + * @param GPIO_Pin ȡֵ + * @arg GPIO_PIN_0/1/2.../15 + * @return GPIO_PinState ȡֵ: + * @arg GPIO_Pin_SET + * @arg GPIO_Pin_RESET + */ +GPIO_PinState GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + if( GPIOx->IDR & GPIO_Pin ) + { + return( GPIO_Pin_SET ); + } + + return( GPIO_Pin_RESET ); +} + +//============================================================================= +//ָŵƽ +//ע⣺ֻһֻţú꺯PA00_SETHIGH(), PA00_SETLOW() +/** + * @brief ָŵƽͬʱö + * + * @param GPIOx GPIOx Ϊв֮һ + * @arg CW_GPIOA CW_GPIOB CW_GPIOC CW_GPIOF + * @param GPIO_Pins ȡֵ + * @arg GPIO_PIN_0/1/2.../15/ALL; + * @param PinState ȡֵ: + * @arg GPIO_Pin_SET + * @arg GPIO_Pin_RESET + */ +void GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pins, GPIO_PinState PinState) +{ + if( PinState == GPIO_Pin_SET ) + { + GPIOx->BSRR = GPIO_Pins; + } + else + { + GPIOx->BRR = GPIO_Pins; + } +} + +//============================================================================= +//ö˿ڵֽڣB0-B7ŵƽ +/** + * @brief ö˿ڵֽڣB0-B7ŵƽ + * + * @param GPIOx Ϊв֮һ + * @arg CW_GPIOA CW_GPIOB CW_GPIOF + * @param Value ȡֵΧ0x00~0xFF + */ +void GPIO_LowByte_Write(GPIO_TypeDef* GPIOx, uint8_t Value ) +{ + GPIOx->ODRLOWBYTE = Value; +} + +//============================================================================= +//ö˿ڸֽڣB8-B15ŵƽ +/** + * @brief ö˿ڸֽڣB8-B15ŵƽ + * + * @param GPIOx Ϊв֮һ + * @arg CW_GPIOA CW_GPIOB CW_GPIOC + * @param Value ȡֵΧ0x00~0xFF + */ +void GPIO_HighByte_Write(GPIO_TypeDef* GPIOx, uint8_t Value ) +{ + GPIOx->ODRHIGHBYTE = Value; +} + +//============================================================================= +//תָŵƽ +//ע⣺ֻһֻţú꺯PA00_TOG() +/** + * @brief תָŵƽͬʱö + * + * @param GPIOx Ϊв֮һ + * @arg CW_GPIOA CW_GPIOB CW_GPIOC CW_GPIOF + * @param GPIO_Pins + */ +void GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pins) +{ + GPIOx->TOG = GPIO_Pins; +} + +//============================================================================= +//ָ +/** + * @brief ָͬʱö + * + * @param GPIOx Ϊв֮һ + * @arg CW_GPIOA CW_GPIOB CW_GPIOC CW_GPIOF + * @param GPIO_Pins + */ +void GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pins) +{ + REGBITS_SET( GPIOx->LOCK , GPIO_Pins ); +} + +//============================================================================= +//PA13/PA14óGPIO +/** + * @brief PA13/PA14óGPIO + * + */ +void GPIO_SWD2GPIO( void ) +{ + CW_SYSCTRL->CR2 = CW_SYSCTRL->CR2 | ( 0x5A5A0000 | bv1 ); +} + +//============================================================================= +//PA13/PA14óSWD +/** + * @brief PA13/PA14óSWDPA13/SWDIO PA14/SWCLK + * + */ +void GPIO_GPIO2SWD( void ) +{ + CW_SYSCTRL->CR2 = 0x5A5A0000 | ( CW_SYSCTRL->CR2 & (~(bv1)) ); +} + +//============================================================================= +//ö˿˲ +// FltClk ֻǺ궨жIJ +/** + * @brief ö˿˲ + * + * @param GPIOx Ϊв֮һ + * @arg CW_GPIOA CW_GPIOB CW_GPIOC CW_GPIOF + * @param GPIO_Pins + * @param FltClk ֻǺ궨жIJ GPIO_FLTCLK_xxx + */ +void GPIO_ConfigFilter( GPIO_TypeDef* GPIOx, uint16_t GPIO_Pins, uint32_t FltClk ) +{ + GPIOx->FILTER = FltClk | GPIO_Pins; +} + +//============================================================================= +//ö˿ڸ +//ʹCW32f030_gpio.hеĺ궨ÿ˿ڵĸ + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_gtim.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_gtim.c new file mode 100644 index 0000000..e2104d4 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_gtim.c @@ -0,0 +1,440 @@ +/** + * @file cw32f030_gtim.c + * @author P&S (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-04-27 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_gtim.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief + * @param GTIMx + */ +void GTIM1_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.GTIM1 = 0; + CW_SYSCTRL->APBRST1_f.GTIM1 = 1; +} + +void GTIM2_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.GTIM2 = 0; + CW_SYSCTRL->APBRST1_f.GTIM2 = 1; +} + +void GTIM3_DeInit(void) +{ + CW_SYSCTRL->APBRST2_f.GTIM3 = 0; + CW_SYSCTRL->APBRST2_f.GTIM3 = 1; +} + +void GTIM4_DeInit(void) +{ + CW_SYSCTRL->APBRST2_f.GTIM4 = 0; + CW_SYSCTRL->APBRST2_f.GTIM4 = 1; +} + +/** + * @brief GTIMĻʼ + * @param GTIMx ȡֵΧCW_GTIM1,CW_GTIM2,CW_GTIM3,CW_GTIM4 + * @param GTIM_InitStruct GTIM_InitTypeDefĶ + */ +void GTIM_TimeBaseInit(GTIM_TypeDef *GTIMx, GTIM_InitTypeDef *GTIM_InitStruct) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_MODE(GTIM_InitStruct->Mode)); + assert_param(IS_GTIM_ONESHOT(GTIM_InitStruct->OneShotMode)); + assert_param(IS_GTIM_PRESCALER(GTIM_InitStruct->Prescaler)); + + REGBITS_MODIFY(GTIMx->CR0, GTIMx_CR0_PRS_Msk | GTIMx_CR0_ONESHOT_Msk |\ + GTIMx_CR0_MODE_Msk | GTIMx_CR0_TOGEN_Msk, \ + GTIM_InitStruct->Prescaler | GTIM_InitStruct->OneShotMode |\ + GTIM_InitStruct->Mode |\ + (GTIM_InitStruct->ToggleOutState ? GTIMx_CR0_TOGEN_Msk : 0)); + + GTIMx->ARR = GTIM_InitStruct->ReloadValue; +} + +/** + * @brief ģʽʼ + * @param GTIMx ȡֵΧCW_GTIM1,CW_GTIM2,CW_GTIM3,CW_GTIM4 + * @param GTIM_EncodeInitStruct + */ +void GTIM_EncodeInit(GTIM_TypeDef *GTIMx, GTIM_EncodeInitTypeDef *GTIM_EncodeInitStruct) +{ + uint32_t tmp; + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_ENCODE_MODE(GTIM_EncodeInitStruct->EncodeMode)); + assert_param(IS_GTIM_ENCODE_RESET(GTIM_EncodeInitStruct->EncodeResetMode)); + assert_param(IS_GTIM_ENCODE_RELOAD(GTIM_EncodeInitStruct->EncodeReloadMode)); + assert_param(IS_GTIM_CHx_FILTER(GTIM_EncodeInitStruct->CH1Filter)); + assert_param(IS_GTIM_CHx_FILTER(GTIM_EncodeInitStruct->CH2Filter)); + assert_param(IS_GTIM_CHx_FILTER(GTIM_EncodeInitStruct->CH3Filter)); + assert_param(IS_GTIM_CHx_INVERT(GTIM_EncodeInitStruct->CH1Invert)); + assert_param(IS_GTIM_CHx_INVERT(GTIM_EncodeInitStruct->CH2Invert)); + assert_param(IS_GTIM_CHx_INVERT(GTIM_EncodeInitStruct->CH3Invert)); + + REGBITS_MODIFY(GTIMx->CR0, + GTIMx_CR0_ENCRELOAD_Msk | GTIMx_CR0_ENCRESET_Msk | GTIMx_CR0_ENCMODE_Msk, + GTIM_EncodeInitStruct->EncodeMode | GTIM_EncodeInitStruct->EncodeResetMode | + GTIM_EncodeInitStruct->EncodeReloadMode); + + tmp = GTIM_EncodeInitStruct->CH1Filter | GTIM_EncodeInitStruct->CH1Invert | + (GTIM_EncodeInitStruct->CH2Filter << 4) | (GTIM_EncodeInitStruct->CH2Invert << 7) | + (GTIM_EncodeInitStruct->CH3Filter << 8) | (GTIM_EncodeInitStruct->CH3Invert << 11); + REGBITS_MODIFY(GTIMx->CR1, ~(GTIMx_CR1_CH4FLT_Msk | GTIMx_CR1_CH4POL_Msk), tmp); +} + +/** + * @brief Ƚܳʼ + * @param GTIMx ȡֵΧCW_GTIM1,CW_GTIM2,CW_GTIM3,CW_GTIM4 + * @param CHx ͨCH1~CH4 + * @param OCMode + */ +void GTIM_OCInit(GTIM_TypeDef *GTIMx, uint32_t CHx, uint32_t OCMode) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_CHANNEL(CHx)); + assert_param(IS_GTIM_OC_OUTPUT(OCMode)); + + REGBITS_MODIFY(GTIMx->CMMR, (GTIMx_CMMR_CC1M_Msk << CHx), (OCMode << CHx)); +} + +void GTIM_ICInit(GTIM_TypeDef *GTIMx, GTIM_ICInitTypeDef *GTIM_ICInitStruct) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_CHANNEL(GTIM_ICInitStruct->CHx)); + assert_param(IS_GTIM_ICPolarity(GTIM_ICInitStruct->ICPolarity)); + assert_param(IS_GTIM_CHx_FILTER(GTIM_ICInitStruct->ICFilter)); + assert_param(IS_GTIM_CHx_INVERT(GTIM_ICInitStruct->ICInvert)); + + REGBITS_MODIFY(GTIMx->CMMR, (GTIMx_CMMR_CC1M_Msk << GTIM_ICInitStruct->CHx), + (GTIM_ICInitStruct->ICPolarity << GTIM_ICInitStruct->CHx)); + + REGBITS_MODIFY(GTIMx->CR1, (0xFUL << GTIM_ICInitStruct->CHx), + (GTIM_ICInitStruct->ICFilter | (GTIM_ICInitStruct->ICInvert << 3)) << GTIM_ICInitStruct->CHx); +} + +/** + * @brief GTIMʹ + * @param GTIMx + */ +void GTIM_Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + GTIMx->CR0_f.EN = NewState; +} + +/** + * @brief ETRźŵļԺ˲ + * @param GTIMx + * @param ETRPolarity + * @param ETRFilter ˲ + */ +void GTIM_ETRConfig(GTIM_TypeDef *GTIMx, uint32_t ETRPolarity, uint32_t ETRFilter) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_ETR_POL(ETRPolarity)); + assert_param(IS_GTIM_ETR_FILTER(ETRFilter)); + + REGBITS_MODIFY(GTIMx->CR0, GTIMx_CR0_TRS_Msk | GTIMx_CR0_POL_Msk, ETRPolarity); + + REGBITS_MODIFY(GTIMx->ETR, GTIMx_ETR_ETRFLT_Msk, ETRFilter); +} + +/** + * @brief + * + * @param ITRSouce ITR_SOURCE_BTIM1 ITR_SOURCE_BTIM2 ITR_SOURCE_BTIM3 + * ITR_SOURCE_GTIM2 ITR_SOURCE_GTIM3 ITR_SOURCE_GTIM4 + * ITR_SOURCE_ATIM + */ +void GTIM1_ITRConfig(uint32_t ITRSouce) +{ + assert_param(IS_ITR_SOURCE(ITRSouce)); + assert_param(ITRSouce != ITR_SOURCE_GTIM1); + + REGBITS_SET(CW_GTIM1->CR0, GTIMx_CR0_TRS_Msk); + + CW_SYSCTRL->TIMITR_f.GTIM1ITR = ITRSouce; +} + +/** + * @brief + * + * @param ITRSouce ITR_SOURCE_BTIM1 ITR_SOURCE_BTIM2 ITR_SOURCE_BTIM3 + * ITR_SOURCE_GTIM1 ITR_SOURCE_GTIM3 ITR_SOURCE_GTIM4 + * ITR_SOURCE_ATIM + */ +void GTIM2_ITRConfig(uint32_t ITRSouce) +{ + assert_param(IS_ITR_SOURCE(ITRSouce)); + assert_param(ITRSouce != ITR_SOURCE_GTIM2); + + REGBITS_SET(CW_GTIM2->CR0, GTIMx_CR0_TRS_Msk); + + CW_SYSCTRL->TIMITR_f.GTIM2ITR = ITRSouce; +} + +/** + * @brief + * + * @param ITRSouce ITR_SOURCE_BTIM1 ITR_SOURCE_BTIM2 ITR_SOURCE_BTIM3 + * ITR_SOURCE_GTIM1 ITR_SOURCE_GTIM2 ITR_SOURCE_GTIM4 + * ITR_SOURCE_ATIM + */ +void GTIM3_ITRConfig(uint32_t ITRSouce) +{ + assert_param(IS_ITR_SOURCE(ITRSouce)); + assert_param(ITRSouce != ITR_SOURCE_GTIM3); + + REGBITS_SET(CW_GTIM3->CR0, GTIMx_CR0_TRS_Msk); + + CW_SYSCTRL->TIMITR_f.GTIM3ITR = ITRSouce; +} + +/** + * @brief + * + * @param ITRSouce ITR_SOURCE_BTIM1 ITR_SOURCE_BTIM2 ITR_SOURCE_BTIM3 + * ITR_SOURCE_GTIM1 ITR_SOURCE_GTIM2 ITR_SOURCE_GTIM3 + * ITR_SOURCE_ATIM + */ +void GTIM4_ITRConfig(uint32_t ITRSouce) +{ + assert_param(IS_ITR_SOURCE(ITRSouce)); + assert_param(ITRSouce != ITR_SOURCE_GTIM4); + + REGBITS_SET(CW_GTIM1->CR0, GTIMx_CR0_TRS_Msk); + + CW_SYSCTRL->TIMITR_f.GTIM4ITR = ITRSouce; +} + +/** + * @brief ͨIJ + * @param GTIMx + * @param CHx + * @param CHxFilter + * @param CHxInvert + */ +void GTIM_ICChannelConfig(GTIM_TypeDef *GTIMx, uint32_t CHx, uint32_t CHxFilter, uint32_t CHxInvert) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_CHANNEL(CHx)); + assert_param(IS_GTIM_CHx_FILTER(CHxFilter)); + assert_param(IS_GTIM_CHx_INVERT(CHxInvert)); + + REGBITS_MODIFY(GTIMx->CR1, (0xFUL << CHx), (CHxFilter | (CHxInvert << 3)) << CHx); +} + +/** + * @brief ԤƵϵ + * @param GTIMx + * @param GTIMPrescaler + */ +void GTIM_SetPrescaler(GTIM_TypeDef *GTIMx, uint32_t GTIMPrescaler) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_PRESCALER(GTIMPrescaler)); + + REGBITS_MODIFY(GTIMx->CR0, GTIMx_CR0_PRS_Msk, GTIMPrescaler); +} + +/** + * @brief ֵ + * @param GTIMx + * @param ReloadValue ȡֵΧ0x0000~0xFFFF + */ +void GTIM_SetReloadValue(GTIM_TypeDef *GTIMx, uint32_t ReloadValue) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + GTIMx->ARR = ReloadValue; +} + +/** + * @brief + * @param GTIMx + * @param Value + */ +void GTIM_SetCounterValue(GTIM_TypeDef *GTIMx, uint32_t Value) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + GTIMx->CNT = Value; +} + +void GTIM_SetCompare1(GTIM_TypeDef *GTIMx, uint32_t Value) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + GTIMx->CCR1 = 0x0000FFFF & Value; +} + +void GTIM_SetCompare2(GTIM_TypeDef *GTIMx, uint32_t Value) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + GTIMx->CCR2 = 0x0000FFFF & Value; +} + +void GTIM_SetCompare3(GTIM_TypeDef *GTIMx, uint32_t Value) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + GTIMx->CCR3 = 0x0000FFFF & Value; +} + +void GTIM_SetCompare4(GTIM_TypeDef *GTIMx, uint32_t Value) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + GTIMx->CCR4 = 0x0000FFFF & Value; +} + +/** + * @brief + * @param GTIMx + * @return uint32_t + */ +uint32_t GTIM_GetCapture1(GTIM_TypeDef *GTIMx) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + return GTIMx->CCR1; +} + +/** + * @brief + * @param GTIMx + * @return uint32_t + */ +uint32_t GTIM_GetCapture2(GTIM_TypeDef *GTIMx) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + return GTIMx->CCR2; +} + +/** + * @brief + * @param GTIMx + * @return uint32_t + */ +uint32_t GTIM_GetCapture3(GTIM_TypeDef *GTIMx) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + return GTIMx->CCR3; +} + +/** + * @brief + * @param GTIMx + * @return uint32_t + */ +uint32_t GTIM_GetCapture4(GTIM_TypeDef *GTIMx) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + return GTIMx->CCR4; +} + +/** + * @brief + * @param GTIMx + * @param GTIM_IT + * @param NewState + */ +void GTIM_ITConfig(GTIM_TypeDef *GTIMx, uint32_t GTIM_IT, FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_IT(GTIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + GTIMx->IER |= GTIM_IT; + } + else + { + GTIMx->IER &= ~GTIM_IT; + } +} + +/** + * @brief + * @param GTIMx + * @param GTIM_IT + * @return ITStatus + */ +ITStatus GTIM_GetITStatus(GTIM_TypeDef *GTIMx, uint32_t GTIM_IT) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_GET_IT(GTIM_IT)); + + return (GTIMx->ISR & GTIM_IT) ? SET : RESET; +} + +/** + * @brief + * @param GTIMx + * @param GTIM_IT + */ +void GTIM_ClearITPendingBit(GTIM_TypeDef *GTIMx, uint32_t GTIM_IT) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_IT(GTIM_IT)); + + GTIMx->ICR = ~GTIM_IT; +} + +/** + * @brief + * @param GTIMx + * @param GTIM_DMA + */ +void GTIM_DMAConfig(GTIM_TypeDef *GTIMx, uint32_t GTIM_DMA, FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_DMA(GTIM_DMA)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + NewState ? (GTIMx->DMA |= GTIM_DMA) : (GTIMx->DMA &= ~GTIM_DMA); +} diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_i2c.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_i2c.c new file mode 100644 index 0000000..fcbfa04 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_i2c.c @@ -0,0 +1,805 @@ +/** + * @file cw32f030_i2c.c + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-04-27 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_i2c.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +//I2C豸ַ8 BITãλ01ɡ +#define I2C_SLAVEADDRESS 0xA0 + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief I2C ʷʹ + * + * @param I2Cx : I2C1 I2C2 + * @param NewState : ENABLE DISABLE + */ +void I2C_BaudGeneratorEnable(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->BRREN_f.EN = 1; + } + else + { + /* Peripheral not under reset */ + I2Cx->BRREN_f.EN = 0; + } +} + +/** + * @brief I2CòʼüĴ + * + * @param I2Cx : I2C1 I2C2 + * @param u8TBaud : ֵ= fPCLK/(8*fSCL) - 1 + * : ֵҪfPCLKfSCL + */ +void I2C_SetBaud(I2C_TypeDef *I2Cx, uint8_t u8TBaud) + { + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_Baud_BRR(u8TBaud)); + I2Cx->BRR = u8TBaud; + } + +/** + * @brief STARTź + * + * @param I2Cx : I2C1 I2C2 + * @param NewState : ENABLE DISABLE + */ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a START condition */ + //I2Cx->CR_f.STA = 1; + + if( I2Cx->STAT != 0xF8 ) + { + I2Cx->CR_f.STA = 1; //set start + I2Cx->CR_f.SI = 0; //clear si + } + else + { + I2Cx->CR_f.STA = 1; //set start + } + + } + else + { + /* Disable the START condition generation */ + I2Cx->CR_f.STA = 0; + } +} + +/** + * @brief STOPź + * + * @param I2Cx : I2C1 I2C2 + * @param NewState : ENABLE DISABLE + */ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR_f.STO = 1; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR_f.STO = 0; + } +} + +/** + * @brief ACKӦ + * + * @param I2Cx : I2C1 I2C2 + * @param NewState : ENABLE DISABLE + */ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR_f.AA = 1; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR_f.AA = 0; + } +} + +/** + * @brief ˲ + * + * @param I2Cx : I2C1 I2C2 + * @param NewState : ENABLE DISABLE + * ΪʱBRRֵСڻ9I2Cx_CR.FLTΪENABLE + * BRRֵ9 I2Cx_CR.FLTΪDISABLE + * + * ӻʱPCLKSCLƵʱֵСڻ40I2Cx_CR.FLTΪENABLE + * PCLKSCLƵʱֵ40I2Cx_CR.FLTΪDISABLE + */ +void I2C_FilterConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CR_f.FLT = 1; + } + else + { + /* Peripheral not under reset */ + I2Cx->CR_f.FLT = 0; + } +} + +/** + * @brief ӻʱI2Cַ0 + * + * @param I2Cx : I2C1 I2C2 + * @param I2CSlaveAddr ȫ0÷ΧΪ0x01 - 0x7F + */ +void I2C_SetOwnSlaveAddress0(I2C_TypeDef* I2Cx, uint8_t I2CSlaveAddr) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + I2Cx->ADDR0_f.ADDR0 = ( I2CSlaveAddr >> 1); + + +} + +/** + * @brief ӻʱI2Cַ1 + * + * @param I2Cx : I2C1 I2C2 + * @param I2CSlaveAddr ȫ0÷ΧΪ0x01 - 0x7F + */ +void I2C_SetOwnSlaveAddress1(I2C_TypeDef* I2Cx, uint8_t I2CSlaveAddr) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + I2Cx->ADDR1_f.ADDR1 = ( I2CSlaveAddr >> 1); +} + +/** + * @brief ӻʱI2Cַ2 + * + * @param I2Cx : I2C1 I2C2 + * @param I2CSlaveAddr ȫ0÷ΧΪ0x01 - 0x7F + */ +void I2C_SetOwnSlaveAddress2(I2C_TypeDef* I2Cx, uint8_t I2CSlaveAddr) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + I2Cx->ADDR2_f.ADDR2 = ( I2CSlaveAddr >> 1); +} + +/** + * @brief 㲥ַӦλ + * + * @param I2Cx : I2C1 I2C2 + * @param NewState : ENABLE DISABLE + */ +void I2C_GcConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Ӧ㲥 */ + I2Cx->ADDR0_f.GC = 1; + } + else + { + /* ֹӦ㲥 */ + I2Cx->ADDR0_f.GC = 0; + } +} + +/** + * @brief I2Cģʹܿ + * + * @param I2Cx : I2C1 I2C2 + * @param NewState : ENABLE DISABLE + */ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR_f.EN = 1; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR_f.EN = 0; + } +} + +/** + * @brief I2Cȡжϱ־λ + * + * @param I2Cx : I2C1 I2C2 + * @return ITStatus : Ϊ0ʾжϱ־(SI = 0)Ϊ1Ϊжϱ־(SI = 1) + */ +ITStatus I2C_GetIrq(I2C_TypeDef *I2Cx) +{ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + return (I2Cx->CR & bv3) ? SET : RESET; +} + +/** + * @brief I2Cжϱ־λ + * + * @param I2Cx : I2C1 I2C2 + */ +void I2C_ClearIrq(I2C_TypeDef *I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + I2Cx->CR_f.SI = 0; +} + +/** + * @brief I2Cȡ״̬Ĵ + * + * @param I2Cx : I2C1 I2C2 + * @return uint8_t : 26ֵַڲͬģʽ²ͬ + * + */ +uint8_t I2C_GetState(I2C_TypeDef *I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + return ((uint8_t)(I2Cx->STAT)); +} + +/** + * @brief I2C:MASTERʼ + * + * @param I2Cx : I2C1 I2C2 + * @param I2C_InitStruct + */ +void I2C_Master_Init(I2C_TypeDef* I2Cx,I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_SetBaud(I2Cx,I2C_InitStruct->I2C_Baud); + I2C_BaudGeneratorEnable(I2Cx,I2C_InitStruct->I2C_BaudEn); + I2C_FilterConfig(I2Cx,I2C_InitStruct->I2C_FLT); + I2C_AcknowledgeConfig(I2Cx,I2C_InitStruct->I2C_AA); + + if(I2C_InitStruct->I2C_Baud<=9) + { + I2C_FilterConfig(I2Cx,ENABLE); + } + +} + +/** + * @brief I2C:SLAVEʼ + * + * @param I2Cx : I2C1 I2C2 + * @param I2C_InitStruct + */ +void I2C_Slave_Init(I2C_TypeDef* I2Cx,I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_FilterConfig(I2Cx,ENABLE); + I2C_AcknowledgeConfig(I2Cx,I2C_InitStruct->I2C_AA); + + I2C_SetOwnSlaveAddress0(I2Cx,I2C_InitStruct->I2C_OwnSlaveAddr0); + I2C_GcConfig(I2Cx,I2C_InitStruct->I2C_OwnGc); + I2C_SetOwnSlaveAddress1(I2Cx,I2C_InitStruct->I2C_OwnSlaveAddr1); + I2C_SetOwnSlaveAddress2(I2Cx,I2C_InitStruct->I2C_OwnSlaveAddr2); + +} + +/** + * @brief I2C1 رճʼ + * + */ +void I2C1_DeInit(void) + { + CW_SYSCTRL->APBRST1_f.I2C1 = 0; + CW_SYSCTRL->APBRST1_f.I2C1 = 1; + CW_I2C1->CR = 0x00; + } + +/** + * @brief I2C2 رճʼ + * + */ + void I2C2_DeInit(void) + { + CW_SYSCTRL->APBRST1_f.I2C2 = 0; + CW_SYSCTRL->APBRST1_f.I2C2 = 1; + CW_I2C2->CR = 0x00; + } + +/** + * @brief 1ֽ + * + * @param I2Cx : I2C1 I2C2 + * @param Data : 0x00 - 0xFF + */ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Write in the DR register the data to be sent */ + I2Cx->DR = Data; +} + +/** + * @brief 1ֽ + * + * @param I2Cx : I2C1 I2C2 + * @return uint8_t : 0x00 - 0xFF + */ +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the data in the DR register */ + return (uint8_t)I2Cx->DR; +} + +/** + * @brief ʱʹӻַֽ + * + * @param I2Cx : I2C1 I2C2 + * @param Address : 8BITãbitΪ01 + * @param I2C_Direction : I2C_Direction_Transmitter I2C_Direction_Receiver + */ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_Direction_Transmitter) + { + /* Set the address bit0 for read */ + Address |= 0x01; + } + else + { + /* Reset the address bit0 for write */ + Address &= 0xfe; + } + /* Send the address */ + I2Cx->DR = Address; +} + +/** + * @brief λI2C1 + * + * @param NewState : ENABLE DISABLE + */ +void I2C1_SoftwareResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + CW_SYSCTRL->APBRST1_f.I2C1 = 1; + } + else + { + /* Peripheral not under reset */ + CW_SYSCTRL->APBRST1_f.I2C1 = 0; + } +} + +/** + * @brief λI2C2 + * + * @param NewState : ENABLE DISABLE + */ +void I2C2_SoftwareResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + CW_SYSCTRL->APBRST1_f.I2C2 = 1; + } + else + { + /* Peripheral not under reset */ + CW_SYSCTRL->APBRST1_f.I2C2 = 0; + } +} + +/** + ****************************************************************************** + * @brief պöȡEEPROMʽȡʽҪдEEPROMĵַ + * + * @param I2Cx : I2C1 I2C2 + * @param u8Addr : ȡEEPROMڴַ + * @param pu8Data : ȡEEPROMݵַ + * @param u32Len : ȡEEPROMݳ + * + ******************************************************************************/ + void I2C_MasterReadEepomData(I2C_TypeDef *I2Cx,uint8_t u8Addr,uint8_t *pu8Data,uint32_t u32Len) +{ + uint8_t u8i=0,u8State; + + I2C_GenerateSTART(I2Cx, ENABLE); + + while(1) + { + while(0 == I2C_GetIrq(I2Cx)) + {} + u8State = I2C_GetState(I2Cx); + switch(u8State) + { + case 0x08: //STARTź + I2C_GenerateSTART(I2Cx, DISABLE); + I2C_Send7bitAddress(I2Cx, I2C_SLAVEADDRESS,0X00); //ʹӻַ + break; + case 0x18: //SLA+W/Rֽ + I2C_SendData(I2Cx,u8Addr); + break; + case 0x28: //1ֽݣEEPROMmemoryַҲͺҲ + I2C_GenerateSTART(I2Cx, ENABLE); + break; + case 0x10: //ظʼź + I2C_GenerateSTART(I2Cx, DISABLE); + I2C_Send7bitAddress(I2Cx, I2C_SLAVEADDRESS, 0X01); + break; + case 0x40: //SLA+Rźţʼ + if(u32Len>1) + { + I2C_AcknowledgeConfig(I2Cx,ENABLE); + } + break; + case 0x50: //һֽݣڽ1ֽ֮ǰAA=0; + pu8Data[u8i++] = I2C_ReceiveData(I2Cx); + if(u8i==u32Len-1) + { + I2C_AcknowledgeConfig(I2Cx,DISABLE); + } + break; + case 0x58: //յһֽڣNACKѻظ + pu8Data[u8i++] = I2C_ReceiveData(I2Cx); + I2C_GenerateSTOP(I2Cx, ENABLE); + break; + case 0x38: //ڷ SLA+W ׶λ߷ݽ׶ζʧٲ ڷ SLA+R ׶λ߻Ӧ NACK ׶ζʧٲ + I2C_GenerateSTART(I2Cx, ENABLE); + break; + case 0x48: //SLA+RӻNACK + I2C_GenerateSTOP(I2Cx, ENABLE); + I2C_GenerateSTART(I2Cx, ENABLE); + break; + default: + I2C_GenerateSTART(I2Cx, ENABLE);//״̬·ʼ + break; + } + I2C_ClearIrq(I2Cx); + if(u8i==u32Len) + { + break; + } + } +} + +/** + ****************************************************************************** + * @brief ͺöȡEEPROMʽȡʽҪдEEPROMĵַ + * + * @param I2Cx : I2C1 I2C2 + * @param u8Addr : дEEPROMڴַ + * @param pu8Data : дݴŵַ + * @param u32Len : дݳ + * + ******************************************************************************/ + +void I2C_MasterWriteEepromData(I2C_TypeDef *I2Cx,uint8_t u8Addr,uint8_t *pu8Data,uint32_t u32Len) +{ + uint8_t u8i=0,u8State; + I2C_GenerateSTART(I2Cx, ENABLE); + while(1) + { + while(0 == I2C_GetIrq(I2Cx)) + {;} + u8State = I2C_GetState(I2Cx); + switch(u8State) + { + case 0x08: //STARTź + I2C_GenerateSTART(I2Cx, DISABLE); + I2C_Send7bitAddress(I2Cx, I2C_SLAVEADDRESS,0X00); //豸ַ + break; + case 0x18: //SLA+Wź,ACKյ + I2C_SendData(I2Cx,u8Addr);//豸ڴַ + break; + case 0x28: //1ֽݣEEPROMmemoryַҲͺҲ + I2C_SendData(I2Cx,pu8Data[u8i++]); + break; + case 0x20: //SLA+WӻNACK + case 0x38: //ڷ SLA+W ׶λ߷ݽ׶ζʧٲ ڷ SLA+R ׶λ߻Ӧ NACK ׶ζʧٲ + I2C_GenerateSTART(I2Cx, ENABLE); + break; + case 0x30: //һֽںӻNACK + I2C_GenerateSTOP(I2Cx, ENABLE); + break; + default: + break; + } + if(u8i>u32Len) + { + I2C_GenerateSTOP(I2Cx, ENABLE);//˳ֹܵͣ + I2C_ClearIrq(I2Cx); + break; + } + I2C_ClearIrq(I2Cx); + } +} + +/** + ****************************************************************************** + * @brief պMCU֮ͨ + * + * @param I2Cx : I2C1 I2C2 + * @param pu8Data : ݴŵַ + * @param u32Len : ݳ + * + ******************************************************************************/ + void I2C_MasterRecDataFromSlave(I2C_TypeDef *I2Cx,uint8_t *pu8Data,uint32_t u32Len) +{ + uint8_t u8i=0,u8State; + + I2C_GenerateSTART(I2Cx, ENABLE); + + while(1) + { + while(0 == I2C_GetIrq(I2Cx)) + {} + u8State = I2C_GetState(I2Cx); + switch(u8State) + { + case 0x08: //STARTź + case 0x10: //ظʼź + I2C_GenerateSTART(I2Cx, DISABLE); + I2C_Send7bitAddress(I2Cx, I2C_SLAVEADDRESS,0X01); //ʹӻַ+Rֽ + break; + case 0x40: //SLA+Rźţʼ + if(u32Len>1) + { + I2C_AcknowledgeConfig(I2Cx,ENABLE); + } + break; + case 0x50: //һֽݣڽ1ֽ֮ǰAA=0; + pu8Data[u8i++] = I2C_ReceiveData(I2Cx); + if(u8i==u32Len-1) + { + I2C_AcknowledgeConfig(I2Cx,DISABLE); + } + break; + case 0x58: //յһֽڣNACKѻظ + pu8Data[u8i++] = I2C_ReceiveData(I2Cx); + I2C_GenerateSTOP(I2Cx, ENABLE); + break; + case 0x38: //ڷ SLA+W ׶λ߷ݽ׶ζʧٲ ڷ SLA+R ׶λ߻Ӧ NACK ׶ζʧٲ + I2C_GenerateSTART(I2Cx, ENABLE); + break; + case 0x48: //SLA+RӻNACK + I2C_GenerateSTOP(I2Cx, ENABLE); + I2C_GenerateSTART(I2Cx, ENABLE); + break; + default: + I2C_GenerateSTART(I2Cx, ENABLE);//״̬·ʼ + break; + } + I2C_ClearIrq(I2Cx); + if(u8i==u32Len) + { + break; + } + } +} + +/** + ****************************************************************************** + * @brief ͺMCU֮ͨ + * + * @param I2Cx : I2C1 I2C2 + * @param pu8Data : ݴŵַ + * @param u32Len : ݳ + * + ******************************************************************************/ +void I2C_MasterSendDataToSlave(I2C_TypeDef *I2Cx,uint8_t *pu8Data,uint32_t u32Len) +{ + uint8_t u8i = 0; + uint8_t u8State; + + I2C_GenerateSTART(I2Cx, ENABLE); + while(1) + { + while(0 == I2C_GetIrq(I2Cx)) + {;} + u8State = I2C_GetState(I2Cx); + switch(u8State) + { + case 0x08: //STARTź + I2C_GenerateSTART(I2Cx, DISABLE); + I2C_Send7bitAddress(I2Cx, I2C_SLAVEADDRESS,0X00); //豸ַ+W + break; + case 0x18: //SLA+Wź + case 0x28: //1ֽݣEEPROMmemoryַҲͺҲ + I2C_SendData(I2Cx,pu8Data[u8i++]); + break; + case 0x20: //SLA+WӻNACK + case 0x38: //ڷ SLA+W ׶λ߷ݽ׶ζʧٲ ڷ SLA+R ׶λ߻Ӧ NACK ׶ζʧٲ + I2C_GenerateSTART(I2Cx, ENABLE); + break; + case 0x30: //һֽںӻNACK + I2C_GenerateSTOP(I2Cx, ENABLE); + break; + default: + break; + } + if(u8i>u32Len) + { + I2C_GenerateSTOP(I2Cx, ENABLE);//˳ֹܵͣ + I2C_ClearIrq(I2Cx); + break; + } + I2C_ClearIrq(I2Cx); + } +} + + +/** + * @brief ӻͺMCU֮ͨ + * + * @param I2Cx : I2C1 I2C2 + * @param pu8Data : ݴŵַ + * @param u32Len : ݳ + */ +void I2C_SlaveSendDataToMaster(I2C_TypeDef* I2Cx,uint8_t *pu8Data,uint32_t *u32Len) +{ + uint8_t u8i=0,u8State; + while(1) + { + while(0 == I2C_GetIrq(I2Cx)) + {} + u8State = I2C_GetState(I2Cx); + switch(u8State) + { + case 0xA8: //յSLA+R,ACKѻӦ + case 0xB0: //ʧٲúתӻSLA+RѰַACKѻӦ + I2C_SendData(I2Cx,pu8Data[u8i++]); + break; + case 0xB8: //ӻѷ1ֽݣACKյ + I2C_SendData(I2Cx,pu8Data[u8i++]); + break; + case 0xC8: //ӻһֽѱ(ǰAAΪ0)ѽյACK +// I2C_SendData(I2Cx,pu8Data[u8i++]); //Ҫ +// break; + case 0xC0: //ѷֽڣѽ NACK + break; + default: + break; + } + + I2C_ClearIrq(I2Cx); + + if((0xC0 == u8State) || (0xC8 == u8State)) + { + break; + } + + } + } + +/** + * @brief ӻպMCU֮ͨ + * + * @param I2Cx : I2C1 I2C2 + * @param pu8Data : ݴŵַ + * @param u32Len : ݳ + */ +void I2C_SlaveRecDataFromMaster(I2C_TypeDef* I2Cx,uint8_t *pu8Data,uint32_t *pu32Len) +{ + uint8_t u8i=0,u8State; + while(1) + { + while(0 == I2C_GetIrq(I2Cx)) + {} + u8State = I2C_GetState(I2Cx); + switch(u8State) + { + case 0x60: //յSLA+WACKѻӦ + case 0x68: //ʧٲúSLA+WѰַACKѻӦ + case 0x70: //յSLA㲥ַ+WACKѻӦ + case 0x78: //ʧٲúSLA㲥ַ+WѰַACKѻӦ + break; + case 0x80: //ӻѽյ1ֽݣACKѻظ + case 0x90: //ӻѽյ1ֽڹ㲥ݣACKѻظ + case 0x88: //ӻѽյ1ֽݣNACKѻӦ + case 0x98: //ӻѽյ1ֽݣNACKѻӦ + pu8Data[u8i++] = I2C_ReceiveData(I2Cx); + break; + case 0xA0: //ظSTARTźŻSTOPźյ + *pu32Len = u8i; + break; + default: + break; + } + I2C_ClearIrq(I2Cx); + if(0xA0 == u8State) + { + break; + } + } +} + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_iwdt.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_iwdt.c new file mode 100644 index 0000000..d327407 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_iwdt.c @@ -0,0 +1,201 @@ +/** + * @file cw32f030_iwdt.c + * @author P&S (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-04-25 + * + * @copyright Copyright (c) 2021 + * + */ +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_iwdt.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief IWDTȥʼ + */ +void IWDT_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.IWDT = 0; + CW_SYSCTRL->APBRST1_f.IWDT = 1; +} + +/** + * @brief IWDTʼ + * @param IWDT_InitStruct ýṹIWDTҪõIJ + */ +void IWDT_Init(IWDT_InitTypeDef *IWDT_InitStruct) +{ + assert_param(IS_IWDT_PRESCALER(IWDT_InitStruct->IWDT_Prescaler)); + assert_param(IS_IWDT_ACTION(IWDT_InitStruct->IWDT_OverFlowAction)); + assert_param(IS_IWDT_SLEEP_MODE(IWDT_InitStruct->IWDT_Pause)); + assert_param(IS_IWDT_WINDOW_VALUE(IWDT_InitStruct->IWDT_WindowValue)); + assert_param(IS_IWDT_RELOAD(IWDT_InitStruct->IWDT_ReloadValue)); + + __IWDT_RUN(); // ҪIWDT󣬲޸Ĵ + __IWDT_UNLOCK(); // Ĵ + if (IWDT_InitStruct->IWDT_ITState == ENABLE) + { + CW_IWDT->CR = IWDT_InitStruct->IWDT_Prescaler | \ + IWDT_InitStruct->IWDT_OverFlowAction | \ + IWDT_CR_IE_Msk | IWDT_InitStruct->IWDT_Pause; + } + else + { + CW_IWDT->CR = (IWDT_InitStruct->IWDT_Prescaler | \ + IWDT_InitStruct->IWDT_OverFlowAction | \ + IWDT_InitStruct->IWDT_Pause); + } + + CW_IWDT->ARR = IWDT_InitStruct->IWDT_ReloadValue; + CW_IWDT->WINR = IWDT_InitStruct->IWDT_WindowValue; + + __IWDT_LOCK(); +} + +/** + * @brief IWDT + */ +void inline IWDT_Cmd(void) +{ + __IWDT_RUN(); +} + +/** + * @brief ι + */ +void inline IWDT_Refresh(void) +{ + __IWDT_REFRESH(); +} + +/** + * @brief Ĵ + */ +void inline IWDT_Unlock(void) +{ + __IWDT_UNLOCK(); +} + +/** + * @brief Ĵ + */ +void inline IWDT_Lock(void) +{ + __IWDT_LOCK(); +} + +/** + * @brief ֹͣIWDT + */ +void inline IWDT_Stop(void) +{ + __IWDT_STOP(); +} + +/** + * @brief IWDTԤƵ + * @param IWDT_Prescaler ȡֵΧ IWDT_Prescaler_DIV4~IWDT_Prescaler_DIV512 + */ +void IWDT_SetPrescaler(uint32_t IWDT_Prescaler) +{ + assert_param(IS_IWDT_PRESCALER(IWDT_Prescaler)); + + __IWDT_UNLOCK(); + while(CW_IWDT->SR & IWDT_SR_CRF_Msk); + CW_IWDT->CR_f.PRS = IWDT_Prescaler; + __IWDT_LOCK(); +} + +/** + * @brief IWDTĴֵ + * @param WindowValue ȡֵΧ0x00000000~0x00000FFF,ֵΪ0x00000FFFʱڹܲ + */ +void IWDT_SetWindowValue(uint32_t WindowValue) +{ + assert_param(IS_IWDT_WINDOW_VALUE(WindowValue)); + + __IWDT_UNLOCK(); + while(CW_IWDT->SR & IWDT_SR_WINRF_Msk); + CW_IWDT->WINR = WindowValue; + __IWDT_LOCK(); +} + +/** + * @brief IWDTؼĴֵ + * @param ReloadValue ȡֵΧ0x00000000~0x00000FFF + */ +void IWDT_SetReloadValue(uint32_t ReloadValue) +{ + assert_param(IS_IWDT_RELOAD(ReloadValue)); + + __IWDT_UNLOCK(); + while(CW_IWDT->SR & IWDT_SR_ARRF_Msk); + CW_IWDT->ARR = ReloadValue; + __IWDT_LOCK(); +} + +/** + * @brief IWDTжʹ + * @param NewState IWDTжʹλ״̬ ΧENABLEDISABLE + */ +void IWDT_ITConfig(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + __IWDT_UNLOCK(); + while(CW_IWDT->SR & IWDT_SR_CRF_Msk); + NewState ? (CW_IWDT->CR_f.IE = ENABLE):(CW_IWDT->CR_f.IE = DISABLE); + __IWDT_LOCK(); +} + +/** + * @brief ȡIWDT״̬ + * @param StatusBit ״̬λλ,ȡֵΧΪIWDT_SR_CRF_Msk + * IWDT_SR_ARRF_Msk + * IWDT_SR_WINRF_Msk + * IWDT_SR_OV_Msk + * IWDT_SR_RUN_Msk + * IWDT_SR_RELOAD_Msk + * + * @return FlagStatus + */ +FlagStatus IWDT_GetFlagStatus(uint32_t StatusBit) +{ + return (FlagStatus)(CW_IWDT->SR & StatusBit); +} + +/** + * @brief IWDT־OV + */ +void inline IWDT_ClearOVFlag(void) +{ + CW_IWDT->SR_f.OV = 0; +} + +/** + * @brief + * @return uint32_t IWDTļֵ + */ +uint32_t IWDT_GetCounterValue(void) +{ + uint32_t tmp1, tmp2; + do { + tmp1 = CW_IWDT->CNT; + tmp2 = CW_IWDT->CNT; + }while(tmp1 != tmp2); + + return tmp1; +} diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_lvd.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_lvd.c new file mode 100644 index 0000000..542a50a --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_lvd.c @@ -0,0 +1,302 @@ +/** + * @file cw32f030_lvd.c + * @author P&S (you@domain.com) + * @brief + * @version 0.1 + * @file cw32f030_lvd.c + * @author P&S (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-07-27 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉力源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉力源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉力源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "cw32f030.h" +#include "cw32f030_lvd.h" + +/** + ****************************************************************************** + ** \addtogroup LvdGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#define IS_VALID_INPUT(x) ( (x) <= LvdInputPB11 ) + +#define IS_VALID_THRESHOLD(x) ( (x) <= LvdTH3p3V ) + +#define IS_VALID_CLK(x) ( (x) <= LvdFilterHsi ) + +#define IS_VALID_FILTER(x) ( (x) <= LvdFilter4095Clk ) + +#define IS_VALID_IRQTYPE(x) ( (x) <= LvdIrqFall ) + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') * + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** + * @brief + * 使能NVIC的LVD中断 + * + * @param intPriority:0~3 + * + * @return 无 + */ +void LVD_EnableNvic(uint8_t intPriority) +{ + NVIC_ClearPendingIRQ(LVD_IRQn); + NVIC_SetPriority(LVD_IRQn, intPriority); + NVIC_EnableIRQ(LVD_IRQn); +} + +/** + * @brief + * 停止NVIC的LVD中断 + * + * @param 无 + * + * @return 无 + */ +void LVD_DisableNvic(void) +{ + NVIC_ClearPendingIRQ(LVD_IRQn); + NVIC_DisableIRQ(LVD_IRQn); +} + +/** + * @brief + * 配置LVD中断/系统复位触发方式 + * + * @param LVD_TRIG: + * @arg LVD_TRIG_LEVEL + * @arg LVD_TRIG_FALL + * @arg LVD_TRIG_RISE + * @param NewState: + * @arg DISABLE + * @arg ENABLE + * + * @return 无 + */ +void LVD_TrigConfig(uint16_t LVD_TRIG, FunctionalState NewState) +{ + uint8_t itMask = 0; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_LVD_TRIG(LVD_TRIG)); + /* Get the LVD TRIG index */ + itMask = (uint8_t) LVD_TRIG; + if (NewState != DISABLE) + { + /* Enable the selected LVD interrupts */ + CW_LVD->CR1 |= itMask; + } + else + { + /* Disable the selected LVD interrupts */ + CW_LVD->CR1 &= (~(uint32_t) itMask); + } +} + +/** + * @brief + * 使能LVD中断 + * + * @param intPriority:0~3 + * + * @return + */ +void LVD_EnableIrq(uint8_t intPriority) +{ + REGBITS_SET(CW_LVD->CR0, LVD_CR0_IE_Msk); + LVD_EnableNvic(intPriority); +} + +/** + * @brief + * 禁止LVD中断 + * + * @param 无 + * + * @return 无 + */ +void LVD_DisableIrq(void) +{ + LVD_DisableNvic(); + REGBITS_CLR(CW_LVD->CR0, LVD_CR0_IE_Msk); + REGBITS_CLR(CW_LVD->CR1 , LVD_CR1_LEVEL_Msk | LVD_CR1_FALL_Msk | LVD_CR1_RISE_Msk); +} + +/** + * @brief + * LVD初始化 + * + * @param LVD_InitStruct + * + * @return 无 + */ +void LVD_Init(LVD_InitTypeDef* LVD_InitStruct) +{ + ASSERT(LVD_InitStruct); + assert_param(IS_LVD_ACTION(LVD_InitStruct->LVD_Action)); + assert_param(IS_LVD_SOURCE(LVD_InitStruct->LVD_Source)); + assert_param(IS_LVD_THRESHOLD(LVD_InitStruct->LVD_Threshold)); + assert_param(IS_LVD_FILTER_CLK(LVD_InitStruct->LVD_FilterClk)); + assert_param(IS_LVD_FILTER_TIME(LVD_InitStruct->LVD_FilterTime)); + assert_param(IS_LVD_FILTER(LVD_InitStruct->LVD_FilterEn)); + + //Need to DISABLE first. + LVD_Disable(); + LVD_DisableIrq(); + + REGBITS_MODIFY( CW_LVD->CR1 , LVD_CR1_FLTCLK_Msk | LVD_CR1_FLTTIME_Msk | LVD_CR1_FLTEN_Msk, \ + (LVD_InitStruct->LVD_FilterClk | \ + LVD_InitStruct->LVD_FilterTime | \ + LVD_InitStruct->LVD_FilterEn)); + + REGBITS_MODIFY( CW_LVD->CR0 , LVD_CR0_VTH_Msk | LVD_CR0_SOURCE_Msk | LVD_CR0_ACTION_Msk, \ + (LVD_InitStruct->LVD_Threshold | \ + LVD_InitStruct->LVD_Source | \ + LVD_InitStruct->LVD_Action)); +} + +/** + * @brief + * LVD deinit + * + * @param 无 + * + * @return 无 + */ +void LVD_DeInit(void) +{ + LVD_DisableIrq(); + LVD_Disable(); +} + +/** + * @brief + * 使能LVD + * + * @param 无 + * + * @return 无 + */ +void LVD_Enable(void) +{ + REGBITS_SET(CW_LVD->CR0, LVD_CR0_EN_Msk); +} + +/** + * @brief + * 停止LVD + * + * @param 无 + * + * @return 无 + */ +void LVD_Disable(void) +{ + REGBITS_CLR(CW_LVD->CR0, LVD_CR0_EN_Msk); +} + +/** + * @brief + * 获取LVD中断标志 + * + * @param 无 + * + * @return boolean_t: TRUE or FALSE + */ +boolean_t LVD_GetIrqStatus(void) +{ + return (boolean_t)(REGBITS_GET(CW_LVD->SR, LVD_SR_INTF_Msk)); +} + +/** + * @brief + * 获取LVD指定的中断状态 + * + * @param LVD_FLAG: + * @arg LVD_FLAG_FLTV + * @arg LVD_FLAG_INTF + * + * @return FlagStatus: SET or RESET + */ +FlagStatus LVD_GetFlagStatus(uint16_t LVD_FLAG) +{ + assert_param(IS_LVD_GET_FLAG(FLAG)(LVD_FLAG)); + return (REGBITS_GET(CW_LVD->SR, LVD_FLAG) ? SET : RESET); +} + +/** + * @brief + * 清除LVD中断标志 + * + * @param 无 + * + * @return 无 + */ +void LVD_ClearIrq(void) +{ + REGBITS_CLR(CW_LVD->SR, LVD_SR_INTF_Msk); +} + +/** + * @brief + * 获取Filter结果 + * + * @param 无 + * + * @return boolean_t: TRUE or FALSE + */ +boolean_t LVD_GetFilterResult(void) +{ + return (boolean_t)(REGBITS_GET(CW_LVD->SR, LVD_SR_FLTV_Msk)); +} +//@} // LvdGroup + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_pwr.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_pwr.c new file mode 100644 index 0000000..ec37d41 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_pwr.c @@ -0,0 +1,113 @@ +/** + * @file cw32f030_pwr.c + * @author P&S (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-06-19 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "cw32f030.h" +#include "cw32f030_pwr.h" + +/** + ******************************************************************************* + ** \addtogroup LpmGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +/* +#define IS_VALID_SEVONPEND(x) (SevPndDisable == (x) ||\ + SevPndEnable == (x)) +#define IS_VALID_SLEEPDEEP(x) (SlpDpDisable == (x) ||\ + SlpDpEnable == (x)) +#define IS_VALID_SLEEPONEXIT(x) (SlpExtDisable == (x) ||\ + SlpExtEnable == (x)) +*/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief ͹ģʽ + * + * @param PWR_InitTypeDef ͹ģʽýṹָ + * + * @return + */ +void PWR_Config(PWR_InitTypeDef* PWR_InitTypeDef) +{ + ASSERT(NULL != PWR_InitTypeDef); + assert_param(IS_PWR_SEVONPEND(PWR_InitTypeDef->PWR_Sevonpend)); + assert_param(IS_PWR_SLEEPDEEP(PWR_InitTypeDef->PWR_SleepDeep)); + assert_param(IS_PWR_SLEEPONEXIT(PWR_InitTypeDef->PWR_SleepOnExit)); + +/* + SCB->SCR = PWR_InitTypeDef->PWR_Sevonpend ? (SCB->SCR | SCB_SCR_SEVONPEND_Msk) : (SCB->SCR & ~SCB_SCR_SEVONPEND_Msk); + SCB->SCR = PWR_InitTypeDef->PWR_SleepDeep ? (SCB->SCR | SCB_SCR_SLEEPDEEP_Msk) : (SCB->SCR & ~SCB_SCR_SLEEPDEEP_Msk); + SCB->SCR = PWR_InitTypeDef->PWR_SleepOnExit ? (SCB->SCR | SCB_SCR_SLEEPONEXIT_Msk) : (SCB->SCR & ~SCB_SCR_SLEEPONEXIT_Msk); +*/ + + REGBITS_MODIFY(SCB->SCR, SCB_SCR_SEVONPEND_Msk | \ + SCB_SCR_SLEEPDEEP_Msk | \ + SCB_SCR_SLEEPONEXIT_Msk, \ + PWR_InitTypeDef->PWR_Sevonpend | \ + PWR_InitTypeDef->PWR_SleepDeep | \ + PWR_InitTypeDef->PWR_SleepOnExit); +} + +/** + * @brief ˯ģʽ + * + * @return + */ +void PWR_GotoLpmMode(void) +{ + __WFI(); +} + +//@} // LpmGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_ram.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_ram.c new file mode 100644 index 0000000..09d6c34 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_ram.c @@ -0,0 +1,99 @@ +/** + * @file cw32f030_ram.c + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-14 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_ram.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief RAMж + * + * @param RAM_IT : RAM_IT_PARITY + * @param NewState : ENABLE DISABLE + */ +void RAM_ITConfig(uint32_t RAM_IT, FunctionalState NewState) +{ + assert_param(IS_RAM_IT(RAM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + CW_RAM->IER |= RAM_IT; + } + else + { + CW_RAM->IER &= (~RAM_IT); + } +} + +/** + * @brief ȡRAMжϱ־ + * + * @param RAM_IT : RAM_IT_PARITY + * @return ITStatus : SET RESET + */ +ITStatus RAM_GetITStatus(uint32_t RAM_IT) +{ + assert_param(IS_RAM_GET_IT(RAM_IT)); + + return (CW_RAM->ISR & RAM_IT) ? SET : RESET; +} + +/** + * @brief RAMжϱ־ + * + * @param RAM_IT : RAM_IT_PARITY + */ +void RAM_ClearITPendingBit(uint32_t RAM_IT) +{ + assert_param(IS_RAM_IT(RAM_IT)); + + CW_RAM->ICR &= (~RAM_IT); +} + +/** + * @brief ȡżУRAMַ + * + * @return uint32_t + */ +uint32_t RAM_GetErrorAddress(void) +{ + return (CW_RAM->ADDR); +} + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_rcc.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_rcc.c new file mode 100644 index 0000000..377565f --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_rcc.c @@ -0,0 +1,1075 @@ +/** + * @file cw32f030_rcc.c + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-13 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_rcc.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ +const uint32_t hsiprs_tbl[] = {6,6,6,6,6,6,1,3,2,4,6,8,10,12,14,16}; + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief SysClk HCLKķƵϵ + * + * @param HCLKPRS RCC_HCLK_DIV1/2/4/8/16/32/64/128 + */ +void RCC_HCLKPRS_Config(uint32_t HCLKPRS) +{ + assert_param(IS_RCC_HCLKPRS(HCLKPRS)); + CW_SYSCTRL->CR0 = ( (CW_SYSCTRL->CR0 & (~ (SYSCTRL_BYPASS_MASK | SYSCTRL_CR0_HCLKPRS_Msk))) | SYSCTRL_BYPASS | HCLKPRS ); +} +/** + * @brief HCLK PCLKķƵϵ + * + * @param PCLKPRS RCC_PCLK_DIV1/2/4/8 + */ +void RCC_PCLKPRS_Config(uint32_t PCLKPRS) +{ + assert_param(IS_RCC_HCLKPRS(PCLKPRS)); + CW_SYSCTRL->CR0 = ( (CW_SYSCTRL->CR0 & (~ (SYSCTRL_BYPASS_MASK | SYSCTRL_CR0_PCLKPRS_Msk))) | SYSCTRL_BYPASS | PCLKPRS ); +} + +/** + * @brief SysClkʱԴ + * + * @param SYSCLKSRC RCC_SYSCLKSRC_HSI RCC_SYSCLKSRC_HSE RCC_SYSCLKSRC_PLL + * RCC_SYSCLKSRC_LSI RCC_SYSCLKSRC_LSE + */ +void RCC_SYSCLKSRC_Config(uint32_t SYSCLKSRC) +{ + assert_param(IS_RCC_SYSCLKSRC(SYSCLKSRC)); + CW_SYSCTRL->CR0 = ( (CW_SYSCTRL->CR0 & (~ (SYSCTRL_BYPASS_MASK | SYSCTRL_CR0_SYSCLK_Msk))) | SYSCTRL_BYPASS | SYSCLKSRC ); + RCC_SystemCoreClockUpdate( RCC_Sysctrl_GetHClkFreq() ); +} + +/** + * @brief CLKCCS HSECCS LSECCS + * + * @param CCS RCC_SYSCTRL_LSECCS RCC_SYSCTRL_HSECCS RCC_SYSCTRL_CLKCCS + * @param NewState :ENABLE DISABLE + */ +void RCC_CCS_Config(uint32_t CCS,FunctionalState NewState) +{ + assert_param(IS_RCC_CCS_STATUS(CCS)); + + if (NewState != DISABLE) + { + CW_SYSCTRL->CR1 = ( ( (CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK) ) | SYSCTRL_BYPASS ) | CCS ); + } + else + { + CW_SYSCTRL->CR1 = ( ( (CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK) ) | SYSCTRL_BYPASS) & (~CCS) ); + } +} + +/** + * @brief LSELOCKܣʹܺ޷رLSEʱ + * + * @param LSELOCK RCC_SYSCTRL_LSELOCKEN RCC_SYSCTRL_LSELOCKDIS + */ +void RCC_LSELOCK_Config(uint32_t LSELOCK) +{ + assert_param(IS_RCC_LSELOCK_STATUS(LSELOCK)); + CW_SYSCTRL->CR1 = ( (CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK) ) | SYSCTRL_BYPASS | LSELOCK ); +} + +/** + * @brief WAKEUPCLK:ģʽѺʹõϵͳʱԴ + * + * @param WAKEUPCLK RCC_SYSCTRL_WAKEUPCLKEN RCC_SYSCTRL_WAKEUPCLKDIS + */ +void RCC_WAKEUPCLK_Config(uint32_t WAKEUPCLK) +{ + assert_param(IS_RCC_WAKEUPCLK_STATUS(WAKEUPCLK)); + CW_SYSCTRL->CR2 = ( (CW_SYSCTRL->CR2 & (~ ( SYSCTRL_BYPASS_MASK | SYSCTRL_CR2_WAKEUPCLK_Msk ) ) ) | SYSCTRL_BYPASS | WAKEUPCLK ); +} + +/** + * @brief LOCKܣ쳣ϺǷLOCKUPλ + * + * @param LOCKUP RCC_SYSCTRL_LOCKUPEN RCC_SYSCTRL_LOCKUPDIS + */ +void RCC_LOCKUP_Config(uint32_t LOCKUP) +{ + assert_param(IS_RCC_LOCKUP_STATUS(LOCKUP)); + CW_SYSCTRL->CR2 = ( (CW_SYSCTRL->CR2 & (~ ( SYSCTRL_BYPASS_MASK | SYSCTRL_CR2_LOCKUP_Msk ) ) ) | SYSCTRL_BYPASS | LOCKUP ); +} + +/** + * @brief ö˿SWDIO + * + * @param SWDIO RCC_SYSCTRL_SWDIOEN RCC_SYSCTRL_SWDIODIS + */ +void RCC_SWDIO_Config(uint32_t SWDIO) +{ + assert_param(IS_RCC_SWDIO_STATUS(SWDIO)); + CW_SYSCTRL->CR2 = ( (CW_SYSCTRL->CR2 & (~ ( SYSCTRL_BYPASS_MASK | SYSCTRL_CR2_SWDIO_Msk ) ) ) | SYSCTRL_BYPASS | SWDIO ); +} + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @param None + * @retval None + * CAUTION: + * 1LSEEN Bit Not Changed ,so it will not affect RTC,BUT LSELOCK BIT Changed. + * 2Before CALL this funciton,we should set FLASH_CR2.WAIT + */ +void RCC_DeInit(void) +{ + /* HSIEN Enable*/ + CW_SYSCTRL->CR1 = ( (CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK) ) | SYSCTRL_BYPASS | RCC_SYSCTRL_HSIEN ); + + //Here need wait HSI STBALE + while( (CW_SYSCTRL->HSI & SYSCTRL_HSI_STABLE_Msk) != SYSCTRL_HSI_STABLE_Msk ) //Wait stable + { + ; + } + + // CW_FLASH->CR2 = ( ((CW_FLASH->CR2) & (~ SYSCTRL_BYPASS_MASK) ) | (uint32_t)0x5A5A0001 ); + /* SWITCH TO HSI*/ + CW_SYSCTRL->CR0 = ( (CW_SYSCTRL->CR0 & (~ SYSCTRL_BYPASS_MASK) ) | SYSCTRL_BYPASS | RCC_SYSCLKSRC_HSI ); + + /* HCLKPRS SET TO 000,PCLKPRS SET TO 00*/ + CW_SYSCTRL->CR0 = ( (CW_SYSCTRL->CR0 & (~ SYSCTRL_BYPASS_MASK) ) | SYSCTRL_BYPASS | RCC_HCLK_DIV1 | \ + RCC_PCLK_DIV1 | RCC_SYSCLKSRC_HSI ); + + /* CLKCCS/HSECCS/LSECCS/LSELOCK/LSIEN/PLLEN/HSEEN Disable CLKCCS / LSEEN NO CHANGE*/ + CW_SYSCTRL->CR1 = ( ((CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK) ) | SYSCTRL_BYPASS | RCC_SYSCTRL_HSIEN) \ + & (~ RCC_SYSCTRL_CLKCCS) & (~ RCC_SYSCTRL_HSECCS) & (~ RCC_SYSCTRL_LSECCS) \ + & (~ RCC_SYSCTRL_LSELOCKEN) & (~ RCC_SYSCTRL_LSIEN) & (~ RCC_SYSCTRL_PLLEN) \ + & (~ RCC_SYSCTRL_HSEEN) ); + + /* SWDIO Enable,LOCKUP/WAKEUPCLK Disable*/ + CW_SYSCTRL->CR2 = ( ( ( ( (CW_SYSCTRL->CR2 & (~ SYSCTRL_BYPASS_MASK) ) | SYSCTRL_BYPASS ) \ + & (~ RCC_SYSCTRL_SWDIOEN) ) & (~ RCC_SYSCTRL_LOCKUPEN) ) & (~ RCC_SYSCTRL_WAKEUPCLKEN) ); + + /* Disable all interrupts */ + CW_SYSCTRL->IER = 0x5A5AFE00; //IER have KEY attribute + + /* Clear all pending bits */ + CW_SYSCTRL->ICR &= 0xFFFFFE00; + + //ʱӺ͸λĴ ?? + +} + +/** + * @brief + * + * @param NewFreq + */ +void RCC_SystemCoreClockUpdate(uint32_t NewFreq) +{ + SystemCoreClock = NewFreq; +} + +/** + * @brief ϵͳʱӣHCLKƵֵ + * + * @return uint32_t HCLKƵֵ(Hz) + */ +uint32_t RCC_Sysctrl_GetHClkFreq(void) +{ + uint32_t u32rtnVal = 0; + uint32_t sysclksource = 0; + uint32_t hsiprs = 0; + uint32_t pllmul = 0; + uint32_t pllrefclk = 0; + + sysclksource = CW_SYSCTRL->CR0_f.SYSCLK; + hsiprs = CW_SYSCTRL->HSI_f.DIV; + pllrefclk = CW_SYSCTRL->PLL_f.SOURCE; + pllmul = CW_SYSCTRL->PLL_f.MUL; + + switch (sysclksource) + { + case 0x00: /* HSI used as system clock */ + u32rtnVal = ( HSIOSC_VALUE / hsiprs_tbl[hsiprs] ); + break; + case 0x01: /* HSE used as system clock */ + u32rtnVal = HSE_VALUE; + break; + case 0x03: /* LSI used as system clock */ + u32rtnVal = LSI_VALUE; + break; + case 0x04: /* LSE used as system clock */ + u32rtnVal = LSE_VALUE; + break; + case 0x02: /* PLL used as system clock */ + switch (pllrefclk) + { + case 0x00: /* HSEOSC used as pll refclk */ + case 0x01: /* HSEIN used as pll refclk */ + u32rtnVal = ( HSE_VALUE * pllmul ) ; + break; + case 0x03: /* HSI used as pll refclk */ + u32rtnVal = ( ( HSIOSC_VALUE / hsiprs_tbl[hsiprs] ) * pllmul ) ; + break; + default: + u32rtnVal = ( ( HSIOSC_VALUE / hsiprs_tbl[hsiprs] ) * pllmul ) ; + break; + } + break; + default: + u32rtnVal = ( HSIOSC_VALUE / hsiprs_tbl[hsiprs] ) ; + break; + } + u32rtnVal = ( u32rtnVal >> CW_SYSCTRL->CR0_f.HCLKPRS ) ; + return u32rtnVal; +} + +/** + * @brief ʱӣPCLKƵֵ + * + * @return uint32_t PCLKƵֵ(Hz) + */ +uint32_t RCC_Sysctrl_GetPClkFreq(void) +{ + uint32_t u32Val = 0; + + u32Val = RCC_Sysctrl_GetHClkFreq(); + u32Val = ( u32Val >> (CW_SYSCTRL->CR0_f.PCLKPRS) ); + return u32Val; +} + +/** +* @brief Enable HSI +* @param HSIDiv: +* RCC_HSIOSC_DIV1 +* RCC_HSIOSC_DIV2 +* RCC_HSIOSC_DIV3 +* RCC_HSIOSC_DIV4 +* RCC_HSIOSC_DIV6 +* RCC_HSIOSC_DIV8 +* RCC_HSIOSC_DIV10 +* RCC_HSIOSC_DIV12 +* RCC_HSIOSC_DIV14 +* RCC_HSIOSC_DIV16 +* +* @retval None +*/ +void RCC_HSI_Enable(uint32_t HSIDiv ) +{ + assert_param(IS_RCC_HSIOSC_DIV(HSIDiv)); + + //CW_SYSCTRL->HSI_f.DIV = HSIDiv; + CW_SYSCTRL->HSI = ( HSIDiv << SYSCTRL_HSI_DIV_Pos ) | ( *((volatile uint16_t *)RCC_HSI_TRIMCODEADDR) ) ; //ʽоƬҪTrimֵ + CW_SYSCTRL->CR1 |= SYSCTRL_BYPASS | SYSCTRL_CR1_HSIEN_Msk ; //Enable HSI + while( (CW_SYSCTRL->HSI & SYSCTRL_HSI_STABLE_Msk) != SYSCTRL_HSI_STABLE_Msk ) //Wait stable + { + ; + } +} + +/** +* @brief Disable HSI +* @param None. +* @retval None. +*/ +void RCC_HSI_Disable(void) +{ + CW_SYSCTRL->CR1 = ( ( (CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK) ) | SYSCTRL_BYPASS ) & \ + (~SYSCTRL_CR1_HSIEN_Msk) ); +} + + +/** +* @brief Enable LSI +* @param None: +* @retval None +*/ +void RCC_LSI_Enable(void) +{ + CW_SYSCTRL->LSI = *((uint16_t *)RCC_LSI_TRIMCODEADDR); //ʽоƬҪTrimֵ + CW_SYSCTRL->LSI |= RCC_LSI_WAITCYCLE_258; //WaitCycle = 258 + CW_SYSCTRL->CR1 |= SYSCTRL_BYPASS | SYSCTRL_CR1_LSIEN_Msk; //Enable LSI + while( (CW_SYSCTRL->LSI & SYSCTRL_LSI_STABLE_Msk) != SYSCTRL_LSI_STABLE_Msk ) //Wait stable + { + ; + } +} + +/** +* @brief Disable LSI +* @param None. +* @retval None. +*/ +void RCC_LSI_Disable(void) +{ + CW_SYSCTRL->CR1 = ( ( (CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK) ) | SYSCTRL_BYPASS ) & \ + (~SYSCTRL_CR1_LSIEN_Msk) ); +} + + +/** +* @brief Enable HSE +* @param Mode: RCC_HSE_MODE_OSC: Oscillator, +* RCC_HSE_MODE_CLK: Input Clk +* +* @param FreqIn: 4000000Hz ~ 32000000Hz +* +* @param Driver: RCC_HSE_DRIVER_LEAST, +* RCC_HSE_DRIVER_SMALL, +* RCC_HSE_DRIVER_NORMAL, (default) +* RCC_HSE_DRIVER_LARGER +* +* @param Flt: RCC_HSE_FLT_OPEN, +* RCC_HSE_FLT_CLOSE +* +* @retval None + +16Mý飺 +Range: Ϊ2 +DriverΪ12 + +24Mý飺 +Range: Ϊ3 +DriverΪ1 + +32Mý飺 +Range: Ϊ3 +DriverΪ2 + +ע⣺1ѡصСľ +2Flt: ǿŻ,һ㲻 +*/ +void RCC_HSE_Enable(uint32_t Mode, uint32_t FreqIn, uint8_t Driver,uint32_t Flt) +{ + uint8_t freqRange = 0; + + // + assert_param(IS_RCC_HSE_MODE(Mode)); + assert_param(IS_RCC_HSE_FREQIN(FreqIn)); //FPGAע͵ʽ + assert_param(IS_RCC_HSE_DRIVER(Driver)); + assert_param(IS_RCC_HSE_FLT(Flt)); + + //HSEģʽIOڹ + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOF_Msk; //Open GPIOF Clk + if( Mode == RCC_HSE_MODE_OSC ) //Oscillator + { + CW_GPIOF->ANALOG |= ( bv0 | bv1 ); //PF00 PF01 as analog pin + } + else //Input clk + { + CW_GPIOF->ANALOG &= ~bv0; //PF00 as input clk pin + CW_GPIOF->DIR |= bv0; //PF00 input + CW_GPIOF->PUR &= ~bv0; + CW_GPIOF->PDR |= bv0; + } + + //ƵʲõӦֵ + freqRange = ( FreqIn == 32000000 ) ? 0x3UL : ( FreqIn / 8000000 ); + + //HSE + CW_SYSCTRL->HSE = (( 8000000000/FreqIn ) << 8 ) | \ + ( Mode | \ + ( RCC_HSE_WAITCYCLE_131072 ) | \ + ( ((uint32_t)freqRange << SYSCTRL_HSE_FREQ_Pos) ) | \ + ( Driver ) |\ + ( Flt ) ); + + //ʹHSE,ͬʱʹCLKCCSHSECCSʹʱʧЧл + CW_SYSCTRL->CR1 |= SYSCTRL_BYPASS | RCC_SYSCTRL_CLKCCS | SYSCTRL_CR1_HSECCS_Msk | SYSCTRL_CR1_HSEEN_Msk; //Enable HSE + + //ȴHSEȶ + while( (CW_SYSCTRL->HSE & SYSCTRL_HSE_STABLE_Msk) != SYSCTRL_HSE_STABLE_Msk ) //Wait stable + { + ; + } +} + +/** +* @brief Disable HSE +* @param None. +* @retval None. +*/ +void RCC_HSE_Disable(void) +{ + CW_SYSCTRL->CR1 = ( ( (CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK) ) | SYSCTRL_BYPASS ) & \ + (~SYSCTRL_CR1_HSEEN_Msk) ); +} + +/** +* @brief Enable LSE +* @param Mode: RCC_LSE_MODE_OSC: Oscillator, +* RCC_LSE_MODE_CLK: Input Clk +* @param Amp: RCC_LSE_AMP_LEAST, RCC_LSE_AMP_SMALL +* RCC_LSE_AMP_NORMALRCC_LSE_AMP_LARGER +* @param Driver: RCC_LSE_DRIVER_LEAST, RCC_LSE_DRIVER_SMALL +* RCC_LSE_DRIVER_NORMALRCC_LSE_DRIVER_LARGER +* +* @retval None + +ý飺 +AMP: Ϊ2RCC_LSE_AMP_NORMAL3RCC_LSE_AMP_LARGER +DriverΪ3RCC_LSE_DRIVER_LARGER +*/ +void RCC_LSE_Enable(uint32_t Mode,uint8_t Amp,uint8_t Driver) +{ + // + assert_param(IS_RCC_LSE_MODE(Mode)); + assert_param(IS_RCC_LSE_AMP(Amp)); + assert_param(IS_RCC_LSE_DRIVER(Driver)); + + //LSEģʽIO + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOC_Msk; //Open GPIOC clk + if( Mode == RCC_LSE_MODE_OSC ) //Oscillator + { + CW_GPIOC->ANALOG |= ( bv13 | bv14 ); //PC13 PC14 as analog pin + } + else //Input clk + { + CW_GPIOC->ANALOG &= ~bv14; //PC14 as input clk pin + CW_GPIOC->DIR |= bv14; //PC14 input + CW_GPIOC->PUR &= bv14; + CW_GPIOC->PDR |= bv14; + } + + //LSE + CW_SYSCTRL->LSE = ((Mode) | \ + (RCC_LSE_WAITCYCLE_16384) | \ + (Amp) | \ + (Driver)); + + //LSEʹ,ͬʱʹCLKCCSLSECCSʹʱʧЧл + CW_SYSCTRL->CR1 |= SYSCTRL_BYPASS | RCC_SYSCTRL_CLKCCS | SYSCTRL_CR1_LSECCS_Msk | SYSCTRL_CR1_LSEEN_Msk; //Enable LSE + + //ȴLSEȶ + while( (CW_SYSCTRL->LSE & SYSCTRL_LSE_STABLE_Msk) != SYSCTRL_LSE_STABLE_Msk ) //Wait stable + { + ; + } +} + +/** +* @brief Disable LSE +* @param None +* @retval None +*/ +void RCC_LSE_Disable(void) +{ + CW_SYSCTRL->CR1 = ( ( (CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK) ) | SYSCTRL_BYPASS ) & \ + (~SYSCTRL_CR1_LSEEN_Msk) ); +} + +/** +* @brief Enable PLL +* @param PLLSource: + RCC_PLLSOURCE_HSEOSC, + RCC_PLLSOURCE_HSECLK, + RCC_PLLSOURCE_HSI +* @param FreqIn: 4000000Hz ~ 24000000Hz +* @param PLLMul: 2~12 +* @retval None +*/ +void RCC_PLL_Enable(uint32_t PLLSource, uint32_t FreqIn, uint32_t PLLMul) +{ + uint8_t i = 0; + uint32_t freqInMsk = 0; + uint32_t freqOutMsk = 0; + uint32_t freqInTable[4] = { 6000000 , 12000000, 20000000, 24000001 }; + //uint32_t freqInTable[4] = { 6000000 , 12000000, 20000000, 32000001 }; //FPGAԴ + uint32_t freqOutTable[5] = { 18000000, 24000000, 36000000, 48000000, 72000001 }; + + // + assert_param(IS_RCC_PLLSOURCE(PLLSource)); + assert_param(IS_RCC_PLL_FREQIN(FreqIn)); //FPGAע͵ʽ + assert_param(IS_RCC_PLL_MUL(PLLMul)); + + //FREQINֵ + for( i = 0; i < (sizeof(freqInTable)/sizeof(freqInTable[0])); i++ ) + { + if( FreqIn < freqInTable[i] ) + { + freqInMsk = i; + break; + } + } + + ////FREQOUTֵ + freqOutMsk = FreqIn * PLLMul; + for( i = 0; i < (sizeof(freqOutTable)/sizeof(freqOutTable[0])); i++ ) + { + if( freqOutMsk < freqOutTable[i] ) + { + freqOutMsk = i; + break; + } + } + + //PLL + CW_SYSCTRL->PLL = ( RCC_PLL_WAITCYCLE_16384 | \ + ((uint32_t)( freqOutMsk << SYSCTRL_PLL_FREQOUT_Pos )) | \ + ((uint32_t)( PLLMul << SYSCTRL_PLL_MUL_Pos )) | \ + ((uint32_t)( freqInMsk << SYSCTRL_PLL_FREQIN_Pos )) | \ + ((uint32_t)( PLLSource << SYSCTRL_PLL_SOURCE_Pos ))); + + //ʹPLL + CW_SYSCTRL->CR1 |= SYSCTRL_BYPASS | SYSCTRL_CR1_PLLEN_Msk; //Enable PLL + + //ȴPLLʱȶ + while( (CW_SYSCTRL->PLL & SYSCTRL_PLL_STABLE_Msk) != SYSCTRL_PLL_STABLE_Msk ) + { + ; + } +} + +/** +* @brief Disable PLL +* @param None +* @retval None +*/ +void RCC_PLL_Disable(void) +{ + CW_SYSCTRL->CR1 = ( ( (CW_SYSCTRL->CR1 & (~ SYSCTRL_BYPASS_MASK) ) | SYSCTRL_BYPASS ) & \ + (~SYSCTRL_CR1_PLLEN_Msk) ); +} + +/** +* @brief CLKSRC switch +* @param NewClk: +* RCC_SYSCLKSRC_HSI, +* RCC_SYSCLKSRC_HSE, +* RCC_SYSCLKSRC_PLL, +* RCC_SYSCLKSRC_LSI, +* RCC_SYSCLKSRC_LSE +* @retval 0: PASS, 1: Fail +* +* NOTE:ô˺֮ǰҪ֤ʱԴѾʹܣENABLEѰȴʱȶ̣ +*/ + +uint8_t RCC_SysClk_Switch(uint32_t NewClk) +{ + assert_param(IS_RCC_SYSCLKSRC(NewClk)); + + CW_SYSCTRL->CR0 = ( (((CW_SYSCTRL->CR0 & (~ SYSCTRL_BYPASS_MASK) ) | SYSCTRL_BYPASS) & (~SYSCTRL_CR0_SYSCLK_Msk)) | (NewClk) ); + + RCC_SystemCoreClockUpdate( RCC_Sysctrl_GetHClkFreq() ); + + return ( ((CW_SYSCTRL->CR0 & SYSCTRL_CR0_SYSCLK_Msk) == NewClk) ? 0U : 1U ); +} + +/** + * @brief RCCж + * + * @param RCC_IT RCC_IT_HSEFAULT RCC_IT_LSEFAULT + * RCC_IT_HSEFAIL RCC_IT_LSEFAIL + * RCC_IT_LSERDY RCC_IT_LSIRDY + * RCC_IT_PLLRDY RCC_IT_HSERDY + * RCC_IT_HSIRDY + * @param NewState :ENABLE DISABLE + */ +void RCC_ITConfig(uint32_t RCC_IT, FunctionalState NewState) +{ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) //IER have KEY attribute + { + CW_SYSCTRL->IER = ((CW_SYSCTRL->IER & (~ SYSCTRL_BYPASS_MASK) ) | SYSCTRL_BYPASS) | RCC_IT; + } + else //IER have KEY attribute + { + CW_SYSCTRL->IER = ((CW_SYSCTRL->IER & (~ SYSCTRL_BYPASS_MASK) ) | SYSCTRL_BYPASS) & (~RCC_IT); + } +} + +/** + * @brief ȡRCCָж״̬ + * + * @param RCC_IT RCC_IT_HSEFAULT RCC_IT_LSEFAULT + * RCC_IT_HSEFAIL RCC_IT_LSEFAIL + * RCC_IT_LSERDY RCC_IT_LSIRDY + * RCC_IT_PLLRDY RCC_IT_HSERDY + * RCC_IT_HSIRDY + * @return ITStatus : SET RESET + */ +ITStatus RCC_GetITStatus(uint32_t RCC_IT) +{ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + return (CW_SYSCTRL->ISR & RCC_IT) ? SET : RESET; +} + + +/** + * @brief RCCָжϱ־ + * + * @param RCC_IT RCC_IT_HSEFAULT RCC_IT_LSEFAULT + * RCC_IT_HSEFAIL RCC_IT_LSEFAIL + * RCC_IT_LSERDY RCC_IT_LSIRDY + * RCC_IT_PLLRDY RCC_IT_HSERDY + * RCC_IT_HSIRDY + */ +void RCC_ClearITPendingBit(uint32_t RCC_IT) +{ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + CW_SYSCTRL->ICR &= (~RCC_IT); +} + +/** + * @brief ȡָʱԴȶ־ + * + * @param RCC_STABLEFLAG RCC_FLAG_HSISTABLE RCC_FLAG_HSESTABLE + * RCC_FLAG_PLLSTABLE RCC_FLAG_LSESTABLE + * RCC_FLAG_LSISTABLE + * @return FlagStatus SET RESET + */ +FlagStatus RCC_GetStableFlag(uint32_t RCC_STABLEFLAG) +{ + assert_param(IS_RCC_STABLEFLAG(RCC_STABLEFLAG)); + + return( ((CW_SYSCTRL->ISR) & RCC_STABLEFLAG) ? SET : RESET); +} + +/** + * @brief ȡʱԴȶ־ + * + * @return uint32_t ISRĴ + */ +uint32_t RCC_GetAllStableFlag( void ) +{ + return( CW_SYSCTRL->ISR ); +} + + +/** + * @brief AHBʱ + * + * @param Periph RCC_AHB_PERIPH_GPIOF RCC_AHB_PERIPH_GPIOC + * RCC_AHB_PERIPH_GPIOB RCC_AHB_PERIPH_GPIOA + * RCC_AHB_PERIPH_CRC RCC_AHB_PERIPH_FLASH + * RCC_AHB_PERIPH_DMA + * @param NewState ENABLE DISABLE + */ +void RCC_AHBPeriphClk_Enable(uint32_t Periph,FunctionalState NewState) +{ + assert_param(IS_RCC_AHB_PERIPH(Periph)); + + if (NewState != DISABLE) + { + CW_SYSCTRL->AHBEN |= Periph; + } + else + { + CW_SYSCTRL->AHBEN &= (~Periph); + } +} + +/** + * @brief APBʱ1 + * + * @param Periph RCC_APB1_PERIPH_I2C2 RCC_APB1_PERIPH_I2C1 + * RCC_APB1_PERIPH_UART3 RCC_APB1_PERIPH_UART2 + * RCC_APB1_PERIPH_SPI2 RCC_APB1_PERIPH_IWDT + * RCC_APB1_PERIPH_WWDT RCC_APB1_PERIPH_RTC + * RCC_APB1_PERIPH_GTIM2 RCC_APB1_PERIPH_GTIM1 + * @param NewState ENABLE DISABLE + */ +void RCC_APBPeriphClk_Enable1(uint32_t Periph,FunctionalState NewState) +{ + assert_param(IS_RCC_APB1_PERIPH(Periph)); + + if (NewState != DISABLE) + { + CW_SYSCTRL->APBEN1 |= Periph; + } + else + { + CW_SYSCTRL->APBEN1 &= (~Periph); + } +} + +/** + * @brief APBʱ2 + * + * @param Periph RCC_APB2_PERIPH_AWT RCC_APB2_PERIPH_BTIM + * RCC_APB2_PERIPH_GTIM4 RCC_APB2_PERIPH_GTIM3 + * RCC_APB2_PERIPH_UART1 RCC_APB2_PERIPH_SPI1 + * RCC_APB2_PERIPH_ATIM RCC_APB2_PERIPH_VC + * RCC_APB2_PERIPH_ADC + * @param NewState : ENABLE DISABLE + */ +void RCC_APBPeriphClk_Enable2(uint32_t Periph,FunctionalState NewState) +{ + assert_param(IS_RCC_APB1_PERIPH(Periph)); + + if (NewState != DISABLE) + { + CW_SYSCTRL->APBEN2 |= Periph; + } + else + { + CW_SYSCTRL->APBEN2 &= (~Periph); + } +} + +/** + * @brief AHB踴λ + * + * @param Periph RCC_AHB_PERIPH_GPIOF RCC_AHB_PERIPH_GPIOC + * RCC_AHB_PERIPH_GPIOB RCC_AHB_PERIPH_GPIOA + * RCC_AHB_PERIPH_CRC RCC_AHB_PERIPH_FLASH + * RCC_AHB_PERIPH_DMA + * @param NewState : ENABLE DISABLE + */ +void RCC_AHBPeriphReset(uint32_t Periph,FunctionalState NewState) +{ + assert_param(IS_RCC_AHB_PERIPH(Periph)); + + if (NewState != DISABLE) + { + CW_SYSCTRL->AHBRST |= Periph; + } + else + { + CW_SYSCTRL->AHBRST &= (~Periph); + } +} + +/** + * @brief APB踴λ1 + * + * @param Periph RCC_APB1_PERIPH_I2C2 RCC_APB1_PERIPH_I2C1 + * RCC_APB1_PERIPH_UART3 RCC_APB1_PERIPH_UART2 + * RCC_APB1_PERIPH_SPI2 RCC_APB1_PERIPH_IWDT + * RCC_APB1_PERIPH_WWDT RCC_APB1_PERIPH_RTC + * RCC_APB1_PERIPH_GTIM2 RCC_APB1_PERIPH_GTIM1 + * @param NewState : ENABLE DISABLE + */ +void RCC_APBPeriphReset1(uint32_t Periph,FunctionalState NewState) +{ + assert_param(IS_RCC_APB1_PERIPH(Periph)); + + if (NewState != DISABLE) + { + CW_SYSCTRL->APBRST1 |= Periph; + } + else + { + CW_SYSCTRL->APBRST1 &= (~Periph); + } +} + +/** + * @brief APB踴λ2 + * + * @param Periph RCC_APB2_PERIPH_AWT RCC_APB2_PERIPH_BTIM + * RCC_APB2_PERIPH_GTIM4 RCC_APB2_PERIPH_GTIM3 + * RCC_APB2_PERIPH_UART1 RCC_APB2_PERIPH_SPI1 + * RCC_APB2_PERIPH_ATIM RCC_APB2_PERIPH_VC + * RCC_APB2_PERIPH_ADC + * @param NewState : ENABLE DISABLE + */ +void RCC_APBPeriphReset2(uint32_t Periph,FunctionalState NewState) +{ + assert_param(IS_RCC_APB1_PERIPH(Periph)); + + if (NewState != DISABLE) + { + CW_SYSCTRL->APBRST2 |= Periph; + } + else + { + CW_SYSCTRL->APBRST2 &= (~Periph); + } +} + +/** + * @brief ȡָϵͳλ־ + * + * @param RCC_RSTFLAG RCC_FLAG_PINRST RCC_FLAG_PORRST + * RCC_FLAG_LVDRST RCC_FLAG_LOCKUPRST + * RCC_FLAG_IWDTRST RCC_FLAG_WWDTRST + * RCC_FLAG_SYSRESETREQRST + * @return FlagStatus SET RESET + */ +FlagStatus RCC_GetRstFlag(uint32_t RCC_RSTFLAG) +{ + assert_param(IS_RCC_RSTFLAG(RCC_RSTFLAG)); + + return( ((CW_SYSCTRL->RESETFLAG) & RCC_RSTFLAG) ? SET : RESET); +} + +/** + * @brief ȡλ־Ĵ + * + * @return uint32_t + */ +uint32_t RCC_GetAllRstFlag( void ) +{ + return( CW_SYSCTRL->RESETFLAG ); +} + +/** + * @brief ָȫλ־ + * + * @param RCC_RSTFLAG RCC_FLAG_PINRST RCC_FLAG_PORRST + * RCC_FLAG_LVDRST RCC_FLAG_LOCKUPRST + * RCC_FLAG_IWDTRST RCC_FLAG_WWDTRST + * RCC_FLAG_SYSRESETREQRST RCC_FLAG_ALLRST + * @return + */ +void RCC_ClearRstFlag(uint32_t RCC_RSTFLAG) +{ + assert_param(IS_RCC_RSTFLAG(RCC_RSTFLAG)); + CW_SYSCTRL->RESETFLAG &= (~RCC_RSTFLAG); +} + +/** + * @brief HCLK_OUTHCLKʱ + * + */ +void RCC_HCLK_OUT(void) +{ + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOA_Msk; + CW_GPIOA->ANALOG_f.PIN4 = 0U; + CW_GPIOA->DIR_f.PIN4 = 0U; + CW_GPIOA->AFRL_f.AFR4 = 4U; +} + +/** + * @brief PCLK_OUTPCLKʱ + * + */ +void RCC_PCLK_OUT(void) +{ + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOA_Msk; + CW_GPIOA->ANALOG_f.PIN3 = 0U; + CW_GPIOA->DIR_f.PIN3 = 0U; + CW_GPIOA->AFRL_f.AFR3 = 4U; +} + +/** + * @brief HSE_OUTHSEʱ + * + */ +void RCC_HSE_OUT(void) +{ + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOB_Msk; + CW_GPIOB->ANALOG_f.PIN2 = 0U; + CW_GPIOB->DIR_f.PIN2 = 0U; + CW_GPIOB->AFRL_f.AFR2 = 3U; +} + +/** + * @brief HSI_OUTHSIOSCʱ + * + */ +void RCC_HSI_OUT(void) +{ + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOB_Msk; + CW_GPIOB->ANALOG_f.PIN0 = 0U; + CW_GPIOB->DIR_f.PIN0 = 0U; + CW_GPIOB->AFRL_f.AFR0 = 5U; +} + +/** + * @brief LSE_OUTLSEʱ + * + */ +void RCC_LSE_OUT(void) +{ + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOB_Msk; + CW_GPIOB->ANALOG_f.PIN12 = 0U; + CW_GPIOB->DIR_f.PIN12 = 0U; + CW_GPIOB->AFRH_f.AFR12 = 3U; +} + +/** + * @brief LSI_OUTLSIʱ + * + */ +void RCC_LSI_OUT(void) +{ + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOB_Msk; + CW_GPIOB->ANALOG_f.PIN11 = 0U; + CW_GPIOB->DIR_f.PIN11 = 0U; + CW_GPIOB->AFRH_f.AFR11 = 1U; +} +/** + * @brief PLL_OUTPLLʱ + * + */ +void RCC_PLL_OUT(void) +{ + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOC_Msk; + CW_GPIOC->ANALOG_f.PIN13 = 0U; + CW_GPIOC->DIR_f.PIN13 = 0U; + CW_GPIOC->AFRH_f.AFR13 = 1U; +} + +/** + * @brief MCO_OUTָʱԴƵ + * + * @param Source RCC_MCO_SRC_NONE RCC_MCO_SRC_HCLK + * RCC_MCO_SRC_PCLK RCC_MCO_SRC_HSI + * RCC_MCO_SRC_LSI RCC_MCO_SRC_HSE + * RCC_MCO_SRC_LSE RCC_MCO_SRC_PLL + * RCC_MCO_SRC_RC150K RCC_MCO_SRC_RC10K + * @param Div RCC_MCO_DIV1/2/8/64/128/256/512/1024 + */ +void RCC_MCO_OUT(uint8_t Source, uint8_t Div) +{ + assert_param(IS_RCC_MCO_SRC(Source)); + assert_param(IS_RCC_MCO_DIV(Div)); + + CW_SYSCTRL->AHBEN |= SYSCTRL_AHBEN_GPIOA_Msk; //Open GPIOA clk + + CW_GPIOA->ANALOG &= ~GPIOx_ANALOG_PIN8_Msk; //Digit + CW_GPIOA->AFRH = ((CW_GPIOA->AFRH) & (~(uint32_t)(GPIOx_AFRH_AFR8_Msk))) | (uint32_t)(0x4U << GPIOx_AFRH_AFR8_Pos); + CW_GPIOA->DIR &= ~GPIOx_DIR_PIN8_Msk; //Output + + CW_SYSCTRL->MCO = (uint32_t)(Source | Div); +} + +/** + * @brief BTIM3ITRԴ + * + * @param Source RCC_TIMITR_BTIM1 RCC_TIMITR_BTIM2 + * RCC_TIMITR_GTIM1 RCC_TIMITR_GTIM2 RCC_TIMITR_GTIM3 RCC_TIMITR_GTIM4 + * RCC_TIMITR_ATIM + */ +void RCC_BTIM3ITRSelect(uint32_t Source) +{ + assert_param(IS_RCC_TIMITR_SOURCE(Source)); + + CW_SYSCTRL->TIMITR_f.BTIM3ITR = Source; +} + +/** + * @brief BTIM2ITRԴ + * + * @param Source RCC_TIMITR_BTIM1 RCC_TIMITR_BTIM3 + * RCC_TIMITR_GTIM1 RCC_TIMITR_GTIM2 RCC_TIMITR_GTIM3 RCC_TIMITR_GTIM4 + * RCC_TIMITR_ATIM + */ +void RCC_BTIM2ITRSelect(uint32_t Source) +{ + assert_param(IS_RCC_TIMITR_SOURCE(Source)); + + CW_SYSCTRL->TIMITR_f.BTIM2ITR = Source; +} + +/** + * @brief BTIM1ITRԴ + * + * @param Source RCC_TIMITR_BTIM2 RCC_TIMITR_BTIM3 + * RCC_TIMITR_GTIM1 RCC_TIMITR_GTIM2 RCC_TIMITR_GTIM3 RCC_TIMITR_GTIM4 + * RCC_TIMITR_ATIM + */ +void RCC_BTIM1ITRSelect(uint32_t Source) +{ + assert_param(IS_RCC_TIMITR_SOURCE(Source)); + + CW_SYSCTRL->TIMITR_f.BTIM1ITR = Source; +} + +/** + * @brief GTIM1ITRԴ + * + * @param Source RCC_TIMITR_BTIM1 RCC_TIMITR_BTIM2 RCC_TIMITR_BTIM3 + * RCC_TIMITR_GTIM2 RCC_TIMITR_GTIM3 RCC_TIMITR_GTIM4 + * RCC_TIMITR_ATIM + */ +void RCC_GTIM1ITRSelect(uint32_t Source) +{ + assert_param(IS_RCC_TIMITR_SOURCE(Source)); + + CW_SYSCTRL->TIMITR_f.GTIM1ITR = Source; +} + +/** + * @brief GTIM2ITRԴ + * + * @param Source RCC_TIMITR_BTIM1 RCC_TIMITR_BTIM2 RCC_TIMITR_BTIM3 + * RCC_TIMITR_GTIM1 RCC_TIMITR_GTIM3 RCC_TIMITR_GTIM4 + * RCC_TIMITR_ATIM + */ +void RCC_GTIM2ITRSelect(uint32_t Source) +{ + assert_param(IS_RCC_TIMITR_SOURCE(Source)); + + CW_SYSCTRL->TIMITR_f.GTIM2ITR = Source; +} + +/** + * @brief GTIM3ITRԴ + * + * @param Source RCC_TIMITR_BTIM1 RCC_TIMITR_BTIM2 RCC_TIMITR_BTIM3 + * RCC_TIMITR_GTIM1 RCC_TIMITR_GTIM2 RCC_TIMITR_GTIM4 + * RCC_TIMITR_ATIM + */ +void RCC_GTIM3ITRSelect(uint32_t Source) +{ + assert_param(IS_RCC_TIMITR_SOURCE(Source)); + + CW_SYSCTRL->TIMITR_f.GTIM3ITR = Source; +} + +/** + * @brief GTIM4ITRԴ + * + * @param Source RCC_TIMITR_BTIM1 RCC_TIMITR_BTIM2 RCC_TIMITR_BTIM3 + * RCC_TIMITR_GTIM1 RCC_TIMITR_GTIM2 RCC_TIMITR_GTIM3 + * RCC_TIMITR_ATIM + */ +void RCC_GTIM4ITRSelect(uint32_t Source) +{ + assert_param(IS_RCC_TIMITR_SOURCE(Source)); + + CW_SYSCTRL->TIMITR_f.GTIM4ITR = Source; +} + +/** + * @brief ATIMITRԴ + * + * @param Source RCC_TIMITR_BTIM1 RCC_TIMITR_BTIM2 RCC_TIMITR_BTIM3 + * RCC_TIMITR_GTIM1 RCC_TIMITR_GTIM2 RCC_TIMITR_GTIM3 + * + */ +void RCC_ATIMITRSelect(uint32_t Source) +{ + assert_param(IS_RCC_TIMITR_SOURCE(Source)); + + CW_SYSCTRL->TIMITR_f.ATIMITR = Source; +} + + + + + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_rtc.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_rtc.c new file mode 100644 index 0000000..fb0e9e6 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_rtc.c @@ -0,0 +1,661 @@ +/** + * @file cw32f030_rtc.c + * @author P&S (dvssy0@gmail.com) + * @brief + * @version 0.1 + * @date 2021-04-29 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_rtc.h" +#include "cw32f030_rcc.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief RTCȥʼ + * + */ +void RTC_DeInit(void) +{ + /* RTCĴд */ + CW_RTC->KEY_f.KEY = RTC_KEY_WORD1; + CW_RTC->KEY_f.KEY = RTC_KEY_WORD2; + + /* ԳRTC_CR0RTC_CR1RTC_CR2RTC_COMPEN⣬RTCĴĬֵ */ + CW_RTC->DATE = RTC_DATE_RESET_VALUE; + CW_RTC->TIME = RTC_TIME_RESET_VALUE; + CW_RTC->ALARMA = RTC_ALARMA_RESET_VALUE; + CW_RTC->ALARMB = RTC_ALARMB_RESET_VALUE; + CW_RTC->TAMPDATE = RTC_TAMPDATA_RESET_VALUE; + CW_RTC->TAMPTIME = RTC_TAMPTIME_RESET_VALUE; + CW_RTC->AWTARR = RTC_AWTARR_RESET_VALUE; + CW_RTC->IER = RTC_IER_RESET_VALUE; + CW_RTC->ICR = 0UL; // жϱ־λ + + /* ʹRTCĴд */ + CW_RTC->KEY_f.KEY = RTC_KEY_WORD1; + CW_RTC->KEY_f.KEY = RTC_KEY_LOCKW; + + /* λRTCģ飬RTC_CR0RTC_CR1RTC_CR2RTC_COMPENλΪĬֵ */ + CW_SYSCTRL->APBRST1_f.RTC = 0; + + /* رRTCģʱ */ + CW_SYSCTRL->APBEN1_f.RTC = 0; +} + +/** + * @brief RTCģʼ + * + * @param ʼRTCģ飬ûRTCʱԴԶRTC + * + * @return ErrorStatus ֵΪSUCCESSERROR + */ +ErrorStatus RTC_Init(RTC_InitTypeDef *RTC_InitStruct) +{ + assert_param(IS_RTC_RTCCLK_SOURCE(RTC_InitStruct->RTC_ClockSource)); + + CW_SYSCTRL->APBEN1_f.RTC = 1; // RTCʱӣʹRTCģ + RTC_Cmd(DISABLE); // ֹͣRTC֤ȷRTCĴ + + RTC_SetClockSource(RTC_InitStruct->RTC_ClockSource); // RTCʱԴ, ûRTCʱԴ + + if((RCC_GetAllRstFlag()&SYSCTRL_RESETFLAG_POR_Msk) == RCC_FLAG_PORRST) //ϵ縴λ,ʱ,H24־ + { + RTC_SetDate(&RTC_InitStruct->DateStruct); + RTC_SetTime(&RTC_InitStruct->TimeStruct); + } + else + { + RTC_UNLOCK(); + CW_RTC->CR0_f.H24 = RTC_InitStruct->TimeStruct.H24; + RTC_LOCK(); + } + CW_SYSCTRL->RESETFLAG=0; // λ־ + RTC_Cmd(ENABLE); + + return SUCCESS; +} + + +void RTC_Cmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + RTC_UNLOCK(); + + CW_RTC->CR0_f.START = NewState; + + RTC_LOCK(); +} + +/** + * @brief ȡжRTC״̬ + * + * @param RTC_ITState + * @return ITStatus + */ + +ITStatus RTC_GetITState(uint32_t RTC_ITState) +{ + uint32_t RegTmp; + assert_param(IS_RTC_GET_IT(RTC_ITState)); + do + { + RegTmp = CW_RTC->ISR; + } while (RegTmp != CW_RTC->ISR); + + return (RegTmp & RTC_ITState) ? SET : RESET; +} + +/** + * @brief жʹ + * + * @param RTC_IT + * @param NewState + */ +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) +{ + assert_param(IS_RTC_CONFIG_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + RTC_UNLOCK(); + +// CW_RTC->CR1_f.ACCESS = 1; +// while (!CW_RTC->CR1_f.WINDOW); + + if (!NewState) + { + CW_RTC->IER &= ~RTC_IT; + } + else + { + CW_RTC->IER |= RTC_IT; + } + +// CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +/** + * @brief жϱ־ + * + * @param RTC_IT + */ +void RTC_ClearITPendingBit(uint32_t RTC_IT) +{ + assert_param(IS_RTC_CLAER_IT(RTC_IT)); + + RTC_UNLOCK(); + +// CW_RTC->CR1_f.ACCESS = 1; +// while (!CW_RTC->CR1_f.WINDOW); + + CW_RTC->ICR = ~RTC_IT; + +// CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +/** + * @brief ʱ䣬HOURMINIUTESECONDΪBCDʽû뱣֤HOURAMPMH24֮Ĺȷ + * + * @param RTC_TimeStruct + */ +void RTC_SetTime(RTC_TimeTypeDef* RTC_TimeStruct) +{ + assert_param(IS_RTC_SECONDS(RTC_BCDToBin(RTC_TimeStruct->Second))); + assert_param(IS_RTC_MINUTES(RTC_BCDToBin(RTC_TimeStruct->Minute))); + if(RTC_TimeStruct->H24 == RTC_HOUR12) + assert_param(IS_RTC_HOUR12(RTC_BCDToBin(RTC_TimeStruct->Hour))); + else + assert_param(IS_RTC_HOUR24(RTC_BCDToBin(RTC_TimeStruct->Hour))); + + RTC_UNLOCK(); + + CW_RTC->CR0_f.H24 = RTC_TimeStruct->H24; + if(RTC_TimeStruct->H24 == RTC_HOUR12) + {CW_RTC->TIME = ((uint32_t)(RTC_TimeStruct->AMPM) << 21) | + ((uint32_t)(RTC_TimeStruct->Hour) << 16) | + ((uint32_t)(RTC_TimeStruct->Minute) << 8) | + ((uint32_t)(RTC_TimeStruct->Second)); + } + else + {CW_RTC->TIME = ((uint32_t)(RTC_TimeStruct->Hour) << 16) | + ((uint32_t)(RTC_TimeStruct->Minute) << 8) | + ((uint32_t)(RTC_TimeStruct->Second)); + } + + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +/** + * @brief + * ڣDAYMONTHYEARΪBCDʽΪ0~6գһ + * @param RTC_DateStruct + */ +void RTC_SetDate(RTC_DateTypeDef *RTC_DateStruct) +{ + assert_param(IS_RTC_YEAR(RTC_BCDToBin(RTC_DateStruct->Year))); + assert_param(IS_RTC_MONTH(RTC_BCDToBin(RTC_DateStruct->Month))); + assert_param(IS_RTC_DAY(RTC_BCDToBin(RTC_DateStruct->Day))); + assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->Week)); + + RTC_UNLOCK(); + + CW_RTC->DATE = ((uint32_t)(RTC_DateStruct->Week) << 24) | + ((uint32_t)(RTC_DateStruct->Year) << 16) | + ((uint32_t)(RTC_DateStruct->Month) << 8) | + ((uint32_t)(RTC_DateStruct->Day)); + + RTC_LOCK(); +} + +/** + * @brief ȡǰʱ䣬BCDʽ + * + * @param RTC_TimeStruct + */ +void RTC_GetTime(RTC_TimeTypeDef* RTC_TimeStruct) +{ + uint32_t RegTmp = 0; + + RTC_TimeStruct->H24 = CW_RTC->CR0_f.H24; // CR0ǷҪΣӲ + + RegTmp = CW_RTC->TIME; + while(RegTmp != CW_RTC->TIME) {RegTmp = CW_RTC->TIME;} // ζȡһ£Ϊȡɹ + + RTC_TimeStruct->Hour = (uint8_t)((RegTmp & RTC_TIME_HOUR_Msk) >> 16); + RTC_TimeStruct->Minute = (uint8_t)((RegTmp & RTC_TIME_MINUTE_Msk) >> 8); + RTC_TimeStruct->Second = (uint8_t)(RegTmp & RTC_TIME_SECOND_Msk); + if(RTC_TimeStruct->H24 == RTC_HOUR12) + { RTC_TimeStruct->AMPM = RTC_TimeStruct->Hour >> 5; + RTC_TimeStruct->Hour &= 0x1f; + } +} + + +/** + * @brief ȡõǰڣBCDʽ + * + * @param RTC_Date + */ +void RTC_GetDate(RTC_DateTypeDef *RTC_Date) +{ + uint32_t RegTmp = 0; + + RegTmp = CW_RTC->DATE; + while(RegTmp != CW_RTC->DATE) {RegTmp = CW_RTC->DATE;} // ζȡһ£Ϊȡɹ + + RTC_Date->Day = (uint8_t)(RegTmp & RTC_DATE_DAY_Msk); + RTC_Date->Month = (uint8_t)((RegTmp & RTC_DATE_MONTH_Msk) >> 8); + RTC_Date->Year = (uint8_t)((RegTmp & RTC_DATE_YEAR_Msk) >> 16); + RTC_Date->Week = (uint8_t)((RegTmp & RTC_DATE_WEEK_Msk) >> 24); +} + +/** + * @brief ӣBCDʽ || + * RTC_AlarmMaskbit32~24:WeeksMaskbit23:HourMaskbit15:MinuteMaskbit7:SecondMask || + * ʱ䣬HOURMINIUTESECONDΪBCDʽû뱣֤HOURAMPMH24֮Ĺȷ + * + * @param RTC_Alarm + * @param RTC_AlarmStruct + */ +void RTC_SetAlarm(uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + uint32_t RegTmp = 0; + + assert_param(IS_RTC_ALARM(RTC_Alarm)); + assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); + assert_param(IS_RTC_SECONDS(RTC_BCDToBin(RTC_AlarmStruct->RTC_AlarmTime.Second))); + assert_param(IS_RTC_MINUTES(RTC_BCDToBin(RTC_AlarmStruct->RTC_AlarmTime.Minute))); + if(RTC_AlarmStruct->RTC_AlarmTime.H24 == RTC_HOUR12) + assert_param(IS_RTC_HOUR12(RTC_BCDToBin(RTC_AlarmStruct->RTC_AlarmTime.Hour))); + else + assert_param(IS_RTC_HOUR24(RTC_BCDToBin(RTC_AlarmStruct->RTC_AlarmTime.Hour))); + + RegTmp = RTC_AlarmStruct->RTC_AlarmMask | + (uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.Hour << 16) | + (uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.Minute << 8) | + (uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.Second); + + RTC_UNLOCK(); + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + + if (RTC_Alarm == RTC_Alarm_A) + { + CW_RTC->ALARMA = RegTmp; + } + else + { + CW_RTC->ALARMB = RegTmp; + } + + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +/** + * @brief ȡӵãʱΪBCDʽ + * + * @param RTC_Alarm + * @param RTC_AlarmStruct + */ +void RTC_GetAlarm(uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + uint32_t RegTmp = 0; + + assert_param(IS_RTC_ALARM(RTC_Alarm)); + + if (RTC_Alarm == RTC_Alarm_A) + { + RegTmp = CW_RTC->ALARMA; + while(RegTmp != CW_RTC->ALARMA) {RegTmp = CW_RTC->ALARMA;} + } + else + { + RegTmp = CW_RTC->ALARMB; + while(RegTmp != CW_RTC->ALARMB) {RegTmp = CW_RTC->ALARMB;} + } + + RTC_AlarmStruct->RTC_AlarmMask = RegTmp & RTC_AlarmMask_All; + + RTC_AlarmStruct->RTC_AlarmTime.H24 = CW_RTC->CR0_f.H24; // CR0ǷҪΣӲ + + RTC_AlarmStruct->RTC_AlarmTime.Hour = (uint8_t)((RegTmp & RTC_TIME_HOUR_Msk) >> 16); + RTC_AlarmStruct->RTC_AlarmTime.Minute = (uint8_t)((RegTmp & RTC_TIME_MINUTE_Msk) >> 8); + RTC_AlarmStruct->RTC_AlarmTime.Second = (uint8_t)(RegTmp & RTC_TIME_SECOND_Msk); + if(RTC_AlarmStruct->RTC_AlarmTime.H24 == RTC_HOUR12) + { RTC_AlarmStruct->RTC_AlarmTime.AMPM = RTC_AlarmStruct->RTC_AlarmTime.Hour >> 5; + RTC_AlarmStruct->RTC_AlarmTime.Hour &= 0x1f; + } +} + +void RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) +{ + assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + RTC_UNLOCK(); + + if (IS_RTC_START()) // RTCУʹWINDOWSACCESS + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + + if (RTC_Alarm == RTC_Alarm_A) + { + CW_RTC->CR2_f.ALARMAEN = NewState; + } + else + { + CW_RTC->CR2_f.ALARMBEN = NewState; + } + + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +void RTC_TamperTriggerConfig(uint32_t RTC_TamperTrigger) +{ + assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); + + RTC_UNLOCK(); + + if (IS_RTC_START()) // RTCУʹWINDOWSACCESS + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + + CW_RTC->CR2_f.TAMPEDGE = RTC_TamperTrigger; + + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +void RTC_TamperCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + RTC_UNLOCK(); + + if (IS_RTC_START()) // RTCУʹWINDOWSACCESS + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + + CW_RTC->CR2_f.TAMPEN = NewState; + + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +void RTC_GetTamperDate(RTC_DateTypeDef *RTC_Date) +{ + uint32_t RegTmp = 0; + + do + { + RegTmp = CW_RTC->TAMPDATE; + } while(RegTmp != CW_RTC->TAMPDATE); + + RTC_Date->Week = (uint8_t)((RegTmp & RTC_TAMPDATE_WEEK_Msk) >> 13); + RTC_Date->Month = (uint8_t)((RegTmp & RTC_TAMPDATE_MONTH_Msk) >> 8 ); + RTC_Date->Day = (uint8_t)(RegTmp & RTC_TAMPDATE_DAY_Msk); +} + +void RTC_GetTamperTime(RTC_TimeTypeDef* RTC_TimeStruct) +{ + uint32_t RegTmp = 0; + + do + { + RegTmp = CW_RTC->TAMPTIME; + } while(RegTmp != CW_RTC->TAMPTIME); // ζȡһ£Ϊȡɹ + + RTC_TimeStruct->Second = (uint8_t)((RegTmp & RTC_TAMPTIME_SECOND_Msk) >> 16); + RTC_TimeStruct->Minute = (uint8_t)((RegTmp & RTC_TAMPTIME_MINUTE_Msk) >> 8); + RTC_TimeStruct->Hour = (uint8_t)(RegTmp & RTC_TAMPTIME_HOUR_Msk); + + RTC_TimeStruct->H24 = CW_RTC->CR0_f.H24; // CR0ǷҪΣӲ + if(RTC_TimeStruct->H24 == RTC_HOUR12) + { RTC_TimeStruct->AMPM = RTC_TimeStruct->Hour >> 5; + RTC_TimeStruct->Hour &= 0x1f; + } + +} + + +/** + * @brief RTCOUTPUTźԴ + * + * @param RTC_Output + */ +void RTC_OutputConfig(uint8_t RTC_Output) +{ + assert_param(IS_RTC_RTCOUT_SOURCE(RTC_Output)); + + RTC_UNLOCK(); + + if (IS_RTC_START()) // RTCУʹWINDOWSACCESS + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + + CW_RTC->CR2_f.RTCOUT = RTC_Output; + + CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +/** + * @brief RTCԶѶʱ + * + * @param RCT_AWTStruct + */ +void RTC_AWTConfig(RTC_AWTTypeDef *RCT_AWTStruct) +{ + assert_param(IS_RTC_AWTTIMER_SOURCE(RCT_AWTStruct->AWT_ClockSource)); + + RTC_UNLOCK(); + + if (IS_RTC_START()) // RTCУʹWINDOWSACCESS + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + + CW_RTC->CR2_f.AWTSRC = RCT_AWTStruct->AWT_ClockSource; + CW_RTC->AWTARR = (uint32_t)RCT_AWTStruct->AWT_ARRValue; + + CW_RTC->CR1_f.ACCESS = 0; + + RTC_LOCK(); +} + +/** + * @brief ʹֹܻAWT + * + * @param NewState + */ +void RTC_AWTCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + RTC_UNLOCK(); + + if (IS_RTC_START()) // RTCУʹWINDOWSACCESS + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + + CW_RTC->CR2_f.AWTEN = NewState; + + CW_RTC->CR1_f.ACCESS = 0; + + RTC_LOCK(); +} + +/** + * @brief + * + * @param Period + */ +void RTC_SetInterval(uint8_t Period) +{ + assert_param(IS_RTC_INTERVAL_PERIOD(Period)); + + RTC_UNLOCK(); + + if (IS_RTC_START()) // RTCУʹWINDOWSACCESS + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + + CW_RTC->CR0_f.INTERVAL = Period; + + CW_RTC->CR1_f.ACCESS = 0; + + RTC_LOCK(); +} + +/** + * @brief RTCļʱʱԴ + * + * @param RTC_ClockSource ֻRTC_RTCCLK_FROM_LSELSIHSEЧֲֵӰWINDOWACCESSλ + * ûRTCʱԴ + */ + void RTC_SetClockSource(uint32_t RTC_ClockSource) +{ + assert_param(IS_RTC_RTCCLK_SOURCE(RTC_ClockSource)); + + RTC_UNLOCK(); /* RTCĴд */ + +// CW_RTC->CR1_f.SOURCE = RTC_ClockSource; // RTCʱԴ + CW_RTC->CR1 = RTC_ClockSource; // RTCʱԴ,ͬʱWINDOWSACCESSλ + + RTC_LOCK(); +} + +/** + * @brief У׼ʱӲFREQSTEPSIGNCOMPEN || + * ע:RTC_CalibStruct->Step Ϊ 0 ʱҪ֤ RTC_CalibStruct->RefClock 4MHz || + * RTC_CalibStruct->Step Ϊ 1 ʱҪ֤ RTC_CalibStruct->RefClock 12MHz || + * RTC_CalibStruct->Step Ϊ 2 ʱҪ֤ RTC_CalibStruct->RefClock 24MHz + * + * @param RTC_CalibStruct + */ +void RTC_CalibrationConfig(RTC_CalibTypeDef *RTC_CalibStruct) +{ + assert_param(IS_RTC_COMPEN_FREQ(RTC_CalibStruct->Freq)); + assert_param(IS_RTC_COMPEN_STEP(RTC_CalibStruct->Step)); + assert_param(IS_RTC_COMPEN_SIGN(RTC_CalibStruct->Sign)); + assert_param(IS_RTC_COMPEN_VALUE(RTC_CalibStruct->CompensationValue)); + + RTC_UNLOCK(); + + if (IS_RTC_START()) // RTCУʹWINDOWSACCESS + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + + CW_RTC->COMPEN = (RTC_CalibStruct->Freq << 16) | + (RTC_CalibStruct->Sign << 14) | + (RTC_CalibStruct->Step << 12) | + RTC_CalibStruct->CompensationValue; + + CW_RTC->CR1_f.ACCESS = 0; + + RTC_LOCK(); +} + +void RTC_CalibrationCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + RTC_UNLOCK(); + + if (IS_RTC_START()) // RTCУʹWINDOWSACCESS + { + CW_RTC->CR1_f.ACCESS = 1; + while (!CW_RTC->CR1_f.WINDOW); + } + + CW_RTC->COMPEN_f.EN = NewState; + + CW_RTC->CR1_f.ACCESS = 0; + + RTC_LOCK(); +} + +/** + * @brief Convert a 2 digit decimal to BCD format. + * @param Value Byte to be converted + * @retval Converted byte + */ +uint8_t RTC_BinToBCD(uint8_t Value) +{ + uint32_t bcdhigh = 0U; + uint8_t Param = Value; + + while (Param >= 10U) + { + bcdhigh++; + Param -= 10U; + } + + return ((uint8_t)(bcdhigh << 4U) | Param); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value BCD value to be converted + * @retval Converted byte + */ +uint8_t RTC_BCDToBin(uint8_t Value) +{ + uint32_t tmp; + tmp = (((uint32_t)Value & 0xF0U) >> 4U) * 10U; + return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU)); +} + +/** + * @} + */ diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_spi.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_spi.c new file mode 100644 index 0000000..2619a52 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_spi.c @@ -0,0 +1,441 @@ +/** + * @file cw32f030_spi.c + * @author P&S (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-06-26 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_spi.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief ͨSPIxһ(4 ~ 16bit) + * + * @param SPIx :SPIx + * : + * CW_SPI1CW_SPI2 + * @param Data :͵ + */ +void SPI_SendData(SPI_TypeDef* SPIx, uint16_t Data) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + SPIx->DR = Data; +} + +/** + * @brief ͨSPIxһ(4 ~ 16bit) + * + * @param SPIx :SPIx + * : + * CW_SPI1CW_SPI2 + * @return uint16_t :յ + */ +uint16_t SPI_ReceiveData(SPI_TypeDef* SPIx) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + return (uint16_t)(SPIx->DR); +} + +/** + * @brief SPI_InitStructָIJʼSPIx + * + * @param SPIx :SPIx + * : + * CW_SPI1CW_SPI2 + * @param SPI_InitStruct :ָSPI_InitTypeDefͽṹָ + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_SPEED(SPI_InitStruct->SPI_Speed)); + + REGBITS_MODIFY(SPIx->CR1, SPIx_CR1_MODE_Msk |\ + SPIx_CR1_WIDTH_Msk | SPIx_CR1_SSM_Msk |\ + SPIx_CR1_SMP_Msk | SPIx_CR1_LSBF_Msk |\ + SPIx_CR1_BR_Msk | SPIx_CR1_MSTR_Msk |\ + SPIx_CR1_CPOL_Msk | SPIx_CR1_CPHA_Msk \ + ,\ + SPI_InitStruct->SPI_Direction |\ + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_NSS |\ + SPI_InitStruct->SPI_Speed | SPI_InitStruct->SPI_FirstBit |\ + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_Mode |\ + SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA); +} + +/** + * @brief ĬֵֵSPI_InitStructṹԱ + * + * @param SPI_InitStruct :ָSPI_InitTypeDefͽṹָ + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ + /* SPI_InitStruct members default value */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_Speed = SPI_Speed_Low; +} + +/** + * @brief SPI1ȥʼ + * + */ +void SPI1_DeInit(void) +{ + CW_SYSCTRL->APBRST2_f.SPI1 = 0; + CW_SYSCTRL->APBRST2_f.SPI1 = 1; +} + +/** + * @brief SPI2ȥʼ + * + */ +void SPI2_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.SPI2 = 0; + CW_SYSCTRL->APBRST1_f.SPI2 = 1; +} + +/** + * @brief ʹֹܻSPIx + * + * @param SPIx :SPIx + * : + * CW_SPI1CW_SPI2 + * @param NewState :ENABLE or DISABLE + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + SPIx->CR1_f.EN = NewState; +} + +/** + * @brief ʹ/ʧSPIxж + * + * @param SPIx :SPIx + * : + * CW_SPI1CW_SPI2 + * @param SPI_IT :жԴ + * : + * @arg SPI_IT_MODF: ģʽж + * @arg SPI_IT_SSERR: ӻģʽµĴӻѡж + * @arg SPI_IT_OV: ջж + * @arg SPI_IT_UD: ӻģʽ·ͻж + * @arg SPI_IT_SSR: ӻѡж + * @arg SPI_IT_SSF: ӻѡ½ж + * @arg SPI_IT_RXNE: ջǿж + * @arg SPI_IT_TXE: ͻж + * @param NewState :ENABLE or DISABLE + */ +void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_IT(SPI_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SPIx->IER |= SPI_IT; + } + else + { + SPIx->IER &= ~SPI_IT; + } +} + +/** + * @brief ȡSPIxжϱ־λ + * + * @param SPIx :SPIx + * : + * CW_SPI1CW_SPI2 + * @param SPI_IT :жԴ + * : + * @arg SPI_IT_MODF: ģʽж + * @arg SPI_IT_SSERR: ӻģʽµĴӻѡж + * @arg SPI_IT_OV: ջж + * @arg SPI_IT_UD: ӻģʽ·ͻж + * @arg SPI_IT_SSR: ӻѡж + * @arg SPI_IT_SSF: ӻѡ½ж + * @arg SPI_IT_RXNE: ջǿж + * @arg SPI_IT_TXE: ͻж + * @return ITStatus :SPI_ITǰ״̬ (SET or RESET) + */ +ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_IT(SPI_IT)); + + return ((SPIx->ISR & SPI_IT) ? SET : RESET); +} + +/** + * @brief SPIxжϱ־λ + * + * @param SPIx :SPIx + * : + * CW_SPI1CW_SPI2 + * @param SPI_IT :жԴ + * : + * @arg SPI_IT_MODF: ģʽж + * @arg SPI_IT_SSERR: ӻģʽµĴӻѡж + * @arg SPI_IT_OV: ջж + * @arg SPI_IT_UD: ӻģʽ·ͻж + * @arg SPI_IT_SSR: ӻѡж + * @arg SPI_IT_SSF: ӻѡ½ж + * @arg SPI_IT_RXNE: ջǿж + * @note + * -TXEжϱ־λֻͨдSPIx_DRĴ + */ +void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CLEAR_IT(SPI_IT)); + + SPIx->ICR &= ~SPI_IT; +} + +/** + * @brief ȡSPIx־λ + * + * @param SPIx :SPIx + * : + * CW_SPI1CW_SPI2 + * @param SPI_FLAG :־λ + * : + * @arg SPI_FLAG_SSLVL: ӻѡź״̬ + * @arg SPI_FLAG_BUSY: æ־ + * @arg SPI_FLAG_MODF: ģʽ־ + * @arg SPI_FLAG_SSERR: ӻģʽµĴӻѡ־ + * @arg SPI_FLAG_OV: ջж + * @arg SPI_FLAG_UD: ӻģʽ·ͻ־ + * @arg SPI_FLAG_SSR: ӻѡر־ + * @arg SPI_FLAG_SSF: ӻѡ½ر־ + * @arg SPI_FLAG_RXNE: ջǿձ־ + * @arg SPI_FLAG_TXE: ͻձ־ + * @return FlagStatus :SPI_FLAGǰ״̬ (SET or RESET) + */ +FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_FLAG(SPI_FLAG)); + + return ((SPIx->ISR & SPI_FLAG) ? SET : RESET); +} + +/** + * @brief SPIx־λ + * + * @param SPIx :SPIx + * : + * CW_SPI1CW_SPI2 + * @param SPI_FLAG :־λ + * : + * @arg SPI_FLAG_MODF: ģʽ־ + * @arg SPI_FLAG_SSERR: ӻģʽµĴӻѡ־ + * @arg SPI_FLAG_OV: ջж + * @arg SPI_FLAG_UD: ӻģʽ·ͻ־ + * @arg SPI_FLAG_SSR: ӻѡر־ + * @arg SPI_FLAG_SSF: ӻѡ½ر־ + * @arg SPI_FLAG_RXNE: ջǿձ־ + * @note + * -SSLVLBUSY־λӲԶú + * -TXE־λֻͨдSPIx_DRĴ + * -RXNE־λҲͨSPIx_DRĴ + * @return FlagStatus :SPI_FLAGǰ״̬ (SET or RESET) + */ +void SPI_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_FLAG) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CLEAR_FLAG(SPI_FLAG)); + + SPIx->ICR &= ~SPI_FLAG; +} + +/** + * @brief ߰˫ݴ䷽ + * + * @param SPIx :SPIx + * : + * CW_SPI1CW_SPI2 + * @param SPI_Direction :/ + * ǣ + * @arg SPI_Direction_Tx: + * @arg SPI_Direction_Rx: + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint8_t SPI_Direction) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + + SPIx->CR2 = SPI_Direction; +} + +/** + * @brief ʹ/ʧSPIx DMA + * + * @param SPIx :SPIx + * : + * CW_SPI1CW_SPI2 + * @param SPI_DMAReq :DMA + * ǣ + * @arg SPI_DMAReq_Tx: DMA + * @arg SPI_DMAReq_Rx: DMA + * @param NewState :ENABLE or DISABLE + */ +void SPI_DMACmd(SPI_TypeDef* SPIx, uint32_t SPI_DMAReq, FunctionalState NewState) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DMAREQ(SPI_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SPIx->CR1 |= SPI_DMAReq; + } + else + { + SPIx->CR1 &= ~SPI_DMAReq; + } +} + +/** + * @brief ڲNSS + * + * @param SPIx :SPIx + * : + * CW_SPI1CW_SPI2 + * @param SPI_NSSInternalSoft :NSS״̬ + * ǣ + * @arg SPI_NSSInternalSoft_Set: Set NSS + * @arg SPI_NSSInternalSoft_Reset: Reset NSS + * @note + * -SPIx_CR1.SSM = 1ʱЧNSS(SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) + * -ʱ0 - CS 1 - CS + * -ӻʱ0 - ѡ 1 - δѡ + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint8_t SPI_NSSInternalSoft) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + + SPIx->SSI = SPI_NSSInternalSoft; +} + +/** + * @brief ֡λ + * + * @param SPIx :SPIx + * : + * CW_SPI1CW_SPI2 + * @param SPI_DataSize :֡ + * ǣ + * @arg SPI_DataSize_4b + * @arg SPI_DataSize_5b + * @arg SPI_DataSize_6b + * @arg SPI_DataSize_7b + * @arg SPI_DataSize_8b + * @arg SPI_DataSize_9b + * @arg SPI_DataSize_10b + * @arg SPI_DataSize_11b + * @arg SPI_DataSize_12b + * @arg SPI_DataSize_13b + * @arg SPI_DataSize_14b + * @arg SPI_DataSize_15b + * @arg SPI_DataSize_16b + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + + REGBITS_MODIFY(SPIx->CR1, SPIx_CR1_WIDTH_Msk, SPI_DataSize); +} + +/** + * @brief ģʽMISO + * + * @param SPIx :SPIx + * : + * CW_SPI1CW_SPI2 + * @param SPI_MISOOutput :MISO + * ǣ + * @arg SPI_MISOOutput_HD: ӻѡʱ MISO Ϊ COMS δѡʱΪ + * @arg SPI_MISOOutput_CMOS: MISO ʼΪ COMS + */ +void SPI_MISOOutputConfig(SPI_TypeDef* SPIx, uint8_t SPI_MISOOutput) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_MISOOUTPUT(SPI_MISOOutput)); + + SPIx->CR1_f.MISOHD = SPI_MISOOutput; +} + +/** + * @brief շͻλĴ + * + * @param SPIx :SPIx + * : + * CW_SPI1CW_SPI2 + */ +void SPI_FlushSendBuff(SPI_TypeDef* SPIx) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + SPIx->ICR_f.FLUSH = 0; +} + + + + + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_systick.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_systick.c new file mode 100644 index 0000000..c4beaf4 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_systick.c @@ -0,0 +1,169 @@ +/** + * @file cw32f030_systick.c + * @author your name (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-05-13 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_systick.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +TickFreqTypeDef uwTickFreq = TICK_FREQ_DEFAULT; /* 1KHz */ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __Weak to be overwritten in case of other + * implementation in user file. + * @param system hclk freq. + * @retval HAL status + */ +__weak void InitTick(uint32_t HclkFreq) +{ + + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (SysTick_Config(HclkFreq / (1000U / uwTickFreq)) > 0U) + { + return ; + } + + /* Configure the SysTick IRQ priority */ + if (TICK_INT_PRIORITY < (1UL << __NVIC_PRIO_BITS)) + { + NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY); + uwTickPrio = TICK_INT_PRIORITY; + } + else + { + return ; + } + +} + + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t GetTick(void) +{ + return uwTick; +} + + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note ThiS function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void SysTickDelay(uint32_t Delay) +{ + uint32_t tickstart = GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < MAX_SYSTICK_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while((GetTick() - tickstart) < wait) + { + } +} + + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void SuspendTick(void) + +{ + /* Disable SysTick Interrupt */ + REGBITS_CLR(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + REGBITS_SET(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn */ + uwTick += uwTickFreq; + /* USER CODE END SysTick_IRQn */ +} diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_uart.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_uart.c new file mode 100644 index 0000000..37311e5 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_uart.c @@ -0,0 +1,526 @@ +/** + * @file cw32f030_uart.c + * @author P&S (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-06-26 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_uart.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief ͨUSARTxһ(16bit) + * + * @param USARTx :USARTx + * : + * CW_UART1CW_UART2CW_UART3 + * @param Data :͵ + */ +void USART_SendData(UART_TypeDef* USARTx, uint16_t Data) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA_16BIT(Data)); + + USARTx->TDR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief ͨUSARTxһ(8bit) + * + * @param USARTx :USARTx + * : + * CW_UART1CW_UART2CW_UART3 + * @param Data :͵ + */ +void USART_SendData_8bit(UART_TypeDef* USARTx, uint8_t Data) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA_8BIT(Data)); + + USARTx->TDR = Data; +} + +/** + * @brief ͨUSARTxһ(16bit) + * + * @param USARTx :USARTx + * : + * CW_UART1CW_UART2CW_UART3 + * @return uint16_t :յ + */ +uint16_t USART_ReceiveData(UART_TypeDef* USARTx) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + return (uint16_t)(USARTx->RDR & (uint16_t)0x01FF); +} + +/** + * @brief ͨUSARTxһ(8bit) + * + * @param USARTx :USARTx + * : + * CW_UART1CW_UART2CW_UART3 + * @return uint8_t :յ + */ +uint8_t USART_ReceiveData_8bit(UART_TypeDef* USARTx) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + return (uint8_t)(USARTx->RDR); +} + +/** + * @brief USART_InitStructָIJʼUARTx + * + * @param USARTx :USARTx + * : + * CW_UART1CW_UART2CW_UART3 + * @param USART_InitStruct :ָUSART_InitTypeDefͽṹָ + */ +void USART_Init(UART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + uint16_t integerdivider = 0x00; + uint16_t fractionaldivider = 0x00; + float32_t temp = 0; + + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + assert_param(IS_USART_Over(USART_InitStruct->USART_Over)); + assert_param(IS_USART_Source(USART_InitStruct->USART_Source)); + assert_param(IS_USART_UCLKFREQ(USART_InitStruct->USART_UclkFreq)); + assert_param(IS_USART_StartBit(USART_InitStruct->USART_StartBit)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + + /* UARTx_CR1 */ + REGBITS_MODIFY(USARTx->CR1, UARTx_CR1_OVER_Msk | UARTx_CR1_START_Msk |\ + UARTx_CR1_STOP_Msk | UARTx_CR1_PARITY_Msk |\ + UARTx_CR1_RXEN_Msk | UARTx_CR1_TXEN_Msk \ + ,\ + (uint32_t)USART_InitStruct->USART_Over |\ + USART_InitStruct->USART_StartBit |\ + USART_InitStruct->USART_StopBits |\ + USART_InitStruct->USART_Parity |\ + USART_InitStruct->USART_Mode); + + /* UARTx_CR2 */ + REGBITS_MODIFY(USARTx->CR2, UARTx_CR2_SOURCE_Msk | UARTx_CR2_RTSEN_Msk |\ + UARTx_CR2_CTSEN_Msk \ + ,\ + (uint32_t)USART_InitStruct->USART_Source |\ + USART_InitStruct->USART_HardwareFlowControl); + + /* */ + if(USART_Over_16 == USART_InitStruct->USART_Over) + { + /* 16 */ + temp = (float32_t)(USART_InitStruct->USART_UclkFreq) / (16 * (USART_InitStruct->USART_BaudRate)); + integerdivider = (uint16_t)temp; + fractionaldivider = (uint16_t)((temp - integerdivider)*16 + 0.5); + USARTx->BRRI = (uint16_t)integerdivider; + USARTx->BRRF = (uint16_t)fractionaldivider; + } + else if(USART_Over_8 == USART_InitStruct->USART_Over) + { + /* 8 */ + integerdivider = (uint16_t)((float32_t)(USART_InitStruct->USART_UclkFreq) / (8 * (USART_InitStruct->USART_BaudRate)) + 0.5); + USARTx->BRRI = (uint16_t)integerdivider; + } + else if(USART_Over_4 == USART_InitStruct->USART_Over) + { + /* 4 */ + integerdivider = (uint16_t)((float32_t)(USART_InitStruct->USART_UclkFreq) / (4 * (USART_InitStruct->USART_BaudRate)) + 0.5); + USARTx->BRRI = (uint16_t)integerdivider; + } + else + { + /* רò */ + /* רòʺϴʱԴΪLSELSIʱ2400bps4800bps9600bpsµUARTͨ */ + integerdivider = (uint16_t)((float32_t)(USART_InitStruct->USART_UclkFreq)*256 / (USART_InitStruct->USART_BaudRate) + 0.5); + USARTx->BRRI = (uint16_t)integerdivider; + } +} + +/** + * @brief ĬֵֵUSART_InitStructṹԱ + * + * @param USART_InitStruct :ָUSART_InitTypeDefͽṹָ + */ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_Over = USART_Over_16; + USART_InitStruct->USART_Source = USART_Source_PCLK; + USART_InitStruct->USART_StartBit = USART_StartBit_FE; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/** + * @brief USARTxͬģʽʼCPOL=1CPHA=1ֻ + * + * @param USARTx :USARTx + * : + * CW_UART1CW_UART2CW_UART3 + * @param USART_ClockInitStruct :ָUSART_ClockInitTypeDefͽṹָ + */ +void USART_ClockInit(UART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); + assert_param(IS_USART_Source(USART_ClockInitStruct->USART_Source)); + + REGBITS_MODIFY(USARTx->CR1, UARTx_CR1_SYNC_Msk, (uint32_t)USART_ClockInitStruct->USART_Clock); + REGBITS_MODIFY(USARTx->CR2, UARTx_CR2_SOURCE_Msk, (uint32_t)USART_ClockInitStruct->USART_Source); +} + +/** + * @brief ĬֵֵUSART_ClockInitStructṹԱ + * + * @param USART_ClockInitStruct :ָUSART_ClockInitTypeDefͽṹָ + */ +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_Source = USART_Source_PCLK; +} + +/** + * @brief UART1ȥʼ + * + */ +void UART1_DeInit(void) +{ + CW_SYSCTRL->APBRST2_f.UART1 = 0; + CW_SYSCTRL->APBRST2_f.UART1 = 1; +} + +/** + * @brief UART2ȥʼ + * + */ +void UART2_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.UART2 = 0; + CW_SYSCTRL->APBRST1_f.UART2 = 1; +} + +/** + * @brief UART3ȥʼ + * + */ +void UART3_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.UART3 = 0; + CW_SYSCTRL->APBRST1_f.UART3 = 1; +} + +/** + * @brief ʹ/ʧUSARTxж + * + * @param USARTx :USARTx + * : + * CW_UART1CW_UART2CW_UART3 + * @param USART_IT :жԴ + * : + * @arg USART_IT_CTS: CTSźű仯ж + * @arg USART_IT_PE: żУж + * @arg USART_IT_FE: ֡ṹж + * @arg USART_IT_RC: ж + * @arg USART_IT_TC: ж + * @arg USART_IT_TXE: ͻж + * @param NewState :ENABLE or DISABLE + */ +void USART_ITConfig(UART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IT(USART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + NewState ? (USARTx->IER |= USART_IT) : (USARTx->IER &= (uint16_t)~USART_IT); + + // if (NewState != DISABLE) + // { + // USARTx->IER |= USART_IT; + // } + // else + // { + // USARTx->IER &= (uint16_t)~USART_IT; + // } +} + +/** + * @brief ȡUSARTxжϱ־λ + * + * @param USARTx :USARTx + * : + * CW_UART1CW_UART2CW_UART3 + * @param USART_IT :жԴ + * ǣ + * @arg USART_IT_CTS: CTSźű仯ж + * @arg USART_IT_PE: żУж + * @arg USART_IT_FE: ֡ṹж + * @arg USART_IT_RC: ж + * @arg USART_IT_TC: ж + * @arg USART_IT_TXE: ͻж + * @return ITStatus :USART_ITǰ״̬ (SET or RESET) + */ +ITStatus USART_GetITStatus(UART_TypeDef* USARTx, uint16_t USART_IT) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IT(USART_IT)); + + return (REGBITS_GET(USARTx->ISR, USART_IT) ? SET : RESET); +} + +/** + * @brief USARTxжϱ־λ + * + * @param USARTx :USARTx + * : + * CW_UART1CW_UART2CW_UART3 + * @param USART_IT :жԴ + * ǣ + * @arg USART_IT_CTS: CTSźű仯ж + * @arg USART_IT_PE: żУж + * @arg USART_IT_FE: ֡ṹж + * @arg USART_IT_RC: ж + * @arg USART_IT_TC: ж + * @note + * -TXEжϱ־λֻͨдUARTx_TDRĴ + * -RCжϱ־λֻͨUARTx_RDRĴ + */ +void USART_ClearITPendingBit(UART_TypeDef* USARTx, uint16_t USART_IT) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + + REGBITS_CLR(USARTx->ICR, USART_IT); +} + +/** + * @brief ȡUSARTx־λ + * + * @param USARTx :USARTx + * : + * CW_UART1CW_UART2CW_UART3 + * @param USART_FLAG :־ + * ǣ + * @arg USART_FLAG_TXBUSY: æ־ + * @arg USART_FLAG_CTSLV: CTSźŵƽ״̬־ + * @arg USART_FLAG_CTS: CTSźű仯־ + * @arg USART_FLAG_MATCH: ӻַƥ־ + * @arg USART_FLAG_PE: żУ־ + * @arg USART_FLAG_FE: ֡ṹ־ + * @arg USART_FLAG_RC: ɱ־ + * @arg USART_FLAG_TC: ɱ־ + * @arg USART_FLAG_TXE: ͻձ־ + * @return FlagStatus :USART_FLAGǰ״̬ (SET or RESET) + */ +FlagStatus USART_GetFlagStatus(UART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + + return (REGBITS_GET(USARTx->ISR, USART_FLAG) ? SET : RESET); +} + +/** + * @brief USARTx־λ + * + * @param USARTx :USARTx + * : + * CW_UART1CW_UART2CW_UART3 + * @param USART_FLAG :־ + * ǣ + * @arg USART_FLAG_CTS: CTSźű仯־ + * @arg USART_FLAG_PE: żУ־ + * @arg USART_FLAG_FE: ֡ṹ־ + * @arg USART_FLAG_RC: ɱ־ + * @arg USART_FLAG_TC: ɱ־ + * @note + * -TXBUSYCTSLVMATCH־λӲԶú + * -TXE־λֻͨдUARTx_TDRĴ + * -RC־λֻͨUARTx_RDRĴ + */ +void USART_ClearFlag(UART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + + REGBITS_CLR(USARTx->ICR, USART_FLAG); +} + +/** + * @brief ʹ/ʧTXDRXD + * + * @param USARTx :USARTx + * : + * CW_UART1CW_UART2CW_UART3 + * @param USART_EN :ʹ + * ǣ + * @arg USART_EN_Tx: TXD + * @arg USART_EN_Rx: RXD + * @param NewState :ENABLE or DISABLE + */ +void USART_TxRxEN(UART_TypeDef* USARTx, uint16_t USART_EN, FunctionalState NewState) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_TxRxEN(USART_EN)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + NewState ? (USARTx->CR1 |= USART_EN) : (USARTx->CR1 &= (uint16_t)~USART_EN); + + // if (NewState != DISABLE) + // { + // USARTx->CR1 |= USART_EN; + // } + // else + // { + // USARTx->CR1 &= (uint16_t)~USART_EN; + // } +} + +/** + * @brief ʹ/ʧTXDźšRXDźŷ + * + * @param USARTx :USARTx + * : + * CW_UART1CW_UART2CW_UART3 + * @param USART_INV : + * ǣ + * @arg USART_INV_Tx: TXDźŷ + * @arg USART_INV_Rx: RXDźŷ + * @param NewState :ENABLE or DISABLE + */ +void USART_TxRxINV(UART_TypeDef* USARTx, uint16_t USART_INV, FunctionalState NewState) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_TxRxINV(USART_INV)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + NewState ? (USARTx->CR2 |= USART_INV) : (USARTx->CR2 &= (uint16_t)~USART_INV); + + // if (NewState != DISABLE) + // { + // USARTx->CR2 |= USART_INV; + // } + // else + // { + // USARTx->CR2 &= (uint16_t)~USART_INV; + // } +} + +/** + * @brief ʹ/ʧUSARTx˫ͨ + * + * @param USARTx :USARTx + * : + * CW_UART1CW_UART2CW_UART3 + * @param NewState :ENABLE or DISABLE + */ + +void USART_HalfDuplexCmd(UART_TypeDef* USARTx, FunctionalState NewState) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + USARTx->CR2_f.SIGNAL = NewState; +} + +/** + * @brief ʹ/ʧUSARTx DMA + * + * @param USARTx :USARTx + * : + * CW_UART1CW_UART2CW_UART3 + * @param USART_DMAReq :DMA + * ǣ + * @arg USART_DMAReq_Tx: DMA + * @arg USART_DMAReq_Rx: DMA + * @param NewState :ENABLE or DISABLE + */ +void USART_DMACmd(UART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + NewState ? (USARTx->CR2 |= USART_DMAReq) : (USARTx->CR2 &= (uint16_t)~USART_DMAReq); + + // if (NewState != DISABLE) + // { + // USARTx->CR2 |= USART_DMAReq; + // } + // else + // { + // USARTx->CR2 &= (uint16_t)~USART_DMAReq; + // } +} + +/** + * @brief USARTxͨ + * + * @param USARTx :USARTx + * : + * CW_UART1CW_UART2CW_UART3 + * @param USART_Address :ӻַ + * @param USART_AddressMsK :ӻַ + * @note + * ʹӻΪԶУ + */ +void USART_SetMultiMode(UART_TypeDef* USARTx, uint8_t USART_Address, uint8_t USART_AddressMsK) +{ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Address)); + assert_param(IS_USART_ADDRESSMSK(USART_AddressMsK)); + + REGBITS_SET(USARTx->CR2, UARTx_CR2_ADDREN_Msk); + REGBITS_MODIFY(USARTx->ADDR, UARTx_ADDR_ADDR_Msk, (uint32_t)USART_Address); + REGBITS_MODIFY(USARTx->MASK, UARTx_MASK_MASK_Msk, (uint32_t)USART_AddressMsK); +} + + + + + + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_vc.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_vc.c new file mode 100644 index 0000000..4840291 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_vc.c @@ -0,0 +1,811 @@ +/** + * @file cw32f030_vc.c + * @author P&S (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-07-27 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "cw32f030.h" +#include "cw32f030_vc.h" +#include "cw32f030_adc.h" + +/** + ****************************************************************************** + ** \addtogroup VcGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_VALID_CHANNEL(x) ( VcChannel1==(x) || VcChannel2 == (x)) +#define IS_VALID_STAT(x) ( VcCmpResult==(x) || VcIntrResult == (x)) +#define IS_VALID_DIV(x) ( (x) <= 64u ) + +#define IS_VALID_INPUT_P(x) ( (x) <= VcInPCh7 ) + +#define IS_VALID_INPUT_N(x) ( (x) <= AiAdcVref ) + +#define IS_VALID_DLY(x) ( (VcDelay30mv == (x)) ||\ + (VcDelay20mv == (x)) ||\ + (VcDelay10mv == (x)) ||\ + (VcDelayoff == (x)) ) + +#define IS_VALID_BIAS(x) ( (VcRespExtraLow == (x)) ||\ + (VcRespLow == (x)) ||\ + (VcRespMedium == (x)) ||\ + (VcRespHigh == (x)) ) + +#define IS_VALID_CLK(x) ( (x) <= LvdFilterHsi ) + +#define IS_VALID_FILTER(x) ( (x) <= VcFilter4095Clk ) + +#define IS_VALID_BLANK(x) ( (x) <= VcBlankAtimCh3 ) + +#define IS_VALID_OUTPUT(x) ( (x) <= VcOutAtimClr ) + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + + +/** + * @brief + * ʹNVICVCxж + * + * @param enIrqn: + * @arg VC1_IRQn + * @arg VC2_IRQn + * @param intPriority: + * @arg 0 ~ 3 + */ +void VC_EnableNvic(IRQn_Type enIrqn, uint8_t intPriority) +{ + if (intPriority < (1UL << __NVIC_PRIO_BITS)) + { + NVIC_ClearPendingIRQ(enIrqn); + NVIC_EnableIRQ(enIrqn); + NVIC_SetPriority(enIrqn, intPriority); + } +} + +/** + * @brief + * VCͨ1жʹ + * + * @param intPriority: + * @arg 0 ~ 3 + * + * @return + */ +void VC1_EnableIrq(uint8_t intPriority) +{ + VC_EnableNvic(VC1_IRQn, intPriority); + REGBITS_SET(CW_VC1->CR0, VCx_CR0_IE_Msk); +} + +/** + * @brief + * VCͨ2жʹ + * + * @param intPriority: + * @arg 0 ~ 3 + * + * @return + */ +void VC2_EnableIrq(uint8_t intPriority) +{ + VC_EnableNvic(VC2_IRQn, intPriority); + REGBITS_SET(CW_VC2->CR0, VCx_CR0_IE_Msk); +} + +/** + * @brief + * VCͨ1жϽ + * + * @return + */ +void VC1_DisableIrq(void) +{ + REGBITS_CLR(CW_VC1->CR0, VCx_CR0_IE_Msk); + VC_DisableNvic(VC1_IRQn); +} + +/** + * @brief + * VCͨ2жϽ + * + * @return + */ +void VC2_DisableIrq(void) +{ + REGBITS_CLR(CW_VC2->CR0, VCx_CR0_IE_Msk); + VC_DisableNvic(VC2_IRQn); +} + +/** + * @brief + * ֹNVICVCж + * + * @param enIrqn: + * @arg VC1_IRQn + * @arg VC2_IRQn + * + * @return + */ +void VC_DisableNvic(IRQn_Type enIrqn) +{ + NVIC_ClearPendingIRQ(enIrqn); + NVIC_DisableIRQ(enIrqn); +} + +/** + * @brief + * ȡVC1ָж״̬ + * + * @param VC_FLAG: + * @arg VC_FLAG_READY + * @arg VC_FLAG_FLTV + * @arg VC_FLAG_INTF + * + * @return FlagStatus: SET or RESET + */ +FlagStatus VC1_GetFlagStatus(uint16_t VC_FLAG) +{ + assert_param(IS_VC_GET_FLAG(VC_FLAG)); + return (REGBITS_GET(CW_VC1->SR, VC_FLAG) ? SET : RESET); +} + +/** + * @brief + * ȡVC2ָж״̬ + * + * @param VC_FLAG: + * @arg VC_FLAG_READY + * @arg VC_FLAG_FLTV + * @arg VC_FLAG_INTF + * + * @return FlagStatus: SET or RESET + */ +FlagStatus VC2_GetFlagStatus(uint16_t VC_FLAG) +{ + assert_param(IS_VC_GET_FLAG(VC_FLAG)); + return (REGBITS_GET(CW_VC2->SR, VC_FLAG) ? SET : RESET); +} + +/** + * @brief + * VC1жϱ־ + * + * @param + * + * @return + */ +void VC1_ClearIrq(void) +{ + REGBITS_CLR(CW_VC1->SR, VCx_SR_INTF_Msk); +} + +/** + * @brief + * VC2жϱ־ + * + * @param + * + * @return + */ +void VC2_ClearIrq(void) +{ + REGBITS_CLR(CW_VC2->SR, VCx_SR_INTF_Msk); +} + +/** + * @brief + * VC1/VC2ģDIVοѹʼ + * + * @param VC_DivStruct + * + * @return + */ +void VC1VC2_DIVInit(VC_DivTypeDef* VC_DivStruct) +{ + ASSERT(NULL != VC_DivStruct); + assert_param(IS_VC_DIV_EN(VC_DivStruct->VC_DivEn)); + assert_param(IS_VC_DIV_VREF(VC_DivStruct->VC_DivVref)); + + REGBITS_MODIFY(CW_VC1->DIV, VCx_DIV_EN_Msk | VCx_DIV_VIN_Msk, \ + VC_DivStruct->VC_DivEn | VC_DivStruct->VC_DivVref); + + REGBITS_MODIFY(CW_VC2->DIV, VCx_DIV_EN_Msk | VCx_DIV_VIN_Msk, \ + VC_DivStruct->VC_DivEn | VC_DivStruct->VC_DivVref); + + if (VC_DivStruct->VC_DivValue < 0x40) + { + CW_VC1->DIV_f.DIV = VC_DivStruct->VC_DivValue; + CW_VC2->DIV_f.DIV = VC_DivStruct->VC_DivValue; + } + else + { + } +} + +/** + * @brief + * VC1/VC2ģDIVοѹȥʼ + * + * @param + * + * @return + */ +void VC1VC2_DIVDeInit(void) +{ + CW_VC1->DIV = 0x0u; + CW_VC2->DIV = 0x0u; +} + +/** + * @brief + * VC1/VC2ģVCxźųʼ + * + * @param VC_InitStruct + * + * @return + */ +void VC1VC2_INNInit(VC_InitTypeDef* VC_InitStruct) +{ + ASSERT(NULL != VC_InitStruct); + assert_param(IS_VC_INPUT_N(VC_InitStruct->VC_InputN)); + + switch (VC_InitStruct->VC_InputN) + { + case VC_InputN_Ts: + //VCxźΪ¶ȴ + //ADCʱ + REGBITS_SET( CW_SYSCTRL->APBEN2, SYSCTRL_APBEN2_ADC_Msk ); + REGBITS_SET(CW_ADC->CR0, ADC_CR0_TSEN_Msk | ADC_CR0_BGREN_Msk); + break; + + case VC_InputN_Bgr1P2: + //VCxźΪBGR 1.2V + //ADCʱ + REGBITS_SET( CW_SYSCTRL->APBEN2, SYSCTRL_APBEN2_ADC_Msk ); + REGBITS_SET( CW_ADC->CR0, ADC_CR0_BGREN_Msk ); + break; + + case VC_InputN_AdcVref: + //VCxźΪADC VREF + //ADCʱ + REGBITS_SET( CW_SYSCTRL->APBEN2, SYSCTRL_APBEN2_ADC_Msk ); + ADC_Enable(); + break; + + default: + break; + } +} + +/** + * @brief + * VCͨ1ʼ + * + * @param VC_InitStruct + * + * @return + */ +void VC1_ChannelInit(VC_InitTypeDef* VC_InitStruct) +{ + ASSERT(NULL != VC_InitStruct); + assert_param(IS_VC_INPUT_P(VC_InitStruct->VC_InputP)); + assert_param(IS_VC_INPUT_N(VC_InitStruct->VC_InputN)); + assert_param(IS_VC_HYS(VC_InitStruct->VC_Hys)); + assert_param(IS_VC_RESP(VC_InitStruct->VC_Resp)); + assert_param(IS_VC_FILTER(VC_InitStruct->VC_FilterEn)); + assert_param(IS_VC_FLT_CLK(VC_InitStruct->VC_FilterClk)); + assert_param(IS_VC_FLT_TIME(VC_InitStruct->VC_FilterTime)); + assert_param(IS_VC_WINDOW(VC_InitStruct->VC_Window)); + assert_param(IS_VC_POLARITY(VC_InitStruct->VC_Polarity)); + + REGBITS_MODIFY(CW_VC1->CR0, \ + VCx_CR0_INN_Msk | VCx_CR0_INP_Msk | \ + VCx_CR0_WINDOW_Msk | VCx_CR0_POL_Msk | \ + VCx_CR0_HYS_Msk | VCx_CR0_RESP_Msk, \ + VC_InitStruct->VC_InputN | \ + VC_InitStruct->VC_InputP | \ + VC_InitStruct->VC_Window | \ + VC_InitStruct->VC_Polarity | \ + VC_InitStruct->VC_Hys | \ + VC_InitStruct->VC_Resp); + + REGBITS_MODIFY(CW_VC1->CR1, \ + VCx_CR1_FLTCLK_Msk | VCx_CR1_FLTTIME_Msk | \ + VCx_CR1_FLTEN_Msk, \ + VC_InitStruct->VC_FilterClk | \ + VC_InitStruct->VC_FilterTime | \ + VC_InitStruct->VC_FilterEn); + + //VCxźųʼ + VC1VC2_INNInit(VC_InitStruct); +} + +/** + * @brief + * VCͨ2ʼ + * + * @param VC_InitStruct + * + * @return + */ +void VC2_ChannelInit(VC_InitTypeDef* VC_InitStruct) +{ + ASSERT(NULL != VC_InitStruct); + assert_param(IS_VC_INPUT_P(VC_InitStruct->VC_InputP)); + assert_param(IS_VC_INPUT_N(VC_InitStruct->VC_InputN)); + assert_param(IS_VC_HYS(VC_InitStruct->VC_Hys)); + assert_param(IS_VC_RESP(VC_InitStruct->VC_Resp)); + assert_param(IS_VC_FILTER(VC_InitStruct->VC_FilterEn)); + assert_param(IS_VC_FLT_CLK(VC_InitStruct->VC_FilterClk)); + assert_param(IS_VC_FLT_TIME(VC_InitStruct->VC_FilterTime)); + assert_param(IS_VC_WINDOW(VC_InitStruct->VC_Window)); + assert_param(IS_VC_POLARITY(VC_InitStruct->VC_Polarity)); + + REGBITS_MODIFY(CW_VC2->CR0, \ + VCx_CR0_INN_Msk | VCx_CR0_INP_Msk | \ + VCx_CR0_WINDOW_Msk | VCx_CR0_POL_Msk | \ + VCx_CR0_HYS_Msk | VCx_CR0_RESP_Msk, \ + VC_InitStruct->VC_InputN | \ + VC_InitStruct->VC_InputP | \ + VC_InitStruct->VC_Window | \ + VC_InitStruct->VC_Polarity | \ + VC_InitStruct->VC_Hys | \ + VC_InitStruct->VC_Resp); + + REGBITS_MODIFY(CW_VC2->CR1, \ + VCx_CR1_FLTCLK_Msk | VCx_CR1_FLTTIME_Msk | \ + VCx_CR1_FLTEN_Msk, \ + VC_InitStruct->VC_FilterClk | \ + VC_InitStruct->VC_FilterTime | \ + VC_InitStruct->VC_FilterEn); + + //VCxźųʼ + VC1VC2_INNInit(VC_InitStruct); +} + +/** + * @brief + * VCģȥʼ + * + * @return + */ +void VC_DeInit(void) +{ + // Enable VC reset state + REGBITS_CLR(CW_SYSCTRL->APBRST2, SYSCTRL_APBRST2_VC_Msk); + // Release VC from reset state + REGBITS_SET(CW_SYSCTRL->APBRST2, SYSCTRL_APBRST2_VC_Msk); + + VC1_ChannelDeInit(); + VC2_ChannelDeInit(); +} + +/** + * @brief + * VCͨ1ȥʼ + * + * @return + */ +void VC1_ChannelDeInit(void) +{ + CW_VC1->CR0 = 0u; + CW_VC1->CR1 = 0u; + VC_DisableNvic(VC1_IRQn); +} + +/** + * @brief + * VCͨ2ȥʼ + * + * @return + */ +void VC2_ChannelDeInit(void) +{ + CW_VC2->CR0 = 0u; + CW_VC2->CR1 = 0u; + VC_DisableNvic(VC2_IRQn); +} + +/** + * @brief + * VC1ͨʹ + * + * @return + */ +void VC1_EnableChannel(void) +{ + REGBITS_SET(CW_VC1->CR0, VCx_CR0_EN_Msk); + //ȴVCxȶ + while(!(VC1_GetFlagStatus(VC_FLAG_READY))); +} + +/** + * @brief + * VC2ͨʹ + * + * @return + */ +void VC2_EnableChannel(void) +{ + REGBITS_SET(CW_VC2->CR0, VCx_CR0_EN_Msk); + //ȴVCxȶ + while(!(VC2_GetFlagStatus(VC_FLAG_READY))); +} + +/** + * @brief + * VC1ͨ + * + * @return + */ +void VC1_DisableChannel(void) +{ + REGBITS_CLR(CW_VC1->CR0, VCx_CR0_EN_Msk); +} + +/** + * @brief + * VC2ͨ + * + * @return + */ +void VC2_DisableChannel(void) +{ + REGBITS_CLR(CW_VC2->CR0, VCx_CR0_EN_Msk); +} + +/** + * @brief + * VC1˲ʹ + * + * @return + */ +void VC1_EnableFilter(void) +{ + REGBITS_SET(CW_VC1->CR1, VCx_CR1_FLTEN_Msk); +} + +/** + * @brief + * VC2˲ʹ + * + * @return + */ +void VC2_EnableFilter(void) +{ + REGBITS_SET(CW_VC2->CR1, VCx_CR1_FLTEN_Msk); +} + +/** + * @brief + * VC1˲ + * + * @return + */ +void VC1_DisableFilter(void) +{ + REGBITS_CLR(CW_VC1->CR1, VCx_CR1_FLTEN_Msk); +} + +/** + * @brief + * VC2˲ + * + * @return + */ +void VC2_DisableFilter(void) +{ + REGBITS_CLR(CW_VC2->CR1, VCx_CR1_FLTEN_Msk); +} + +/** + * @brief + * VCͨ1/2 Ĭֵʼ + * @param VC_OutStruct + * + * @return + */ +void VC1VC2_OutInit(VC_OutTypeDef* VC_OutStruct) +{ + VC_OutStruct->VC_ATIMBk = 0u; + VC_OutStruct->VC_OutAtimClr = 0u; +} + +/** + * @brief + * VCͨ1 + * @param VC_OutStruct + * + * @return + */ +void VC1_OutputCfg(VC_OutTypeDef* VC_OutStruct) +{ + ASSERT(NULL != VC_OutStruct); + assert_param(IS_VC_ATIMBK(VC_OutStruct->VC_ATIMBk)); + assert_param(IS_VC_ATIMCLR(VC_OutStruct->VC_OutAtimClr)); + + REGBITS_MODIFY(CW_VC1->CR1, \ + VCx_CR1_ATIMBK_Msk | VCx_CR1_ATIMCLR_Msk, + VC_OutStruct->VC_ATIMBk | \ + VC_OutStruct->VC_OutAtimClr); +} + +/** + * @brief + * VCͨ2 + * @param VC_OutStruct + * + * @return + */ +void VC2_OutputCfg(VC_OutTypeDef* VC_OutStruct) +{ + ASSERT(NULL != VC_OutStruct); + assert_param(IS_VC_ATIMBK(VC_OutStruct->VC_ATIMBk)); + assert_param(IS_VC_ATIMCLR(VC_OutStruct->VC_OutAtimClr)); + + REGBITS_MODIFY(CW_VC2->CR1, \ + VCx_CR1_ATIMBK_Msk | VCx_CR1_ATIMCLR_Msk, + VC_OutStruct->VC_ATIMBk | \ + VC_OutStruct->VC_OutAtimClr); +} + +/** + * @brief + * VCͨ1/2 BlanKĬֵʼ + * @param VC_BlankStruct + * + * @return + */ +void VC1VC2_BlankInit(VC_BlankTypeDef* VC_BlankStruct) +{ + VC_BlankStruct->VC_BlankFlt = 0u; + VC_BlankStruct->VC_BlankCh3B = 0u; + VC_BlankStruct->VC_BlankCh2B = 0u; + VC_BlankStruct->VC_BlankCh1B = 0u; +} + +/** + * @brief + * VCͨ1 BlanK + * @param VC_BlankStruct + * + * @return + */ +void VC1_BlankCfg(VC_BlankTypeDef* VC_BlankStruct) +{ + ASSERT(NULL != VC_BlankStruct); + assert_param(IS_VC_BLANK_FLT(VC_BlankStruct->VC_BlankFlt)); + assert_param(IS_VC_BLANK_CH3B(VC_BlankStruct->VC_BlankCh3B)); + assert_param(IS_VC_BLANK_CH2B(VC_BlankStruct->VC_BlankCh2B)); + assert_param(IS_VC_BLANK_CH1B(VC_BlankStruct->VC_BlankCh1B)); + + REGBITS_MODIFY(CW_VC1->CR1, \ + VCx_CR1_BLANKFLT_Msk | VCx_CR1_BLANKCH3B_Msk | \ + VCx_CR1_BLANKCH2B_Msk | VCx_CR1_BLANKCH1B_Msk, + VC_BlankStruct->VC_BlankFlt | \ + VC_BlankStruct->VC_BlankCh3B | \ + VC_BlankStruct->VC_BlankCh2B | \ + VC_BlankStruct->VC_BlankCh1B); +} + +/** + * @brief + * VCͨ2 BlanK + * @param VC_BlankStruct + * + * @return + */ +void VC2_BlankCfg(VC_BlankTypeDef* VC_BlankStruct) +{ + ASSERT(NULL != VC_BlankStruct); + assert_param(IS_VC_BLANK_FLT(VC_BlankStruct->VC_BlankFlt)); + assert_param(IS_VC_BLANK_CH3B(VC_BlankStruct->VC_BlankCh3B)); + assert_param(IS_VC_BLANK_CH2B(VC_BlankStruct->VC_BlankCh2B)); + assert_param(IS_VC_BLANK_CH1B(VC_BlankStruct->VC_BlankCh1B)); + + REGBITS_MODIFY(CW_VC2->CR1, \ + VCx_CR1_BLANKFLT_Msk | VCx_CR1_BLANKCH3B_Msk | \ + VCx_CR1_BLANKCH2B_Msk | VCx_CR1_BLANKCH1B_Msk, + VC_BlankStruct->VC_BlankFlt | \ + VC_BlankStruct->VC_BlankCh3B | \ + VC_BlankStruct->VC_BlankCh2B | \ + VC_BlankStruct->VC_BlankCh1B); +} + +/** + * @brief + * VCͨ1ڱȽϹ + * + * @param bWindow: TRUE or FALSE + * + * @return + */ +void VC1_WindowEnable(boolean_t bWindow) +{ + if (bWindow) + { + REGBITS_SET(CW_VC1->CR0, VCx_CR0_WINDOW_Msk); + } + else + { + REGBITS_CLR(CW_VC1->CR0, VCx_CR0_WINDOW_Msk); + } +} + +/** + * @brief + * VCͨ2ڱȽϹ + * + * @param bWindow: TRUE or FALSE + * + * @return + */ +void VC2_WindowEnable(boolean_t bWindow) +{ + if (bWindow) + { + REGBITS_SET(CW_VC2->CR0, VCx_CR0_WINDOW_Msk); + } + else + { + REGBITS_CLR(CW_VC2->CR0, VCx_CR0_WINDOW_Msk); + } +} + +/** + * @brief + * VCͨ1źż + * + * @param bPolarity: TRUE or FALSE + * + * @return + */ +void VC1_PolarityCfg(boolean_t bPolarity) +{ + if (bPolarity) + { + REGBITS_SET(CW_VC1->CR0, VCx_CR0_POL_Msk); + } + else + { + REGBITS_CLR(CW_VC1->CR0, VCx_CR0_POL_Msk); + } +} + +/** + * @brief + * VCͨ2źż + * + * @param bPolarity: TRUE or FALSE + * + * @return + */ +void VC2_PolarityCfg(boolean_t bPolarity) +{ + if (bPolarity) + { + REGBITS_SET(CW_VC2->CR0, VCx_CR0_POL_Msk); + } + else + { + REGBITS_CLR(CW_VC2->CR0, VCx_CR0_POL_Msk); + } +} + +/** + * @brief + * VC1ж + * + * @param VC_IT: + * @arg VC_IT_HIGH + * @arg VC_IT_RISE + * @arg VC_IT_FALL + * @param NewState: + * @arg DISABLE + * @arg ENABLE + */ +void VC1_ITConfig(uint16_t VC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_VC_IT(VC_IT)); + if (NewState != DISABLE) + { + /* Enable the selected VC interrupts */ + CW_VC1->CR1 |= VC_IT; + } + else + { + /* Disable the selected VC interrupts */ + CW_VC1->CR1 &= (~(uint32_t) VC_IT); + } +} + +/** + * @brief + * VC2ж + * + * @param VC_IT: + * @arg VC_IT_READY + * @arg VC_IT_OVW + * @arg VC_IT_WDTR + * @param NewState: + * @arg DISABLE + * @arg ENABLE + */ +void VC2_ITConfig(uint16_t VC_IT, FunctionalState NewState) +{ + uint8_t itMask = 0; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_VC_IT(VC_IT)); + /* Get the VC IT index */ + itMask = (uint8_t) VC_IT; + if (NewState != DISABLE) + { + /* Enable the selected VC interrupts */ + CW_VC2->CR1 |= itMask; + } + else + { + /* Disable the selected VC interrupts */ + CW_VC2->CR1 &= (~(uint32_t) itMask); + } +} + +//@} // VcGroup + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_wwdt.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_wwdt.c new file mode 100644 index 0000000..6becf5a --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/cw32f030_wwdt.c @@ -0,0 +1,161 @@ +/** + * @file cw32f030_wwdt.c + * @author P&S (you@domain.com) + * @brief + * @version 0.1 + * @date 2021-04-23 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* ɺϢ +* 人Դ뵼޹˾ʹб̴ʾķרİȨɣɴ +* ɸضҪƵƹܡݲܱųκη֤人Դ +* ޹˾򿪷̺͹Ӧ̶Գ֧֣Уṩκʾ +* ı֤ڰйԡijض;ͷȨı֤ +* +* ۺΣ人Դ뵼޹˾򿪷̻Ӧ̾и +* ʹ֪䷢ĿʱҲˣݵĶʧ𻵣ֱӵġرġ +* ӵ𺦣κκԾ𺦣ҵ롢Ԥڿɽʡ +* ʧ +* ijЩ˾ϽֱӵġĻԵκεųƣijЩ +* ȫųƿܲ +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32f030_wwdt.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief WWDTȥʼ + * @param + * @return + */ +void WWDT_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.WWDT = 0; + CW_SYSCTRL->APBRST1_f.WWDT = 1; +} + +/** + * @brief ʼWWDT + * @param WWDT_InitStruct ṹ嶨WWDT_InitTypeDef + */ +void WWDT_Init(WWDT_InitTypeDef* WWDT_InitStruct) +{ + assert_param(IS_WWDT_COUNTER(WWDT_InitStruct->WWDT_CounterValue)); + assert_param(IS_WWDT_PRESCALER(WWDT_InitStruct->WWDT_Prescaler)); + assert_param(IS_WWDT_WINDOW_VALUE(WWDT_InitStruct->WWDT_WindowValue)); + + CW_SYSCTRL->APBEN1_f.WWDT = 1U; /* WWDTAPB߷ʱʹ */ + + CW_WWDT->CR0 = (WWDT_InitStruct->WWDT_CounterValue & WWDT_CR0_WCNT_Msk); + + if(WWDT_InitStruct->WWDT_ITState == ENABLE) + { + CW_WWDT->CR1 = WWDT_InitStruct->WWDT_WindowValue | WWDT_InitStruct->WWDT_Prescaler | WWDT_CR1_IE_Msk; + } + else + { + CW_WWDT->CR1 = (WWDT_InitStruct->WWDT_WindowValue | WWDT_InitStruct->WWDT_Prescaler) & (~WWDT_CR1_IE_Msk); + } + + +} + +/** + * @brief ʹWWDTʹWWDTֹܽ + */ +void WWDT_Cmd(void) +{ + CW_WWDT->CR0_f.EN = 1U; +} + +/** + * @brief ι + * @param Counter WWDTĸֵȡֵΧ0x40~0x7F + */ +void WWDT_Refresh(uint8_t Counter) +{ + assert_param(IS_WWDT_COUNTER(Counter)); + + CW_WWDT->CR0_f.WCNT = Counter; +} + +/** + * @brief WWDTԤƵϵ + * @param WWDT_Prescaler ȡֵΧWWDT_Prescaler_DIV4096~WWDT_Prescaler_DIV524288 + */ +void WWDT_SetPrescaler(uint32_t WWDT_Prescaler) +{ + assert_param(IS_WWDT_PRESCALER(WWDT_Prescaler)); + REGBITS_MODIFY(CW_WWDT->CR1, WWDT_CR1_PRS_Msk, WWDT_Prescaler); +} + +/** + * @brief WWDTĴϵ + * @param WindowValue ֵȡֵΧ0x40~0x7F + */ +void WWDT_SetWindowValue(uint8_t WindowValue) +{ + assert_param(IS_WWDT_WINDOW_VALUE(WindowValue)); + + CW_WWDT->CR1_f.WINR = WindowValue; +} + +/** + * @brief ȡǰֵ + * @return uint8_t ǰֵ + */ +uint8_t WWDT_GetCounterValue(void) +{ + return (uint8_t) (CW_WWDT->CR0 & WWDT_CR0_WCNT_Msk); +} + +/** + * @brief ȡǰõĴֵ + * @return uint8_t ǰõĴֵ + */ +uint8_t WWDT_GetWindowValue(void) +{ + return (uint8_t) (CW_WWDT->CR1 & WWDT_CR1_WINR_Msk); +} + +/** + * @brief WWDTԤжʹ λĬϹرжʹ + */ +void WWDT_EnableIT(void) +{ + CW_WWDT->CR1_f.IE = ENABLE; +} + +/** + * @brief ȡWWDT״̬ĴԤλ״̬ + * @return FlagStatus + */ +FlagStatus WWDT_GetFlagStatus(void) +{ + return (FlagStatus)(CW_WWDT->SR); +} + +/** + * @brief WWDT״̬ĴԤλ״̬ + */ +void WWDT_ClearFlag(void) +{ + REGBITS_CLR(CW_WWDT->SR, WWDT_SR_POV_Msk); +} diff --git a/原单片机-CW32F030/原项目程序/SW/Libraries/src/system_cw32f030.c b/原单片机-CW32F030/原项目程序/SW/Libraries/src/system_cw32f030.c new file mode 100644 index 0000000..bfd59d6 --- /dev/null +++ b/原单片机-CW32F030/原项目程序/SW/Libraries/src/system_cw32f030.c @@ -0,0 +1,199 @@ + + +/****************************************************************************** +* Include files * +******************************************************************************/ +#include "base_types.h" +#include "cw32f030.h" +#include "system_cw32f030.h" +#include "cw32f030_rcc.h" + + +/****************************************************************************** + ** System Clock Frequency (Core Clock) Variable according CMSIS + ******************************************************************************/ + +uint32_t SystemCoreClock = 8000000; + +void SystemCoreClockUpdate(void) // Update SystemCoreClock variable +{ + SystemCoreClock = 8000000; +} + +/** + ****************************************************************************** + ** \brief Setup the microcontroller system. Initialize the System and update + ** the SystemCoreClock variable. + ** + ** \param none + ** \return none + ******************************************************************************/ +void SystemInit(void) +{ + //Load TrimCode in this. + //... + + SystemCoreClockUpdate(); + CW_SYSCTRL->HSI_f.TRIM = *((volatile uint16_t *)RCC_HSI_TRIMCODEADDR); + CW_SYSCTRL->LSI_f.TRIM = *((volatile uint16_t *)RCC_LSI_TRIMCODEADDR); + //Init Hide thing. + //... +} + +#if 0 +#if defined (__CC_ARM) +extern int32_t $Super$$main(void); +/* re-define main function */ +int $Sub$$main(void) +{ + SystemInit(); + $Super$$main(); + return 0; +} +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +extern int32_t $Super$$main(void); +/* re-define main function */ +int $Sub$$main(void) +{ + SystemInit(); + $Super$$main(); + return 0; +} +#elif defined(__ICCARM__) +extern int32_t main(void); +/* __low_level_init will auto called by IAR cstartup */ +extern void __iar_data_init3(void); +int __low_level_init(void) +{ + // call IAR table copy function. + __iar_data_init3(); + SystemInit(); + main(); + return 0; +} +#endif + +#endif + + +/****************************************************************************** +* Internal Funcation * +******************************************************************************/ + +///** +// * \brief delay1ms +// * delay approximately 1ms. +// * \param [in] u32Cnt +// * \retval void +// */ +//void delay1ms(uint32_t u32Cnt) +//{ +// uint32_t u32end; +// +// SysTick->LOAD = 0xFFFFFF; +// SysTick->VAL = 0; +// SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; +// +// while(u32Cnt-- > 0) +// { +// SysTick->VAL = 0; +// u32end = 0x1000000 - SystemCoreClock/1000; +// while(SysTick->VAL > u32end) +// { +// ; +// } +// } +// +// SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +//} + + +///** +// * \brief delay100us +// * delay approximately 100us. +// * \param [in] u32Cnt +// * \retval void +// */ +//void delay100us(uint32_t u32Cnt) +//{ +// uint32_t u32end; +// +// SysTick->LOAD = 0xFFFFFF; +// SysTick->VAL = 0; +// SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; +// +// while(u32Cnt-- > 0) +// { +// SysTick->VAL = 0; + +// u32end = 0x1000000 - SystemCoreClock/10000; +// while(SysTick->VAL > u32end) +// { +// ; +// } +// } +// +// SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +//} + + +///** +// * \brief delay10us +// * delay approximately 10us. +// * \param [in] u32Cnt +// * \retval void +// */ +//void delay10us(uint32_t u32Cnt) +//{ +// uint32_t u32end; +// +// SysTick->LOAD = 0xFFFFFF; +// SysTick->VAL = 0; +// SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; +// +// while(u32Cnt-- > 0) +// { +// SysTick->VAL = 0; + +// u32end = 0x1000000 - SystemCoreClock/100000; +// while(SysTick->VAL > u32end) +// { +// ; +// } +// } +// +// SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +//} + + +void FirmwareDelay(uint32_t DlyCnt ) +{ + volatile uint32_t thisCnt = DlyCnt; + while( thisCnt-- ) + { + ; + } +} + +/** + * \brief clear memory + * + * \param [in] start addr + * \param [in] memory size(byte) + * \retval void + */ +void MemClr(void *pu8Address, uint32_t u32Count) +{ + uint8_t *pu8Addr = (uint8_t *)pu8Address; + + if(NULL == pu8Addr) + { + return; + } + + while (u32Count--) + { + *pu8Addr++ = 0; + } +} + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_DataSheet_CN_V1.0.pdf b/新单片机-CW32L012/MCU厂资料/CW32L012_DataSheet_CN_V1.0.pdf new file mode 100644 index 0000000..b755516 Binary files /dev/null and b/新单片机-CW32L012/MCU厂资料/CW32L012_DataSheet_CN_V1.0.pdf differ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3.zip b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3.zip new file mode 100644 index 0000000..ba772cf Binary files /dev/null and b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3.zip differ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/EWARM/project.ewp new file mode 100644 index 0000000..87ad923 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/EWARM/project.ewp @@ -0,0 +1,2258 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gtim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/MDK/project.uvoptx new file mode 100644 index 0000000..d6f0853 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/MDK/project.uvoptx @@ -0,0 +1,364 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + project + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_adc.c + cw32l012_adc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gtim.c + cw32l012_gtim.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 11 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/MDK/project.uvprojx new file mode 100644 index 0000000..7f7d706 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/MDK/project.uvprojx @@ -0,0 +1,498 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_adc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_adc.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gtim.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/USER/inc/main.h new file mode 100644 index 0000000..c708839 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/USER/src/main.c new file mode 100644 index 0000000..f36638d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/USER/src/main.c @@ -0,0 +1,187 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "cw32l012_systick.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_adc.h" +#include "cw32l012_gtim.h" + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint16_t valueAdc; +uint32_t valueAdcAcc; +volatile uint8_t gFlagIrq; +uint16_t gCntEoc = 0; +uint8_t cntSample; +float fTsDegree, fVoltage; + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief ADC 配置 + * + */ +void ADC_Configuration(void) +{ + ADC_InitTypeDef ADC_InitStructure = {0}; + __SYSCTRL_ADC_CLK_ENABLE(); + + ADC_InitStructure.ADC_ClkDiv = ADC_Clk_Div1; + ADC_InitStructure.ADC_ConvertMode = ADC_ConvertMode_Once; + ADC_InitStructure.ADC_SQREns = ADC_SqrEns0to1; + ADC_InitStructure.ADC_IN0.ADC_InputChannel = ADC_InputTs; // 温度 + ADC_InitStructure.ADC_IN0.ADC_SampTime = ADC_SampTime166Clk; // 采Ts至少需要40us，ADCCLK = 40us*Fadc = 40*4 =160 + ADC_InitStructure.ADC_IN1.ADC_InputChannel = ADC_InputVref1P2; // 内部1.2V参考 + ADC_InitStructure.ADC_IN1.ADC_SampTime = ADC_SampTime166Clk; // 采样持续时间至少需要40us + + + ADC_Init(CW_ADC1, &ADC_InitStructure); + // 采集温度需要开启内置温度传感器 + ADC_SetTs(ADC_TsEnable); + + //ADC外部中断触发源配置 + ADC_ExtTrigCfg(CW_ADC1, ADC_TRIG_GTIM1TRGO, ENABLE); + ADC_Enable(CW_ADC1); + + // PB05 作为采样时序指示 + PB05_DIGTAL_ENABLE(); + PB05_DIR_OUTPUT(); + PB05_PUSHPULL_ENABLE(); + PB05_AFx_ADC1SAM(); + +} + +/** + * @brief GTIM初始化 + * + */ +void GTIM_Init(void) +{ + GTIM_InitTypeDef GTIM_InitStruct = { 0 }; + + //打开GTIM时 + __SYSCTRL_GTIM1_CLK_ENABLE(); + + GTIM_InitStruct.AlignMode = GTIM_ALIGN_MODE_EDGE; + GTIM_InitStruct.ARRBuffState = GTIM_ARR_BUFF_DIS; + GTIM_InitStruct.Direction = GTIM_DIRECTION_UP; + GTIM_InitStruct.EventOption = GTIM_EVENT_NORMAL; + GTIM_InitStruct.Prescaler = 4000 - 1; //实际分频为 Prescaler+1 = 4000, 频率为1kHz + GTIM_InitStruct.PulseMode = GTIM_PULSE_MODE_DIS; + GTIM_InitStruct.ReloadValue = 1000 - 1; // 1秒 + GTIM_InitStruct.UpdateOption = GTIM_UPDATE_EN; + + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + // 配置GTIM的TRGO信号 + GTIM_MasterTRGOCfg(CW_GTIM1, GTIM_MASTER_TRGO_UPDATE); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + // 初始化板上资源 + Bsp_Init(4000000ul); + + // ADC 初始化 + ADC_Configuration(); + + // GTIM初始化 + GTIM_Init(); + + // 启动GTIM，开始计时 + GTIM_Cmd(CW_GTIM1, ENABLE); + + while (1) + { + if (CW_ADC1->ISR_f.EOS) // 采样转换完成 + { + Bsp_Led_Tog(&LED1); + CW_ADC1->ICR = 0; + ADC_GetSqr1Result(CW_ADC1, &valueAdc); + fVoltage = ADC_BgrResult2Avcc(valueAdc); + ADC_GetSqr0Result(CW_ADC1, &valueAdc); + fTsDegree = ADC_GetTs(fVoltage, valueAdc); + printf("The Temperature is %2f\r\n", fTsDegree); + printf("The Reference voltage is %2f\r\n", fVoltage); + } + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/readme.txt new file mode 100644 index 0000000..334cfef --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_get_AVcc_temp_refBgr1v2/readme.txt @@ -0,0 +1,28 @@ +示例目的： + 演示定时器外部触发启动ADC转换，定时1s采样芯片温度和BGR，通过BGR的1.2V反推出AVCC，从而获取较为准确的温度。 + +硬件资源： + 1. CW32L012CxTx StartKit + 2. 系统时钟默认，为HSIOSC 24分配， 4MH在，PCLK、HCLK不分频， + PCLK=HCLK=SysClk=4MHz + 3. GTIM1的时钟源选为PCLK，4000分频 + 4. ADC的时钟源为PCLK，1分频 + 5. PB09设置为PUSH-PULL输出，驱动LED1 + 6. uart3配置为115200bps，作为调试打印 + +演示说明： + 通用定时器GTIM1定时1s自动触发ADC模块进行转换，ADC通道为MCU内部温度传感器TS。 + ADC转换完成后，转换结果通过uart3输出，LED1的电平翻转，LED1以0.5Hz的频率闪烁. + +使用说明： ++ EWARM + 1. 打开adc_sgl_ext_trig.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开adc_sgl_ext_trig.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/EWARM/project.ewp new file mode 100644 index 0000000..7908612 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/EWARM/project.ewp @@ -0,0 +1,2255 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/MDK/adc_master_slaverl_sw.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/MDK/adc_master_slaverl_sw.uvoptx new file mode 100644 index 0000000..436c9c3 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/MDK/adc_master_slaverl_sw.uvoptx @@ -0,0 +1,383 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + adc_master_slave_sw + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\SYSCTRL + 35904 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_adc.c + cw32l012_adc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/MDK/adc_master_slaverl_sw.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/MDK/adc_master_slaverl_sw.uvprojx new file mode 100644 index 0000000..b45fc88 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/MDK/adc_master_slaverl_sw.uvprojx @@ -0,0 +1,483 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + adc_master_slave_sw + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + adc_master_slave_sw + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 3 + 5 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_adc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_adc.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/USER/inc/main.h new file mode 100644 index 0000000..f31a96f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/USER/inc/main.h @@ -0,0 +1,86 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +#define ADC_RETRIEVE_POLLING 0 +#define ADC_RETRIEVE_INTERRUPTION 1 + +#define ADC_RETRIEVE_MODE ADC_RETRIEVE_POLLING + +#ifndef ADC_RETRIEVE_MODE +#define ADC_RETRIEVE_MODE ADC_RETRIEVE_POLLING +#endif + +#define ADC_CONVERT_ONCE 0 +#define ADC_CONVERT_CONTINUE 1 + +#define ADC_CONVERT_MODE ADC_CONVERT_CONTINUE + +#ifndef ADC_CONVERT_MODE +#define ADC_CONVERT_MODE ADC_CONVERT_CONTINUE +#endif +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..1a04548 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/USER/src/interrupts_cw32l012.c @@ -0,0 +1,441 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +extern volatile uint8_t gFlagIrq; +extern uint16_t gCntEoc; + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + gFlagIrq = CW_ADC1->ISR; + CW_ADC1->ICR = 0x00; + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/USER/src/main.c new file mode 100644 index 0000000..98101b3 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/USER/src/main.c @@ -0,0 +1,196 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "cw32l012_systick.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_adc.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint16_t valueAdc1, valueAdc2; + +volatile uint8_t gFlagIrq; + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief ADC I/O初始化 + * + */ +void ADC_PortInit(void) +{ + //打开GPIO时钟 + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + //打开ADC时钟 + __SYSCTRL_ADC_CLK_ENABLE(); + + //set PA00 as ADC1 AIN0 INPUT + PA00_ANALOG_ENABLE(); + // set PA05 as ADC 2 AIN0 INPUT + PA05_ANALOG_ENABLE(); + + // set PB05 as ADC1_SAM + PB05_AFx_ADC1SAM(); + PB05_DIGTAL_ENABLE(); + PB05_DIR_OUTPUT(); + PB05_PUSHPULL_ENABLE(); + + // set PA04 as ADC2_SAM + PA04_AFx_ADC2SAM(); + PA04_DIGTAL_ENABLE(); + PA04_DIR_OUTPUT(); + PA04_PUSHPULL_ENABLE(); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + ADC_InitTypeDef ADC_InitStructure = {0}; + + //使用sysTick,产生1ms中断计时 + InitTick(4000000); + + Bsp_Init(4000000); + + //配置ADC测试IO口 + ADC_PortInit(); + + ADC_InitStructure.ADC_ClkDiv = ADC_Clk_Div1; + ADC_InitStructure.ADC_SlaveMod = ADC_SlaveMode_Disable; +#if (ADC_CONVERT_MODE == ADC_CONVERT_ONCE) + ADC_InitStructure.ADC_ConvertMode = ADC_ConvertMode_Once; // 单次采样 +#else + ADC_InitStructure.ADC_ConvertMode = ADC_ConvertMode_Continuous; // 连续采样 +#endif + ADC_InitStructure.ADC_SQREns = ADC_SqrEns0to0; // 单通道 + ADC_InitStructure.ADC_IN0.ADC_InputChannel = ADC_InputCH0; + ADC_InitStructure.ADC_IN0.ADC_SampTime = ADC_SampTime6Clk; // 3个基本周期 +6个采样周期+ 15个固定转换周期，共24个周期，48MHz ADCCLK条件下可达2MSa/s + + ADC_Init(CW_ADC1, &ADC_InitStructure); + + // 配置ADC2为从模式 + ADC_InitStructure.ADC_SlaveMod = ADC_SlaveMode_Enable; + ADC_Init(CW_ADC2, &ADC_InitStructure); + + ADC_ClearITPendingAll(CW_ADC1); + +#if (ADC_RETRIEVE_MODE == ADC_RETRIEVE_INTERRUPTION) + ADC_ITConfig(CW_ADC1, ADC_IT_EOC, ENABLE); + NVIC_EnableIRQ(ADC1_IRQn); +#endif + + //ADC使能 + ADC_Enable(CW_ADC1); + ADC_Enable(CW_ADC2); + ADC_SoftwareStartConvCmd(CW_ADC1, ENABLE); + + while (1) + { +#if (ADC_RETRIEVE_MODE == ADC_RETRIEVE_POLLING) + + while (!(CW_ADC1->ISR & ADCx_ISR_EOC_Msk)); + ADC_ClearITPendingBit(CW_ADC1,ADC_IT_EOC); + valueAdc1 = ADC_GetConversionValue(CW_ADC1,0); + valueAdc2 = ADC_GetConversionValue(CW_ADC2,0); +#endif + +#if (ADC_RETRIEVE_MODE == ADC_RETRIEVE_INTERRUPTION) + + if (gFlagIrq & ADCx_ISR_EOC_Msk) + { + valueAdc1 = ADC_GetConversionValue(CW_ADC1, 0); + valueAdc2 = ADC_GetConversionValue(CW_ADC2,0); + gFlagIrq = 0; + } + +#endif + + Bsp_Led_Tog(&LED1); + printf("The ADC1 Result:0x%3x[%d]\r\n", valueAdc1, valueAdc1); + printf("The ADC2 Result:0x%3x[%d]\r\n", valueAdc2, valueAdc2); + SysTickDelay(300); + + } +} + + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/readme.txt new file mode 100644 index 0000000..0ee7cba --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_master_slave_sw/readme.txt @@ -0,0 +1,34 @@ +示例目的： + 演示ADC1与ADC2同步启动的功能。ADC1做主，ADC2做从，通过ADC1的启动同步启动ADC2。 + +硬件资源： + 1. CW32L012CxTx StartKit + 2. 系统时钟源为默认的HSIOSC 24分频，4MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=4MHz + 3. ADC1的时钟源为PCLK，1分频， 4MHz + 4. ADC2的时钟源为PCLK，1分频， 4MHz + 5. PB09(LED1)设置为PUSH-PULL输出 + 6. PB05设置为ADC1_SAM,指示转换时间。 + 7. PA04设置为ADC2_SAM,指示转换时间。 + 7. uart3配置为115200bps，作为调试打印 + +演示说明： + ADC1使用通道为AIN0:PA00。 + ADC2使用通道为AIN0：PA05 + ADC转换完成，LED1闪烁,并通过UART3输出转换结果 + 支持查询模式和中断模式，获取采样结果 + 支持单次转换和连续连续 + + +使用说明： ++ EWARM + 1. 打开adc_sgl_sw.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开adc_sgl_sw.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/EWARM/project.ewp new file mode 100644 index 0000000..ea46fea --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/MDK/adc_sqr_irq_sw.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/MDK/adc_sqr_irq_sw.uvoptx new file mode 100644 index 0000000..2641a74 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/MDK/adc_sqr_irq_sw.uvoptx @@ -0,0 +1,378 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + adc_sqr_irq_sw + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"CW-DAPLINK(CMSIS-DAP)" -U6713442356488877066CFF50 -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0Flashcw32l012_TEST.FLM -FS00 -FL010000 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012_TEST.FLM) + + + 0 + UL2CM3 + -UV0010M9E -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0Flashcw32l012_TEST.FLM -FS00 -FL010000 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\ADC1 + 35905 + + + + 1 + 1 + 0 + 2 + 1000000 + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_adc.c + cw32l012_adc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/MDK/adc_sqr_irq_sw.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/MDK/adc_sqr_irq_sw.uvprojx new file mode 100644 index 0000000..ce4668c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/MDK/adc_sqr_irq_sw.uvprojx @@ -0,0 +1,503 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + adc_sqr_irq_sw + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + adc_sqr_irq_sw + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_adc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_adc.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/USER/inc/main.h new file mode 100644 index 0000000..3d43022 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void LED_Init(void); +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/USER/src/main.c new file mode 100644 index 0000000..489a378 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/USER/src/main.c @@ -0,0 +1,197 @@ +/** + * @file main.c + * @author WHXY + * @version 0.1 + * @date 2024-08-07 + * @brief + * + * @copyright All rights reserved. + * + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + * + */ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "cw32l012_systick.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_adc.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +uint16_t gAdcResult[8]; +volatile uint8_t gFlagIrq; + + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief ADC I/O初始化 + * + */ +void ADC_PortInit(void) +{ + //打开GPIO时钟 + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + //打开ADC时钟 + __SYSCTRL_ADC_CLK_ENABLE(); + + //set PA00 as AIN0 INPUT + PA00_ANALOG_ENABLE(); + //set PA01 as AIN1 INPUT + PA01_ANALOG_ENABLE(); + //set PA02 as AIN2 INPUT + PA02_ANALOG_ENABLE(); + //set PA03 as AIN2 INPUT + PA03_ANALOG_ENABLE(); + //set PA04 as AIN2 INPUT + PA04_ANALOG_ENABLE(); + //set PA05 as AIN5 INPUT + PA05_ANALOG_ENABLE(); + //set PA06 as AIN6 INPUT + PA06_ANALOG_ENABLE(); + //set PB00 as AIN7 INPUT + PB00_ANALOG_ENABLE(); + //set PB01 as AIN8 INPUT + PB01_ANALOG_ENABLE(); + + // PB05 作为采样时序指示 + PB05_DIGTAL_ENABLE(); + PB05_DIR_OUTPUT(); + PB05_PUSHPULL_ENABLE(); + PB05_AFx_ADC1SAM(); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + uint8_t i; + ADC_InitTypeDef ADC_InitStructure = {0}; + + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV6); + + InitTick(16000000); + + Bsp_Init(16000000); + + //配置ADC输入端口 + ADC_PortInit(); + + //ADC序列转换模式配置 + ADC_InitStructure.ADC_ClkDiv = ADC_Clk_Div1; // PCLK/1 + ADC_InitStructure.ADC_ConvertMode = ADC_ConvertMode_Continuous; + ADC_InitStructure.ADC_IN0.ADC_InputChannel = ADC_InputCH0; + ADC_InitStructure.ADC_IN0.ADC_SampTime = ADC_SampTime6Clk; + ADC_InitStructure.ADC_IN1.ADC_InputChannel = ADC_InputCH1; + ADC_InitStructure.ADC_IN1.ADC_SampTime = ADC_SampTime6Clk; + ADC_InitStructure.ADC_IN2.ADC_InputChannel = ADC_InputCH2; + ADC_InitStructure.ADC_IN2.ADC_SampTime = ADC_SampTime6Clk; + ADC_InitStructure.ADC_IN3.ADC_InputChannel = ADC_InputCH3; + ADC_InitStructure.ADC_IN3.ADC_SampTime = ADC_SampTime6Clk; + ADC_InitStructure.ADC_IN4.ADC_InputChannel = ADC_InputCH4; + ADC_InitStructure.ADC_IN4.ADC_SampTime = ADC_SampTime6Clk; + ADC_InitStructure.ADC_IN5.ADC_InputChannel = ADC_InputCH5; + ADC_InitStructure.ADC_IN5.ADC_SampTime = ADC_SampTime6Clk; + ADC_InitStructure.ADC_IN6.ADC_InputChannel = ADC_InputCH6; + ADC_InitStructure.ADC_IN6.ADC_SampTime = ADC_SampTime6Clk; + ADC_InitStructure.ADC_IN7.ADC_InputChannel = ADC_InputCH7; + ADC_InitStructure.ADC_IN7.ADC_SampTime = ADC_SampTime6Clk; + ADC_InitStructure.ADC_SQREns = ADC_SqrEns0to7; + + ADC_Init(CW_ADC1, &ADC_InitStructure); + + ADC_ClearITPendingAll(CW_ADC1); + +// ADC_ITConfig(CW_ADC1, ADC_IT_EOS, ENABLE); +// NVIC_EnableIRQ(ADC1_IRQn); + + //ADC使能 + ADC_Enable(CW_ADC1); + ADC_SoftwareStartConvCmd(CW_ADC1, ENABLE); + + while (1) + { + /* 序列通道连续采样模式 */ + if (CW_ADC1->ISR & ADCx_ISR_EOS_Msk) + { + ADC_SoftwareStartConvCmd(CW_ADC1,DISABLE); + ADC_ClearITPendingAll(CW_ADC1); + + for (i = 0; i<8; i++) + { + gAdcResult[i] = ADC_GetConversionValue(CW_ADC1, i); + printf("The sampling value of Channel %d is %d\r\n", i, gAdcResult[i]); + } + + ADC_SoftwareStartConvCmd(CW_ADC1,ENABLE); + } + + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/readme.txt new file mode 100644 index 0000000..d6ab467 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_multi-channel_sequence_conversion/readme.txt @@ -0,0 +1,27 @@ +示例目的： + 演示软件触发ADC模块进行序列转换模式。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟6分频，16MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=16MHz + 4. ADC1的时钟源为PCLK，1分频 + + +演示说明： + ADC SQR通道分别为：AIN00:PA00, AIN01:PA01, AIN02:PA02, AIN03:PA03, AIN04:PA04, AIN05:PA05, + AIN06:PA06, AIN07:PB00。 + 转换完成后，转换结果通过板载串口送出 + +使用说明： ++ EWARM + 1. 打开adc_sqr_irq_sw.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开adc_sqr_irq_sw.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/EWARM/project.ewp new file mode 100644 index 0000000..3651a1b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/EWARM/project.ewp @@ -0,0 +1,2261 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_spi.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/MDK/project.uvoptx new file mode 100644 index 0000000..a0e4307 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/MDK/project.uvoptx @@ -0,0 +1,435 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + DLGUARM + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + + 0 + 1 + RamBuff + + + 1 + 1 + &UART_CRValue + + + + + 1 + 0 + 0x2000000C + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\ADC1 + 35905 + + + System Viewer\DMA + 35903 + + + System Viewer\UART3 + 35904 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_adc.c + cw32l012_adc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_dma.c + cw32l012_dma.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_spi.c + cw32l012_spi.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 12 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/MDK/project.uvprojx new file mode 100644 index 0000000..0ee27d7 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/MDK/project.uvprojx @@ -0,0 +1,493 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 3 + 5 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_adc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_adc.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_dma.c + 1 + ..\..\..\..\Libraries\src\cw32l012_dma.c + + + cw32l012_spi.c + 1 + ..\..\..\..\Libraries\src\cw32l012_spi.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/USER/inc/main.h new file mode 100644 index 0000000..f31a96f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/USER/inc/main.h @@ -0,0 +1,86 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +#define ADC_RETRIEVE_POLLING 0 +#define ADC_RETRIEVE_INTERRUPTION 1 + +#define ADC_RETRIEVE_MODE ADC_RETRIEVE_POLLING + +#ifndef ADC_RETRIEVE_MODE +#define ADC_RETRIEVE_MODE ADC_RETRIEVE_POLLING +#endif + +#define ADC_CONVERT_ONCE 0 +#define ADC_CONVERT_CONTINUE 1 + +#define ADC_CONVERT_MODE ADC_CONVERT_CONTINUE + +#ifndef ADC_CONVERT_MODE +#define ADC_CONVERT_MODE ADC_CONVERT_CONTINUE +#endif +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/USER/src/main.c new file mode 100644 index 0000000..e39c6ca --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/USER/src/main.c @@ -0,0 +1,250 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "cw32l012_systick.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_adc.h" +#include "cw32l012_dma.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint16_t valueAdc1, valueAdc2; + +volatile uint8_t gFlagIrq; + +uint32_t RamBuff[8]; +volatile uint32_t RegisterValue; + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +static void RCC_Config(void); +static void ADC_PortInit(void); +static void ADC_Config(void); +static void DMA_Config(void); + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + RCC_Config(); + //使用sysTick,产生1ms中断计时 + InitTick(16000000); + + Bsp_Uart_Init(16000000, 1000000); // 将打印串口的波特率改为1Mbps + + ADC_Config(); + DMA_Config(); + ADC_SoftwareStartConvCmd(CW_ADC1, ENABLE); + + while (1) + { + if (CW_DMA->ISR_f.TC2) + { + // 传输完成，暂停串口的DMA功能，待ADC转换完成后触发DMA功能再次打开 + CW_UART3->CR2 = 0; + CW_DMA->ICR = 0; + } + } +} + +static void RCC_Config(void) +{ + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI16MHZ); // HSI分频到16Mhz +} + +/** + * @brief ADC I/O初始化 + * + */ +static void ADC_PortInit(void) +{ + //打开GPIO时钟 + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + + //set PA00 as AIN0 INPUT + PA00_ANALOG_ENABLE(); + //set PA01 as AIN1 INPUT + PA01_ANALOG_ENABLE(); + //set PA02 as AIN2 INPUT + PA02_ANALOG_ENABLE(); + //set PA03 as AIN2 INPUT + PA03_ANALOG_ENABLE(); + //set PA04 as AIN2 INPUT + PA04_ANALOG_ENABLE(); + //set PA05 as AIN5 INPUT + PA05_ANALOG_ENABLE(); + //set PA06 as AIN6 INPUT + PA06_ANALOG_ENABLE(); + //set PA07 as AIN7 INPUT + PA07_ANALOG_ENABLE(); + + // set PB05 as ADC1_SAM + PB05_AFx_ADC1SAM(); + PB05_DIGTAL_ENABLE(); + PB05_DIR_OUTPUT(); + PB05_PUSHPULL_ENABLE(); +} + +static void ADC_Config(void) +{ + ADC_InitTypeDef ADC_InitStructure = {0}; + ADC_DMA_TriggerTypeDef ADC_DmaTriggerStruct; + + + ADC_InitStructure.ADC_ClkDiv = ADC_Clk_Div8; + ADC_InitStructure.ADC_SlaveMod = ADC_SlaveMode_Disable; + ADC_InitStructure.ADC_ConvertMode = ADC_ConvertMode_Continuous; // 连续采样 + ADC_InitStructure.ADC_SQREns = ADC_SqrEns0to7; // 8通道序列采样 + ADC_InitStructure.ADC_IN0.ADC_InputChannel = ADC_InputCH0; + ADC_InitStructure.ADC_IN0.ADC_SampTime = ADC_SampTime518Clk; + ADC_InitStructure.ADC_IN1.ADC_InputChannel = ADC_InputCH1; + ADC_InitStructure.ADC_IN1.ADC_SampTime = ADC_SampTime518Clk; + ADC_InitStructure.ADC_IN2.ADC_InputChannel = ADC_InputCH2; + ADC_InitStructure.ADC_IN2.ADC_SampTime = ADC_SampTime518Clk; + ADC_InitStructure.ADC_IN3.ADC_InputChannel = ADC_InputCH3; + ADC_InitStructure.ADC_IN3.ADC_SampTime = ADC_SampTime518Clk; + ADC_InitStructure.ADC_IN4.ADC_InputChannel = ADC_InputCH4; + ADC_InitStructure.ADC_IN4.ADC_SampTime = ADC_SampTime518Clk; + ADC_InitStructure.ADC_IN5.ADC_InputChannel = ADC_InputCH5; + ADC_InitStructure.ADC_IN5.ADC_SampTime = ADC_SampTime518Clk; + ADC_InitStructure.ADC_IN6.ADC_InputChannel = ADC_InputCH6; + ADC_InitStructure.ADC_IN6.ADC_SampTime = ADC_SampTime518Clk; + ADC_InitStructure.ADC_IN7.ADC_InputChannel = ADC_InputCH7; + ADC_InitStructure.ADC_IN7.ADC_SampTime = ADC_SampTime518Clk; + ADC_Init(CW_ADC1, &ADC_InitStructure); + ADC_ClearITPendingAll(CW_ADC1); + + //配置ADC测试IO口 + ADC_PortInit(); + + // 配置DMA使能 + ADC_DmaTriggerStruct.dma_eoc_enable = FALSE; + ADC_DmaTriggerStruct.dma_eos_enable = TRUE; + ADC_DMACmd(CW_ADC1, &ADC_DmaTriggerStruct); + + //ADC使能 + ADC_Enable(CW_ADC1); +} + + +static void DMA_Config(void) +{ + DMA_InitTypeDef DMA_InitStructure = {0}; + + RegisterValue = 0x80; // 此值有DMA传输UART3的CR2寄存器，使能UART的DMA tx + + //打开DMA时钟 + __SYSCTRL_DMA_CLK_ENABLE(); + + DMA_InitStructure.DataSize = DMA_DATA_SIZE_32BITS; + DMA_InitStructure.SrcIncrement = DMA_ADDRESS_FIXED; + DMA_InitStructure.DstIncrement = DMA_ADDRESS_FIXED; + DMA_InitStructure.TransferMode = DMA_MODE_BLOCK; + DMA_InitStructure.TransferCount = 1; + DMA_InitStructure.BlockCount = 1; //必须设置为1 + DMA_InitStructure.SrcAddress = (uint32_t) & (RegisterValue); + DMA_InitStructure.DstAddress = (uint32_t) & (CW_UART3->CR2); // 使能UART的DMA tx + DMA_InitStructure.TriggerType = DMA_TRIGGER_HARDWARE; + DMA_InitStructure.TriggerSource = DMA_TRIGGER_SRC_ADC1_SEQ; + DMA_InitStructure.RestartEnable = TRUE; + + DMA_Init(DMA_CHANNEL_1, &DMA_InitStructure); + DMA_Cmd(DMA_CHANNEL_1, ENABLE); + + DMA_InitStructure.DataSize = DMA_DATA_SIZE_8BITS; + DMA_InitStructure.SrcIncrement = DMA_ADDRESS_INCREMENT; + DMA_InitStructure.DstIncrement = DMA_ADDRESS_FIXED; + DMA_InitStructure.TransferMode = DMA_MODE_BLOCK; + DMA_InitStructure.TransferCount = 32; + DMA_InitStructure.BlockCount = 1; //必须设置为1 + DMA_InitStructure.SrcAddress = (uint32_t) & (CW_ADC1->RESULT0); + DMA_InitStructure.DstAddress = (uint32_t) & (CW_UART3->TDR); // UART通过DMA传输ADC的转换结果 + DMA_InitStructure.TriggerType = DMA_TRIGGER_HARDWARE; + DMA_InitStructure.TriggerSource = DMA_TRIGGER_SRC_UART3_TX; + DMA_InitStructure.RestartEnable = TRUE; + + DMA_Init(DMA_CHANNEL_2, &DMA_InitStructure); + DMA_Cmd(DMA_CHANNEL_2, ENABLE); +} + + + + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/readme.txt new file mode 100644 index 0000000..0f41c39 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_results_with_dma_transfer/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 演示ADC1与ADC2同步启动的功能。ADC1做主，ADC2做从，通过ADC1的启动同步启动ADC2。 + +硬件资源： + 1. CW32L012CxTx StartKit + 2. 系统时钟源为默认的HSIOSC ，分频到16MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=16MHz + 3. ADC1的时钟源为PCLK，8分频， 2MHz + 4. PB05设置为ADC1_SAM,指示转换时间。 + 5. uart3配置为1Mbps，作为调试打印 + 6. DMA 通道1设置为ADC的EOS触发 + 7. DMA 通道2设置为UART3的TXE触发 + +演示说明： + ADC1使用通道为AIN0~7，序列采样结束后，触发DMA通道1，开启UART3的DMA功能，UART3开始将采样结果依次打印。 + + +使用说明： ++ EWARM + 1. 打开adc_sgl_sw.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开adc_sgl_sw.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/EWARM/project.ewp new file mode 100644 index 0000000..7908612 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/EWARM/project.ewp @@ -0,0 +1,2255 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/MDK/adc_sgl_sw.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/MDK/adc_sgl_sw.uvoptx new file mode 100644 index 0000000..bf7916c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/MDK/adc_sgl_sw.uvoptx @@ -0,0 +1,377 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FN1 -FC1000 -FD20000000 -FF0FlashCW32L012_TEST -FL010000 -FS00 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_adc.c + cw32l012_adc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/MDK/adc_sgl_sw.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/MDK/adc_sgl_sw.uvprojx new file mode 100644 index 0000000..c095098 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/MDK/adc_sgl_sw.uvprojx @@ -0,0 +1,484 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_adc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_adc.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/USER/inc/main.h new file mode 100644 index 0000000..d528b35 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/USER/inc/main.h @@ -0,0 +1,89 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +#define ADC_RETRIEVE_POLLING 0 +#define ADC_RETRIEVE_INTERRUPTION 1 + +#define ADC_RETRIEVE_MODE ADC_RETRIEVE_POLLING + +#ifndef ADC_RETRIEVE_MODE +#define ADC_RETRIEVE_MODE ADC_RETRIEVE_POLLING +#endif + +#define ADC_CONVERT_ONCE 0 +#define ADC_CONVERT_CONTINUE 1 + +#define ADC_CONVERT_MODE ADC_CONVERT_CONTINUE + +#ifndef ADC_CONVERT_MODE +#define ADC_CONVERT_MODE ADC_CONVERT_CONTINUE +#endif +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/USER/src/main.c new file mode 100644 index 0000000..89e7b76 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/USER/src/main.c @@ -0,0 +1,183 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "cw32l012_systick.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_adc.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint16_t valueAdc; + +volatile uint8_t gFlagIrq; + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief ADC I/O初始化 + * + */ +void ADC_PortInit(void) +{ + //打开GPIO时钟 + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + //打开ADC时钟 + __SYSCTRL_ADC_CLK_ENABLE(); + + //set PA00 as AIN0 INPUT + PA00_ANALOG_ENABLE(); + + // set PB05 as ADC1_SAM + PB05_AFx_ADC1SAM(); + PB05_DIGTAL_ENABLE(); + PB05_DIR_OUTPUT(); + PB05_PUSHPULL_ENABLE(); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + ADC_InitTypeDef ADC_InitStructure = {0}; + + // 系统时钟配置为8MHz + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI96MHZ); + + //使用sysTick,产生1ms中断计时 + InitTick(96000000); + + // 调试串口初始化 + Bsp_Init(96000000); + + //配置ADC测试IO口 + ADC_PortInit(); + + ADC_InitStructure.ADC_ClkDiv = ADC_Clk_Div2; + ADC_InitStructure.ADC_SlaveMod = ADC_SlaveMode_Disable; +#if (ADC_CONVERT_MODE == ADC_CONVERT_ONCE) + ADC_InitStructure.ADC_ConvertMode = ADC_ConvertMode_Once; // 单次采样 +#else + ADC_InitStructure.ADC_ConvertMode = ADC_ConvertMode_Continuous; // 连续采样 +#endif + ADC_InitStructure.ADC_SQREns = ADC_SqrEns0to0; // 单通道 + ADC_InitStructure.ADC_IN0.ADC_InputChannel = ADC_InputCH0; + ADC_InitStructure.ADC_IN0.ADC_SampTime = ADC_SampTime9Clk; // 9个采样周期+ 15个固定转换周期，共24个周期，48MHz ADCCLK条件下可达2MSa/s + + ADC_Init(CW_ADC1, &ADC_InitStructure); + + ADC_ClearITPendingAll(CW_ADC1); + +#if (ADC_RETRIEVE_MODE == ADC_RETRIEVE_INTERRUPTION) + ADC_ITConfig(CW_ADC1, ADC_IT_EOC, ENABLE); + NVIC_EnableIRQ(ADC1_IRQn); +#endif + + //ADC使能 + ADC_Enable(CW_ADC1); + ADC_SoftwareStartConvCmd(CW_ADC1, ENABLE); + + while (1) + { +#if (ADC_RETRIEVE_MODE == ADC_RETRIEVE_POLLING) + + while (!(CW_ADC1->ISR & ADCx_ISR_EOC_Msk)); + ADC_ClearITPendingBit(CW_ADC1,ADC_IT_EOC); + valueAdc = ADC_GetConversionValue(CW_ADC1,0); +#endif + +#if (ADC_RETRIEVE_MODE == ADC_RETRIEVE_INTERRUPTION) + + if (gFlagIrq & ADCx_ISR_EOC_Msk) + { + valueAdc = ADC_GetConversionValue(CW_ADC1, 0); + gFlagIrq = 0; + } + +#endif + + Bsp_Led_Tog(&LED1); + printf("The ADC Result:0x%3x[%d]\r\n", valueAdc, valueAdc); + SysTickDelay(300); + } +} + + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/readme.txt new file mode 100644 index 0000000..2b13dfc --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_sw/readme.txt @@ -0,0 +1,31 @@ +示例目的： + 演示软件启动ADC单通道转换模式。 + +硬件资源： + 1. CW32L012CxTx StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟1分频，96MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=96MHz + 4. ADC1的时钟源为PCLK，2分频， 48MHz，ADC1的采样率最高达2M/s + 5. PB09(LED1)设置为PUSH-PULL输出 + 6. PB05设置为ADC1_SAM,指示转换时间。 + 7. uart3配置为115200bps，作为调试打印 + +演示说明： + ADC通道为AIN0:PA00。 + ADC转换完成，LED1闪烁,并通过UART3输出转换结果 + 支持查询模式和中断模式，获取采样结果 + 支持单次转换和连续连续 + + +使用说明： ++ EWARM + 1. 打开adc_sgl_sw.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开adc_sgl_sw.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/EWARM/project.ewp new file mode 100644 index 0000000..7908612 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/EWARM/project.ewp @@ -0,0 +1,2255 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/MDK/adc_sgl_wdt.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/MDK/adc_sgl_wdt.uvoptx new file mode 100644 index 0000000..612e1ea --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/MDK/adc_sgl_wdt.uvoptx @@ -0,0 +1,394 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + adc_sgl_wdt + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0Flashcw32l012_TEST.FLM -FS00 -FL010000 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012_TEST.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + DLGTARM + (1010=75,104,486,606,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + DLGUARM + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + + 0 + 1 + uwTick + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_adc.c + cw32l012_adc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/MDK/adc_sgl_wdt.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/MDK/adc_sgl_wdt.uvprojx new file mode 100644 index 0000000..81d0a09 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/MDK/adc_sgl_wdt.uvprojx @@ -0,0 +1,493 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + adc_sgl_wdt + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + adc_sgl_wdt + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_adc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_adc.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/USER/inc/main.h new file mode 100644 index 0000000..c708839 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..362fa97 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/USER/src/interrupts_cw32l012.c @@ -0,0 +1,439 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + extern uint8_t gFlagIrq; + /* USER CODE BEGIN */ + gFlagIrq = CW_ADC1->ISR; + CW_ADC1->ICR = 0; + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/USER/src/main.c new file mode 100644 index 0000000..1592a78 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/USER/src/main.c @@ -0,0 +1,174 @@ +/** + * @file main.c + * @author WHXY + * @version 0.1 + * @date 2024-08-07 + * @brief + * + * @copyright All rights reserved. + * + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + * + */ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "cw32l012_systick.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_adc.h" + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ +uint16_t valueAdc; +volatile uint8_t gFlagIrq; + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** +* Local pre-processor symbols/macros ('#define') +******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief ADC I/O初始化 + * + */ +void ADC_PortInit(void) +{ + //打开GPIO时钟 + __SYSCTRL_GPIOA_CLK_ENABLE(); + //打开ADC时钟 + __SYSCTRL_ADC_CLK_ENABLE(); + + //set PA00 as AIN0 INPUT + PA00_ANALOG_ENABLE(); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + uint32_t TicksCount; + ADC_WatchdogTypeDef ADC_WdtStructure = {0}; + + InitTick(4000000ul); //初始化SysTick + + // 初始化板上资源 + Bsp_Init(4000000ul); + + //配置ADC测试IO + ADC_PortInit(); + + //ADC模拟看门狗通道初始化 + ADC_WdtStructure.ADC_InitStruct.ADC_ClkDiv = ADC_Clk_Div1; + ADC_WdtStructure.ADC_InitStruct.ADC_ConvertMode = ADC_ConvertMode_Continuous; + ADC_WdtStructure.ADC_InitStruct.ADC_SQREns = ADC_SqrEns0to0; + ADC_WdtStructure.ADC_InitStruct.ADC_IN0.ADC_InputChannel = ADC_InputCH0; + ADC_WdtStructure.ADC_InitStruct.ADC_IN0.ADC_SampTime = ADC_SampTime9Clk; + ADC_WdtStructure.ADC_WatchdogCHx = ADC_WATCHDOG_IN0; // 模拟看门狗监控的是输入通道 + ADC_WdtStructure.ADC_WatchdogOverHighIrq = ENABLE; + ADC_WdtStructure.ADC_WatchdogUnderLowIrq = ENABLE; + ADC_WdtStructure.ADC_WatchdogVth = 0x700; + ADC_WdtStructure.ADC_WatchdogVtl = 0x600; + + ADC_WatchdogInit(CW_ADC1, &ADC_WdtStructure); + ADC_ITConfig(CW_ADC1, ADC_IT_AWDH | ADC_IT_AWDL | ADC_IT_EOC, ENABLE); + ADC_ClearITPendingAll(CW_ADC1); + + NVIC_EnableIRQ(ADC1_IRQn); + //ADC使能 + ADC_Enable(CW_ADC1); + ADC_SoftwareStartConvCmd(CW_ADC1, ENABLE); + + TicksCount = GetTick(); + + while (1) + { + if ((gFlagIrq & ADCx_ISR_EOC_Msk) && !(gFlagIrq & (ADCx_ISR_AWDH_Msk | ADCx_ISR_AWDL_Msk))) + { + gFlagIrq &= ~ADCx_ISR_EOC_Msk; + + if (GetTick() - TicksCount >= 1000) + { + Bsp_Led_Tog(&LED1); + TicksCount = GetTick(); + valueAdc = ADC_GetConversionValue(CW_ADC1, ADC_RESULT_0); + printf("The result is:0x%3x\r\n", valueAdc); + } + } + + if (gFlagIrq & ADCx_ISR_AWDH_Msk) + { + Bsp_Led_On(&LED1); + gFlagIrq &= ~ADCx_ISR_AWDH_Msk; + valueAdc = ADC_GetConversionValue(CW_ADC1, ADC_RESULT_0); + printf("The result is:0x%3x\r\n", valueAdc); + } + else if (gFlagIrq & ADCx_ISR_AWDL_Msk) + { + Bsp_Led_Off(&LED1); + gFlagIrq &= ~ADCx_ISR_AWDL_Msk; + valueAdc = ADC_GetConversionValue(CW_ADC1, ADC_RESULT_0); + printf("The result is:0x%3x\r\n", valueAdc); + } + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/readme.txt new file mode 100644 index 0000000..47362fd --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sgl_wdt/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 演示ADC模块单通道模拟看门狗功能。 + +硬件资源： + 1. CW32L012CxTx StartKit + 2. 系统时钟源为默认HSIOSC的24分配，4MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=4MHz + 3. ADC的时钟源为PCLK，1分频 + 4. PB09设置为PUSH-PULL输出，驱动LED1 + 5. UART3作为调试串口 + +演示说明： + 软件触发ADC模块进行单通道单次转换。LED1以0.5Hz的频率闪速 + ADC模拟看门狗通道为AIN0:PA00，下阈值为0x600, 上门限为0x700； + 外接可调直流电源到PA00，ADC转换完成，如果采样值小于下阈值，则LED1灭； + 如果采样值大于上阈值，LED1亮。 + +使用说明： ++ EWARM + 1. 打开adc_sgl_wdt.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开adc_sgl_wdt.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/EWARM/project.ewp new file mode 100644 index 0000000..3343511 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/EWARM/project.ewp @@ -0,0 +1,2258 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gtim.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/MDK/adc_sqr_ext_trig.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/MDK/adc_sqr_ext_trig.uvoptx new file mode 100644 index 0000000..d468179 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/MDK/adc_sqr_ext_trig.uvoptx @@ -0,0 +1,395 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + 0 + CMSIS_AGDI + -X"" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC2000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=2025,137,2232,358,0)(1008=2860,520,3236,756,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\ADC1 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_adc.c + cw32l012_adc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gtim.c + cw32l012_gtim.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 11 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + bsp + 1 + 0 + 0 + 0 + + 5 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/MDK/adc_sqr_ext_trig.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/MDK/adc_sqr_ext_trig.uvprojx new file mode 100644 index 0000000..b2b6bc8 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/MDK/adc_sqr_ext_trig.uvprojx @@ -0,0 +1,498 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_adc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_adc.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gtim.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/USER/inc/main.h new file mode 100644 index 0000000..8030395 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/USER/inc/main.h @@ -0,0 +1,84 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +#define ADC_RETRIEVE_POLLING 0 +#define ADC_RETRIEVE_INTERRUPTION 1 + +#define ADC_RETRIEVE_MODE ADC_RETRIEVE_INTERRUPTION + +#ifndef ADC_RETRIEVE_MODE +#define ADC_RETRIEVE_MODE ADC_RETRIEVE_POLLING +#endif + +#define ADC_CONVERT_ONCE 0 +#define ADC_CONVERT_CONTINUE 1 + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..7f13e7d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/USER/src/interrupts_cw32l012.c @@ -0,0 +1,442 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +extern volatile uint8_t gFlagIrq; +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + if(CW_ADC1->ISR_f.EOS) + { + gFlagIrq = CW_ADC1->ISR; + CW_ADC1->ICR = 0x00; + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/USER/src/main.c new file mode 100644 index 0000000..0bc6311 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/USER/src/main.c @@ -0,0 +1,228 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "cw32l012_systick.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_adc.h" +#include "cw32l012_gtim.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint16_t valueAdc[2]; + +volatile uint8_t gFlagIrq; + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +void GTIM_OutputConfig(void); +/** + * @brief ADC I/O初始化 + * + */ +void ADC_PortInit(void) +{ + //打开GPIO时钟 + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + //打开ADC时钟 + __SYSCTRL_ADC_CLK_ENABLE(); + + //set PA00 as AIN0 INPUT + //set PA01 as AIN1 INPUT + PA00_ANALOG_ENABLE(); + PA01_ANALOG_ENABLE(); + + // set PB05 as ADC1_SAM + PB05_AFx_ADC1SAM(); + PB05_DIGTAL_ENABLE(); + PB05_DIR_OUTPUT(); + PB05_PUSHPULL_ENABLE(); +} +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + ADC_InitTypeDef ADC_InitStructure = {0}; + + // 系统时钟配置为96MHz + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI96MHZ); + + //使用sysTick,产生1ms中断计时 + InitTick(96000000); + + // 调试串口初始化 + Bsp_Init(96000000); + + //配置ADC测试IO口 + ADC_PortInit(); + + ADC_InitStructure.ADC_ClkDiv = ADC_Clk_Div2;//ADCLK = PCLK/2 = 48MHz + ADC_InitStructure.ADC_SlaveMod = ADC_SlaveMode_Disable; + ADC_InitStructure.ADC_ConvertMode = ADC_ConvertMode_Once; // 单次采样 + ADC_InitStructure.ADC_SQREns = ADC_SqrEns0to1; // 双通道 + ADC_InitStructure.ADC_IN0.ADC_InputChannel = ADC_InputCH0; + ADC_InitStructure.ADC_IN0.ADC_SampTime = ADC_SampTime102Clk;//10个BaseSampTime+ 102个SampTime+ 15个固定转换周期，共127个ADCCLK周期，48MHz ADCCLK条件下需要2.6us + ADC_InitStructure.ADC_IN1.ADC_InputChannel = ADC_InputCH1; + ADC_InitStructure.ADC_IN1.ADC_SampTime = ADC_SampTime70Clk;//10个BaseSampTime+ 70个SampTime+ 15个固定转换周期，共95个ADCCLK周期，48MHz ADCCLK条件下需要1.98us + + ADC_Init(CW_ADC1, &ADC_InitStructure); + + ADC_ClearITPendingAll(CW_ADC1); + +#if (ADC_RETRIEVE_MODE == ADC_RETRIEVE_INTERRUPTION) + ADC_ITConfig(CW_ADC1, ADC_IT_EOS, ENABLE); + NVIC_EnableIRQ(ADC1_IRQn); +#endif + + //ADC使能 + ADC_Enable(CW_ADC1); + ADC_ExtTrigCfg(CW_ADC1,ADC_TRIG_GTIM1TRGO,ENABLE);//ADC外部触发源是GTIM1的TRGO信号 + + GTIM_OutputConfig(); + + while (1) + { +#if (ADC_RETRIEVE_MODE == ADC_RETRIEVE_POLLING) + + while (!(CW_ADC1->ISR & ADCx_ISR_EOS_Msk)); + ADC_ClearITPendingBit(CW_ADC1,ADC_IT_EOS); + valueAdc[0] = ADC_GetConversionValue(CW_ADC1,0); + valueAdc[1] = ADC_GetConversionValue(CW_ADC1,1); + + Bsp_Led_Tog(&LED1);//每1秒LED1翻转一次 + printf("The ADC sample PA00 , result is : %d\r\n", valueAdc[0]); + printf("The ADC sample PA01 , result is : %d\r\n", valueAdc[1]); +#endif + +#if (ADC_RETRIEVE_MODE == ADC_RETRIEVE_INTERRUPTION) + + if (gFlagIrq & ADCx_ISR_EOS_Msk) + { + valueAdc[0] = ADC_GetConversionValue(CW_ADC1, 0); + valueAdc[1] = ADC_GetConversionValue(CW_ADC1,1); + gFlagIrq = 0; + + Bsp_Led_Tog(&LED1);//每1秒LED1翻转一次 + printf("The ADC sample PA00 , result is : %d\r\n", valueAdc[0]); + printf("The ADC sample PA01 , result is : %d\r\n", valueAdc[1]); + } + +#endif + + } +} + +void GTIM_OutputConfig(void) +{ + //PB04---GTIM1_CH1 + __SYSCTRL_GPIOB_CLK_ENABLE(); + PB04_DIGTAL_ENABLE(); + PB04_DIR_OUTPUT(); + PB04_PUSHPULL_ENABLE(); + PB04_AFx_GTIM1CH1(); + + //GTIM1 + GTIM_InitTypeDef GTIM_InitStruct = {0}; + GTIM_OCModeCfgTypeDef GTIM_OCModeCfgStruct = {DISABLE, DISABLE, 0}; + + __SYSCTRL_GTIM1_CLK_ENABLE(); + + GTIM_InitStruct.AlignMode = GTIM_ALIGN_MODE_EDGE;//边沿计数 + GTIM_InitStruct.ARRBuffState = GTIM_ARR_BUFF_EN; + GTIM_InitStruct.Direction = GTIM_DIRECTION_UP; + GTIM_InitStruct.EventOption = GTIM_EVENT_NORMAL; + GTIM_InitStruct.Prescaler = 9600 - 1;//96M/9600 = 10KHz + GTIM_InitStruct.PulseMode = GTIM_PULSE_MODE_DIS; + GTIM_InitStruct.ReloadValue = 10000 - 1;//溢出时间 = 10000*0.1ms = 1s + GTIM_InitStruct.UpdateOption = GTIM_UPDATE_EN; + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + + GTIM_OCModeCfgStruct.FastMode = DISABLE; + GTIM_OCModeCfgStruct.OCMode = GTIM_OC_MODE_PWM2; + GTIM_OCModeCfgStruct.OCPolarity = GTIM_OC_POLAR_NONINVERT; + GTIM_OCModeCfgStruct.PreloadState = DISABLE; + GTIM_OC1ModeCfg(CW_GTIM1, >IM_OCModeCfgStruct); + + GTIM_SetCompare1(CW_GTIM1, 5000); + GTIM_OC1Cmd(CW_GTIM1, ENABLE); + + GTIM_Cmd(CW_GTIM1, ENABLE); + GTIM_MasterTRGOCfg(CW_GTIM1,GTIM_MASTER_TRGO_OC1REF);//GTIM1的TRGO信号源是OC1REF的上升沿时刻 +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/readme.txt new file mode 100644 index 0000000..6f58e3d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_ext_trig/readme.txt @@ -0,0 +1,31 @@ +示例目的： + 演示定时器外部触发启动ADC转换，定时1s采样PA00(AIN0)、PA01(AIN1)。 + +硬件资源： + 1. CW32L012CxTx StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟1分频，96MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=96MHz + 4. ADC1的时钟源为PCLK，2分频， 48MHz + 5. PB09(LED1)设置为PUSH-PULL输出 + 6. PB05设置为ADC1_SAM,指示转换时间，PA00、PA01模拟输入，作为AIN0、AIN1。 + 7. uart3配置为115200bps，作为调试打印 + 8.GTIM1的时钟源为PCLK，9600分频，溢出时间1s，CH1的占空比50%，PWM2模式，比较匹配时刻触发ADC序列采样 + 9. PB04设置为推挽输出，复用做GTIM1的CH1，输出PWM + +演示说明： + 通用定时器GTIM1定时1s自动触发ADC模块进行转换，ADC采样通道为PA00、PA01。 + ADC转换完成后，LED1的电平翻转，以0.5Hz的频率闪烁。可以通过PB04观察GTIM1_CH1的输出情况，PB05观察ADC的采样时刻 + + +使用说明： ++ EWARM + 1. 打开adc_sqr_ext_trig.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开adc_sqr_ext_trig.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/EWARM/project.ewp new file mode 100644 index 0000000..3343511 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/EWARM/project.ewp @@ -0,0 +1,2258 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gtim.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/MDK/adc_sqr_ext_trig.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/MDK/adc_sqr_ext_trig.uvoptx new file mode 100644 index 0000000..c8ce409 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/MDK/adc_sqr_ext_trig.uvoptx @@ -0,0 +1,407 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + 0 + CMSIS_AGDI + -X"CW-DAPLINK(CMSIS-DAP)" -U6713442356488877066CFF50 -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC2000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=2025,137,2232,358,0)(1008=2824,520,3200,756,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\ADC1 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_adc.c + cw32l012_adc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gtim.c + cw32l012_gtim.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_btim.c + cw32l012_btim.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 12 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + bsp + 1 + 0 + 0 + 0 + + 5 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/MDK/adc_sqr_ext_trig.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/MDK/adc_sqr_ext_trig.uvprojx new file mode 100644 index 0000000..64bdcad --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/MDK/adc_sqr_ext_trig.uvprojx @@ -0,0 +1,503 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_adc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_adc.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gtim.c + + + cw32l012_btim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_btim.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/USER/inc/main.h new file mode 100644 index 0000000..8030395 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/USER/inc/main.h @@ -0,0 +1,84 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +#define ADC_RETRIEVE_POLLING 0 +#define ADC_RETRIEVE_INTERRUPTION 1 + +#define ADC_RETRIEVE_MODE ADC_RETRIEVE_INTERRUPTION + +#ifndef ADC_RETRIEVE_MODE +#define ADC_RETRIEVE_MODE ADC_RETRIEVE_POLLING +#endif + +#define ADC_CONVERT_ONCE 0 +#define ADC_CONVERT_CONTINUE 1 + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..7f13e7d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/USER/src/interrupts_cw32l012.c @@ -0,0 +1,442 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +extern volatile uint8_t gFlagIrq; +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + if(CW_ADC1->ISR_f.EOS) + { + gFlagIrq = CW_ADC1->ISR; + CW_ADC1->ICR = 0x00; + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/USER/src/main.c new file mode 100644 index 0000000..c261a08 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/USER/src/main.c @@ -0,0 +1,206 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "cw32l012_systick.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_adc.h" +#include "cw32l012_gtim.h" +#include "cw32l012_btim.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint16_t valueAdc[2]; + +volatile uint8_t gFlagIrq; + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +void BTIM_TriggerOutConfig(void); + +/** + * @brief ADC I/O初始化 + * + */ +void ADC_PortInit(void) +{ + //打开GPIO时钟 + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + //打开ADC时钟 + __SYSCTRL_ADC_CLK_ENABLE(); + + //set PA00 as AIN0 INPUT + //set PA01 as AIN1 INPUT + PA00_ANALOG_ENABLE(); + PA01_ANALOG_ENABLE(); + + // set PB05 as ADC1_SAM + PB05_AFx_ADC1SAM(); + PB05_DIGTAL_ENABLE(); + PB05_DIR_OUTPUT(); + PB05_PUSHPULL_ENABLE(); +} +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + ADC_InitTypeDef ADC_InitStructure = {0}; + + // 系统时钟配置为96MHz + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI96MHZ); + + //使用sysTick,产生1ms中断计时 + InitTick(96000000); + + // 调试串口初始化 + Bsp_Init(96000000); + + //配置ADC测试IO口 + ADC_PortInit(); + + ADC_InitStructure.ADC_ClkDiv = ADC_Clk_Div2;//ADCLK = PCLK/2 = 48MHz + ADC_InitStructure.ADC_SlaveMod = ADC_SlaveMode_Disable; + ADC_InitStructure.ADC_ConvertMode = ADC_ConvertMode_Once; // 单次采样 + ADC_InitStructure.ADC_SQREns = ADC_SqrEns0to1; // 双通道 + ADC_InitStructure.ADC_IN0.ADC_InputChannel = ADC_InputCH0; + ADC_InitStructure.ADC_IN0.ADC_SampTime = ADC_SampTime102Clk;//10个BaseSampTime+ 102个SampTime+ 15个固定转换周期，共127个ADCCLK周期，48MHz ADCCLK条件下需要2.6us + ADC_InitStructure.ADC_IN1.ADC_InputChannel = ADC_InputCH1; + ADC_InitStructure.ADC_IN1.ADC_SampTime = ADC_SampTime70Clk;//10个BaseSampTime+ 70个SampTime+ 15个固定转换周期，共95个ADCCLK周期，48MHz ADCCLK条件下需要1.98us + + ADC_Init(CW_ADC1, &ADC_InitStructure); + + ADC_ClearITPendingAll(CW_ADC1); + +#if (ADC_RETRIEVE_MODE == ADC_RETRIEVE_INTERRUPTION) + ADC_ITConfig(CW_ADC1, ADC_IT_EOS, ENABLE); + NVIC_EnableIRQ(ADC1_IRQn); +#endif + + //ADC使能 + ADC_Enable(CW_ADC1); + ADC_ExtTrigCfg(CW_ADC1,ADC_TRIG_BTIM1TRGO,ENABLE); //ADC外部触发源是BTIM1的TRGO信号 + + //配置BTIM1为触发输出模式 + BTIM_TriggerOutConfig(); + while (1) + { +#if (ADC_RETRIEVE_MODE == ADC_RETRIEVE_POLLING) + + while (!(CW_ADC1->ISR & ADCx_ISR_EOS_Msk)); + ADC_ClearITPendingBit(CW_ADC1,ADC_IT_EOS); + valueAdc[0] = ADC_GetConversionValue(CW_ADC1,0); + valueAdc[1] = ADC_GetConversionValue(CW_ADC1,1); + + Bsp_Led_Tog(&LED1);//每1秒LED1翻转一次 + printf("The ADC sample PA00 , result is : %d\r\n", valueAdc[0]); + printf("The ADC sample PA01 , result is : %d\r\n", valueAdc[1]); +#endif + +#if (ADC_RETRIEVE_MODE == ADC_RETRIEVE_INTERRUPTION) + + if (gFlagIrq & ADCx_ISR_EOS_Msk) + { + valueAdc[0] = ADC_GetConversionValue(CW_ADC1, 0); + valueAdc[1] = ADC_GetConversionValue(CW_ADC1,1); + gFlagIrq = 0; + + Bsp_Led_Tog(&LED1);//每1秒LED1翻转一次 + printf("The ADC sample PA00 , result is : %d\r\n", valueAdc[0]); + printf("The ADC sample PA01 , result is : %d\r\n", valueAdc[1]); + } + +#endif + + } +} + +void BTIM_TriggerOutConfig(void) +{ + BTIM_TimeBaseInitTypeDef BTIM_InitStruct; + + BTIM_InitStruct.BTIM_CountMode = BTIM_COUNT_MODE_REPETITIVE; + BTIM_InitStruct.BTIM_Mode = BTIM_MODE_TIMER; + BTIM_InitStruct.BTIM_Period = 10000 - 1; + BTIM_InitStruct.BTIM_Prescaler = 9600 - 1; + + __SYSCTRL_BTIM123_CLK_ENABLE(); + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_InitStruct); + BTIM_MasterOutputTriggerConfig(CW_BTIM1, BTIM_MASTER_OUTPUT_TRIGGER_UPDATE); + BTIM_Cmd(CW_BTIM1, ENABLE); +} +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/readme.txt new file mode 100644 index 0000000..e556a02 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ADC/adc_sqr_trig_byBtim/readme.txt @@ -0,0 +1,31 @@ +示例目的： + 演示定时器外部触发启动ADC转换，定时1s采样PA00(AIN0)、PA01(AIN1)。 + +硬件资源： + 1. CW32L012CxTx StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟1分频，96MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=96MHz + 4. ADC1的时钟源为PCLK，2分频， 48MHz + 5. PB09(LED1)设置为PUSH-PULL输出 + 6. PB05设置为ADC1_SAM,指示转换时间，PA00、PA01模拟输入，作为AIN0、AIN1。 + 7. uart3配置为115200bps，作为调试打印 + 8. BTIM1的时钟源为PCLK，9600分频，溢出时间1s， + + +演示说明： + 基本定时器BTIM1定时1s自动触发ADC模块进行转换，ADC采样通道为PA00、PA01。 + ADC转换完成后，LED1的电平翻转，以0.5Hz的频率闪烁。可以通过PB05观察ADC的采样时刻 + + +使用说明： ++ EWARM + 1. 打开adc_sqr_ext_trig.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开adc_sqr_ext_trig.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/EWARM/project.ewp new file mode 100644 index 0000000..73e96c3 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/EWARM/project.ewp @@ -0,0 +1,2255 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_atim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/MDK/project.uvoptx new file mode 100644 index 0000000..0ef944d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/MDK/project.uvoptx @@ -0,0 +1,387 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + -UV0010M9E -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0Flashcw32l012_TEST.FLM -FS00 -FL010000 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\ATIM + 35905 + + + System Viewer\GPIOA + 35904 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_atim.c + cw32l012_atim.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 11 + 1 + 1 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/MDK/project.uvprojx new file mode 100644 index 0000000..1d444f1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/MDK/project.uvprojx @@ -0,0 +1,493 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_atim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_atim.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/USER/inc/main.h new file mode 100644 index 0000000..7c166af --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/USER/inc/main.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_atim.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_systick.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/USER/src/main.c new file mode 100644 index 0000000..0903499 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/USER/src/main.c @@ -0,0 +1,183 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void ATIM_Configuration(void); +void NVIC_Configuration(void); +void ATIM_IRQHandlerCallBack(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief ATIM边沿对齐模式，向上计数，PCLK作为时钟源 + * + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + Bsp_Init(8000000); + + InitTick(8000000); + + /* GPIO Configuration */ + GPIO_Configuration(); + + ATIM_Configuration(); + + while (1) + { + // 动态调整占空比 + ATIM_SetCompare1(250); + SysTickDelay(1000); // 1秒 + + ATIM_SetCompare1(500); + SysTickDelay(1000); // 1秒 + + ATIM_SetCompare1(750); + SysTickDelay(1000); // 1秒 + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); // 配置系统时钟为8MHz + SYSCTRL_PCLKPRS_Config(SYSCTRL_PCLK_DIV8); // PCLK= 8MHz/8 = 1MHz + __SYSCTRL_ATIM_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + PA05_AFx_ATIMCH1(); + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_5; + + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); +} + +void ATIM_Configuration(void) +{ + ATIM_InitTypeDef ATIM_InitStruct = {DISABLE, 0}; + ATIM_OCInitTypeDef ATIM_OCInitStruct; + + ATIM_InitStruct.BufferState = ENABLE; //使能缓存寄存器 + ATIM_InitStruct.CounterAlignedMode = ATIM_COUNT_ALIGN_MODE_EDGE; //边沿对齐 + ATIM_InitStruct.CounterDirection = ATIM_COUNTING_UP; //向上计数； + ATIM_InitStruct.CounterOPMode = ATIM_OP_MODE_REPETITIVE; //连续运行模式 + ATIM_InitStruct.Prescaler = 0; // 1分频 + ATIM_InitStruct.ReloadValue = 999; // 自动重载值999+1 ，1kHz PWM频率 + ATIM_InitStruct.RepetitionCounter = 0; // 重复周期0 + ATIM_Init(&ATIM_InitStruct); + + ATIM_OCInitStruct.BufferState = ENABLE; + ATIM_OCInitStruct.OCComplement = DISABLE; + ATIM_OCInitStruct.OCFastMode = ATIM_OC_FAST_MODE_DISABLE; + ATIM_OCInitStruct.OCInterruptState = DISABLE; + ATIM_OCInitStruct.OCMode = ATIM_OCMODE_PWM1; + ATIM_OCInitStruct.OCPolarity = ATIM_OCPOLARITY_NONINVERT; + ATIM_OC1Init(&ATIM_OCInitStruct); + + ATIM_SetCompare1(250); //初始占空比 25% + ATIM_CH1Config(ENABLE); + + ATIM_Cmd(ENABLE); + ATIM_CtrlPWMOutputs(ENABLE); + +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(ATIM_IRQn); + __enable_irq(); +} + +void ATIM_IRQHandlerCallBack(void) +{ + + +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/readme.txt new file mode 100644 index 0000000..ab78627 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_PWM_Signal_Generation/readme.txt @@ -0,0 +1,27 @@ +示例目的： + 生成基本的PWM信号，调整占空比和频率。 + +硬件资源： + 1. CW32L012 StartKit + 2. 系统时钟设置为HSI时钟 + 3. 定时器的时钟源设置为系统时钟（HSI）。 + 预分频器（PSC）设置为0，表示无预分频。 + 自动重载寄存器（ARR）设置为999，表示PWM信号的周期为1000个时钟周期，频率为1kHz。 + 4. PA05 作为ATIM的PWM输出 + + +演示说明： + 在示波器上观察生成的PWM信号，初始占空比为25%。 每隔1秒，占空比依次调整为25%、50%和75%，观察信号的变化。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/EWARM/project.ewp new file mode 100644 index 0000000..73e96c3 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/EWARM/project.ewp @@ -0,0 +1,2255 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_atim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/MDK/project.uvoptx new file mode 100644 index 0000000..12b919e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/MDK/project.uvoptx @@ -0,0 +1,387 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + -UV0010M9E -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0Flashcw32l012_TEST.FLM -FS00 -FL010000 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\ATIM + 35905 + + + System Viewer\GPIOA + 35904 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_atim.c + cw32l012_atim.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/MDK/project.uvprojx new file mode 100644 index 0000000..1d444f1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/MDK/project.uvprojx @@ -0,0 +1,493 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_atim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_atim.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/USER/inc/main.h new file mode 100644 index 0000000..7c166af --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/USER/inc/main.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_atim.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_systick.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..ea8c56f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + ATIM_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/USER/src/main.c new file mode 100644 index 0000000..b37e173 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/USER/src/main.c @@ -0,0 +1,159 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void ATIM_Configuration(void); +void NVIC_Configuration(void); +void ATIM_IRQHandlerCallBack(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief ATIM边沿对齐模式，向上计数，PCLK作为时钟源 + * + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + Bsp_Init(8000000); + Bsp_Led_On(&LED1); // 默认LED1灭 + + InitTick(8000000); + + ATIM_Configuration(); + NVIC_Configuration(); + + while (1) + { + //中断服务程序中翻转LED1的电平 + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); // 配置系统时钟为8MHz + SYSCTRL_PCLKPRS_Config(SYSCTRL_PCLK_DIV8); // PCLK= 8MHz/8 = 1MHz + __SYSCTRL_ATIM_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + +} + +void ATIM_Configuration(void) +{ + ATIM_InitTypeDef ATIM_InitStruct = {DISABLE, 0}; + + ATIM_InitStruct.BufferState = ENABLE; //使能缓存寄存器 + ATIM_InitStruct.CounterAlignedMode = ATIM_COUNT_ALIGN_MODE_EDGE; //边沿对齐 + ATIM_InitStruct.CounterDirection = ATIM_COUNTING_UP; //向上计数； + ATIM_InitStruct.CounterOPMode = ATIM_OP_MODE_REPETITIVE; //连续运行模式 + ATIM_InitStruct.Prescaler = 0; // 1分频 + ATIM_InitStruct.ReloadValue = 49999; // 自动重载值50000 ，20Hz PWM频率 + ATIM_InitStruct.RepetitionCounter = 0; // 重复周期0 + ATIM_Init(&ATIM_InitStruct); + + ATIM_ITConfig(ATIM_IT_UIE,ENABLE); + ATIM_UpdateEventSelect(ATIM_UPDATE_EVENT_NORMAL); + ATIM_Cmd(ENABLE); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(ATIM_IRQn); + __enable_irq(); +} + +void ATIM_IRQHandlerCallBack(void) +{ + if (CW_ATIM->ISR_f.UIF) + { + CW_ATIM->ICR_f.UIF = 0; + Bsp_Led_Tog(&LED1); + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/readme.txt new file mode 100644 index 0000000..6a28dff --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Basic_Timing/readme.txt @@ -0,0 +1,26 @@ +示例目的： + 演示ATIM作为基础定时器的使用方法。 + +硬件资源： + 1. CW32L012 StartKit + 2. 系统时钟设置为HSI时钟 + 3. 定时器的时钟源设置为系统时钟（HSI）。 + 预分频器（PSC）设置为0，表示无预分频。 + 自动重载寄存器（ARR）设置为49999，表示PWM信号的周期为50000个时钟周期，频率为20Hz。 + 4. LED1(PB09) + +演示说明： + LED1以10Hz的频率闪烁。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/EWARM/project.ewp new file mode 100644 index 0000000..c7d1a34 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_atim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/MDK/project.uvoptx new file mode 100644 index 0000000..90af5ed --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/MDK/project.uvoptx @@ -0,0 +1,375 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC2000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\ATIM + 35904 + + + System Viewer\SYSCTRL + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_atim.c + cw32l012_atim.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/MDK/project.uvprojx new file mode 100644 index 0000000..4ca732d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/MDK/project.uvprojx @@ -0,0 +1,488 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.2 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_atim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_atim.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/USER/inc/main.h new file mode 100644 index 0000000..a416427 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/USER/inc/main.h @@ -0,0 +1,68 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_atim.h" +#include "cw32l012_btim.h" +#include "cw32l012_flash.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_uart.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void GTIM1_IRQHandlerCallback(void); + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/USER/src/main.c new file mode 100644 index 0000000..32af109 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/USER/src/main.c @@ -0,0 +1,207 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void ATIM_IRQHandlerCallBack(void); +void ATIM_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +int32_t main(void) +{ + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + /* GPIO Configuration */ + GPIO_Configuration(); + + ATIM_Configuration(); + + /* NVIC Configuration */ + NVIC_Configuration(); + + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV1); + __SYSCTRL_ATIM_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOF_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + PA07_AFx_ATIMCH1N(); + PB00_AFx_ATIMCH2N(); + PB01_AFx_ATIMCH3N(); + PA02_AFx_ATIMCH4N(); + PF07_AFx_ATIMCH5N(); + + PB02_AFx_ATIMCH1(); + PB10_AFx_ATIMCH2(); + PB11_AFx_ATIMCH3(); + PA03_AFx_ATIMCH4(); + PF06_AFx_ATIMCH5(); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_7; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_10 | GPIO_PIN_11; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_6 | GPIO_PIN_7; + GPIO_Init(CW_GPIOF, &GPIO_InitStruct); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(ATIM_IRQn); + __enable_irq(); +} + + +void ATIM_Configuration(void) +{ + ATIM_InitTypeDef ATIM_InitStruct; + ATIM_OCInitTypeDef ATIM_OCInitStruct; + + // 对ATIM进行计数的基本设置 + ATIM_InitStruct.BufferState = DISABLE; //不启用ARR的缓存功能 + ATIM_InitStruct.CounterAlignedMode = ATIM_COUNT_ALIGN_MODE_CENTER_BOTH; // + ATIM_InitStruct.CounterDirection = ATIM_COUNTING_UP; + ATIM_InitStruct.CounterOPMode = ATIM_OP_MODE_REPETITIVE; + ATIM_InitStruct.Prescaler = 0; //1分频，计数时钟96MHz + ATIM_InitStruct.ReloadValue = 2400 - 1; // 单边溢出周期25us， 中心对齐共50us，PWM周期20kHz + ATIM_InitStruct.RepetitionCounter = 0; + ATIM_Init(&ATIM_InitStruct); + + ATIM_OCInitStruct.BufferState = DISABLE; + ATIM_OCInitStruct.OCComplement = ENABLE; + ATIM_OCInitStruct.OCFastMode = DISABLE; + ATIM_OCInitStruct.OCInterruptState = ENABLE; + ATIM_OCInitStruct.OCMode = ATIM_OCMODE_PWM1; + ATIM_OCInitStruct.OCPolarity = ATIM_OCPOLARITY_NONINVERT; + ATIM_OC1Init(&ATIM_OCInitStruct); + ATIM_OC2Init(&ATIM_OCInitStruct); + ATIM_OC3Init(&ATIM_OCInitStruct); + ATIM_OC4Init(&ATIM_OCInitStruct); + ATIM_OC5Init(&ATIM_OCInitStruct); + + ATIM_SetCompare1(ATIM_InitStruct.ReloadValue >> 3); + ATIM_SetCompare2(ATIM_InitStruct.ReloadValue >> 2); + ATIM_SetCompare3(3*ATIM_InitStruct.ReloadValue >> 3); + ATIM_SetCompare4(ATIM_InitStruct.ReloadValue >> 1); + ATIM_SetCompare5(5*ATIM_InitStruct.ReloadValue >> 3); + + ATIM_SetPWMDeadtime(20, 40, ENABLE); // 前死区为20个单位，后死区为40个单位，死区计算见用户手册 + ATIM_CH1Config(ENABLE); + ATIM_CH2Config(ENABLE); + ATIM_CH3Config(ENABLE); + ATIM_CH4Config(ENABLE); + ATIM_CH5Config(ENABLE); + + ATIM_CtrlPWMOutputs(ENABLE); + ATIM_Cmd(ENABLE); +} +void ATIM_IRQHandlerCallBack(void) +{ + + +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + (void)file; + (void)line; + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ +// printf("Wrong parameters value: file %s on line %d\r\n", file, line); + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/readme.txt new file mode 100644 index 0000000..69c4940 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Complementary_PWM_with_Dead-Time_Control/readme.txt @@ -0,0 +1,31 @@ +示例目的： + 演示ATIM的PWM互补输出功能 + +硬件资源： + 1. CW32L012 StartKit + 2. 系统时钟设置为HSI时钟1分频，96MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=96MHz + 3. ATIM中心对齐模式计数，计数时钟96MHz,ARR设置为2399，单边溢出周期25us， + 中心对齐共50us，PWM周期20kHz, 输出比较, 使用ATIM的CH1和CH1N, + CH2和CH2N，CH3和CH3N， CH4和CH4N，CH5和CH5N通道输出互补的PWM信号 + + +演示说明: + PB02：CH1 和 PA07：CH1N + PB10：CH2 和 PB00：CH2N + PB11：CH3 和 PB01：CH3N + PA03：CH4 和 PA02：CH4N + PF06：CH5 和 PF07：CH5N 互为互补输出，占空比分别为12.5%， 25%， 37.5%，50%，62.5% + 并插入不对称的死区时间。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/EWARM/project.ewp new file mode 100644 index 0000000..73e96c3 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/EWARM/project.ewp @@ -0,0 +1,2255 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_atim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/MDK/project.uvoptx new file mode 100644 index 0000000..bdeb53a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/MDK/project.uvoptx @@ -0,0 +1,387 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + -UV0010M9E -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0Flashcw32l012_TEST.FLM -FS00 -FL010000 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\ATIM + 35905 + + + System Viewer\GPIOB + 35904 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_atim.c + cw32l012_atim.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/MDK/project.uvprojx new file mode 100644 index 0000000..1d444f1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/MDK/project.uvprojx @@ -0,0 +1,493 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_atim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_atim.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/USER/inc/main.h new file mode 100644 index 0000000..7c166af --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/USER/inc/main.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_atim.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_systick.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..ea8c56f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + ATIM_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/USER/src/main.c new file mode 100644 index 0000000..06df846 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/USER/src/main.c @@ -0,0 +1,178 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void ATIM_Configuration(void); +void NVIC_Configuration(void); +void ATIM_IRQHandlerCallBack(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief ATIM边沿对齐模式，向上计数，ATIMETR作为时钟源 + * + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + Bsp_Init(8000000); + Bsp_Led_On(&LED1); // 默认LED1灭 + + InitTick(8000000); + + GPIO_Configuration(); + + ATIM_Configuration(); + NVIC_Configuration(); + + while (1) + { + //中断服务程序中翻转LED1的电平 + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); // 配置系统时钟为8MHz + SYSCTRL_PCLKPRS_Config(SYSCTRL_PCLK_DIV8); // PCLK= 8MHz/8 = 1MHz + __SYSCTRL_ATIM_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + GPIO_InitStruct.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_InitStruct.Pins = GPIO_PIN_0; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + + PB00_AFx_ATIMETR(); //PB00复用为ATIMETR +} + +void ATIM_Configuration(void) +{ + ATIM_InitTypeDef ATIM_InitStruct = {DISABLE, 0}; + ATIM_ETRInitTypeDef ATIM_ETRInitStruct; + + ATIM_InitStruct.BufferState = ENABLE; //使能缓存寄存器 + ATIM_InitStruct.CounterAlignedMode = ATIM_COUNT_ALIGN_MODE_EDGE; //边沿对齐 + ATIM_InitStruct.CounterDirection = ATIM_COUNTING_UP; //向上计数； + ATIM_InitStruct.CounterOPMode = ATIM_OP_MODE_REPETITIVE; //连续运行模式 + ATIM_InitStruct.Prescaler = 0; // 1分频 + ATIM_InitStruct.ReloadValue = 9; // 自动重载值10 + ATIM_InitStruct.RepetitionCounter = 0; // 重复周期0 + ATIM_Init(&ATIM_InitStruct); + + ATIM_ETRInitStruct.Source = ATIM_ETRSOURCE_ETR_PIN; + ATIM_ETRInitStruct.Polarity = ATIM_ETR_POLARITY_NEGATIVE; + ATIM_ETRInitStruct.Prescaler = ATIM_ETR_PRESCALE_NONE; + ATIM_ETRInitStruct.Filter = ATIM_ETR_FILTER_DIV32_N8; + ATIM_ETRInit(&ATIM_ETRInitStruct); + + ATIM_SetFilterClockDiv(FILTER_CLOCK_DIV4); + ATIM_EnableExternalClock(ENABLE); + + + ATIM_ITConfig(ATIM_IT_UIE,ENABLE); + ATIM_UpdateEventSelect(ATIM_UPDATE_EVENT_NORMAL); + ATIM_Cmd(ENABLE); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(ATIM_IRQn); + __enable_irq(); +} + +void ATIM_IRQHandlerCallBack(void) +{ + if (CW_ATIM->ISR_f.UIF) + { + CW_ATIM->ICR_f.UIF = 0; + Bsp_Led_Tog(&LED1); + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/readme.txt new file mode 100644 index 0000000..08ca473 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_External_Clock_Mode/readme.txt @@ -0,0 +1,30 @@ +示例目的： + 通过配置 ATIM 的外部时钟模式2，使用外部信号作为计数器时钟源。 + +硬件资源： + 1. CW32L012 StartKit + 2. 系统时钟设置为HSI时钟 + 3. 定时器的时钟源设置为外部时钟模式。 + 预分频器（PSC）设置为0，表示无预分频。 + 自动重载寄存器（ARR）设置为9。 + 4. ATIM的ETR引脚（PB00） + 5. LED1 + +演示说明： + 外部信号通过ETR引脚输入到ATIM模块，通过配置ATIM的外部时钟模式2，使用外部信号作为计数器时钟源。 + 外部信号的上升沿触发计数器计数。计数器从0计数到自动重载值（9）时，会产生更新事件。 + 更新事件触发中断，在中断服务程序中，将LED1的状态取反，然后清除中断标志位。 + + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/EWARM/project.ewp new file mode 100644 index 0000000..73e96c3 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/EWARM/project.ewp @@ -0,0 +1,2255 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_atim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/MDK/project.uvoptx new file mode 100644 index 0000000..0ef944d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/MDK/project.uvoptx @@ -0,0 +1,387 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + -UV0010M9E -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0Flashcw32l012_TEST.FLM -FS00 -FL010000 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\ATIM + 35905 + + + System Viewer\GPIOA + 35904 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_atim.c + cw32l012_atim.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 11 + 1 + 1 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/MDK/project.uvprojx new file mode 100644 index 0000000..1d444f1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/MDK/project.uvprojx @@ -0,0 +1,493 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_atim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_atim.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/USER/inc/main.h new file mode 100644 index 0000000..7c166af --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/USER/inc/main.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_atim.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_systick.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..ea8c56f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + ATIM_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/USER/src/main.c new file mode 100644 index 0000000..110d923 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/USER/src/main.c @@ -0,0 +1,210 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void ATIM_Configuration(void); +void NVIC_Configuration(void); +void ATIM_IRQHandlerCallBack(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint16_t Period, PulseWidth; +uint8_t CompeletFlag = 0; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief ATIM边沿对齐模式，向上计数，PCLK作为时钟源 + * + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + Bsp_Init(96000000); + + InitTick(96000000); + + /* GPIO Configuration */ + GPIO_Configuration(); + + ATIM_Configuration(); + NVIC_Configuration(); + + while (1) + { + if (CompeletFlag) + { + CompeletFlag = 0; + printf("The captured waveform period is %fus, and the pulse width is %fus\r\n", Period/96.0, PulseWidth/96.0); + } + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI96MHZ); // 配置系统时钟为96MHz + SYSCTRL_PCLKPRS_Config(SYSCTRL_PCLK_DIV1); // PCLK= 96MHz/1 = 96MHz + __SYSCTRL_ATIM_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + PA05_AFx_ATIMCH1(); + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_5; + + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); +} + +void ATIM_Configuration(void) +{ + ATIM_InitTypeDef ATIM_InitStruct = {DISABLE, 0}; + ATIM_ICInitTypeDef ATIM_ICInitStruct; + + ATIM_InitStruct.BufferState = ENABLE; //使能缓存寄存器 + ATIM_InitStruct.CounterAlignedMode = ATIM_COUNT_ALIGN_MODE_EDGE; //边沿对齐 + ATIM_InitStruct.CounterDirection = ATIM_COUNTING_UP; //向上计数； + ATIM_InitStruct.CounterOPMode = ATIM_OP_MODE_REPETITIVE; //连续运行模式 + ATIM_InitStruct.Prescaler = 0; // 1分频 + ATIM_InitStruct.ReloadValue = 0xFFFF; // 自动重载值最大 + ATIM_InitStruct.RepetitionCounter = 0; // 重复周期0 + ATIM_Init(&ATIM_InitStruct); + + ATIM_ICInitStruct.ICFilter = ATIM_ICFILTER_FCLKDIV32_N8; + ATIM_ICInitStruct.ICMap = ATIM_IC_MAP_DIRECT; // 直连到IC1 + ATIM_ICInitStruct.ICPolarity = ATIM_ICPOLOARITY_FALLING; // 捕获下降沿，用于获取周期 + ATIM_ICInitStruct.ICPrescaler = ATIM_ICPRESCALER_DIV1; + ATIM_IC1Init(&ATIM_ICInitStruct); + + ATIM_ICInitStruct.ICFilter = ATIM_ICFILTER_FCLKDIV32_N8; + ATIM_ICInitStruct.ICMap = ATIM_IC_MAP_CROSS; // 交叉连接到IC2 + ATIM_ICInitStruct.ICPolarity = ATIM_ICPOLOARITY_RISING; // 捕获上升沿，用于捕获脉宽的结束 + ATIM_ICInitStruct.ICPrescaler = ATIM_ICPRESCALER_DIV1; + ATIM_IC2Init(&ATIM_ICInitStruct); + + ATIM_SetFilterClockDiv(FILTER_CLOCK_DIV1); + + ATIM_CH1Config(ENABLE); + ATIM_CH2Config(ENABLE); + + ATIM_ITConfig(ATIM_IT_CC1IE|ATIM_IT_CC2IE, ENABLE); + + ATIM_Cmd(ENABLE); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(ATIM_IRQn); + __enable_irq(); +} + +void ATIM_IRQHandlerCallBack(void) +{ + static uint8_t step = 0; + + if (CW_ATIM->ISR_f.CC1IF) + { + CW_ATIM->ICR_f.CC1IF = 0; + if (step == 0) + { + step = 1; + Period = CW_ATIM->CCR1; + } + else if (step == 1) + { + step = 0; + CompeletFlag = 1; + Period = CW_ATIM->CCR1 - Period; + } + } + if (CW_ATIM->ISR_f.CC2IF) + { + CW_ATIM->ICR_f.CC2IF = 0; + if (step == 1) + { + PulseWidth = CW_ATIM->CCR2 - Period; + } + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/readme.txt new file mode 100644 index 0000000..53c8241 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/ATIM/ATIM_Input_Capture_with_Digital_Filtering/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 展示如何使用ATIM的输入捕获功能来测量外部信号的周期和脉冲宽度。 + +硬件资源： + 1. CW32L012 StartKit + 2. 系统时钟设置为HSI时钟 + 3. 定时器的时钟源设置为系统时钟（HSI）。 + 预分频器（PSC）设置为0，表示无预分频。 + 自动重载寄存器（ARR）设置为0xFFFF， + 4. PA05 作为ATIM的捕获输入 + + +演示说明： + 将外部信号连接到 ATIM 的输入捕获通道，配置捕获模式和滤波参数，当外部信号的边沿触发捕获时， + 读取计数器的值并记录到捕获比较寄存器中，通过计算两个捕获值之间的差值得到信号的周期或脉冲宽度，进而计算出信号的频率。 + + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/EWARM/project.ewp new file mode 100644 index 0000000..b798071 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_btim.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/MDK/project.uvoptx new file mode 100644 index 0000000..f603c6c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/MDK/project.uvoptx @@ -0,0 +1,376 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + + + 0 + 0 + 77 + 1 +
2094
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\project\../USER/src/main.c\77 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\BTIM1 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_btim.c + cw32l012_btim.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/MDK/project.uvprojx new file mode 100644 index 0000000..0024f71 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/MDK/project.uvprojx @@ -0,0 +1,474 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.2 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_btim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_btim.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/USER/inc/main.h new file mode 100644 index 0000000..873ea7c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_btim.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..5637ad5 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/USER/src/interrupts_cw32l012.c @@ -0,0 +1,438 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + BTIM1_IRQHandlerCallBack(); + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/USER/src/main.c new file mode 100644 index 0000000..b706404 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/USER/src/main.c @@ -0,0 +1,153 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void BTIM_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + /* BSP Configuration */ + Bsp_Init(4000000); + + /* BTIM Configuration */ + BTIM_Configuration(); + + /* NVIC Configuration */ + NVIC_Configuration(); + + while (1) + { + /* 中断服务程序 */ + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + __SYSCTRL_BTIM123_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void BTIM_Configuration(void) +{ + BTIM_TimeBaseInitTypeDef BTIM_TimeBaseInitStruct = {0}; + + BTIM_TimeBaseInitStruct.BTIM_Mode = BTIM_MODE_TIMER; + BTIM_TimeBaseInitStruct.BTIM_Period = 49999; // 50ms/1MHz - 1=50000 - 1 + BTIM_TimeBaseInitStruct.BTIM_Prescaler = 3; // 3+1=4分频 + + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_TimeBaseInitStruct); + BTIM_ITConfig(CW_BTIM1, BTIM_IT_UPDATE, ENABLE); + BTIM_Cmd(CW_BTIM1, ENABLE); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(BTIM1_IRQn); + __enable_irq(); +} + +void BTIM1_IRQHandlerCallBack(void) +{ + if (BTIM_GetITStatus(CW_BTIM1, BTIM_IT_UPDATE)) + { + BTIM_ClearITPendingBit(CW_BTIM1, BTIM_IT_UPDATE); + Bsp_Led_Tog(&LED1); + } +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/readme.txt new file mode 100644 index 0000000..7c91934 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer/readme.txt @@ -0,0 +1,26 @@ +示例目的： + 控制基本定时器BTIM1以固定的时间间隔产生中断，并在中断控制口线电平翻转 + +硬件资源： + 1. CW32L012 StarKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟默认分频，4MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + 4. BTIM1的时钟设置为PCLK，4分频 + 5. LED1 + +演示说明： + BTIM1以1MHz时钟进行计数，ARR寄存器为49999，则BTIM1将每50ms溢出一次，并触发中断 + 中断服务程序中，LED1以10Hz的频率闪烁 + +使用说明 ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/EWARM/project.ewp new file mode 100644 index 0000000..b798071 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_btim.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/MDK/project.uvoptx new file mode 100644 index 0000000..ae09f29 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/MDK/project.uvoptx @@ -0,0 +1,353 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FN1 -FC1000 -FD20000000 -FF0FlashCW32L012_TEST -FL010000 -FS00 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_btim.c + cw32l012_btim.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/MDK/project.uvprojx new file mode 100644 index 0000000..d05058b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/MDK/project.uvprojx @@ -0,0 +1,473 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 5 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_btim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_btim.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/USER/inc/main.h new file mode 100644 index 0000000..ead0aad --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_btim.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..804ce48 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + BTIM1_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/USER/src/main.c new file mode 100644 index 0000000..19f830a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/USER/src/main.c @@ -0,0 +1,169 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void BTIM_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + Bsp_Init(48000000); + + /* GPIO Configuration */ + GPIO_Configuration(); + + BTIM_Configuration(); + + /* NVIC Configuration */ + NVIC_Configuration(); + + while (1) + { + /* 中断服务程序 */ + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI48MHZ); + __SYSCTRL_BTIM123_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + // PA06: BTIM1_ETR + PA06_AFx_BTIM1ETR(); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_6; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); +} + +void BTIM_Configuration(void) +{ + BTIM_TimeBaseInitTypeDef BTIM_TimeBaseInitStruct = {0}; + + BTIM_TimeBaseInitStruct.BTIM_Mode = BTIM_MODE_TRIGGER; + BTIM_TimeBaseInitStruct.BTIM_Period = 49999; + BTIM_TimeBaseInitStruct.BTIM_Prescaler = 48 - 1; + + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_TimeBaseInitStruct); + BTIM_ITConfig(CW_BTIM1, BTIM_IT_UPDATE, ENABLE); + BTIM_TriggerInputConfig(CW_BTIM1, BTIM_TS_BTIMx_ETR, BTIM_TRIGGER_POLARITY_NEGATIVE); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(BTIM1_IRQn); + __enable_irq(); +} + +void BTIM1_IRQHandlerCallBack(void) +{ + if (BTIM_GetITStatus(CW_BTIM1, BTIM_IT_UPDATE)) + { + BTIM_ClearITPendingBit(CW_BTIM1, BTIM_IT_UPDATE); + Bsp_Led_Tog(&LED1); + } +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/readme.txt new file mode 100644 index 0000000..709e6c3 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_ETR/readme.txt @@ -0,0 +1,28 @@ +示例目的： + 演示BTIM1的触发功能。 + +硬件资源： + 1. CW32L012 StarKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟2分频，48MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=48MHz + 4. BTIM1的时钟设置为PCLK，48分频 + 5. LED2 + 6. 按键KEY1 + 7. PA06复用为BTIM1的ETR引脚 + +演示说明： + 将KEY1和BTIM1的ETR引脚用条线连接，按下KEY1后，触发BTIM1以1MHz时钟进行计数，ARR寄存器为49999， + 则BTIM1将每50ms溢出一次，并触发中断。中断服务程序中，LED1以10Hz的频率闪烁 + +使用说明 ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/EWARM/project.ewp new file mode 100644 index 0000000..b798071 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_btim.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/MDK/project.uvoptx new file mode 100644 index 0000000..6733d76 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/MDK/project.uvoptx @@ -0,0 +1,363 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\BTIM1 + 35905 + + + System Viewer\SYSCTRL + 35904 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 1 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_btim.c + cw32l012_btim.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/MDK/project.uvprojx new file mode 100644 index 0000000..0b7b2ea --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/MDK/project.uvprojx @@ -0,0 +1,494 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 3 + 5 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_btim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_btim.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\Device\CW32L012F8\startup_CW32l012.s + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/USER/inc/main.h new file mode 100644 index 0000000..ead0aad --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_btim.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/USER/src/main.c new file mode 100644 index 0000000..9fd66bb --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/USER/src/main.c @@ -0,0 +1,163 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void BTIM_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + /* NVIC Configuration */ + NVIC_Configuration(); + + /* GPIO Configuration */ + GPIO_Configuration(); + + /* BTIM Configuration */ + BTIM_Configuration(); + + while (1) + { + + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI3MHZ); + SYSCTRL_PCLK_OUT(); + __SYSCTRL_BTIM123_CLK_ENABLE(); + __SYSCTRL_GPIOA_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + PA09_AFx_BTIM1TOGN(); + PA10_AFx_BTIM1TOGP(); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_9 | GPIO_PIN_10; + + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); +} + +void BTIM_Configuration(void) +{ + BTIM_TimeBaseInitTypeDef BTIM_TimeBaseInitStruct = {0}; + + BTIM_TimeBaseInitStruct.BTIM_Mode = BTIM_MODE_TRIGGER; + BTIM_TimeBaseInitStruct.BTIM_Period = 0; + BTIM_TimeBaseInitStruct.BTIM_Prescaler = 0; + + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_TimeBaseInitStruct); + + BTIM_OutputToggleCmd(CW_BTIM1, ENABLE); + + BTIM_Cmd(CW_BTIM1, ENABLE); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(BTIM1_IRQn); + __enable_irq(); +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/readme.txt new file mode 100644 index 0000000..433edc5 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/BTIM/BaseTimer_TOG/readme.txt @@ -0,0 +1,26 @@ +示例目的： + BTIM的引脚翻转功能 + +硬件资源： + 1. CW32L012 StarKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟32分频，3MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=3MHz + 4. BTIM1的时钟设置为PCLK，1分频，ARR设置为0. + 5. BTIM1的TOGP（PA10）和TOGN（PA09）引脚 + 6. PCLKOUT引脚（PA03） + +演示说明： + BTIM1以3MHz时钟频率计数，ARR设置为0，BTIM1的TOG引脚每周期翻转一次。可观测PCLKOUT引脚，BTIM1的TOGP和TOGN引脚上的波形。 + +使用说明 ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/EWARM/project.ewp new file mode 100644 index 0000000..71547ae --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_cordic.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/MDK/project.uvoptx new file mode 100644 index 0000000..66286ba --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/MDK/project.uvoptx @@ -0,0 +1,367 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + DLGUARM + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + + 1 + 8 + RamBuf + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\CORDIC + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 1 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_cordic.c + cw32l012_cordic.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/MDK/project.uvprojx new file mode 100644 index 0000000..027dc53 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/MDK/project.uvprojx @@ -0,0 +1,474 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_cordic.c + 1 + ..\..\..\..\Libraries\src\cw32l012_cordic.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/USER/inc/main.h new file mode 100644 index 0000000..185bfaf --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/USER/src/main.c new file mode 100644 index 0000000..ac416c5 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/USER/src/main.c @@ -0,0 +1,111 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "cw32l012_cordic.h" +#include "cw32l012_sysctrl.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +char RamBuf[100] __attribute__((at(0x20000200))); +int main() +{ + cordic_init_t init = { + .func = CORDIC_FUNC_ATAN2, // 选择相位角函数 + .scale = 0, + .format = CORDIC_FORMAT_Q1_15, + .iter = CORDIC_ITER_32, + .comp = 1, + .ie = 0, + .dmaeoc = 0, + .dmaidle = 0 + }; + + CORDIC_Init(&init); + + // 输入X和Y值 + int32_t x = float_to_q1_15(0.375); // Q1.15 :0x3000 + int32_t y = float_to_q1_15(0.125); // Q1.15 :0x1000 + CW_CORDIC->X = x; // 写入X寄存器 + CW_CORDIC->Y = y; // 写入Y寄存器启动运算 + + while (!CORDIC_GetStatus().eoc); + + int32_t result = CW_CORDIC->Z; // 相位角结果在Z寄存器 + sprintf(RamBuf, "atan2(0.125, 0.375) = %d (q1.15 format, in units of pi)\n", result&0xFFFF); + sprintf(&RamBuf[59], "atan2(0.125, 0.375) = %f(in units of pi) \n", q1_15_to_float(result&0xFFFF)); + while(1); +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/readme.txt new file mode 100644 index 0000000..da01c40 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_atan2/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 演示CORDIC的硬件算法相位角atan2。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟默认24分频，4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + +演示说明： + 计算结果将在RAM（0x20000200）中显示，设置为Ascii可查看 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/EWARM/project.ewp new file mode 100644 index 0000000..71547ae --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_cordic.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/MDK/project.uvoptx new file mode 100644 index 0000000..2413c40 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/MDK/project.uvoptx @@ -0,0 +1,378 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + DLGUARM + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + 0 + 0 + 82 + 1 +
5114
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\project\../USER/src/main.c\82 + + + + + 1 + 8 + RamBuf + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 1 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_cordic.c + cw32l012_cordic.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/MDK/project.uvprojx new file mode 100644 index 0000000..027dc53 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/MDK/project.uvprojx @@ -0,0 +1,474 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_cordic.c + 1 + ..\..\..\..\Libraries\src\cw32l012_cordic.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/USER/inc/main.h new file mode 100644 index 0000000..185bfaf --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/USER/src/main.c new file mode 100644 index 0000000..eeff0a0 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/USER/src/main.c @@ -0,0 +1,114 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "cw32l012_cordic.h" +#include "cw32l012_sysctrl.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +char RamBuf[100] __attribute__((at(0x20000200))); +int main() +{ + cordic_init_t init = { + .func = CORDIC_FUNC_COS, // 选择余弦函数 + .scale = 0, // 不使用扩展范围 + .format = CORDIC_FORMAT_Q1_15, // 使用q1.15格式 + .iter = CORDIC_ITER_20, // 迭代次数 + .comp = 1, // 硬件补偿伸缩因子 + .ie = 0, // 禁用中断 + .dmaeoc = 0, // 禁用DMA + .dmaidle = 0 // 禁用DMA空闲 + }; + + memset(RamBuf, 0, 100); + + // 初始化CORDIC模块 + CORDIC_Init(&init); + + // 输入角度（以pi为单位，q1.15格式） + int32_t angle = float_to_q1_15(0.25); // 0.25 Q1.15: 0x2000, 即：PI/4 + CW_CORDIC->Z = angle; // 写入Z寄存器启动运算 + + // 等待运算完成 + while (!CORDIC_GetStatus().eoc); //运算完成标志硬件置1，读取运算结果硬件清0 + + // 读取结果 + int32_t result = CW_CORDIC->X; // 余弦结果在X寄存器 + sprintf(RamBuf, "cos(0.25 * pi) = %d (q1.15 format)\n", result&0xFFFF); // 在RamBuf中看结果q1.15格式 + sprintf(&RamBuf[59], "cos(0.25 * pi) = %f\n", q1_15_to_float(result&0xFFFF)); // 在RamBuf中看结果 + while(1); +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/readme.txt new file mode 100644 index 0000000..552b99b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_cos/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 演示CORDIC的硬件算法余弦cos。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟默认24分频，4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + +演示说明： + 计算结果将在RAM（0x20000200）中显示，设置为Ascii可查看 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/EWARM/project.ewp new file mode 100644 index 0000000..71547ae --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_cordic.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/MDK/project.uvoptx new file mode 100644 index 0000000..23cda6d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/MDK/project.uvoptx @@ -0,0 +1,378 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + DLGUARM + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + 0 + 0 + 82 + 1 +
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+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\project\../USER/src/main.c\82 + + + + + 1 + 8 + RamBuf + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 1 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_cordic.c + cw32l012_cordic.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/MDK/project.uvprojx new file mode 100644 index 0000000..027dc53 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/MDK/project.uvprojx @@ -0,0 +1,474 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_cordic.c + 1 + ..\..\..\..\Libraries\src\cw32l012_cordic.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/USER/inc/main.h new file mode 100644 index 0000000..185bfaf --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/USER/src/main.c new file mode 100644 index 0000000..cb4e303 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/USER/src/main.c @@ -0,0 +1,112 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "cw32l012_cordic.h" +#include "cw32l012_sysctrl.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +char RamBuf[100] __attribute__((at(0x20000200))); +int main() +{ + cordic_init_t init = { + .func = CORDIC_FUNC_LN, // 选择自然对数函数 + .scale = 1, + .format = CORDIC_FORMAT_Q1_31, + .iter = CORDIC_ITER_32, + .comp = 1, + .ie = 0, + .dmaeoc = 0, + .dmaidle = 0 + }; + + memset(RamBuf, 0, 100); + + // 初始化CORDIC模块 + CORDIC_Init(&init); + + // 输入X值（q1.31格式） + int32_t x = float_to_q1_31(0.4); // 0.4 = q1.31：0x33333340 + CW_CORDIC->X = x; // 写入X寄存器启动运算 + + while (!CORDIC_GetStatus().eoc); + + int32_t result = CW_CORDIC->Z; // 自然对数结果在Z寄存器 + sprintf(RamBuf,"ln(0.4*2)/4 = %d (q1.31 format)\n", result); // 在RamBuf中看结果q1.31格式 + sprintf(&RamBuf[59],"ln(0.4*2)/4 = %f", q1_31_to_float(result)); + while(1); +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/readme.txt new file mode 100644 index 0000000..75f5813 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_ln/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 演示CORDIC的硬件算法自然对数ln。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟默认24分频，4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + +演示说明： + 计算结果将在RAM（0x20000200）中显示，设置为Ascii可查看 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/EWARM/project.ewp new file mode 100644 index 0000000..71547ae --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_cordic.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/MDK/project.uvoptx new file mode 100644 index 0000000..9f98a70 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/MDK/project.uvoptx @@ -0,0 +1,378 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + 0 + 0 + 82 + 1 +
4928
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\project\../USER/src/main.c\82 + + + + + 1 + 8 + RamBuf + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 1 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_cordic.c + cw32l012_cordic.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/MDK/project.uvprojx new file mode 100644 index 0000000..027dc53 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/MDK/project.uvprojx @@ -0,0 +1,474 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_cordic.c + 1 + ..\..\..\..\Libraries\src\cw32l012_cordic.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/USER/inc/main.h new file mode 100644 index 0000000..185bfaf --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/USER/src/main.c new file mode 100644 index 0000000..3928a92 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/USER/src/main.c @@ -0,0 +1,112 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "cw32l012_cordic.h" +#include "cw32l012_sysctrl.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +char RamBuf[100] __attribute__((at(0x20000200))); +int main() +{ + cordic_init_t init = { + .func = CORDIC_FUNC_SINH, // 选择双曲正弦函数 + .scale = 0, + .format = CORDIC_FORMAT_Q1_31, + .iter = CORDIC_ITER_32, + .comp = 1, + .ie = 0, + .dmaeoc = 0, + .dmaidle = 0 + }; + + memset(RamBuf, 0, 100); + + // 初始化CORDIC模块 + CORDIC_Init(&init); + + // 输入Z值（q1.31格式） + int32_t z = float_to_q1_31(0.2); // 0.2 = Q1.31：0x199999A0 + CW_CORDIC->Z = z; // 写入Z寄存器启动运算 + + while (!CORDIC_GetStatus().eoc); + + int32_t result = CW_CORDIC->Y; // 双曲正弦结果在Y寄存器 + sprintf(RamBuf,"sinh(0.2*2)/2 = %d (q1.31 format)\n", result); // 在RamBuf中看结果q1.31格式 + sprintf(&RamBuf[47],"sinh(0.2*2)/2 = %f\n", q1_31_to_float(result)); + while(1); +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/readme.txt new file mode 100644 index 0000000..cbd6b4f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sinh/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 演示CORDIC的硬件算法双曲正弦sinh。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟默认24分频，4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + +演示说明： + 计算结果将在RAM（0x20000200）中显示，设置为Ascii可查看 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/EWARM/project.ewp new file mode 100644 index 0000000..71547ae --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_cordic.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/MDK/project.uvoptx new file mode 100644 index 0000000..9f6d981 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/MDK/project.uvoptx @@ -0,0 +1,378 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + DLGUARM + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + 0 + 0 + 82 + 1 +
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+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\project\../USER/src/main.c\82 + + + + + 1 + 8 + RamBuf + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 1 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_cordic.c + cw32l012_cordic.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/MDK/project.uvprojx new file mode 100644 index 0000000..027dc53 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/MDK/project.uvprojx @@ -0,0 +1,474 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_cordic.c + 1 + ..\..\..\..\Libraries\src\cw32l012_cordic.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/USER/inc/main.h new file mode 100644 index 0000000..185bfaf --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/USER/src/main.c new file mode 100644 index 0000000..0d2a0ce --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/USER/src/main.c @@ -0,0 +1,112 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "cw32l012_cordic.h" +#include "cw32l012_sysctrl.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +char RamBuf[100] __attribute__((at(0x20000200))); +int main() +{ + cordic_init_t init = { + .func = CORDIC_FUNC_SQRT, // 选择平方根函数 + .scale = 0, + .format = CORDIC_FORMAT_Q1_31, + .iter = CORDIC_ITER_32, + .comp = 1, + .ie = 0, + .dmaeoc = 0, + .dmaidle = 0 + }; + + memset(RamBuf, 0, 100); + + // 初始化CORDIC模块 + CORDIC_Init(&init); + + // 输入X值（q1.31格式） + int32_t x = float_to_q1_31(0.4); // 0.4 + CW_CORDIC->X = x; // 写入X寄存器启动运算 + + while (!CORDIC_GetStatus().eoc); + + int32_t result = CW_CORDIC->X; // 平方根结果在X寄存器 + sprintf(RamBuf,"sqrt(0.4) = %d (q1.31 format)\n", result); // 在RamBuf中看结果q1.31格式 + sprintf(&RamBuf[47],"sqrt(0.4) = %f \n", q1_31_to_float(result)); // 在RamBuf中看结果float格式 + while(1); +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/readme.txt new file mode 100644 index 0000000..648ede0 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CORDIC/cordic_sqrt/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 演示CORDIC的硬件算法平方根sqrt。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟默认24分频，4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + +演示说明： + 计算结果将在RAM（0x20000200）中显示，设置为Ascii可查看 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/EWARM/project.ewp new file mode 100644 index 0000000..3837422 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_crc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/MDK/crc_calc.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/MDK/crc_calc.uvoptx new file mode 100644 index 0000000..185b0d8 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/MDK/crc_calc.uvoptx @@ -0,0 +1,353 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + DLGUARM + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_crc.c + cw32l012_crc.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/MDK/crc_calc.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/MDK/crc_calc.uvprojx new file mode 100644 index 0000000..8d71362 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/MDK/crc_calc.uvprojx @@ -0,0 +1,474 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_crc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_crc.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/USER/inc/main.h new file mode 100644 index 0000000..185bfaf --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/USER/inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/USER/src/main.c new file mode 100644 index 0000000..5a95097 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/USER/src/main.c @@ -0,0 +1,162 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "cw32l012_crc.h" +#include "cw32l012_sysctrl.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** 计算CRC16 / CRC32 + ** + ******************************************************************************/ + +//========================================================================= + +uint32_t tmp1; + +//========================================================================= + +int32_t main(void) +{ + uint8_t Raw08[8] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77 }; + //========================================================================= + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + //enable CRC CLK + __SYSCTRL_CRC_CLK_ENABLE(); + //========================================================================= + //CRC16_IBM + tmp1 = CRC16_Calc_8bit(CRC16_IBM, Raw08, 8); //按Byte计算CRC16 计算结果0xE16C + __asm("BKPT 0"); //请在此出观察tmp1的值 + + + + //========================================================================= + //CRC16_MAXIM + tmp1 = CRC16_Calc_8bit(CRC16_MAXIM, Raw08, 8); //按Byte计算CRC16 计算结果0x1E93 + __asm("BKPT 0"); //请在此出观察tmp1的值 + + + //========================================================================= + //CRC16_USB + tmp1 = CRC16_Calc_8bit(CRC16_USB, Raw08, 8); //按Byte计算CRC16 计算结果0x15D3 + __asm("BKPT 0"); //请在此出观察tmp1的值 + + + //========================================================================= + //CRC16_MODBUS + tmp1 = CRC16_Calc_8bit(CRC16_MODBUS, Raw08, 8); //按Byte计算CRC1 计算结果0xEA2C + __asm("BKPT 0"); //请在此出观察tmp1的值 + + + //========================================================================= + //CRC16_CCITT + tmp1 = CRC16_Calc_8bit(CRC16_CCITT, Raw08, 8); //按Byte计算CRC16 计算结果0x868F + __asm("BKPT 0"); //请在此出观察tmp1的值 + + + //========================================================================= + //CRC16_CCITTFALSE + tmp1 = CRC16_Calc_8bit(CRC16_CCITTFALSE, Raw08, 8); //按Byte计算CRC16 计算结果0x5CFF + __asm("BKPT 0"); //请在此出观察tmp1的值 + + + //========================================================================= + //CRC16_X25 + tmp1 = CRC16_Calc_8bit(CRC16_X25, Raw08, 8); //按Byte计算CRC16 计算结果0x05FC + __asm("BKPT 0"); //请在此出观察tmp1的值 + + + //========================================================================= + //CRC16_XMODEM + tmp1 = CRC16_Calc_8bit(CRC16_XMODEM, Raw08, 8); //按Byte计算CRC16 计算结果0x6DC1 + __asm("BKPT 0"); //请在此出观察tmp1的值 + + + while (1) + { + ; + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/readme.txt new file mode 100644 index 0000000..a2612ca --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/CRC/crc_calc/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 测试8种不同CRC算法在8bit输入位宽方式下的计算结果。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟12分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + +演示说明： + 通过调试工具，结合软件断点，依次观察8种不同算法模式的结果。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/EWARM/project.ewp new file mode 100644 index 0000000..6895d86 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/EWARM/project.ewp @@ -0,0 +1,2243 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts.c + + + + Bsp + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_dac.c + + + + Doc + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/MDK/project.uvoptx new file mode 100644 index 0000000..53d31c7 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/MDK/project.uvoptx @@ -0,0 +1,352 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + DLGUARM + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + 0 + 0 + 88 + 1 +
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+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\project\../USER/src/main.c\88 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\DAC + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts.c + interrupts.c + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + + + Driver + 1 + 0 + 0 + 0 + + 4 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 4 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 4 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_dac.c + cw32l012_dac.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/MDK/project.uvprojx new file mode 100644 index 0000000..bb35551 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/MDK/project.uvprojx @@ -0,0 +1,460 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts.c + 1 + ..\USER\src\interrupts.c + + + + + Bsp + + + Driver + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_dac.c + 1 + ..\..\..\..\Libraries\src\cw32l012_dac.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/USER/inc/interrupts.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/USER/inc/interrupts.h new file mode 100644 index 0000000..b50ff01 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/USER/inc/interrupts.h @@ -0,0 +1,99 @@ +/** + ****************************************************************************** + * @file interrupts.h + * @author AE Team + * @version 1.0 + * @date 2024-03-08 + * @brief This file contains the headers of the interrupt handlers. + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 SIYIMicro. + * All rights reserved.

+ * + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_H +#define __INTERRUPTS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void SysTick_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void SYSCTRL_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_DMACH2_IRQHandler(void); +extern void DMACH3_DMACH4_IRQHandler(void); +extern void CORDIC_IRQHandler(void); +extern void ADC1_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_VC3_IRQHandler(void); +extern void VC2_VC4_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_GTIM4_IRQHandler(void); +extern void LPTIM_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_HALLTIM_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI23_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void ADC2_DAC_IRQHandler(void); +extern void CLKFAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_H */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/USER/inc/main.h new file mode 100644 index 0000000..7a0cd88 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/USER/inc/main.h @@ -0,0 +1,67 @@ +/** + ****************************************************************************** + * @file main.h + * @author AE Team + * @version 1.0 + * @date 2024-08-15 + * @brief Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 SIYIMicro. + * All rights reserved.

+ * + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/USER/src/interrupts.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/USER/src/interrupts.c new file mode 100644 index 0000000..1335f4a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/USER/src/interrupts.c @@ -0,0 +1,446 @@ +/** + ****************************************************************************** + * @file interrupts.c + * @author AE Team + * @version 1.0 + * @date 2024-03-08 + * @brief Interrupt Service Routines. + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 SIYIMicro. + * All rights reserved.

+ * + * + ****************************************************************************** + */ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "interrupts.h" + + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + NVIC_SystemReset(); + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + + /* USER CODE BEGIN SysTick_IRQn */ + + /* USER CODE END SysTick_IRQn */ +} + + +/******************************************************************************/ +/* SYM32L012 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_sym32l012.s). */ +/******************************************************************************/ + +/** + * @brief This function handles WDT. + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles LVD. + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles RTC. + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles FLASH and RAM. + */ +void FLASHRAM_IRQHandler(void) +{ + + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles SYSCTRL. + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GPIOA. + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GPIOB. + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GPIOC. + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GPIOF. + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles DMACH1 and DMACH2. + */ +void DMACH1_DMACH2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles DMACH3 and DMACH4. + */ +void DMACH3_DMACH4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles ADC1. + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles ATIM. + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles VC1 and VC3. + */ +void VC1_VC3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles VC2 and VC4. + */ +void VC2_VC4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GTIM1. + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GTIM2. + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GTIM3 and GTIM4. + */ +void GTIM3_GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles LPTIM. + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles BTIM1. + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles BTIM2. + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles BTIM3 and HALLTIM. + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles I2C1. + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles I2C2. + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles SPI1. + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles SPI2 and SPI3. + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles UART1. + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles UART2. + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles UART3. + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles ADC2 and DAC. + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles CLKFAULT. + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/USER/src/main.c new file mode 100644 index 0000000..4a56a9e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveNoise_SingleCh_SwTrig/USER/src/main.c @@ -0,0 +1,154 @@ +/** + ****************************************************************************** + * @file main.c + * @author AE Team + * @version 1.0 + * @date 2024-08-15 + * @brief 本样例演示通过软件触发的方式使 DAC 单个通道输出噪声。 + * 使用示波器观察DAC_CH1(PB00)或DAC_CH1(PB01) + * + * @note 硬件平台：CW32L012_StartKit_V1.0 + * 接线说明：None + * + ****************************************************************************** + * @attention + * + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + * + ****************************************************************************** + */ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "main.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_dac.h" + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +static void DAC_Config(void); + +/******************************************************************************* + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ******************************************************************************/ +int32_t main(void) +{ + // 初始化系统时钟 + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV24); // 96MHz/24 = 4MHz + + // 初始化DAC + DAC_Config(); + + while (1) + { + DAC_SoftwareTrigger(DAC_CHANNEL_1); +// DAC_SoftwareTrigger(DAC_CHANNEL_2); + FirmwareDelay(10); // 等待输出稳定 + + } +} + + +/******************************************************************************* + * @brief DAC 配置 + * @param None + * @retval None + */ +static void DAC_Config(void) +{ + DAC_InitTypeDef DAC_InitStruct; + + __SYSCTRL_DAC_CLK_ENABLE(); // 开DAC外设时钟 + __SYSCTRL_GPIOB_CLK_ENABLE(); // 开GPIOB外设时钟 + + AFx_DACOUT1_PB00(); // PB00为DAC通道1的输出 +// AFx_DACOUT2_PB01(); // PB01为DAC通道2的输出 + + DAC_DeInit(); + + DAC_InitStruct.DAC_ChannelState = DAC_CHANNEL_ENABLE; + DAC_InitStruct.DAC_DMAState = DAC_DMA_DISABLE; // DMA关闭 + DAC_InitStruct.DAC_DMAUnderflowState = DAC_DMA_UNDERFLOW_DISABLE; // DMA中断关闭 + DAC_InitStruct.DAC_NoiseLFSRUnmaskBits = DAC_LFSRUnmask_Bits11_0; // + DAC_InitStruct.DAC_TriggerSource = DAC_TRIG_SOFTWARE; // 软件触发 + DAC_InitStruct.DAC_TriggerState = DAC_TRIGGER_ENABLE; + DAC_InitStruct.DAC_WaveformMode = DAC_WAVE_NOISE; + + DAC_Init(DAC_CHANNEL_1, &DAC_InitStruct); +// DAC_Init(DAC_CHANNEL_2, &DAC_InitStruct); + + // 通道1输出到PB00使能 + DAC_ChannelOutCmd(DAC_CHANNEL_1, ENABLE); + + // 通道2输出到PB01使能 +// DAC_ChannelOutCmd(DAC_CHANNEL_2, ENABLE); + +} + + +/******************************************************************************* + ** EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END */ +} +#endif /* USE_FULL_ASSERT */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/EWARM/project.ewp new file mode 100644 index 0000000..6895d86 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/EWARM/project.ewp @@ -0,0 +1,2243 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts.c + + + + Bsp + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_dac.c + + + + Doc + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/MDK/project.uvoptx new file mode 100644 index 0000000..6f610d7 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/MDK/project.uvoptx @@ -0,0 +1,335 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\DAC + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts.c + interrupts.c + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + + + Driver + 1 + 0 + 0 + 0 + + 4 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 4 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 4 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_dac.c + cw32l012_dac.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/MDK/project.uvprojx new file mode 100644 index 0000000..bb35551 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/MDK/project.uvprojx @@ -0,0 +1,460 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts.c + 1 + ..\USER\src\interrupts.c + + + + + Bsp + + + Driver + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_dac.c + 1 + ..\..\..\..\Libraries\src\cw32l012_dac.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/USER/inc/interrupts.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/USER/inc/interrupts.h new file mode 100644 index 0000000..b50ff01 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/USER/inc/interrupts.h @@ -0,0 +1,99 @@ +/** + ****************************************************************************** + * @file interrupts.h + * @author AE Team + * @version 1.0 + * @date 2024-03-08 + * @brief This file contains the headers of the interrupt handlers. + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 SIYIMicro. + * All rights reserved.

+ * + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_H +#define __INTERRUPTS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void SysTick_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void SYSCTRL_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_DMACH2_IRQHandler(void); +extern void DMACH3_DMACH4_IRQHandler(void); +extern void CORDIC_IRQHandler(void); +extern void ADC1_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_VC3_IRQHandler(void); +extern void VC2_VC4_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_GTIM4_IRQHandler(void); +extern void LPTIM_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_HALLTIM_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI23_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void ADC2_DAC_IRQHandler(void); +extern void CLKFAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_H */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/USER/inc/main.h new file mode 100644 index 0000000..7a0cd88 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/USER/inc/main.h @@ -0,0 +1,67 @@ +/** + ****************************************************************************** + * @file main.h + * @author AE Team + * @version 1.0 + * @date 2024-08-15 + * @brief Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 SIYIMicro. + * All rights reserved.

+ * + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/USER/src/interrupts.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/USER/src/interrupts.c new file mode 100644 index 0000000..1335f4a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/USER/src/interrupts.c @@ -0,0 +1,446 @@ +/** + ****************************************************************************** + * @file interrupts.c + * @author AE Team + * @version 1.0 + * @date 2024-03-08 + * @brief Interrupt Service Routines. + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 SIYIMicro. + * All rights reserved.

+ * + * + ****************************************************************************** + */ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "interrupts.h" + + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + NVIC_SystemReset(); + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + + /* USER CODE BEGIN SysTick_IRQn */ + + /* USER CODE END SysTick_IRQn */ +} + + +/******************************************************************************/ +/* SYM32L012 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_sym32l012.s). */ +/******************************************************************************/ + +/** + * @brief This function handles WDT. + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles LVD. + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles RTC. + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles FLASH and RAM. + */ +void FLASHRAM_IRQHandler(void) +{ + + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles SYSCTRL. + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GPIOA. + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GPIOB. + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GPIOC. + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GPIOF. + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles DMACH1 and DMACH2. + */ +void DMACH1_DMACH2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles DMACH3 and DMACH4. + */ +void DMACH3_DMACH4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles ADC1. + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles ATIM. + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles VC1 and VC3. + */ +void VC1_VC3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles VC2 and VC4. + */ +void VC2_VC4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GTIM1. + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GTIM2. + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GTIM3 and GTIM4. + */ +void GTIM3_GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles LPTIM. + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles BTIM1. + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles BTIM2. + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles BTIM3 and HALLTIM. + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles I2C1. + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles I2C2. + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles SPI1. + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles SPI2 and SPI3. + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles UART1. + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles UART2. + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles UART3. + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles ADC2 and DAC. + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles CLKFAULT. + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/USER/src/main.c new file mode 100644 index 0000000..53026a1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_WaveTriangle_SingleCh_SwTrig/USER/src/main.c @@ -0,0 +1,154 @@ +/** + ****************************************************************************** + * @file main.c + * @author AE Team + * @version 1.0 + * @date 2024-08-15 + * @brief 本样例演示通过软件触发的方式使 DAC 单个通道输出三角波。 + * 使用示波器观察DAC_CH1(PB00)或DAC_CH1(PB01) + * + * @note 硬件平台：CW32L012_StartKit_V1.0 + * 接线说明：None + * + ****************************************************************************** + * @attention + * + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + * + ****************************************************************************** + */ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "main.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_dac.h" + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +static void DAC_Config(void); + +/******************************************************************************* + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ******************************************************************************/ +int32_t main(void) +{ + // 初始化系统时钟 + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV24); // 96MHz/24 = 4MHz + + // 初始化DAC + DAC_Config(); + + while (1) + { + DAC_SoftwareTrigger(DAC_CHANNEL_1); +// DAC_SoftwareTrigger(DAC_CHANNEL_2); + FirmwareDelay(10); // 等待输出稳定 + + } +} + + +/******************************************************************************* + * @brief DAC 配置 + * @param None + * @retval None + */ +static void DAC_Config(void) +{ + DAC_InitTypeDef DAC_InitStruct; + + __SYSCTRL_DAC_CLK_ENABLE(); // 开DAC外设时钟 + __SYSCTRL_GPIOB_CLK_ENABLE(); // 开GPIOB外设时钟 + + AFx_DACOUT1_PB00(); // PB00为DAC通道1的输出 +// AFx_DACOUT2_PB01(); // PB01为DAC通道2的输出 + + DAC_DeInit(); + + DAC_InitStruct.DAC_ChannelState = DAC_CHANNEL_ENABLE; + DAC_InitStruct.DAC_DMAState = DAC_DMA_DISABLE; // DMA关闭 + DAC_InitStruct.DAC_DMAUnderflowState = DAC_DMA_UNDERFLOW_DISABLE; // DMA中断关闭 + DAC_InitStruct.DAC_TriangleAmplitude = DAC_TriangleAmplitude_4095; // + DAC_InitStruct.DAC_TriggerSource = DAC_TRIG_SOFTWARE; // 软件触发 + DAC_InitStruct.DAC_TriggerState = DAC_TRIGGER_ENABLE; + DAC_InitStruct.DAC_WaveformMode = DAC_WAVE_TRIANGLE; + + DAC_Init(DAC_CHANNEL_1, &DAC_InitStruct); +// DAC_Init(DAC_CHANNEL_2, &DAC_InitStruct); + + // 通道1输出到PB00使能 + DAC_ChannelOutCmd(DAC_CHANNEL_1, ENABLE); + + // 通道2输出到PB01使能 +// DAC_ChannelOutCmd(DAC_CHANNEL_2, ENABLE); + +} + + +/******************************************************************************* + ** EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END */ +} +#endif /* USE_FULL_ASSERT */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/EWARM/project.ewp new file mode 100644 index 0000000..ac2479d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/MDK/project.uvoptx new file mode 100644 index 0000000..3773186 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/MDK/project.uvoptx @@ -0,0 +1,363 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts.c + 1 + ..\USER\src\interrupts.c + + + + + Bsp + + + Driver + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_dac.c + 1 + ..\..\..\..\Libraries\src\cw32l012_dac.c + + + cw32l012_btim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_btim.c + + + cw32l012_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gtim.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/USER/inc/interrupts.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/USER/inc/interrupts.h new file mode 100644 index 0000000..0239c36 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/USER/inc/interrupts.h @@ -0,0 +1,99 @@ +/** + ****************************************************************************** + * @file interrupts.h + * @author AE Team + * @version 1.0 + * @date 2024-03-08 + * @brief This file contains the headers of the interrupt handlers. + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 SIYIMicro. + * All rights reserved.

+ * + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_H +#define __INTERRUPTS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void SysTick_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void SYSCTRL_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_DMACH2_IRQHandler(void); +extern void DMACH3_DMACH4_IRQHandler(void); +extern void CORDIC_IRQHandler(void); +extern void ADC1_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_VC3_IRQHandler(void); +extern void VC2_VC4_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_GTIM4_IRQHandler(void); +extern void LPTIM_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_HALLTIM_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI23_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void ADC2_DAC_IRQHandler(void); +extern void CLKFAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_H */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/USER/inc/main.h new file mode 100644 index 0000000..8d21f1b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/USER/inc/main.h @@ -0,0 +1,67 @@ +/** + ****************************************************************************** + * @file main.h + * @author AE Team + * @version 1.0 + * @date 2024-08-15 + * @brief Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 SIYIMicro. + * All rights reserved.

+ * + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "sym32l012_hal_def.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/USER/src/interrupts.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/USER/src/interrupts.c new file mode 100644 index 0000000..3a2d98c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/USER/src/interrupts.c @@ -0,0 +1,445 @@ +/** + ****************************************************************************** + * @file interrupts.c + * @author AE Team + * @version 1.0 + * @date 2024-03-08 + * @brief Interrupt Service Routines. + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 SIYIMicro. + * All rights reserved.

+ * + * + ****************************************************************************** + */ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "interrupts.h" + + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + + /* USER CODE BEGIN SysTick_IRQn */ + + /* USER CODE END SysTick_IRQn */ +} + + +/******************************************************************************/ +/* SYM32L012 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_sym32l012.s). */ +/******************************************************************************/ + +/** + * @brief This function handles WDT. + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles LVD. + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles RTC. + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles FLASH and RAM. + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles SYSCTRL. + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GPIOA. + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GPIOB. + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GPIOC. + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GPIOF. + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles DMACH1 and DMACH2. + */ +void DMACH1_DMACH2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles DMACH3 and DMACH4. + */ +void DMACH3_DMACH4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles ADC1. + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles ATIM. + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles VC1 and VC3. + */ +void VC1_VC3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles VC2 and VC4. + */ +void VC2_VC4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GTIM1. + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GTIM2. + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GTIM3 and GTIM4. + */ +void GTIM3_GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles LPTIM. + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles BTIM1. + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles BTIM2. + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles BTIM3 and HALLTIM. + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles I2C1. + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles I2C2. + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles SPI1. + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles SPI2 and SPI3. + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles UART1. + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles UART2. + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles UART3. + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles ADC2 and DAC. + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles CLKFAULT. + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/USER/src/main.c new file mode 100644 index 0000000..6d0177b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_HwTrig/USER/src/main.c @@ -0,0 +1,230 @@ +/** + ****************************************************************************** + * @file main.c + * @author AE Team + * @version 1.0 + * @date 2024-08-15 + * @brief 本样例演示通过硬件触发的方式使 DAC 双通道输出三角波或者噪声波。 + * DAC_CH1 由 BTIM1_TRGO(OV) 信号进行硬件触发，生成三角波。 + * DAC_CH2 由 GTIM1_TRGO(UPDATE) 信号进行硬件触发，生成噪声波。 + * + * 使用示波器观察 DAC_CH1(PB00) 的波形。 + * 使用示波器观察 DAC_CH2(PB01) 的波形。 + * + * @note 硬件平台：CW32L012_StartKit_V1.0 + * 接线说明：None + * + ****************************************************************************** + * @attention + * + * + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + * + ****************************************************************************** + */ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_dac.h" +#include "cw32l012_btim.h" +#include "cw32l012_gtim.h" + + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +static void DAC_Config(void); +static void BTIM_Config(void); +static void GTIM_Config(void); + +/******************************************************************************* + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ******************************************************************************/ +int32_t main(void) +{ + // 初始化系统时钟 + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV24); // 系统时钟4Mhz + + // 初始化DAC + DAC_Config(); + + // 初始化BTIM1 + BTIM_Config(); + + // 初始化GTIM1 + GTIM_Config(); + + // 开启BTIM计数触发DAC转换 + BTIM_Cmd(CW_BTIM1, ENABLE); + // 开启GTIM计数触发DAC转换 + GTIM_Cmd(CW_GTIM1, ENABLE); + + + while (1) + { + ; + } +} + + +/******************************************************************************* + * @brief DAC 初始化 + * @param None + * @retval None + */ +static void DAC_Config(void) +{ + DAC_InitTypeDef DAC_InitStruct; + + __SYSCTRL_DAC_CLK_ENABLE(); // 开DAC外设时钟 + __SYSCTRL_GPIOB_CLK_ENABLE(); // 开GPIOB外设时钟 + + AFx_DACOUT1_PB00(); // PB00为DAC通道1的输出 + AFx_DACOUT2_PB01(); // PB01为DAC通道2的输出 + + DAC_DeInit(); + + DAC_InitStruct.DAC_ChannelState = DAC_CHANNEL_ENABLE; + DAC_InitStruct.DAC_DMAState = DAC_DMA_DISABLE; // DMA关闭 + DAC_InitStruct.DAC_DMAUnderflowState = DAC_DMA_UNDERFLOW_DISABLE; // DMA中断关闭 + DAC_InitStruct.DAC_TriangleAmplitude = DAC_TriangleAmplitude_4095; // + DAC_InitStruct.DAC_TriggerSource = DAC_TRIG_BTIM1_Trgo; // 基本定时器1 TRGO + DAC_InitStruct.DAC_TriggerState = DAC_TRIGGER_ENABLE; + DAC_InitStruct.DAC_WaveformMode = DAC_WAVE_TRIANGLE; + DAC_Init(DAC_CHANNEL_1, &DAC_InitStruct); + + DAC_InitStruct.DAC_NoiseLFSRUnmaskBits = DAC_LFSRUnmask_Bits11_0; // + DAC_InitStruct.DAC_TriggerSource = DAC_TRIG_GTIM1_Trgo; // 通用定时器1 TRGO + DAC_InitStruct.DAC_TriggerState = DAC_TRIGGER_ENABLE; + DAC_InitStruct.DAC_WaveformMode = DAC_WAVE_NOISE; + DAC_Init(DAC_CHANNEL_2, &DAC_InitStruct); + + // 通道1输出到PB00使能 + DAC_ChannelOutCmd(DAC_CHANNEL_1, ENABLE); + + // 通道2输出到PB01使能 + DAC_ChannelOutCmd(DAC_CHANNEL_2, ENABLE); + +} + + +/******************************************************************************* + * @brief BTIM1 初始化 + * @param None + * @retval None + */ +static void BTIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + BTIM_TimeBaseInitTypeDef BTIM_InitStruct ={0}; + + // 使能外设时钟 + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_BTIM123_CLK_ENABLE(); + + // 配置PA07作为BTIM1的TOGN管脚，以查看BTIM的溢出周期 + PA07_AFx_BTIM1TOGN(); + GPIO_InitStruct.Pins = GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + + // 初始化BTIM1 + BTIM_InitStruct.BTIM_CountMode = BTIM_COUNT_MODE_REPETITIVE; + BTIM_InitStruct.BTIM_Mode = BTIM_MODE_TIMER; + BTIM_InitStruct.BTIM_Prescaler = 4 - 1; // 预分频系数3, 4分频，4MHz/(3+1)= 1MHz + BTIM_InitStruct.BTIM_Period = 100 -1; // 溢出频率为10KHz (1MHz / 100 = 10KHz) + + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_InitStruct); + + BTIM_OutputToggleCmd(CW_BTIM1, ENABLE); // 每次溢出，IO翻转一次 + + BTIM_MasterOutputTriggerConfig(CW_BTIM1, BTIM_MASTER_OUTPUT_TRIGGER_OVERFLOW); +} + +/******************************************************************************* + * @brief GTIM1 初始化 + * @param None + * @retval None + */ +static void GTIM_Config(void) +{ + GTIM_InitTypeDef GTIM_InitStruct = {0}; + + __SYSCTRL_GTIM1_CLK_ENABLE(); + + GTIM_InitStruct.AlignMode = GTIM_ALIGN_MODE_CENTER_UP; + GTIM_InitStruct.ARRBuffState = GTIM_ARR_BUFF_DIS; + GTIM_InitStruct.PulseMode = GTIM_PULSE_MODE_DIS; + GTIM_InitStruct.Prescaler = 2 - 1; // 预分频系数1, 2分频，4MHz/(1+1)= 2MHz + GTIM_InitStruct.ReloadValue = 100 - 1; // 溢出频率为20KHz (2MHz / 100 = 20KHz) + + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + GTIM_MasterTRGOCfg(CW_GTIM1, GTIM_MASTER_TRGO_UPDATE); + +} +/******************************************************************************* + ** EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END */ +} +#endif /* USE_FULL_ASSERT */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/EWARM/project.ewp new file mode 100644 index 0000000..6c0f8f1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/EWARM/project.ewp @@ -0,0 +1,2246 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_dac.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_btim.c + + + + Doc + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/MDK/project.uvoptx new file mode 100644 index 0000000..039a588 --- /dev/null +++ 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts.c + 1 + ..\USER\src\interrupts.c + + + + + Bsp + + + Driver + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_dac.c + 1 + ..\..\..\..\Libraries\src\cw32l012_dac.c + + + cw32l012_btim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_btim.c + + + + + Doc + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/USER/inc/interrupts.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/USER/inc/interrupts.h new file mode 100644 index 0000000..ec4c6b5 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/USER/inc/interrupts.h @@ -0,0 +1,98 @@ +/** + ****************************************************************************** + * @file interrupts.h + * @author AE Team + * @version 1.0 + * @date 2024-03-08 + * @brief This file contains the headers of the interrupt handlers. + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 SIYIMicro. + * All rights reserved.

+ * + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_H +#define __INTERRUPTS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void SysTick_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void SYSCTRL_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void GPIOC_IRQHandler(void); +extern void GPIOF_IRQHandler(void); +extern void DMACH1_DMACH2_IRQHandler(void); +extern void DMACH3_DMACH4_IRQHandler(void); +extern void CORDIC_IRQHandler(void); +extern void ADC1_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_VC3_IRQHandler(void); +extern void VC2_VC4_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void GTIM2_IRQHandler(void); +extern void GTIM3_GTIM4_IRQHandler(void); +extern void LPTIM_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_HALLTIM_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void I2C2_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void SPI23_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void UART3_IRQHandler(void); +extern void ADC2_DAC_IRQHandler(void); +extern void CLKFAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_H */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/USER/inc/main.h new file mode 100644 index 0000000..8d21f1b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/USER/inc/main.h @@ -0,0 +1,67 @@ +/** + ****************************************************************************** + * @file main.h + * @author AE Team + * @version 1.0 + * @date 2024-08-15 + * @brief Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 SIYIMicro. + * All rights reserved.

+ * + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "sym32l012_hal_def.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/USER/src/interrupts.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/USER/src/interrupts.c new file mode 100644 index 0000000..4937072 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/USER/src/interrupts.c @@ -0,0 +1,446 @@ +/** + ****************************************************************************** + * @file interrupts.c + * @author AE Team + * @version 1.0 + * @date 2024-03-08 + * @brief Interrupt Service Routines. + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 SIYIMicro. + * All rights reserved.

+ * + * + ****************************************************************************** + */ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "interrupts.h" + + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + + /* USER CODE BEGIN SysTick_IRQn */ + + /* USER CODE END SysTick_IRQn */ +} + + +/******************************************************************************/ +/* SYM32L012 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_sym32l012.s). */ +/******************************************************************************/ + +/** + * @brief This function handles WDT. + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles LVD. + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles RTC. + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles FLASH and RAM. + */ +void FLASHRAM_IRQHandler(void) +{ + + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles SYSCTRL. + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GPIOA. + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GPIOB. + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GPIOC. + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GPIOF. + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles DMACH1 and DMACH2. + */ +void DMACH1_DMACH2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles DMACH3 and DMACH4. + */ +void DMACH3_DMACH4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles ADC1. + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles ATIM. + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles VC1 and VC3. + */ +void VC1_VC3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles VC2 and VC4. + */ +void VC2_VC4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GTIM1. + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GTIM2. + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles GTIM3 and GTIM4. + */ +void GTIM3_GTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles LPTIM. + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles BTIM1. + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles BTIM2. + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles BTIM3 and HALLTIM. + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles I2C1. + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles I2C2. + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles SPI1. + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles SPI2 and SPI3. + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles UART1. + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles UART2. + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles UART3. + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles ADC2 and DAC. + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This function handles CLKFAULT. + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/USER/src/main.c new file mode 100644 index 0000000..52f2840 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DAC/DAC_Wave_DualCh_SwTrig/USER/src/main.c @@ -0,0 +1,156 @@ +/** + ****************************************************************************** + * @file main.c + * @author AE Team + * @version 1.0 + * @date 2024-08-15 + * @brief 本样例演示通过软件触发的方式使 DAC 双通道分别输出三角波或噪声波。 + * + * 使用示波器观察 DAC_CH1(PB00) 生成的三角波 + * 使用示波器观察 DAC_CH2(PB01) 生成的噪声波 + * + * @note 硬件平台：CW32L012_StartKit_V1.0 + * 接线说明：None + * + ****************************************************************************** + * @attention + * + * + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + * + ****************************************************************************** + */ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_dac.h" + + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +static void DAC_Config(void); + + +/******************************************************************************* + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ******************************************************************************/ +int32_t main(void) +{ + // 初始化系统时钟 + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV24); // 系统时钟4Mhz + + // 初始化DAC + DAC_Config(); + + while (1) + { + DAC_DualSoftwareTrigger(); + FirmwareDelay(10); // 等待输出稳定 + } +} + + +/******************************************************************************* + * @brief DAC 初始化 + * @param None + * @retval None + */ +static void DAC_Config(void) +{ + DAC_InitTypeDef DAC_InitStruct; + + __SYSCTRL_DAC_CLK_ENABLE(); // 开DAC外设时钟 + __SYSCTRL_GPIOB_CLK_ENABLE(); // 开GPIOB外设时钟 + + AFx_DACOUT1_PB00(); // PB00为DAC通道1的输出 + AFx_DACOUT2_PB01(); // PB01为DAC通道2的输出 + + DAC_DeInit(); + + DAC_InitStruct.DAC_ChannelState = DAC_CHANNEL_ENABLE; + DAC_InitStruct.DAC_DMAState = DAC_DMA_DISABLE; // DMA关闭 + DAC_InitStruct.DAC_DMAUnderflowState = DAC_DMA_UNDERFLOW_DISABLE; // DMA中断关闭 + DAC_InitStruct.DAC_TriangleAmplitude = DAC_TriangleAmplitude_4095; // + DAC_InitStruct.DAC_TriggerSource = DAC_TRIG_SOFTWARE; // 软件触发 + DAC_InitStruct.DAC_TriggerState = DAC_TRIGGER_ENABLE; + DAC_InitStruct.DAC_WaveformMode = DAC_WAVE_TRIANGLE; + DAC_Init(DAC_CHANNEL_1, &DAC_InitStruct); + + DAC_InitStruct.DAC_NoiseLFSRUnmaskBits = DAC_LFSRUnmask_Bits11_0; // + DAC_InitStruct.DAC_WaveformMode = DAC_WAVE_NOISE; + DAC_Init(DAC_CHANNEL_2, &DAC_InitStruct); + + // 通道1输出到PB00使能 + DAC_ChannelOutCmd(DAC_CHANNEL_1, ENABLE); + + // 通道2输出到PB01使能 + DAC_ChannelOutCmd(DAC_CHANNEL_2, ENABLE); +} + + +/******************************************************************************* + ** EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END */ +} +#endif /* USE_FULL_ASSERT */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/EWARM/project.ewp new file mode 100644 index 0000000..fe0ded6 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_digitalsign.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/MDK/DigitalSign.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/MDK/DigitalSign.uvoptx new file mode 100644 index 0000000..ca35ef6 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/MDK/DigitalSign.uvoptx @@ -0,0 +1,392 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO0 -FD20000000 -FC1000 -FN1 -FF0Flashcw32l012.FLM -FS00 -FL010000 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + + 0 + 1 + Chip_Type + + + 1 + 1 + Chip_Uid + + + + + 1 + 0 + 0x3c00 + 0 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 1000000 + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_digitalsign.c + cw32l012_digitalsign.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/MDK/DigitalSign.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/MDK/DigitalSign.uvprojx new file mode 100644 index 0000000..be08086 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/MDK/DigitalSign.uvprojx @@ -0,0 +1,488 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + cw32l012xx + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_digitalsign.c + 1 + ..\..\..\..\Libraries\src\cw32l012_digitalsign.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/USER/inc/main.h new file mode 100644 index 0000000..b68cbe0 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/USER/inc/main.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/USER/src/main.c new file mode 100644 index 0000000..ddbd6f0 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/USER/src/main.c @@ -0,0 +1,130 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2022-7-12 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_digitalsign.h" +#include "cw32l012_gpio.h" +#include "cw32l012_systick.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +//extern LED_InitTypeDef LED1 , LED2; +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +uint8_t Chip_Type[24]; +uint8_t Pin_Count; +uint32_t Flash_Size; +uint16_t Ram_Size; +uint8_t Chip_Uid[10]; + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle GPIOA.00 + ** + ******************************************************************************/ +int32_t main(void) +{ + uint8_t i; + Bsp_Init(4000000); + InitTick(4000000); + + DIGITALSIGN_GetChipType(Chip_Type); + Pin_Count = DIGITALSIGN_GetPinCount(); + Flash_Size = DIGITALSIGN_GetFlashSize(); + Ram_Size = DIGITALSIGN_GetRamSize(); + DIGITALSIGN_GetChipUid(Chip_Uid); //UID地址 + + printf("The chip Type is %s\r\n", Chip_Type); + printf("The chip has %d pins\r\n", Pin_Count); + printf("The chip provides %d bytes FLASH\r\n", Flash_Size); + printf("The chip provides %d bytes SRAM\r\n", Ram_Size); + printf("The chip UUID is"); + for (i = 0; i < 10; i++) + { + printf(" 0x%02X", Chip_Uid[i]); + } + printf("\r\n"); + + while (1) + { + Bsp_Led_Tog(&LED1); + SysTickDelay(1000); + } + +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/readme.txt new file mode 100644 index 0000000..baf5787 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DIGITALSIGN/DigitalSign/readme.txt @@ -0,0 +1,24 @@ +示例目的： + 读取数字签名相关内容。 + +硬件资源： + 1. CW32L012CxTx StartKit + 2. 时钟HSI + 3. 系统时钟默认HSI时钟分频到4MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + 4. 板载串口 + +演示说明： + 程序依次读取芯片类型/引脚数/FLASH容量/RAM容量以及芯片UID，然后通过板载串口打印。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/EWARM/project.ewp new file mode 100644 index 0000000..fdc6471 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_dma.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/MDK/Project.uvoptx new file mode 100644 index 0000000..624edcd --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/MDK/Project.uvoptx @@ -0,0 +1,328 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012 -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_dma.c + cw32l012_dma.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/MDK/Project.uvprojx new file mode 100644 index 0000000..0de1b7c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/MDK/Project.uvprojx @@ -0,0 +1,474 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_dma.c + 1 + ..\..\..\..\Libraries\src\cw32l012_dma.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/USER/inc/main.h new file mode 100644 index 0000000..1341c24 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/USER/inc/main.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "cw32l012_opa.h" +#include "cw32l012_adc.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/USER/src/main.c new file mode 100644 index 0000000..b016acc --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/DMA/DMA_SoftTrigger_Poll/USER/src/main.c @@ -0,0 +1,132 @@ +/** + ****************************************************************************** + * @file main.c + * @author AE Team + * @version 1.0 + * @date 2024-08-15 + * @brief + * + * @note 硬件平台：CW32L012_StartKit_V1.0 + * + * + *****************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" +#include "cw32l012_dma.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ** + ******************************************************************************/ +int32_t main(void) +{ + + // 初始化时钟为96MHz/12 = 8MHz； + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + + DMA_InitTypeDef DMA_InitStruct = {0}; + + DMA_InitStruct.BlockCount = 1; + DMA_InitStruct.TransferCount = 20; + DMA_InitStruct.DataSize = DMA_DATA_SIZE_32BITS; + DMA_InitStruct.DstAddress = 0x20000200; + DMA_InitStruct.DstIncrement = DMA_ADDRESS_INCREMENT; + DMA_InitStruct.RestartEnable = FALSE; + DMA_InitStruct.SrcAddress = 0x00000000; + DMA_InitStruct.SrcIncrement = DMA_ADDRESS_INCREMENT; + DMA_InitStruct.TransferMode = DMA_MODE_BLOCK; + DMA_InitStruct.TriggerSource = DMA_TRIGGER_SRC_UART1_RX; //采用软件触发，硬件触发源无意义 + DMA_InitStruct.TriggerType = DMA_TRIGGER_SOFTWARE; + + // 初始化DMA + DMA_Init(DMA_CHANNEL_1, &DMA_InitStruct); + + // 使能DMA + DMA_Cmd(DMA_CHANNEL_1, ENABLE); + + // 软件启动传输 + DMA_StartTransfer(DMA_CHANNEL_1); + + // 检查传输完成 + while(DMA_STATUS_COMPLETE != DMA_CheckStatus(DMA_CHANNEL_1)); + + // 清除传输完成中断标志 + DMA_ClearInterruptFlag(DMA_CHANNEL_1, DMA_INTERRUPT_TE|DMA_INTERRUPT_TC); + + while(1); + + +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/EWARM/project.ewp new file mode 100644 index 0000000..47d52f4 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + 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$PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/MDK/Project.uvoptx new file mode 100644 index 0000000..3e18cf8 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/MDK/Project.uvoptx @@ -0,0 +1,368 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + -UAny -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012F8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ST-LINKIII-KEIL_SWO + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FN1 -FC1000 -FD20000000 -FF0FlashCW32L012 -FL010000 -FS00 -FP0($$Device:CW32L012F8$Flash\FlashCW32L012.FLM) + + + 0 + DLGTARM + (1010=75,104,486,606,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 1 + 8 + 0x20000200 + 0 + + + + + 2 + 0 + 0 + 0 + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\DMA + 35905 + + + System Viewer\EAU + 35904 + + + System Viewer\SYSCTRL + 35903 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_eau.c + cw32l012_eau.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/MDK/Project.uvprojx new file mode 100644 index 0000000..c5404e9 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/MDK/Project.uvprojx @@ -0,0 +1,474 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_eau.c + 1 + ..\..\..\..\Libraries\src\cw32l012_eau.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/USER/inc/main.h new file mode 100644 index 0000000..1341c24 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/USER/inc/main.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "cw32l012_opa.h" +#include "cw32l012_adc.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/USER/src/main.c new file mode 100644 index 0000000..e05a842 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Signed_Div/USER/src/main.c @@ -0,0 +1,128 @@ +/** + ****************************************************************************** + * @file main.c + * @author AE Team + * @version 1.0 + * @date 2024-08-15 + * @brief + * + * @note 硬件平台：CW32L012_StartKit_V1.0 + * + * + *****************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" +#include "cw32l012_eau.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ** + ******************************************************************************/ +char RamBuf[100] __attribute__((at(0x20000200))); +int32_t main(void) +{ + int32_t dividend = -1000; // 被除数（有符号） + int32_t divisor = 7; // 除数（有符号） + int32_t quotient; + int32_t remainder; + + // 初始化EAU + EAU_Init(); + + // 设置为有符号除法模式 + EAU_SetMode(EAU_MODE_SIGNED_DIV); + + // 开始运算 + EAU_StartOperation((uint32_t)dividend, (uint32_t)divisor); + + // 等待运算完成 + while (EAU_GetStatus() & EAU_STATUS_BUSY) { + // 等待忙碌标志位清零 + } + + // 获取结果 + quotient = (int32_t)EAU_GetQuotient(); + remainder = (int32_t)EAU_GetRemainder(); + + // 输出结果 + sprintf(RamBuf, "signed div operation:\n"); + sprintf(&RamBuf[25],"dividend:%d\n", dividend); + sprintf(&RamBuf[45],"divisor:%d\n", divisor); + sprintf(&RamBuf[60],"quotient:%d\n", quotient); + sprintf(&RamBuf[80],"remainder:%d\n", remainder); + + while(1); +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/EWARM/project.ewp new file mode 100644 index 0000000..47d52f4 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_eau.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/MDK/Project.uvoptx new file mode 100644 index 0000000..3e18cf8 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/MDK/Project.uvoptx @@ -0,0 +1,368 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + -UAny -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012F8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ST-LINKIII-KEIL_SWO + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FN1 -FC1000 -FD20000000 -FF0FlashCW32L012 -FL010000 -FS00 -FP0($$Device:CW32L012F8$Flash\FlashCW32L012.FLM) + + + 0 + DLGTARM + (1010=75,104,486,606,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 1 + 8 + 0x20000200 + 0 + + + + + 2 + 0 + 0 + 0 + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\DMA + 35905 + + + System Viewer\EAU + 35904 + + + System Viewer\SYSCTRL + 35903 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_eau.c + cw32l012_eau.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/MDK/Project.uvprojx new file mode 100644 index 0000000..c5404e9 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/MDK/Project.uvprojx @@ -0,0 +1,474 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_eau.c + 1 + ..\..\..\..\Libraries\src\cw32l012_eau.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/USER/inc/main.h new file mode 100644 index 0000000..1341c24 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/USER/inc/main.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "cw32l012_opa.h" +#include "cw32l012_adc.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/USER/src/main.c new file mode 100644 index 0000000..ca5ab37 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Sqrt/USER/src/main.c @@ -0,0 +1,125 @@ +/** + ****************************************************************************** + * @file main.c + * @author AE Team + * @version 1.0 + * @date 2024-08-15 + * @brief + * + * @note 硬件平台：CW32L012_StartKit_V1.0 + * + * + *****************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" +#include "cw32l012_eau.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ** + ******************************************************************************/ +char RamBuf[100] __attribute__((at(0x20000200))); +int32_t main(void) +{ + uint32_t dividend = 1024; // 被开方数 + uint32_t quotient; + + memset(RamBuf,0, 100); + + // 初始化EAU + EAU_Init(); + + // 设置为开方模式 + EAU_SetMode(EAU_MODE_SQRT); + + // 开始开方运算（除数寄存器不使用） + EAU_StartOperation(dividend, 0); + + // 等待运算完成 + while (EAU_GetStatus() & EAU_STATUS_BUSY) { + // 等待忙碌标志位清零 + } + + // 获取结果 + quotient = EAU_GetQuotient(); + + // 输出结果 + sprintf(RamBuf, "sqrt operation:\n"); + sprintf(&RamBuf[32],"dividend:%u\n", dividend); + sprintf(&RamBuf[64],"quotient:%u\n", quotient); + + while(1); +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/EWARM/project.ewp new file mode 100644 index 0000000..47d52f4 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_eau.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/MDK/Project.uvoptx new file mode 100644 index 0000000..3e18cf8 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/MDK/Project.uvoptx @@ -0,0 +1,368 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + -UAny -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012F8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ST-LINKIII-KEIL_SWO + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FN1 -FC1000 -FD20000000 -FF0FlashCW32L012 -FL010000 -FS00 -FP0($$Device:CW32L012F8$Flash\FlashCW32L012.FLM) + + + 0 + DLGTARM + (1010=75,104,486,606,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 1 + 8 + 0x20000200 + 0 + + + + + 2 + 0 + 0 + 0 + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\DMA + 35905 + + + System Viewer\EAU + 35904 + + + System Viewer\SYSCTRL + 35903 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_eau.c + cw32l012_eau.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/MDK/Project.uvprojx new file mode 100644 index 0000000..c5404e9 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/MDK/Project.uvprojx @@ -0,0 +1,474 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_eau.c + 1 + ..\..\..\..\Libraries\src\cw32l012_eau.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/USER/inc/main.h new file mode 100644 index 0000000..1341c24 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/USER/inc/main.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "cw32l012_opa.h" +#include "cw32l012_adc.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/USER/src/main.c new file mode 100644 index 0000000..bea48bf --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/EAU/EAU_Mode_Unsigned_Div/USER/src/main.c @@ -0,0 +1,127 @@ +/** + ****************************************************************************** + * @file main.c + * @author AE Team + * @version 1.0 + * @date 2024-08-15 + * @brief + * + * @note 硬件平台：CW32L012_StartKit_V1.0 + * + * + *****************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" +#include "cw32l012_eau.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ** + ******************************************************************************/ +char RamBuf[100] __attribute__((at(0x20000200))); +int32_t main(void) +{ + uint32_t dividend = 1000; // 被除数 + uint32_t divisor = 7; // 除数 + uint32_t quotient, remainder; + + // 初始化EAU + EAU_Init(); + + // 设置为无符号除法模式 + EAU_SetMode(EAU_MODE_UNSIGNED_DIV); + + // 开始运算 + EAU_StartOperation(dividend, divisor); + + // 等待运算完成 + while (EAU_GetStatus() & EAU_STATUS_BUSY) { + // 等待忙碌标志位清零 + } + + // 获取结果 + quotient = EAU_GetQuotient(); + remainder = EAU_GetRemainder(); + + // 输出结果 + sprintf(RamBuf, "signed div operation:\n"); + sprintf(&RamBuf[25],"dividend:%d\n", dividend); + sprintf(&RamBuf[45],"divisor:%d\n", divisor); + sprintf(&RamBuf[60],"quotient:%d\n", quotient); + sprintf(&RamBuf[80],"remainder:%d\n", remainder); + + while(1); +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/EWARM/project.ewp new file mode 100644 index 0000000..3659620 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/EWARM/project.ewp @@ -0,0 +1,2255 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + 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a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/MDK/OTP_Write.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/MDK/OTP_Write.uvoptx new file mode 100644 index 0000000..0c5acbd --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/MDK/OTP_Write.uvoptx @@ -0,0 +1,406 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FN1 -FC1000 -FD20000000 -FF0FlashCW32L012_TEST -FL010000 -FS00 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + + 1 + 0 + 0x00100760 + 0 + + + + + 2 + 0 + 0xfc00 + 0 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\FLASH + 35905 + + + + 1 + 1 + 0 + 2 + 1000000 + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/MDK/OTP_Write.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/MDK/OTP_Write.uvprojx new file mode 100644 index 0000000..5f98410 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/MDK/OTP_Write.uvprojx @@ -0,0 +1,483 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\StartKit_Board + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..a78faed --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,88 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void SYSCTRL_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void LPTIM_IRQHandler(void); +extern void CLKFAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/USER/inc/main.h new file mode 100644 index 0000000..e9f1b7b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "system_cw32l012.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_flash.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..2d8e7be --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/USER/src/interrupts_cw32l012.c @@ -0,0 +1,374 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" +#include "interrupts_cw32l012.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW32 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_cw32xxxx.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C + */ +void I2C_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/USER/src/main.c new file mode 100644 index 0000000..6e65747 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/USER/src/main.c @@ -0,0 +1,156 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2022-7-12 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define LED2_PORT CW_GPIOB +#define LED2_PIN GPIO_PIN_8 +#define LED2_ON() PB08_SETHIGH() +#define LED2_OFF() PB08_SETLOW() +#define LED2_TOG() PB08_TOG() + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Main function of project + * + * + * @return int32_t + */ + +int32_t main(void) +{ + uint8_t Flag; + uint32_t OTP_Addr = OTP_START_ADDRESS; + uint8_t OTP_DataBuf[] ={0x55, 0xAA, 0xC3, 0x3C}; + + GPIO_InitTypeDef GPIO_InitStruct; + + //时钟初始化 + SYSCTRL_Configuration(); + + + //LED2 配置 + GPIO_InitStruct.Pins = LED2_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(LED2_PORT, &GPIO_InitStruct); + + LED2_ON(); + __breakpoint(0); // 暂停，以防程序下载后自动运行 + + // 写入数据到OTP区 + Flag = OTP_WriteBytes(OTP_Addr, OTP_DataBuf, 4); + if (Flag) + { + LED2_OFF(); + while(1); //写入失败 + } + + __breakpoint(0); // 请在此处查看OTP区是否写入目标数据 + + // 再次写入 + OTP_DataBuf[0] = 0x00; + Flag = OTP_WriteBytes(OTP_Addr, OTP_DataBuf, 4); + if (!Flag) + { + LED2_OFF(); + while(1); // 正常状态应该不会执行到此处 + } + + __breakpoint(0); // 请在此处查看OTP区是否写入目标数据 + + + //结束 + while(1) + { + LED2_TOG(); + FirmwareDelay(300000); + } + +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + __SYSCTRL_FLASH_CLK_ENABLE(); +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/readme.txt new file mode 100644 index 0000000..a05e15f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/OTP_Write/readme.txt @@ -0,0 +1,25 @@ +示例目的： + 对MCU内置的OTP区写/读操作，并对比写入和读取的数据是否一致。 + +硬件资源： + 1. CW32L011 StartKit + 2. 时钟HSI，默认频率4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + 3. LED2 + +演示说明： + 采用默认时钟配置，开启FLASH的操作时钟。对MCU内置OTP区写以及读取， + 然后对比写入和读取的数据是否相同。然后再此对同一地址的OTP进行写入操作， + 执行应不成功。执行完毕后，LED2闪烁。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/EWARM/project.ewp new file mode 100644 index 0000000..7a57085 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/EWARM/project.ewp @@ -0,0 +1,2246 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/MDK/flash_EraseWrite.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/MDK/flash_EraseWrite.uvoptx new file mode 100644 index 0000000..98bdf6f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/MDK/flash_EraseWrite.uvoptx @@ -0,0 +1,372 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + + + 0 + 0 + 149 + 1 +
1770
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\project\../USER/src/main.c\149 + + + + + 1 + 0 + 0xFE00 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\FLASH + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 7 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/MDK/flash_EraseWrite.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/MDK/flash_EraseWrite.uvprojx new file mode 100644 index 0000000..adf09b7 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/MDK/flash_EraseWrite.uvprojx @@ -0,0 +1,469 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/USER/inc/main.h new file mode 100644 index 0000000..b68cbe0 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/USER/inc/main.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/USER/src/main.c new file mode 100644 index 0000000..adf8779 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/USER/src/main.c @@ -0,0 +1,248 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "cw32l012_flash.h" +#include "cw32l012_gpio.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint8_t AddrBuf[256]; + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Main function of project + * //对PAGE127进行擦除，并验证。 + * //对PAGE127进行写入，并验证。 + * @return int32_t + */ + +int32_t main(void) +{ + uint8_t Flag, tmp8; + uint16_t i; + + //时钟初始化 + SYSCTRL_Configuration(); + + GPIO_InitTypeDef GPIO_InitStruct; + //PB09 推挽输出 + GPIO_InitStruct.Pins = GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + + PB09_SETHIGH(); //驱动LED1 + FirmwareDelay(2000000); //暂停 + + //erase + FLASH_UnlockPages(512*127, 512*127); //解锁127页 + Flag = FLASH_ErasePages(512*127, 512*127); //擦除最后一页面 + FLASH_LockAllPages(); + if( Flag ) + { + while(1); //擦除失败 + } + // blank check + for( i=0; i<512; i++ ) + { + tmp8 = *((volatile uint8_t *)( 512*127 + i )); + if( tmp8 != 0xFF ) + { + while(1); //对擦除后的结果进行验证失败 + } + } + //write + for( i=0; i<=255; i++ ) + { + AddrBuf[i] = i; + } + FLASH_UnlockPages( 512*127, 512*127 ); //解锁最后一个页面 + Flag = FLASH_WriteBytes(512*127, AddrBuf, 256 ); // 127页按字节写入 + if( Flag ) + { + while(1); //写入失败 + } + //read compare + for( i=0; i<=255; i++ ) + { + tmp8 = *((volatile uint8_t *)( 512*127 + i )); + if( tmp8 != i ) + { + while(1); //127页写入的数据进行验证失败 + } + } + for(i = 6; i; i--) + { + PB09_TOG(); + FirmwareDelay(50000); // PB09驱动LED2闪烁表示通过 + } + FirmwareDelay(2000000); //暂停 + // 半字写入 + FLASH_UnlockPages( 512*127, 512*127 ); //解锁127页面 + Flag = FLASH_ErasePages(512*127, 512*127); //擦除 + FLASH_LockAllPages(); + if( Flag ) + { + while(1); //擦除失败 + } + for( i=0; i<512; i++ ) + { + tmp8 = *((volatile uint8_t *)( 512*127 + i )); + if( tmp8 != 0xFF ) + { + while(1); //对擦除验证是否为空 + } + } + FLASH_UnlockPages( 512*127, 512*127 ); //解锁最后一页 + Flag = FLASH_WriteHalfWords(512*127, (uint16_t *)AddrBuf, 128); //127页按半字写入 + if( Flag ) + { + while(1); //写入失败 + } + //read + for( i=0; i<=255; i++ ) + { + tmp8 = *((volatile uint8_t *)( 512*127 + i )); + if( tmp8 != i ) + { + while(1); //第127页写入的数据进行验证失败 + } + } + for(i = 6; i; i--) + { + PB09_TOG(); + FirmwareDelay(50000); //闪烁表示通过 + } + FirmwareDelay(2000000); //暂停 + + // 字写入 + FLASH_UnlockPages( 512*127, 512*127 ); //解锁127页面 + Flag = FLASH_ErasePages(512*127, 512*127); //擦除 + FLASH_LockAllPages(); + if( Flag ) + { + while(1); //擦除失败 + } + for( i=0; i<512; i++ ) + { + tmp8 = *((volatile uint8_t *)( 512*127 + i )); + if( tmp8 != 0xFF ) + { + while(1); //对擦除后的结果进行验证失败 + } + } + FLASH_UnlockPages( 512*127, 512*127 ); //解锁最后一页面 + Flag = FLASH_WriteWords(512*127, (uint32_t *)AddrBuf, 64); //127页按字写入 + if( Flag ) + { + while(1); //写入失败 + } + //read + for( i=0; i<=255; i++ ) + { + tmp8 = *((volatile uint8_t *)( 512*127 + i )); + if( tmp8 != i ) + { + while(1); //127页写入的数据进行验证失败 + } + } + for(i = 6; i; i--) + { + + PB09_TOG(); + FirmwareDelay(50000); //闪烁表示通过 + } + FLASH_LockAllPages(); + + //结束 + while(1) + { + PB09_TOG(); + FirmwareDelay(1000000); + } + +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + REGBITS_SET(CW_SYSCTRL->AHBEN, (0x5A5A0000 |SYSCTRL_AHBEN_FLASH_Msk)); + REGBITS_SET(CW_SYSCTRL->AHBEN, (0x5A5A0000 |SYSCTRL_AHBEN_GPIOB_Msk)); +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/readme.txt new file mode 100644 index 0000000..665a6f0 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_EraseWrite/readme.txt @@ -0,0 +1,24 @@ +示例目的： + 对MCU内置的FLASH的最后一个页面（第127页）依次进行擦除/写/读操作，并对比写入和读取的数据是否一致。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟12分频，4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + +演示说明： + 采用默认时钟配置，开启FLASH的操作时钟。依次对MCU内置FLASH的最后一个页面（127页）进行擦除、写以及读取， + 然后对比写入和读取的数据是否相同。如果擦除、写、读取数据操作或者读写数据不一致则挂起，否则完成后会闪灯提示。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/EWARM/project.ewp new file mode 100644 index 0000000..613d524 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/EWARM/project.ewp @@ -0,0 +1,2258 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + $PROJ_DIR$\..\USER\src\EraseInRam.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/MDK/flash_FullChipErase.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/MDK/flash_FullChipErase.uvoptx new file mode 100644 index 0000000..705a125 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/MDK/flash_FullChipErase.uvoptx @@ -0,0 +1,468 @@ + + + + 1.0 + +
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+ 0 + 0 + 0 + 0 + 0 + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + \\Project\../../../../StartKit_Board/cw32l012_startkit.c\259 + + + + + 1 + 0 + 0x00 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\FLASH + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\USER\src\EraseInRam.c + EraseInRam.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 11 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/MDK/flash_FullChipErase.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/MDK/flash_FullChipErase.uvprojx new file mode 100644 index 0000000..ab7ab49 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/MDK/flash_FullChipErase.uvprojx @@ -0,0 +1,539 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\StartKit_Board + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + EraseInRam.c + 1 + ..\USER\src\EraseInRam.c + + + 2 + 9 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + + + Driver + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..a78faed --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,88 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void SYSCTRL_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void LPTIM_IRQHandler(void); +extern void CLKFAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/USER/inc/main.h new file mode 100644 index 0000000..a19bd68 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "system_cw32l012.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_flash.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/USER/src/EraseInRam.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/USER/src/EraseInRam.c new file mode 100644 index 0000000..942282b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/USER/src/EraseInRam.c @@ -0,0 +1,47 @@ +/** + * @file EraseInRam.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2022-7-12 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +#include "cw32l012.h" + +void EraseInRam(void) +{ + CW_SYSCTRL->AHBEN |= 0x5a5a0000 | SYSCTRL_AHBEN_FLASH_Msk; + + CW_FLASH->PAGELOCK = 0x5a5aFFFF; // 解除所有页的锁定 + + CW_FLASH->CR1 = 0x5a5a0003; // 片擦除 + + *((volatile uint32_t *)(0x00000000)) = 0; // 执行擦除 + + while(CW_FLASH->ISR_f.BUSY); + + while(1); // 擦除完毕，调试时可在此观察 + +} + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..2d8e7be --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/USER/src/interrupts_cw32l012.c @@ -0,0 +1,374 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" +#include "interrupts_cw32l012.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW32 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_cw32xxxx.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C + */ +void I2C_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/USER/src/main.c new file mode 100644 index 0000000..ca6926e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/USER/src/main.c @@ -0,0 +1,118 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2022-7-12 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +extern void EraseInRam(void); +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Main function of project + * 在ram中运行擦除全片 + * @return int32_t + */ + +int32_t main(void) +{ + uint16_t i; + + //时钟初始化 + SYSCTRL_Configuration(); + Bsp_Init(4000000); + + FirmwareDelay(500000); //暂停 + + i = 10; + while(i--) + { + Bsp_Led_Tog(&LED2); + FirmwareDelay(300000); + } + // 擦除 + EraseInRam(); +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + __SYSCTRL_FLASH_CLK_ENABLE(); +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/readme.txt new file mode 100644 index 0000000..cb802d2 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_FullChipErase/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 程序对FLASH的全片擦除 + +硬件资源： + 1. CW32L011 StartKit + 2. 时钟HSI，默认频率4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + 3. LED2 + +演示说明： + 演示如何下ram中运行程序，对FLASH进行全片擦除。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/EWARM/project.ewp new file mode 100644 index 0000000..3659620 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/EWARM/project.ewp @@ -0,0 +1,2255 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/MDK/flash_safety_lib_call.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/MDK/flash_safety_lib_call.uvoptx new file mode 100644 index 0000000..2eb9538 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/MDK/flash_safety_lib_call.uvoptx @@ -0,0 +1,402 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FN1 -FC1000 -FD20000000 -FF0FlashCW32L012_TEST -FL010000 -FS00 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + + 1 + 0 + 0xfc00 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\FLASH + 35905 + + + System Viewer\SYSCTRL + 35904 + + + + 1 + 1 + 0 + 2 + 1000000 + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/MDK/flash_safety_lib_call.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/MDK/flash_safety_lib_call.uvprojx new file mode 100644 index 0000000..5f98410 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/MDK/flash_safety_lib_call.uvprojx @@ -0,0 +1,483 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\StartKit_Board + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..a78faed --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,88 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void SYSCTRL_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void LPTIM_IRQHandler(void); +extern void CLKFAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/USER/inc/main.h new file mode 100644 index 0000000..e9f1b7b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "system_cw32l012.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_flash.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/USER/inc/slib.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/USER/inc/slib.h new file mode 100644 index 0000000..dc54ebc --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/USER/inc/slib.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : slib.h + * @brief : Header for slib.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SLIB_H +#define __SLIB_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l01x.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +#define SLIB_START_PAGE 0x7E +#define SLIB_END_PAGE 0x7F // 固定为0x7F +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void Slib_Led_Blink(uint32_t Cnt) __attribute__ ((section(".ARM.__at_0x0000FC00"))); +void Slib_Delay(uint32_t DlyCnt) __attribute__ ((section(".ARM.__at_0x0000FE00"))); + +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..2d8e7be --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/USER/src/interrupts_cw32l012.c @@ -0,0 +1,374 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" +#include "interrupts_cw32l012.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW32 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_cw32xxxx.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C + */ +void I2C_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/USER/src/main.c new file mode 100644 index 0000000..865aaa4 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/USER/src/main.c @@ -0,0 +1,113 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2022-7-12 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" + +#define Slib_Led_Blink ((void (*)(uint32_t))(0x0000FC00UL + 1)) + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Main function of project + * + * + * @return int32_t + */ + +int32_t main(void) +{ + Slib_Led_Blink(10); // 调用安全运行库区里的函数 + + while(1) + { + + } + +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + __SYSCTRL_FLASH_CLK_ENABLE(); +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/readme.txt new file mode 100644 index 0000000..3acf748 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_call/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 举例说明安全运行库的使用 + +硬件资源： + 1. CW32L011 StartKit + 2. 时钟HSI，默认频率4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + 3. LED2 + +演示说明： + 演示如何调用安全运行库区的函数 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/EWARM/project.ewp new file mode 100644 index 0000000..7df639b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/EWARM/project.ewp @@ -0,0 +1,2258 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + $PROJ_DIR$\..\USER\src\slib.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/MDK/flash_safety_lib_create.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/MDK/flash_safety_lib_create.uvoptx new file mode 100644 index 0000000..b330e8a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/MDK/flash_safety_lib_create.uvoptx @@ -0,0 +1,417 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FN1 -FC1000 -FD20000000 -FF0FlashCW32L012_TEST -FL010000 -FS00 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + + 0 + 1 + _passwords + + + + + 1 + 0 + 0x0 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\FLASH + 35905 + + + + 1 + 1 + 0 + 2 + 1000000 + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\USER\src\slib.c + slib.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 6 + 1 + 1 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 11 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/MDK/flash_safety_lib_create.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/MDK/flash_safety_lib_create.uvprojx new file mode 100644 index 0000000..75839fe --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/MDK/flash_safety_lib_create.uvprojx @@ -0,0 +1,488 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc;..\..\..\..\StartKit_Board + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + slib.c + 1 + ..\USER\src\slib.c + + + + + Driver + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..a78faed --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,88 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void SYSCTRL_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void LPTIM_IRQHandler(void); +extern void CLKFAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/inc/main.h new file mode 100644 index 0000000..e9f1b7b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "system_cw32l012.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_flash.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/inc/slib.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/inc/slib.h new file mode 100644 index 0000000..837bef4 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/inc/slib.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : slib.h + * @brief : Header for slib.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SLIB_H +#define __SLIB_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +#define SLIB_START_PAGE 0x7E +#define SLIB_END_PAGE 0x7F // 固定为0x7F +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void Slib_Led_Blink(uint32_t Cnt) __attribute__ ((section(".ARM.__at_0x0000FC00"))); +void Slib_Delay(uint32_t DlyCnt) __attribute__ ((section(".ARM.__at_0x0000FE00"))); + +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..2d8e7be --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/src/interrupts_cw32l012.c @@ -0,0 +1,374 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" +#include "interrupts_cw32l012.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW32 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_cw32xxxx.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1 + */ +void VC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2 + */ +void VC2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 + */ +void BTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C + */ +void I2C_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + + + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/src/main.c new file mode 100644 index 0000000..87c205c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/src/main.c @@ -0,0 +1,125 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2022-7-12 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "slib.h" + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +static uint8_t SlibKey[8] = {1,2,3,4,5,6,7,8}; //密码，用户自行设置 +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + * @brief Main function of project + * + * + * @return int32_t + */ +int32_t main(void) +{ + uint8_t ret; + + SYSCTRL_Configuration(); + ret = FLASH_SafetyLibraryEnable(SlibKey, SLIB_START_PAGE, SLIB_END_PAGE); + + if (ret) + { + // 开启安全区失败 + while(1); + } + + Slib_Led_Blink(10); + //结束 + while(1) + { + + } + +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + __SYSCTRL_FLASH_CLK_ENABLE(); + __SYSCTRL_CRC_CLK_ENABLE(); +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/src/slib.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/src/slib.c new file mode 100644 index 0000000..e590cd3 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/USER/src/slib.c @@ -0,0 +1,104 @@ +/** + * @file slib.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2022-7-12 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "slib.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#define LED2_PORT CW_GPIOB +#define LED2_PIN GPIO_PIN_8 +#define LED2_ON() PB08_SETHIGH() +#define LED2_OFF() PB08_SETLOW() +#define LED2_TOG() PB08_TOG() + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief LED闪烁 + * 不可调用安全区外的函数 + * @param Cnt: 闪烁次数 + * @return + */ +void Slib_Led_Blink(uint32_t Cnt) +{ + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + + LED2_PORT->ANALOG &= (~LED2_PIN); + LED2_PORT->DIR &= (~LED2_PIN); + LED2_PORT->ODR &= (~LED2_PIN); + + while(Cnt) + { + LED2_TOG(); + Slib_Delay(200000); + Cnt--; + } +} +/******************************************************************************* + * @brief Slib区函数，Delay函数 + * @param DlyCnt : Delay 的计数 + * @retval None + */ +void Slib_Delay(uint32_t DlyCnt) +{ + while(DlyCnt) + { + DlyCnt--; + } +} diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/readme.txt new file mode 100644 index 0000000..c3a15b7 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/FLASH/flash_safety_lib_create/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 举例说明安全运行库的使用 + +硬件资源： + 1. CW32L011 StartKit + 2. 时钟HSI，默认频率4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + 3. LED2 + +演示说明： + 演示如何创建安全运行库区。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/EWARM/project.ewp new file mode 100644 index 0000000..e6ddd21 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/EWARM/project.ewp @@ -0,0 +1,2246 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/MDK/Project.uvoptx new file mode 100644 index 0000000..31b3fc8 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/MDK/Project.uvoptx @@ -0,0 +1,341 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 7 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/MDK/Project.uvprojx new file mode 100644 index 0000000..9b7f5ba --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/MDK/Project.uvprojx @@ -0,0 +1,469 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/USER/inc/main.h new file mode 100644 index 0000000..1fdec5a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/USER/inc/main.h @@ -0,0 +1,64 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/USER/src/main.c new file mode 100644 index 0000000..792b539 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/USER/src/main.c @@ -0,0 +1,125 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define LED_GPIO_PORT CW_GPIOB +#define LED_GPIO_PINS GPIO_PIN_9 + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +void Delay(uint16_t nCount); +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ** + ******************************************************************************/ +int32_t main(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = LED_GPIO_PINS; + + GPIO_Init(LED_GPIO_PORT, &GPIO_InitStruct); + + while (1) + { + GPIO_TogglePin(LED_GPIO_PORT, LED_GPIO_PINS); + Delay(0xFFFF); + } +} + +/** +* @brief 简单延时 + * + * @param nCount + */ +void Delay(__IO uint16_t nCount) +{ + /* Decrement nCount value */ + while (nCount != 0) + { + nCount--; + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/readme.txt new file mode 100644 index 0000000..8fc448c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_blink/readme.txt @@ -0,0 +1,24 @@ +示例目的： + 演示GPIO的位翻转 + +硬件资源： + 1. CW32L012FxPx StarKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟12分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. PB09设置为PUSH-PULL输出，驱动LED1 + +演示说明： + LED1闪烁。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/EWARM/project.ewp new file mode 100644 index 0000000..0ab2b9f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/MDK/Project.uvoptx new file mode 100644 index 0000000..9a08e09 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/MDK/Project.uvoptx @@ -0,0 +1,359 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\GPIOA + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 1 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/MDK/Project.uvprojx new file mode 100644 index 0000000..fe0b998 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/MDK/Project.uvprojx @@ -0,0 +1,474 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/USER/inc/main.h new file mode 100644 index 0000000..5f6d13e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/USER/src/main.c new file mode 100644 index 0000000..8af506c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/USER/src/main.c @@ -0,0 +1,139 @@ + +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle GPIOA + ** + ******************************************************************************/ +int32_t main(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + __SYSCTRL_GPIOA_CLK_ENABLE(); //Open GPIOA Clk + __SYSCTRL_GPIOB_CLK_ENABLE(); //Open GPIOB Clk + + //set PB08 / PB09 as output + GPIO_InitStruct.Pins = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + + GPIO_Init( CW_GPIOB, &GPIO_InitStruct); + + // set PA00 as input + GPIO_InitStruct.Pins = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_Init( CW_GPIOA, &GPIO_InitStruct); + + + while (1) + { + //----------------------------------------------------------------------- + //以下调用函数法读写PIN + if ( GPIO_ReadPin(CW_GPIOA, GPIO_PIN_0 ) ) + { + GPIO_WritePin( CW_GPIOB, GPIO_PIN_8 | GPIO_PIN_9, GPIO_Pin_SET ); + } + else + { + GPIO_WritePin( CW_GPIOB, GPIO_PIN_8 | GPIO_PIN_9, GPIO_Pin_RESET ); + } + + //----------------------------------------------------------------------- + //以下采用宏定义读写PIN + if ( PA00_GETVALUE() ) + { + PB08_SETHIGH(); + PB09_TOG(); + } + else + { + PB08_SETLOW(); + } + } + +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/readme.txt new file mode 100644 index 0000000..063538a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_input_output/readme.txt @@ -0,0 +1,24 @@ +示例目的： + 演示GPIO通过库函数和宏定义的方法完整初始化配置和输入输出的读写操作 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟24分频，4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + 4. PB08 / PB09推挽输出，PA00上拉输入 + +演示说明： + 按下按键KEY1(PA00),观察 PB08 / PB09电平。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/EWARM/project.ewp new file mode 100644 index 0000000..0ab2b9f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/MDK/Project.uvoptx new file mode 100644 index 0000000..67f5a20 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/MDK/Project.uvoptx @@ -0,0 +1,359 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\GPIOA + 35905 + + + + + + + Startup + 0 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 1 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/MDK/Project.uvprojx new file mode 100644 index 0000000..fe0b998 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/MDK/Project.uvprojx @@ -0,0 +1,474 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/USER/inc/main.h new file mode 100644 index 0000000..5f6d13e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..426e00c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + GPIOA_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/USER/src/main.c new file mode 100644 index 0000000..30213f7 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/USER/src/main.c @@ -0,0 +1,126 @@ + +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define LED_GPIO_PORT CW_GPIOB +#define LED_GPIO_PINS GPIO_PIN_9 +#define KEY_GPIO_PORT CW_GPIOA +#define KEY_GPIO_PINS GPIO_PIN_0 +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * + * @return int32_t + */ +int32_t main(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + __SYSCTRL_GPIOA_CLK_ENABLE(); // 使能GPIO的配置时钟 + __SYSCTRL_GPIOB_CLK_ENABLE(); + + GPIO_InitStruct.IT = GPIO_IT_RISING | GPIO_IT_FALLING; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = KEY_GPIO_PINS; + + GPIO_Init(KEY_GPIO_PORT, &GPIO_InitStruct); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = LED_GPIO_PINS; + GPIO_Init(LED_GPIO_PORT, &GPIO_InitStruct); + + //清除KEY_GPIO_PINS中断标志并使能NVIC + KEY_GPIO_PORT->ICR &= ~KEY_GPIO_PINS; + NVIC_EnableIRQ(GPIOA_IRQn); + //---------------------------------------------------------------------- + //相关程序在中断函数GPIOA_IRQHandler中处理 + + + while (1) + { + + } +} + +void GPIOA_IRQHandlerCallBack(void) +{ + if ((KEY_GPIO_PORT->ISR & KEY_GPIO_PINS) != 0) + { + KEY_GPIO_PORT->ICR &= ~KEY_GPIO_PINS; + LED_GPIO_PORT->TOG |= LED_GPIO_PINS; + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/readme.txt new file mode 100644 index 0000000..37b9473 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_default/readme.txt @@ -0,0 +1,24 @@ +示例目的： + 演示GPIO的默认中断的使用 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟24分频，4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + 4. PA00（KEY1） 中断输入，PB09（LED1）输出 + +演示说明： + 按下KEY1，LED1的状态改变，松开KEY1， LED1的状态改变。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/EWARM/project.ewp new file mode 100644 index 0000000..0ab2b9f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/MDK/Project.uvoptx new file mode 100644 index 0000000..29224ed --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/MDK/Project.uvoptx @@ -0,0 +1,353 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0Flashcw32l012_TEST.FLM -FS00 -FL010000 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0Flashcw32l012_TEST.FLM -FS00 -FL010000 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012_TEST.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/MDK/Project.uvprojx new file mode 100644 index 0000000..b5036b1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/MDK/Project.uvprojx @@ -0,0 +1,483 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/USER/inc/main.h new file mode 100644 index 0000000..5f6d13e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..426e00c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + GPIOA_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/USER/src/main.c new file mode 100644 index 0000000..d23fa20 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/USER/src/main.c @@ -0,0 +1,128 @@ + +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define LED_GPIO_PORT CW_GPIOB +#define LED_GPIO_PINS GPIO_PIN_9 +#define KEY_GPIO_PORT CW_GPIOA +#define KEY_GPIO_PINS GPIO_PIN_0 +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * + * @return int32_t + */ +int32_t main(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + __SYSCTRL_GPIOA_CLK_ENABLE(); // 使能GPIO的配置时钟 + __SYSCTRL_GPIOB_CLK_ENABLE(); + + GPIO_InitStruct.IT = GPIO_IT_RISING | GPIO_IT_FALLING; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = KEY_GPIO_PINS; + + GPIO_Init(KEY_GPIO_PORT, &GPIO_InitStruct); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = LED_GPIO_PINS; + GPIO_Init(LED_GPIO_PORT, &GPIO_InitStruct); + //配置中断滤波 + GPIO_ConfigFilter(KEY_GPIO_PORT, KEY_GPIO_PINS, GPIO_FLTCLK_HCLK8); + //清除KEY_GPIO_PINS中断标志并使能NVIC + KEY_GPIO_PORT->ICR &= ~KEY_GPIO_PINS; + NVIC_EnableIRQ(GPIOA_IRQn); + //---------------------------------------------------------------------- + //相关程序在中断函数GPIOA_IRQHandler中处理 + + + while (1) + { + + } +} + +void GPIOA_IRQHandlerCallBack(void) +{ + if ((KEY_GPIO_PORT->ISR & KEY_GPIO_PINS) != 0) + { + KEY_GPIO_PORT->ICR &= ~KEY_GPIO_PINS; + LED_GPIO_PORT->TOG |= LED_GPIO_PINS; + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/readme.txt new file mode 100644 index 0000000..3c3c2fe --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_int_filter/readme.txt @@ -0,0 +1,24 @@ +示例目的： + 演示GPIO的中断滤波的使用 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟24分频，4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + 4. PA00（KEY1） 中断输入，PB09（LED1）输出 + +演示说明： + 按下KEY1，LED1的状态改变，松开KEY1， LED1的状态改变。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/EWARM/project.ewp new file mode 100644 index 0000000..328bfe5 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/MDK/Project.uvoptx new file mode 100644 index 0000000..30e0c3e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/MDK/Project.uvoptx @@ -0,0 +1,377 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + + + 0 + 0 + 79 + 1 +
914
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\project\../USER/src/main.c\79 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/MDK/Project.uvprojx new file mode 100644 index 0000000..ff12e46 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/MDK/Project.uvprojx @@ -0,0 +1,479 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/USER/inc/main.h new file mode 100644 index 0000000..5f6d13e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/USER/src/main.c new file mode 100644 index 0000000..fdefd10 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/USER/src/main.c @@ -0,0 +1,131 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** 将SWD端口配置成通用GPIO功能 + ** + ******************************************************************************/ +int32_t main(void) +{ + uint32_t tmp32; + + //================================================================================ + //复位后延时一段时间再将SWD接口变成GPIO，防止芯片被锁死 + InitTick(4000000); //SYSTICK 的工作频率为4MHz，每ms中断一次 + SysTickDelay(4000); //等待4s + + //================================================================================ + //Open GPIOA Clk + __SYSCTRL_GPIOA_CLK_ENABLE(); + //将PA13 / PA14配置成通用GPIO功能 + GPIO_SWD2GPIO(); + //配置 PA13 / PA14 为数字功能 - 输出 + REGBITS_CLR(CW_GPIOA->ANALOG, bv13 | bv14); + REGBITS_CLR(CW_GPIOA->DIR, bv13 | bv14); + + tmp32 = GetTick() + 10000; + while (GetTick() < tmp32) //在10秒内为GPIO功能 + { + PA13_SETHIGH(); + PA14_SETHIGH(); + PA13_SETLOW(); + PA14_SETLOW(); + + } + + //================================================================================ + //配置 PA13 / PA13 为UART1.RXD / UART1.TXD + REGBITS_CLR(CW_GPIOA->ANALOG, bv13 | bv14); //设置PA13/PA14为数字功能 + REGBITS_MODIFY(CW_GPIOA->DIR, bv13 | bv14, bv13); //设置PA13为输入，PA14为输出 + PA13_AFx_UART1RXD(); //配置PA13为UART1.RXD + PA14_AFx_UART1TXD(); //配置PA14为UART1.TXD + + //================================================================================ + + while (1) + { + ; + } + + //================================================================================ +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/readme.txt new file mode 100644 index 0000000..cf60e41 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_swd_io/readme.txt @@ -0,0 +1,25 @@ +示例目的： + 演示SWD端口配置为GPIO和UART端口功能。 + +硬件资源： + 1. CW32L012FxPx StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟24分频（默认），4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + 4. PA13和PA14 + +演示说明： + 程序上电2S后，PA13和PA14从默认的SWD功能切换为GPIO，PA13和PA14再电平翻转10秒 + 后，功能切换为UART1的RXD和TXD. + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/EWARM/project.ewp new file mode 100644 index 0000000..328bfe5 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/MDK/Project.uvoptx new file mode 100644 index 0000000..2e8f6a9 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/MDK/Project.uvoptx @@ -0,0 +1,365 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + CMSIS_AGDI + -X"CW-DAPLINK(CMSIS-DAP)" -U6713442356488877066CFF50 -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0Flashcw32l012_TEST.FLM -FS00 -FL010000 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012_TEST.FLM) + + + 0 + DLGUARM + + + + 0 + UL2CM3 + -U -O206 -S0 -C0 -P00 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0Flashcw32l012_TEST.FLM -FS00 -FL010000 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012_TEST.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/MDK/Project.uvprojx new file mode 100644 index 0000000..ded80be --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/MDK/Project.uvprojx @@ -0,0 +1,488 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/USER/inc/main.h new file mode 100644 index 0000000..5f6d13e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..426e00c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + GPIOA_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/USER/src/main.c new file mode 100644 index 0000000..e8ec11a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/USER/src/main.c @@ -0,0 +1,141 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define LED_GPIO_PORT CW_GPIOB +#define LED_GPIO_PINS GPIO_PIN_9 +#define KEY_GPIO_PORT CW_GPIOA +#define KEY_GPIO_PINS GPIO_PIN_0 +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ** + ******************************************************************************/ +int32_t main(void) +{ + uint16_t tmp; + + GPIO_InitTypeDef GPIO_InitStruct; + + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + + InitTick(4000000); + + GPIO_InitStruct.IT = GPIO_IT_FALLING; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_InitStruct.Pins = KEY_GPIO_PINS; + GPIO_Init(KEY_GPIO_PORT, &GPIO_InitStruct); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = LED_GPIO_PINS; + GPIO_Init(LED_GPIO_PORT, &GPIO_InitStruct); + + SYSCTRL_LSI_Enable(); // 使用LSI提供GPIO中断滤波的时钟 + GPIO_ConfigFilter(KEY_GPIO_PORT, KEY_GPIO_PINS, GPIO_FLTCLK_LSI); + + GPIO_WritePin(LED_GPIO_PORT, LED_GPIO_PINS, GPIO_Pin_SET); // LED1 turn on + + while (GPIO_ReadPin(KEY_GPIO_PORT, KEY_GPIO_PINS) == GPIO_Pin_SET); + GPIOA_INTFLAG_CLR(KEY_GPIO_PINS); + NVIC_EnableIRQ(GPIOA_IRQn); + GPIO_WritePin(LED_GPIO_PORT, LED_GPIO_PINS, GPIO_Pin_RESET); // LED1 turn off + tmp = 0x00; + while (1) + { + SYSCTRL_GotoDeepSleep(); + for(tmp = 0; tmp < 10; tmp++) + { + GPIO_TogglePin(LED_GPIO_PORT, LED_GPIO_PINS); + SysTickDelay(200); // 200ms延时 + } + } +} + +void GPIOA_IRQHandlerCallBack(void) +{ + if ((KEY_GPIO_PORT->ISR & KEY_GPIO_PINS) != 0) + { + KEY_GPIO_PORT->ICR &= ~KEY_GPIO_PINS; + } + + +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/readme.txt new file mode 100644 index 0000000..e11df31 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GPIO/gpio_wakeup_filter/readme.txt @@ -0,0 +1,24 @@ +示例目的： + 演示GPIO中断唤醒功能 + +硬件资源： + 1. CW32L012FxPx StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟24分频，4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + 4. PA00（KEY1） 中断输入，PB09（LED1）输出 + +演示说明： + 上电后，LED1亮，KEY1按下后，LED1闪烁5次后熄灭，系统进入休眠。再次按下KEY1，将系统从休眠中唤醒，LED1闪烁5次后熄灭，系统进入休眠. + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/EWARM/project.ewp new file mode 100644 index 0000000..2eea581 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gtim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/MDK/project.uvoptx new file mode 100644 index 0000000..edd792c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/MDK/project.uvoptx @@ -0,0 +1,384 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + -UV0010M9E -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0Flashcw32l012 -FS00 -FL010000 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + + 0 + 1 + Period + + + 1 + 1 + Width + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 1000000 + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 1 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gtim.c + cw32l012_gtim.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/MDK/project.uvprojx new file mode 100644 index 0000000..f0d3d6a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/MDK/project.uvprojx @@ -0,0 +1,488 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gtim.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/USER/inc/main.h new file mode 100644 index 0000000..10f06cc --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/USER/inc/main.h @@ -0,0 +1,74 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_gtim.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_flash.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..ffe285f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/USER/src/interrupts_cw32l012.c @@ -0,0 +1,438 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW32 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_cw32xxxx.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + GTIM1_IRQHandlerCallback(); + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/USER/src/main.c new file mode 100644 index 0000000..c41d4de --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/USER/src/main.c @@ -0,0 +1,211 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint32_t Period = 0, Width = 0 ; +uint8_t flagComplete = 0; +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void PWM_InputConfig(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief 使用GTIM1的CH1通道对PWM输入信号进行测量，同一通道输入信号被两路捕获寄存器进行捕获。 + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + Bsp_Init(96000000); + + /* GPIO Configuration */ + GPIO_Configuration(); + + PWM_InputConfig(); + + /* NVIC Configuration */ + NVIC_Configuration(); + + printf("Please connect the PWM signal to pin PA06.\r\n"); + + while (1) + { + if (flagComplete) + { + flagComplete = 0; + printf("The positive pulse width of the PWM signal is %.4fus, and the period is %.4fus.\r\n", Width/96.0, Period/96.0); + } + + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + /* 0. HSI使能并校准 */ + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV1); + + /* 1. 设置HCLK和PCLK的分频系数　*/ + SYSCTRL_HCLKPRS_Config(SYSCTRL_HCLK_DIV1); + SYSCTRL_PCLKPRS_Config(SYSCTRL_PCLK_DIV1); + + SYSCTRL_SystemCoreClockUpdate(96000000); + SYSCTRL_MCO_OUT(SYSCTRL_MCO_SRC_HCLK, SYSCTRL_MCO_DIV4096); //PA04输出23.4375KHz波形，模拟测试信号 +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + // PA06: GTIM1CH1 + __SYSCTRL_GPIOA_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_6 ; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + PA06_AFx_GTIM1CH1(); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(GTIM1_IRQn); + __enable_irq(); +} + +void PWM_InputConfig(void) +{ + GTIM_InitTypeDef GTIM_InitStruct = {0}; + GTIM_ICModeCfgTypeDef GTIM_ICModeCfgStruct = {0}; + GTIM_SlaverCfgTypeDef GTIM_SlaverCfgStruct = {0}; + __SYSCTRL_GTIM1_CLK_ENABLE(); + + GTIM_InitStruct.AlignMode = GTIM_ALIGN_MODE_EDGE; //边沿对齐 + GTIM_InitStruct.ARRBuffState = GTIM_ARR_BUFF_EN; //使能缓存寄存器 + GTIM_InitStruct.Direction = GTIM_DIRECTION_UP; //向上计数 + GTIM_InitStruct.EventOption = GTIM_EVENT_NORMAL; + GTIM_InitStruct.Prescaler = 0; // 1分频 + GTIM_InitStruct.PulseMode = GTIM_PULSE_MODE_DIS; + GTIM_InitStruct.ReloadValue = 0xFFFF; + GTIM_InitStruct.UpdateOption = GTIM_UPDATE_EN; + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + + GTIM_ICModeCfgStruct.ICMap = GTIM_IC1_MAP_TI1; //IC1 映射到 TI1 上 + GTIM_ICModeCfgStruct.ICPrescaler = GTIM_IC_PRESCALER_DIV1; + GTIM_ICModeCfgStruct.ICFilter = GTIM_IC_FILTER_PCLK_NONE ; + GTIM_ICModeCfgStruct.ICPolarity = GTIM_ICPolarity_Rising ; //检测 IC1 上升沿 + GTIM_IC1ModeCfg(CW_GTIM1, >IM_ICModeCfgStruct); + GTIM_IC1Cmd(CW_GTIM1, ENABLE); + + GTIM_ICModeCfgStruct.ICMap = GTIM_IC2_MAP_TI1; //IC2 映射到 TI1 上 + GTIM_ICModeCfgStruct.ICPrescaler = GTIM_IC_PRESCALER_DIV1; + GTIM_ICModeCfgStruct.ICFilter = GTIM_IC_FILTER_PCLK_NONE ; + GTIM_ICModeCfgStruct.ICPolarity = GTIM_ICPolarity_Falling; //检测 IC2下降沿 + GTIM_IC2ModeCfg(CW_GTIM1, >IM_ICModeCfgStruct); + GTIM_IC2Cmd(CW_GTIM1, ENABLE); + + GTIM_SlaverCfgStruct.SlaverMode = GTIM_SLAVER_MODE_RESET; //GTIM 工作于复位模式 + GTIM_SlaverCfgStruct.TrigInput = GTIM_TRIG_INPUT_TI1FP1; //TRGI 输入为 TI1FP1 + GTIM_SlaverModeCfg(CW_GTIM1, >IM_SlaverCfgStruct); + + GTIM_ITConfig(CW_GTIM1, GTIM_IT_CC1 | GTIM_IT_CC2 | GTIM_IT_UPDATA, ENABLE); + GTIM_Cmd(CW_GTIM1, ENABLE); +} + +void GTIM1_IRQHandlerCallback(void) +{ + /* USER CODE BEGIN */ + if (GTIM_GetITStatus(CW_GTIM1, GTIM_IT_UPDATA)) + { + GTIM_ClearITPendingBit(CW_GTIM1, GTIM_IT_UPDATA); + } + if (GTIM_GetITStatus(CW_GTIM1, GTIM_IT_CC1)) + { + Period = CW_GTIM1->CCR1; + GTIM_ClearITPendingBit(CW_GTIM1, GTIM_IT_CC1); + } + if (GTIM_GetITStatus(CW_GTIM1, GTIM_IT_CC2)) + { + Width = CW_GTIM1->CCR2; + GTIM_ClearITPendingBit(CW_GTIM1, GTIM_IT_CC2); + flagComplete = 1; + } + /* USER CODE END */ +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/readme.txt new file mode 100644 index 0000000..8713c13 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_input/readme.txt @@ -0,0 +1,30 @@ +示例目的： + 演示GTIM的PWM输入捕获功能 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI，1分频，96MHz，PCLK、HCLK不分频， + PCLK=HCLK=SysClk=96MHz + 4. GTIM1的分频系数1，以96MHz的频率计数，ARR设置最大0xFFFF，将CH1映射到IC1和IC2上， + IC1上升沿捕获，IC2下降沿捕获 + 5. PA06配置为GTIM1的CH1输入通道。 + 6. 板载串口 115200bps + 7. PA04输出HCLK/64，模拟测试信号 + +演示说明： + 将PWM输入信号引入到PA06上。使用GTIM1的CH1单个通道对PWM输入信号进行测量,CCR1寄存器测量周期， + CCR2寄存器测量脉宽。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/EWARM/project.ewp new file mode 100644 index 0000000..2eea581 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gtim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/MDK/project.uvoptx new file mode 100644 index 0000000..c4c649f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/MDK/project.uvoptx @@ -0,0 +1,375 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + CW32L012F8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x01000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012F8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012F8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012F8$SVD\CW32L012.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gtim.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/USER/inc/main.h new file mode 100644 index 0000000..10f06cc --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/USER/inc/main.h @@ -0,0 +1,74 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_gtim.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_flash.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/USER/src/main.c new file mode 100644 index 0000000..9339dc7 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/USER/src/main.c @@ -0,0 +1,180 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint32_t Period = 500; // 周期，单位us +uint32_t PosWidth = 0; // 正脉宽，单位us +uint8_t Dir = 1; // 计数方向 1增加 0 减少 +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void PWM_OutputConfig(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief GTIM1计数，CH3通道比较，PB06做PWM输出 + * + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + /* GPIO Configuration */ + GPIO_Configuration(); + + PWM_OutputConfig(); + + /* NVIC Configuration */ + NVIC_Configuration(); + + while (1) + { + + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + /* 0. HSI使能并校准 */ + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV24); + + /* 1. 设置HCLK和PCLK的分频系数　*/ + SYSCTRL_HCLKPRS_Config(SYSCTRL_HCLK_DIV1); + SYSCTRL_PCLKPRS_Config(SYSCTRL_PCLK_DIV1); + + SYSCTRL_SystemCoreClockUpdate(4000000); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + /* PB6 作为GTIM1的CH3 PWM 输出 */ + __SYSCTRL_GPIOB_CLK_ENABLE(); + + PB06_DIGTAL_ENABLE(); + PB06_DIR_OUTPUT(); + PB06_PUSHPULL_ENABLE(); + PB06_AFx_GTIM1CH3(); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(GTIM1_IRQn); + __enable_irq(); +} + +void PWM_OutputConfig(void) +{ + GTIM_InitTypeDef GTIM_InitStruct = {0}; + GTIM_OCModeCfgTypeDef GTIM_OCModeCfgStruct = {DISABLE, DISABLE, 0}; + + __SYSCTRL_GTIM1_CLK_ENABLE(); + + GTIM_InitStruct.AlignMode = GTIM_ALIGN_MODE_EDGE; + GTIM_InitStruct.ARRBuffState = GTIM_ARR_BUFF_EN; + GTIM_InitStruct.Direction = GTIM_DIRECTION_UP; + GTIM_InitStruct.EventOption = GTIM_EVENT_NORMAL; + GTIM_InitStruct.Prescaler = 4 - 1; + GTIM_InitStruct.PulseMode = GTIM_PULSE_MODE_DIS; + GTIM_InitStruct.ReloadValue = 1000 - 1; + GTIM_InitStruct.UpdateOption = GTIM_UPDATE_DIS; + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + + + GTIM_OCModeCfgStruct.FastMode = DISABLE; + GTIM_OCModeCfgStruct.OCMode = GTIM_OC_MODE_PWM1; + GTIM_OCModeCfgStruct.OCPolarity = GTIM_OC_POLAR_NONINVERT; + GTIM_OCModeCfgStruct.PreloadState = DISABLE; + GTIM_OC3ModeCfg(CW_GTIM1, >IM_OCModeCfgStruct); + + GTIM_SetCompare3(CW_GTIM1, 250); + GTIM_OC3Cmd(CW_GTIM1, ENABLE); + GTIM_Cmd(CW_GTIM1, ENABLE); +} + +void GTIM1_IRQHandlerCallBack(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/readme.txt new file mode 100644 index 0000000..6ca5f40 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_pwm_output/readme.txt @@ -0,0 +1,26 @@ +示例目的： + 演示GTIM的PWM输出功能 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI，24分频，4MHz，PCLK、HCLK不分频， + PCLK=HCLK=SysClk=4MHz + 4. GTIM1的分频系数4-1，ARR设置1000-1，CCR3为250 + 5. 设置PB06为GTIM1的CH3通道 + +演示说明： + 程序运行后,PB06输出周期为1ms， 正脉宽为250us的方波 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/EWARM/project.ewp new file mode 100644 index 0000000..2eea581 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gtim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/MDK/project.uvoptx new file mode 100644 index 0000000..8c7b67b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/MDK/project.uvoptx @@ -0,0 +1,365 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 1 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gtim.c + cw32l012_gtim.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/MDK/project.uvprojx new file mode 100644 index 0000000..c5e78af --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/MDK/project.uvprojx @@ -0,0 +1,479 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gtim.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/USER/inc/main.h new file mode 100644 index 0000000..a2b6bbe --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/USER/inc/main.h @@ -0,0 +1,75 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_gtim.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_btim.h" +#include "cw32l012_flash.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/USER/src/main.c new file mode 100644 index 0000000..a0a0b86 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/USER/src/main.c @@ -0,0 +1,155 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief GTIM1计数溢出后，使PB08输出翻转 + * @return int32_t + */ +int32_t main(void) +{ + GTIM_InitTypeDef GTIM_InitStruct = {0}; + + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + /* GPIO Configuration */ + GPIO_Configuration(); + + /* NVIC Configuration */ + NVIC_Configuration(); + + GTIM_InitStruct.AlignMode = GTIM_ALIGN_MODE_EDGE; + GTIM_InitStruct.ARRBuffState = GTIM_ARR_BUFF_EN; + GTIM_InitStruct.Direction = GTIM_DIRECTION_UP; + GTIM_InitStruct.EventOption = GTIM_EVENT_NORMAL; + GTIM_InitStruct.Prescaler = 1000 - 1; + GTIM_InitStruct.PulseMode = GTIM_PULSE_MODE_DIS; + GTIM_InitStruct.ReloadValue = 200 - 1; + GTIM_InitStruct.UpdateOption = GTIM_UPDATE_EN; + + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + GTIM_Cmd(CW_GTIM1, ENABLE); + + while (1) + { + if (GTIM_GetITStatus(CW_GTIM1, GTIM_IT_UPDATA)) + { + GTIM_ClearITPendingBit(CW_GTIM1, GTIM_IT_UPDATA); + PB08_TOG(); + } + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + __SYSCTRL_GTIM1_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + __SYSCTRL_FLASH_CLK_ENABLE(); + + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI4MHZ); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_8; + + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + + /* PB08 输出 */ + PB08_SETLOW(); + +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + /* __disable_irq(); + NVIC_EnableIRQ(GTIM1_IRQn); + __enable_irq(); */ +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/readme.txt new file mode 100644 index 0000000..cbbf82c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/GTIM/gtim_timer/readme.txt @@ -0,0 +1,26 @@ +示例目的： + 演示GTIM的定时器功能 + +硬件资源： + 1. CW32L012FxPx StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI，24分频，96MHz/24=4MHz，PCLK、HCLK不分频， + PCLK=HCLK=SysClk=4MHz + 4. GTIM1的分频系数1000-1，ARR设置200-1，则GTIM1每50ms溢出一次 + 5. 设置PB08为PUSH-PULL输出,驱动LED2 + +演示说明： + 程序运后,PB08每50ms翻转一次，驱动LED2以10HZ的频率闪烁 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/EWARM/project.ewp new file mode 100644 index 0000000..a0e18cb --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_halltim.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/MDK/Project.uvoptx new file mode 100644 index 0000000..b5ba8dd --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/MDK/Project.uvoptx @@ -0,0 +1,437 @@ + + + + 1.0 + +
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### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_halltim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_halltim.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Project + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/USER/inc/main.h new file mode 100644 index 0000000..1341c24 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/USER/inc/main.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "cw32l012_opa.h" +#include "cw32l012_adc.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/USER/src/main.c new file mode 100644 index 0000000..2a12dc8 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/USER/src/main.c @@ -0,0 +1,179 @@ +/** + ****************************************************************************** + * @file main.c + * @author AE Team + * @version 1.0 + * @date 2024-08-15 + * @brief + * + * @note 硬件平台：CW32L012_StartKit_V1.0 + * + * + *****************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" +#include "cw32l012_halltim.h" +#include "cw32l012_btim.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ** + ******************************************************************************/ +char RamBuf[100] __attribute__((at(0x20000200))); + + +int main(void) +{ + HALLTIM_InitTypeDef HALLTIM_InitStruct; + GPIO_InitTypeDef GPIO_InitStruct; + + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + + PA03_AFx_HALLTIMCH1(); + PA04_AFx_HALLTIMCH2(); + PA05_AFx_HALLTIMCH3(); + PB00_AFx_HALLTIMOUT(); + PB01_AFx_HALLTIMTRGO(); + + GPIO_InitStruct.Pins = GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pins = GPIO_PIN_0 | GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + + HALLTIM_InitStruct.filter_enable = TRUE; + HALLTIM_InitStruct.auto_reload_value = 9999; // 设置自动重装载值为10000-1 + HALLTIM_InitStruct.filter_length = 10; // 设置滤波宽度为10个时钟周期 + HALLTIM_InitStruct.clock_division = HALLTIM_DIV_PCLK_DIV4; // 设置时钟分频为PCLK/4 + HALLTIM_InitStruct.trigger_output = HALLTIM_MMS_MATCH; // 设置触发输出模式为CCR匹配脉冲 + + // 初始化HALLTIM模块 + HALLTIM_Init(&HALLTIM_InitStruct); + + // 设置比较值为500 + HALLTIM_SetCompareValue(5000); + + // 清除所有状态标志 + HALLTIM_ClearStatus(HALLTIM_ISR_MATCH | HALLTIM_ISR_OV | HALLTIM_ISR_CHG); + + // 启用HALLTIM模块 + HALLTIM_Cmd(ENABLE); + + // 生成软件触发信号 + HALLTIM_GenerateSoftTrigger(); + + // 等待一段时间，让HALLTIM模块运行 + for (volatile int i = 0; i < 1000000; i++); + + // 获取计数值 + uint32_t counter_value = HALLTIM_GetCounterValue(); + sprintf(RamBuf,"counter_value:%u\n", counter_value); + + // 获取脉冲宽度 + uint32_t pulse_width = HALLTIM_GetPulseWidth(); + sprintf(&RamBuf[25],"pulse_width:%u\n", pulse_width); + + // 获取未滤波的HALL信号状态 + uint32_t raw_state = HALLTIM_GetRawStateCH1(); + sprintf(&RamBuf[50],"raw_state_ch1:0x%X\n", raw_state); + + raw_state = HALLTIM_GetRawStateCH2(); + sprintf(&RamBuf[50],"raw_state_ch2:0x%X\n", raw_state); + + raw_state = HALLTIM_GetRawStateCH3(); + sprintf(&RamBuf[50],"raw_state_ch3:0x%X\n", raw_state); + + // 获取滤波后的HALL信号状态 + uint32_t filtered_state = HALLTIM_GetFilteredStateCH1(); + sprintf(&RamBuf[70],"filtered_state_ch1:0x%X\n", filtered_state); + + filtered_state = HALLTIM_GetFilteredStateCH2(); + sprintf(&RamBuf[70],"filtered_state_ch2:0x%X\n", filtered_state); + + filtered_state = HALLTIM_GetFilteredStateCH3(); + sprintf(&RamBuf[70],"filtered_state_ch3:0x%X\n", filtered_state); + + // 清除所有状态标志 + HALLTIM_ClearStatus(HALLTIM_ISR_MATCH | HALLTIM_ISR_OV | HALLTIM_ISR_CHG); + + while(1) + { + + } + +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/readme.txt new file mode 100644 index 0000000..4f4c814 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/HALLTIM/HALLTIM_Poll/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 演示HALL定时器功能 + +硬件资源： + 1. CW32L012FxPx StartKit + 2. 时钟HSI + 3. 系统工作频率位HSI默认分频24分频，96MHz/24=4MHz，PCLK、HCLK不分频， + PCLK=HCLK=SysClk=4MHz + 4. HILLTIM的ARR设置10000-1，则HILLTIM能测量最长9999个PCLK时钟周期的输入脉宽 + 5. PA03、04、05作为HILLTIM的输入 + 6. PB00作为HILLTIM的输出 + 7. PB01作为HILLTIM的TRGO输出 + +演示说明： + 将霍尔传感器接入到PA03、04、05，程序运行后可测量三个输入信号之间变化沿之间的间隔。 + 同时PB00输出占空比位50%的PWM的波， PB01输出比较匹配时刻。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/EWARM/I2C_cw24c02_Int.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/EWARM/I2C_cw24c02_Int.ewp new file mode 100644 index 0000000..2ed5635 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/EWARM/I2C_cw24c02_Int.ewp @@ -0,0 +1,2278 @@ + + + + 2 + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gtim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_iwdt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_lpi2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_lvd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_opa.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_pwr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_ram.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_vc.c + + + + Startup + + $PROJ_DIR$\..\..\..\..\IDEsupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + $PROJ_DIR$\..\USER\src\main.c + + + Release + + ICCARM + + 31 + 0 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/EWARM/I2C_cw24c02_Int.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/EWARM/I2C_cw24c02_Int.eww new file mode 100644 index 0000000..1a492a0 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/EWARM/I2C_cw24c02_Int.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\I2C_cw24c02_Int.ewp + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/MDK/I2C_cw24c02_Int.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/MDK/I2C_cw24c02_Int.uvoptx new file mode 100644 index 0000000..2b99c0e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/MDK/I2C_cw24c02_Int.uvoptx @@ -0,0 +1,387 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + I2C_cw24c02_Int + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U56FF71065178565626600287 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=1071,21,1482,523,0)(1007=812,90,1019,311,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC2000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC2000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + + + + 0 + 1 + masterHandle + + + 1 + 1 + s_lpi2cMasterHandle + + + + + 1 + 0 + iState + 0 + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_lpi2c.c + cw32l012_lpi2c.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_ram.c + cw32l012_ram.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/MDK/I2C_cw24c02_Int.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/MDK/I2C_cw24c02_Int.uvprojx new file mode 100644 index 0000000..0975232 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/MDK/I2C_cw24c02_Int.uvprojx @@ -0,0 +1,471 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + I2C_cw24c02_Int + 0x4 + ARM-ADS + :::: + 1 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012 -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + I2C_cw24c02_Int + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_lpi2c.c + 1 + ..\..\..\..\Libraries\src\cw32l012_lpi2c.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_ram.c + 1 + ..\..\..\..\Libraries\src\cw32l012_ram.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..15c90dc --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,88 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void SYSCTRL_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void LPTIM_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void CLKFAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/USER/inc/main.h new file mode 100644 index 0000000..e99a479 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/USER/inc/main.h @@ -0,0 +1,86 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012.h" +#include "system_cw32l012.h" +#include "interrupts_cw32l012.h" +#include "base_types.h" + +#include "cw32l012_lpi2c.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_flash.h" +#include "cw32l012_ram.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +static void I2C_Stop_SW(void); +void I2C_ExceptionHandling(void); +//... +void LPI2C_MasterReceiveIT(void); +void LPI2C_MasterTransferIT(void); +//... + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..046957e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupts_cw32l012.h" +#include "..\inc\main.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH12 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH34 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC13 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC24 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM34 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3_HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + LPI2C_CommonIRQHandler(CW_I2C1, 1U); + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI23 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2_DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/USER/src/main.c new file mode 100644 index 0000000..f5a3ff3 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/USER/src/main.c @@ -0,0 +1,345 @@ +/** +* @file main.c +* @author WHXY +* @brief +* @version 0.1 +* @date 2022-7-12 +* +* @copyright Copyright (c) 2021 +* +*/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +#include "..\inc\main.h" + +#define HSI48MHZ_EN + +#ifndef HSI48MHZ_EN +#define HSI8MHZ_EN +#endif + +//#define BAUD_RATE_100K_EN + +#define I2C1_SCL_GPIO_PORT CW_GPIOB +#define I2C1_SCL_GPIO_PIN GPIO_PIN_6 +#define I2C1_SDA_GPIO_PORT CW_GPIOB +#define I2C1_SDA_GPIO_PIN GPIO_PIN_7 + +#define I2C1_SCL_LOW() PB06_SETLOW() +#define I2C1_SDA_LOW() PB07_SETLOW() +#define I2C1_SCL_HIGH() PB06_SETHIGH() +#define I2C1_SDA_HIGH() PB07_SETHIGH() + +#define I2C1_SCL2GPIO() PB06_AFx_GPIO() +#define I2C1_SDA2GPIO() PB07_AFx_GPIO() +#define GPIO2I2C1_SCL() PB06_AFx_I2C1SCL() +#define GPIO2I2C1_SDA() PB07_AFx_I2C1SDA() + +// EEPROM内部地址 +#define START_ADDR_EE 0 // 写入或者读取的EEPROM的地址 +#define BUFFER_SIZE 8 +#define TEST_CNT 16 // 写读次数 + +uint8_t g_TxBuffer[BUFFER_SIZE] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37}; +uint8_t g_RxBuffer[BUFFER_SIZE]; +lpi2c_master_handle_t masterHandle = {0}; +lpi2c_master_transfer_t masterXfer = {0}; +uint8_t u8StateMathine; +volatile boolean_t g_TransferDone = FALSE; + + +void LPI2C_MasterIRQHandler(void) +{ + LPI2C_MasterTransferHandleIRQ(CW_I2C1, &masterHandle); +} + +void LPI2C_MasterCallback(I2C_TypeDef *I2Cx, lpi2c_master_handle_t *handle, status_t status, void *userData) +{ + if (kStatus_Success == status) + { + g_TransferDone = TRUE; + } + else + { + // 错误处理 + } +} + +void LPI2C_MasterInit(void) +{ + I2C_MasterConfigTypeDef I2C_InitStruct; + + I2C_MasterDeinit(CW_I2C1); + + // I2C default values + I2C_MasterInitDefault(&I2C_InitStruct); +#ifdef BAUD_RATE_100K_EN + I2C_InitStruct.I2C_BaudRate_Hz = 100000UL; +#endif + + // 初始化模块 +#ifdef HSI48MHZ_EN + I2C_MasterInit(CW_I2C1, &I2C_InitStruct, 48000000UL); +#elif defined (HSI8MHZ_EN) + I2C_MasterInit(CW_I2C1, &I2C_InitStruct, 8000000UL); +#else +#endif + +} + +void LPI2C_MasterTransferIT(void) +{ + u8StateMathine = kIdleState; + + masterXfer.data = &g_TxBuffer[0]; + masterXfer.dataSize = BUFFER_SIZE; + masterXfer.direction = I2C_MODE_WRITE; + masterXfer.flags = kLPI2C_TransferDefaultFlag; + masterXfer.slaveAddress = I2C_SLAVEADDRESS_EEPROM; + masterXfer.subaddress = START_ADDR_EE; + masterXfer.subaddressSize = 1; + + masterHandle.state = kIdleState; + masterHandle.remainingBytes = BUFFER_SIZE; + masterHandle.buf = &u8StateMathine; + masterHandle.userData = NULL; + masterHandle.commandBuffer[0] = (I2C_SLAVEADDRESS_EEPROM << 1) | I2C_MODE_WRITE; + masterHandle.commandBuffer[1] = START_ADDR_EE; + masterHandle.commandBuffer[2] = NULL; + masterHandle.commandBuffer[3] = NULL; + masterHandle.commandBuffer[4] = NULL; + masterHandle.commandBuffer[5] = NULL; + masterHandle.completionCallback = LPI2C_MasterCallback; + masterHandle.transfer = masterXfer; + + LPI2C_MasterTransferCreateHandle(CW_I2C1, &masterHandle, LPI2C_MasterCallback, NULL); + LPI2C_MasterTransferNonBlocking(CW_I2C1, &masterHandle, &masterXfer); +} + +void LPI2C_MasterReceiveIT(void) +{ + u8StateMathine = kIdleState; + + masterXfer.data = &g_RxBuffer[0]; + masterXfer.dataSize = BUFFER_SIZE; + masterXfer.direction = I2C_MODE_READ; + masterXfer.flags = kLPI2C_TransferDefaultFlag; + masterXfer.slaveAddress = I2C_SLAVEADDRESS_EEPROM; + masterXfer.subaddress = START_ADDR_EE; + masterXfer.subaddressSize = 1; + + masterHandle.state = kIdleState; + masterHandle.remainingBytes = BUFFER_SIZE; + masterHandle.buf = &u8StateMathine; + masterHandle.userData = NULL; + masterHandle.commandBuffer[0] = (I2C_SLAVEADDRESS_EEPROM << 1) | I2C_MODE_WRITE; + masterHandle.commandBuffer[1] = START_ADDR_EE; + masterHandle.commandBuffer[2] = NULL; + masterHandle.commandBuffer[3] = NULL; + masterHandle.commandBuffer[4] = NULL; + masterHandle.commandBuffer[5] = NULL; + masterHandle.completionCallback = LPI2C_MasterCallback; + masterHandle.transfer = masterXfer; + + LPI2C_MasterTransferCreateHandle(CW_I2C1, &masterHandle, LPI2C_MasterCallback, NULL); + LPI2C_MasterTransferNonBlocking(CW_I2C1, &masterHandle, &masterXfer); +} + +/** +* @brief main函数 +* +* 本函数实现了I2C通信的初始化及数据读写操作。 +* +* @return int32_t 返回0表示程序正常结束 +*/ +int32_t main(void) +{ + uint16_t tempCnt = 0; + + // 时钟初始化 + SYSCTRL_Configuration(); + + // IO口初始化 + GPIO_Configuration(); + + // I2C主设备初始化 + LPI2C_MasterInit(); + + // 中断设置 + NVIC_Configuration(); + I2C_MasterCmd(CW_I2C1, ENABLE); // I2C模块使能 + if (I2C_MasterPollingFlag(CW_I2C1, I2C_IT_BUSBUSY) == I2C_Status_Success) + { + I2C_ExceptionHandling(); + } + + while (1) + { + LPI2C_MasterTransferIT(); // I2C数据写操作 + while (!g_TransferDone) + { + ; + } + // Data transfer is ok, then read eeprom data. +#ifdef HSI48MHZ_EN + FirmwareDelay(30000); //@48MHz +#else + FirmwareDelay(5000); //@8MHz +#endif + + g_TransferDone = 0; + LPI2C_MasterReceiveIT(); // I2C数据读操作 + while (!g_TransferDone) + { + ; + } + // 检查Write/Read数据一致性 + if (0 == memcmp(g_TxBuffer, g_RxBuffer, BUFFER_SIZE)) + { + // LED1亮:PASSED + PB09_SETHIGH(); + } + else + { + // LED1灭:FAILED + PB09_SETLOW(); + } + + ++tempCnt; + for (uint8_t i = 0; i < 8; ++i) + { + g_TxBuffer[i] = tempCnt + i; + } + if (tempCnt >= TEST_CNT) + { + break; + } + +#ifdef HSI48MHZ_EN + FirmwareDelay(30000); //@48MHz +#else + FirmwareDelay(5000); //@8MHz +#endif + } + + while (1) + { + } +} + +/** +* @brief Configures the different system clocks. +* @param None +* @retval None +*/ +void SYSCTRL_Configuration(void) +{ +#ifndef HSI48MHZ_EN + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); // 8MHz +#else + __SYSCTRL_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_2); + CW_FLASH->CR2 |= (0x5A5A0000 | 0x18); //Enable FLASH Prefetch and Cache. + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV2); // 48MHz + __SYSCTRL_FLASH_CLK_DISABLE(); +#endif + __SYSCTRL_I2C1_CLK_ENABLE(); +} + +/** +* @brief Configure the GPIO Pins. +* @param None +* @retval None +*/ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + + __SYSCTRL_GPIOB_CLK_ENABLE(); + + GPIO2I2C1_SCL(); + GPIO2I2C1_SDA(); + GPIO_InitStructure.Pins = I2C1_SCL_GPIO_PIN | I2C1_SDA_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_Init(I2C1_SCL_GPIO_PORT, &GPIO_InitStructure); + + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_9; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + + //LED灭 + PB09_SETLOW(); +} + +static void I2C_Stop_SW(void) +{ + I2C1_SCL_LOW(); // SCL = 0 + I2C1_SDA_LOW(); // SDA = 0 + FirmwareDelay(4); // delay 4us@8MHz + I2C1_SCL_HIGH(); // SCL = 1 + FirmwareDelay(4); // delay 4us@8MHz + I2C1_SDA_HIGH(); // SDA = 1 +} + +void I2C_ExceptionHandling(void) +{ + I2C1_SCL2GPIO(); + I2C1_SDA2GPIO(); + I2C_Stop_SW(); + FirmwareDelay(1000); // delay 1ms@8MHz + GPIO2I2C1_SCL(); + GPIO2I2C1_SDA(); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_SetPriority(I2C1_IRQn, 3); //Lowest priority + NVIC_ClearPendingIRQ(I2C1_IRQn); + NVIC_EnableIRQ(I2C1_IRQn); + __enable_irq(); +} + + + +/****************************************************************************** +* EOF (not truncated) +******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** +* @brief Reports the name of the source file and the source line number +* where the assert_param error has occurred. +* @param file: pointer to the source file name +* @param line: assert_param error line source number +* @retval None +*/ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + __NOP(); + while(1); + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/readme.txt new file mode 100644 index 0000000..aff8c70 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_Int/readme.txt @@ -0,0 +1,32 @@ +示例目的： + 利用I2C接口，采用中断方式读写EEPROM芯片（CW24C02）。 + +硬件资源： + 1. CW32L012C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟2分频，48MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=48MHz + 4. PB09(LED1)设置为PUSH-PULL输出 + +演示说明： + 1、初始化MCU I2C为主机接口，400KHz，使能I2C中断。提示：可以通过宏定义，支持8MHz HSI主频和100kHz I2C通信速率。 + 2、I2C写时序：根据CW24C02手册，采用页写模式：依次发送START信号、SLA+W字节、目标地址字节、以及最多8字节（受CW24C02每页8字节限制）数据，最后发送STOP信号。 + 3、I2C读时序：根据CW24C02手册，采用顺序读模式：先通过字节写模式完成SLA+W字节以及目标地址发送，然后发送重复START信号、SLA+R， + 并根据需要读取的字节数产生对应字节的时钟信号，最后发送STOP信号。 + 4、数据写、读传输完成后，比较发送/接收数组，如果数据一致，则LED1亮，否则LED1灭。 + 5、注意实际测试时需要更改I2C/GPIO口线、时钟配置以及GPIO配置都需要修改。 + 6、注意由于EEPROM器件限制，在写入数据之后，需要加入一定的等待延时(5ms)，以等待EEPROM实际的写操作完成。 + 7、I2C从机设备地址目前统一在cw32l012_lpi2c.h文件中进行定义，必要时请自行修改。 + +使用说明： ++ EWARM + 1. 打开I2C_cw24c02_Int.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开I2C_cw24c02_Int.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/EWARM/I2C_cw24c02_poll.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/EWARM/I2C_cw24c02_poll.ewp new file mode 100644 index 0000000..1cfecdf --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/EWARM/I2C_cw24c02_poll.ewp @@ -0,0 +1,2278 @@ + + + + 2 + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_btim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_crc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_debug.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_digitalsign.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_eau.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gtim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_iwdt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_lpi2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_lvd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_opa.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_pwr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_ram.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_spi.c + 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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + I2C_cw24c02_poll + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U56FF71065178565626600287 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=359,202,770,704,0)(1007=1364,244,1571,465,0)(1008=820,299,1196,535,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC2000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC2000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + + + + 0 + 1 + u8RecData + + + + + 1 + 0 + iState + 0 + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_lpi2c.c + cw32l012_lpi2c.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/MDK/I2C_cw24c02_poll.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/MDK/I2C_cw24c02_poll.uvprojx new file mode 100644 index 0000000..1585adf --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/MDK/I2C_cw24c02_poll.uvprojx @@ -0,0 +1,466 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + I2C_cw24c02_poll + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012 -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + I2C_cw24c02_poll + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_lpi2c.c + 1 + ..\..\..\..\Libraries\src\cw32l012_lpi2c.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..15c90dc --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,88 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void SYSCTRL_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void LPTIM_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void CLKFAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/USER/inc/main.h new file mode 100644 index 0000000..eb76ec1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/USER/inc/main.h @@ -0,0 +1,81 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012.h" +#include "system_cw32l012.h" +#include "interrupts_cw32l012.h" +#include "base_types.h" + +#include "cw32l012_lpi2c.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_flash.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +static void I2C_Stop_SW(void); +void I2C_ExceptionHandling(void); +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..12be925 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupts_cw32l012.h" +#include "..\inc\main.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH12 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH34 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC13 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC24 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM34 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3_HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI23 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2_DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/USER/src/main.c new file mode 100644 index 0000000..b88ab37 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/USER/src/main.c @@ -0,0 +1,221 @@ +/** +* @file main.c +* @author WHXY +* @brief +* @version 0.1 +* @date 2022-7-12 +* +* @copyright Copyright (c) 2021 +* +*/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +#include "..\inc\main.h" + +#define HSI48MHZ_EN + +#ifndef HSI48MHZ_EN +#define HSI8MHZ_EN +#endif + +//#define BAUD_RATE_100K_EN + +#define I2C1_SCL_GPIO_PORT CW_GPIOB +#define I2C1_SCL_GPIO_PIN GPIO_PIN_6 +#define I2C1_SDA_GPIO_PORT CW_GPIOB +#define I2C1_SDA_GPIO_PIN GPIO_PIN_7 + +#define I2C1_SCL_LOW() PB06_SETLOW() +#define I2C1_SDA_LOW() PB07_SETLOW() +#define I2C1_SCL_HIGH() PB06_SETHIGH() +#define I2C1_SDA_HIGH() PB07_SETHIGH() + +#define I2C1_SCL2GPIO() PB06_AFx_GPIO() +#define I2C1_SDA2GPIO() PB07_AFx_GPIO() +#define GPIO2I2C1_SCL() PB06_AFx_I2C1SCL() +#define GPIO2I2C1_SDA() PB07_AFx_I2C1SDA() + +// EEPROM内部地址 +#define START_ADDR_EE 0 // 写入或者读取的EEPROM的地址 +#define TEST_CNT 16 // 写读次数 + +uint8_t u8SendData1[8] = {0x66, 0x02, 0x03, 0x04, 0x05, 0x60, 0x70, 0x20}; +uint8_t u8SendData2[8] = {0x55, 0xAA, 0xAA, 0x55, 0x55, 0xAA, 0x55, 0xAA}; +uint8_t u8RecData[16]; +uint8_t u8State = 0; + + +/** +* @brief main函数 +* +* 本函数实现了I2C通信的初始化及数据读写操作。 +* +* @return int32_t 返回0表示程序正常结束 +*/ +int32_t main(void) +{ + I2C_MasterConfigTypeDef I2C_InitStruct; + uint16_t tempCnt = 0; + + // 时钟初始化 + SYSCTRL_Configuration(); + + // IO口初始化 + GPIO_Configuration(); + + // I2C初始化 + I2C_MasterDeinit(CW_I2C1); + I2C_MasterInitDefault(&I2C_InitStruct); + + // 初始化模块 +#ifdef BAUD_RATE_100K_EN + I2C_InitStruct.I2C_BaudRate_Hz = 100000UL; +#endif + +#ifdef HSI48MHZ_EN + I2C_MasterInit(CW_I2C1, &I2C_InitStruct, 48000000UL); + +#elif defined (HSI8MHZ_EN) + I2C_MasterInit(CW_I2C1, &I2C_InitStruct, 8000000UL); +#else +#endif + + I2C_MasterCmd(CW_I2C1, ENABLE); // I2C模块使能 + if (I2C_MasterPollingFlag(CW_I2C1, I2C_IT_BUSBUSY) == I2C_Status_Success) + { + I2C_ExceptionHandling(); + } + + while (1) + { + u8State = I2C_MasterWriteEepromData(CW_I2C1, START_ADDR_EE, I2C_REG_ADDR_8BIT, u8SendData1, 8); +#ifdef HSI48MHZ_EN + FirmwareDelay(30000); //@48MHz +#else + FirmwareDelay(5000); //@8MHz +#endif + + u8State = I2C_MasterWriteEepromData(CW_I2C1, START_ADDR_EE + 8, I2C_REG_ADDR_8BIT, u8SendData2, 8); +#ifdef HSI48MHZ_EN + FirmwareDelay(30000); //@48MHz +#else + FirmwareDelay(5000); //@8MHz +#endif + + u8State = I2C_MasterReadEepromData(CW_I2C1, START_ADDR_EE, I2C_REG_ADDR_8BIT, u8RecData, 16); + + ++tempCnt; + for (uint8_t i = 0; i < 8; ++i) + { + u8SendData1[i] = tempCnt + i; + } + if (tempCnt >= TEST_CNT) + { + break; + } + +#ifdef HSI48MHZ_EN + FirmwareDelay(30000); //@48MHz +#else + FirmwareDelay(5000); //@8MHz +#endif + + } + + while (1) + { + } +} + +/** +* @brief Configures the different system clocks. +* @param None +* @retval None +*/ +void SYSCTRL_Configuration(void) +{ +#ifndef HSI48MHZ_EN + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); // 8MHz +#else + __SYSCTRL_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_2); + CW_FLASH->CR2 |= (0x5A5A0000 | 0x18); //Enable FLASH Prefetch and Cache. + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV2); // 48MHz + __SYSCTRL_FLASH_CLK_DISABLE(); +#endif + __SYSCTRL_I2C1_CLK_ENABLE(); +} + +/** +* @brief Configure the GPIO Pins. +* @param None +* @retval None +*/ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + + __SYSCTRL_GPIOB_CLK_ENABLE(); + + GPIO2I2C1_SCL(); + GPIO2I2C1_SDA(); + GPIO_InitStructure.Pins = I2C1_SCL_GPIO_PIN | I2C1_SDA_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_Init(I2C1_SCL_GPIO_PORT, &GPIO_InitStructure); +} + +static void I2C_Stop_SW(void) +{ + I2C1_SCL_LOW(); // SCL = 0 + I2C1_SDA_LOW(); // SDA = 0 + FirmwareDelay(4); // delay 4us@8MHz + I2C1_SCL_HIGH(); // SCL = 1 + FirmwareDelay(4); // delay 4us@8MHz + I2C1_SDA_HIGH(); // SDA = 1 +} + +void I2C_ExceptionHandling(void) +{ + I2C1_SCL2GPIO(); + I2C1_SDA2GPIO(); + I2C_Stop_SW(); + FirmwareDelay(1000); // delay 1ms@8MHz + GPIO2I2C1_SCL(); + GPIO2I2C1_SDA(); +} + +/****************************************************************************** +* EOF (not truncated) +******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** +* @brief Reports the name of the source file and the source line number +* where the assert_param error has occurred. +* @param file: pointer to the source file name +* @param line: assert_param error line source number +* @retval None +*/ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + __NOP(); + while(1); + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/readme.txt new file mode 100644 index 0000000..87bbb76 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_cw24c02_poll/readme.txt @@ -0,0 +1,36 @@ +示例目的： + 利用I2C接口，采用轮询方式读写EEPROM芯片（CW24C02）。 + +硬件资源： + 1. CW32L012C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟2分频，48MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=48MHz + +演示说明： + 1、采用默认时钟配置，初始化MCU I2C为主机接口，400KHz，不使能I2C中断。提示：可以通过宏定义，支持8MHz HSI主频和100kHz I2C通信速率。 + 2、I2C写时序：根据CW24C02手册，采用页写模式：依次发送START信号、SLA+W字节、目标地址字节、以及最多8字节（受CW24C02每页8字节限制）数据，最后发送STOP信号。 + 3、I2C读时序：根据CW24C02手册，采用顺序读模式：先通过字节写模式完成SLA+W字节以及目标地址发送，然后发送重复START信号、SLA+R， + 并根据需要读取的字节数产生对应字节的时钟信号，最后发送STOP信号。 + 4、程序流程： + （1）程序完成I2C主设备配置后，先将各待发送数组中的数据依次写入到EEPROM的第1/2页（CW24C02每页8字节）： + 发送START信号后，I2C模块会产生状态改变，程序持续查询I2C模块状态并根据不同状态值进行不同处理，直到完成CW24C02的页写模式所有数据字节以及STOP信号发送。 + （2）然后启动从EERROM的起始地址开始的16字节（第1/2页）数据读取流程： + 发送START信号后，I2C模块会产生状态改变，程序持续查询I2C模块状态并根据不同状态值进行不同处理，直到完成CW24C02的顺序读模式所有数据字节发送及接收， + 并发送STOP信号，完成读操作流程。 + （3）然后重新初始化待发送数组的数据，重复下一次测试过程。直到达到设定测试次数之后，测试程序退出。 + 5、注意实际测试时需要更改I2C/GPIO口线、时钟配置以及GPIO配置都需要修改。 + 6、注意由于EEPROM器件限制，在写入数据之后，需要加入一定的等待延时(5ms)，以等待EEPROM实际的写操作完成。 + 7、I2C从机设备地址目前统一在cw32l012_lpi2c.h文件中进行定义，必要时请自行修改。 + +使用说明： ++ EWARM + 1. 打开I2C_cw24c02_poll.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开I2C_cw24c02_poll.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/EWARM/I2C_mcu_master_Int.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/EWARM/I2C_mcu_master_Int.ewp new file mode 100644 index 0000000..9ad2388 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/EWARM/I2C_mcu_master_Int.ewp @@ -0,0 +1,2278 @@ + + + + 2 + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + 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+ 0 + 0 + 0 + 0 + 0 + 0 + ..\USER\src\main.c + + + + + + + 0 + 1 + g_RxBuffer + + + 1 + 1 + masterHandle + + + + + 1 + 0 + 0x1000a0 + 0 + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_lpi2c.c + cw32l012_lpi2c.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/MDK/I2C_mcu_master_Int.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/MDK/I2C_mcu_master_Int.uvprojx new file mode 100644 index 0000000..cfc8d95 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/MDK/I2C_mcu_master_Int.uvprojx @@ -0,0 +1,466 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + I2C_mcu_master_Int + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012 -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + I2C_mcu_master_Int + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x8000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_lpi2c.c + 1 + ..\..\..\..\Libraries\src\cw32l012_lpi2c.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..15c90dc --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,88 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void SYSCTRL_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void LPTIM_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void CLKFAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/USER/inc/main.h new file mode 100644 index 0000000..1cec89e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/USER/inc/main.h @@ -0,0 +1,83 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012.h" +#include "system_cw32l012.h" +#include "interrupts_cw32l012.h" +#include "base_types.h" + +#include "cw32l012_lpi2c.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_flash.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +#define LEN_DATA_RAM (16) +/* USER CODE END EM */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +static void I2C_Stop_SW(void); +void I2C_ExceptionHandling(void); +void LPI2C_MasterInit(void); + + +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..e078f6b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupts_cw32l012.h" +#include "..\inc\main.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW32L012 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH12 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH34 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC13 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC24 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM34 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3_HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + LPI2C_CommonIRQHandler(CW_I2C1, 1U); + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI23 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2_DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/USER/src/main.c new file mode 100644 index 0000000..ee91a1d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/USER/src/main.c @@ -0,0 +1,399 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2022-7-12 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +#define _MAIN + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//#define HSI48MHZ_EN + +#ifndef HSI48MHZ_EN +#define HSI8MHZ_EN +#endif + +//#define BAUD_RATE_100K_EN +//#define BAUD_RATE_1000K_EN + +#define I2C1_SCL_GPIO_PORT CW_GPIOB +#define I2C1_SCL_GPIO_PIN GPIO_PIN_6 +#define I2C1_SDA_GPIO_PORT CW_GPIOB +#define I2C1_SDA_GPIO_PIN GPIO_PIN_7 + +#define I2C1_SCL_LOW() PB06_SETLOW() +#define I2C1_SDA_LOW() PB07_SETLOW() +#define I2C1_SCL_HIGH() PB06_SETHIGH() +#define I2C1_SDA_HIGH() PB07_SETHIGH() + +#define I2C1_SCL2GPIO() PB06_AFx_GPIO() +#define I2C1_SDA2GPIO() PB07_AFx_GPIO() +#define GPIO2I2C1_SCL() PB06_AFx_I2C1SCL() +#define GPIO2I2C1_SDA() PB07_AFx_I2C1SDA() + +#define DEV_ADDR_SLAVE_7B 0x70 //I2C从机设备地址：7bits. +#define DEV_ADDR_SLAVE_10B 0x3F0 //I2C从机设备地址：10bits. +#define RAM_ADDR_OFFSET_SLAVE 0x0800 //I2C从机RAM目标地址:0x20000000 + 0x0800. + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint8_t g_TxBuffer[LEN_DATA_RAM] = {0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x60, 0x70, 0x80, 0x90, 0xa0, 0xb0, 0xc0, 0xd0, 0xe0, 0xf0}; +uint8_t g_RxBuffer[2 + LEN_DATA_RAM]; +lpi2c_master_handle_t masterHandle = {0}; +lpi2c_master_transfer_t masterXfer = {0}; +uint8_t u8StateMathine; +volatile boolean_t g_TransferDone = FALSE; + + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +void LPI2C_MasterIRQHandler(void) +{ + LPI2C_MasterTransferHandleIRQ(CW_I2C1, &masterHandle); +} + +void LPI2C_MasterCallback(I2C_TypeDef *I2Cx, lpi2c_master_handle_t *handle, status_t status, void *userData) +{ + if (kStatus_Success == status) + { + g_TransferDone = TRUE; + } + else + { + // 错误处理 + } +} + +void LPI2C_MasterInit(void) +{ + I2C_MasterConfigTypeDef I2C_InitStruct; + + I2C_MasterDeinit(CW_I2C1); + // I2C default values + I2C_MasterInitDefault(&I2C_InitStruct); + + // 初始化模块 +#ifdef BAUD_RATE_100K_EN + I2C_InitStruct.I2C_BaudRate_Hz = 100000UL; +#elif defined (BAUD_RATE_1000K_EN) + I2C_InitStruct.I2C_BaudRate_Hz = 1000000UL; +#else +#endif + +#ifdef HSI48MHZ_EN + I2C_MasterInit(CW_I2C1, &I2C_InitStruct, 48000000UL); +#elif defined (HSI8MHZ_EN) + I2C_MasterInit(CW_I2C1, &I2C_InitStruct, 8000000UL); +#else +#endif + +} + +void LPI2C_MasterTransferIT(void) +{ + u8StateMathine = kIdleState; + + masterXfer.data = &g_TxBuffer[0]; + masterXfer.dataSize = LEN_DATA_RAM; + masterXfer.direction = I2C_MODE_WRITE; + masterXfer.flags = kLPI2C_TransferDefaultFlag; + masterXfer.slaveAddress = DEV_ADDR_SLAVE_7B; + masterXfer.subaddress = RAM_ADDR_OFFSET_SLAVE; + masterXfer.subaddressSize = 2; + + masterHandle.state = kIdleState; + masterHandle.remainingBytes = LEN_DATA_RAM; + masterHandle.buf = &u8StateMathine; + masterHandle.userData = NULL; + masterHandle.commandBuffer[0] = DEV_ADDR_SLAVE_7B | I2C_MODE_WRITE; + masterHandle.commandBuffer[1] = RAM_ADDR_OFFSET_SLAVE >> 8; + masterHandle.commandBuffer[2] = RAM_ADDR_OFFSET_SLAVE & 0x00FF; + masterHandle.commandBuffer[3] = NULL; + masterHandle.commandBuffer[4] = NULL; + masterHandle.commandBuffer[5] = NULL; + masterHandle.completionCallback = LPI2C_MasterCallback; + masterHandle.transfer = masterXfer; + + LPI2C_MasterTransferCreateHandle(CW_I2C1, &masterHandle, LPI2C_MasterCallback, NULL); + LPI2C_MasterTransferNonBlocking(CW_I2C1, &masterHandle, &masterXfer); +} + +void LPI2C_MasterReceiveIT(void) +{ + u8StateMathine = kIdleState; + + masterXfer.data = &g_RxBuffer[0]; + masterXfer.dataSize = 2 + LEN_DATA_RAM; //Include 2-byte subAddress. + masterXfer.direction = I2C_MODE_READ; + masterXfer.flags = kLPI2C_TransferDefaultFlag; + masterXfer.slaveAddress = DEV_ADDR_SLAVE_7B; + masterXfer.subaddress = RAM_ADDR_OFFSET_SLAVE; + masterXfer.subaddressSize = 2; + + masterHandle.state = kIdleState; + masterHandle.remainingBytes = LEN_DATA_RAM; + masterHandle.buf = &u8StateMathine; + masterHandle.userData = NULL; + masterHandle.commandBuffer[0] = DEV_ADDR_SLAVE_7B | I2C_MODE_WRITE; + masterHandle.commandBuffer[1] = RAM_ADDR_OFFSET_SLAVE >> 8; + masterHandle.commandBuffer[2] = RAM_ADDR_OFFSET_SLAVE & 0x00FF; + masterHandle.commandBuffer[3] = NULL; + masterHandle.commandBuffer[4] = NULL; + masterHandle.commandBuffer[5] = NULL; + masterHandle.completionCallback = LPI2C_MasterCallback; + masterHandle.transfer = masterXfer; + + LPI2C_MasterTransferCreateHandle(CW_I2C1, &masterHandle, LPI2C_MasterCallback, NULL); + LPI2C_MasterTransferNonBlocking(CW_I2C1, &masterHandle, &masterXfer); +} + +/** + * @brief main函数 + * + * 初始化系统时钟、I2C的IO口和I2C模块，并通过I2C模块发送和接收数据。 + * + * @return int32_t 返回0表示程序正常结束。 + */ +int32_t main(void) +{ + uint8_t cntTemp = 0; + + //时钟初始化 + SYSCTRL_Configuration(); + + // I2C的IO口初始化 + GPIO_Configuration(); + + // I2C主设备初始化 + LPI2C_MasterInit(); + + //中断设置 + NVIC_Configuration(); + I2C_MasterCmd(CW_I2C1, ENABLE); // I2C模块使能 + + if (I2C_MasterPollingFlag(CW_I2C1, I2C_IT_BUSBUSY) == I2C_Status_Success) + { + I2C_ExceptionHandling(); + } + + while (1) + { + //I2C Interrupt mode + LPI2C_MasterTransferIT(); // I2C数据写操作 + + while (!g_TransferDone) + { + ; + } + +#ifdef HSI48MHZ_EN + FirmwareDelay(30000); //@48MHz +#else + FirmwareDelay(5000); //@8MHz +#endif + + g_TransferDone = 0; + LPI2C_MasterReceiveIT(); //I2C数据读操作 + + while (!g_TransferDone) + { + ; + } + + //检查Write/Read数据一致性 + if(0 == memcmp(g_TxBuffer, g_RxBuffer + 2, LEN_DATA_RAM)) + { + //LED1亮/LED2灭 //PASSED + PB09_SETHIGH(); + PB08_SETLOW(); + } + else + { + //LED1灭/LED2亮 //FAILED + PB09_SETLOW(); + PB08_SETHIGH(); + + //I2C_MasterCmd(CW_I2C1, DISABLE); + I2C_MasterSoftReset(CW_I2C1); + // I2C初始化 + LPI2C_MasterInit(); + I2C_MasterCmd(CW_I2C1, ENABLE); // I2C模块使能 + + if (I2C_MasterPollingFlag(CW_I2C1, I2C_IT_BUSBUSY) == I2C_Status_Success) + { + I2C_ExceptionHandling(); + } + } + + ++cntTemp; + for (uint8_t i = 0; i < sizeof(g_TxBuffer); ++i) + { + g_TxBuffer[i] = cntTemp + i; + } + +#ifdef HSI48MHZ_EN + FirmwareDelay(3000); +#else + FirmwareDelay(500); +#endif + + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ +#ifdef HSI48MHZ_EN + __SYSCTRL_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_2); + CW_FLASH->CR2 |= (0x5A5A0000 | 0x18); // Enable FLASH Prefetch and Cache. + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV2); // 48MHz + __SYSCTRL_FLASH_CLK_DISABLE(); +#elif defined(HSI8MHZ_EN) + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); // 8MHz +#else + // Default HSI4MHz +#endif + __SYSCTRL_I2C1_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + + __SYSCTRL_GPIOB_CLK_ENABLE(); + + GPIO2I2C1_SCL(); + GPIO2I2C1_SDA(); + GPIO_InitStructure.Pins = I2C1_SCL_GPIO_PIN | I2C1_SDA_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_Init(I2C1_SCL_GPIO_PORT, &GPIO_InitStructure); + + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_8 | GPIO_PIN_9 ; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + + //LEDs are off. + PB09_SETLOW(); + PB08_SETLOW(); +} + +static void I2C_Stop_SW(void) +{ + I2C1_SCL_LOW(); + I2C1_SDA_LOW(); +#ifdef HSI48MHZ_EN + FirmwareDelay(24); // delay 4us@48MHz + I2C1_SCL_HIGH(); + FirmwareDelay(24); +#else + FirmwareDelay(4); // delay 4us@8MHz + I2C1_SCL_HIGH(); + FirmwareDelay(4); +#endif + I2C1_SDA_HIGH(); +} + +void I2C_ExceptionHandling(void) +{ + I2C1_SCL2GPIO(); + I2C1_SDA2GPIO(); + I2C_Stop_SW(); +#ifdef HSI48MHZ_EN + FirmwareDelay(6000); // delay 1ms@48MHz +#else + FirmwareDelay(1000); // delay 1ms@8MHz +#endif + GPIO2I2C1_SCL(); + GPIO2I2C1_SDA(); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_SetPriority(I2C1_IRQn, 3); //Lowest priority + NVIC_ClearPendingIRQ(I2C1_IRQn); + NVIC_EnableIRQ(I2C1_IRQn); + __enable_irq(); +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + __NOP(); + while(1); + /* USER CODE END 6 */ +} + +#endif + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/readme.txt new file mode 100644 index 0000000..56bc40e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_Int/readme.txt @@ -0,0 +1,34 @@ +示例目的： + 采用中断方式，通过I2C接口， 实现I2C主设备功能，和I2C从机进行数据通信。 + +硬件资源： + 1. CW32L012C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟12分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. PB09/PB08设置为PUSH-PULL输出，驱动LED + +演示说明： + 1、采用默认时钟配置，初始化I2C为主机，400KHz。 + 2、主从通信主设备I2C发送时序为多字节写：依次发送START信号、SLA+W字节、多个数据字节，最后发送STOP信号。 + 3、主从通信主设备I2C接收时序为随机地址+顺序读。 + 4、程序流程：程序完成I2C主设备配置后，先将发送数组中的内容发给从机，从机RAM目标地址:0x20000000 + 0x0800。 + 然后延时，主机启动数据接收流程，并比较接收数据是否与发送数据一致，如果相同，LED1指示灯亮，否则LED2指示灯亮。 + 最后重新初始化发送数组内容，不断重复数据发送、接收过程。 + 5、注意主机、从机上电顺序，建议从机先工作，等待主机开始发送数据。 + +硬件连接： + LPI2C_MASTER SCL (PB06)-- LPI2C_SLAVE SCL (PB06) + LPI2C_MASTER SDA (PB07)-- LPI2C_SLAVE SDA (PB07) + +使用说明： ++ EWARM + 1. 打开I2C_mcu_master_Int.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开I2C_mcu_master_Int.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/EWARM/I2C_mcu_master_poll.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/EWARM/I2C_mcu_master_poll.ewp new file mode 100644 index 0000000..ec836a0 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/EWARM/I2C_mcu_master_poll.ewp @@ -0,0 +1,2278 @@ + + + + 2 + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_atim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_btim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_crc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_debug.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_digitalsign.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_eau.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gtim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_iwdt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_lpi2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_lvd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_opa.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_pwr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_ram.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_vc.c + + + + Startup + + $PROJ_DIR$\..\..\..\..\IDEsupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + $PROJ_DIR$\..\USER\src\main.c + + + Release + + ICCARM + + 31 + 0 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/EWARM/I2C_mcu_master_poll.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/EWARM/I2C_mcu_master_poll.eww new file mode 100644 index 0000000..dc522bb --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/EWARM/I2C_mcu_master_poll.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\I2C_mcu_master_poll.ewp + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/MDK/I2C_mcu_master_poll.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/MDK/I2C_mcu_master_poll.uvoptx new file mode 100644 index 0000000..3a6b433 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/MDK/I2C_mcu_master_poll.uvoptx @@ -0,0 +1,370 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + I2C_mcu_master_poll + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U56FF71065178565626600287 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC2000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL08000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC2000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + + + + 0 + 1 + u8DataReceived + + + + + 1 + 0 + iState + 0 + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_lpi2c.c + cw32l012_lpi2c.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/MDK/I2C_mcu_master_poll.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/MDK/I2C_mcu_master_poll.uvprojx new file mode 100644 index 0000000..4d68a6a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/MDK/I2C_mcu_master_poll.uvprojx @@ -0,0 +1,466 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + I2C_mcu_master_poll + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012 -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + I2C_mcu_master_poll + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x8000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_lpi2c.c + 1 + ..\..\..\..\Libraries\src\cw32l012_lpi2c.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..15c90dc --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,88 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void SYSCTRL_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void LPTIM_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void CLKFAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/USER/inc/main.h new file mode 100644 index 0000000..cf48806 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/USER/inc/main.h @@ -0,0 +1,88 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012.h" +#include "system_cw32l012.h" +#include "interrupts_cw32l012.h" +#include "base_types.h" + +#include "cw32l012_lpi2c.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_flash.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +#define LEN_DATA_RAM (16) +/* USER CODE END EM */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +typedef struct _ramTesting_handle +{ + I2C_TypeDef *base; + lpi2c_master_transfer_t xfer; + uint8_t ramRx_buf[2 + LEN_DATA_RAM]; +} ramTesting_handle_t; +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +static void I2C_Stop_SW(void); +void I2C_ExceptionHandling(void); +void I2C_InitBsp(void); +status_t RAM_TestingInit(ramTesting_handle_t *handle, I2C_TypeDef *base); +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c0e8610 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupts_cw32l012.h" +#include "..\inc\main.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW32L012 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH12 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH34 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC13 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC24 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM34 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3_HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI23 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2_DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/USER/src/main.c new file mode 100644 index 0000000..c703eec --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/USER/src/main.c @@ -0,0 +1,374 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2022-7-12 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +#define _MAIN + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint8_t u8DataSent[LEN_DATA_RAM] = {0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x60, 0x70, 0x80, 0x90, 0xa0, 0xb0, 0xc0, 0xd0, 0xe0, 0xf0}; +uint8_t u8DataReceived[2 + LEN_DATA_RAM] = {0x00}; +//... +static ramTesting_handle_t ramHandle; +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//#define HSI48MHZ_EN + +#ifndef HSI48MHZ_EN +#define HSI8MHZ_EN +#endif + +//#define BAUD_RATE_100K_EN +//#define BAUD_RATE_1000K_EN + +#define I2C1_SCL_GPIO_PORT CW_GPIOB +#define I2C1_SCL_GPIO_PIN GPIO_PIN_6 +#define I2C1_SDA_GPIO_PORT CW_GPIOB +#define I2C1_SDA_GPIO_PIN GPIO_PIN_7 + +#define I2C1_SCL_LOW() PB06_SETLOW() +#define I2C1_SDA_LOW() PB07_SETLOW() +#define I2C1_SCL_HIGH() PB06_SETHIGH() +#define I2C1_SDA_HIGH() PB07_SETHIGH() + +#define I2C1_SCL2GPIO() PB06_AFx_GPIO() +#define I2C1_SDA2GPIO() PB07_AFx_GPIO() +#define GPIO2I2C1_SCL() PB06_AFx_I2C1SCL() +#define GPIO2I2C1_SDA() PB07_AFx_I2C1SDA() + +#define DEV_ADDR_SLAVE_7B 0x70 //I2C从机设备地址：7bits. +#define DEV_ADDR_SLAVE_10B 0x3F0 //I2C从机设备地址：10bits. +#define RAM_ADDR_OFFSET_SLAVE 0x0800 //I2C从机RAM目标地址:0x20000000 + 0x0800. + + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief main函数 + * + * 初始化系统时钟、I2C的IO口和I2C模块，并通过I2C模块发送和接收数据。 + * + * @return int32_t 返回0表示程序正常结束。 + */ +int32_t main(void) +{ + uint16_t cntTemp = 0 ; + uint8_t dataTemp[sizeof(u8DataSent) + 2]; + + //时钟初始化 + SYSCTRL_Configuration(); + + // I2C的IO口初始化 + GPIO_Configuration(); + + I2C_DeInit(CW_I2C1); + + I2C_InitBsp(); + + I2C_MasterCmd(CW_I2C1, ENABLE); // I2C模块使能 + + if (I2C_MasterPollingFlag(CW_I2C1, I2C_IT_BUSBUSY) == I2C_Status_Success) + { + I2C_ExceptionHandling(); + } + + dataTemp[0] = (uint8_t)((RAM_ADDR_OFFSET_SLAVE & 0xFF00) >> 8); // 写数据高字节 + dataTemp[1] = (uint8_t)(RAM_ADDR_OFFSET_SLAVE & 0x00FF); // 写数据低字节 + + while (1) + { + memcpy(dataTemp + 2, u8DataSent, sizeof(u8DataSent)); +#if 0 + /*I2C Polling method 1*/ + // 主机发送2 + X字节数据 + if(I2C_Status_Success == I2C_MasterSendDataToSlave(CW_I2C1, DEV_ADDR_SLAVE_7B, dataTemp, sizeof(dataTemp))) + { +#ifdef HSI48MHZ_EN + FirmwareDelay(1000); //@48MHz +#else + FirmwareDelay(100); //@8MHz +#endif + + if(I2C_Status_Success != I2C_MasterReceiveDataFromSlave(CW_I2C1, DEV_ADDR_SLAVE_7B, dataTemp, I2C_REG_ADDR_16BIT, u8DataReceived, sizeof(u8DataReceived))) // 主机读取2+X字节数据 + { + I2C_MasterSTOP(CW_I2C1); + } + } + else + { + I2C_MasterSTOP(CW_I2C1); + } + + I2C_MasterClearFlag(CW_I2C1, ~CLEAR_IT_MASK); // 清除I2C_MISR中断标志 + + //检查Write/Read数据一致性 + if(0 == memcmp(dataTemp, u8DataReceived, sizeof(u8DataReceived))) +#else + /*I2C Polling method 2*/ + /* Initialize RAM Testing */ + status_t status = RAM_TestingInit(&ramHandle, CW_I2C1); + + //检查Write/Read数据一致性 + if (0 == memcmp(dataTemp, &ramHandle.ramRx_buf[0], sizeof(ramHandle.ramRx_buf))) +#endif + { + //LED1亮/LED2灭 //PASSED + PB09_SETHIGH(); + PB08_SETLOW(); + } + else + { + //LED1灭/LED2亮 //FAILED + PB09_SETLOW(); + PB08_SETHIGH(); + + I2C_MasterSoftReset(CW_I2C1); + // I2C初始化 + I2C_InitBsp(); + I2C_MasterCmd(CW_I2C1, ENABLE); // I2C模块使能 + + if (I2C_MasterPollingFlag(CW_I2C1, I2C_IT_BUSBUSY) == I2C_Status_Success) + { + I2C_ExceptionHandling(); + } + } + + ++cntTemp; + for (uint8_t i = 0; i < sizeof(u8DataSent); ++i) + { + u8DataSent[i] = cntTemp + i; + } + +#ifdef HSI48MHZ_EN + FirmwareDelay(3000); +#else + FirmwareDelay(500); +#endif + + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ +#ifdef HSI48MHZ_EN + __SYSCTRL_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_2); + CW_FLASH->CR2 |= (0x5A5A0000 | 0x18); // Enable FLASH Prefetch and Cache. + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV2); // 48MHz + __SYSCTRL_FLASH_CLK_DISABLE(); +#elif defined(HSI8MHZ_EN) + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); // 8MHz +#else + // Default HSI4MHz +#endif + __SYSCTRL_I2C1_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + + __SYSCTRL_GPIOB_CLK_ENABLE(); + + GPIO2I2C1_SCL(); + GPIO2I2C1_SDA(); + GPIO_InitStructure.Pins = I2C1_SCL_GPIO_PIN | I2C1_SDA_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_Init(I2C1_SCL_GPIO_PORT, &GPIO_InitStructure); + + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_8 | GPIO_PIN_9 ; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + + //LEDs are off. + PB09_SETLOW(); + PB08_SETLOW(); +} + +static void I2C_Stop_SW(void) +{ + I2C1_SCL_LOW(); + I2C1_SDA_LOW(); +#ifdef HSI48MHZ_EN + FirmwareDelay(24); // delay 4us@48MHz + I2C1_SCL_HIGH(); + FirmwareDelay(24); +#else + FirmwareDelay(4); // delay 4us@8MHz + I2C1_SCL_HIGH(); + FirmwareDelay(4); +#endif + I2C1_SDA_HIGH(); +} + +void I2C_ExceptionHandling(void) +{ + I2C1_SCL2GPIO(); + I2C1_SDA2GPIO(); + I2C_Stop_SW(); +#ifdef HSI48MHZ_EN + FirmwareDelay(6000); // delay 1ms@48MHz +#else + FirmwareDelay(1000); // delay 1ms@8MHz +#endif + GPIO2I2C1_SCL(); + GPIO2I2C1_SDA(); +} + +void I2C_InitBsp(void) +{ + I2C_MasterConfigTypeDef I2C_InitStruct; + // I2C初始化为默认值 + I2C_MasterInitDefault(&I2C_InitStruct); + +#ifdef BAUD_RATE_100K_EN + I2C_InitStruct.I2C_BaudRate_Hz = 100000UL; +#elif defined (BAUD_RATE_1000K_EN) + I2C_InitStruct.I2C_BaudRate_Hz = 1000000UL; +#else +#endif + +// 初始化模块 +#ifdef HSI48MHZ_EN + I2C_MasterInit(CW_I2C1, &I2C_InitStruct, 48000000UL); +#elif defined(HSI8MHZ_EN) + I2C_MasterInit(CW_I2C1, &I2C_InitStruct, 8000000UL); +#else +#endif +} + +/** + * @brief 初始化RAM测试模块 + * + * 该函数用于初始化RAM测试模块，配置I2C通信参数，并准备向从设备写入和读取数据。 + * + * @param handle RAM测试模块的句柄，用于存储测试过程中需要的数据 + * @param base I2C通信的基地址 + * + * @return 返回状态码，成功返回kStatus_Success，失败返回错误代码 + */ +status_t RAM_TestingInit(ramTesting_handle_t *handle, I2C_TypeDef *base) +{ + lpi2c_master_transfer_t *xfer = &(handle->xfer); + status_t status; + + assert_param(handle); + assert_param(base); + + if (!handle || !base) + { + return kStatus_InvalidArgument; + } + + handle->base = base; + + /* clear transfer structure and buffer */ + memset(xfer, 0, sizeof(*xfer)); + memset(handle->ramRx_buf, 0, LEN_DATA_RAM); + + /* set device mode to normal operation */ + xfer->slaveAddress = DEV_ADDR_SLAVE_7B; + xfer->direction = I2C_MODE_WRITE; + xfer->subaddress = RAM_ADDR_OFFSET_SLAVE; + xfer->subaddressSize = 2; + xfer->data = &u8DataSent; + xfer->dataSize = LEN_DATA_RAM; + xfer->flags = kLPI2C_TransferDefaultFlag; + //Write data to slave RAM. + status = LPI2C_MasterTransferBlocking(handle->base, &handle->xfer); + +#ifdef HSI48MHZ_EN + FirmwareDelay(1000); //@48MHz +#else + FirmwareDelay(100); //@8MHz +#endif + /* prepare transfer structure for reading ram data */ + xfer->slaveAddress = DEV_ADDR_SLAVE_7B; + xfer->direction = I2C_MODE_READ; + xfer->subaddress = RAM_ADDR_OFFSET_SLAVE; + xfer->subaddressSize = 2; + xfer->data = handle->ramRx_buf; + xfer->dataSize = LEN_DATA_RAM + 2; + xfer->flags = kLPI2C_TransferDefaultFlag; + //Read data from slave RAM. + status = LPI2C_MasterTransferBlocking(handle->base, &handle->xfer); + return status; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + __NOP(); + while(1); + /* USER CODE END 6 */ +} + +#endif + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/readme.txt new file mode 100644 index 0000000..67d890e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_master_poll/readme.txt @@ -0,0 +1,35 @@ +示例目的： + 采用查询方式，通过I2C接口， 实现I2C主设备功能，和I2C从机进行数据通信。 + +硬件资源： + 1. CW32L012C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟12分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. PB09/PB08设置为PUSH-PULL输出，驱动LED + +演示说明： + 1、采用默认时钟配置，初始化I2C为主机，400KHz，不使能I2C中断。 + 2、主从通信主设备I2C发送时序为多字节写：依次发送START信号、SLA+W字节、多个数据字节，最后发送STOP信号。 + 3、主从通信主设备I2C接收时序为随机地址+顺序读。 + 4、程序流程：程序完成I2C主设备配置后，先将发送数组中的内容发给从机，从机RAM目标地址:0x20000000 + 0x0800。 + 然后延时，主机启动数据接收流程，并比较接收数据是否与发送数据一致，如果相同，LED1指示灯亮，否则LED2指示灯亮。 + 最后重新初始化发送数组内容，不断重复数据发送、接收过程。 + 5、注意主机、从机上电顺序，建议从机先工作，等待主机开始发送数据。 + 6、示例中提供了两种I2C Polling方式，请自行选择。 + +硬件连接： + LPI2C_MASTER SCL (PB06)-- LPI2C_SLAVE SCL (PB06) + LPI2C_MASTER SDA (PB07)-- LPI2C_SLAVE SDA (PB07) + +使用说明： ++ EWARM + 1. 打开I2C_mcu_master_poll.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开I2C_mcu_master_poll.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/EWARM/I2C_mcu_slave_Int.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/EWARM/I2C_mcu_slave_Int.ewp new file mode 100644 index 0000000..d605ff4 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/EWARM/I2C_mcu_slave_Int.ewp @@ -0,0 +1,2278 @@ + + + + 2 + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_atim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_btim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_crc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_debug.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_digitalsign.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_eau.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gtim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_iwdt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_lpi2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_lvd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_opa.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_pwr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_ram.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_vc.c + + + + Startup + + $PROJ_DIR$\..\..\..\..\IDEsupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + $PROJ_DIR$\..\USER\src\main.c + + + Release + + ICCARM + + 31 + 0 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/EWARM/I2C_mcu_slave_Int.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/EWARM/I2C_mcu_slave_Int.eww new file mode 100644 index 0000000..1e90285 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/EWARM/I2C_mcu_slave_Int.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\I2C_mcu_slave_Int.ewp + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/MDK/I2C_mcu_slave_Int.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/MDK/I2C_mcu_slave_Int.uvoptx new file mode 100644 index 0000000..6e37e4b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/MDK/I2C_mcu_slave_Int.uvoptx @@ -0,0 +1,370 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + I2C_mcu_slave_Int + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC2000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC2000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + + + + 0 + 1 + u8RegAddr + + + 1 + 1 + u8DataReceived + + + + + 1 + 0 + 0x20000004 + 0 + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_lpi2c.c + cw32l012_lpi2c.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/MDK/I2C_mcu_slave_Int.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/MDK/I2C_mcu_slave_Int.uvprojx new file mode 100644 index 0000000..139157d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/MDK/I2C_mcu_slave_Int.uvprojx @@ -0,0 +1,466 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + I2C_mcu_slave_Int + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012 -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + I2C_mcu_slave_Int + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_lpi2c.c + 1 + ..\..\..\..\Libraries\src\cw32l012_lpi2c.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..15c90dc --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,88 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void SYSCTRL_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void LPTIM_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void CLKFAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/USER/inc/main.h new file mode 100644 index 0000000..7e942bc --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/USER/inc/main.h @@ -0,0 +1,85 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012.h" +#include "system_cw32l012.h" +#include "interrupts_cw32l012.h" +#include "base_types.h" + +#include "cw32l012_lpi2c.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_flash.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void I2C_ExceptionHandling(void); +uint8_t I2C_SlaveReceiveDataFromMaster(I2C_TypeDef *I2Cx, uint8_t *pu8RegAddr, I2C_SlaveRegAddrTypeDef u8RegAddrType,uint8_t *pu8Data, uint16_t *pu16Len); +uint8_t I2C_SlaveSendDataToMaster(I2C_TypeDef *I2Cx, uint8_t *pu8Data, uint16_t u16Len); +//... +void LPI2C_SlaveIRQHandler(I2C_TypeDef *I2Cx, uint8_t *pu8RegAddr, I2C_SlaveRegAddrTypeDef u8RegAddrType, uint8_t *pu8Data, uint16_t *pu16Len, uint16_t *pLenTx); +uint8_t I2C_SlaveReceiveDataISR(I2C_TypeDef *I2Cx, uint8_t *pu8RegAddr, I2C_SlaveRegAddrTypeDef u8RegAddrType, uint8_t *pu8Data, uint16_t *pu16Len); + +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..3addf9c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/USER/src/interrupts_cw32l012.c @@ -0,0 +1,442 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupts_cw32l012.h" +#include "..\inc\main.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +extern uint8_t u8RegAddr[]; +extern uint16_t u16LenReceived, u16LenSent; +extern uint8_t u8DataReceived[]; +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW32L012 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH12 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH34 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC13 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC24 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM34 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3_HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + LPI2C_SlaveIRQHandler(CW_I2C1, u8RegAddr, I2C_REG_ADDR_16BIT, u8DataReceived, &u16LenReceived, &u16LenSent); + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI23 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2_DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/USER/src/main.c new file mode 100644 index 0000000..f3135ee --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/USER/src/main.c @@ -0,0 +1,469 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2022-7-12 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +#define _MAIN + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//#define HSI48MHZ_EN + +#ifndef HSI48MHZ_EN +#define HSI8MHZ_EN +#endif + +//#define BAUD_RATE_100K_EN +//#define BAUD_RATE_1000K_EN + +//#define ADDR_SLAVE_10B_EN + +#define I2C1_SCL_GPIO_PORT CW_GPIOB +#define I2C1_SCL_GPIO_PIN GPIO_PIN_6 +#define I2C1_SDA_GPIO_PORT CW_GPIOB +#define I2C1_SDA_GPIO_PIN GPIO_PIN_7 + +#define I2C1_SCL_LOW() PB06_SETLOW() +#define I2C1_SDA_LOW() PB07_SETLOW() +#define I2C1_SCL_HIGH() PB06_SETHIGH() +#define I2C1_SDA_HIGH() PB07_SETHIGH() + +#define I2C1_SCL2GPIO() PB06_AFx_GPIO() +#define I2C1_SDA2GPIO() PB07_AFx_GPIO() +#define GPIO2I2C1_SCL() PB06_AFx_I2C1SCL() +#define GPIO2I2C1_SDA() PB07_AFx_I2C1SDA() + +#define DEV_ADDR_SLAVE_7B 0x70 //I2C从机设备地址：7bits. +#define DEV_ADDR_SLAVE_10B 0x3F0 //I2C从机设备地址：10bits. +#define RAM_ADDR_OFFSET_SLAVE 0x0800 //I2C从机RAM目标地址:0x20000000 + 0x0800. +#define RAM_ADDR_BASE_SLAVE 0x20000000 + +#define BUFFER_SIZE_TX 16UL + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint8_t u8RegAddr[MAX_SIZE_SUBADDRESS]; +uint16_t u16LenReceived, u16LenSent; +//... +size_t cntTx; +uint8_t addrRx; + +#if defined ( __CC_ARM ) +uint8_t u8DataReceived[2 + 16] __attribute__((at(RAM_ADDR_BASE_SLAVE + RAM_ADDR_OFFSET_SLAVE))); +#elif defined ( __ICCARM__ ) +uint8_t u8DataReceived[2 + 16 + 2] @ (RAM_ADDR_BASE_SLAVE + RAM_ADDR_OFFSET_SLAVE); +#elif defined ( __GNUC__ ) +uint8_t u8DataReceived[2 + 16] __attribute__((section(".ARM.__at_(RAM_ADDR_BASE_SLAVE + RAM_ADDR_OFFSET_SLAVE)"))); +#endif +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +static void GPIO_Configuration(void); +static void NVIC_Configuration(void); + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +lpi2c_slave_handle_t slaveHandle; +lpi2c_slave_transfer_t slaveXfer; +uint8_t u8StateMathine; +volatile boolean_t g_ReceiveDone = FALSE; + +void LPI2C_SlaveIRQHandler(I2C_TypeDef *I2Cx, uint8_t *pu8RegAddr, I2C_SlaveRegAddrTypeDef u8RegAddrType, uint8_t *pu8Data, uint16_t *pu16Len, uint16_t *pLenTx) +{ + uint32_t f_ISR = 0; + uint32_t timeout = 0x10; + + // Step 1: Slave address is valid. + // Step 2: Wait for slave register address & user data. + + do + { + I2C_SlaveReceiveDataISR(I2Cx, u8RegAddr, u8RegAddrType, pu8Data, pu16Len); + f_ISR = I2C_SlaveGetFlag(I2Cx, I2C_IT_STOP_SLV | I2C_IT_RESTART_SLV); + + } while ((0 == f_ISR) && (--timeout > 0)); + + if (0 == timeout) + { + return; + } + + if ((f_ISR & I2C_IT_STOP_SLV) > 0) + { + *pLenTx = *pu16Len; + } + + else if ((f_ISR & I2C_IT_RESTART_SLV) > 0) + { + // Slave transmit mode + CW_I2C1->SICR = 0; + I2C_SlaveSendDataToMaster(CW_I2C1, u8DataReceived, *pLenTx); + CW_I2C1->SICR = 0; + + f_ISR = 0; + } + else + { + } + CW_I2C1->SICR = 0; +} + + + +void LPI2C_SlaveInit(void) +{ + I2C_SlaveConfigTypeDef I2C_InitStruct; + + I2C_SlaveDeinit(CW_I2C1); + + // I2C default values + I2C_SlaveInitDefault(&I2C_InitStruct); + + I2C_InitStruct.I2C_Addr0 = DEV_ADDR_SLAVE_7B; + I2C_InitStruct.I2C_RegAddr = I2C_REG_ADDR_16BIT; + +#ifdef BAUD_RATE_100K_EN + I2C_InitStruct.clockHoldTime_ns = 250U; +#elif defined(BAUD_RATE_1000K_EN) + I2C_InitStruct.clockHoldTime_ns = 50U; +#else + I2C_InitStruct.clockHoldTime_ns = 100U; +#endif + + // 初始化模块 +#ifdef HSI48MHZ_EN + I2C_SlaveInit(CW_I2C1, &I2C_InitStruct, 48000000UL); +#elif defined (HSI8MHZ_EN) + I2C_SlaveInit(CW_I2C1, &I2C_InitStruct, 8000000UL); +#else + //... +#endif + +} + +/** + * @brief main entry point for the application. + * + * @return int32_t + */ +int32_t main(void) +{ + // 时钟初始化 + SYSCTRL_Configuration(); + + // IO口初始化 + GPIO_Configuration(); + + // I2C从设备初始化 + LPI2C_SlaveInit(); + + //中断设置 + NVIC_Configuration(); + I2C_SlaveCmd(CW_I2C1, ENABLE); // I2C模块使能 + + if (I2C_SlavePollingFlag(CW_I2C1, I2C_IT_BUSBUSY | I2C_IT_SLVBUSY_SLV) == I2C_Status_Success) + { + I2C_ExceptionHandling(); + } + + /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + LPI2C_SlaveEnableInterrupts(CW_I2C1, (uint32_t)kLPI2C_SlaveIrqFlags); + + I2C_SlaveCmd(CW_I2C1, ENABLE); // I2C模块使能 + + while (1) + { + + FirmwareDelay(0x100000); + PB09_TOG(); + } +} + + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ +#ifdef HSI48MHZ_EN + __SYSCTRL_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_2); + CW_FLASH->CR2 |= (0x5A5A0000 | 0x18); // Enable FLASH Prefetch and Cache. + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV2); // 48MHz + __SYSCTRL_FLASH_CLK_DISABLE(); +#elif defined(HSI8MHZ_EN) + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); // 8MHz +#else +// Default HSI4MHz +#endif + __SYSCTRL_I2C1_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + + __SYSCTRL_GPIOB_CLK_ENABLE(); + + GPIO2I2C1_SCL(); + GPIO2I2C1_SDA(); + GPIO_InitStructure.Pins = I2C1_SCL_GPIO_PIN | I2C1_SDA_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_Init(I2C1_SCL_GPIO_PORT, &GPIO_InitStructure); + + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_8 | GPIO_PIN_9 ; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + + //LEDs are off. + PB09_SETLOW(); + PB08_SETLOW(); +} + +void I2C_ExceptionHandling(void) +{ + //异常处理 + //while(1); +} + +uint8_t I2C_SlaveSendDataToMaster(I2C_TypeDef *I2Cx, uint8_t *pu8Data, uint16_t u16Len) +{ + uint8_t u8State; + uint16_t data0; + + // 使能应答标志 + I2C_SlaveTxNAck(I2Cx, DISABLE); + +#if 1 + // 查询等待I2C_SISR.RESTART , I2C_SISR.ADDR 变为 1 + while (I2C_SlavePollingFlag(I2Cx, I2C_IT_RESTART_SLV | I2C_IT_ADDR_SLV) != I2C_Status_Success) + ; + +#else + if (I2C_SlavePollingFlag(I2Cx, I2C_IT_RESTART_SLV | I2C_IT_ADDR_SLV) != I2C_Status_Success) + { + return I2C_Status_Timeout; // 超时错误 + } + +#endif + + data0 = (uint16_t)I2Cx->SASR_f.RADDR; // 读取 I2C_SASR 寄存器，自动清除 I2C_SISR.ADDR 标志 + + u8State = I2C_SlaveSend(I2Cx, pu8Data, u16Len); + + if (u8State != I2C_Status_Success) + { + return u8State; + } + + // 返回 NACK,释放总线 + if (1 == I2Cx->SCR1_f.ACKSTALL) + { + I2C_SlaveTxNAck(I2Cx, ENABLE); + } + + return I2C_Status_Success; +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_SetPriority(I2C1_IRQn, 3); //Lowest priority + NVIC_ClearPendingIRQ(I2C1_IRQn); + NVIC_EnableIRQ(I2C1_IRQn); + __enable_irq(); +} + + +uint8_t I2C_SlaveReceiveDataISR(I2C_TypeDef *I2Cx, uint8_t *pu8RegAddr, I2C_SlaveRegAddrTypeDef u8RegAddrType, uint8_t *pu8Data, uint16_t *pu16Len) +{ + uint8_t u8State; + uint16_t data0; + boolean_t modeRead; + uint8_t i, j; + + //清除I2C从机标志位 + CW_I2C1->SICR = 0; + // 使能应答标志 + I2C_SlaveTxNAck(I2Cx, DISABLE); + + data0 = (uint16_t)I2Cx->SASR_f.RADDR; // 读取 I2C_SASR 寄存器，自动清除 I2C_SISR.ADDR 标志 + modeRead = (boolean_t)(data0 & 0x01); + data0 = (uint16_t)(data0 >> 1); // 读取从机地址 + + //清除I2C从机标志位 + CW_I2C1->SICR = 0; //I2C_SlaveClearFlag(I2Cx, ~CLEAR_IT_MASK_SLV); + + u8State = I2C_SlaveReceive(I2Cx, pu8Data, pu16Len); + + if (u8State != I2C_Status_Success) + { + return u8State; + } + + if (modeRead == FALSE) + { + /*I2C write-mode: + Register address is at 1st or 1st & 2nd byte received; + Other bytes received are user data. + */ + // Save register address to local variable + *pu8RegAddr = *pu8Data; + + switch (u8RegAddrType) + { + case I2C_REG_ADDR_8BIT: + j = 1; + break; + case I2C_REG_ADDR_16BIT: + j = 2; + break; + case I2C_REG_ADDR_24BIT: + j = 3; + break; + case I2C_REG_ADDR_32BIT: + j = 4; + break; + default: + return I2C_Status_Error; + } + + if (j > 1) + { + if (*pu16Len >= j) // 检查是否有足够的数据长度 + { + i = j - 1; + while (i--) + { + ++pu8Data; + *(pu8RegAddr + 1) = *pu8Data; + } + } + else + { + return I2C_Status_Error; // 数据长度不足 + } + } + } + else + { + // I2C read-mode + uint8_t f_Stop = 0; + uint32_t addrReg = (((uint32_t) * pu8RegAddr) << 8) + (*(pu8RegAddr + 1)) + RAM_ADDR_BASE_SLAVE; + uint8_t *pData = (uint8_t *)&addrReg; + + do + { + // 等待TXE标志位被置位，表示发送缓冲区空闲 + if (I2C_SlavePollingFlag(I2Cx, I2C_IT_TXE_SLV) != I2C_Status_Success) + { + return I2C_Status_Timeout; // 超时错误 + } + + // 发送数据 + I2Cx->STDR = *pData++; + + if (I2C_SlaveGetFlag(I2Cx, I2C_IT_STOP_SLV)) + { + f_Stop = 1; + } + + } + while (f_Stop == 0); + + // 返回 NACK,释放总线 + if (1 == I2Cx->SCR1_f.ACKSTALL) + { + I2C_SlaveTxNAck(I2Cx, ENABLE); + } + + } + + return I2C_Status_Success; +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + __NOP(); + while(1); + /* USER CODE END 6 */ +} + +#endif + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/readme.txt new file mode 100644 index 0000000..de71bc2 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_Int/readme.txt @@ -0,0 +1,27 @@ +示例目的： + 采用中断方式，通过I2C接口， 实现I2C从设备功能，和I2C主机进行数据通信。 + +硬件资源： + 1. CW32L012C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟12分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. PB09/PB08设置为PUSH-PULL输出，驱动LED + +演示说明： + 1、采用默认时钟配置，初始化I2C为从机，400KHz。 + 2、程序流程：从机完成I2C从设备配置后，一直等待主机发送数据。 + 3、从机接收到数据后，自动保存到RAM目标地址:0x20000000 + 0x0800开始的数据区，LED1闪亮。 + 4、从机接收到主机读数据指令后，自动将RAM目标地址中的数据回传给主机。 + +使用说明： ++ EWARM + 1. 打开I2C_mcu_slave_Int.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开I2C_mcu_slave_Int.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/EWARM/I2C_mcu_slave_poll.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/EWARM/I2C_mcu_slave_poll.ewp new file mode 100644 index 0000000..0c378e5 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/EWARM/I2C_mcu_slave_poll.ewp @@ -0,0 +1,2278 @@ + + + + 2 + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gtim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_iwdt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_lpi2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_lvd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_opa.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_pwr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_ram.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_vc.c + + + + Startup + + $PROJ_DIR$\..\..\..\..\IDEsupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + $PROJ_DIR$\..\USER\src\main.c + + + Release + + ICCARM + + 31 + 0 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/EWARM/I2C_mcu_slave_poll.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/EWARM/I2C_mcu_slave_poll.eww new file mode 100644 index 0000000..98f98a3 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/EWARM/I2C_mcu_slave_poll.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\i2c_mcu_slave_poll.ewp + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/MDK/I2C_mcu_slave_poll.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/MDK/I2C_mcu_slave_poll.uvoptx new file mode 100644 index 0000000..4d97395 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/MDK/I2C_mcu_slave_poll.uvoptx @@ -0,0 +1,370 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + I2C_mcu_slave_poll + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC2000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC2000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + JL2CM3 + -U50120677 -O78 -S3 -ZTIFSpeedSel3000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC2000 -FN1 -FF0FlashCW32F030_64K+ -FS00 -FL012800 + + + + + + 0 + 1 + u8RegAddr + + + 1 + 1 + u8DataReceived + + + + + 1 + 0 + 0x20000004 + 0 + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_lpi2c.c + cw32l012_lpi2c.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/MDK/I2C_mcu_slave_poll.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/MDK/I2C_mcu_slave_poll.uvprojx new file mode 100644 index 0000000..078729e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/MDK/I2C_mcu_slave_poll.uvprojx @@ -0,0 +1,466 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + I2C_mcu_slave_poll + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012 -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + I2C_mcu_slave_poll + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IdeSupport\MDK;..\..\..\..\Libraries\inc;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + Project.sct + + + --keep=*Handler + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_lpi2c.c + 1 + ..\..\..\..\Libraries\src\cw32l012_lpi2c.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..15c90dc --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,88 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void NMI_Handler(void); +extern void HardFault_Handler(void); +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void WDT_IRQHandler(void); +extern void LVD_IRQHandler(void); +extern void RTC_IRQHandler(void); +extern void FLASHRAM_IRQHandler(void); +extern void SYSCTRL_IRQHandler(void); +extern void GPIOA_IRQHandler(void); +extern void GPIOB_IRQHandler(void); +extern void ADC_IRQHandler(void); +extern void ATIM_IRQHandler(void); +extern void VC1_IRQHandler(void); +extern void VC2_IRQHandler(void); +extern void GTIM1_IRQHandler(void); +extern void LPTIM_IRQHandler(void); +extern void BTIM1_IRQHandler(void); +extern void BTIM2_IRQHandler(void); +extern void BTIM3_IRQHandler(void); +extern void I2C1_IRQHandler(void); +extern void SPI1_IRQHandler(void); +extern void UART1_IRQHandler(void); +extern void UART2_IRQHandler(void); +extern void CLKFAULT_IRQHandler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/USER/inc/main.h new file mode 100644 index 0000000..ddca2e1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/USER/inc/main.h @@ -0,0 +1,82 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012.h" +#include "system_cw32l012.h" +#include "interrupts_cw32l012.h" +#include "base_types.h" + +#include "cw32l012_lpi2c.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_flash.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void I2C_ExceptionHandling(void); +uint8_t I2C_SlaveReceiveDataFromMaster(I2C_TypeDef *I2Cx, uint8_t *pu8RegAddr, I2C_SlaveRegAddrTypeDef u8RegAddrType,uint8_t *pu8Data, uint16_t *pu16Len); +uint8_t I2C_SlaveSendDataToMaster(I2C_TypeDef *I2Cx, uint8_t *pu8Data, uint16_t u16Len); +uint8_t I2C_SlaveReceiveSubAddressFromMaster(I2C_TypeDef *I2Cx, uint8_t *rxBuff, uint16_t *rxSize); + +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c0e8610 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupts_cw32l012.h" +#include "..\inc\main.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW32L012 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH12 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH34 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC13 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC24 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM34 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3_HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI23 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2_DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/USER/src/main.c new file mode 100644 index 0000000..fef286a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/USER/src/main.c @@ -0,0 +1,459 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2022-7-12 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +#define _MAIN + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//#define HSI48MHZ_EN + +#ifndef HSI48MHZ_EN +#define HSI8MHZ_EN +#endif + +//#define BAUD_RATE_100K_EN +//#define BAUD_RATE_1000K_EN + +//#define ADDR_SLAVE_10B_EN + +#define I2C1_SCL_GPIO_PORT CW_GPIOB +#define I2C1_SCL_GPIO_PIN GPIO_PIN_6 +#define I2C1_SDA_GPIO_PORT CW_GPIOB +#define I2C1_SDA_GPIO_PIN GPIO_PIN_7 + +#define I2C1_SCL_LOW() PB06_SETLOW() +#define I2C1_SDA_LOW() PB07_SETLOW() +#define I2C1_SCL_HIGH() PB06_SETHIGH() +#define I2C1_SDA_HIGH() PB07_SETHIGH() + +#define I2C1_SCL2GPIO() PB06_AFx_GPIO() +#define I2C1_SDA2GPIO() PB07_AFx_GPIO() +#define GPIO2I2C1_SCL() PB06_AFx_I2C1SCL() +#define GPIO2I2C1_SDA() PB07_AFx_I2C1SDA() + +#define DEV_ADDR_SLAVE_7B 0x70 //I2C从机设备地址：7bits. +#define DEV_ADDR_SLAVE_10B 0x3F0 //I2C从机设备地址：10bits. +#define RAM_ADDR_OFFSET_SLAVE 0x0800 //I2C从机RAM目标地址:0x20000000 + 0x0800. +#define RAM_ADDR_BASE_SLAVE 0x20000000 + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint8_t u8RegAddr[MAX_SIZE_SUBADDRESS]; +uint16_t u16LenReceive, u16LenSend; +uint32_t regBackup[5]; + +#if defined ( __CC_ARM ) +uint8_t u8DataReceived[2 + 16] __attribute__((at(RAM_ADDR_BASE_SLAVE + RAM_ADDR_OFFSET_SLAVE))); +#elif defined ( __ICCARM__ ) +uint8_t u8DataReceived[2 + 16 + 2] @ (RAM_ADDR_BASE_SLAVE + RAM_ADDR_OFFSET_SLAVE); +#elif defined ( __GNUC__ ) +uint8_t u8DataReceived[2 + 16] __attribute__((section(".ARM.__at_(RAM_ADDR_BASE_SLAVE + RAM_ADDR_OFFSET_SLAVE)"))); +#endif + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +static void GPIO_Configuration(void); +static void NVIC_Configuration(void); + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + * @brief main entry point for the application. + * + * @return int32_t + */ +int32_t main(void) +{ + I2C_SlaveConfigTypeDef I2C_InitStruct; + + // 时钟初始化 + SYSCTRL_Configuration(); + + // IO口初始化 + GPIO_Configuration(); + + I2C_DeInit(CW_I2C1); + + // I2C初始化 + I2C_SlaveInitDefault(&I2C_InitStruct); +#ifdef ADDR_SLAVE_10B_EN + I2C_InitStruct.I2C_Addr0 = DEV_ADDR_SLAVE_10B; + I2C_InitStruct.addressMatchMode = I2C_Addr0_10bit; +#else + I2C_InitStruct.I2C_Addr0 = DEV_ADDR_SLAVE_7B; +#endif + +#ifdef BAUD_RATE_100K_EN + I2C_InitStruct.clockHoldTime_ns = 250U; +#elif defined(BAUD_RATE_1000K_EN) + I2C_InitStruct.clockHoldTime_ns = 50U; +#else + I2C_InitStruct.clockHoldTime_ns = 100U; +#endif + + I2C_InitStruct.I2C_RegAddr = I2C_REG_ADDR_16BIT; + +#ifdef HSI48MHZ_EN + I2C_SlaveInit(CW_I2C1, &I2C_InitStruct, 48000000UL); // 初始化模块 +#else + I2C_SlaveInit(CW_I2C1, &I2C_InitStruct, 8000000UL); // 初始化模块 +#endif + + I2C_SlaveCmd(CW_I2C1, ENABLE); // I2C模块使能 + + if (I2C_SlavePollingFlag(CW_I2C1, I2C_IT_SLVBUSY_SLV) == I2C_Status_Success) + { + I2C_ExceptionHandling(); + } + + while (1) + { + uint32_t lenTemp; + + // 等主机写数据 + if(I2C_Status_Success == I2C_SlaveReceiveDataFromMaster(CW_I2C1, u8RegAddr, I2C_REG_ADDR_16BIT, u8DataReceived, &u16LenReceive)) + { + lenTemp = u16LenReceive; + // 等主机读数据 + while (I2C_Status_Success != I2C_SlaveReceiveDataFromMaster(CW_I2C1, u8RegAddr, I2C_REG_ADDR_16BIT, u8DataReceived, &u16LenReceive)) + { + I2C_SlaveClearFlag(CW_I2C1, ~CLEAR_IT_MASK_SLV); + } + I2C_SlaveSendDataToMaster(CW_I2C1, u8DataReceived, lenTemp); + I2C_SlaveClearFlag(CW_I2C1, ~CLEAR_IT_MASK_SLV); + PB09_TOG(); +#if 0 +#ifdef HSI48MHZ_EN + FirmwareDelay(3000); +#else + FirmwareDelay(500); // Ensure that all data has been sent from the slave. +#endif +#endif + + } + } +} + + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ +#ifdef HSI48MHZ_EN + __SYSCTRL_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_2); + CW_FLASH->CR2 |= (0x5A5A0000 | 0x18); // Enable FLASH Prefetch and Cache. + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV2); // 48MHz + __SYSCTRL_FLASH_CLK_DISABLE(); +#elif defined(HSI8MHZ_EN) + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); // 8MHz +#else + // Default HSI4MHz +#endif + __SYSCTRL_I2C1_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + + __SYSCTRL_GPIOB_CLK_ENABLE(); + + GPIO2I2C1_SCL(); + GPIO2I2C1_SDA(); + GPIO_InitStructure.Pins = I2C1_SCL_GPIO_PIN | I2C1_SDA_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_Init(I2C1_SCL_GPIO_PORT, &GPIO_InitStructure); + + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_8 | GPIO_PIN_9 ; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + + //LEDs are off. + PB09_SETLOW(); + PB08_SETLOW(); +} + +void I2C_ExceptionHandling(void) +{ + //异常处理 + //while(1); +} + +uint8_t I2C_SlaveReceiveDataFromMaster(I2C_TypeDef *I2Cx, uint8_t *pu8RegAddr, I2C_SlaveRegAddrTypeDef u8RegAddrType, uint8_t *pu8Data, uint16_t *pu16Len) +{ + uint8_t u8State; + uint16_t data0; + boolean_t modeRead; + uint8_t i, j; + + //清除I2C从机标志位 + I2C_SlaveClearFlag(I2Cx, ~CLEAR_IT_MASK_SLV); + // 使能应答标志 + I2C_SlaveTxNAck(I2Cx, DISABLE); + +#if 1 + // 查询等待 I2C_SISR.ADDR 变为 1 + while (I2C_SlavePollingFlag(I2Cx, I2C_IT_ADDR_SLV) != I2C_Status_Success) + { + ; + } + +#else + if (I2C_SlavePollingFlag(I2Cx, I2C_IT_ADDR_SLV) != I2C_Status_Success) + { + return I2C_Status_Timeout; // 超时错误 + } + +#endif + + data0 = (uint16_t)I2Cx->SASR_f.RADDR; // 读取 I2C_SASR 寄存器，自动清除 I2C_SISR.ADDR 标志 + modeRead = (boolean_t)(data0 & 0x01); + data0 = (uint16_t)(data0 >> 1); // 读取从机地址 + + //清除I2C从机标志位 + I2C_SlaveClearFlag(I2Cx, ~CLEAR_IT_MASK_SLV); + + u8State = I2C_SlaveReceive(I2Cx, pu8Data, pu16Len); + + if (u8State != I2C_Status_Success) + { + return u8State; + } + + if (modeRead == FALSE) + { + /*I2C write-mode: + Register address is at 1st or 1st & 2nd byte received; + Other bytes received are user data. + */ + // Save register address to local variable + *pu8RegAddr = *pu8Data; + + switch (u8RegAddrType) + { + case I2C_REG_ADDR_8BIT: + j = 1; + break; + case I2C_REG_ADDR_16BIT: + j = 2; + break; + case I2C_REG_ADDR_24BIT: + j = 3; + break; + case I2C_REG_ADDR_32BIT: + j = 4; + break; + default: + return I2C_Status_Error; + } + + if (j > 1) + { + if (*pu16Len >= j) // 检查是否有足够的数据长度 + { + i = j - 1; + while (i--) + { + ++pu8Data; + *(pu8RegAddr + 1) = *pu8Data; + } + } + else + { + return I2C_Status_Error; // 数据长度不足 + } + } + } + else + { + // I2C read-mode + uint8_t f_Stop = 0; + uint32_t addrReg = (((uint32_t) * pu8RegAddr) << 8) + (*(pu8RegAddr + 1)) + RAM_ADDR_BASE_SLAVE; + uint8_t *pData = (uint8_t *)&addrReg; + + do + { + // 等待TXE标志位被置位，表示发送缓冲区空闲 + if (I2C_SlavePollingFlag(I2Cx, I2C_IT_TXE_SLV) != I2C_Status_Success) + { + return I2C_Status_Timeout; // 超时错误 + } + + // 发送数据 + I2Cx->STDR = *pData++; + + if (I2C_SlaveGetFlag(I2Cx, I2C_IT_STOP_SLV)) + { + f_Stop = 1; + } + + } + while (f_Stop == 0); + + // 返回 NACK,释放总线 + if (1 == I2Cx->SCR1_f.ACKSTALL) + { + I2C_SlaveTxNAck(I2Cx, ENABLE); + } + + } + + return I2C_Status_Success; +} + +uint8_t I2C_SlaveSendDataToMaster(I2C_TypeDef *I2Cx, uint8_t *pu8Data, uint16_t u16Len) +{ + uint8_t u8State; + uint16_t data0; + + // 使能应答标志 + I2C_SlaveTxNAck(I2Cx, DISABLE); + +#if 1 + // 查询等待 I2C_SISR.RESTART 变为 1 + while (I2C_SlavePollingFlag(I2Cx, I2C_IT_RESTART_SLV | I2C_IT_ADDR_SLV) != I2C_Status_Success) + ; + +#else + if (I2C_SlavePollingFlag(I2Cx, I2C_IT_ADDR_SLV) != I2C_Status_Success) + { + return I2C_Status_Timeout; // 超时错误 + } + + data0 = (uint16_t)I2Cx->SASR_f.RADDR; // 读取 I2C_SASR 寄存器，自动清除 I2C_SISR.ADDR 标志 +#endif + + u8State = I2C_SlaveSend(I2Cx, pu8Data, u16Len); + + if (u8State != I2C_Status_Success) + { + return u8State; + } + + // 返回 NACK,释放总线 + if (1 == I2Cx->SCR1_f.ACKSTALL) + { + I2C_SlaveTxNAck(I2Cx, ENABLE); + } + + return I2C_Status_Success; +} + +uint8_t I2C_SlaveReceiveSubAddressFromMaster(I2C_TypeDef *I2Cx, uint8_t *rxBuff, uint16_t *rxSize) +{ + uint32_t dataTemp; + uint8_t *buf; + uint32_t cntRx = 0; + buf = rxBuff; + + do + { + if(I2C_SlaveGetFlag(I2Cx, I2C_IT_RXNE_SLV)) + { + dataTemp = I2Cx->SRDR; + + if (cntRx >= MAX_SIZE_SUBADDRESS) + { + // 缓冲区即将溢出，停止接收并返回错误 + *rxSize = cntRx; + return I2C_Status_FifoError; + } + + *buf++ = (uint8_t)dataTemp; + cntRx++; + } + + } + + while (I2C_SlaveGetFlag(I2Cx, I2C_IT_RESTART_SLV) == 0); + + *rxSize = cntRx; + return I2C_Status_Success; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + __NOP(); + while(1); + /* USER CODE END 6 */ +} + +#endif + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/readme.txt new file mode 100644 index 0000000..9db1f13 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/I2C/I2C_mcu_slave_poll/readme.txt @@ -0,0 +1,31 @@ +示例目的： + 采用查询方式，通过I2C接口， 实现I2C从设备功能，和I2C主机进行数据通信。 + +硬件资源： + 1. CW32L012C8T6 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟12分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. PB09/PB08设置为PUSH-PULL输出，驱动LED + +演示说明： + 1、采用默认时钟配置，初始化I2C为从机，400KHz，不使能I2C中断。 + 2、程序流程：从机完成I2C从设备配置后，一直等待主机发送数据。 + 3、从机接收到数据后，自动保存到RAM目标地址:0x20000000 + 0x0800开始的数据区，LED1闪亮。 + 4、从机接收到主机读数据指令后，自动将RAM目标地址中的数据回传给主机。 + +硬件连接： + LPI2C_MASTER SCL (PB06)-- LPI2C_SLAVE SCL (PB06) + LPI2C_MASTER SDA (PB07)-- LPI2C_SLAVE SDA (PB07) + +使用说明： ++ EWARM + 1. 打开I2C_mcu_slave_poll.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开I2C_mcu_slave_poll.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/EWARM/project.ewp new file mode 100644 index 0000000..769313f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/EWARM/project.ewp @@ -0,0 +1,2261 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_atim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gtim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_irmod.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/MDK/project.uvoptx new file mode 100644 index 0000000..302a247 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/MDK/project.uvoptx @@ -0,0 +1,401 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FN1 -FC1000 -FD20000000 -FF0FlashCW32L012_TEST -FL010000 -FS00 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_atim.c + cw32l012_atim.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_adc.c + cw32l012_adc.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gtim.c + cw32l012_gtim.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_irmod.c + cw32l012_irmod.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 12 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/MDK/project.uvprojx new file mode 100644 index 0000000..1160948 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/MDK/project.uvprojx @@ -0,0 +1,493 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_atim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_atim.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_adc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_adc.c + + + cw32l012_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gtim.c + + + cw32l012_irmod.c + 1 + ..\..\..\..\Libraries\src\cw32l012_irmod.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/USER/inc/main.h new file mode 100644 index 0000000..0b3e044 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/USER/inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_flash.h" +#include "cw32l012_iwdt.h" +#include "cw32l012_gpio.h" +#include "cw32l012_gtim.h" +#include "cw32l012_irmod.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/USER/src/main.c new file mode 100644 index 0000000..9f6a93a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/USER/src/main.c @@ -0,0 +1,263 @@ +/** + * @file main.c + * @brief 该文件是程序的入口点，包含主函数`main`以及一些辅助函数的实现 + * @author + * @date + * @version + * + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由 + * 此生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯 + * 源半导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明 + * 示或暗含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵 + * 权的保证或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带 + * 的或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金 + * 额的损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些 + * 或全部上述排除或限制可能并不适用于您。 + **/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define NEC_LEAD_HIGH_TIME 9000 // 引导码高电平时间（单位：us） +#define NEC_LEAD_LOW_TIME 4500 // 引导码低电平时间（单位：us） +#define NEC_BIT_HIGH_TIME 560 // 每个比特的高电平时间（单位：us） +#define NEC_BIT_LOW_TIME_0 560 // 逻辑0的低电平时间（单位：us） +#define NEC_BIT_LOW_TIME_1 1680 // 逻辑1的低电平时间（单位：us） +#define NEC_CARRIER_FREQ 38000 // 载波频率（单位：Hz） + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +static void GTIM1_Config(void); +static void GTIM3_Config(void); + +void IrDA_Send(const uint8_t *pData, uint16_t len); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +uint32_t DelayTime; +static uint8_t DataBuffer[10] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39}; + + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + /* GPIO Configuration */ + GPIO_Configuration(); + + GTIM1_Config(); + GTIM3_Config(); + + IRMOD_Config(IRMOD_GTIM1_CH1_AND_GTIM3_CH1, IRMOD_POLARITY_POSITIVE); + + /* NVIC Configuration */ + NVIC_Configuration(); + + while (1) + { + IrDA_Send(DataBuffer, 10); + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI96MHZ); + SYSCTRL_HCLKPRS_Config(SYSCTRL_HCLK_DIV1); + SYSCTRL_PCLKPRS_Config(SYSCTRL_PCLK_DIV1); + SYSCTRL_SystemCoreClockUpdate(96000000); +} + +/** + * @brief Configure the GPIO Pins. + * * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + __SYSCTRL_GPIOB_CLK_ENABLE(); + PB09_AFx_IROUT(); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_9; + + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); +} + + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + +} + +/** + * @brief GTIM1设置为PWM1，产生38KHz的载波 + * + */ +static void GTIM1_Config(void) +{ + GTIM_InitTypeDef GTIM_InitStruct = {0}; + GTIM_OCModeCfgTypeDef GTIM_OCModeCfgStruct; + + __SYSCTRL_GTIM1_CLK_ENABLE(); + + GTIM_InitStruct.AlignMode = GTIM_ALIGN_MODE_EDGE; + GTIM_InitStruct.ARRBuffState = GTIM_ARR_BUFF_DIS; + GTIM_InitStruct.Direction = GTIM_DIRECTION_UP; + GTIM_InitStruct.EventOption = GTIM_EVENT_NORMAL; + GTIM_InitStruct.Prescaler = 5; // 96MHz/(Prescaler+1) = 16MHz + GTIM_InitStruct.PulseMode = GTIM_PULSE_MODE_DIS; + GTIM_InitStruct.ReloadValue = 420; // 38kHz ReloadValue = 16000/38 -1 + GTIM_InitStruct.UpdateOption = GTIM_UPDATE_DIS; + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + + GTIM_OCModeCfgStruct.FastMode = ENABLE; + GTIM_OCModeCfgStruct.OCMode = GTIM_OC_MODE_PWM1; + GTIM_OCModeCfgStruct.OCPolarity = GTIM_OC_POLAR_NONINVERT; + GTIM_OCModeCfgStruct.PreloadState = ENABLE; + GTIM_OC1ModeCfg(CW_GTIM1, >IM_OCModeCfgStruct); + + GTIM_SetCompare1(CW_GTIM1, (GTIM_InitStruct.ReloadValue / 16) * 3); + GTIM_OC1Cmd(CW_GTIM1, ENABLE); +} + +/** + * @brief GTIM3设置为PWM2，控制高低电平的时常。 + * + */ +static void GTIM3_Config(void) +{ + GTIM_InitTypeDef GTIM_InitStruct = {0}; + GTIM_OCModeCfgTypeDef GTIM_OCModeCfgStruct; + + __SYSCTRL_GTIM3_CLK_ENABLE(); + + GTIM_InitStruct.AlignMode = GTIM_ALIGN_MODE_EDGE; + GTIM_InitStruct.ARRBuffState = GTIM_ARR_BUFF_EN; + GTIM_InitStruct.Direction = GTIM_DIRECTION_UP; + GTIM_InitStruct.EventOption = GTIM_EVENT_NORMAL; + GTIM_InitStruct.Prescaler = 95; // 96MHz/(Prescaler+1) = 1MHz + GTIM_InitStruct.PulseMode = GTIM_PULSE_MODE_EN; // 单次模式 + GTIM_InitStruct.ReloadValue = NEC_LEAD_HIGH_TIME + NEC_LEAD_LOW_TIME ; // 实际工作时会动态修改 + GTIM_InitStruct.UpdateOption = GTIM_UPDATE_EN; + GTIM_TimeBaseInit(CW_GTIM3, >IM_InitStruct); + + GTIM_OCModeCfgStruct.FastMode = DISABLE; + GTIM_OCModeCfgStruct.OCMode = GTIM_OC_MODE_PWM1; + GTIM_OCModeCfgStruct.OCPolarity = GTIM_OC_POLAR_NONINVERT; + GTIM_OCModeCfgStruct.PreloadState = ENABLE; + GTIM_OC1ModeCfg(CW_GTIM3, >IM_OCModeCfgStruct); + + GTIM_SetCompare1(CW_GTIM3, NEC_LEAD_HIGH_TIME); + GTIM_OC1Cmd(CW_GTIM3, ENABLE); + GTIM_Cmd(CW_GTIM3, ENABLE); +} + + + +void IrDA_Send(const uint8_t *pData, uint16_t len) +{ + uint8_t i; + + // 发送引导码 + CW_GTIM3->CNT = 0; + CW_GTIM3->CCR1 = NEC_LEAD_HIGH_TIME; + CW_GTIM3->ARR = NEC_LEAD_HIGH_TIME + NEC_LEAD_LOW_TIME; + + CW_GTIM3->ICR = 0x0000; + + GTIM_Cmd(CW_GTIM1, ENABLE); + GTIM_Cmd(CW_GTIM3, ENABLE); + while (!CW_GTIM3->ISR_f.UIF); + + while (len--) + { + for (i = 0; i < 8; i++) + { + if (*pData & (1 << i)) + { + CW_GTIM3->ICR = 0; + CW_GTIM3->CCR1 = NEC_BIT_HIGH_TIME; + CW_GTIM3->ARR = NEC_BIT_HIGH_TIME + NEC_BIT_LOW_TIME_1; + CW_GTIM3->CR1_f.CEN = 1; + while (!CW_GTIM3->ISR_f.UIF); + } + else + { + CW_GTIM3->ICR = 0; + CW_GTIM3->CCR1 = NEC_BIT_HIGH_TIME; + CW_GTIM3->ARR = NEC_BIT_HIGH_TIME + NEC_BIT_LOW_TIME_0; + CW_GTIM3->CR1_f.CEN = 1; + while (!CW_GTIM3->ISR_f.UIF); + } + } + } + + CW_GTIM3->CR1_f.CEN = 0; + CW_GTIM3->CR1_f.CEN = 0; + +} +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/readme.txt new file mode 100644 index 0000000..774c5c1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_tim/readme.txt @@ -0,0 +1,26 @@ +示例目的： + 演示GTIM1和GTIM3联合产生IrDA的输出波形 + +硬件资源： + 1. CW32L012 StarKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟，PCLK、HCLK不分频， + PCLK=HCLK=SysClk=96MHz + 4. GTIM1生成38kHz载波 + 5. GTIM3使用PWM模式调制GTIM1的38KHz载波。 + +演示说明： + PB9输出IrDA调制的波形。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/EWARM/project.ewp new file mode 100644 index 0000000..9837550 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/EWARM/project.ewp @@ -0,0 +1,2264 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_atim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gtim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_irmod.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/MDK/project.uvoptx new file mode 100644 index 0000000..2ddd4a9 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/MDK/project.uvoptx @@ -0,0 +1,430 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FN1 -FC1000 -FD20000000 -FF0FlashCW32L012_TEST -FL010000 -FS00 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + + 0 + 1 + ((IRMOD_TypeDef*) 0x40004080UL) + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\GTIM1 + 35905 + + + System Viewer\IRMOD + 35904 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_atim.c + cw32l012_atim.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_adc.c + cw32l012_adc.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gtim.c + cw32l012_gtim.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_irmod.c + cw32l012_irmod.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 13 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/MDK/project.uvprojx new file mode 100644 index 0000000..f24dc18 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/MDK/project.uvprojx @@ -0,0 +1,498 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_atim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_atim.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_adc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_adc.c + + + cw32l012_gtim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gtim.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_irmod.c + 1 + ..\..\..\..\Libraries\src\cw32l012_irmod.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/USER/inc/main.h new file mode 100644 index 0000000..65fb8b2 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/USER/inc/main.h @@ -0,0 +1,78 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_flash.h" +#include "cw32l012_iwdt.h" +#include "cw32l012_gpio.h" +#include "cw32l012_gtim.h" +#include "cw32l012_uart.h" +#include "cw32l012_irmod.h" + + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ +extern uint16_t ADC_ConvertedValue; +extern float ADC_ConvertedVoltage; +extern uint8_t ADC_ConvertedFlag; + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/USER/src/main.c new file mode 100644 index 0000000..ed9c0ef --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/USER/src/main.c @@ -0,0 +1,225 @@ +/** + * @file main.c + * @brief 该文件是程序的入口点，包含主函数`main`以及一些辅助函数的实现 + * @author + * @date + * @version + * + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由 + * 此生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯 + * 源半导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明 + * 示或暗含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵 + * 权的保证或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带 + * 的或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金 + * 额的损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些 + * 或全部上述排除或限制可能并不适用于您。 + **/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define BAUDRATE 115200 +#define BIT_PERIOD_ns (1000000000/BAUDRATE) +#define LOGIC_0_PERIOD_ns (BIT_PERIOD_ns * 3 / 16) // 3/16 ENDEC编码波形 + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +static void GTIM1_Config(void); +static void UART1_Config(void); + +void IrDA_Send(const uint8_t *pData, uint16_t len); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint32_t DelayTime; +static uint8_t DataBuffer[10] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39}; + + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + /* GPIO Configuration */ + GPIO_Configuration(); + + GTIM1_Config(); + UART1_Config(); + + IRMOD_Config(IRMOD_UART1_TXD_AND_GTIM1_CH2, IRMOD_POLARITY_POSITIVE); + + /* NVIC Configuration */ + NVIC_Configuration(); + + while (1) + { + IrDA_Send(DataBuffer, 10); + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI96MHZ); + SYSCTRL_HCLKPRS_Config(SYSCTRL_HCLK_DIV1); + SYSCTRL_PCLKPRS_Config(SYSCTRL_PCLK_DIV1); + SYSCTRL_SystemCoreClockUpdate(96000000); +} + +/** + * @brief Configure the GPIO Pins. * + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + __SYSCTRL_GPIOB_CLK_ENABLE(); + PB09_AFx_IROUT(); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_9; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); +} + + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + +} + +/** + * @brief GTIM1生成载波 + * + */ +static void GTIM1_Config(void) +{ + GTIM_InitTypeDef GTIM_InitStruct; + GTIM_OCModeCfgTypeDef GTIM_OCModeCfgStruct; + + __SYSCTRL_GTIM1_CLK_ENABLE(); + __SYSCTRL_GPIOA_CLK_ENABLE(); + + PA07_AFx_GTIM1CH2(); + PA07_DIGTAL_ENABLE(); + PA07_DIR_OUTPUT(); + PA07_PUSHPULL_ENABLE(); + + GTIM_InitStruct.AlignMode = GTIM_ALIGN_MODE_EDGE; + GTIM_InitStruct.ARRBuffState = GTIM_ARR_BUFF_EN; + GTIM_InitStruct.Direction = GTIM_DIRECTION_UP; + GTIM_InitStruct.EventOption = GTIM_EVENT_NORMAL; + GTIM_InitStruct.Prescaler = 0; // 1分频 + GTIM_InitStruct.PulseMode = GTIM_PULSE_MODE_DIS; + GTIM_InitStruct.ReloadValue = BIT_PERIOD_ns * 96 / 1000; + GTIM_InitStruct.UpdateOption = GTIM_UPDATE_DIS; + GTIM_TimeBaseInit(CW_GTIM1, >IM_InitStruct); + + GTIM_OCModeCfgStruct.FastMode = ENABLE; + GTIM_OCModeCfgStruct.OCMode = GTIM_OC_MODE_PWM1; + GTIM_OCModeCfgStruct.OCPolarity = GTIM_OC_POLAR_NONINVERT; + GTIM_OCModeCfgStruct.PreloadState = ENABLE; + + GTIM_OC2ModeCfg(CW_GTIM1, >IM_OCModeCfgStruct); + GTIM_SetCompare2(CW_GTIM1, LOGIC_0_PERIOD_ns * 96 /1000); + GTIM_OC2Cmd(CW_GTIM1, ENABLE); + + GTIM_Cmd(CW_GTIM1, ENABLE); +} + +static void UART1_Config(void) +{ + UART_InitTypeDef UART_InitStruct = {0}; + __SYSCTRL_UART1_CLK_ENABLE(); + __SYSCTRL_GPIOA_CLK_ENABLE(); + + PA02_AFx_UART1TXD(); + PA02_DIGTAL_ENABLE(); + PA02_DIR_OUTPUT(); + PA02_PUSHPULL_ENABLE(); + + UART_InitStruct.UART_BaudRate = 115200; + UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStruct.UART_Mode = UART_Mode_Tx; + UART_InitStruct.UART_Over = UART_Over_16; + UART_InitStruct.UART_Parity = UART_Parity_No; + UART_InitStruct.UART_Source = UART_Source_PCLK; + UART_InitStruct.UART_StartBit = UART_StartBit_LL; + UART_InitStruct.UART_StopBits = UART_StopBits_1; + UART_InitStruct.UART_UclkFreq = SystemCoreClock; + + UART_Init(CW_UART1, &UART_InitStruct); +} + + +void IrDA_Send(const uint8_t *pData, uint16_t len) +{ + while (len--) + { + UART_SendData(CW_UART1, *pData); + while (CW_UART1->ISR_f.TXBUSY) + ; + pData++; + } +} +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/readme.txt new file mode 100644 index 0000000..4cdb37c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IRDA/IrDA_uart/readme.txt @@ -0,0 +1,26 @@ +示例目的： + 演示GTIM1和UART1联合产生IrDA的输出波形 + +硬件资源： + 1. CW32L012 StarKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=96MHz + 4. GTIM1生成周期为8.68us，占空比为3/16的载波 + 5. UART1的波特率为115200，其TXD调制GTIM1的产生的载波。 + +演示说明： + PB9输出IrDA调制的波形。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/EWARM/project.ewp new file mode 100644 index 0000000..2a91467 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_iwdt.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/MDK/project.uvoptx new file mode 100644 index 0000000..452d7b6 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/MDK/project.uvoptx @@ -0,0 +1,371 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\IWDT + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_iwdt.c + cw32l012_iwdt.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/MDK/project.uvprojx new file mode 100644 index 0000000..13958f6 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/MDK/project.uvprojx @@ -0,0 +1,479 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_iwdt.c + 1 + ..\..\..\..\Libraries\src\cw32l012_iwdt.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/USER/inc/main.h new file mode 100644 index 0000000..ed94561 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/USER/inc/main.h @@ -0,0 +1,69 @@ +/** + * @file main.h + * @author WHXY + * @brief Header for main.c file. + * This file contains the common defines of the application. + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +//#include "device.h" + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_iwdt.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_flash.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..b0bd30b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/USER/src/interrupts_cw32l012.c @@ -0,0 +1,438 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + WDT_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/USER/src/main.c new file mode 100644 index 0000000..d1d01f0 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/USER/src/main.c @@ -0,0 +1,190 @@ +/** + * @file main.c + * @author WHXY + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IWDT_DURATION 250 // 250ms +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * @return int32_t + */ +int32_t main(void) +{ + IWDT_InitTypeDef IWDT_InitStruct = {0}; + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + /* GPIO Configuration */ + GPIO_Configuration(); + + SysTick_Config(SystemCoreClock / 1000 * 100); // 100ms + + IWDT_InitStruct.IWDT_ITState = ENABLE; + IWDT_InitStruct.IWDT_OverFlowAction = IWDT_OVERFLOW_ACTION_INT; + IWDT_InitStruct.IWDT_Pause = IWDT_SLEEP_PAUSE; + IWDT_InitStruct.IWDT_Prescaler = IWDT_Prescaler_DIV512; // IWDT使用RC10K为计时时钟，分频后计时间隔为51.2ms + IWDT_InitStruct.IWDT_ReloadValue = IWDT_1_SECS; // 对应512分频 + IWDT_InitStruct.IWDT_WindowValue = 0xFFF; + + IWDT_Init(&IWDT_InitStruct); + + IWDT_Cmd(); + while(!CW_IWDT->SR_f.RUN); + IWDT_Refresh(); + + /* NVIC Configuration */ + NVIC_Configuration(); + + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + /* HSI和 LSI使能 */ + + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI8MHZ); + //SYSCTRL_LSI_Enable( ); + + /* 1. 设置HCLK和PCLK的分频系数　*/ + SYSCTRL_HCLKPRS_Config(SYSCTRL_HCLK_DIV1); + SYSCTRL_PCLKPRS_Config(SYSCTRL_PCLK_DIV1); + + SYSCTRL_SystemCoreClockUpdate(8000000); + /* 2. 配置外设时钟 */ + __SYSCTRL_IWDT_CLK_ENABLE(); //使能IWDT模块 + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /* 配置PA1为按键输入 */ + + GPIO_InitStruct.IT = GPIO_IT_FALLING; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_1; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + + /* 配置PB09为LED1 */ + GPIO_InitStruct.Pins = GPIO_PIN_9 ; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(WDT_IRQn); + NVIC_SetPriority(GPIOA_IRQn, 0); + NVIC_SetPriority(SysTick_IRQn, 1); + NVIC_EnableIRQ(GPIOA_IRQn); + __enable_irq(); +} + +void SysTick_Handler(void) +{ + IWDT_Refresh(); + PB09_TOG(); +} + +void WDT_IRQHandlerCallBack(void) +{ + if (CW_IWDT->SR & IWDT_SR_OV_Msk) + { + IWDT_ClearOVFlag(); + PB09_TOG(); + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/readme.txt new file mode 100644 index 0000000..a8ff49f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_int/readme.txt @@ -0,0 +1,37 @@ +示例目的： + 模拟软件发生故障时，独立看门狗IWDT产生中断。 + +硬件资源： + 1. CW32L012F8P6 StartKit + 2. 时钟HSI + 3. 系统时钟由HSI提供，分频为8MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=8MHz + 4. IWDT的时钟为RC10K + 5. PB09设置为PUSH-PULL输出，驱动LED1 + 6. PA01设置为输入，作为按键KEY2的输入 + 7. 系统节拍定时器设置为100ms产生一次中断 + +演示说明： + 配置IWDT的分频比为最大512，则计数时钟的周期为51.2ms， 配置IWDT的ARR为19，即IWDT的计时时常为 + （19 + 1）* 51.2ms = 1024ms，并且溢出后产生中断，不复位。 + 系统节拍配置为每 100 ms 产生一个中断，中断复位程序中 LED1闪烁，并喂狗。 + 按键KEY2配置为在其下降沿上产生中断。 + 在 NVIC 中，将KEY2对应引脚的中断向量且优先级等于0，并且 SysTick 中断向量优先级设置为1 + （KEY2的中断优先于 SysTick 中断）。 + 按钮KEY2用于模拟软件故障：KEY2按下后，进入对应的中断服务程序，且中断标志 + 位不清零，CPU不会进入系统节拍中断服务程序，因此不会重载IWDT计数器。 + 当IWDT计数器溢出时，IWDT将产生一个中断。中断服务程序中LED1的状态翻转。 + 当程序正常运行时，LED1按5Hz频率闪烁，当按下KEY2后，LED1闪烁间隔变为1000ms。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/EWARM/project.ewp new file mode 100644 index 0000000..2a91467 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_iwdt.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/MDK/project.uvoptx new file mode 100644 index 0000000..44eedd7 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/MDK/project.uvoptx @@ -0,0 +1,382 @@ + + + + 1.0 + +
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_iwdt.c + 1 + ..\..\..\..\Libraries\src\cw32l012_iwdt.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/USER/inc/main.h new file mode 100644 index 0000000..f98e124 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/USER/inc/main.h @@ -0,0 +1,70 @@ +/** + * @file main.h + * @author WHXY + * @brief Header for main.c file. + * This file contains the common defines of the application. + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +//#include "device.h" + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_iwdt.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_flash.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/USER/src/main.c new file mode 100644 index 0000000..31f0b52 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/USER/src/main.c @@ -0,0 +1,180 @@ +/** + * @file main.c + * @author WHXY + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IWDT_DURATION 250 // 250ms +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * @return int32_t + */ +int32_t main(void) +{ + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + /* GPIO Configuration */ + GPIO_Configuration(); + + // 如果程序发生的看门狗复位，LED1常亮，并停止运行，需要手动NRST复位。 + if (SYSCTRL_GetRstFlag(SYSCTRL_RESETFLAG_IWDT )) + { + PB09_SETHIGH(); + SYSCTRL_ClearRstFlag(SYSCTRL_RESETFLAG_IWDT); + while(1); + } + + SysTick_Config(SystemCoreClock / 1000 * 250); // 250ms + + IWDT_SetPeriod(IWDT_2_SECS); + + NVIC_Configuration(); + + while(1) + { + + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + /* HSI和 LSI使能 */ + + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI8MHZ); + //SYSCTRL_LSI_Enable( ); + + /* 1. 设置HCLK和PCLK的分频系数　*/ + SYSCTRL_HCLKPRS_Config(SYSCTRL_HCLK_DIV1); + SYSCTRL_PCLKPRS_Config(SYSCTRL_PCLK_DIV1); + + SYSCTRL_SystemCoreClockUpdate(8000000); + + __SYSCTRL_IWDT_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + __SYSCTRL_GPIOA_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /* 配置PA1为按键输入 */ + + GPIO_InitStruct.IT = GPIO_IT_FALLING; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_1; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + + /* 配置PB09为LED1 */ + GPIO_InitStruct.Pins = GPIO_PIN_9 ; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init( CW_GPIOB, &GPIO_InitStruct); + + PB09_SETLOW(); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); +// NVIC_EnableIRQ(WDT_IRQn); + NVIC_SetPriority(GPIOA_IRQn, 0); + NVIC_SetPriority(SysTick_IRQn, 1); + NVIC_EnableIRQ(GPIOA_IRQn); + __enable_irq(); +} + +void SysTick_Handler(void) +{ + PB09_TOG(); + IWDT_Refresh(); +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/readme.txt new file mode 100644 index 0000000..c97ef4a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/IWDT/IWDT_reset/readme.txt @@ -0,0 +1,35 @@ +示例目的： + 模拟软件发生故障时，独立看门狗IWDT复位系统的功能。 + +硬件资源： + 1. CW32L012F8P6 StartKit + 2. 时钟HSI + 3. 系统时钟由HSI提供，分频为12，8MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=8MHz + 4. IWDT的时钟为RC10K + 5. PB09设置为PUSH-PULL输出，驱动LED1 + 6. PA01设置为输入，作为按键KEY2的输入 + 7. 系统节拍定时器设置为250ms产生一次中断 + +演示说明： + 配置IWDT的分频比为最大512，溢出时常设置为2秒。 + 系统节拍配置为每 250ms 产生一个中断，中断复位程序中 LED1闪烁，并喂狗。 + 按键KEY2配置为在其下降沿上产生中断。 + 在 NVIC 中，将KEY2对应引脚的中断向量且优先级等于0，并且 SysTick 中断向量优先级设置为1 + （KEY2的中断优先于 SysTick 中断）。 + 按钮KEY2用于模拟软件故障：KEY2按下后，进入对应的中断服务程序，且中断标志 + 位不清零，CPU不会进入系统节拍中断服务程序，因此不会重载IWDT计数器。 + 当IWDT计数器溢出时，IWDT将复位系统。程序发生IWDT复位后，LED1亮起后程序死循环，需通过按键复位恢复。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/EWARM/project.ewp new file mode 100644 index 0000000..147e4a6 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/EWARM/project.ewp @@ -0,0 +1,2255 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_lptim.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + + Utilities + + + doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/MDK/project.uvoptx new file mode 100644 index 0000000..f6a6a45 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/MDK/project.uvoptx @@ -0,0 +1,394 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FN1 -FC1000 -FD20000000 -FF0Flashcw32l012_TEST -FL010000 -FS00 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012_TEST.FLM) + + + 0 + CMSIS_AGDI + -X"CW-DAPLINK(CMSIS-DAP)" -U6713442356488877066CFF50 -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0Flashcw32l012_TEST.FLM -FS00 -FL010000 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=105,137,312,358,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + + 0 + 1 + CW_LCD->RAM[0] + + + + + 1 + 0 + CW_SYSCTRL + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\LPTIM + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_lptim.c + cw32l012_lptim.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + + + Utilities + 1 + 0 + 0 + 0 + + + + doc + 1 + 0 + 0 + 0 + + 5 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 6 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/MDK/project.uvprojx new file mode 100644 index 0000000..9c2561f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/MDK/project.uvprojx @@ -0,0 +1,491 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.3 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_lptim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_lptim.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + + + Utilities + + + doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/USER/inc/main.h new file mode 100644 index 0000000..1dc4d0a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/USER/inc/main.h @@ -0,0 +1,67 @@ +/** + * @file main.h + * @author WHXY + * @brief Header for main.c file. + * This file contains the common defines of the application. + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_flash.h" +#include "cw32l012_lptim.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..3ae7a7a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/USER/src/interrupts_cw32l012.c @@ -0,0 +1,441 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + if(CW_LPTIM->ISR_f.ARRM) + { + CW_LPTIM->ICR_f.ARRM = 0; + PB08_SETLOW(); + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/USER/src/main.c new file mode 100644 index 0000000..d8abccd --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/USER/src/main.c @@ -0,0 +1,195 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + * +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IWDT_DURATION 250 // 250ms + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void LPTIM_Configuration(void); +void LowPowerSetup(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +extern uint16_t Key1Count; + +/** + * @brief + * @return int32_t + */ +int32_t main(void) +{ + RCC_Configuration(); + + GPIO_Configuration(); + LPTIM_Configuration(); + NVIC_Configuration(); + + PB08_SETHIGH(); + + while (1) + { + + } +} + +void LPTIM_Configuration(void) +{ + LPTIM_InitTypeDef LPTIM_InitStruct = {0}; + __SYSCTRL_LPTIM_CLK_ENABLE(); + + LPTIM_InitStruct.LPTIM_ClockSource = LPTIM_CLOCK_SOURCE_CH1; + LPTIM_InitStruct.LPTIM_CounterMode = LPTIM_COUNTER_MODE_COUNT; + LPTIM_InitStruct.LPTIM_Period = 6; //计数10个脉冲，前3个脉冲用于内核配置，从第4个脉冲开始计数 + LPTIM_InitStruct.LPTIM_Prescaler = LPTIM_PRS_DIV1; + + LPTIM_Init(&LPTIM_InitStruct); + + LPTIM_ITConfig(LPTIM_IT_ARRM, ENABLE); + CW_LPTIM->ICR = 0x00; + + LPTIM_Cmd(ENABLE); + LPTIM_SelectOnePulseMode(LPTIM_OPERATION_SINGLE); +} + + +void LowPowerSetup(void) +{ + +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + /* 0. HSI使能并校准 */ + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); // HSIOSC的默认频率为96MHz 默认12分频 以频率8MHz提供给CPU + + /* 1. 设置HCLK和PCLK的分频系数　*/ + SYSCTRL_HCLKPRS_Config(SYSCTRL_HCLK_DIV1); + SYSCTRL_PCLKPRS_Config(SYSCTRL_PCLK_DIV1); + SYSCTRL_SystemCoreClockUpdate(8000000); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + // PB08用于指示灯 + __SYSCTRL_GPIOB_CLK_ENABLE(); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_8; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + + // PA02为LPTIM的CH1输入 + __SYSCTRL_GPIOA_CLK_ENABLE(); + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_2; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + + PA02_AFx_LPTIMCH1(); +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(LPTIM_IRQn); + __enable_irq(); +} + + +void LPTIM_IRQHandlerCallBack() +{ + if (CW_LPTIM->ISR & LPTIM_ISR_ARRM_Msk) + { + CW_LPTIM->ICR_f.ARRM = 0; + PB08_SETLOW(); + } +} + + + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/readme.txt new file mode 100644 index 0000000..413c1e9 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LPTIM/lptim_counter_mode/readme.txt @@ -0,0 +1,28 @@ +示例目的： + 演示LPTIM作为计数器的基本用法，对来自CH1的信号的脉冲个数进行计数。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟由HSI提供，12分频到8MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=8MHz + 4. PA02设置为LPTIM_CH1的复用功能 + 5. PB08设置为PUSH-PULL输出，驱动LED2 + +演示说明： + 系统时钟由HSI提供，频率为8 MHz。LPTIM的选择为计数模式，计数来源为CH1。ARR设置为6，使能ARRM的中断。 + LPTIM设置为单次运行模式，运行前LED2点亮，当计数满10个脉冲后，将产生一次ARRM的中断。 + 中断服务程序中将LED2熄灭。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/EWARM/project.ewp new file mode 100644 index 0000000..1f2dd4a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_lvd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/MDK/lvd_detect_falling_irq.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/MDK/lvd_detect_falling_irq.uvoptx new file mode 100644 index 0000000..2c23e6b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/MDK/lvd_detect_falling_irq.uvoptx @@ -0,0 +1,340 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012F8$Flash\FlashCW32L012_TEST.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 1 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 1 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_lvd.c + cw32l012_lvd.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/MDK/lvd_detect_falling_irq.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/MDK/lvd_detect_falling_irq.uvprojx new file mode 100644 index 0000000..48ee2ae --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/MDK/lvd_detect_falling_irq.uvprojx @@ -0,0 +1,479 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_lvd.c + 1 + ..\..\..\..\Libraries\src\cw32l012_lvd.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/USER/inc/main.h new file mode 100644 index 0000000..c1e83e8 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +void LVD_PortInit(void); +void LED_Init(void); +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..50fdf33 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/USER/src/interrupts_cw32l012.c @@ -0,0 +1,443 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +extern volatile boolean_t gFlagIrq; +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + gFlagIrq = CW_LVD->SR_f.INTF; + if(CW_LVD->SR_f.INTF) + { + CW_LVD->SR_f.INTF = 0; + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/USER/src/main.c new file mode 100644 index 0000000..db35b6a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/USER/src/main.c @@ -0,0 +1,163 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "cw32l012_systick.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_lvd.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +volatile boolean_t gFlagIrq = FALSE; + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief LVD I/O初始化 + * + */ +void LVD_PortInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + //打开GPIO时钟 + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + + //set PA08 as output + GPIO_InitStructure.Pins = GPIO_PIN_8; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOA, &GPIO_InitStructure); + //set PA08 as LVD output + PA08_AFx_LVDOUT(); + + //set PA00 as LVD source + PA00_ANALOG_ENABLE(); +} + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + LVD_InitTypeDef LVD_InitStruct = {0}; + + //配置测试IO口 + LVD_PortInit(); + + //LED初始化 + LED_Init(); + + LVD_InitStruct.LVD_Action = LVD_Action_Irq; //配置中断功能 + LVD_InitStruct.LVD_Source = LVD_Source_PA00; //配置LVD输入口 + LVD_InitStruct.LVD_Threshold = LVD_Threshold_2p2V; //配置LVD基准电压 + LVD_InitStruct.LVD_FilterClk = LVD_FilterClk_SYSCLK; + LVD_InitStruct.LVD_FilterTime = LVD_FilterTime_4N6; //fSAMPLING = fFLTCLK /4, N=6 + LVD_Init(&LVD_InitStruct); + + LVD_TrigConfig(LVD_TRIG_FALL, ENABLE); + LVD_EnableIrq(LVD_INT_PRIORITY); + LVD_ClearIrq(); + FirmwareDelay(4800); + LVD_Enable(); //LVD使能 + + while (1) + { + if (gFlagIrq) + { + PB09_TOG(); + gFlagIrq = FALSE; + } + } +} + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_9 ; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/readme.txt new file mode 100644 index 0000000..0d5545e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/LVD/lvd_detect_falling_irq/readme.txt @@ -0,0 +1,27 @@ +示例目的： + 演示LVD模块的下降沿触发中断功能。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟默认12分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. LVD的滤波时钟源为SYSCLK + 5. PB02设置为PUSH-PULL输出 + +演示说明： + LVD输入通道为PA00，输出端口为PA08，门限电压为2.2V。 + 外接可调直流电源，当LVD输入通道电压低于门限电压时刻，PB02输出电平翻转一次。 + LVD输入通道电压保持低于或者高于门限电压，PB02输出电平不变。 + +使用说明： ++ EWARM + 1. 打开lvd_detect_falling_irq.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开lvd_detect_falling_irq.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/EWARM/project.ewp new file mode 100644 index 0000000..6692d6c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_opa.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_adc.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/MDK/Project.uvoptx new file mode 100644 index 0000000..5deda9b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/MDK/Project.uvoptx @@ -0,0 +1,385 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + DLGUARM + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + + 1 + 0 + Avcc + 0 + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_opa.c + cw32l012_opa.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_adc.c + cw32l012_adc.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/MDK/Project.uvprojx new file mode 100644 index 0000000..01337e1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/MDK/Project.uvprojx @@ -0,0 +1,497 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_opa.c + 1 + ..\..\..\..\Libraries\src\cw32l012_opa.c + + + cw32l012_adc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_adc.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/USER/inc/main.h new file mode 100644 index 0000000..1341c24 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/USER/inc/main.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "cw32l012_opa.h" +#include "cw32l012_adc.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/USER/src/main.c new file mode 100644 index 0000000..039ac6b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Soft/USER/src/main.c @@ -0,0 +1,267 @@ +/** + ****************************************************************************** + * @file main.c + * @author AE Team + * @version 1.0 + * @date 2024-08-15 + * @brief 本样例演示 OPA 被 软件控制 校正的功能。 + * OPA1 工作于 PGAx8 模式，ADC1 采样 BGR1.2V、OPA1_INP3 和 OPA1_OUT, + * 软件控制OPA1校正。 + * + * 向OPA1_INP3(PB01)输入小于 Vcc/2 的电压，从OPA1_OUT(PB00)输出OPA1放大后的电压。 + * ADC1 采样并转换完成的结果存入RAM中 + * + * @note 硬件平台：CW32L012_StartKit_V1.0 + * + * + *****************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" +#include "cw32l012_startkit.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define DEBUG_UARTx CW_UART3 + + +#define TIMES 16 + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +static void OPA_Config(void); +static void ADC_Config(void); +static void Delay(uint16_t nCount); + +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ** + ******************************************************************************/ +int32_t main(void) +{ + uint32_t ResultBgr = 0; + uint32_t ResultOpaIn = 0; + uint32_t ResultOpaOut = 0; + char RAM_DisplayBuff[512]; + + memset(RAM_DisplayBuff, 0 , 512); + + // 初始化时钟为96MHz/12 = 8MHz； + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + + Bsp_Uart_Init(8000000,115200); + + // 配置ADC + ADC_Config(); + + //初始化OPA + OPA_Config(); + + // 启动OPA + OPA_Start(CW_OPA1); + while(1) + { + OPA_AutoZeroSoft_Start(CW_OPA1); // 启动软件校正 + FirmwareDelay(100); // 保持软件校正时间 + OPA_AutoZeroSoft_Stop(CW_OPA1); // 停止软件校正 + + ADC_SoftwareStartConvCmd(CW_ADC1, ENABLE); // 启动ADC + for (int i = 0; i < TIMES; i++) + { + while (ADC_GetITStatus(CW_ADC1, ADC_IT_EOS) == 0); // 等待EOS序列转换完成 + ADC_ClearITPendingAll(CW_ADC1); // 清除EOS序列转换完成 + + ResultBgr += ADC_GetConversionValue(CW_ADC1, ADC_RESULT_0); // 读出BGR1.2V的Code + ResultOpaIn += ADC_GetConversionValue(CW_ADC1,ADC_RESULT_2); // 读出OPA1_IN3的Code + ResultOpaOut += ADC_GetConversionValue(CW_ADC1, ADC_RESULT_1); // 读出OPA1_OUT的Code + } + ADC_SoftwareStartConvCmd(CW_ADC1, DISABLE); + + ResultBgr /= TIMES; + ResultOpaIn /= TIMES; + ResultOpaOut /= TIMES; + + float Avcc = 1253 * 4.095f / ResultBgr; // 获取AVCC的电压 + float OpaIn = Avcc * ResultOpaIn / 4095; // 计算出OPA_IN的电压 + float OpaOut = Avcc * ResultOpaOut / 4095; // 计算出OPA_OUT的电压 + + // 打印ADC转换的结果 + //sprintf(RAM_DisplayBuff,"BgrCode = 0x%04X OpaInCode = 0x%04X OpaInCode = 0x%04X\r\n", ResultBgr, ResultOpaIn, ResultOpaOut); + //sprintf(RAM_DisplayBuff+0x50,"AvccVol = %4.3fV OpaInVol = %4.3fV OpaOutVol = %4.3fV\r\n", Avcc , OpaIn, OpaOut); + FirmwareDelay(500000); + + printf("BgrCode = 0x%04X OpaInCode = 0x%04X OpaInCode = 0x%04X\r\n", ResultBgr, ResultOpaIn, ResultOpaOut); + printf("AvccVol = %4.3fV OpaInVol = %4.3fV OpaOutVol = %4.3fV\r\n", Avcc , OpaIn, OpaOut); + + ResultBgr = 0; + ResultOpaIn = 0; + ResultOpaOut = 0; + } + + +} + +static void ADC_Config(void) +{ + ADC_InitTypeDef ADC_InitStruct={0}; + + //是能ADC的APB时钟 + __SYSCTRL_ADC_CLK_ENABLE(); + + ADC_InitStruct.ADC_ClkDiv = ADC_Clk_Div8; // ADCCLK = 8MHz/8 = 1MHz + ADC_InitStruct.ADC_ConvertMode = ADC_ConvertMode_Continuous; // 持续转换模式 + ADC_InitStruct.ADC_SlaveMod = ADC_SlaveMode_Disable; // 关闭从模式 + ADC_InitStruct.ADC_SQREns = ADC_SqrEns0to2; // 配置转换序列通道0~2 + ADC_InitStruct.ADC_IN0.ADC_InputChannel = ADC_InputVref1P2; // 内部1.2V + ADC_InitStruct.ADC_IN0.ADC_SampTime = ADC_SampTime518Clk; // 1.2V采样时间要大于40us + ADC_InitStruct.ADC_IN1.ADC_InputChannel = ADC_InputCH8; // 配置序列通道1的模拟输入源为ADC_IN8(PB00)，OPA1OUT + ADC_InitStruct.ADC_IN1.ADC_SampTime = ADC_SampTime30Clk; + ADC_InitStruct.ADC_IN2.ADC_InputChannel = ADC_InputCH9; // 配置序列通道2的模拟输入源为ADC_IN9(PB01) OPA1INP3 + ADC_InitStruct.ADC_IN2.ADC_SampTime = ADC_SampTime30Clk; + + ADC_Init(CW_ADC1,&ADC_InitStruct); + ADC_Enable(CW_ADC1); +} + +static void OPA_Config(void) +{ + OPA_InitTypeDef OPA_InitStruct ={0}; + + //使能OPA的时钟 + __SYSCTRL_OPA_CLK_ENABLE(); + + //使能GPIO的时钟 + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + + AFx_OPA1INP3_PB01(); // 设置OPA1INP3_PB01为模式端口 + AFx_OPA1OUT_PB00(); // 设置OPA1OUT_PB00为模拟端口 + + OPA_InitStruct.InputP = OPA_INPUT_INP3; // 正端输入源来自INP3 + OPA_InitStruct.InputN = OPA_INPUT_NONE; // 负端输入源不连接IO + OPA_InitStruct.Bias = OPA_BIAS_8UA_4US; // BIAS电流为8uA, AZ需要4us + OPA_InitStruct.PgaGain = OPA_PGA_GAIN2; // 同相放大2倍 + OPA_InitStruct.WorkMode = OPA_WORKMODE_PGA; // PGA模式 + + OPA_Init(CW_OPA1, &OPA_InitStruct); +} + +PUTCHAR_PROTOTYPE +{ + UART_SendData(DEBUG_UARTx, (uint8_t)ch); + + while (UART_GetFlagStatus(DEBUG_UARTx, UART_FLAG_TXE) == RESET); + + return ch; +} + +size_t __write(int handle, const unsigned char * buffer, size_t size) +{ + size_t nChars = 0; + + if (buffer == 0) + { + /* + * This means that we should flush internal buffers. Since we + * don't we just return. (Remember, "handle" == -1 means that all + * handles should be flushed.) + */ + return 0; + } + + + for (/* Empty */; size != 0; --size) + { + UART_SendData(DEBUG_UARTx, *buffer++); + while (UART_GetFlagStatus(DEBUG_UARTx, UART_FLAG_TXE) == RESET); + ++nChars; + } + + return nChars; +} + +/** +* @brief 简单延时 + * + * @param nCount + */ +void Delay(__IO uint16_t nCount) +{ + /* Decrement nCount value */ + while (nCount != 0) + { + nCount--; + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/EWARM/project.ewp new file mode 100644 index 0000000..ed01a01 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_opa.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_adc.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/MDK/Project.uvoptx new file mode 100644 index 0000000..79db4ec --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/MDK/Project.uvoptx @@ -0,0 +1,373 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + + 1 + 0 + 0x001007C0 + 0 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_opa.c + cw32l012_opa.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_adc.c + cw32l012_adc.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/MDK/Project.uvprojx new file mode 100644 index 0000000..77d2c56 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/MDK/Project.uvprojx @@ -0,0 +1,479 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_opa.c + 1 + ..\..\..\..\Libraries\src\cw32l012_opa.c + + + cw32l012_adc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_adc.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/USER/inc/main.h new file mode 100644 index 0000000..1341c24 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/USER/inc/main.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "cw32l012_opa.h" +#include "cw32l012_adc.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/USER/src/main.c new file mode 100644 index 0000000..676e721 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_AutoZero_Trig_ByADC/USER/src/main.c @@ -0,0 +1,207 @@ +/** + ****************************************************************************** + * @file main.c + * @author AE Team + * @version 1.0 + * @date 2024-08-15 + * @brief 本样例演示 OPA 被硬件 ADC 触发校正的功能。 + * OPA1 工作于 PGAx8 模式，ADC1 采样 BGR1.2V、OPA1_INP3 和 OPA1_OUT, + * 软件控制OPA1校正。 + * + * 向OPA1_INP3(PB01)输入小于 Vcc/2 的电压，从OPA1_OUT(PB00)输出OPA1放大后的电压。 + * ADC1 采样并转换完成的结果存入RAM中 + * + * @note 硬件平台：CW32L012_StartKit_V1.0 + * + * + *****************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define TIMES 16 + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +static void OPA_Config(void); +static void ADC_Config(void); +static void Delay(uint16_t nCount); +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ** + ******************************************************************************/ +int32_t main(void) +{ + uint32_t ResultBgr = 0; + uint32_t ResultOpaIn = 0; + uint32_t ResultOpaOut = 0; + char RAM_DisplayBuff[200]; + + memset(RAM_DisplayBuff, 0 , 200); + + // 初始化时钟为96MHz/12 = 8MHz； + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + + // 配置ADC + ADC_Config(); + + //初始化OPA + OPA_Config(); + + // 启动OPA + OPA_Start(CW_OPA1); + while(1) + { + ADC_SoftwareStartConvCmd(CW_ADC1, ENABLE); // 启动ADC + for (int i = 0; i < TIMES; i++) + { + while (ADC_GetITStatus(CW_ADC1, ADC_IT_EOS) == 0); // 等待EOS序列转换完成 + ADC_ClearITPendingAll(CW_ADC1); // 清除EOS序列转换完成 + + ResultBgr += ADC_GetConversionValue(CW_ADC1, ADC_RESULT_0); // 读出BGR1.2V的Code + ResultOpaIn += ADC_GetConversionValue(CW_ADC1,ADC_RESULT_2); // 读出OPA1_IN3的Code + ResultOpaOut += ADC_GetConversionValue(CW_ADC1, ADC_RESULT_1); // 读出OPA1_OUT的Code + } + ADC_SoftwareStartConvCmd(CW_ADC1, DISABLE); + + ResultBgr /= TIMES; + ResultOpaIn /= TIMES; + ResultOpaOut /= TIMES; + + float Avcc = 1253 * 4.095f / ResultBgr; // 获取AVCC的电压 + float OpaIn = Avcc * ResultOpaIn / 4095; // 计算出OPA_IN的电压 + float OpaOut = Avcc * ResultOpaOut / 4095; // 计算出OPA_OUT的电压 + + // 打印ADC转换的结果 + sprintf(RAM_DisplayBuff,"BgrCode = 0x%04X OpaInCode = 0x%04X OpaInCode = 0x%04X\r\n", ResultBgr, ResultOpaIn, ResultOpaOut); + sprintf(RAM_DisplayBuff+0x50,"AvccVol = %4.3fV OpaInVol = %4.3fV OpaOutVol = %4.3fV\r\n", Avcc , OpaIn, OpaOut); + Delay(50000); + } +} + +static void ADC_Config(void) +{ + ADC_InitTypeDef ADC_InitStruct={0}; + + //是能ADC的APB时钟 + __SYSCTRL_ADC_CLK_ENABLE(); + + ADC_InitStruct.ADC_ClkDiv = ADC_Clk_Div8; // ADCCLK = 8MHz/8 = 1MHz + ADC_InitStruct.ADC_ConvertMode = ADC_ConvertMode_Continuous; // 持续转换模式 + ADC_InitStruct.ADC_SlaveMod = ADC_SlaveMode_Disable; // 关闭从模式 + ADC_InitStruct.ADC_SQREns = ADC_SqrEns0to2; // 配置转换序列通道0~2 + ADC_InitStruct.ADC_IN0.ADC_InputChannel = ADC_InputVref1P2; // 内部1.2V + ADC_InitStruct.ADC_IN0.ADC_SampTime = ADC_SampTime262Clk; // 1.2V采样时间要大于40us + ADC_InitStruct.ADC_IN1.ADC_InputChannel = ADC_InputCH8; // 配置序列通道1的模拟输入源为ADC_IN8(PB00)，OPA1OUT + ADC_InitStruct.ADC_IN1.ADC_SampTime = ADC_SampTime12Clk; + ADC_InitStruct.ADC_IN2.ADC_InputChannel = ADC_InputCH9; // 配置序列通道2的模拟输入源为ADC_IN9(PB01) OPA1INP3 + ADC_InitStruct.ADC_IN2.ADC_SampTime = ADC_SampTime12Clk; + + ADC_Init(CW_ADC1,&ADC_InitStruct); + ADC_Enable(CW_ADC1); +} + +static void OPA_Config(void) +{ + OPA_InitTypeDef OPA_InitStruct ={0}; + + //使能OPA的时钟 + __SYSCTRL_OPA_CLK_ENABLE(); + + //使能GPIO的时钟 + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + + AFx_OPA1INP3_PB01(); // 设置OPA1INP3_PB01为模式端口 + AFx_OPA1OUT_PB00(); // 设置OPA1OUT_PB00为模拟端口 + + OPA_InitStruct.InputP = OPA_INPUT_INP3; // 正端输入源来自INP3 + OPA_InitStruct.InputN = OPA_INPUT_NONE; // 负端输入源不连接IO + OPA_InitStruct.Bias = OPA_BIAS_8UA_4US; // BIAS电流为8uA, AZ需要4us + OPA_InitStruct.PgaGain = OPA_PGA_GAIN2; // 同相放大2倍 + OPA_InitStruct.WorkMode = OPA_WORKMODE_PGA; // PGA模式 + + OPA_Init(CW_OPA1, &OPA_InitStruct); + // 使用ADC1Start信号触发OPA校正，需要配置ADC的SAM时间超过OPA的AZ时间 + OPA_AutoZeroTrig_Config(CW_OPA1, OPA_AZCLOCK_PCLK_DIV8, OPA_AZPERIOD_AZCLK64, OPA_AZTRIGSRC_ADC1START); +} + +/** +* @brief 简单延时 + * + * @param nCount + */ +void Delay(__IO uint16_t nCount) +{ + /* Decrement nCount value */ + while (nCount != 0) + { + nCount--; + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/EWARM/project.ewp new file mode 100644 index 0000000..ed01a01 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + 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+ 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_opa.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_adc.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/MDK/Project.uvoptx new file mode 100644 index 0000000..b448e7d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/MDK/Project.uvoptx @@ -0,0 +1,392 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + -UAny -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ST-LINKIII-KEIL_SWO + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FN1 -FC1000 -FD20000000 -FF0FlashCW32L012 -FL010000 -FS00 -FP0($$Device:CW32L012F8$Flash\FlashCW32L012.FLM) + + + 0 + DLGTARM + (1010=75,104,486,606,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 1 + 8 + RAM_DisplayBuff + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\ADC1 + 35903 + + + System Viewer\OPA1 + 35904 + + + System Viewer\SYSCTRL + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_opa.c + cw32l012_opa.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_adc.c + cw32l012_adc.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/MDK/Project.uvprojx new file mode 100644 index 0000000..3064e40 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/MDK/Project.uvprojx @@ -0,0 +1,488 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_opa.c + 1 + ..\..\..\..\Libraries\src\cw32l012_opa.c + + + cw32l012_adc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_adc.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/USER/inc/main.h new file mode 100644 index 0000000..1341c24 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/USER/inc/main.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "cw32l012_opa.h" +#include "cw32l012_adc.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/USER/src/main.c new file mode 100644 index 0000000..dfca365 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/OPA/OPA_StandAlone/USER/src/main.c @@ -0,0 +1,144 @@ +/** + ****************************************************************************** + * @file main.c + * @author AE Team + * @version 1.0 + * @date 2024-08-15 + * @brief 本样例演示OPA的独立运放功能 + * 由于开发板没有OPA的外围电路，因此只做代码配置演示，不做功能演示。 + * + * @note 硬件平台：CW32L012_StartKit_V1.0 + * + * + *****************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +static void OPA_Config(void); +static void Delay(uint16_t nCount); +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ** + ******************************************************************************/ +int32_t main(void) +{ + // 初始化时钟为96MHz/12 = 8MHz； + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + + //初始化OPA + OPA_Config(); + + // 启动OPA + OPA_Start(CW_OPA1); + while(1) + { + } +} + +static void OPA_Config(void) +{ + OPA_InitTypeDef OPA_InitStruct ={0}; + + //使能OPA的时钟 + __SYSCTRL_OPA_CLK_ENABLE(); + + //使能GPIO的时钟 + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + + AFx_OPA1INP3_PB01(); // 设置OPA1INP3_PB01为模式端口 + AFx_OPA1INN2_PA07(); // 设置OPA1INN2_PA07为模拟端口 + AFx_OPA1OUT_PB00(); // 设置OPA1OUT_PB00为模拟端口 + + OPA_InitStruct.InputP = OPA_INPUT_INP3; // 正端输入源来自INP3 + OPA_InitStruct.InputN = OPA_INPUT_INN2; // 负端输入源不连接IO + OPA_InitStruct.Bias = OPA_BIAS_8UA_4US; // BIAS电流为8uA, AZ需要4us + OPA_InitStruct.WorkMode = OPA_WORKMODE_STANDALONE; // 独立运放模式，由外部电阻决定电路类型 + + OPA_Init(CW_OPA1, &OPA_InitStruct); +} + +/** +* @brief 简单延时 + * + * @param nCount + */ +void Delay(__IO uint16_t nCount) +{ + /* Decrement nCount value */ + while (nCount != 0) + { + nCount--; + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT + /** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/EWARM/project.ewp new file mode 100644 index 0000000..6a4fae6 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/EWARM/project.ewp @@ -0,0 +1,2258 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/MDK/rcc_hsi_hse.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/MDK/rcc_hsi_hse.uvoptx new file mode 100644 index 0000000..3d44972 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/MDK/rcc_hsi_hse.uvoptx @@ -0,0 +1,340 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012 -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + + + Doc + 0 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/MDK/rcc_hsi_hse.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/MDK/rcc_hsi_hse.uvprojx new file mode 100644 index 0000000..969c404 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/MDK/rcc_hsi_hse.uvprojx @@ -0,0 +1,488 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + rcc_hsi_hse + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/USER/inc/main.h new file mode 100644 index 0000000..1e47386 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/USER/src/main.c new file mode 100644 index 0000000..78dcefe --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/USER/src/main.c @@ -0,0 +1,190 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_flash.h" +#include "cw32l012_systick.h" + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample HSI switch to HSE, HSE switch to HSI. + ** + ******************************************************************************/ +int32_t main(void) +{ + uint8_t res = 0; + GPIO_InitTypeDef GPIO_InitStruct; + + // HSE PIN config + GPIO_InitStruct.Pins = HSE_PIN_IN | HSE_PIN_OUT; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_Init(HSE_PIN_PORT, &GPIO_InitStruct); + + // PCLK PIN Config + GPIO_InitStruct.Pins = PCLK_OUT_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(PCLK_OUT_PIN_PORT, &GPIO_InitStruct); + GPIO_SetAlternateFunction(PCLK_OUT_PIN_PORT, PCLK_OUT_PIN, PCLK_OUT_PIN_AF); + + // MCO PIN Config + GPIO_InitStruct.Pins = MCO_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(MCO_PIN_PORT, &GPIO_InitStruct); + GPIO_SetAlternateFunction(MCO_PIN_PORT, MCO_PIN, MCO_PIN_AF); + + // LED init + Bsp_Led_Init(&LED1); + Bsp_Led_Init(&LED2); + + while (1) + { + //============================================================================ + //以下从HSI切换到HSE + SYSCTRL_HSE_Enable( SYSCTRL_HSE_MODE_OSC, 16000000, SYSCTRL_HSE_DRIVER_LEVEL5, 0); //开外部高速时钟，实际频率需要根据实际晶体频率重新配置 + res = SYSCTRL_SysClk_Switch( SYSCTRL_SYSCLKSRC_HSE ); //切换系统时钟到外部高速时钟 + + if ( res == 0x00 ) //切换系统时钟成功 + { + SYSCTRL_HSI_Disable(); + CW_SYSCTRL->MCO_f.SOURCE = 5;//MCO时钟源为HSE，通过MCO_PIN输出来观察HSE + InitTick(16000000); + res = 10; + + while (res--) + { + Bsp_Led_On(&LED1); + SysTickDelay(100); + Bsp_Led_Off(&LED1); + SysTickDelay(100); + } + + } + else + { + while (1) + { + Bsp_Led_On(&LED1); + SysTickDelay(1000); + Bsp_Led_Off(&LED1); + SysTickDelay(1000); + } + } + + + //============================================================================ + //以下从HSE切换到HSI + SYSCTRL_HSI_Enable( SYSCTRL_HSIOSC_DIV24 ); //开启内部高速时钟HSI = HSIOSC / 24 + res = SYSCTRL_SysClk_Switch( SYSCTRL_SYSCLKSRC_HSI ); //切换系统时钟到内部高速时时钟 + + if ( res == 0x00 ) //切换系统时钟成功 + { + SYSCTRL_HSE_Disable(); + CW_SYSCTRL->MCO_f.SOURCE = 3;//MCO时钟源为HSIOSC，通过PB03的MCO输出来观察HSIOSC + InitTick(4000000); + res = 10; + + while (res--) + { + Bsp_Led_On(&LED1); + SysTickDelay(400); + Bsp_Led_Off(&LED1); + SysTickDelay(400); + } + } + else + { + while (1) + { + Bsp_Led_On(&LED1); + SysTickDelay(1000); + Bsp_Led_Off(&LED1); + SysTickDelay(1000); + } + } + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/readme.txt new file mode 100644 index 0000000..eebbd71 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_hse/readme.txt @@ -0,0 +1,26 @@ +示例目的： + 系统时钟源在HSI和HSE之间进行切换。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI和HSE + 3. HSI作为系统时钟时，默认SysClk为4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz。 + 4. HSE作为系统时钟时，16MHz。PCLK、HCLK不分频，PCLK=HCLK=SysClk=16MHz。 + +演示说明： + 程序循环在HSI和HSE时钟之间进行切换，LED1先以HSI做延时闪烁10次后，切换成HSE做时钟， + LED1再闪烁次，如此循环，可明显看到使用HSI和HSE时，LED2的闪烁频率不一样。 + 如果切换失败，则LED1灯会慢闪（约1S亮，1S熄）。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开rcc_hsi_hse.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/EWARM/project.ewp new file mode 100644 index 0000000..dc53207 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/EWARM/project.ewp @@ -0,0 +1,2255 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/MDK/rcc_hsi_lse.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/MDK/rcc_hsi_lse.uvoptx new file mode 100644 index 0000000..6048c66 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/MDK/rcc_hsi_lse.uvoptx @@ -0,0 +1,328 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012 -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 0 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/MDK/rcc_hsi_lse.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/MDK/rcc_hsi_lse.uvprojx new file mode 100644 index 0000000..e4e6e99 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/MDK/rcc_hsi_lse.uvprojx @@ -0,0 +1,474 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/USER/inc/main.h new file mode 100644 index 0000000..1e47386 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/USER/src/main.c new file mode 100644 index 0000000..6e3fc76 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/USER/src/main.c @@ -0,0 +1,180 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_systick.h" + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample HSI switch to LSI, LSI switch to HSI. + ** + ******************************************************************************/ +int32_t main(void) +{ + uint8_t res = 0U; + + GPIO_InitTypeDef GPIO_InitStruct; + + // LSE PIN config + GPIO_InitStruct.Pins = LSE_PIN_IN | LSE_PIN_OUT; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_Init(LSE_PIN_PORT, &GPIO_InitStruct); + + // PCLK PIN Config + GPIO_InitStruct.Pins = PCLK_OUT_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(PCLK_OUT_PIN_PORT, &GPIO_InitStruct); + GPIO_SetAlternateFunction(PCLK_OUT_PIN_PORT, PCLK_OUT_PIN, PCLK_OUT_PIN_AF); + + // MCO PIN Config + GPIO_InitStruct.Pins = MCO_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(MCO_PIN_PORT, &GPIO_InitStruct); + GPIO_SetAlternateFunction(MCO_PIN_PORT, MCO_PIN, MCO_PIN_AF); + + // LED init + Bsp_Led_Init(&LED1); + Bsp_Led_Init(&LED2); + + while (1) + { + //============================================================================ + //以下从HSI切换到LSE + SYSCTRL_LSE_Enable( SYSCTRL_LSE_MODE_OSC, SYSCTRL_LSE_DRIVER_LEVEL5); //开外部高速时钟LSE + res = SYSCTRL_SysClk_Switch( SYSCTRL_SYSCLKSRC_LSE ); //切换系统时钟到LSE + + if ( res == 0x00 ) //切换系统时钟成功 + { + SYSCTRL_HSI_Disable(); //切换时钟到LSE后关闭源时钟HSI + CW_SYSCTRL->MCO_f.SOURCE = 6;//MCO时钟源为LSE，通过MCO_PIN输出来观察LSE + res = 10; + + while (res--) + { + Bsp_Led_On(&LED1); + FirmwareDelay(1000); + Bsp_Led_Off(&LED1); + FirmwareDelay(1000); + } + } + else + { + while (1) + { + Bsp_Led_On(&LED1); + } + } + + //============================================================================ + //以下从LSE切换到HSI + SYSCTRL_HSI_Enable( SYSCTRL_HSIOSC_DIV24 ); //开内部高速时钟HSI = HSIOSC / 24 + res = SYSCTRL_SysClk_Switch( SYSCTRL_SYSCLKSRC_HSI ); //切换系统时钟到HSI + + if ( res == 0x00 ) //切换系统时钟成功 + { + SYSCTRL_LSE_Disable(); //切换时钟到HSI后关闭LSE时钟 + CW_SYSCTRL->MCO_f.SOURCE = 3;//MCO时钟源为HSIOSC，通过PB03的MCO输出来观察HSIOSC + res = 10; + + while (res--) + { + Bsp_Led_On(&LED1); + FirmwareDelay(40000); + Bsp_Led_Off(&LED1); + FirmwareDelay(40000); + } + } + else + { + while (1) + { + Bsp_Led_On(&LED1); + } + } + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/readme.txt new file mode 100644 index 0000000..514e65a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_hsi_lse/readme.txt @@ -0,0 +1,25 @@ +示例目的： + 系统时钟源在HSI和LSE之间进行切换。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI和LSI + 3. HSI作为系统时钟时，设置为HSIOSC到HSI时钟的分频比为24，则SysClk为4MHz， + PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + 4. LSE作为系统时钟时，32.768K。PCLK、HCLK不分频，PCLK=HCLK=SysClk=32.768KHz。 + +演示说明： + 程序循环在HSI和LSE时钟之间进行切换，可看到在不同时钟下，LED1闪烁频率不一样，如果切换失败，则LED1灯常亮。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开rcc_hsi_lse.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/EWARM/project.ewp new file mode 100644 index 0000000..c8d6066 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/EWARM/project.ewp @@ -0,0 +1,2258 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/MDK/rcc_mco.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/MDK/rcc_mco.uvoptx new file mode 100644 index 0000000..29c5a1c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/MDK/rcc_mco.uvoptx @@ -0,0 +1,400 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012 -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM)) + + + + + 0 + 0 + 157 + 1 +
2976
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\project\../USER/src/main.c\157 + + + + + 1 + 0 + 0x001007c0 + 0 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\GPIOA + 35904 + + + System Viewer\SYSCTRL + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 1 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 4 + 9 + 1 + 1 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 5 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/MDK/rcc_mco.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/MDK/rcc_mco.uvprojx new file mode 100644 index 0000000..f3d32b4 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/MDK/rcc_mco.uvprojx @@ -0,0 +1,488 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + rcc_mco + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/USER/inc/main.h new file mode 100644 index 0000000..fc4e141 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_gpio.h" +#include "cw32l012_systick.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/USER/src/main.c new file mode 100644 index 0000000..b44047d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/USER/src/main.c @@ -0,0 +1,178 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "cw32l012_sysctrl.h" + + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle MCO + ** + ******************************************************************************/ +int32_t main(void) +{ + PLL_InitTypeDef PLL_InitStruct = { .ClockSource = SYSCTRL_PLL_SOURCE_HSE, + .PLL_OutFreq = 64000000, + .SourceFreq = 16000000, + .WaitCycle = SYSCTRL_PLL_WAIT_CYCLE_2048}; + Bsp_Key_Init(&KEY1); + InitTick(4000000); + + while (1) + { + + /******************************************************************** + 1. MCO toggle HCLK Test. MCO_CLK = HCLK + *******************************************************************/ + SYSCTRL_MCO_OUT( SYSCTRL_MCO_SRC_HCLK, SYSCTRL_MCO_DIV1 ); + + while (Bsp_Read_Key(&KEY1) == KEY_STATE_RELEASED); + SysTickDelay(50); + while (Bsp_Read_Key(&KEY1) == KEY_STATE_PRESSED); + + + /******************************************************************** + 2. MCO toggle PCLK Test. MCO_CLK = PCLK / 2 + *******************************************************************/ + SYSCTRL_MCO_OUT( SYSCTRL_MCO_SRC_PCLK, SYSCTRL_MCO_DIV2 ); + + while (Bsp_Read_Key(&KEY1) == KEY_STATE_RELEASED); + SysTickDelay(50); + while (Bsp_Read_Key(&KEY1) == KEY_STATE_PRESSED); + + /******************************************************************** + 3. MCO toggle HSI Test. MCO_CLK = HSIOSC / 8 + *******************************************************************/ + SYSCTRL_MCO_OUT( SYSCTRL_MCO_SRC_HSI, SYSCTRL_MCO_DIV8 ); + + while (Bsp_Read_Key(&KEY1) == KEY_STATE_RELEASED); + SysTickDelay(50); + while (Bsp_Read_Key(&KEY1) == KEY_STATE_PRESSED); + + /******************************************************************** + 4. MCO toggle LSI Test. MCO_CLK = LSI / 64 + *******************************************************************/ + SYSCTRL_LSI_Enable(); + SYSCTRL_MCO_OUT( SYSCTRL_MCO_SRC_LSI, SYSCTRL_MCO_DIV64 ); + + while (Bsp_Read_Key(&KEY1) == KEY_STATE_RELEASED); + SysTickDelay(50); + while (Bsp_Read_Key(&KEY1) == KEY_STATE_PRESSED); + + /******************************************************************** + 5. MCO toggle HSE Test. MCO_CLK = HSE / 128 + *******************************************************************/ + SYSCTRL_HSE_Enable( SYSCTRL_HSE_MODE_OSC, 16000000, SYSCTRL_HSE_DRIVER_LEVEL5, SYSCTRL_HSE_FLT_CLOSE); + SYSCTRL_MCO_OUT( SYSCTRL_MCO_SRC_HSE, SYSCTRL_MCO_DIV128 ); + + while (Bsp_Read_Key(&KEY1) == KEY_STATE_RELEASED); + SysTickDelay(50); + while (Bsp_Read_Key(&KEY1) == KEY_STATE_PRESSED); + + + /******************************************************************** + 6. MCO toggle LSE Test. MCO_CLK = LSE / 256 + *******************************************************************/ + SYSCTRL_LSE_Enable(SYSCTRL_LSE_MODE_OSC, SYSCTRL_LSE_DRIVER_LEVEL2); + SYSCTRL_MCO_OUT( SYSCTRL_MCO_SRC_LSE, SYSCTRL_MCO_DIV256 ); + + while (Bsp_Read_Key(&KEY1) == KEY_STATE_RELEASED); + SysTickDelay(50); + while (Bsp_Read_Key(&KEY1) == KEY_STATE_PRESSED); + /******************************************************************** + 7. MCO toggle PLL Test. MCO_CLK = PLL / 512 + *******************************************************************/ + SYSCTRL_PLL_Enable(&PLL_InitStruct); + SYSCTRL_MCO_OUT( SYSCTRL_MCO_SRC_PLL, SYSCTRL_MCO_DIV512 ); + + while (Bsp_Read_Key(&KEY1) == KEY_STATE_RELEASED); + SysTickDelay(50); + while (Bsp_Read_Key(&KEY1) == KEY_STATE_PRESSED); + + + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/readme.txt new file mode 100644 index 0000000..80af577 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_mco/readme.txt @@ -0,0 +1,25 @@ +示例目的： + 利用MCO时钟输出功能将各种所需要观测的时钟从PA04引脚输出，用户可根据需要修改时钟源和分频比。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟24分频，4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + 4. PA00配置为浮空输入作为按键KEY1使用 + +演示说明： + 采用默认时钟配置，并设置MCO时钟输出，用户按下KEY1后，程序循环修改时钟源和分频比，用示波器观测PA04引脚的波形，默认程序为4MHz时钟信号。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开rcc_mco.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/EWARM/project.ewp new file mode 100644 index 0000000..946f7df --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/MDK/rcc_pclkout.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/MDK/rcc_pclkout.uvoptx new file mode 100644 index 0000000..a806db1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/MDK/rcc_pclkout.uvoptx @@ -0,0 +1,367 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0Flashcw32l012_TEST.FLM -FS00 -FL010000 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012_TEST.FLM) + + + 0 + DLGUARM + + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0Flashcw32l012_TEST.FLM -FS00 -FL010000 -FP0($$Device:cw32l012F8$Flash\Flashcw32l012_TEST.FLM) + + + + + + 1 + 0 + 0 + 0 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\GPIOA + 35905 + + + + + + + Startup + 0 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/MDK/rcc_pclkout.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/MDK/rcc_pclkout.uvprojx new file mode 100644 index 0000000..1cf4ebf --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/MDK/rcc_pclkout.uvprojx @@ -0,0 +1,473 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Project + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\exe\ + Project + 1 + 0 + 1 + 1 + 1 + .\output\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/USER/inc/main.h new file mode 100644 index 0000000..3cfac81 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_gpio.h" + + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/USER/src/main.c new file mode 100644 index 0000000..79cc95b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/USER/src/main.c @@ -0,0 +1,108 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" +#include "cw32l012_sysctrl.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample output PCLK + ** + ******************************************************************************/ +int32_t main(void) +{ + /******************************************************************** + PCLK Output Test. + PCLK 输出到PA03管脚，通过PA03观察PCLK频率 + *******************************************************************/ + SYSCTRL_HSI_Enable( SYSCTRL_HSIOSC_DIV12 ); //8M + + SYSCTRL_PCLK_OUT(); //PA03输出PCLK + + while(1) + { + ; + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/readme.txt new file mode 100644 index 0000000..33d493c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RCC/rcc_pclkout/readme.txt @@ -0,0 +1,23 @@ +示例目的： + 利用PCLK时钟输出功能将PCLK时钟从PA03引脚输出。 + +硬件资源： + 1. CW32L012CxTx StartKit + 2. 时钟HSI + 3. 系统时钟设置为HSI时钟12分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + +演示说明： + 采用默认时钟配置，并设置PCLK时钟输出，用示波器观测PA03引脚的波形，默认程序为8MHz。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开rcc_pclkout.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/EWARM/project.ewp new file mode 100644 index 0000000..385881d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/MDK/Project.uvoptx new file mode 100644 index 0000000..aeb655c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/MDK/Project.uvoptx @@ -0,0 +1,396 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + 0 + 82 + 1 +
5718
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\project\../USER/src/main.c\82 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\GPIOA + 35904 + + + System Viewer\RTC + 35903 + + + System Viewer\UART3 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_rtc.c + cw32l012_rtc.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/MDK/Project.uvprojx new file mode 100644 index 0000000..20d7200 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/MDK/Project.uvprojx @@ -0,0 +1,488 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.3 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_rtc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_rtc.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/USER/inc/main.h new file mode 100644 index 0000000..d5f1ac6 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/USER/inc/main.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + +#include "cw32l012_sysctrl.h" +#include "cw32l012_rtc.h" +#include "cw32l012_uart.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + +#include "cw32l012_gpio.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..630f019 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + RTC_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/USER/src/main.c new file mode 100644 index 0000000..afb2d20 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/USER/src/main.c @@ -0,0 +1,225 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); +void delay(uint16_t ms); +void ShowTime(void); +void RTC_IRQHandlerCallBack(void); +void UART1_Configure(void); + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** This sample toggle GPIOA.00 + ** + ******************************************************************************/ + +/** + * @brief RTC时钟测试，初始化日历，使用间隔中断0.5秒通过Log输出日期时间 + * @return int32_t + */ +int32_t main(void) +{ + RTC_InitTypeDef RTC_InitStruct = {0}; + RTC_AlarmTypeDef RTC_AlarmStruct = {0}; + + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + Bsp_Uart_Init(8000000,115200); + + /* NVIC Configuration */ + NVIC_Configuration(); + + printf("RTC Init...\r\n"); + printf(" (RTC CR0:%04x,CR1:%04x,CR2:%04x,RESET FLAG:0x%08x)\r\n",CW_RTC->CR0,CW_RTC->CR1,CW_RTC->CR2,CW_SYSCTRL->RESETFLAG); + + SYSCTRL_LSE_Enable( SYSCTRL_LSE_MODE_OSC,SYSCTRL_LSE_DRIVER_LEVEL5);// 选择LSE为RTC时钟 + + RTC_InitStruct.DateStruct.Day = 0x21; //设置日期，DAY、MONTH、YEAR必须为BCD方式，星期为0~6，代表星期日，星期一至星期六 + RTC_InitStruct.DateStruct.Month = RTC_Month_June; + RTC_InitStruct.DateStruct.Week = RTC_Weekday_Monday; + RTC_InitStruct.DateStruct.Year = 0x21; + + printf("-------Set Date as 20%x/%x/%x\r\n", RTC_InitStruct.DateStruct.Year,RTC_InitStruct.DateStruct.Month,RTC_InitStruct.DateStruct.Day); + + RTC_InitStruct.TimeStruct.Hour = 0x32; //设置时间，HOUR、MINIUTE、SECOND必须为BCD方式，用户须保证HOUR、AMPM、H24之间的关联正确性 + RTC_InitStruct.TimeStruct.Minute = 0x59; + RTC_InitStruct.TimeStruct.Second = 0x51; + RTC_InitStruct.TimeStruct.AMPM = 0; + RTC_InitStruct.TimeStruct.H24 = 0; + printf("-------Set Time as %02x:%02x:%02x\r\n", RTC_InitStruct.TimeStruct.Hour,RTC_InitStruct.TimeStruct.Minute,RTC_InitStruct.TimeStruct.Second); + RTC_InitStruct.RTC_ClockSource = RTC_RTCCLK_FROM_LSE; + RTC_Init(&RTC_InitStruct); // 用户需选定需要使用的时钟源 + + printf("=====Set interval period as 0.5s...\r\n"); + RTC_SetInterval(RTC_INTERVAL_EVERY_0_5S); + + /* 设置闹钟为工作日上午的6：45 */ + printf("=====Set AlarmA at 6:45 on workday...\r\n"); + + RTC_AlarmStruct.RTC_AlarmMask = RTC_AlarmMask_WeekMON | RTC_AlarmMask_WeekTUE | + RTC_AlarmMask_WeekWED | RTC_AlarmMask_WeekTHU | + RTC_AlarmMask_WeekFRI; + RTC_AlarmStruct.RTC_AlarmTime.Hour = 6; + RTC_AlarmStruct.RTC_AlarmTime.Minute = 0x45; + RTC_AlarmStruct.RTC_AlarmTime.Second = 0; + RTC_SetAlarm(RTC_Alarm_A, &RTC_AlarmStruct); + RTC_AlarmCmd(RTC_Alarm_A, ENABLE); + + printf("=====Enable ALRAMA and INTERVAL IT...\r\n"); + + RTC_ITConfig(RTC_IT_ALARMA | RTC_IT_INTERVAL, ENABLE); + + while(1) + { + + } +} + + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + SYSCTRL_LSI_Enable(); + SYSCTRL_LSE_Enable( SYSCTRL_LSE_MODE_OSC,SYSCTRL_LSE_DRIVER_LEVEL5); + SYSCTRL_APBPeriphClk_Enable2(SYSCTRL_APB2_PERIPH_RTC, ENABLE); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + //GPIO_InitTypeDef GPIO_InitStruct; +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(RTC_IRQn); + __enable_irq(); +} + +void delay(uint16_t ms) +{ + uint32_t i; + for( ; ms >0; ms--) + { + i = 796; + while(i--); + } +} + +void ShowTime(void) +{ + RTC_TimeTypeDef RTC_TimeStruct = {0}; + RTC_DateTypeDef RTC_DateStruct = {0}; + static char *WeekdayStr[7]= {"SUN","MON","TUE","WED","THU","FRI","SAT"}; + static char *H12AMPMStr[2][2]= {{"AM","PM"},{"",""}}; + + RTC_GetDate(&RTC_DateStruct); + RTC_GetTime(&RTC_TimeStruct); + + printf(".Date is 20%02x/%02x/%02x(%s).Time is %02x%s:%02x:%02x\r\n", RTC_DateStruct.Year, RTC_DateStruct.Month, RTC_DateStruct.Day, WeekdayStr[RTC_DateStruct.Week], RTC_TimeStruct.Hour, H12AMPMStr[RTC_TimeStruct.H24][RTC_TimeStruct.AMPM],RTC_TimeStruct.Minute, RTC_TimeStruct.Second); +} + +void RTC_IRQHandlerCallBack(void) +{ + if (RTC_GetITState(RTC_IT_ALARMA)) + { + RTC_ClearITPendingBit(RTC_IT_ALARMA); + printf("*********Alarm!!!!\r\n"); + } + if (RTC_GetITState(RTC_IT_INTERVAL)) + { + RTC_ClearITPendingBit(RTC_IT_INTERVAL); + ShowTime(); + } +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/readme.txt new file mode 100644 index 0000000..4cd7884 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/RTC/RTC_Calendar/readme.txt @@ -0,0 +1,30 @@ +示例目的： + RTC时钟测试，初始化日历，使用间隔中断0.5秒通过串口输出日期时间 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI， LSE使能 + 3. 系统时钟设置为HSI时钟12分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. RTC使用LSE作为时钟输入 + 5. 串口UART3作为调试串口,打印调试信息,波特率115200 + + +演示说明： + 每0.5秒通过串口输出日期时间. + +硬件连接： + UART3_TXD (PA08) -- PCRX + UART3_RXD (PA09) -- PCTX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/EWARM/project.ewp new file mode 100644 index 0000000..7859cfb --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/MDK/Project.uvoptx new file mode 100644 index 0000000..75a4146 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/MDK/Project.uvoptx @@ -0,0 +1,380 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U4294967295 -O206 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TP21 -TDS8008 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + CMSIS_AGDI + -X"" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + + + + 0 + 1 + RxBuffer2 + + + 1 + 1 + TxBuffer1 + + + 2 + 1 + RxBuffer1 + + + 3 + 1 + RxBuffer1 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 1 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + + + Driver + 0 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_spi.c + cw32l012_spi.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/MDK/Project.uvprojx new file mode 100644 index 0000000..6815d63 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/MDK/Project.uvprojx @@ -0,0 +1,474 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + + + Driver + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_spi.c + 1 + ..\..\..\..\Libraries\src\cw32l012_spi.c + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/USER/inc/main.h new file mode 100644 index 0000000..1afae2b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/USER/inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_uart.h" +#include "cw32l012_spi.h" +#include "cw32l012_systick.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/USER/src/main.c new file mode 100644 index 0000000..53123d9 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/USER/src/main.c @@ -0,0 +1,329 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2022 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define SPI_MASTER //主机模式 +//#define SPI_SLAVE //从机模式 + +//SPI GPIO +#define SPI_SCK_GPIO_CLK SYSCTRL_AHB_PERIPH_GPIOA +#define SPI_SCK_GPIO_PORT CW_GPIOA +#define SPI_SCK_GPIO_PIN GPIO_PIN_5 +#define SPI_SCK_AF() PA05_AFx_SPI1SCK() + +#define SPI_MISO_GPIO_CLK SYSCTRL_AHB_PERIPH_GPIOA +#define SPI_MISO_GPIO_PORT CW_GPIOA +#define SPI_MISO_GPIO_PIN GPIO_PIN_6 +#define SPI_MISO_AF() PA06_AFx_SPI1MISO() + +#define SPI_MOSI_GPIO_CLK SYSCTRL_AHB_PERIPH_GPIOA +#define SPI_MOSI_GPIO_PORT CW_GPIOA +#define SPI_MOSI_GPIO_PIN GPIO_PIN_7 +#define SPI_MOSI_AF() PA07_AFx_SPI1MOSI() + +#define SPI_CS_GPIO_CLK SYSCTRL_AHB_PERIPH_GPIOA +#define SPI_CS_GPIO_PORT CW_GPIOA +#define SPI_CS_GPIO_PIN GPIO_PIN_9 +#define SPI_CS_AF() PA09_AFx_SPI1NCS() + +//CS LOW or HIGH +#define SPI_CS_LOW() PA09_SETLOW() +#define SPI_CS_HIGH() PA09_SETHIGH() + + +#define BufferSize ARRAY_SZ(TxBuffer1) +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void SPI_Configuration(void); +TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxBuffer1[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, + 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, + 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, + 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23 + }; +uint8_t TxBuffer2[] = {0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, + 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, + 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, + 0x7D, 0x7E, 0x7F, 0x80, 0x81, 0x82, 0x83 + }; +uint8_t RxBuffer1[BufferSize]; +uint8_t RxBuffer2[BufferSize]; +uint8_t TxRxCounter = 0; +volatile TestStatus TransferStatus = FAILED; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + + //配置GPIO + GPIO_Configuration(); + + InitTick(96000000); + + + //配置SPI + SPI_Configuration(); + + + /**************************主机 <-> 从机**********************/ +#ifdef SPI_MASTER + //拉低CS，选中SPI从机 + SPI_CS_LOW(); + while (TxRxCounter < BufferSize) + { + RxBuffer1[TxRxCounter] = SPI_TransmitReceive(CW_SPI1, TxBuffer1[TxRxCounter]); + TxRxCounter++; +// FirmwareDelay(30); + } + + //拉高CS，释放SPI从机 + SPI_CS_HIGH(); + + //检查收发数据一致性 + TransferStatus = Buffercmp(TxBuffer2, RxBuffer1, BufferSize); +#endif + +#ifdef SPI_SLAVE + //清空发送缓冲区和移位寄存器 + SPI_FlushSendBuff(CW_SPI1); + + while (TxRxCounter < BufferSize) + { + + // CW_SPI1->DR = TxBuffer2[TxRxCounter]; + RxBuffer2[TxRxCounter] = SPI_TransmitReceive(CW_SPI1, TxBuffer2[TxRxCounter]); + TxRxCounter++; + while((CW_SPI1->ISR & SPIx_ISR_TXE_Msk) == 0); + } + + //检查收发数据一致性 + TransferStatus = Buffercmp(TxBuffer1, RxBuffer2, BufferSize); +#endif + + if (TransferStatus == PASSED) //PASSED + { + //LED1亮 + PB09_SETHIGH(); + } + else //FAILED + { + //LED1灭 + PB09_SETLOW(); + } + while (1) + { + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI96MHZ); + + SYSCTRL_AHBPeriphClk_Enable(SPI_SCK_GPIO_CLK | SPI_MISO_GPIO_CLK | SPI_MOSI_GPIO_CLK | SPI_CS_GPIO_CLK, ENABLE); + SYSCTRL_APBPeriphClk_Enable1(SYSCTRL_APB1_PERIPH_SPI1, ENABLE); + +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + +#ifdef SPI_MASTER + //推挽输出 SCK MOSI CS + GPIO_InitStructure.Pins = SPI_SCK_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(SPI_SCK_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pins = SPI_MOSI_GPIO_PIN; + GPIO_Init(SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pins = SPI_CS_GPIO_PIN; + GPIO_Init(SPI_CS_GPIO_PORT, &GPIO_InitStructure); + + //浮空输入 MISO + GPIO_InitStructure.Pins = SPI_MISO_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT; + GPIO_Init(SPI_MISO_GPIO_PORT, &GPIO_InitStructure); + //SPI SCK MOSI MISO 复用 + + //拉高CS + SPI_CS_HIGH(); +#endif + +#ifdef SPI_SLAVE + //SPI CS复用 + + //推挽输出 MISO + GPIO_InitStructure.Pins = SPI_MISO_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(SPI_MISO_GPIO_PORT, &GPIO_InitStructure); + + //浮空输入 SCK MOSI CS + GPIO_InitStructure.Pins = SPI_SCK_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT; + GPIO_Init(SPI_SCK_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pins = SPI_MOSI_GPIO_PIN; + GPIO_Init(SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pins = SPI_CS_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(SPI_CS_GPIO_PORT, &GPIO_InitStructure); + SPI_CS_AF(); +#endif + SPI_SCK_AF(); + SPI_MISO_AF(); + SPI_MOSI_AF(); + + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.Pins = GPIO_PIN_9; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + + //LED灭 + PB09_SETLOW(); +} + +/** + * @brief 配置UART + * + */ +void SPI_Configuration(void) +{ + SPI_InitTypeDef SPI_InitStructure = {0}; + + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; // 双线全双工 + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; // 主机模式 + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; // 帧数据长度为8bit + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; // 时钟空闲电平为低 + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; // 第1个边沿采样 + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; // 片选信号由SSI寄存器控制 + SPI_InitStructure.SPI_BaudRatePrescaler = 47; // 波特率为PCLK的96分频 SCK = PCLK/(2*(n+1)) + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; // 最高有效位 MSB 收发在前 + SPI_InitStructure.SPI_Speed = SPI_Speed_Low; // 低速SPI + +#ifdef SPI_SLAVE + SPI_InitStructure.SPI_Mode = SPI_Mode_Slave; // 从机模式 + SPI_InitStructure.SPI_NSS = SPI_NSS_Hard; // SPI_CS引脚电平决定本机是否被选中 +#endif + + SPI_Init(CW_SPI1, &SPI_InitStructure); + SPI_Cmd(CW_SPI1, ENABLE); +} + +/** + * @brief Compares two buffers + * + * @param pBuffer1 :buffers to be compared + * @param pBuffer2 :buffers to be compared + * @param BufferLength :buffer's length + * @return TestStatus + * @arg PASSED: pBuffer1 identical to pBuffer2 + * @arg FAILED: pBuffer1 differs from pBuffer2 + */ +TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + + pBuffer1++; + pBuffer2++; + } + + return PASSED; +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/readme.txt new file mode 100644 index 0000000..bdc6075 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/SPI/SPI_FullDuplex_ComPolling/readme.txt @@ -0,0 +1,41 @@ +示例目的： + SPI可以配置为双线全双工模式，演示SPI主从机通信。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟12分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. SPI，波特率为PCLK的8分频，1Mbps + 5. PB09（LED1）设置为PUSH-PULL输出 + +演示说明： + - + #define SPI_MASTER //主机模式 + 主机查询方式（TXE）将TxBuffer1缓冲区中的数据写入DR寄存器，启动传输。 + 主机查询方式（RXNE）读取DR寄存器并存储到RxBuffer1缓冲区。 + 传输完成后，比较TxBuffer2和RxBuffer1，如果数据一致，则LED1亮，否则LED1灭。 + + - + #define SPI_SLAVE //从机模式 + 从机查询方式（TXE）将TxBuffer2缓冲区中的数据写入DR寄存器。 + 主机查询方式（RXNE）读取DR寄存器并存储到RxBuffer1缓冲区。 + 传输完成后，比较TxBuffer1和RxBuffer2，如果数据一致，则LED1亮，否则LED1灭。 + +硬件连接： + SPI_MASTER SCK (PA05)-- SPI_SLAVE SCK (PA05) + SPI_MASTER MISO (PA06)-- SPI_SLAVE MISO (PA06) + SPI_MASTER MOSI (PA07)-- SPI_SLAVE MOSI (PA07) + SPI_MASTER CS (PA09)-- SPI_SLAVE CS (PA09) + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/EWARM/project.ewp new file mode 100644 index 0000000..a16df07 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/EWARM/project.ewp @@ -0,0 +1,2261 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/MDK/project.uvoptx new file mode 100644 index 0000000..2b07e9b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/MDK/project.uvoptx @@ -0,0 +1,377 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 0 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 10 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/MDK/project.uvprojx new file mode 100644 index 0000000..bba5508 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/MDK/project.uvprojx @@ -0,0 +1,484 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/USER/inc/main.h new file mode 100644 index 0000000..aff21a6 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_flash.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/USER/src/main.c new file mode 100644 index 0000000..b9f6d5d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/USER/src/main.c @@ -0,0 +1,122 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "..\inc\main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint16_t valueAdc; + +volatile uint8_t gFlagIrq; + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Main function of project + * + * @return int + */ +int main(void) +{ + Bsp_Init(4000000); + + Bsp_Led_On(&LED1); + Bsp_Led_On(&LED2); + printf("Welcome to use CW32L012.\n"); + + while(1) + { + if (Bsp_Read_Key(&KEY1)) + { + Bsp_Led_On(&LED1); + } + else + { + Bsp_Led_Off(&LED1); + } + + if (Bsp_Read_Key(&KEY2)) + { + Bsp_Led_On(&LED2); + } + else + { + Bsp_Led_Off(&LED2); + } + } +} + + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @return None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/readme.txt new file mode 100644 index 0000000..0591460 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/Template/Template/readme.txt @@ -0,0 +1,28 @@ +示例目的： + 演示StartKit板上的LED1，LED2，KEY1，KEY2和串口的使用。 + +硬件资源： + 1. CW32L012CxTx StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟24分频，4MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=4MHz + 4. LED1，LED2, KEY1, KEY2 + 5. 板载USB转串口配置为115200bps，作为调试打印 + 6. 板上J3的VDDIN跳线短接，PCRXD跳线短接。 + +演示说明： + LED1和LED2常亮，调试串口输出“Welcome to use CW32L012.” + KEY1按下LED1熄灭，释放LED1点亮 + KEY2按下LED2熄灭，释放LED2点亮 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/EWARM/project.ewp new file mode 100644 index 0000000..31e6865 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/MDK/Project.uvoptx new file mode 100644 index 0000000..9ead057 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/MDK/Project.uvoptx @@ -0,0 +1,387 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + + 0 + 1 + TxRxBufferSize + + + 1 + 1 + TxRxBuffer + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\DMA + 35903 + + + System Viewer\SYSCTRL + 35905 + + + System Viewer\UART1 + 35901 + + + System Viewer\UART2 + 35902 + + + System Viewer\UART3 + 35904 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/MDK/Project.uvprojx new file mode 100644 index 0000000..62e5316 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/MDK/Project.uvprojx @@ -0,0 +1,483 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/USER/inc/main.h new file mode 100644 index 0000000..6b64761 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_uart.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/USER/src/main.c new file mode 100644 index 0000000..680a78d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/USER/src/main.c @@ -0,0 +1,198 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2022 + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + ******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTx +#define DEBUG_UARTx CW_UART3 +#define DEBUG_UART_CLK SYSCTRL_APB1_PERIPH_UART3 +#define DEBUG_UART_APBClkENx SYSCTRL_APBPeriphClk_Enable1 +#define DEBUG_UART_BaudRate 9600 +#define DEBUG_UART_UclkFreq 8000000 + +//UARTx GPIO +#define DEBUG_UART_GPIO_CLK (SYSCTRL_AHB_PERIPH_GPIOA) +#define DEBUG_UART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_UART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_UART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_UART_RX_GPIO_PIN GPIO_PIN_9 + +//GPIO AF +#define DEBUG_UART_AFTX PA08_AFx_UART3TXD() +#define DEBUG_UART_AFRX PA09_AFx_UART3RXD() + +//中断 +#define DEBUG_UART_IRQ UART3_IRQn + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxRxBufferSize; +uint8_t TxRxBuffer[200]; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + + //配置GPIO + GPIO_Configuration(); + + while (1) + { + //配置UART, 上位机发送字符'C'以识别波特率 + UART_Configuration(); + printf("The baud rate has been automatically matched.\r\n"); + printf("Please reset the baud rate.\r\n"); + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 8MHz = HCLK = PCLK + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + + //外设时钟使能 + SYSCTRL_AHBPeriphClk_Enable(DEBUG_UART_GPIO_CLK, ENABLE); + DEBUG_UART_APBClkENx(DEBUG_UART_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_InitStructure.Pins = DEBUG_UART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(DEBUG_UART_TX_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pins = DEBUG_UART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_UART_RX_GPIO_PORT, &GPIO_InitStructure); + + //UART TX RX 复用 + DEBUG_UART_AFTX; + DEBUG_UART_AFRX; +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + UART_InitTypeDef UART_InitStructure = {0}; + + UART_EnableAutoBaudRateDetection(DEBUG_UARTx, UART_AUTO_BAUD_RATE_MODE_1); + while (UART_AutoBaudRateDetectionComplete(DEBUG_UARTx) != TRUE); + UART_DisableAutoBaudRateDetection(DEBUG_UARTx); + + UART_InitStructure.UART_BaudRate = DEBUG_UART_UclkFreq / UART_GetDetectedBaudRate(DEBUG_UARTx); + UART_InitStructure.UART_Over = UART_Over_16; + UART_InitStructure.UART_Source = UART_Source_PCLK; + UART_InitStructure.UART_UclkFreq = DEBUG_UART_UclkFreq; + UART_InitStructure.UART_StartBit = UART_StartBit_FE; + UART_InitStructure.UART_StopBits = UART_StopBits_1; + UART_InitStructure.UART_Parity = UART_Parity_No ; + UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStructure.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; + UART_Init(DEBUG_UARTx, &UART_InitStructure); +} + +/** + * @brief 配置NVIC + * + */ +void NVIC_Configuration(void) +{ + //优先级，无优先级分组 + NVIC_SetPriority(DEBUG_UART_IRQ, 0); + //UARTx中断使能 + NVIC_EnableIRQ(DEBUG_UART_IRQ); +} + + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/readme.txt new file mode 100644 index 0000000..59b6f80 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Auto_BaudRate/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 演示LPUART的波特率检测功能。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟12分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为PCLK，无奇偶校验 + +演示说明： + 程序运行后，上位机发特定字符’C'，以便程序能识别波特率。 + + +硬件连接： + UART3_TXD (PA8) -- PCRX + UART3_RXD (PA9) -- PCTX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/EWARM/project.ewp new file mode 100644 index 0000000..31e6865 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/MDK/Project.uvoptx new file mode 100644 index 0000000..6a655d1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/MDK/Project.uvoptx @@ -0,0 +1,383 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0FlashCW32L012_TEST -FL010000 -FS00 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + + 0 + 1 + TxRxBufferSize + + + 1 + 1 + TxRxBuffer + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\DMA + 35902 + + + System Viewer\UART1 + 35905 + + + System Viewer\UART2 + 35904 + + + System Viewer\UART3 + 35903 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/MDK/Project.uvprojx new file mode 100644 index 0000000..23a35bc --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/MDK/Project.uvprojx @@ -0,0 +1,483 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.2 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/USER/inc/main.h new file mode 100644 index 0000000..6b64761 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_uart.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/USER/src/main.c new file mode 100644 index 0000000..f91580e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/USER/src/main.c @@ -0,0 +1,208 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2022 + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + ******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTx +#define DEBUG_UARTx CW_UART3 +#define DEBUG_UART_CLK SYSCTRL_APB1_PERIPH_UART3 +#define DEBUG_UART_APBClkENx SYSCTRL_APBPeriphClk_Enable1 +#define DEBUG_UART_BaudRate 9600 +#define DEBUG_UART_UclkFreq 8000000 + +//UARTx GPIO +#define DEBUG_UART_GPIO_CLK (SYSCTRL_AHB_PERIPH_GPIOA) +#define DEBUG_UART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_UART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_UART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_UART_RX_GPIO_PIN GPIO_PIN_9 + +//GPIO AF +#define DEBUG_UART_AFTX PA08_AFx_UART3TXD() +#define DEBUG_UART_AFRX PA09_AFx_UART3RXD() + +//中断 +#define DEBUG_UART_IRQ UART3_IRQn + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxRxBufferSize; +uint8_t TxRxBuffer[200]; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + uint8_t i; + //配置RCC + RCC_Configuration(); + + //配置GPIO + GPIO_Configuration(); + + //配置UART + UART_Configuration(); + + for (i = 0; i < 200; i++) + { + TxRxBuffer[i] = i; + } + + UART_TransmitDMA(DEBUG_UARTx, DMA_CHANNEL_1, TxRxBuffer, 200); + while (CW_DMA->ISR_f.TC1 == 0); // 等待DMA发送完成 + + while (1) + { + UART_ReceiveDMA(DEBUG_UARTx, DMA_CHANNEL_2, TxRxBuffer, 10); + while (CW_DMA->ISR_f.TC2 == 0); // 等待DMA接收到足够的数量 + + UART_TransmitDMA(DEBUG_UARTx, DMA_CHANNEL_1, TxRxBuffer, 10); + while (CW_DMA->ISR_f.TC1 == 0); // 等待DMA发送完成 + + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 8MHz = HCLK = PCLK + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + + //外设时钟使能 + SYSCTRL_AHBPeriphClk_Enable(DEBUG_UART_GPIO_CLK, ENABLE); + DEBUG_UART_APBClkENx(DEBUG_UART_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_InitStructure.Pins = DEBUG_UART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(DEBUG_UART_TX_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pins = DEBUG_UART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_UART_RX_GPIO_PORT, &GPIO_InitStructure); + + //UART TX RX 复用 + DEBUG_UART_AFTX; + DEBUG_UART_AFRX; +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + UART_InitTypeDef UART_InitStructure = {0}; + + UART_InitStructure.UART_BaudRate = DEBUG_UART_BaudRate; + UART_InitStructure.UART_Over = UART_Over_16; + UART_InitStructure.UART_Source = UART_Source_PCLK; + UART_InitStructure.UART_UclkFreq = DEBUG_UART_UclkFreq; + UART_InitStructure.UART_StartBit = UART_StartBit_FE; + UART_InitStructure.UART_StopBits = UART_StopBits_1; + UART_InitStructure.UART_Parity = UART_Parity_No ; + UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStructure.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; + UART_Init(DEBUG_UARTx, &UART_InitStructure); +} + +/** + * @brief 配置NVIC + * + */ +void NVIC_Configuration(void) +{ + //优先级，无优先级分组 + NVIC_SetPriority(DEBUG_UART_IRQ, 0); + //UARTx中断使能 + NVIC_EnableIRQ(DEBUG_UART_IRQ); +} + + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/readme.txt new file mode 100644 index 0000000..c9eec92 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_DMA_Transfer/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 演示LPUART使用DMA（直接存储器访问）进行数据传输，提高数据传输效率，适用于需要高速数据传输的场景。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟12分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为PCLK，波特率9600，无奇偶校验 + +演示说明： + 程序运行后，先通过DMA发送200个数据，然后通过DMA接收10个数据，再通过DMA将接收的数据发送。 + + +硬件连接： + UART3_TXD (PA8) -- PCRX + UART3_RXD (PA9) -- PCTX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/EWARM/project.ewp new file mode 100644 index 0000000..31e6865 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/MDK/Project.uvoptx new file mode 100644 index 0000000..8f6b500 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/MDK/Project.uvoptx @@ -0,0 +1,379 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + + 0 + 1 + TxRxBufferSize + + + 1 + 1 + TxRxBuffer + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\DMA + 35903 + + + System Viewer\SYSCTRL + 35905 + + + System Viewer\UART3 + 35904 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/MDK/Project.uvprojx new file mode 100644 index 0000000..62e5316 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/MDK/Project.uvprojx @@ -0,0 +1,483 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/USER/inc/main.h new file mode 100644 index 0000000..6b64761 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_uart.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/USER/src/main.c new file mode 100644 index 0000000..01c6cea --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/USER/src/main.c @@ -0,0 +1,204 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2022 + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + ******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTx +#define DEBUG_UARTx CW_UART3 +#define DEBUG_UART_CLK SYSCTRL_APB1_PERIPH_UART3 +#define DEBUG_UART_APBClkENx SYSCTRL_APBPeriphClk_Enable1 +#define DEBUG_UART_BaudRate 9600 +#define DEBUG_UART_UclkFreq 8000000 + +//UARTx GPIO +#define DEBUG_UART_GPIO_CLK (SYSCTRL_AHB_PERIPH_GPIOA) +#define DEBUG_UART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_UART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_UART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_UART_RX_GPIO_PIN GPIO_PIN_9 + +//GPIO AF +#define DEBUG_UART_AFTX PA08_AFx_UART3TXD() +#define DEBUG_UART_AFRX PA09_AFx_UART3RXD() + +//中断 +#define DEBUG_UART_IRQ UART3_IRQn + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxRxBufferSize; +uint8_t TxRxBuffer[200]; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + + //配置GPIO + GPIO_Configuration(); + + //配置UART + UART_Configuration(); + + while (1) + { + UART_ReceiveDMA(DEBUG_UARTx, DMA_CHANNEL_2, TxRxBuffer, 200); + while (UART_GetDataMatchFlag(DEBUG_UARTx)!= TRUE); // 等待接收匹配 + UART_ClearFlag(DEBUG_UARTx, UART_FLAG_RXMATCH); + TxRxBufferSize = *DMA_CNTy(DMA_CHANNEL_2) - *DMA_CCNTy(DMA_CHANNEL_2); // 计算接收数据长度 + + UART_TransmitDMA(DEBUG_UARTx, DMA_CHANNEL_1, TxRxBuffer, TxRxBufferSize); + while (CW_DMA->ISR_f.TC1 == 0); // 等待DMA发送完成 + + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 8MHz = HCLK = PCLK + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + + //外设时钟使能 + SYSCTRL_AHBPeriphClk_Enable(DEBUG_UART_GPIO_CLK, ENABLE); + DEBUG_UART_APBClkENx(DEBUG_UART_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_InitStructure.Pins = DEBUG_UART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(DEBUG_UART_TX_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pins = DEBUG_UART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_UART_RX_GPIO_PORT, &GPIO_InitStructure); + + //UART TX RX 复用 + DEBUG_UART_AFTX; + DEBUG_UART_AFRX; +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + UART_InitTypeDef UART_InitStructure = {0}; + + UART_InitStructure.UART_BaudRate = DEBUG_UART_BaudRate; + UART_InitStructure.UART_Over = UART_Over_16; + UART_InitStructure.UART_Source = UART_Source_PCLK; + UART_InitStructure.UART_UclkFreq = DEBUG_UART_UclkFreq; + UART_InitStructure.UART_StartBit = UART_StartBit_FE; + UART_InitStructure.UART_StopBits = UART_StopBits_1; + UART_InitStructure.UART_Parity = UART_Parity_Odd ; + UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStructure.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; + UART_Init(DEBUG_UARTx, &UART_InitStructure); + + UART_SetDataMatch(DEBUG_UARTx, '\n'| 0x100); // 换行符 奇校验 + UART_EnableDataMatch(DEBUG_UARTx); +} + +/** + * @brief 配置NVIC + * + */ +void NVIC_Configuration(void) +{ + //优先级，无优先级分组 + NVIC_SetPriority(DEBUG_UART_IRQ, 0); + //UARTx中断使能 + NVIC_EnableIRQ(DEBUG_UART_IRQ); +} + + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/readme.txt new file mode 100644 index 0000000..be9d8d4 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Data_Match/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 接收数据匹配功能示例。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟12分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为PCLK，波特率9600，奇校验 + +演示说明： + 设置串口以DMA的方式接收数据，接收字符匹配检测开启，等待匹配标志置位，当匹配的接收字符后，将接收到的数据通过DMA发送，然后复位DMA接收。 + + +硬件连接： + UART3_TXD (PA8) -- PCRX + UART3_RXD (PA9) -- PCTX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/EWARM/project.ewp new file mode 100644 index 0000000..31e6865 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/MDK/Project.uvoptx new file mode 100644 index 0000000..fa1fce3 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/MDK/Project.uvoptx @@ -0,0 +1,371 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + + 0 + 1 + TxRxBufferSize + + + 1 + 1 + TxRxBuffer + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\UART3 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/MDK/Project.uvprojx new file mode 100644 index 0000000..9cc3efd --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/MDK/Project.uvprojx @@ -0,0 +1,483 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.3 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/USER/inc/main.h new file mode 100644 index 0000000..6b64761 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_uart.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..92c4ee1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + UART3_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/USER/src/main.c new file mode 100644 index 0000000..4dc7a70 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/USER/src/main.c @@ -0,0 +1,237 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2022 + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + ******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTx +#define DEBUG_UARTx CW_UART3 +#define DEBUG_UART_CLK SYSCTRL_APB1_PERIPH_UART3 +#define DEBUG_UART_APBClkENx SYSCTRL_APBPeriphClk_Enable1 +#define DEBUG_UART_BaudRate 9600 +#define DEBUG_UART_UclkFreq 8000000 + +//UARTx GPIO +#define DEBUG_UART_GPIO_CLK (SYSCTRL_AHB_PERIPH_GPIOA) +#define DEBUG_UART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_UART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_UART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_UART_RX_GPIO_PIN GPIO_PIN_9 + +//GPIO AF +#define DEBUG_UART_AFTX PA08_AFx_UART3TXD() +#define DEBUG_UART_AFRX PA09_AFx_UART3RXD() + +//中断 +#define DEBUG_UART_IRQ UART3_IRQn + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxRxBufferSize; +uint8_t TxRxBuffer[] = "1234567890\r\n"; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + + //配置GPIO + GPIO_Configuration(); + + //配置UART + UART_Configuration(); + + //配置NVIC + NVIC_Configuration(); + + while (1) + { + //发送 + UART_TransmitInterrupt(DEBUG_UARTx, TxRxBuffer, sizeof(TxRxBuffer)); + //接收 + UART_ReceiveInterrupt(DEBUG_UARTx, TxRxBuffer, sizeof(TxRxBuffer)); + while (rxComplete != TRUE); + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 8MHz = HCLK = PCLK + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + + //外设时钟使能 + SYSCTRL_AHBPeriphClk_Enable(DEBUG_UART_GPIO_CLK, ENABLE); + DEBUG_UART_APBClkENx(DEBUG_UART_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_InitStructure.Pins = DEBUG_UART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(DEBUG_UART_TX_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pins = DEBUG_UART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_UART_RX_GPIO_PORT, &GPIO_InitStructure); + + //UART TX RX 复用 + DEBUG_UART_AFTX; + DEBUG_UART_AFRX; +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + UART_InitTypeDef UART_InitStructure = {0}; + + UART_InitStructure.UART_BaudRate = DEBUG_UART_BaudRate; + UART_InitStructure.UART_Over = UART_Over_16; + UART_InitStructure.UART_Source = UART_Source_PCLK; + UART_InitStructure.UART_UclkFreq = DEBUG_UART_UclkFreq; + UART_InitStructure.UART_StartBit = UART_StartBit_FE; + UART_InitStructure.UART_StopBits = UART_StopBits_1; + UART_InitStructure.UART_Parity = UART_Parity_No ; + UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStructure.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; + UART_Init(DEBUG_UARTx, &UART_InitStructure); +} + +/** + * @brief 配置NVIC + * + */ +void NVIC_Configuration(void) +{ + //优先级，无优先级分组 + NVIC_SetPriority(DEBUG_UART_IRQ, 0); + //UARTx中断使能 + NVIC_EnableIRQ(DEBUG_UART_IRQ); +} + +void UART3_IRQHandlerCallBack(void) +{ + //接收 + if (UART_GetITStatus(DEBUG_UARTx, UART_IT_RC) != RESET) + { + UART_ClearITPendingBit(DEBUG_UARTx, UART_IT_RC); + if (rxDataLen == 0) + { + rxComplete = TRUE; + } + else + { + *rxDataPtr = UART_ReceiveData(DEBUG_UARTx); + rxDataLen--; + rxDataPtr++; + } + + } + + //发送 + if (UART_GetITStatus(DEBUG_UARTx, UART_IT_TC) != RESET) + { + UART_ClearITPendingBit(DEBUG_UARTx, UART_IT_TC); + if (txDataLen == 0) + { + txComplete = TRUE; + } + else + { + txDataLen--; + txDataPtr++; + UART_SendData(DEBUG_UARTx, *txDataPtr); + } + + + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/readme.txt new file mode 100644 index 0000000..9294e43 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Interrupt_Driven_TransmitReceive/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 演示LPUART在中断驱动模式下的发送和接收功能，通过中断处理接收和发送数据，适用于需要低延迟和高效率的场景。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟12分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为PCLK，波特率9600，无奇偶校验 + +演示说明： + 程序运行后，串口发送字符串“1234567890”和“\r\n\0"不可显示字符共13个字符，后等待接收到13个字符，然后继续将接收到的字 + 符通过串口发送出来。 + +硬件连接： + UART3_TXD (PA8) -- PCRX + UART3_RXD (PA9) -- PCTX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/EWARM/project.ewp new file mode 100644 index 0000000..31e6865 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/MDK/Project.uvoptx new file mode 100644 index 0000000..aa0d3eb --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/MDK/Project.uvoptx @@ -0,0 +1,365 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + + 0 + 1 + TxRxBufferSize + + + 1 + 1 + TxRxBuffer + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 1 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/MDK/Project.uvprojx new file mode 100644 index 0000000..3116346 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/MDK/Project.uvprojx @@ -0,0 +1,483 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/USER/inc/main.h new file mode 100644 index 0000000..6b64761 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_uart.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/USER/src/main.c new file mode 100644 index 0000000..2e9c4d0 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/USER/src/main.c @@ -0,0 +1,197 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2022 + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + ******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTx +#define DEBUG_UARTx CW_UART3 +#define DEBUG_UART_CLK SYSCTRL_APB1_PERIPH_UART3 +#define DEBUG_UART_APBClkENx SYSCTRL_APBPeriphClk_Enable1 +#define DEBUG_UART_BaudRate 9600 +#define DEBUG_UART_UclkFreq 8000000 + +//UARTx GPIO +#define DEBUG_UART_GPIO_CLK (SYSCTRL_AHB_PERIPH_GPIOA) +#define DEBUG_UART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_UART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_UART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_UART_RX_GPIO_PIN GPIO_PIN_9 + +//GPIO AF +#define DEBUG_UART_AFTX PA08_AFx_UART3TXD() +#define DEBUG_UART_AFRX PA09_AFx_UART3RXD() + +//中断 +#define DEBUG_UART_IRQ UART3_IRQn + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxRxBufferSize; +uint8_t TxRxBuffer[] = "\r\nCW32L012 UART Polling\r\n"; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + + //配置GPIO + GPIO_Configuration(); + + //配置UART + UART_Configuration(); + + UART_TransmitPolling(DEBUG_UARTx, TxRxBuffer, sizeof(TxRxBuffer)); + + UART_ClearITPendingBit(DEBUG_UARTx, UART_IT_RC); + while(1) + { + //轮询收发 + UART_ReceivePolling(DEBUG_UARTx, TxRxBuffer, sizeof(TxRxBuffer)); + UART_TransmitPolling(DEBUG_UARTx, TxRxBuffer, sizeof(TxRxBuffer)); + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 8MHz = HCLK = PCLK + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + + //外设时钟使能 + SYSCTRL_AHBPeriphClk_Enable(DEBUG_UART_GPIO_CLK, ENABLE); + DEBUG_UART_APBClkENx(DEBUG_UART_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_InitStructure.Pins = DEBUG_UART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(DEBUG_UART_TX_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pins = DEBUG_UART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_UART_RX_GPIO_PORT, &GPIO_InitStructure); + + //UART TX RX 复用 + DEBUG_UART_AFTX; + DEBUG_UART_AFRX; +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + UART_InitTypeDef UART_InitStructure = {0}; + + UART_InitStructure.UART_BaudRate = DEBUG_UART_BaudRate; + UART_InitStructure.UART_Over = UART_Over_16; + UART_InitStructure.UART_Source = UART_Source_PCLK; + UART_InitStructure.UART_UclkFreq = DEBUG_UART_UclkFreq; + UART_InitStructure.UART_StartBit = UART_StartBit_FE; + UART_InitStructure.UART_StopBits = UART_StopBits_1; + UART_InitStructure.UART_Parity = UART_Parity_No ; + UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStructure.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; + UART_Init(DEBUG_UARTx, &UART_InitStructure); +} + +/** + * @brief 配置NVIC + * + */ +void NVIC_Configuration(void) +{ + //优先级，无优先级分组 + NVIC_SetPriority(DEBUG_UART_IRQ, 0); + //UARTx中断使能 + NVIC_EnableIRQ(DEBUG_UART_IRQ); +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/readme.txt new file mode 100644 index 0000000..7f61d85 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_NoParity_TransmitReceive/readme.txt @@ -0,0 +1,30 @@ +示例目的： + UART查询方式发送和接收数据示例。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟12分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为PCLK，波特率9600，无奇偶校验 + +演示说明： + PC发送数据，UART查询方式（RC）接收数据，并存储到TxRxBuffer缓冲区； + 当UART接收sizeof(TxRxBuffer)个数据后，停止接收数据。 + UART查询方式（TXE）发送TxRxBuffer缓冲区中的数据至PC。 + +硬件连接： + UART3_TXD (PA8) -- PCRX + UART3_RXD (PA9) -- PCTX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/EWARM/project.ewp new file mode 100644 index 0000000..31e6865 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/MDK/Project.uvoptx new file mode 100644 index 0000000..826f1f7 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/MDK/Project.uvoptx @@ -0,0 +1,359 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\SYSCTRL + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/MDK/Project.uvprojx new file mode 100644 index 0000000..c301128 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/MDK/Project.uvprojx @@ -0,0 +1,483 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.2 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/USER/inc/main.h new file mode 100644 index 0000000..4989cfb --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + + +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_uart.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/USER/src/main.c new file mode 100644 index 0000000..7b7fd5b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/USER/src/main.c @@ -0,0 +1,228 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2022 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTx +#define DEBUG_UARTx CW_UART3 +#define DEBUG_UART_CLK SYSCTRL_APB1_PERIPH_UART3 +#define DEBUG_UART_APBClkENx SYSCTRL_APBPeriphClk_Enable1 +#define DEBUG_UART_BaudRate 9600 +#define DEBUG_UART_UclkFreq 8000000 + +//UARTx GPIO +#define DEBUG_UART_GPIO_CLK (SYSCTRL_AHB_PERIPH_GPIOA) +#define DEBUG_UART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_UART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_UART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_UART_RX_GPIO_PIN GPIO_PIN_9 + +//GPIO AF +#define DEBUG_UART_AFTX PA08_AFx_UART3TXD() +#define DEBUG_UART_AFRX PA09_AFx_UART3RXD() + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); + +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + //配置RCC + RCC_Configuration(); + + //配置GPIO + GPIO_Configuration(); + + //配置UART + UART_Configuration(); + + printf("\r\nCW32L012 UART Printf Example\r\n"); + + while(1) + { + + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 8MHz = HCLK = PCLK + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + + //外设时钟使能 + SYSCTRL_AHBPeriphClk_Enable(DEBUG_UART_GPIO_CLK, ENABLE); + DEBUG_UART_APBClkENx(DEBUG_UART_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_WritePin(DEBUG_UART_TX_GPIO_PORT, DEBUG_UART_TX_GPIO_PIN,GPIO_Pin_SET); // 设置TXD的默认电平为高，空闲 + + GPIO_InitStructure.Pins = DEBUG_UART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(DEBUG_UART_TX_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pins = DEBUG_UART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_UART_RX_GPIO_PORT, &GPIO_InitStructure); + + //UART TX RX 复用 + DEBUG_UART_AFTX; + DEBUG_UART_AFRX; +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + UART_InitTypeDef UART_InitStructure = {0}; + + UART_InitStructure.UART_BaudRate = DEBUG_UART_BaudRate; + UART_InitStructure.UART_Over = UART_Over_16; + UART_InitStructure.UART_Source = UART_Source_PCLK; + UART_InitStructure.UART_UclkFreq = DEBUG_UART_UclkFreq; + UART_InitStructure.UART_StartBit = UART_StartBit_FE; + UART_InitStructure.UART_StopBits = UART_StopBits_1; + UART_InitStructure.UART_Parity = UART_Parity_No ; + UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStructure.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; + UART_Init(DEBUG_UARTx, &UART_InitStructure); +} + +/** + * @brief Retargets the C library printf function to the UART. + * + */ +PUTCHAR_PROTOTYPE +{ + UART_SendData(DEBUG_UARTx, (uint8_t)ch); + + while (UART_GetFlagStatus(DEBUG_UARTx, UART_FLAG_TXE) == RESET); + + return ch; +} + +size_t __write(int handle, const unsigned char * buffer, size_t size) +{ + size_t nChars = 0; + + if (buffer == 0) + { + /* + * This means that we should flush internal buffers. Since we + * don't we just return. (Remember, "handle" == -1 means that all + * handles should be flushed.) + */ + return 0; + } + + + for (/* Empty */; size != 0; --size) + { + UART_SendData(DEBUG_UARTx, *buffer++); + while (UART_GetFlagStatus(DEBUG_UARTx, UART_FLAG_TXE) == RESET); + ++nChars; + } + + return nChars; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/readme.txt new file mode 100644 index 0000000..ce1ed03 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_Printf/readme.txt @@ -0,0 +1,28 @@ +示例目的： + 将C库的printf函数重定向到UART。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟12分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为PCLK，波特率9600 + +演示说明： + 使用UART在串口调试助手上输出printf调试信息。 + +硬件连接： + UART3_TXD (PA8) -- PCRX + UART3_RXD (PA9) -- PCTX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/EWARM/project.ewp new file mode 100644 index 0000000..2182070 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/MDK/Project.uvoptx new file mode 100644 index 0000000..051f9a9 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/MDK/Project.uvoptx @@ -0,0 +1,415 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + JL2CM3 + -U4294967295 -O78 -S4 -ZTIFSpeedSel2000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8027 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + + 0 + 1 + TxRxBufferSize + + + 1 + 1 + TxRxBuffer + + + + + 0 + 2 + RxBuffer + + + + + 1 + 0 + 0x00100600 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\GPIOA + 35903 + + + System Viewer\SYSCTRL + 35904 + + + System Viewer\UART1 + 35902 + + + System Viewer\UART3 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/MDK/Project.uvprojx new file mode 100644 index 0000000..95a4960 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/MDK/Project.uvprojx @@ -0,0 +1,488 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.2 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/USER/inc/main.h new file mode 100644 index 0000000..0f03ca9 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/USER/inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_uart.h" +#include "cw32l012_systick.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/USER/src/main.c new file mode 100644 index 0000000..0ccca94 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/USER/src/main.c @@ -0,0 +1,171 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2022 + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + ******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_SendBuf_Polling(UART_TypeDef *UARTx, uint8_t *TxBuf, uint8_t TxCnt); +uint8_t UART_RecvBuf_Polling(UART_TypeDef *UARTx, uint8_t *RxBuf); + + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxBuffer[] = {0x90, 0xFF, 0xFF, 0x00, 0xFF, 0xFF}; +uint8_t RxBuffer[60]; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + uint8_t cmd = 0x9F; //JEDEC ID + UART_SyncModeInitTypeDef UART_SyncModeInitStruct = {0}; + //配置RCC + RCC_Configuration(); + + Bsp_Init(96000000); + + InitTick(96000000); // tick 1ms + //配置GPIO + GPIO_Configuration(); + + //配置UART + UART_SyncModeInitStruct.UART_ClockSource = UART_Source_PCLK; + UART_SyncModeInitStruct.UART_ClockFreq = 96000000; + UART_SyncModeInitStruct.UART_BaudRate = 1000000; // 注：BaudRate = UCLK/(2*BRRI), BRRI<0x100 + UART_SyncModeInitStruct.UART_TransmitOrder = UART_Transmit_Order_MSB; + UART_SyncMode_Init(CW_UART1, &UART_SyncModeInitStruct); + + PB02_SETLOW(); // CS + UART_SyncMode_SendDataPolling(CW_UART1, &cmd, 1); + UART_SyncMode_ReceiveDataPolling(CW_UART1, RxBuffer, 3); + PB02_SETHIGH(); + + printf("The JEDEC ID is :0x%2X 0x%2X 0x%2X\r\n", RxBuffer[0], RxBuffer[1],RxBuffer[2]); + + + while (1) + { + Bsp_Led_Tog(&LED1); + SysTickDelay(500); + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSIOSC/1 = HCLK = PCLK == 96MHz + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI96MHZ); + + //外设时钟使能 + __SYSCTRL_UART1_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + __SYSCTRL_GPIOB_CLK_ENABLE(); + + //UART TX RX 复用 + PB00_AFx_UART1RXD(); + PB01_AFx_UART1TXD(); + + GPIO_InitStructure.Pins = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStructure); + + PB02_SETHIGH(); +} + + + +/** + * @brief 配置NVIC + * + */ +void NVIC_Configuration(void) +{ + +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/readme.txt new file mode 100644 index 0000000..71d9536 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_SyncComm/readme.txt @@ -0,0 +1,33 @@ +示例目的： + 演示UART的同步通信功能 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟1分频，96MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=96MHz + 4. 板载打印串口，波特率115200， 1-8-N-1 + 5. 板载LED1 + 6. UART1的传输时钟设置为PCLK，波特率1Mbps，同步模式 + 7. 板载SPI FLASH（W25Q64JV） + 8. PB02 Push-pull输出 + +演示说明： + UART1同步模式下和SPI FLASH通信，读取FLASH的JEDEC ID的信息，并通过板载打印串口输出。完成后LED1闪烁。 + +硬件连接： + UART1_TXD (PB01) -- SPI.SCK + UART1_RXD (PB00) -- SPI.MOSI和SPI.MISO + PB02 -- SPI.CS + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/EWARM/project.ewp new file mode 100644 index 0000000..31e6865 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/EWARM/project.ewp @@ -0,0 +1,2249 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/MDK/Project.uvoptx new file mode 100644 index 0000000..3addd8d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/MDK/Project.uvoptx @@ -0,0 +1,404 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + 0 + 122 + 1 +
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+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\main.c + + \\project\../USER/src/main.c\122 + + + 1 + 0 + 113 + 1 +
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+ 0 + 0 + 0 + 0 + 0 + 0 + ..\USER\src\main.c + + + + + + + 0 + 1 + TxRxBufferSize + + + 1 + 1 + TxRxBuffer + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\UART3 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_uart.c + cw32l012_uart.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 8 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 1 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/MDK/Project.uvprojx new file mode 100644 index 0000000..9cc3efd --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/MDK/Project.uvprojx @@ -0,0 +1,483 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.3 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_uart.c + 1 + ..\..\..\..\Libraries\src\cw32l012_uart.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/USER/inc/main.h new file mode 100644 index 0000000..6b64761 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/USER/inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_uart.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..c1b398e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/USER/src/interrupts_cw32l012.c @@ -0,0 +1,437 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/USER/src/main.c new file mode 100644 index 0000000..f4a7309 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/USER/src/main.c @@ -0,0 +1,216 @@ +/** + * @file main.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2022 + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + ******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "main.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//UARTx +#define DEBUG_UARTx CW_UART3 +#define DEBUG_UART_CLK SYSCTRL_APB1_PERIPH_UART3 +#define DEBUG_UART_APBClkENx SYSCTRL_APBPeriphClk_Enable1 +#define DEBUG_UART_BaudRate 115200 +#define DEBUG_UART_UclkFreq 8000000 + +//UARTx GPIO +#define DEBUG_UART_GPIO_CLK (SYSCTRL_AHB_PERIPH_GPIOA) +#define DEBUG_UART_TX_GPIO_PORT CW_GPIOA +#define DEBUG_UART_TX_GPIO_PIN GPIO_PIN_8 +#define DEBUG_UART_RX_GPIO_PORT CW_GPIOA +#define DEBUG_UART_RX_GPIO_PIN GPIO_PIN_9 + +//GPIO AF +#define DEBUG_UART_AFTX PA08_AFx_UART3TXD() +#define DEBUG_UART_AFRX PA09_AFx_UART3RXD() + +//中断 +#define DEBUG_UART_IRQ UART3_IRQn + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void UART_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ +uint8_t TxRxBufferSize; +uint8_t TxRxBuffer[] = "\r\nCW32L012 UART Polling\r\n"; +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + // 要发送的数据 + uint8_t dataToSend = 'A'; + uint8_t receivedData; + + //配置RCC + RCC_Configuration(); + + //配置GPIO + GPIO_Configuration(); + + //配置UART + UART_Configuration(); + + while(1) + { + UART_SendData(DEBUG_UARTx, dataToSend); + while (UART_GetFlagStatus(DEBUG_UARTx, UART_IT_RC) != SET); //轮询接收 + receivedData = UART_ReceiveData(DEBUG_UARTx); + UART_ClearITPendingBit(DEBUG_UARTx, UART_IT_RC); + if (dataToSend == receivedData) + { + if (UART_GetFlagStatus(DEBUG_UARTx, UART_IT_PE) == SET) + { + printf("Parity Error\n"); + UART_ClearITPendingBit(DEBUG_UARTx, UART_IT_PE); + } + else + { + printf("Data received correctly: %c\n", receivedData); + } + } + else + { + printf("Data mismatch: sent %c, received %c\n", dataToSend, receivedData); + } + } +} + +/** + * @brief 配置RCC + * + */ +void RCC_Configuration(void) +{ + //SYSCLK = HSI = 8MHz = HCLK = PCLK + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + + //外设时钟使能 + SYSCTRL_AHBPeriphClk_Enable(DEBUG_UART_GPIO_CLK, ENABLE); + DEBUG_UART_APBClkENx(DEBUG_UART_CLK, ENABLE); +} + +/** + * @brief 配置GPIO + * + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_InitStructure.Pins = DEBUG_UART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(DEBUG_UART_TX_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pins = DEBUG_UART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_UART_RX_GPIO_PORT, &GPIO_InitStructure); + + //UART TX RX 复用 + DEBUG_UART_AFTX; + DEBUG_UART_AFRX; +} + +/** + * @brief 配置UART + * + */ +void UART_Configuration(void) +{ + UART_InitTypeDef UART_InitStructure = {0}; + + UART_InitStructure.UART_BaudRate = DEBUG_UART_BaudRate; + UART_InitStructure.UART_Over = UART_Over_16; + UART_InitStructure.UART_Source = UART_Source_PCLK; + UART_InitStructure.UART_UclkFreq = DEBUG_UART_UclkFreq; + UART_InitStructure.UART_StartBit = UART_StartBit_FE; + UART_InitStructure.UART_StopBits = UART_StopBits_1; + UART_InitStructure.UART_Parity = UART_Parity_Even; + UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStructure.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; + UART_Init(DEBUG_UARTx, &UART_InitStructure); + + UART_ClearITPendingBit(DEBUG_UARTx, UART_IT_ALL); +} + +/** + * @brief 配置NVIC + * + */ +void NVIC_Configuration(void) +{ + //优先级，无优先级分组 + NVIC_SetPriority(DEBUG_UART_IRQ, 0); + //UARTx中断使能 + NVIC_EnableIRQ(DEBUG_UART_IRQ); +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/readme.txt new file mode 100644 index 0000000..26f9c69 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/UART/UART_WithParity_TransmitReceive/readme.txt @@ -0,0 +1,29 @@ +示例目的： + UART带奇偶校验以查询方式发送和接收数据示例。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSIOSC + 3. 系统时钟设置为HSIOSC时钟12分频，8MHz，PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. UART的传输时钟设置为PCLK，波特率115200, 偶校验 + +演示说明： + 程序以偶校验的方式向串口助手发送字符‘A’，如果串口助手也以相同的校验发送字符‘A'，则会打印“Data received correctly: A” + 否则打印Parity Error或Data mismatch: sent A, received X。 + +硬件连接： + UART3_TXD (PA8) -- PCRX + UART3_RXD (PA9) -- PCTX + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/EWARM/project.ewp new file mode 100644 index 0000000..a1630c0 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/EWARM/project.ewp @@ -0,0 +1,2258 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_vc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_btim.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/MDK/Project.uvoptx new file mode 100644 index 0000000..8052de7 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/MDK/Project.uvoptx @@ -0,0 +1,407 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + DLGUARM + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\BTIM1 + 35902 + + + System Viewer\DAC + 35904 + + + System Viewer\VC1 + 35905 + + + System Viewer\VC12REF + 35903 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_vc.c + cw32l012_vc.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_btim.c + cw32l012_btim.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 11 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/MDK/Project.uvprojx new file mode 100644 index 0000000..265a013 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/MDK/Project.uvprojx @@ -0,0 +1,489 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.4 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_vc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_vc.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + cw32l012_btim.c + 1 + ..\..\..\..\Libraries\src\cw32l012_btim.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/USER/inc/main.h new file mode 100644 index 0000000..9af672f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/USER/inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_btim.h" + +#include "cw32l012_vc.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..cc92a2f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/USER/src/interrupts_cw32l012.c @@ -0,0 +1,438 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + VC13_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/USER/src/main.c new file mode 100644 index 0000000..189fe3e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/USER/src/main.c @@ -0,0 +1,248 @@ +/** + * @file main.c + * @brief 本文件为设备驱动库模块的主程序文件。 + * @details + * @author WHXY + * @date 2021-03-12 + * @version 1.0 + * + * @copyright + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + */ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" +#include "cw32l012_vc.h" + + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +static void SYSCTRL_Configuration(void); +//static void GPIO_Configuration(void); +static void LED_Init(void); +static void BTIM_Configuration(void); +static void NVIC_Configuration(void); +static void VC_PortInit(void); +static void VC_Configuration(void); + + +/** + * @brief 主函数，程序的入口点。 + * + * 该函数完成系统初始化工作，包括系统时钟配置、滴答定时器初始化、LED初始化、 + * VC模块配置以及中断向量控制器配置。 + * + * @return int32_t 程序正常运行时不会返回。 + */ +int32_t main(void) +{ + // 调用系统时钟配置函数，将系统时钟配置为8MHz + SYSCTRL_Configuration(); + + // 初始化滴答定时器，传入系统时钟频率8000000Hz + InitTick(8000000); + // 调用LED初始化函数，对LED进行初始化操作 + LED_Init(); + + BTIM_Configuration(); + + // 调用VC模块配置函数，对VC模块进行配置 + VC_Configuration(); + + // 调用中断向量控制器配置函数，对中断向量控制器进行配置 + NVIC_Configuration(); + + while (1) + { + if (CW_VC1->SR_f.FLTV == 0) + { + PB09_SETLOW(); + SysTickDelay(50); + } + else + { + PB09_SETHIGH(); + } + } +} + +static void SYSCTRL_Configuration(void) +{ + // 系统时钟配置为8MHz + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI8MHZ); + /* 1. 设置HCLK和PCLK的分频系数　*/ + SYSCTRL_HCLKPRS_Config(SYSCTRL_HCLK_DIV1); + SYSCTRL_PCLKPRS_Config(SYSCTRL_PCLK_DIV1); + SYSCTRL_SystemCoreClockUpdate(8000000); + /* 2. 配置外设时钟 */ + __SYSCTRL_VC_CLK_ENABLE(); //使能VC模块 + + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); +} + +//static void GPIO_Configuration(void) +//{ +// GPIO_InitTypeDef GPIO_InitStruct; +//} + +static void BTIM_Configuration(void) +{ + BTIM_TimeBaseInitTypeDef BTIM_TimeBaseInitStruct; + + __SYSCTRL_BTIM123_CLK_ENABLE(); + + BTIM_TimeBaseInitStruct.BTIM_CountMode = BTIM_COUNT_MODE_REPETITIVE; + BTIM_TimeBaseInitStruct.BTIM_Mode = BTIM_MODE_TIMER; // 使用PCLK计数 + BTIM_TimeBaseInitStruct.BTIM_Period = 99; // 100ms = (99+1) * 1/ (8000000/(7999+1)) + BTIM_TimeBaseInitStruct.BTIM_Prescaler = 7999; // 8000分频得到1KHz计数时钟 + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_TimeBaseInitStruct); + + BTIM_MasterOutputTriggerConfig(CW_BTIM1, BTIM_MASTER_OUTPUT_TRIGGER_OVERFLOW); + + BTIM_Cmd(CW_BTIM1, ENABLE); +} + +static void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(VC13_IRQn); + __enable_irq(); +} + +void VC13_IRQHandlerCallBack(void) +{ + // 清除中断标志 + VC_ClearInterruptFlag(CW_VC1); + PB09_SETHIGH(); +} + +/** + * @brief 初始化VC模块的输入输出引脚 + * + * 此函数用于配置GPIO引脚，将PA00设置为VC1的输出引脚， + * 并将PA02设置为VC1的正输入引脚。 + */ +void VC_PortInit(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + __SYSCTRL_GPIOA_CLK_ENABLE(); + + //set PA00 as VC1 output + GPIO_InitStruct.Pins = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + + PA00_AFx_VC1OUT(); + + //set PA02 as VC1 Positive input + PA02_ANALOG_ENABLE(); +} + +static void VC_Configuration(void) +{ + VC_InitTypeDef VC_InitStruct; + VC_BlankWindowCfg VC_BlankCfg; + + // 配置VC的端口 + VC_PortInit(); + + // 初始化 VC 模块 + VC_InitStruct.div = VC_DIV_3; // AVCC*(1+3)/8 = 0.5AVCC + VC_InitStruct.filterConfig.FilterClock = VC_FILTER_CLOCK_PCLK; + VC_InitStruct.filterConfig.FilterTime = VC_FILTER_16X_6SAMPLES; + VC_InitStruct.hysteresisEnable = TRUE; + VC_InitStruct.inputNegative = VC_INN_REF; // 内置VC参考源 + VC_InitStruct.inputPositive = VC_INP_IN1; // PA02 + VC_InitStruct.interruptMode = VC_INT_DISABLE; + VC_InitStruct.polarityInvert = FALSE; + VC_InitStruct.RefVoltage = VC_REF_AVCC; + VC_InitStruct.responseSpeed = VC_RESPONSE_SLOW; + VC_Init(CW_VC1, &VC_InitStruct); + + // 设置VC的BLANK功能 + VC_BlankCfg.BlankOutput = VC_BLANK_OUTPUT_LOW; + VC_BlankCfg.BlankTime = VC_BLANKTIME_258PCLK; + VC_BlankCfg.BlankTrigSource = VC_CR2_BTIM1TRGO; + VC_SetBlankWindow(CW_VC1, &VC_BlankCfg); + + VC_Cmd(CW_VC1, ENABLE); +} + + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + //打开GPIO时钟 + + __SYSCTRL_GPIOB_CLK_ENABLE(); + /* Configure the GPIO_LED pin */ + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Pins = GPIO_PIN_9; //LED1为PB09 + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + //LEDs are off. + PB09_SETLOW(); +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/readme.txt new file mode 100644 index 0000000..513dd29 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_blank_btim1trgo/readme.txt @@ -0,0 +1,30 @@ +示例目的： + 演示VC的BLANK功能。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟12分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. VC的滤波时钟源为PCLK + 5. PB09设置为PUSH-PULL输出 + 6. BTIM1设置为定时功能，使用PCLK的8000分频计数，即1KHz时钟计数，100ms溢出产生TRGO信号 + +演示说明： + VC输入P通道为PA02，N通道为AVCC通过电阻网络分压得到0.5AVCC，VC输出端口为PA00。 + PA02输入一个电压信号，PA02上的电压小于0.5AVCC时，PB09（LED）输出低电平，LED1灭。 + 当PA02上的电压大于0.5AVCC时， PB09（LED）输出高电平，但由于BLANK的作用，当BTIM1产生TRGO信号时， + VC将停止比较BLANKTIME设置的时间，此时VC的输出由BLANKLVL设置为低，因此会看到LED1将在程序的控制下 + 熄灭50ms，使能LED1闪烁。 + +使用说明： ++ EWARM + 1. 打开vc_detect_falling_irq.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开vc_detect_falling_irq.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/EWARM/project.ewp new file mode 100644 index 0000000..117ab32 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_vc.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/MDK/Project.uvoptx new file mode 100644 index 0000000..fa65e62 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/MDK/Project.uvoptx @@ -0,0 +1,362 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\output\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FN1 -FC1000 -FD20000000 -FF0FlashSI6680 -FL010000 -FS00 -FP0($$Device:cw32l012F8$Flash\FlashSI6680.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S1 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO23 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012F8$Flash\FlashCW32L012_TEST.FLM) + + + + + 0 + 0 + 217 + 1 +
820
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\USER\src\interrupts_cw32l012.c + + \\Project\../USER/src/interrupts_cw32l012.c\217 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 8 + 1 + 1 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_vc.c + cw32l012_vc.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/MDK/Project.uvprojx new file mode 100644 index 0000000..10d8eac --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/MDK/Project.uvprojx @@ -0,0 +1,479 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_vc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_vc.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/USER/inc/main.h new file mode 100644 index 0000000..6cbbb95 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + +#include "cw32l012_vc.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..8104669 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/USER/src/interrupts_cw32l012.c @@ -0,0 +1,442 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + if(CW_VC1->SR_f.INTF) + { + CW_VC1->SR_f.INTF = 0; + PB09_TOG(); + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/USER/src/main.c new file mode 100644 index 0000000..9d3d81d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/USER/src/main.c @@ -0,0 +1,164 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" +#include "cw32l012_vc.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint16_t gFlagIrq = FALSE; +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +void VC_PortInit(void); +void LED_Init(void); +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ** + ******************************************************************************/ +int32_t main(void) +{ + // 系统时钟配置为8MHz + + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + VC_InitTypeDef VC_InitStruct; + + //LED初始化 + LED_Init(); + //配置测试IO口 + VC_PortInit(); + + // 初始化 VC 模块 + VC_InitStruct.div = VC_DIV_3; // (3+1)/8 = 1/2 + VC_InitStruct.filterConfig.FilterClock = VC_FILTER_CLOCK_PCLK; + VC_InitStruct.filterConfig.FilterTime = VC_FILTER_16X_6SAMPLES; + VC_InitStruct.hysteresisEnable = TRUE; + VC_InitStruct.inputNegative = VC_INPUT_IN3; // 内部电阻分压 + VC_InitStruct.inputPositive = VC_INPUT_IN1; // PA02 + VC_InitStruct.interruptMode = VC_INT_FALLING | VC_INT_RISING; + VC_InitStruct.polarityInvert = FALSE; + VC_InitStruct.RefVoltage = VC_REF_AVCC; + VC_InitStruct.responseSpeed = VC_RESPONSE_SLOW; + + VC_Init(CW_VC1, &VC_InitStruct); + VC_Cmd(CW_VC1, ENABLE); + + NVIC_EnableIRQ(VC13_IRQn); + + while (1) + { + + } +} + + +/** + * @brief VC I/O初始化 + * + */ +void VC_PortInit(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + __SYSCTRL_GPIOA_CLK_ENABLE(); + + //set PA00 as VC1 output + GPIO_InitStruct.Pins = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + + PA00_AFx_VC1OUT(); + + //set PA02 as VC1 Positive input + PA02_ANALOG_ENABLE(); +} + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + //打开GPIO时钟 + + __SYSCTRL_GPIOB_CLK_ENABLE(); + /* Configure the GPIO_LED pin */ + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Pins = GPIO_PIN_9; //LED口为PB09 + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + //LEDs are off. + PB09_SETLOW(); +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/readme.txt new file mode 100644 index 0000000..88e88f0 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_fallingRising_irq/readme.txt @@ -0,0 +1,27 @@ +示例目的： + 演示VC模块的输出信号上升沿/下降沿触发中断功能。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟12分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. VC的滤波时钟源为PCLK + 5. PB09设置为PUSH-PULL输出 + +演示说明： + VC输入P通道为PA02，N通道为电阻分压，VC输出端口为PA00。 + 外接可调直流电源，当VC输入P通道电压低于或者高于N通道电压时刻，PB09（LED）输出电平翻转一次。 + 保持P通道电压低于N通道电压，或者高于N通道电压时，PB02输出电平不变； + +使用说明： ++ EWARM + 1. 打开vc_detect_falling_irq.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开vc_detect_falling_irq.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/EWARM/project.ewp new file mode 100644 index 0000000..117ab32 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_vc.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + ::CMSIS + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/MDK/Project.uvoptx new file mode 100644 index 0000000..2d8347d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/MDK/Project.uvoptx @@ -0,0 +1,320 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 1 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_vc.c + cw32l012_vc.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/MDK/Project.uvprojx new file mode 100644 index 0000000..10d8eac --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/MDK/Project.uvprojx @@ -0,0 +1,479 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.1 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_vc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_vc.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + ::CMSIS + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/USER/inc/main.h new file mode 100644 index 0000000..6cbbb95 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + +#include "cw32l012_vc.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..8104669 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/USER/src/interrupts_cw32l012.c @@ -0,0 +1,442 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + if(CW_VC1->SR_f.INTF) + { + CW_VC1->SR_f.INTF = 0; + PB09_TOG(); + } + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/USER/src/main.c new file mode 100644 index 0000000..920f902 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/USER/src/main.c @@ -0,0 +1,163 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" +#include "cw32l012_vc.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint16_t gFlagIrq = FALSE; +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +void VC_PortInit(void); +void LED_Init(void); +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ** + ******************************************************************************/ +int32_t main(void) +{ + // 系统时钟配置为8MHz + SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV12); + + VC_InitTypeDef VC_InitStruct; + + //LED初始化 + LED_Init(); + //配置测试IO口 + VC_PortInit(); + + // 初始化 VC 模块 + VC_InitStruct.div = VC_DIV_3; // (3+1)/8 = 1/2 + VC_InitStruct.filterConfig.FilterClock = VC_FILTER_CLOCK_PCLK; + VC_InitStruct.filterConfig.FilterTime = VC_FILTER_16X_6SAMPLES; + VC_InitStruct.hysteresisEnable = TRUE; + VC_InitStruct.inputNegative = VC_INPUT_IN3; // 内部电阻分压 + VC_InitStruct.inputPositive = VC_INPUT_IN1; // PA02 + VC_InitStruct.interruptMode = VC_INT_HIGH; + VC_InitStruct.polarityInvert = FALSE; + VC_InitStruct.RefVoltage = VC_REF_AVCC; + VC_InitStruct.responseSpeed = VC_RESPONSE_SLOW; + + VC_Init(CW_VC1, &VC_InitStruct); + VC_Cmd(CW_VC1, ENABLE); + + NVIC_EnableIRQ(VC13_IRQn); + + while (1) + { + + } +} + +/** + * @brief VC I/O初始化 + * + */ +void VC_PortInit(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + __SYSCTRL_GPIOA_CLK_ENABLE(); + + //set PA00 as VC1 output + GPIO_InitStruct.Pins = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + + PA00_AFx_VC1OUT(); + + //set PA02 as VC1 Positive input + PA02_ANALOG_ENABLE(); +} + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + //打开GPIO时钟 + + __SYSCTRL_GPIOB_CLK_ENABLE(); + /* Configure the GPIO_LED pin */ + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Pins = GPIO_PIN_9; //LED口为PB09 + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + //LEDs are off. + PB09_SETLOW(); +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/readme.txt new file mode 100644 index 0000000..6f5aa77 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_detect_high_irq/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 演示VC模块的输出信号高电平触发中断功能。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟12分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. VC的滤波时钟源为PCLK + 5. PB09设置为PUSH-PULL输出 + +演示说明： + VC输入P通道为PA02，N通道为内部电阻分压，VC输出端口为PA00。 + 外接可调直流电源，当VC输入P通道电压高于N通道电压时，PB09（LED）输出电平翻转。 + 延时一段时间之后，重新监测VC输入P通道电压，如果仍然高于N通道电压时，PB09输出电平继续翻转； + 如果低于N通道电压时，PB09输出电平不变。 + + +使用说明： ++ EWARM + 1. 打开vc_detect_falling_irq.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开vc_detect_falling_irq.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/EWARM/project.ewp new file mode 100644 index 0000000..48815ce --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/EWARM/project.ewp @@ -0,0 +1,2258 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_vc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_dac.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/MDK/Project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/MDK/Project.uvoptx new file mode 100644 index 0000000..bbe6af9 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/MDK/Project.uvoptx @@ -0,0 +1,416 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + DLGUARM + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + + + + + 0 + 0 + 131 + 1 +
0
+ 0 + 0 + 0 + 0 + 0 + 0 + ..\USER\src\main.c + + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\DAC + 35904 + + + System Viewer\VC1 + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_vc.c + cw32l012_vc.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_dac.c + cw32l012_dac.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_systick.c + cw32l012_systick.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 11 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/MDK/Project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/MDK/Project.uvprojx new file mode 100644 index 0000000..603ec09 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/MDK/Project.uvprojx @@ -0,0 +1,489 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.2 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_vc.c + 1 + ..\..\..\..\Libraries\src\cw32l012_vc.c + + + cw32l012_dac.c + 1 + ..\..\..\..\Libraries\src\cw32l012_dac.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/USER/inc/main.h new file mode 100644 index 0000000..6cbbb95 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/USER/inc/main.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_systick.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" + +#include "cw32l012_vc.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..cc92a2f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/USER/src/interrupts_cw32l012.c @@ -0,0 +1,438 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + VC13_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/USER/src/main.c new file mode 100644 index 0000000..0370a00 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/USER/src/main.c @@ -0,0 +1,252 @@ +/** + * @file main.c + * @brief 本文件为设备驱动库模块的主程序文件。 + * @details + * @author WHXY + * @date 2021-03-12 + * @version 1.0 + * + * @copyright + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + */ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" +#include "cw32l012_vc.h" +#include "cw32l012_dac.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +static void SYSCTRL_Configuration(void); +//static void GPIO_Configuration(void); +static void LED_Init(void); +static void NVIC_Configuration(void); +static void VC_PortInit(void); +static void VC_Configuration(void); +static void DAC_Configuration(void); + +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** + ** + ******************************************************************************/ +/** + * @brief 主函数，程序的入口点。 + * + * 该函数完成系统初始化工作，包括系统时钟配置、滴答定时器初始化、LED初始化、 + * VC模块配置、DAC模块配置以及中断向量控制器配置。随后进入一个无限循环， + * 不断更新DAC通道1的数据并触发软件触发，同时将PB09引脚置低。 + * + * @return int32_t 程序正常运行时不会返回。 + */ +int32_t main(void) +{ + uint8_t outputValue; + // 调用系统时钟配置函数，将系统时钟配置为8MHz + SYSCTRL_Configuration(); + + // 初始化滴答定时器，传入系统时钟频率8000000Hz + InitTick(8000000); + // 调用LED初始化函数，对LED进行初始化操作 + LED_Init(); + + // 调用VC模块配置函数，对VC模块进行配置 + VC_Configuration(); + // 调用DAC模块配置函数，对DAC模块进行配置 + DAC_Configuration(); + // 调用中断向量控制器配置函数，对中断向量控制器进行配置 + NVIC_Configuration(); + + while (1) + { + for (outputValue = 0; ; outputValue++) + { + DAC_SetChannel1Data(DAC_ALIGN_8B_R, outputValue); + DAC_SoftwareTrigger(DAC_CHANNEL_1); + // 延时50个滴答定时器周期 + SysTickDelay(50); + PB09_SETLOW(); + } + + } +} + +static void SYSCTRL_Configuration(void) +{ + // 系统时钟配置为8MHz + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI8MHZ); + /* 1. 设置HCLK和PCLK的分频系数　*/ + SYSCTRL_HCLKPRS_Config(SYSCTRL_HCLK_DIV1); + SYSCTRL_PCLKPRS_Config(SYSCTRL_PCLK_DIV1); + SYSCTRL_SystemCoreClockUpdate(8000000); + /* 2. 配置外设时钟 */ + __SYSCTRL_VC_CLK_ENABLE(); //使能VC模块 + + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + +} + +//static void GPIO_Configuration(void) +//{ +// GPIO_InitTypeDef GPIO_InitStruct; +//} + +static void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(VC13_IRQn); + __enable_irq(); +} + +void VC13_IRQHandlerCallBack(void) +{ + // 清除中断标志 + VC_ClearInterruptFlag(CW_VC1); + PB09_SETHIGH(); +} + +/** + * @brief 初始化VC模块的输入输出引脚 + * + * 此函数用于配置GPIO引脚，将PA00设置为VC1的输出引脚， + * 并将PA02设置为VC1的正输入引脚。 + */ +void VC_PortInit(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + __SYSCTRL_GPIOA_CLK_ENABLE(); + + //set PA00 as VC1 output + GPIO_InitStruct.Pins = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + + PA00_AFx_VC1OUT(); + + //set PA02 as VC1 Positive input + PA02_ANALOG_ENABLE(); +} + +static void VC_Configuration(void) +{ + VC_InitTypeDef VC_InitStruct; + + // 配置VC的端口 + VC_PortInit(); + + // 初始化 VC 模块 + VC_InitStruct.div = VC_DIV_0; // 此例程改参数未使用 + VC_InitStruct.filterConfig.FilterClock = VC_FILTER_CLOCK_PCLK; + VC_InitStruct.filterConfig.FilterTime = VC_FILTER_16X_6SAMPLES; + VC_InitStruct.hysteresisEnable = TRUE; + VC_InitStruct.inputNegative = VC_INN_DAC; // DAC1的输出作为参考 + VC_InitStruct.inputPositive = VC_INP_IN1; // PA02 + VC_InitStruct.interruptMode = VC_INT_FALLING; + VC_InitStruct.polarityInvert = FALSE; + VC_InitStruct.RefVoltage = VC_REF_EXT; + VC_InitStruct.responseSpeed = VC_RESPONSE_SLOW; + + VC_Init(CW_VC1, &VC_InitStruct); + + VC_Cmd(CW_VC1, ENABLE); +} + +static void DAC_Configuration(void) +{ + DAC_InitTypeDef DAC_InitStruct; + + DAC_InitStruct.DAC_ChannelState = DAC_CHANNEL_ENABLE; + DAC_InitStruct.DAC_DMAState = DAC_DMA_DISABLE; + DAC_InitStruct.DAC_DMAUnderflowState = DAC_DMA_UNDERFLOW_DISABLE; + DAC_InitStruct.DAC_TriangleAmplitude = DAC_TriangleAmplitude_255; + DAC_InitStruct.DAC_TriggerSource = DAC_TRIG_SOFTWARE; + DAC_InitStruct.DAC_TriggerState = DAC_TRIGGER_DISABLE; + DAC_InitStruct.DAC_WaveformMode = DAC_WAVE_TRIANGLE; + DAC_Init(DAC_CHANNEL_1, &DAC_InitStruct); + + DAC_Cmd(DAC_CHANNEL_1, ENABLE); + DAC_ChannelOutCmd(DAC_CHANNEL_1, DISABLE); // DAC的输出在内部提供给VC，如果需要观测波形可打开对外输出。 + DAC_SetChannel1Data(DAC_ALIGN_8B_R, 0x00); +} + +/** + * @brief LED I/O初始化 + * + */ +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + //打开GPIO时钟 + + __SYSCTRL_GPIOB_CLK_ENABLE(); + /* Configure the GPIO_LED pin */ + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Pins = GPIO_PIN_9; //LED1为PB09 + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + //LEDs are off. + PB09_SETLOW(); +} + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/readme.txt new file mode 100644 index 0000000..a9e10b0 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/VC/vc_ref_from_dac/readme.txt @@ -0,0 +1,29 @@ +示例目的： + 使用 DAC 生成一个参考电压，然后利用电压比较器 VC 将该参考电压与其他输入电压进行比较。 + +硬件资源： + 1. CW32L012 StartKit + 2. 时钟HSI + 3. 系统时钟源为HSI时钟12分频，8MHz， PCLK、HCLK不分频，PCLK=HCLK=SysClk=8MHz + 4. VC的滤波时钟源为PCLK + 5. PB09设置为PUSH-PULL输出 + +演示说明： + VC输入P通道为PA02，N通道为DAC1内部输出，VC输出端口为PA00。 + PA02输入一个电压信号，作为VC的正端输入，其负端输入内DAC的通道一输出。DAC的输出每50ms变化一次， + 当DAC的输出电压高于PA02上的电压后，VC产生中断，PB09（LED）输出高电平，LED1亮，否则LED1灭。 + + + +使用说明： ++ EWARM + 1. 打开vc_detect_falling_irq.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开vc_detect_falling_irq.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/EWARM/project.ewp new file mode 100644 index 0000000..6c3569f --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/EWARM/project.ewp @@ -0,0 +1,2252 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_wwdt.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/MDK/project.uvoptx new file mode 100644 index 0000000..fd6d153 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/MDK/project.uvoptx @@ -0,0 +1,378 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + UL2CM3 + -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST.FLM -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM) + + + + + + 0 + 1 + ((WWDT_TypeDef*) 0x40005400UL) + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\IWDT + 35905 + + + + + + + Startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + startup_cw32l012.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\system_cw32l012.c + system_cw32l012.c + 0 + 0 + + + + + User + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\USER\src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\USER\src\interrupts_cw32l012.c + interrupts_cw32l012.c + 0 + 0 + + + + + Driver + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + cw32l012_sysctrl.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + cw32l012_gpio.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_flash.c + cw32l012_flash.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\src\cw32l012_wwdt.c + cw32l012_wwdt.c + 0 + 0 + + + + + Doc + 1 + 0 + 0 + 0 + + 4 + 9 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + + Bsp + 0 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + cw32l012_startkit.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/MDK/project.uvprojx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/MDK/project.uvprojx new file mode 100644 index 0000000..4dfdc30 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/MDK/project.uvprojx @@ -0,0 +1,479 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.2 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_wwdt.c + 1 + ..\..\..\..\Libraries\src\cw32l012_wwdt.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/USER/inc/main.h new file mode 100644 index 0000000..b290f66 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/USER/inc/main.h @@ -0,0 +1,70 @@ +/** + * @file main.h + * @author WHXY + * @brief Header for main.c file. + * This file contains the common defines of the application. + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +//#include "device.h" + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_iwdt.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_flash.h" +#include "cw32l012_wwdt.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..b0bd30b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/USER/src/interrupts_cw32l012.c @@ -0,0 +1,438 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + WDT_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/USER/src/main.c new file mode 100644 index 0000000..73b7108 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/USER/src/main.c @@ -0,0 +1,183 @@ +/** + * @file main.c + * @author WHXY + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + * + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * @return int32_t + */ +int32_t main(void) +{ + WWDT_InitTypeDef WWDT_InitStruct = {0}; + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + /* GPIO Configuration */ + GPIO_Configuration(); + + SysTick_Config(SystemCoreClock / 1000 * 100); // 100ms + + //------------------------------------------------------------ + // 初始化并运行WWDT + // 8MHz / 16384 = 488.2Hz, 溢出时间 = (0x7F - 0x40) * 16384 * (1/8MHz) = 129ms + WWDT_InitStruct.CounterValue = 0x7F; + WWDT_InitStruct.PreOvInt = ENABLE; + WWDT_InitStruct.Prescaler = WWDT_PRESCALER_DIV16384; + WWDT_InitStruct.WindowValue = 0x60; // 0x60 - 0x40的窗口区间可以喂狗 + WWDT_Init(&WWDT_InitStruct); + + /* NVIC Configuration */ + NVIC_Configuration(); + + while (1) + { + // 在 WDT_IRQHandler 中，喂狗 + // 在 WDT_IRQHandler 中，对LED1的输出电平进行翻转 + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + /* HSI使能 */ + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI8MHZ); + + /* 1. 设置HCLK和PCLK的分频系数　*/ + SYSCTRL_HCLKPRS_Config(SYSCTRL_HCLK_DIV1); + SYSCTRL_PCLKPRS_Config(SYSCTRL_PCLK_DIV1); + + SYSCTRL_SystemCoreClockUpdate(8000000); + /* 2. 配置外设时钟 */ + __SYSCTRL_WWDT_CLK_ENABLE(); //使能IWDT模块 + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /* 配置PA1为按键输入 */ + + GPIO_InitStruct.IT = GPIO_IT_FALLING; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_1; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + + /* 配置PB09为LED1 */ + GPIO_InitStruct.Pins = GPIO_PIN_9 ; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(WDT_IRQn); + __enable_irq(); +} + +void SysTick_Handler(void) +{ + +} + +void WDT_IRQHandlerCallBack(void) +{ + if (CW_WWDT->SR & WWDT_SR_POV_Msk) + { + WWDT_ClearPOVFlag(); + WWDT_Feed(0x7F); + PB09_TOG(); + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/readme.txt new file mode 100644 index 0000000..fea6e26 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_int/readme.txt @@ -0,0 +1,26 @@ +示例目的： + 本样例演示 WWDT 定时产生中断，在中断服务程序中对PB09的输出电平进行翻转 + +硬件资源： + 1. CW32L012F8P6 StartKit + 2. 时钟HSI + 3. 系统时钟由HSI提供，分频为8MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=8MHz + 4. WWDT的时钟为PCLK/16384 + 5. PB09设置为PUSH-PULL输出，驱动LED1 + +演示说明： + WWDT每129ms产生一次预溢出中断，在中断中喂狗，并翻转LED1的输出电平 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/EWARM/project.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/EWARM/project.ewp new file mode 100644 index 0000000..7a43787 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/EWARM/project.ewp @@ -0,0 +1,2255 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Startup + + $PROJ_DIR$\..\..\..\..\IdeSupport\EWARM\startup_cw32l012.s + + + $PROJ_DIR$\..\..\..\..\Libraries\src\system_cw32l012.c + + + + User + + $PROJ_DIR$\..\USER\src\main.c + + + $PROJ_DIR$\..\USER\src\interrupts_cw32l012.c + + + + Driver + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_wwdt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\src\cw32l012_systick.c + + + + Doc + + $PROJ_DIR$\..\readme.txt + + + + Bsp + + $PROJ_DIR$\..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + ::CMSIS + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/EWARM/project.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/EWARM/project.eww new file mode 100644 index 0000000..692edc1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/EWARM/project.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\project.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/MDK/project.uvoptx b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/MDK/project.uvoptx new file mode 100644 index 0000000..8bc9c3a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/MDK/project.uvoptx @@ -0,0 +1,390 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.0.0.2 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + + + + + + + + + + $$Device:CW32L012C8$SVD\CW32L012.sfr + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\IDEsupport\MDK;..\..\..\..\Libraries\inc;..\..\..\..\StartKit_Board;..\USER\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\IdeSupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\Libraries\src\cw32l012_gpio.c + + + cw32l012_flash.c + 1 + ..\..\..\..\Libraries\src\cw32l012_flash.c + + + cw32l012_wwdt.c + 1 + ..\..\..\..\Libraries\src\cw32l012_wwdt.c + + + cw32l012_systick.c + 1 + ..\..\..\..\Libraries\src\cw32l012_systick.c + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + Bsp + + + cw32l012_startkit.c + 1 + ..\..\..\..\StartKit_Board\cw32l012_startkit.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..8590487 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts_cw32l012.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ + +extern void WDT_IRQHandlerCallBack(void); +extern void LVD_IRQHandlerCallBack(void); +extern void RTC_IRQHandlerCallBack(void); +extern void FLASHRAM_IRQHandlerCallBack(void); +extern void SYSCTRL_IRQHandlerCallBack(void); +extern void GPIOA_IRQHandlerCallBack(void); +extern void GPIOB_IRQHandlerCallBack(void); +extern void GPIOC_IRQHandlerCallBack(void); +extern void GPIOF_IRQHandlerCallBack(void); +extern void DMACH12_IRQHandlerCallBack(void); +extern void DMACH34_IRQHandlerCallBack(void); +extern void CORDIC_IRQHandlerCallBack(void); +extern void ADC1_IRQHandlerCallBack(void); +extern void ATIM_IRQHandlerCallBack(void); +extern void VC13_IRQHandlerCallBack(void); +extern void VC24_IRQHandlerCallBack(void); +extern void GTIM1_IRQHandlerCallBack(void); +extern void GTIM2_IRQHandlerCallBack(void); +extern void GTIM34_IRQHandlerCallBack(void); +extern void LPTIM_IRQHandlerCallBack(void); +extern void BTIM1_IRQHandlerCallBack(void); +extern void BTIM2_IRQHandlerCallBack(void); +extern void BTIM3_HALLTIM_IRQHandlerCallBack(void); +extern void I2C1_IRQHandlerCallBack(void); +extern void I2C2_IRQHandlerCallBack(void); +extern void SPI1_IRQHandlerCallBack(void); +extern void SPI23_IRQHandlerCallBack(void); +extern void UART1_IRQHandlerCallBack(void); +extern void UART2_IRQHandlerCallBack(void); +extern void UART3_IRQHandlerCallBack(void); +extern void ADC2_DAC_IRQHandlerCallBack(void); +extern void CLKFAULT_IRQHandlerCallBack(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/USER/inc/main.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/USER/inc/main.h new file mode 100644 index 0000000..61ed2df --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/USER/inc/main.h @@ -0,0 +1,70 @@ +/** + * @file main.h + * @author WHXY + * @brief Header for main.c file. + * This file contains the common defines of the application. + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +//#include "device.h" + + +#include "interrupts_cw32l012.h" +#include "cw32l012_startkit.h" +#include "cw32l012_iwdt.h" +#include "cw32l012_gpio.h" +#include "cw32l012_systick.h" +#include "cw32l012_flash.h" +#include "cw32l012_wwdt.h" + + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ +/* USER CODE END ET */ + + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +/* USER CODE END EC */ + + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +/* USER CODE END EM */ + + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ +/* USER CODE END EFP */ + + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ +/* USER CODE END Private defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..b0bd30b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/USER/src/interrupts_cw32l012.c @@ -0,0 +1,438 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file interrupts.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 CW. + * All rights reserved.

+ * + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "..\inc\main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ +/* USER CODE END TD */ + + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +/* USER CODE END PM */ + + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + + +/******************************************************************************/ +/* Cortex-M0P Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn */ + + /* USER CODE END NonMaskableInt_IRQn */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn */ + + /* USER CODE END HardFault_IRQn */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn */ + + /* USER CODE END W1_HardFault_IRQn */ + } +} + + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn */ + + /* USER CODE END SVCall_IRQn */ +} + + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn */ + + /* USER CODE END PendSV_IRQn */ +} + + + +/******************************************************************************/ +/* CW030 Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_ps030.s). */ +/******************************************************************************/ + +/** + * @brief This funcation handles WDT + */ +void WDT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + WDT_IRQHandlerCallBack(); + /* USER CODE END */ +} + +/** + * @brief This funcation handles LVD + */ +void LVD_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles RTC + */ +void RTC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FLASHRAM + */ +void FLASHRAM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SYSCTRL + */ +void SYSCTRL_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOA + */ +void GPIOA_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOB + */ +void GPIOB_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOC + */ +void GPIOC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GPIOF + */ +void GPIOF_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH1/DMACH2 + */ +void DMACH12_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles DMACH3/DMACH4 + */ +void DMACH34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles CORDIC + */ +void CORDIC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC1 + */ +void ADC1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ATIM + */ +void ATIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC1/VC3 + */ +void VC13_IRQHandler(void) +{ + /* USER CODE BEGIN */ + /* USER CODE END */ +} + +/** + * @brief This funcation handles VC2/VC4 + */ +void VC24_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM1 + */ +void GTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM2 + */ +void GTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles GTIM3/4 + */ +void GTIM34_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles LPTIM + */ +void LPTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM1 + */ +void BTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM2 + */ +void BTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles BTIM3 and HALLTIM + */ +void BTIM3_HALLTIM_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C1 + */ +void I2C1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles I2C2 + */ +void I2C2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI1 + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles SPI2/3 + */ +void SPI23_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART1 + */ +void UART1_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART2 + */ +void UART2_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles UART3 + */ +void UART3_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles ADC2 and DAC + */ +void ADC2_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/** + * @brief This funcation handles FAULT + */ +void CLKFAULT_IRQHandler(void) +{ + /* USER CODE BEGIN */ + + /* USER CODE END */ +} + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/USER/src/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/USER/src/main.c new file mode 100644 index 0000000..4c1c4b1 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/USER/src/main.c @@ -0,0 +1,191 @@ +/** + * @file main.c + * @author WHXY + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + * + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "../inc/main.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +void SYSCTRL_Configuration(void); +void GPIO_Configuration(void); +void NVIC_Configuration(void); + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief + * @return int32_t + */ +int32_t main(void) +{ + WWDT_InitTypeDef WWDT_InitStruct; + /* System Clocks Configuration */ + SYSCTRL_Configuration(); + + /* GPIO Configuration */ + GPIO_Configuration(); + + SysTick_Config(SystemCoreClock / 1000); // 1ms systick节拍 + + // 快速闪烁4次 + for (uint8_t i=0; i<8; i++) + { + PB09_TOG(); + SysTickDelay(100); + } + + //------------------------------------------------------------ + // 初始化并运行WWDT + // 131072 *(1/8MHz) = 16.4ms, 溢出时间 = (0x7F - 0x40) * 16384 * (1/8MHz) = 1.048s + WWDT_InitStruct.CounterValue = 0x7F; + WWDT_InitStruct.PreOvInt = DISABLE; + WWDT_InitStruct.Prescaler = WWDT_PRESCALER_DIV131072; + WWDT_InitStruct.WindowValue = 0x60; // 0x60 - 0x40的窗口区间可以喂狗 + WWDT_Init(&WWDT_InitStruct); + + //------------------------------------------------------------ + // 在6秒内，持续喂狗并慢速闪烁LED + for (uint8_t i=0; i<6; i++) + { + PB09_SETHIGH(); + SysTickDelay(600); + WWDT_Feed(0x7F); + + PB09_SETLOW(); + SysTickDelay(600); + WWDT_Feed(0x7F); + } + + //------------------------------------------------------------ + // 不再喂狗，约1秒后，WWDT 自动复位 + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void SYSCTRL_Configuration(void) +{ + /* HSI使能 */ + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI8MHZ); + + /* 1. 设置HCLK和PCLK的分频系数　*/ + SYSCTRL_HCLKPRS_Config(SYSCTRL_HCLK_DIV1); + SYSCTRL_PCLKPRS_Config(SYSCTRL_PCLK_DIV1); + + SYSCTRL_SystemCoreClockUpdate(8000000); + /* 2. 配置外设时钟 */ + __SYSCTRL_WWDT_CLK_ENABLE(); //使能IWDT模块 + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); +} + +/** + * @brief Configure the GPIO Pins. + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /* 配置PA1为按键输入 */ + + GPIO_InitStruct.IT = GPIO_IT_FALLING; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pins = GPIO_PIN_1; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + + /* 配置PB09为LED1 */ + GPIO_InitStruct.Pins = GPIO_PIN_9 ; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + +} + +/** + * @brief Configure the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + __disable_irq(); + NVIC_EnableIRQ(WDT_IRQn); + __enable_irq(); +} + + +void WDT_IRQHandlerCallBack(void) +{ + +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/readme.txt b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/readme.txt new file mode 100644 index 0000000..1e61d4c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/WWDT/WWDT_reset/readme.txt @@ -0,0 +1,26 @@ +示例目的： + 本样例演示 WWDT 的启动及重载及复位 + +硬件资源： + 1. CW32L012F8P6 StartKit + 2. 时钟HSI + 3. 系统时钟由HSI提供，分频为8MHz， PCLK、HCLK不分频， + PCLK=HCLK=SysClk=8MHz + 4. WWDT的时钟为PCLK/131072 + 5. PB09设置为PUSH-PULL输出，驱动LED1 + +演示说明： + 程序上电后，LED1快速闪烁4次，然后慢速闪6次，约1秒后，程序复位。 + +使用说明： ++ EWARM + 1. 打开project.eww文件 + 2. 编译所有文件：Project->Rebuild all + 3. 载入工程镜像：Project->Debug + 4. 运行程序：Debug->Go(F5) + ++ MDK-ARM + 1. 打开project.uvproj文件 + 2. 编译所有文件：Project->Rebuild all target files + 3. 载入工程镜像：Debug->Start/Stop Debug Session + 4. 运行程序：Debug->Run(F5) diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/cleanup.bat b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/cleanup.bat new file mode 100644 index 0000000..a1c70db --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Examples/cleanup.bat @@ -0,0 +1,57 @@ +del *.bak /s +del *.orig /s +:: keil +del *.axf /s +del *.htm /s +del *.hex /s +del *.lnp /s +del *.sct /s +del *.crf /s +del *.d /s +del *.o /s +del *.dep /s +del *.map /s +del *.lst /s +del *.i /s +del *.scvd /s +del *.uvguix.* /s +del *.Socrates /s +del /s/q output +del JLink*.* /s + +:: IAR +rem del *.hex /s +del *.out /s +del *.sim /s +del *.linf /s +del *.pbi /s +rem del *.o /s +del *.xcl /s +del *.browse /s +del *.pbd /s +del *.pbw /s +del Backup*.ewp /s +del *.ewt /s +del *.reggroups /s +del *.crun /s +del *.dbgdt /s +del *.cspy.* /s +del *.wsdt /s +del *.jlink /s + +del *.svd /s +del *.bak /s + +cd %~dp0 +for /F "delims=" %%a in ('dir /ad/s/b output') do rd /s/q "%%~a" +for /F "delims=" %%a in ('dir /ad/s/b settings') do rd /s/q "%%~a" +for /F "delims=" %%a in ('dir /ad/s/b Release') do rd /s/q "%%~a" +for /F "delims=" %%a in ('dir /ad/s/b RTE') do rd /s/q "%%~a" +for /F "delims=" %%a in ('dir /ad/s/b flashloader') do rd /s/q "%%~a" +for /F "delims=" %%a in ('dir /ad/s/b objects') do rd /s/q "%%~a" +for /F "delims=" %%a in ('dir /ad/s/b listings') do rd /s/q "%%~a" +for /F "delims=" %%a in ('dir /ad/s/b debug') do rd /s/q "%%~a" +rem for /F "delims=" %%a in ('dir /ad/s/b EWARM') do rd /s/q "%%~a" +del *.icf /s +pause +exit diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/debugger/WHXY/CW32L012.svd b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/debugger/WHXY/CW32L012.svd new file mode 100644 index 0000000..3642790 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/debugger/WHXY/CW32L012.svd @@ -0,0 +1,15590 @@ + + + Wuhan Xinyuan Semiconductor Co.Ltd + WHXY + CW32L012 + CW32L012x8xx + ARMCM0P + 1.2 + + CM0+ + r0p1 + little + false + false + 2 + false + + 8 + 32 + 32 + read-write + 0x0 + 0x0 + + + ADC1 + desc ADC1 + 0x40000000 + + ADC1 + ADC Interrupt + 12 + + ADC + ADC + 32 + + 0x0 + 0x7C + registers + + + + CR + desc CR + 0x0 + 32 + read-write + + + SAM + desc SAM + 9 + 8 + read-write + + + SLAVE + desc SLAVE + 7 + 7 + read-write + + + ENS + desc ENS + 6 + 4 + read-write + + + CLK + desc CLK + 3 + 2 + read-write + + + CONT + desc CONT + 1 + 1 + read-write + + + EN + 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32 + read-write + + + REP + desc REP + 15 + 0 + read-write + + + + + CCR1 + capture compare register1 + 0x34 + 32 + read-write + + + CCR1 + desc CCR1 + 15 + 0 + read-write + + + + + CCR2 + capture compare register2 + 0x38 + 32 + read-write + + + CCR2 + desc CCR2 + 15 + 0 + read-write + + + + + CCR3 + capture compare register3 + 0x3C + 32 + read-write + + + CCR3 + desc CCR3 + 15 + 0 + read-write + + + + + CCR4 + capture compare register4 + 0x40 + 32 + read-write + + + CCR4 + desc CCR4 + 15 + 0 + read-write + + + + + CCR5 + capture compare register5 + 0x48 + 32 + read-write + + + GC5C6 + desc GC5C6 + 31 + 31 + read-write + + + GC5C5 + desc GC5C5 + 30 + 30 + read-write + + + GC5C4 + desc GC5C4 + 29 + 29 + read-write + + + GC5C3 + desc GC5C3 + 28 + 28 + read-write + + + GC5C2 + desc GC5C2 + 27 + 27 + read-write + + + GC5C1 + desc GC5C1 + 26 + 26 + read-write + + + CCR5 + desc CCR5 + 15 + 0 + read-write + + + + + CCR6 + capture compare register6 + 0x4C + 32 + read-write + + + GC6C6 + desc GC6C6 + 31 + 31 + read-write + + + GC6C5 + desc GC6C5 + 30 + 30 + read-write + + + GC6C4 + desc GC6C4 + 29 + 29 + read-write + + + GC6C3 + desc GC6C3 + 28 + 28 + read-write + + + GC6C2 + desc GC6C2 + 27 + 27 + read-write + + + GC6C1 + desc GC6C1 + 26 + 26 + read-write + + + CCR6 + desc CCR6 + 15 + 0 + read-write + + + + + BDTR + break and dead-time register + 0x44 + 32 + read-write + + + BK2P + desc BK2P + 25 + 25 + read-write + + + BK2E + desc BK2E + 24 + 24 + read-write + + + BK2F + desc BK2F + 23 + 20 + read-write + + + BKF + desc BKF + 19 + 16 + read-write + + + MOE + desc MOE + 15 + 15 + read-write + + + AOE + desc AOE + 14 + 14 + read-write + + + BKP + desc BKP + 13 + 13 + read-write + + + BKE + desc BKE + 12 + 12 + read-write + + + OSSR + desc OSSR + 11 + 11 + read-write + + + OSSI + desc OSSI + 10 + 10 + read-write + + + LOCK + desc LOCK + 9 + 8 + read-write + + + DTG + desc DTG + 7 + 0 + read-write + + + + + DTR2 + dead-time register2 + 0x54 + 32 + read-write + + + DTPE + desc DTPE + 17 + 17 + read-write + + + DTAE + desc DTAE + 16 + 16 + read-write + + + DTGF + desc DTGF + 7 + 0 + read-write + + + + + ECR + Encoder control Register + 0x58 + 32 + read-write + + + IPOS + desc IPOS + 7 + 6 + read-write + + + FIDX + desc FIDX + 5 + 5 + read-write + + + IDIR + desc IDIR + 2 + 1 + read-write + + + IE + desc IE + 0 + 0 + read-write + + + + + TISEL1 + Timer Input Select Register1 + 0x5C + 32 + read-write + + + TI4SEL + desc TI4SEL + 27 + 24 + read-write + + + TI3SEL + desc TI3SEL + 19 + 16 + read-write + + + TI2SEL + desc TI2SEL + 11 + 8 + read-write + + + TI1SEL + desc TI1SEL + 3 + 0 + read-write + + + + + TISEL2 + Timer Input Select Register2 + 0x6C + 32 + read-write + + + TI6SEL + desc TI6SEL + 11 + 8 + read-write + + + TI5SEL + desc TI5SEL + 3 + 0 + read-write + + + + + AF1 + Alternate function Register1 + 0x60 + 32 + read-write + + + ETRSEL + desc ETRSEL + 19 + 16 + read-write + + + BKVC4P + desc BKVC4P + 13 + 13 + read-write + + + BKVC3P + desc BKVC3P + 12 + 12 + read-write + + + BKVC2P + desc BKVC2P + 11 + 11 + read-write + + + BKVC1P + desc BKVC1P + 10 + 10 + read-write + + + BKINP + desc BKINP + 9 + 9 + read-write + + + BKVC4E + desc BKVC4E + 4 + 4 + read-write + + + BKVC3E + desc BKVC3E + 3 + 3 + read-write + + + BKVC2E + desc BKVC2E + 2 + 2 + read-write + + + BKVC1E + desc BKVC1E + 1 + 1 + read-write + + + BKINE + desc BKINE + 0 + 0 + read-write + + + + + AF2 + Alternate function Register2 + 0x64 + 32 + read-write + + + OCRSEL + desc OCRSEL + 19 + 16 + read-write + + + BK2VC4P + desc BK2VC4P + 13 + 13 + read-write + + + BK2VC3P + desc BK2VC3P + 12 + 12 + read-write + + + BK2VC2P + desc BK2VC2P + 11 + 11 + read-write + + + BK2VC1P + desc BK2VC1P + 10 + 10 + read-write + + + BK2INP + desc BK2INP + 9 + 9 + read-write + + + BK2VC4E + desc BK2VC4E + 4 + 4 + read-write + + + BK2VC3E + desc BK2VC3E + 3 + 3 + read-write + + + BK2VC2E + desc BK2VC2E + 2 + 2 + read-write + + + BK2VC1E + desc BK2VC1E + 1 + 1 + read-write + + + BK2INE + desc BK2INE + 0 + 0 + read-write + + + + + ICR + Interrupt clean register + 0x70 + 32 + read-write + + + TERRF + desc TERRF + 23 + 23 + read-write + + + IERRF + desc IERRF + 22 + 22 + read-write + + + DIRF + desc DIRF + 21 + 21 + read-write + + + IDXF + desc IDXF + 20 + 20 + read-write + + + CC6OF + desc CC6OF + 19 + 19 + read-write + + + CC5OF + desc CC5OF + 18 + 18 + read-write + + + CC6IF + desc CC6IF + 17 + 17 + read-write + + + CC5IF + desc CC5IF + 16 + 16 + read-write + + + SBIF + desc SBIF + 13 + 13 + read-write + + + CC4OF + desc CC4OF + 12 + 12 + read-write + + + CC3OF + desc CC3OF + 11 + 11 + read-write + + + CC2OF + desc CC2OF + 10 + 10 + read-write + + + CC1OF + desc CC1OF + 9 + 9 + read-write + + + B2IF + desc B2IF + 8 + 8 + read-write + + + BIF + desc BIF + 7 + 7 + read-write + + + TIF + desc TIF + 6 + 6 + read-write + + + COMIF + desc COMIF + 5 + 5 + read-write + + + CC4IF + desc CC4IF + 4 + 4 + read-write + + + CC3IF + desc CC3IF + 3 + 3 + read-write + + + CC2IF + desc CC2IF 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+ 17 + 17 + read-write + + + RSTIPOL + desc RSTIPOL + 16 + 16 + read-write + + + TRGIFLT + desc TRGIFLT + 14 + 12 + read-write + + + MSM + desc MSM + 11 + 11 + read-write + + + TRGISRC + desc TRGISRC + 10 + 7 + read-write + + + RSTISRC + desc RSTISRC + 6 + 3 + read-write + + + SMS + desc SMS + 2 + 0 + read-write + + + + + DIER + Interrupt enable register + 0xC + 32 + read-write + + + TDE + desc TDE + 14 + 14 + read-write + + + UDE + desc UDE + 8 + 8 + read-write + + + TIE + desc TIE + 6 + 6 + read-write + + + UIE + desc UIE + 0 + 0 + read-write + + + + + ISR + Interrupt status register + 0x10 + 32 + read-only + + + TIF + desc TIF + 6 + 6 + read-only + + + UIF + desc UIF + 0 + 0 + read-only + + + + + ICR + Interrupt flag clear register + 0x18 + 32 + read-write + + + TIF + desc TIF + 6 + 6 + read-write + + + UIF + desc UIF + 0 + 0 + read-write + + + + + EGR + Event Generate register + 0x14 + 32 + write-only + + + TG + desc TG + 6 + 6 + write-only + + + UG + desc UG + 0 + 0 + write-only + + + + + + CNT + Counter Register + 0x24 + 32 + read-write + + + UIFCPY + desc UIFCPY + 31 + 31 + read-only + + + CNT + desc CNT + 15 + 0 + read-write + + + + + PSC + Prescaler Control Register + 0x28 + 32 + read-write + + + PSC + desc PSC + 15 + 0 + read-write + + + + + ARR + Auto Reload Register + 0x2C + 32 + read-write + + + ARR + desc ARR + 15 + 0 + read-write + + + + + + + BTIM2 + Base Timer 2 + 0x40004840 + + BTIM2 + Base Timer2 Interrupt + 21 + + + + BTIM3 + Base Timer 3 + 0x40004880 + + BTIM3_HALLTIM + Base Timer3 and Hall timer Interrupt + 22 + + + + CORDIC + desc CORDIC + 0x40023400 + + CORDIC + desc CORDIC + 11 + + CORDIC + 32 + + 0x0 + 0x10 + registers + + + + CSR + Control and State register + 0x0 + 32 + read-write + + + BUSY + desc BUSY + 17 + 17 + read-only + + + EOC + desc EOC + 16 + 16 + read-only + + + DMAIDLE + desc DMAIDLE + 15 + 15 + read-write + + + DMAEOC + desc DMAEOC + 14 + 14 + read-write + + + IE + desc IE + 13 + 13 + read-write + + + COMP + desc COMP + 12 + 12 + read-write + + + ITER + desc ITER + 11 + 8 + read-write + + + FORMAT + desc FORMAT + 7 + 7 + read-write + + + SCALE + desc SCALE + 6 + 4 + read-write + + + FUNC + desc FUNC + 3 + 0 + read-write + + + + + X + Data register X + 0x4 + 32 + read-write + + + X + desc X + 31 + 0 + read-write + + + + + Y + Data register Y + 0x8 + 32 + read-write + + + Y + desc Y + 31 + 0 + read-write + + + + + Z + desc Z + 0xC + 32 + read-write + + + Z + desc Z + 31 + 0 + read-write + + + + + + + CRC + desc CRC + 0x40023000 + CRC + 32 + + 0x0 + 0x10 + registers + + + + CR + Control register + 0x0 + 32 + read-write + + + MODE + desc MODE + 3 + 0 + read-write + + + + + DR + Data register + 0x8 + 32 + read-write + + + DR + desc DR + 7 + 0 + read-write + + + + + RESULT + Result register + 0xC + 32 + read-only + + + RESULT + desc RESULT + 15 + 0 + read-only + + + + + + + DAC + desc DAC + 0x400000C0 + + ADC2_DAC + ADC2 and DAC Interrupt + 30 + + DAC + 32 + + 0x0 + 0x38 + registers + + + + CR0 + Control register + 0x0 + 32 + read-write + + + DMAUDRIE2 + desc DMAUDRIE2 + 29 + 29 + read-write + + + DMAEN2 + desc DMAEN2 + 28 + 28 + read-write + + + MAMP2 + desc MAMP2 + 27 + 24 + read-write + + + WAVE2 + desc WAVE2 + 23 + 22 + read-write + + + TSEL2 + desc TSEL2 + 21 + 18 + read-write + + + TEN2 + desc TEN2 + 17 + 17 + read-write + + + EN2 + desc EN2 + 16 + 16 + read-write + + + DMAUDRIE1 + desc DMAUDRIE1 + 13 + 13 + read-write + + + DMAEN1 + desc DMAEN1 + 12 + 12 + read-write + + + MAMP1 + desc MAMP1 + 11 + 8 + read-write + + + WAVE1 + desc WAVE1 + 7 + 6 + read-write + + + TSEL1 + desc TSEL1 + 5 + 2 + read-write + + + TEN1 + desc TEN1 + 1 + 1 + read-write + + + EN1 + desc EN1 + 0 + 0 + read-write + + + + + SWTRGR + Data register + 0x4 + 32 + read-write + + + SWTRIG2 + desc SWTRIG2 + 1 + 1 + read-write + + + SWTRIG1 + desc SWTRIG1 + 0 + 0 + read-write + + + + + DHR12R1 + desc DHR12R1 + 0x08 + 32 + read-write + + + DATA + desc DATA + 11 + 0 + read-write + + + + + DHR12L1 + desc DHR12L1 + 0x0C + 32 + read-write + + + DATA + desc DATA + 15 + 4 + read-write + + + + + DHR8R1 + desc DHR8R1 + 0x10 + 32 + read-write + + + DATA + desc DATA + 7 + 4 + read-write + + + + + DHR12R2 + desc DHR12R2 + 0x14 + 32 + read-write + + + DATA + desc DATA + 11 + 0 + read-write + + + + + DHR12L2 + desc DHR12L2 + 0x18 + 32 + read-write + + + DATA + desc DATA + 15 + 4 + read-write + + + + + DHR8R2 + desc DHR8R2 + 0x1C + 32 + read-write + + + DATA + desc DATA + 7 + 4 + read-write + + + + + DHR12RD + desc DHR12RD + 0x20 + 32 + read-write + + + C2DATA + desc C2DATA + 27 + 16 + read-write + + + C1DATA + desc C1DATA + 11 + 0 + read-write + + + + + DHR12LD + desc DHR12LD + 0x24 + 32 + read-write + + + C2DATA + desc C2DATA + 31 + 20 + read-write + + + C1DATA + desc C1DATA + 15 + 4 + read-write + + + + + DHR8RD + desc DHR8RD + 0x28 + 32 + read-write + + + C2DATA + desc C2DATA + 15 + 8 + read-write + + + C1DATA + desc C1DATA + 7 + 0 + read-write + + + + + DOR1 + desc DOR1 + 0x2C + 32 + read-write + + + DMAUDR + desc DMAUDR + 15 + 15 + read-write + + + DATA + desc DATA + 11 + 0 + read-write + + + + + DOR2 + desc DOR2 + 0x30 + 32 + read-write + + + DMAUDR + desc DMAUDR + 15 + 15 + read-write + + + DATA + desc DATA + 11 + 0 + read-write + + + + + CR1 + Result register + 0x34 + 32 + read-write + + + C2OUT + desc C2OUT + 1 + 1 + read-write + + + C1OUT + desc C1OUT + 0 + 0 + read-write + + + + + + + DMA + desc DMA + 0x40020000 + + DMACH12 + DMA Channel 1/2 Interrupt + 9 + + DMA + DMA + 32 + + 0x0 + 0xA0 + registers + + + + ISR + Interrupt status register + 0x0 + 32 + read-only + + + TE4 + desc TE4 + 13 + 13 + read-only + + + TC4 + desc TC4 + 12 + 12 + read-only + + + TE3 + desc TE3 + 9 + 9 + read-only + + + TC3 + desc TC3 + 8 + 8 + read-only + + + TE2 + desc TE2 + 5 + 5 + read-only + + + TC2 + desc TC2 + 4 + 4 + read-only + + + TE1 + desc TE1 + 1 + 1 + read-only + + + TC1 + desc TC1 + 0 + 0 + read-only + + + + + ICR + Interrupt flag clear register + 0x4 + 32 + read-write + + + TE4 + desc TE4 + 13 + 13 + read-write + + + TC4 + desc TC4 + 12 + 12 + read-write + + + TE3 + desc TE3 + 9 + 9 + read-write + + + TC3 + desc TC3 + 8 + 8 + read-write + + + TE2 + desc TE2 + 5 + 5 + read-write + + + TC2 + desc TC2 + 4 + 4 + read-write + + + TE1 + desc TE1 + 1 + 1 + read-write + + + TC1 + desc TC1 + 0 + 0 + read-write + + + + + CSR1 + Channel1 control and status register + 0x20 + 32 + read-write + + + DSTLOAD + desc DSTLOAD + 15 + 15 + read-write + + + SRCLOAD + desc SRCLOAD + 14 + 14 + read-write + + + TE + desc TE + 13 + 13 + read-only + + + TC + desc TC + 12 + 12 + read-only + + + RESTART + desc RESTART + 11 + 11 + read-write + + + STATUS + desc STATUS + 10 + 8 + read-write + + + SIZE + desc SIZE + 7 + 6 + read-write + + + DSTINC + desc DSTINC + 5 + 5 + read-write + + + SRCINC + desc SRCINC + 4 + 4 + read-write + + + TRANS + desc TRANS + 3 + 3 + read-write + + + TEIE + desc TEIE + 2 + 2 + read-write + + + TCIE + desc TCIE + 1 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + TRIG1 + Channel1 trigger register + 0x30 + 32 + read-write + + + HARDSRC + desc HARDSRC + 7 + 2 + read-write + + + SOFTSRC + desc SOFTSRC + 1 + 1 + read-write + + + TYPE + desc TYPE + 0 + 0 + read-write + + + + + CNT1 + Channel1 counter register + 0x24 + 32 + read-write + + + REPEAT + desc REPEAT + 19 + 16 + read-write + + + CNT + desc CNT + 15 + 0 + read-write + + + + + SRCADDR1 + Channel1 source address register + 0x28 + 32 + read-write + + + SRCADDR + desc SRCADDR + 31 + 0 + read-write + + + + + DSTADDR1 + Channel1 destination address register + 0x2C + 32 + read-write + + + DSTADDR + desc DSTADDR + 31 + 0 + read-write + + + + + CCNT1 + Channel1 trigger register + 0x34 + 32 + read-write + + + CREPEAT + desc CREPEAT + 19 + 16 + read-write + + + CCNT + desc CCNT + 15 + 0 + read-write + + + + + CSRCADDR1 + Channel1 source address register + 0x38 + 32 + read-only + + + CSRCADDR + desc CSRCADDR + 31 + 0 + read-only + + + + + CDSTADDR1 + Channel1 destination address register + 0x3C + 32 + read-only + + + CDSTADDR + desc CDSTADDR + 31 + 0 + read-only + + + + + CSR2 + Channel1 control and status register + 0x40 + 32 + read-write + + + DSTLOAD + desc DSTLOAD + 15 + 15 + read-write + + + SRCLOAD + desc SRCLOAD + 14 + 14 + read-write + + + TE + desc TE + 13 + 13 + read-only + + + TC + desc TC + 12 + 12 + read-only + + + RESTART + desc RESTART + 11 + 11 + read-write + + + STATUS + desc STATUS + 10 + 8 + read-write + + + SIZE + desc SIZE + 7 + 6 + read-write + + + DSTINC + desc DSTINC + 5 + 5 + read-write + + + SRCINC + desc SRCINC + 4 + 4 + read-write + + + TRANS + desc TRANS + 3 + 3 + read-write + + + TEIE + desc TEIE + 2 + 2 + read-write + + + TCIE + desc TCIE + 1 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + CNT2 + Channel1 counter register + 0x44 + 32 + read-write + + + REPEAT + desc REPEAT + 19 + 16 + read-write + + + CNT + desc CNT + 15 + 0 + read-write + + + + + SRCADDR2 + Channel1 source address register + 0x48 + 32 + read-write + + + SRCADDR + desc SRCADDR + 31 + 0 + read-write + + + + + DSTADDR2 + Channel1 destination address register + 0x4C + 32 + read-write + + + DSTADDR + desc DSTADDR + 31 + 0 + read-write + + + + + TRIG2 + Channel1 trigger register + 0x50 + 32 + read-write + + + HARDSRC + desc HARDSRC + 7 + 2 + read-write + + + SOFTSRC + desc SOFTSRC + 1 + 1 + read-write + + + TYPE + desc TYPE + 0 + 0 + read-write + + + + + CCNT2 + Channel1 trigger register + 0x54 + 32 + read-write + + + CREPEAT + desc CREPEAT + 19 + 16 + read-write + + + CCNT + desc CCNT + 15 + 0 + read-write + + + + + CSRCADDR2 + Channel1 source address register + 0x58 + 32 + read-only + + + CSRCADDR + desc CSRCADDR + 31 + 0 + read-only + + + + + CDSTADDR2 + Channel1 destination address register + 0x5C + 32 + read-only + + + CDSTADDR + desc CDSTADDR + 31 + 0 + read-only + + + + + CSR3 + Channel1 control and status register + 0x60 + 32 + read-write + + + DSTLOAD + desc DSTLOAD + 15 + 15 + read-write + + + SRCLOAD + desc SRCLOAD + 14 + 14 + read-write + + + TE + desc TE + 13 + 13 + read-only + + + TC + desc TC + 12 + 12 + read-only + + + RESTART + desc RESTART + 11 + 11 + read-write + + + STATUS + desc STATUS + 10 + 8 + read-write + + + SIZE + desc SIZE + 7 + 6 + read-write + + + DSTINC + desc DSTINC + 5 + 5 + read-write + + + SRCINC + desc SRCINC + 4 + 4 + read-write + + + TRANS + desc TRANS + 3 + 3 + read-write + + + TEIE + desc TEIE + 2 + 2 + read-write + + + TCIE + desc TCIE + 1 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + CNT3 + Channel1 counter register + 0x64 + 32 + read-write + + + REPEAT + desc REPEAT + 19 + 16 + read-write + + + CNT + desc CNT + 15 + 0 + read-write + + + + + SRCADDR3 + Channel1 source address register + 0x68 + 32 + read-write + + + SRCADDR + desc SRCADDR + 31 + 0 + read-write + + + + + DSTADDR3 + Channel1 destination address register + 0x6C + 32 + read-write + + + DSTADDR + desc DSTADDR + 31 + 0 + read-write + + + + + TRIG3 + Channel1 trigger register + 0x70 + 32 + read-write + + + HARDSRC + desc HARDSRC + 7 + 2 + read-write + + + SOFTSRC + desc SOFTSRC + 1 + 1 + read-write + + + TYPE + desc TYPE + 0 + 0 + read-write + + + + + CCNT3 + Channel1 trigger register + 0x74 + 32 + read-write + + + CREPEAT + desc CREPEAT + 19 + 16 + read-write + + + CCNT + desc CCNT + 15 + 0 + read-write + + + + + CSRCADDR3 + Channel1 source address register + 0x78 + 32 + read-only + + + CSRCADDR + desc CSRCADDR + 31 + 0 + read-only + + + + + CDSTADDR3 + Channel1 destination address register + 0x7C + 32 + read-only + + + CDSTADDR + desc CDSTADDR + 31 + 0 + read-only + + + + + CSR4 + Channel1 control and status register + 0x80 + 32 + read-write + + + DSTLOAD + desc DSTLOAD + 15 + 15 + read-write + + + SRCLOAD + desc SRCLOAD + 14 + 14 + read-write + + + TE + desc TE + 13 + 13 + read-only + + + TC + desc TC + 12 + 12 + read-only + + + RESTART + desc RESTART + 11 + 11 + read-write + + + STATUS + desc STATUS + 10 + 8 + read-write + + + SIZE + desc SIZE + 7 + 6 + read-write + + + DSTINC + desc DSTINC + 5 + 5 + read-write + + + SRCINC + desc SRCINC + 4 + 4 + read-write + + + TRANS + desc TRANS + 3 + 3 + read-write + + + TEIE + desc TEIE + 2 + 2 + read-write + + + TCIE + desc TCIE + 1 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + CNT4 + Channel1 counter register + 0x84 + 32 + read-write + + + REPEAT + desc REPEAT + 19 + 16 + read-write + + + CNT + desc CNT + 15 + 0 + read-write + + + + + SRCADDR4 + Channel1 source address register + 0x88 + 32 + read-write + + + SRCADDR + desc SRCADDR + 31 + 0 + read-write + + + + + DSTADDR4 + Channel1 destination address register + 0x8C + 32 + read-write + + + DSTADDR + desc DSTADDR + 31 + 0 + read-write + + + + + TRIG4 + Channel1 trigger register + 0x90 + 32 + read-write + + + HARDSRC + desc HARDSRC + 7 + 2 + read-write + + + SOFTSRC + desc SOFTSRC + 1 + 1 + read-write + + + TYPE + desc TYPE + 0 + 0 + read-write + + + + + CCNT4 + Channel1 trigger register + 0x94 + 32 + read-write + + + CREPEAT + desc CREPEAT + 19 + 16 + read-write + + + CCNT + desc CCNT + 15 + 0 + read-write + + + + + CSRCADDR4 + Channel1 source address register + 0x98 + 32 + read-only + + + CSRCADDR + desc CSRCADDR + 31 + 0 + read-only + + + + + CDSTADDR4 + Channel1 destination address register + 0x9C + 32 + read-only + + + CDSTADDR + desc CDSTADDR + 31 + 0 + read-only + + + + + + + DMACHANNEL1 + DMA Channel 1 + 0x40020020 + DMA + + DMACH12 + DMA Channel 1/2 Interrupt + 9 + + DMA + DMACHANNEL + 32 + + 0x0 + 0x20 + registers + + + + CSR + Channel1 control and status register + 0x0 + 32 + read-write + + + DSTLOAD + desc DSTLOAD + 15 + 15 + read-write + + + SRCLOAD + desc SRCLOAD + 14 + 14 + read-write + + + TE + desc TE + 13 + 13 + read-only + + + TC + desc TC + 12 + 12 + read-only + + + RESTART + desc RESTART + 11 + 11 + read-write + + + STATUS + desc STATUS + 10 + 8 + read-write + + + SIZE + desc SIZE + 7 + 6 + read-write + + + DSTINC + desc DSTINC + 5 + 5 + read-write + + + SRCINC + desc SRCINC + 4 + 4 + read-write + + + TRANS + desc TRANS + 3 + 3 + read-write + + + TEIE + desc TEIE + 2 + 2 + read-write + + + TCIE + desc TCIE + 1 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + CNT + Channel1 counter register + 0x4 + 32 + read-write + + + REPEAT + desc REPEAT + 19 + 16 + read-write + + + CNT + desc CNT + 15 + 0 + read-write + + + + + SRCADDR + Channel1 source address register + 0x8 + 32 + read-write + + + SRCADDR + desc SRCADDR + 31 + 0 + read-write + + + + + DSTADDR + Channel1 destination address register + 0xC + 32 + read-write + + + DSTADDR + desc DSTADDR + 31 + 0 + read-write + + + + + TRIG + Channel1 trigger register + 0x10 + 32 + read-write + + + HARDSRC + desc HARDSRC + 7 + 2 + read-write + + + SOFTSRC + desc SOFTSRC + 1 + 1 + read-write + + + TYPE + desc TYPE + 0 + 0 + read-write + + + + + CCNT + Channel1 trigger register + 0x14 + 32 + read-write + + + CREPEAT + desc CREPEAT + 19 + 16 + read-write + + + CCNT + desc CCNT + 15 + 0 + read-write + + + + + CSRCADDR + Channel1 source address register + 0x18 + 32 + read-only + + + CSRCADDR + desc CSRCADDR + 31 + 0 + read-only + + + + + CDSTADDR + Channel1 destination address register + 0x1C + 32 + read-only + + + CDSTADDR + desc CDSTADDR + 31 + 0 + read-only + + + + + + + DMACHANNEL2 + DMA Channel 2 + 0x40020040 + DMA + + DMACH12 + DMA Channel 1/2 Interrupt + 9 + + + + DMACHANNEL3 + DMA Channel 3 + 0x40020060 + DMA + + DMACH34 + DMA Channel 3/4 Interrupt + 10 + + + + DMACHANNEL4 + DMA Channel 4 + 0x40020080 + DMA + + DMACH34 + DMA Channel 3/4 Interrupt + 10 + + + + EAU + desc EAU + 0x40023200 + EAU + 32 + + 0x0 + 0x14 + registers + + + + CSR + desc CSR + 0x0 + 32 + read-write + + + BUSY + desc BUSY + 4 + 4 + read-only + + + ZERO + desc ZERO + 3 + 3 + read-only + + + OVR + desc OVR + 2 + 2 + read-only + + + MODE + desc MODE + 1 + 0 + read-write + + + + + DIVIDEND + desc DIVIDEND + 0x4 + 32 + read-write + + + DIVIDEND + desc DIVIDEND + 31 + 0 + read-write + + + + + DIVISOR + desc DIVISOR + 0x8 + 32 + read-write + + + DIVISOR + desc DIVISOR + 31 + 0 + read-write + + + + + QUOTIENT + desc QUOTIENT + 0xC + 32 + read-only + + + QUOTIENT + desc QUOTIENT + 31 + 0 + read-only + + + + + REMAINDER + desc REMAINDER + 0x10 + 32 + read-only + + + REMAINDER + desc REMAINDER + 31 + 0 + read-only + + + + + + + FLASH + desc FLASH + 0x40022000 + + FLASHRAM + Flash/RAM Interrupt + 3 + + FLASH + 32 + + 0x0 + 0x74 + registers + + + + CR1 + Control register1 + 0x0 + 32 + read-write + + + KEY + desc KEY + 31 + 16 + write-only + + + SECURITY + desc SECURITY + 6 + 5 + read-only + + + MODE + desc MODE + 1 + 0 + read-write + + + + + CR2 + Control register2 + 0x4 + 32 + read-write + + + KEY + desc KEY + 31 + 16 + write-only + + + CACHEINVALID + desc CACHEINVALID + 5 + 5 + read-write + + + CACHE + desc CACHE + 4 + 4 + read-write + + + FETCH + desc FETCH + 3 + 3 + read-write + + + WAIT + desc WAIT + 2 + 0 + read-write + + + + + PAGELOCK + Page Write Erase Lock + 0x8 + 32 + read-write + + + KEY + desc KEY + 31 + 16 + write-only + + + LOCK15 + Page120 - 127 + 15 + 15 + read-write + + + LOCK14 + Page112 - 119 + 14 + 14 + read-write + + + LOCK13 + Page104 - 111 + 13 + 13 + read-write + + + LOCK12 + Page96 - 103 + 12 + 12 + read-write + + + LOCK11 + Page88 - 95 + 11 + 11 + read-write + + + LOCK10 + Page80 - 87 + 10 + 10 + read-write + + + LOCK9 + Page72 - 79 + 9 + 9 + read-write + + + LOCK8 + Page64 - 71 + 8 + 8 + read-write + + + LOCK7 + Page56 - 63 + 7 + 7 + read-write + + + LOCK6 + Page48 - 55 + 6 + 6 + read-write + + + LOCK5 + Page40 - 47 + 5 + 5 + read-write + + + LOCK4 + Page32 - 39 + 4 + 4 + read-write + + + LOCK3 + Page24 - 31 + 3 + 3 + read-write + + + LOCK2 + Page16 - 23 + 2 + 2 + read-write + + + LOCK1 + Page8 - 15 + 1 + 1 + read-write + + + LOCK0 + Page0 - 7 + 0 + 0 + read-write + + + + + IER + Interrupt enable register + 0x20 + 32 + read-write + + + PROG + desc PROG + 4 + 4 + read-write + + + CACHEON + desc CACHEON + 3 + 3 + read-write + + + SDKERR + desc SDKERR + 2 + 2 + read-write + + + PAGELOCK + desc PAGELOCK + 1 + 1 + read-write + + + PC + desc PC + 0 + 0 + read-write + + + + + ISR + Interrupt status register + 0x24 + 32 + read-only + + + BUSY + desc BUSY + 5 + 5 + read-only + + + PROG + desc PROG + 4 + 4 + read-only + + + CACHEON + desc CACHEON + 3 + 3 + read-only + + + SDKERR + desc SDKERR + 2 + 2 + read-only + + + PAGELOCK + desc PAGELOCK + 1 + 1 + read-only + + + PC + desc PC + 0 + 0 + read-only + + + + + ICR + Interrupt flag clear register + 0x28 + 32 + read-write + + + PROG + desc PROG + 4 + 4 + read-write + + + CACHEON + desc CACHEON + 3 + 3 + read-write + + + SDKERR + desc SDKERR + 2 + 2 + read-write + + + PAGELOCK + desc PAGELOCK + 1 + 1 + read-write + + + PC + desc PC + 0 + 0 + read-write + + + + + SDKCFR + SDK config register + 0x70 + 32 + read-only + + + END + desc END + 14 + 8 + read-only + + + START + desc START + 6 + 0 + read-only + + + + + + + GPIOA + desc GPIOA + 0x48000000 + + GPIOA + GPIOA Interrupt + 5 + + GPIO + GPIO + 32 + + 0x0 + 0x64 + registers + + + + DIR + desc DIR + 0x0 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + OPENDRAIN + desc OPENDRAIN + 0x4 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + PUR + desc PUR + 0x10 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + AFRH + desc AFRH + 0x14 + 32 + read-write + + + PIN15 + desc AFR15 + 31 + 28 + read-write + + + PIN14 + desc AFR14 + 27 + 24 + read-write + + + PIN13 + desc AFR13 + 23 + 20 + read-write + + + PIN12 + desc AFR12 + 19 + 16 + read-write + + + PIN11 + desc AFR11 + 15 + 12 + read-write + + + PIN10 + desc AFR10 + 11 + 8 + read-write + + + PIN9 + desc AFR9 + 7 + 4 + read-write + + + PIN8 + desc AFR8 + 3 + 0 + read-write + + + + + AFRL + desc AFRL + 0x18 + 32 + read-write + + + PIN7 + desc AFR7 + 31 + 28 + read-write + + + PIN6 + desc AFR6 + 27 + 24 + read-write + + + PIN5 + desc AFR5 + 23 + 20 + read-write + + + PIN4 + desc AFR4 + 19 + 16 + read-write + + + PIN3 + desc AFR3 + 15 + 12 + read-write + + + PIN2 + desc AFR2 + 11 + 8 + read-write + + + PIN1 + desc AFR1 + 7 + 4 + read-write + + + PIN0 + desc AFR0 + 3 + 0 + read-write + + + + + ANALOG + desc ANALOG + 0x1C + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + RISEIE + Interrupt enable register + 0x24 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + FALLIE + Interrupt enable register + 0x28 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + ISR + Interrupt status register + 0x34 + 32 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN9 + desc PIN9 + 9 + 9 + read-only + + + PIN8 + desc PIN8 + 8 + 8 + read-only + + + PIN7 + desc PIN7 + 7 + 7 + read-only + + + PIN6 + desc PIN6 + 6 + 6 + read-only + + + PIN5 + desc PIN5 + 5 + 5 + read-only + + + PIN4 + desc PIN4 + 4 + 4 + read-only + + + PIN3 + desc PIN3 + 3 + 3 + read-only + + + PIN2 + desc PIN2 + 2 + 2 + read-only + + + PIN1 + desc PIN1 + 1 + 1 + read-only + + + PIN0 + desc PIN0 + 0 + 0 + read-only + + + + + ICR + Interrupt flag clear register + 0x38 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + FILTER + desc FILTER + 0x40 + 32 + read-write + + + FLTCLK + desc FLTCLK + 18 + 16 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 + read-write + + + PIN11 + desc PIN11 + 11 + 11 + read-write + + + PIN10 + desc PIN10 + 10 + 10 + read-write + + + PIN9 + desc PIN9 + 9 + 9 + read-write + + + PIN8 + desc PIN8 + 8 + 8 + read-write + + + PIN7 + desc PIN7 + 7 + 7 + read-write + + + PIN6 + desc PIN6 + 6 + 6 + read-write + + + PIN5 + desc PIN5 + 5 + 5 + read-write + + + PIN4 + desc PIN4 + 4 + 4 + read-write + + + PIN3 + desc PIN3 + 3 + 3 + read-write + + + PIN2 + desc PIN2 + 2 + 2 + read-write + + + PIN1 + desc PIN1 + 1 + 1 + read-write + + + PIN0 + desc PIN0 + 0 + 0 + read-write + + + + + IDR + desc IDR + 0x50 + 32 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN9 + desc PIN9 + 9 + 9 + read-only + + + PIN8 + desc PIN8 + 8 + 8 + read-only + + + PIN7 + desc PIN7 + 7 + 7 + read-only + + + PIN6 + desc PIN6 + 6 + 6 + read-only + + + PIN5 + desc PIN5 + 5 + 5 + read-only + + + PIN4 + desc PIN4 + 4 + 4 + read-only + + + PIN3 + desc PIN3 + 3 + 3 + read-only + + + PIN2 + desc PIN2 + 2 + 2 + read-only + + + PIN1 + desc PIN1 + 1 + 1 + read-only + + + PIN0 + desc PIN0 + 0 + 0 + read-only + + + + + ODR + desc ODR + 0x54 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write + + + PIN13 + desc PIN13 + 13 + 13 + read-write + + + PIN12 + desc PIN12 + 12 + 12 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7 + 7 + read-write + + + BRR6 + desc BRR6 + 6 + 6 + read-write + + + BRR5 + desc BRR5 + 5 + 5 + read-write + + + BRR4 + desc BRR4 + 4 + 4 + read-write + + + BRR3 + desc BRR3 + 3 + 3 + read-write + + + BRR2 + desc BRR2 + 2 + 2 + read-write + + + BRR1 + desc BRR1 + 1 + 1 + read-write + + + BRR0 + desc BRR0 + 0 + 0 + read-write + + + + + BSRR + desc BSRR + 0x5C + 32 + read-write + + + BRR15 + desc BRR15 + 31 + 31 + read-write + + + BRR14 + desc BRR14 + 30 + 30 + read-write + + + BRR13 + desc BRR13 + 29 + 29 + read-write + + + BRR12 + desc BRR12 + 28 + 28 + read-write + + + BRR11 + desc BRR11 + 27 + 27 + read-write + + + BRR10 + desc BRR10 + 26 + 26 + read-write + + + BRR9 + desc BRR9 + 25 + 25 + read-write + + + BRR8 + desc BRR8 + 24 + 24 + read-write + + + BRR7 + desc BRR7 + 23 + 23 + read-write + + + BRR6 + desc BRR6 + 22 + 22 + read-write + + + BRR5 + desc BRR5 + 21 + 21 + read-write + + + BRR4 + desc BRR4 + 20 + 20 + read-write + + + BRR3 + desc BRR3 + 19 + 19 + read-write + + + BRR2 + desc BRR2 + 18 + 18 + read-write + + + BRR1 + desc BRR1 + 17 + 17 + read-write + + + BRR0 + desc BRR0 + 16 + 16 + read-write + + + BSS15 + desc BSS15 + 15 + 15 + read-write + + + BSS14 + desc BSS14 + 14 + 14 + read-write + + + BSS13 + desc BSS13 + 13 + 13 + read-write + + + BSS12 + desc BSS12 + 12 + 12 + read-write + + + BSS11 + desc BSS11 + 11 + 11 + read-write + + + BSS10 + desc BSS10 + 10 + 10 + read-write + + + BSS9 + desc BSS9 + 9 + 9 + read-write + + + BSS8 + desc BSS8 + 8 + 8 + read-write + + + BSS7 + desc BSS7 + 7 + 7 + read-write + + + BSS6 + desc BSS6 + 6 + 6 + read-write + + + BSS5 + desc BSS5 + 5 + 5 + read-write + + + BSS4 + desc BSS4 + 4 + 4 + read-write + + + BSS3 + desc BSS3 + 3 + 3 + read-write + + + BSS2 + desc BSS2 + 2 + 2 + read-write + + + BSS1 + desc BSS1 + 1 + 1 + read-write + + + BSS0 + desc BSS0 + 0 + 0 + read-write + + + + + TOG + desc TOG + 0x60 + 32 + read-write + + + PIN15 + desc PIN15 + 15 + 15 + read-write + + + PIN14 + desc PIN14 + 14 + 14 + read-write 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14 + read-write + + + ETPS + desc ETPS + 13 + 12 + read-write + + + ETF + desc ETF + 11 + 8 + read-write + + + MSM + desc MSM + 7 + 7 + read-write + + + TS + desc TS + 6 + 4 + read-write + + + OCCS + desc OCCS + 3 + 3 + read-write + + + SMS + desc SMS + 2 + 0 + read-write + + + + + IER + Interrupt control register + 0xC + 32 + read-write + + + TERRIE + desc TERRIE + 23 + 23 + read-write + + + IERRIE + desc IERRIE + 22 + 22 + read-write + + + DIRIE + desc DIRIE + 21 + 21 + read-write + + + IDXIE + desc IDXIE + 20 + 20 + read-write + + + TDE + desc TDE + 14 + 14 + read-write + + + CC4DE + desc CC4DE + 12 + 12 + read-write + + + CC3DE + desc CC3DE + 11 + 11 + read-write + + + CC2DE + desc CC2DE + 10 + 10 + read-write + + + CC1DE + desc CC1DE + 9 + 9 + read-write + + + UDE + desc UDE + 8 + 8 + read-write + + + TIE + desc TIE + 6 + 6 + read-write + + + CC4IE + desc CC4IE + 4 + 4 + read-write + + + CC3IE + desc CC3IE + 3 + 3 + read-write + + + CC2IE + desc CC2IE + 2 + 2 + read-write + + + CC1IE + desc CC1IE + 1 + 1 + read-write + + + UIE + desc UIE + 0 + 0 + read-write + + + + + ISR + Interrupt status register + 0x10 + 32 + read-only + + + TERRF + desc TERRF + 23 + 23 + read-only + + + IERRF + desc IERRF + 22 + 22 + read-only + + + DIRF + desc DIRF + 21 + 21 + read-only + + + IDXF + desc IDXF + 20 + 20 + read-only + + + CC4OF + desc CC4OF + 12 + 12 + read-only + + + CC3OF + desc CC3OF + 11 + 11 + read-only + + + CC2OF + desc CC2OF + 10 + 10 + read-only + + + CC1OF + desc CC1OF + 9 + 9 + read-only + + + TIF + desc TIF + 6 + 6 + read-only + + + CC4IF + desc CC4IF + 4 + 4 + read-only + + + CC3IF + desc CC3IF + 3 + 3 + read-only + + + CC2IF + desc CC2IF + 2 + 2 + read-only + + + CC1IF + desc CC1IF + 1 + 1 + read-only + + + UIF + desc UIF + 0 + 0 + read-only + + + + + ICR + Interrupt flag clear register + 0x70 + 32 + read-write + + + TERRF + desc TERRF + 23 + 23 + read-write + + + IERRF + desc IERRF + 22 + 22 + read-write + + + DIRF + desc DIRF + 21 + 21 + read-write + + + IDXF + desc IDXF + 20 + 20 + read-write + + + CC4OF + desc CC4OF + 12 + 12 + read-write + + + CC3OF + desc CC3OF + 11 + 11 + read-write + + + CC2OF + desc CC2OF + 10 + 10 + read-write + + + CC1OF + desc CC1OF + 9 + 9 + read-write + + + TIF + desc TIF + 6 + 6 + read-write + + + CC4IF + desc CC4IF + 4 + 4 + read-write + + + CC3IF + desc CC3IF + 3 + 3 + read-write + + + CC2IF + desc CC2IF + 2 + 2 + read-write + + + CC1IF + desc CC1IF + 1 + 1 + read-write + + + UIF + desc UIF + 0 + 0 + read-write + + + + + EGR + Event Generate register + 0x14 + 32 + read-write + + + TG + desc TG + 6 + 6 + read-write + + + CC4G + desc CC4G + 4 + 4 + read-write + + + CC3G + desc CC3G + 3 + 3 + read-write + + + CC2G + desc CC2G + 2 + 2 + read-write + + + CC1G + desc CC1G + 1 + 1 + read-write + + + UG + desc UG + 0 + 0 + read-write + + + + + CCMR1CAP + Capture control Register1 + 0x18 + 32 + read-write + + + IC2F + desc IC2F + 15 + 12 + read-write + + + IC2PSC + desc IC2PSC + 11 + 10 + read-write + + + CC2S + desc CC2S + 9 + 8 + read-write + + + IC1F + desc IC1F + 7 + 4 + read-write + + + IC1PSC + desc IC1PSC + 3 + 2 + read-write + + + CC1S + desc CC1S + 1 + 0 + read-write + + + + + CCMR1CMP + Compare control Register1 + CCMR1CAP + 0x18 + 32 + read-write + + + OC2MH + desc OC2MH + 24 + 24 + read-write + + + OC1MH + desc OC1MH + 16 + 16 + read-write + + + OC2CE + desc OC2CE + 15 + 15 + read-write + + + OC2M + desc OC2M + 14 + 12 + read-write + + + OC2PE + desc OC2PE + 11 + 11 + read-write + + + OC2FE + desc OC2FE + 10 + 10 + read-write + + + CC2S + desc CC2S + 9 + 8 + read-write + + + OC1CE + desc OC1CE + 7 + 7 + read-write + + + OC1M + desc OC1M + 6 + 4 + read-write + + + OC1PE + desc OC1PE + 3 + 3 + read-write + + + OC1FE + desc OC1FE + 2 + 2 + read-write + + + CC1S + desc CC1S + 1 + 0 + read-write + + + + + CCMR2CAP + Capture control Register2 + 0x1C + 32 + read-write + + + IC4F + desc IC4F + 15 + 12 + read-write + + + IC4PSC + desc IC4PSC + 11 + 10 + read-write + + + CC4S + desc CC4S + 9 + 8 + read-write + + + IC3F + desc IC3F + 7 + 4 + read-write + + + IC3PSC + desc IC3PSC + 3 + 2 + read-write + + + CC3S + desc CC3S + 1 + 0 + read-write + + + + + CCMR2CMP + Compare control Register2 + CCMR2CAP + 0x1C + 32 + read-write + + + OC4MH + desc OC4MH + 24 + 24 + read-write + + + OC3MH + desc OC3MH + 16 + 16 + read-write + + + OC4CE + desc OC4CE + 15 + 15 + read-write + + + OC4M + desc OC4M + 14 + 12 + read-write + + + OC4PE + desc OC4PE + 11 + 11 + read-write + + + OC4FE + desc OC4FE + 10 + 10 + read-write + + + CC4S + desc CC4S + 9 + 8 + read-write + + + OC3CE + desc OC3CE + 7 + 7 + read-write + + + OC3M + desc OC3M + 6 + 4 + read-write + + + OC3PE + desc OC3PE + 3 + 3 + read-write + + + OC3FE + desc OC3FE + 2 + 2 + read-write + + + CC3S + desc CC3S + 1 + 0 + read-write + + + + + CCER + Capture compare Enable Register + 0x20 + 32 + read-write + + + CC4NP + desc CC4NP + 15 + 15 + read-write + + + CC4P + desc CC4P + 13 + 13 + read-write + + + CC4E + desc CC4E + 12 + 12 + read-write + + + CC3NP + desc CC3NP + 11 + 11 + read-write + + + CC3P + desc CC3P + 9 + 9 + read-write + + + CC3E + desc CC3E + 8 + 8 + read-write + + + CC2NP + desc CC2NP + 7 + 7 + read-write + + + CC2P + desc CC2P + 5 + 5 + read-write + + + CC2E + desc CC2E + 4 + 4 + read-write + + + CC1NP + desc CC1NP + 3 + 3 + read-write + + + CC1P + desc CC1P + 1 + 1 + read-write + + + CC1E + desc CC1E + 0 + 0 + read-write + + + + + CNT + Counter Register + 0x24 + 32 + read-write + + + UIFCPY + desc UIFCPY + 31 + 31 + read-only + + + CNT + desc CNT + 15 + 0 + read-write + + + + + PSC + Prescaler Control Register + 0x28 + 32 + read-write + + + PSC + desc PSC + 15 + 0 + read-write + + + + + ARR + Auto Reload Register + 0x2C + 32 + read-write + + + ARR + desc ARR + 15 + 0 + read-write + + + + + CCR1 + Capture control Register1 + 0x34 + 32 + read-write + + + CCR1 + desc CCR1 + 15 + 0 + read-write + + + + + CCR2 + Capture control Register2 + 0x38 + 32 + read-write + + + CCR2 + desc CCR2 + 15 + 0 + read-write + + + + + CCR3 + Capture control Register3 + 0x3C + 32 + read-write + + + CCR3 + desc CCR3 + 15 + 0 + read-write + + + + + CCR4 + Capture control Register4 + 0x40 + 32 + read-write + + + CCR4 + desc CCR4 + 15 + 0 + read-write + + + + + ECR + Encoder control Register + 0x58 + 32 + read-write + + + IPOS + desc IPOS + 7 + 6 + read-write + + + FIDX + desc FIDX + 5 + 5 + read-write + + + IDIR + desc IDIR + 2 + 1 + read-write + + + IE + desc IE + 0 + 0 + read-write + + + + + TISEL + Timer Input Select Register + 0x5C + 32 + read-write + + + TI4SEL + desc TI4SEL + 27 + 24 + read-write + + + TI3SEL + desc TI3SEL + 19 + 16 + read-write + + + TI2SEL + desc TI2SEL + 11 + 8 + read-write + + + TI1SEL + desc TI1SEL + 3 + 0 + read-write + + + + + AF1 + Alternate function Register1 + 0x60 + 32 + read-write + + + ETRSEL + desc ETRSEL + 17 + 14 + read-write + + + + + AF2 + Alternate function Register2 + 0x64 + 32 + read-write + + + OCRSEL + desc OCRSEL + 18 + 16 + read-write + + + + + + + GTIM2 + General Timer 2 + 0x40001C00 + + GTIM2 + General Timer1 Interrupt + 17 + + + + GTIM3 + General Timer 3 + 0x40002400 + + GTIM34 + General Timer3_4 Interrupt + 18 + + + + GTIM4 + General Timer 4 + 0x40002800 + + GTIM34 + General Timer3_4 Interrupt + 18 + + + + HALLTIM + HALL Timer + 0x40006400 + + BTIM3_HALLTIM + Base Timer3 and Hall timer Interrupt + 22 + + HALLTIM + 32 + + 0x0 + 0x24 + registers + + + + CR + Control register1 + 0x0 + 32 + read-write + + + SOFTCAP + desc SOFTCAP + 23 + 23 + read-write + + + FLT2LEN + desc FLT2LEN + 22 + 8 + read-write + + + MMS + desc MMS + 6 + 4 + read-write + + + DIV + desc DIV + 3 + 2 + read-write + + + FLT1EN + desc FLT1EN + 1 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + DIER + DMA and Interrupt register2 + 0x4 + 32 + read-write + + + SOFTDMA + desc SOFTDMA + 7 + 7 + read-write + + + MATCHDMA + desc MATCHDMA + 6 + 6 + read-write + + + OVDMA + desc OVDMA + 5 + 5 + read-write + + + CAPDMA + desc CAPDMA + 4 + 4 + read-write + + + MATCHIE + desc MATCHIE + 2 + 2 + read-write + + + OVIE + desc OVIE + 1 + 1 + read-write + + + CAPIE + desc CAPIE + 0 + 0 + read-write + + + + + CNT + counter register + 0x8 + 32 + read-write + + + DATA + desc DATA + 23 + 0 + read-write + + + + + ARR + Auto Reload Register + 0xC + 32 + read-write + + + DATA + desc DATA + 23 + 0 + read-write + + + + + WIDTH + Width Register + 0x10 + 32 + read-only + + + DATA + desc DATA + 23 + 0 + read-only + + + + + CCR + Compare control Register + 0x14 + 32 + read-write + + + DATA + desc DATA + 23 + 0 + read-write + + + + + ISR + Interrupt states register + 0x18 + 32 + read-only + + + MATCH + desc MATCH + 2 + 2 + read-only + + + OV + desc OV + 1 + 1 + read-only + + + CAPF + desc CAPF + 0 + 0 + read-only + + + + + ICR + Interrupt clean register + 0x1C + 32 + read-write + + + MATCHF + desc MATCHF + 2 + 2 + read-write + + + OVF + desc OVF + 1 + 1 + read-write + + + CAPF + desc CAPF + 0 + 0 + read-write + + + + + STATE + State register + 0x20 + 32 + read-only + + + CH3S + desc CH3S + 6 + 6 + read-only + + + CH2S + desc CH2S + 5 + 5 + read-only + + + CH1S + desc CH1S + 4 + 4 + read-only + + + CH3F + desc CH3F + 2 + 2 + read-only + + + CH2F + desc CH2F + 1 + 1 + read-only + + + CH1F + desc CH1F + 0 + 0 + read-only + + + + + + + I2C1 + desc I2C1 + 0x40005800 + + I2C1 + I2C1 Interrupt + 23 + + I2C + I2C + 32 + + 0x0 + 0x174 + registers + + + + INSEL + desc INSEL + 0x08 + 32 + read-write + + + SDAINSEL + desc SDAINSEL + 5 + 3 + read-write + + + SCLINSEL + desc SCLINSEL + 2 + 0 + read-write + + + + + MCR0 + desc MCR0 + 0x10 + 32 + read-write + + + RXFIFORST + desc RXFIFORST + 9 + 9 + read-write + + + TXFIFORST + desc TXFIFORST + 8 + 8 + read-write + + + CLKSRC + desc CLKSRC + 7 + 6 + read-write + + + DBGEN + desc DBGEN + 3 + 3 + read-write + + + SLEEPEN + desc SLEEPEN + 2 + 2 + read-write + + + RESET + desc RESET + 1 + 1 + read-write + + + MEN + desc MEN + 0 + 0 + read-write + + + + + MCR1 + Master Control Register1 + 0x20 + 32 + read-write + + + RDMO + desc RDMO + 9 + 9 + read-write + + + CIRFIFO + desc CIRFIFO + 8 + 8 + read-write + + + + + MCR2 + Master Control Register2 + 0x24 + 32 + read-write + + + PINCFG + desc PINCFG + 26 + 24 + read-write + + + MATCFG + desc MATCFG + 18 + 16 + read-write + + + TRGSEL + desc TRGSEL + 15 + 15 + read-write + + + TIMECFG + desc TIMECFG + 10 + 10 + read-write + + + IGNACK + desc IGNACK + 9 + 9 + read-write + + + AUTOSTOP + desc AUTOSTOP + 8 + 8 + read-write + + + PRESCALE + desc PRESCALE + 2 + 0 + read-write + + + + + MCR3 + Master Control Register3 + 0x28 + 32 + read-write + + + FLTSDA + desc FLTSDA + 27 + 24 + read-write + + + FLTSCL + desc FLTSCL + 19 + 16 + read-write + + + BUSIDLE + desc BUSIDLE + 11 + 0 + read-write + + + + + MCR4 + Master Control Register4 + 0x2C + 32 + read-write + + + PINLOW + desc PINLOW + 19 + 8 + read-write + + + + + MCCR + Master Clock Control Register + 0x48 + 32 + read-write + + + DATAVD + desc DATAVD + 29 + 24 + read-write + + + SETHOLD + desc SETHOLD + 21 + 16 + read-write + + + CLKHI + desc CLKHI + 13 + 8 + read-write + + + CLKLO + desc CLKLO + 5 + 0 + read-write + + + + + MMATCH + Master Match Register + 0x40 + 32 + read-write + + + MATCH1 + desc MATCH1 + 23 + 16 + read-write + + + MATCH0 + desc MATCH0 + 7 + 0 + read-write + + + + + MFIFOCR + Master FIFO Control Register + 0x58 + 32 + read-write + + + RXWATER + desc RXWATER + 17 + 16 + read-write + + + TXWATER + desc TXWATER + 1 + 0 + read-write + + + + + MFIFOSR + Master FIFO Status Register + 0x5C + 32 + read-only + + + RXCNT + desc RXCNT + 17 + 16 + read-only + + + TXCNT + desc TXCNT + 1 + 0 + read-only + + + + + MTDR + Master Tx Data Register + 0x60 + 32 + write-only + + + CMD + desc CMD + 10 + 8 + write-only + + + DATA + desc DATA + 7 + 0 + write-only + + + + + MRDR + Master Rx Data Register + 0x70 + 32 + read-only + + + EMPTY + desc EMPTY + 14 + 14 + read-only + + + DATA + desc DATA + 7 + 0 + read-only + + + + + MDER + Master DMA Enable Register + 0x1C + 32 + read-write + + + RXNE + desc RXNE + 1 + 1 + read-write + + + TXE + desc TXE + 0 + 0 + read-write + + + + + MIER + Master Interrupt Enable Register + 0x18 + 32 + read-write + + + MATCH + desc MATCH + 14 + 14 + read-write + + + PINLOW + desc PINLOW + 13 + 13 + read-write + + + FIFO + desc FIFO + 12 + 12 + read-write + + + ARBI + desc ARBI + 11 + 11 + read-write + + + NACK + desc NACK + 10 + 10 + read-write + + + STOP + desc STOP + 9 + 9 + read-write + + + PACKET + desc PACKET + 8 + 8 + read-write + + + RXNE + desc RXNE + 1 + 1 + read-write + + + TXE + desc TXE + 0 + 0 + read-write + + + + + MISR + Master Interrupt Status Register + 0x14 + 32 + read-only + + + BUSBUSY + desc BUSBUSY + 25 + 25 + read-only + + + MSTBUSY + desc MSTBUSY + 24 + 24 + read-only + + + MATCH + desc MATCH + 14 + 14 + read-only + + + PINLOW + desc PINLOW + 13 + 13 + read-only + + + FIFO + desc FIFO + 12 + 12 + read-only + + + ARBI + desc ARBI + 11 + 11 + read-only + + + NACK + desc NACK + 10 + 10 + read-only + + + STOP + desc STOP + 9 + 9 + read-only + + + PACKET + desc PACKET + 8 + 8 + read-only + + + RXNE + desc RXNE + 1 + 1 + read-only + + + TXE + desc TXE + 0 + 0 + read-only + + + + + MICR + Master Interrupt Flag Clear Register + 0xC + 32 + read-write + + + MATCH + desc MATCH + 14 + 14 + read-write + + + PINLOW + desc PINLOW + 13 + 13 + read-write + + + FIFO + desc FIFO + 12 + 12 + read-write + + + ARBI + desc ARBI + 11 + 11 + read-write + + + NACK + desc NACK + 10 + 10 + read-write + + + STOP + desc STOP + 9 + 9 + read-write + + + PACKET + desc PACKET + 8 + 8 + read-write + + + + + SCR0 + Slave Control Register0 + 0x110 + 32 + read-write + + + RXFIFORST + desc RXFIFORST + 9 + 9 + read-write + + + TXFIFORST + desc TXFIFORST + 8 + 8 + read-write + + + CLKSRC + desc CLKSRC + 7 + 6 + read-write + + + FLTEN + desc FLTEN + 4 + 4 + read-write + + + RESET + desc RESET + 1 + 1 + read-write + + + SEN + desc SEN + 0 + 0 + read-write + + + + + SCR1 + desc SCR1 + 0x124 + 32 + read-write + + + ADDRCFG + desc ADDRCFG + 18 + 16 + read-write + + + TRGSEL + desc TRGSEL + 15 + 15 + read-write + + + IGNACK + desc IGNACK + 12 + 12 + read-write + + + RXCFG + desc RXCFG + 11 + 11 + read-write + + + TXCFG + desc TXCFG + 10 + 10 + read-write + + + ALERTEN + desc ALERTEN + 9 + 9 + read-write + + + GCEN + desc GCEN + 8 + 8 + read-write + + + ACKSTALL + desc ACKSTALL + 3 + 3 + read-write + + + TXSTALL + desc TXSTALL + 2 + 2 + read-write + + + RXSTALL + desc RXSTALL + 1 + 1 + read-write + + + ADRSTALL + desc ADRSTALL + 0 + 0 + read-write + + + + + SCR2 + desc SCR2 + MCR2 + 0x24 + 32 + read-write + + + PINCFG + desc PINCFG + 26 + 24 + read-write + + + + + SCR3 + desc SCR3 + 0x128 + 32 + read-write + + + FLTSDA + desc FLTSDA + 27 + 24 + read-write + + + FLTSCL + desc FLTSCL + 19 + 16 + read-write + + + DATAVD + desc DATAVD + 13 + 8 + read-write + + + CLKHOLD + desc CLKHOLD + 3 + 0 + read-write + + + + + SAMR + desc SAMR + 0x140 + 32 + read-write + + + ADDR1 + desc ADDR1 + 26 + 17 + read-write + + + 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0 + 0 + read-only + + + + + SICR + desc SICR + 0x10C + 32 + read-write + + + FIFO + desc FIFO + 11 + 11 + read-write + + + BIT + desc BIT + 10 + 10 + read-write + + + STOP + desc STOP + 9 + 9 + read-write + + + RESTART + desc RESTART + 8 + 8 + read-write + + + + + + + I2C2 + desc I2C2 + 0x40005C00 + + I2C2 + I2C2 Interrupt + 24 + + + + IRMOD + desc IRMOD + 0x40004080 + IRMOD + 32 + + 0x0 + 0xC + registers + + + + CR + Input selection register + 0x0 + 32 + read-write + + + INV + desc INV + 5 + 5 + read-write + + + IRSW + desc IRSW + 4 + 4 + read-write + + + MOD + desc MOD + 3 + 0 + read-write + + + + + + + IWDT + desc IWDT + 0x40005000 + + WDT + Watch Dog Timer Interrupt + 0 + + WDT + IWDT + 32 + + 0x0 + 0x28 + registers + + + + KR + Key register + 0x0 + 32 + write-only + + + KR + desc KR + 15 + 0 + write-only + + + + + CR + Control register + 0x4 + 32 + read-write + + + PAUSE + desc PAUSE + 5 + 5 + read-write + + + IE + desc IE + 4 + 4 + read-write + + + ACTION + desc ACTION + 3 + 3 + read-write + + + PRS + desc PRS + 2 + 0 + read-write + + + + + ARR + Auto reload register + 0x8 + 32 + read-write + + + ARR + desc ARR + 11 + 0 + read-write + + + + + CNT + counter + 0x24 + 32 + read-only + + + CNT + desc CNT + 11 + 0 + read-only + + + + + WINR + Window register + 0x10 + 32 + read-write + + + WINR + desc WINR + 11 + 0 + read-write + + + + + SR + Status register + 0xC + 32 + read-write + + + RELOAD + desc RELOAD + 5 + 5 + read-only + + + RUN + desc RUN + 4 + 4 + read-only + + + OV + desc OV + 3 + 3 + read-write + + + WINRF + desc WINRF + 2 + 2 + read-only + + + ARRF + desc ARRF + 1 + 1 + read-only + + + CRF + desc CRF + 0 + 0 + read-only + + + + + + + LPTIM + desc LPTIM + 0x40006000 + + LPTIM + LPTIM Interrupt + 19 + + LPTIM + 32 + + 0x0 + 0x24 + registers + + + + + CFGR + desc CFGR + 0x0C + 32 + read-write + + + ICLKSRC + desc ICLKSRC + 26 + 25 + read-write + + + ENC + desc ENC + 24 + 24 + read-write + + + COUNTMD + desc COUNTMD + 23 + 23 + read-write + + + PRELOAD + desc PRELOAD + 22 + 22 + read-write + + + WAVPOL + desc WAVPOL + 21 + 21 + read-write + + + WAVE + desc WAVE + 20 + 20 + read-write + + + TIMOUT + desc TIMOUT + 19 + 19 + read-write + + + TRIGEN + desc TRIGEN + 18 + 17 + read-write + + + TRIGSEL + desc TRIGSEL + 15 + 12 + read-write + + + PRS + desc PRS + 11 + 9 + read-write + + + TRIGFLT + desc TRIGFLT + 7 + 6 + read-write + + + CHFLT + desc CHFLT + 4 + 3 + read-write + + + ENCMD_CKPOL + desc ENCMD_CKPOL + 2 + 1 + read-write + + + CKSEL + desc CKSEL + 0 + 0 + read-write + + + + + CR0 + desc CR0 + 0x10 + 32 + read-write + + + ARST + desc ARST + 4 + 4 + read-write + + + SRST + desc SRST + 3 + 3 + read-write + + + CNTSTART + desc CNTSTART + 2 + 2 + read-write + + + SNGSTART + desc SNGSTART + 1 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + ARR + desc ARR + 0x18 + 32 + read-write + + + ARR + desc ARR + 15 + 0 + read-write + + + + + CNT + desc CNT + 0x1C + 32 + read-only + + + CNT + desc CNT + 15 + 0 + read-only + + + + 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ARROK + 4 + 4 + read-write + + + CMPOK + desc CMPOK + 3 + 3 + read-write + + + EXTTRIG + desc EXTTRIG + 2 + 2 + read-write + + + ARRM + desc ARRM + 1 + 1 + read-write + + + CMPM + desc CMPM + 0 + 0 + read-write + + + + + CR1 + desc CR1 + 0x20 + 32 + read-write + + + CH2SRC + desc CH2SRC + 5 + 3 + read-write + + + CH1SRC + desc CH1SRC + 2 + 0 + read-write + + + + + + + UART1 + desc UART1 + 0x40000C00 + + UART1 + UART1 Interrupt + 27 + + UART + UART + 32 + + 0x0 + 0x40 + registers + + + + CR1 + Control register1 + 0x0 + 32 + read-write + + + SYNC + desc SYNC + 14 + 14 + read-write + + + SOURCE + desc SOURCE + 13 + 12 + read-write + + + SIGNAL + desc SIGNAL + 11 + 11 + read-write + + + OVER + desc OVER + 10 + 9 + read-write + + + START + desc START + 8 + 8 + read-write + + + MSBF + desc MSBF + 7 + 7 + read-write + + + CHLEN + desc CHLEN + 6 + 6 + read-write + + + STOP + desc STOP + 5 + 4 + read-write + + + PARITYEN + desc PARITYEN + 3 + 3 + read-write + + + PARITY + desc PARITY + 2 + 2 + read-write + + + RXEN + desc RXEN + 1 + 1 + read-write + + + TXEN + desc TXEN + 0 + 0 + read-write + + + + + CR2 + Control register2 + 0x4 + 32 + read-write + + + RXSRC + desc RXSRC + 17 + 15 + read-write + + + LOOP + desc LOOP + 14 + 14 + read-write + + + ADCTX + desc ADCTX + 13 + 13 + read-write + + + + ADCRX + desc ADCRX + 12 + 12 + read-write + + + + SWAP + desc SWAP + 11 + 11 + read-write + + + TIMCR + desc TIMCR + 10 + 8 + read-write + + + DMATX + desc DMATX + 7 + 7 + read-write + + + DMARX + desc DMARX + 6 + 6 + read-write + + + TXINV + desc TXINV + 5 + 5 + read-write + + + RXINV + desc RXINV + 4 + 4 + read-write + + + RTSEN + desc RTSEN + 3 + 3 + read-write + + + CTSEN + desc CTSEN + 2 + 2 + read-write + + + RXMATCHEN + desc RXMATCHEN + 1 + 1 + read-write + + + ADDREN + desc ADDREN + 0 + 0 + read-write + + + + + CR3 + Control register3 + 0x38 + 32 + read-write + + + BRKL + desc BRKL + 8 + 8 + read-write + + + LIN + desc LIN + 7 + 7 + read-write + + + DETIME + desc DETIME + 6 + 2 + read-write + + + DEP + desc DEP + 1 + 1 + read-write + + + DEM + desc DEM + 0 + 0 + read-write + + + + + BRRI + desc BRRI + 0xC + 32 + read-write + + + BRRI + desc BRRI + 15 + 0 + read-write + + + + + BRRF + desc BRRF + 0x10 + 32 + read-write + + + BRRF + desc BRRF + 3 + 0 + read-write + + + + + TIMARR + desc TIMARR + 0x14 + 32 + read-write + + + TIMARR + desc TIMARR + 23 + 0 + read-write + + + + + TIMCNT + desc TIMCNT + 0x18 + 32 + read-only + + + TIMCNT + desc TIMCNT + 23 + 0 + read-only + + + + + TDR + Data reg for write + 0x28 + 32 + write-only + + + BREAK + desc BREAK + 10 + 10 + write-only + + + IDLE + desc IDLE + 9 + 9 + write-only + + + TDR + desc TDR + 8 + 0 + write-only + + + + + RDR + Data reg for read + 0x24 + 32 + read-only + + + RDR + desc RDR + 8 + 0 + read-only + + + + + IER + Interrupt enable register + 0x8 + 32 + read-write + + + RXMATCH + desc RXMATCH + 12 + 12 + read-write + + + ORE + desc ORE + 11 + 11 + read-write + + + NE + desc NE + 10 + 10 + read-write + + + PE + desc PE + 9 + 9 + read-write + + + FE + desc FE + 8 + 8 + read-write + + + CTS + desc CTS + 7 + 7 + read-write + + + TIMOV + desc TIMOV + 6 + 6 + read-write + + + BAUD + desc BAUD + 5 + 5 + read-write + + + RXBRK + desc RXBRK + 4 + 4 + read-write + + + RXIDLE + desc RXIDLE + 3 + 3 + read-write + + + RC + desc RC + 2 + 2 + read-write + + + TC + desc TC + 1 + 1 + read-write + + + TXE + desc TXE + 0 + 0 + read-write + + + + + ISR + Interrupt status register + 0x1C + 32 + read-only + + + CTSLV + desc CTSLV + 15 + 15 + read-only + + + TXBUSY + desc TXBUSY + 14 + 14 + read-only + + + SLVMATCH + desc SLVMATCH + 13 + 13 + read-only + + + RXMATCH + desc RXMATCH + 12 + 12 + read-only + + + ORE + desc ORE + 11 + 11 + read-only + + + NE + desc NE + 10 + 10 + read-only + + + PE + desc PE + 9 + 9 + read-only + + + FE + desc FE + 8 + 8 + read-only + + + CTS + desc CTS + 7 + 7 + read-only + + + TIMOV + desc TIMOV + 6 + 6 + read-only + + + BAUD + desc BAUD + 5 + 5 + read-only + + + RXBRK + desc RXBRK + 4 + 4 + read-only + + + RXIDLE + desc RXIDLE + 3 + 3 + read-only + + + RC + desc RC + 2 + 2 + read-only + + + TC + desc TC + 1 + 1 + read-only + + + TXE + desc TXE + 0 + 0 + read-only + + + + + ICR + Interrupt flag clear register + 0x20 + 32 + read-write + + + RXMATCH + desc RXMATCH + 12 + 12 + read-write + + + ORE + desc ORE + 11 + 11 + read-write + + + NE + desc NE + 10 + 10 + read-write + + + PE + desc PE + 9 + 9 + read-write + + + FE + desc FE + 8 + 8 + read-write + + + CTS + desc CTS + 7 + 7 + read-write + + + TIMOV + desc TIMOV + 6 + 6 + read-write + + + BAUD + desc BAUD + 5 + 5 + read-write + + + RXBRK + desc RXBRK + 4 + 4 + read-write + + + RXIDLE + desc RXIDLE + 3 + 3 + read-write + + + RC + desc RC + 2 + 2 + read-write + + + TC + desc TC + 1 + 1 + read-write + + + + + ADDR + Slave addr + 0x30 + 32 + read-write + + + ADDR + desc ADDR + 7 + 0 + read-write + + + + + MASK + Slave addr mask + 0x34 + 32 + read-write + + + MASK + desc MASK + 7 + 0 + read-write + + + + + RXMATCH + desc RXMATCH + 0x3C + 32 + read-write + + + RXMATCH + desc RXMATCH + 8 + 0 + read-write + + + + + + + UART2 + desc UART2 + 0x40001000 + + UART2 + UART2 Interrupt + 28 + + + + UART3 + desc UART3 + 0x40002000 + + UART3 + UART3 Interrupt + 29 + + + + LVD + desc LVD + 0x400000A4 + + LVD + Low Voltage Detect Interrupt + 1 + + LVD + 32 + + 0x0 + 0xC + registers + + + + CR0 + Control register0 + 0x0 + 32 + read-write + + + FLTCLK + desc FLTCLK + 8 + 8 + read-write + + + VTH + desc VTH + 6 + 4 + read-write + + + SOURCE + desc SOURCE + 2 + 2 + read-write + + + ACTION + desc ACTION + 1 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + CR1 + Control register1 + 0x4 + 32 + read-write + + + FLTTIME + desc FLTTIME + 7 + 4 + read-write + + + FALL + desc FALL + 3 + 3 + read-write + + + RISE + desc RISE + 2 + 2 + read-write + + + LEVEL + desc LEVEL + 1 + 1 + read-write + + + IE + desc IE + 0 + 0 + read-write + + + + + SR + status register + 0x8 + 32 + read-write + + + FLTV + desc FLTV + 1 + 1 + read-only + + + INTF + desc INTF + 0 + 0 + read-write + + + + + + + OPA1 + desc OPA1 + 0x400000B0 + OPA + OPA + 32 + + 0x0 + 0x8 + registers + + + + CR + desc CR + 0x00 + 32 + read-write + + + BIAS + desc BIAS + 15 + 13 + read-write + + + AMP + desc AMP + 12 + 10 + read-write + + + INN2EN + desc INN2EN + 9 + 9 + read-write + + + INN1EN + desc INN1EN + 8 + 8 + read-write + + + INP4EN + desc INP4EN + 7 + 7 + read-write + + + INP3EN + desc INP3EN + 6 + 6 + read-write + + + INP2EN + desc INP2EN + 5 + 5 + read-write + + + INP1EN + desc INP1EN + 4 + 4 + read-write + + + MODE + desc MODE + 2 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + CAL + desc CAL + 0x04 + 32 + read-write + + + GTIM4OC2 + desc GTIM4OC2 + 31 + 31 + read-write + + + GTIM4OC1 + desc GTIM4OC1 + 30 + 30 + read-write + + + GTIM4TRGO + desc GTIM4TRGO + 29 + 29 + read-write + + + GTIM3OC2 + desc GTIM3OC2 + 28 + 28 + read-write + + + GTIM3OC1 + desc GTIM3OC1 + 27 + 27 + read-write + + + GTIM3TRGO + desc GTIM3TRGO + 26 + 26 + read-write + + + GTIM2OC2 + desc GTIM2OC2 + 25 + 25 + read-write + + + GTIM2OC1 + desc GTIM2OC1 + 24 + 24 + read-write + + + GTIM2TRGO + desc GTIM2TRGO + 23 + 23 + read-write + + + GTIM1OC2 + desc GTIM1OC2 + 22 + 22 + read-write + + + GTIM1OC1 + desc GTIM1OC1 + 21 + 21 + read-write + + + GTIM1TRGO + desc GTIM1TRGO + 20 + 20 + read-write + + + ATIM1OC6 + desc ATIM1OC6 + 19 + 19 + read-write + + + ATIM1OC5 + desc ATIM1OC5 + 18 + 18 + read-write + + + ATIM1OC4 + desc ATIM1OC4 + 17 + 17 + read-write + + + ATIM1TRGO + desc ATIM1TRGO + 16 + 16 + read-write + + + ADC2START1 + desc ADC2START1 + 15 + 15 + read-write + + + ADC1START1 + desc ADC1START1 + 14 + 14 + read-write + + + CLKDIV + desc CLKDIV + 13 + 11 + read-write + + + AZRUN + desc AZRUN + 10 + 10 + read-only + + + ADCSTART + desc ADCSTART + 8 + 8 + read-write + + + CALPERIOD + desc CALPERIOD + 7 + 4 + read-write + + + SOFTTRIG + desc SOFTTRIG + 3 + 3 + read-write + + + START + desc START + 2 + 2 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desc YEAR + 23 + 16 + read-write + + + MONTH + desc MONTH + 12 + 8 + read-write + + + DAY + desc DAY + 5 + 0 + read-write + + + + + TIME + desc TIME + 0x18 + 32 + read-write + + + HOUR + desc HOUR + 21 + 16 + read-write + + + MINUTE + desc MINUTE + 14 + 8 + read-write + + + SECOND + desc SECOND + 6 + 0 + read-write + + + + + SSCNT + desc SSCNT + 0x44 + 32 + read-only + + + SSCNT1 + desc SSCNT1 + 20 + 20 + read-only + + + SSCNT0 + desc SSCNT0 + 19 + 0 + read-only + + + + + ALARMA + desc ALARMA + 0x1C + 32 + read-write + + + WEEKMASK + desc WEEKMASK + 30 + 24 + read-write + + + HOUREN + desc HOUREN + 23 + 23 + read-write + + + HOUR + desc HOUR + 21 + 16 + read-write + + + MINUTEEN + desc MINUTEEN + 15 + 15 + read-write + + + MINUTE + desc MINUTE + 14 + 8 + read-write + + + SECONDEN + desc SECONDEN + 7 + 7 + read-write + + + SECOND + desc SECOND + 6 + 0 + read-write + + + + + ALARMB + desc ALARMB + 0x20 + 32 + read-write + + + WEEKMASK + desc WEEKMASK + 30 + 24 + read-write + + + HOUREN + desc HOUREN + 23 + 23 + read-write + + + HOUR + desc HOUR + 21 + 16 + read-write + + + MINUTEEN + desc MINUTEEN + 15 + 15 + read-write + + + MINUTE + desc MINUTE + 14 + 8 + read-write + + + SECONDEN + desc SECONDEN + 7 + 7 + read-write + + + SECOND + desc SECOND + 6 + 0 + read-write + + + + + TAMPDATE + desc TAMPDATE + 0x24 + 32 + read-only + + + WEEK + desc WEEK + 15 + 13 + read-only + + + MONTH + desc MONTH + 12 + 8 + read-only + + + DAY + desc DAY + 5 + 0 + read-only + + + + + TAMPTIME + desc TAMPTIME + 0x28 + 32 + read-only + + + HOUR + desc HOUR + 21 + 16 + read-only + + + MINUTE + desc MINUTE + 14 + 8 + read-only + + + SECOND + desc SECOND + 6 + 0 + read-only + + + + + IER + desc IER + 0x30 + 32 + read-write + + + INTERVAL + desc INTERVAL + 6 + 6 + read-write + + + TAMPOV + desc TAMPOV + 4 + 4 + read-write + + + TAMP + desc TAMP + 3 + 3 + read-write + + + AWTIMER + desc AWTIMER + 2 + 2 + read-write + + + ALARMB + desc ALARMB + 1 + 1 + read-write + + + ALARMA + desc ALARMA + 0 + 0 + read-write + + + + + ISR + desc ISR + 0x34 + 32 + read-only + + + INTERVAL + desc INTERVAL + 6 + 6 + read-only + + + TAMPOV + desc TAMPOV + 4 + 4 + read-only + + + TAMP + desc TAMP + 3 + 3 + read-only + + + AWTIMER + desc AWTIMER + 2 + 2 + read-only + + + ALARMB + desc ALARMB + 1 + 1 + read-only + + + ALARMA + desc ALARMA + 0 + 0 + read-only + + + + + ICR + desc ICR + 0x38 + 32 + read-write + + + INTERVAL + desc INTERVAL + 6 + 6 + read-write + + + TAMPOV + desc TAMPOV + 4 + 4 + read-write + + + TAMP + desc TAMP + 3 + 3 + read-write + + + AWTIMER + desc AWTIMER + 2 + 2 + read-write + + + ALARMB + desc ALARMB + 1 + 1 + read-write + + + ALARMA + desc ALARMA + 0 + 0 + read-write + + + + + AWTARR + desc AWTARR + 0x2C + 32 + read-write + + + ARR + desc ARR + 15 + 0 + read-write + + + + + AWTCNT + desc AWTCNT + 0x3C + 32 + read-only + + + CNT + desc CNT + 15 + 0 + read-only + + + + + COMPCFR1 + desc COMPCFR1 + 0x10 + 32 + read-write + + + EN + desc EN + 15 + 15 + read-write + + + SIGN + desc SIGN + 14 + 14 + read-write + + + PERIOD + desc PERIOD + 13 + 12 + read-write + + + COMP + desc COMP + 11 + 0 + read-write + + + + + + + SPI1 + desc SPI1 + 0x40000800 + + SPI1 + SPI1 Interrupt + 25 + + SPI + SPI + 32 + + 0x0 + 0x20 + registers + + + + CR1 + Control register1 + 0x0 + 32 + read-write + + + BR + desc BR + 30 + 24 + read-write + + + SMP + desc SMP + 20 + 20 + read-write + + + MISOHD + desc MISOHD + 19 + 19 + read-write + + + FLTEN + desc FLTEN + 18 + 18 + read-write + + + MODE + desc MODE + 17 + 16 + read-write + + + GAP + desc GAP + 15 + 12 + read-write + + + WIDTH + desc WIDTH + 11 + 8 + read-write + + + LSBF + desc LSBF + 7 + 7 + read-write + + + CPOL + desc CPOL + 3 + 3 + read-write + + + CPHA + desc CPHA + 2 + 2 + read-write + + + SSM + desc SSM + 1 + 1 + read-write + + + MSTR + desc MSTR + 0 + 0 + read-write + + + + + CR2 + Control register2 + 0x4 + 32 + read-write + + + DMATX + desc DMATX + 2 + 2 + read-write + + + DMARX + desc DMARX + 1 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + CR3 + desc CR3 + 0x8 + 32 + read-write + + + HDOE + desc HDOE + 0 + 0 + read-write + + + + + SSI + Slave slect register + 0xC + 32 + read-write + + + SSI + desc SSI + 0 + 0 + read-write + + + + + IER + Interrupt enable register + 0x10 + 32 + read-write + + + MODF + desc MODF + 7 + 7 + read-write + + + SSERR + desc SSERR + 6 + 6 + read-write + + + OV + desc OV + 5 + 5 + read-write + + + UD + desc UD + 4 + 4 + read-write + + + SSR + desc SSR + 3 + 3 + read-write + + + SSF + desc SSF + 2 + 2 + read-write + + + RXNE + desc RXNE + 1 + 1 + read-write + + + TXE + desc TXE + 0 + 0 + read-write + + + + + ISR + Interrupt status register + 0x14 + 32 + read-only + + + SSLVL + desc SSLVL + 9 + 9 + read-only + + + BUSY + desc BUSY + 8 + 8 + read-only + + + MODF + desc MODF + 7 + 7 + read-only + + + SSERR + desc SSERR + 6 + 6 + read-only + + + OV + desc OV + 5 + 5 + read-only + + + UD + desc UD + 4 + 4 + read-only + + + SSR + desc SSR + 3 + 3 + read-only + + + SSF + desc SSF + 2 + 2 + read-only + + + RXNE + desc RXNE + 1 + 1 + read-only + + + TXE + desc TXE + 0 + 0 + read-only + + + + + ICR + Interrupt flag clear register + 0x18 + 32 + read-write + + + MODF + desc MODF + 7 + 7 + read-write + + + SSERR + desc SSERR + 6 + 6 + read-write + + + OV + desc OV + 5 + 5 + read-write + + + UD + desc UD + 4 + 4 + read-write + + + SSR + desc SSR + 3 + 3 + read-write + + + SSF + desc SSF + 2 + 2 + read-write + + + RXNE + desc RXNE + 1 + 1 + read-write + + + FLUSH + desc FLUSH + 0 + 0 + read-write + + + + + DR + Data register + 0x1C + 32 + read-write + + + DR + desc DR + 15 + 0 + read-write + + + + + + + SPI2 + desc SPI2 + 0x40000400 + + SPI23 + SPI23 Interrupt + 26 + + + + SPI3 + desc SPI3 + 0x40003400 + + SPI23 + SPI23 Interrupt + 26 + + + + SYSCTRL + System Ctrl + 0x40004000 + + SYSCTRL + SYSCTRL Interupt + 4 + + SYSCTRL + 32 + + 0x0 + 0x74 + registers + + + + CR0 + Control Reg0 + 0x0 + 32 + read-write + + + KEY + desc KEY + 31 + 16 + write-only + + + HCLKPRS + desc HCLKPRS + 7 + 5 + read-write + + + PCLKPRS + desc PCLKPRS + 4 + 3 + read-write + + + SYSCLK + desc SYSCLK + 2 + 0 + read-write + + + + + CR1 + Control Reg1 + 0x4 + 32 + read-write + + + KEY + desc KEY + 31 + 16 + write-only + + + CLKCCS + desc CLKCCS + 8 + 8 + read-write + + + HSECCS + desc HSECCS + 7 + 7 + read-write + + + LSECCS + desc LSECCS + 6 + 6 + read-write + + + LSELOCK + desc LSELOCK + 5 + 5 + read-write + + + LSEEN + desc LSEEN + 4 + 4 + read-write + + + LSIEN + desc LSIEN + 3 + 3 + read-write + + + PLLEN + desc PLLEN + 2 + 2 + read-write + + + HSEEN + desc HSEEN + 1 + 1 + read-write + + + HSIEN + desc HSIEN + 0 + 0 + read-write + + + + + CR2 + Control Reg2 + 0x8 + 32 + read-write + + + KEY + desc KEY + 31 + 16 + write-only + + + RAMBRKEN + desc RAMBRKEN + 15 + 15 + read-write + + + LVDBRKEN + desc LVDBRKEN + 14 + 14 + read-write + + + DSBRKEN + desc DSBRKEN + 13 + 13 + read-write + + + CLLBRKEN + desc CLLBRKEN + 12 + 12 + read-write + + + LSEBRKEN + desc LSEBRKEN + 11 + 11 + read-write + + + HSEBRKEN + desc HSEBRKEN + 10 + 10 + read-write + + + FLASHWAIT + desc FLASHWAIT + 6 + 4 + read-write + + + WAKEUPCLK + desc WAKEUPCLK + 3 + 3 + read-write + + + LOCKUP + desc LOCKUP + 2 + 2 + read-write + + + SWDIO + desc SWDIO + 1 + 1 + read-write + + + + + HSI + HSI Control Reg + 0x18 + 32 + read-write + + + STABLE + desc STABLE + 15 + 15 + read-only + + + DIV + desc DIV + 14 + 11 + read-write + + + TRIM + desc TRIM + 10 + 0 + read-write + + + + + LSI + LSI Control Reg + 0x20 + 32 + read-write + + + STABLE + desc STABLE + 15 + 15 + read-only + + + WAITCYCLE + desc WAITCYCLE + 11 + 10 + read-write + + + TRIM + desc TRIM + 8 + 0 + read-write + + + + + HSE + desc HSE + 0x1C + 32 + read-write + + + DIGFLT + desc DIGFLT + 24 + 24 + read-write + + + PDRIVER + desc PDRIVER + 23 + 20 + read-write + + + STABLE + desc STABLE + 19 + 19 + read-only + + + DETCNT + desc DETCNT + 18 + 8 + read-write + + + HEXENPOL + desc HEXENPOL + 7 + 7 + read-write + + + MODE + desc MODE + 6 + 6 + read-write + + + WAITCYCLE + desc WAITCYCLE + 5 + 4 + read-write + + + DRIVER + desc DRIVER + 3 + 0 + read-write + + + + + LSE + LSE Control Reg + 0x24 + 32 + read-write + + + STABLE + desc STABLE + 18 + 18 + read-only + + + PINLOCK + desc PINLOCK + 17 + 17 + read-write + + + PDRIVER + desc PDRIVER + 11 + 8 + read-write + + + MODE + desc MODE + 6 + 6 + read-write + + + WAITCYCLE + desc WAITCYCLE + 5 + 4 + read-write + + + DRIVER + desc DRIVER + 3 + 0 + read-write + + + + + IER + Interupt Enable Reg + 0xC + 32 + read-write + + + KEY + desc KEY + 31 + 16 + write-only + + + HSEFAULT + desc HSEFAULT + 8 + 8 + read-write + + + LSEFAULT + desc LSEFAULT + 7 + 7 + read-write + + + HSEFAIL + desc HSEFAIL + 6 + 6 + read-write + + + LSEFAIL + desc LSEFAIL + 5 + 5 + read-write + + + LSERDY + desc LSERDY + 4 + 4 + read-write + + + LSIRDY + desc LSIRDY + 3 + 3 + read-write + + + PLLRDY + desc PLLRDY + 2 + 2 + read-write + + + HSERDY + desc HSERDY + 1 + 1 + read-write + + + HSIRDY + desc HSIRDY + 0 + 0 + read-write + + + + + ISR + Interupt Status Reg + 0x10 + 32 + read-only + + + LSESTABLE + desc LSESTABLE + 15 + 15 + read-only + + + LSISTABLE + desc LSISTABLE + 14 + 14 + read-only + + + PLLSTABLE + desc PLLSTABLE + 13 + 13 + read-only + + + HSESTABLE + desc HSESTABLE + 12 + 12 + read-only + + + HSISTABLE + desc HSISTABLE + 11 + 11 + read-only + + + HSEFAULT + desc HSEFAULT + 8 + 8 + read-only + + + LSEFAULT + desc LSEFAULT + 7 + 7 + read-only + + + HSEFAIL + desc HSEFAIL + 6 + 6 + read-only + + + LSEFAIL + desc LSEFAIL + 5 + 5 + read-only + + + LSERDY + desc LSERDY + 4 + 4 + read-only + + + LSIRDY + desc LSIRDY + 3 + 3 + read-only + + + PLLRDY + desc PLLRDY + 2 + 2 + read-only + + + HSERDY + desc HSERDY + 1 + 1 + read-only + + + HSIRDY + desc HSIRDY + 0 + 0 + read-only + + + + + ICR + Interupt Clear Reg + 0x14 + 32 + read-write + + + HSEFAULT + desc HSEFAULT + 8 + 8 + read-write + + + LSEFAULT + desc LSEFAULT + 7 + 7 + read-write + + + HSEFAIL + desc HSEFAIL + 6 + 6 + read-write + + + LSEFAIL + desc LSEFAIL + 5 + 5 + read-write + + + LSERDY + desc LSERDY + 4 + 4 + read-write + + + LSIRDY + desc LSIRDY + 3 + 3 + read-write + + + PLLRDY + desc PLLRDY + 2 + 2 + read-write + + + HSERDY + desc HSERDY + 1 + 1 + read-write + + + HSIRDY + desc HSIRDY + 0 + 0 + read-write + + + + + AHBEN + AHB Clock Control Reg + 0x30 + 32 + read-write + + + KEY + desc KEY + 31 + 16 + write-only + + + CORDIC + desc CORDIC + 8 + 8 + read-write + + + GPIOF + desc GPIOF + 7 + 7 + read-write + + + GPIOC + desc GPIOC + 6 + 6 + read-write + + + GPIOB + desc GPIOB + 5 + 5 + read-write + + + GPIOA + desc GPIOA + 4 + 4 + read-write + + + EAU + desc EAU + 3 + 3 + read-write + + + CRC + desc CRC + 2 + 2 + read-write + + + FLASH + desc FLASH + 1 + 1 + read-write + + + DMA + desc DMA + 0 + 0 + read-write + + + + + APBEN1 + APB Clock Control Reg1 + 0x38 + 32 + read-write + + + KEY + desc KEY + 31 + 16 + write-only + + + SPI3 + desc SPI3 + 14 + 14 + read-write + + + SPI2 + desc SPI2 + 13 + 13 + read-write + + + GTIM4 + desc GTIM4 + 12 + 12 + read-write + + + GTIM3 + desc GTIM3 + 11 + 11 + read-write + + + UART3 + desc UART3 + 8 + 8 + read-write + + + GTIM2 + desc GTIM2 + 7 + 7 + read-write + + + GTIM1 + desc GTIM1 + 6 + 6 + read-write + + + ATIM + desc ATIM + 5 + 5 + read-write + + + UART2 + desc UART2 + 4 + 4 + read-write + + + UART1 + desc UART1 + 3 + 3 + read-write + + + SPI1 + desc SPI1 + 2 + 2 + read-write + + + VC + desc VC + 1 + 1 + read-write + + + ADC + desc ADC + 0 + 0 + read-write + + + + + APBEN2 + APB Clock Control Reg2 + 0x34 + 32 + read-write + + + KEY + desc KEY + 31 + 16 + write-only + + + HALLTIM + desc HALLTIM + 12 + 12 + read-write + + + I2C2 + desc I2C2 + 11 + 11 + read-write + + + DAC + desc DAC + 10 + 10 + read-write + + + OPA + desc OPA + 9 + 9 + read-write + + + LPTIM + desc LPTIM + 7 + 7 + read-write + + + I2C1 + desc I2C1 + 6 + 6 + read-write + + + WWDT + desc WWDT + 5 + 5 + read-write + + + IWDT + desc IWDT + 4 + 4 + read-write + + + BTIM123 + desc BTIM123 + 2 + 2 + read-write + + + RTC + desc RTC + 1 + 1 + read-write + + + + + AHBRST + AHB Reset Control Reg + 0x40 + 32 + read-write + + + CORDIC + desc CORDIC + 8 + 8 + read-write + + + GPIOF + desc GPIOF + 7 + 7 + read-write + + + GPIOC + desc GPIOC + 6 + 6 + read-write + + + GPIOB + desc GPIOB + 5 + 5 + read-write + + + GPIOA + desc GPIOA + 4 + 4 + read-write + + + EAU + desc EAU + 3 + 3 + read-write + + + CRC + desc CRC + 2 + 2 + read-write + + + FLASH + desc FLASH + 1 + 1 + read-write + + + DMA + desc DMA + 0 + 0 + read-write + + + + + APBRST1 + APB Reset Control Reg1 + 0x48 + 32 + read-write + + + SPI3 + desc SPI3 + 14 + 14 + read-write + + + SPI2 + desc SPI2 + 13 + 13 + read-write + + + GTIM4 + desc GTIM4 + 12 + 12 + read-write + + + GTIM3 + desc GTIM3 + 11 + 11 + read-write + + + UART3 + desc UART3 + 8 + 8 + read-write + + + GTIM2 + desc GTIM2 + 7 + 7 + read-write + + + GTIM1 + desc GTIM1 + 6 + 6 + read-write + + + ATIM + desc ATIM + 5 + 5 + read-write + + + UART2 + desc UART2 + 4 + 4 + read-write + + + UART1 + desc UART1 + 3 + 3 + read-write + + + SPI1 + desc SPI1 + 2 + 2 + read-write + + + VC + desc VC + 1 + 1 + read-write + + + ADC + desc ADC + 0 + 0 + read-write + + + + + APBRST2 + APB Reset Control Reg2 + 0x44 + 32 + read-write + + + HALLTIM + desc HALLTIM + 12 + 12 + read-write + + + I2C2 + desc I2C2 + 11 + 11 + read-write + + + DAC + desc DAC + 10 + 10 + read-write + + + OPA + desc OPA + 9 + 9 + read-write + + + LPTIM + desc LPTIM + 7 + 7 + read-write + + + I2C1 + desc I2C1 + 6 + 6 + read-write + + + WWDT + desc WWDT + 5 + 5 + read-write + + + IWDT + desc IWDT + 4 + 4 + read-write + + + BTIM123 + desc BTIM123 + 2 + 2 + read-write + + + RTC + desc RTC + 1 + 1 + read-write + + + + + RESETFLAG + Reset Status Reg + 0x4C + 32 + read-write + + + SYSRESETREQ + desc SYSRESETREQ + 9 + 9 + read-write + + + LOCKUP + desc LOCKUP + 8 + 8 + read-write + + + RSTB + desc RSTB + 6 + 6 + read-write + + + WWDT + desc WWDT + 5 + 5 + read-write + + + IWDT + desc IWDT + 4 + 4 + read-write + + + LVD + desc LVD + 3 + 3 + read-write + + + POR + desc POR + 0 + 0 + read-write + + + + + DEBUG + Debug Control Reg + 0x2C + 32 + read-write + + + HALLTIM + desc HALLTIM + 11 + 11 + read-write + + + WWDT + desc WWDT + 10 + 10 + read-write + + + IWDT + desc IWDT + 9 + 9 + read-write + + + RTC + desc RTC + 8 + 8 + read-write + + + LPTIM + desc LPTIM + 6 + 6 + read-write + + + BTIM123 + desc BTIM123 + 5 + 5 + read-write + + + GTIM4 + desc GTIM4 + 4 + 4 + read-write + + + GTIM3 + desc GTIM3 + 3 + 3 + read-write + + + GTIM2 + desc GTIM2 + 2 + 2 + read-write + + + GTIM1 + desc GTIM1 + 1 + 1 + read-write + + + ATIM + desc ATIM + 0 + 0 + read-write + + + + + MCO + Master Clock Output Control Reg + 0x70 + 32 + read-write + + + DIV + desc DIV + 7 + 4 + read-write + + + SOURCE + desc SOURCE + 3 + 0 + read-write + + + + + PLL + PLL Control Reg + 0x28 + 32 + read-write + + + STABLE + desc STABLE + 16 + 16 + read-only + + + MUL + desc MUL + 15 + 8 + read-write + + + WAITCYCLE + desc WAITCYCLE + 7 + 5 + read-write + + + DIV + desc DIV + 4 + 1 + read-write + + + SOURCE + desc SOURCE + 0 + 0 + read-write + + + + + + + VC1 + desc VC1 + 0x40000084 + + VC13 + Voltage Comparator 1/3 Interrupt + 14 + + VC + VC + 32 + + 0x0 + 0x10 + registers + + + + CR0 + Control register0 + 0x0 + 32 + read-write + + + INP + desc INP + 13 + 12 + read-write + + + INN + desc INN + 9 + 8 + read-write + + + WINDOW + desc WINDOW + 7 + 7 + read-write + + + POL + desc POL + 6 + 6 + read-write + + + IE + desc IE + 5 + 5 + read-write + + + HYS + desc HYS + 3 + 3 + read-write + + + RESP + desc RESP + 1 + 1 + read-write + + + EN + desc EN + 0 + 0 + read-write + + + + + CR1 + Control register1 + 0x4 + 32 + read-write + + + BLANKLVL + desc BLANKLVL + 11 + 11 + read-write + + + BLANKTIME + desc BLANKTIME + 10 + 8 + read-write + + + HIGHIE + desc HIGHIE + 7 + 7 + read-write + + + RISEIE + desc RISEIE + 6 + 6 + read-write + + + FALLIE + desc FALLIE + 5 + 5 + read-write + + + FLTCLK + desc FLTCLK + 4 + 4 + read-write + + + FLTTIME + desc FLTTIME + 3 + 0 + read-write + + + + + CR2 + Control register1 + 0x8 + 32 + read-write + + + HALLTIM1TRGO + desc HALLTIM1TRGO + 31 + 31 + read-write + + + BTIM3TRGO + desc BTIM3TRGO + 30 + 30 + read-write + + + BTIM2TRGO + desc BTIM2TRGO + 29 + 29 + read-write + + + BTIM1TRGO + desc BTIM1TRGO + 28 + 28 + read-write + + + GTIM4OC4REFC + desc GTIM4OC4REFC + 27 + 27 + read-write + + + GTIM4OC3REFC + desc GTIM4OC3REFC + 26 + 26 + read-write + + + GTIM4OC2REFC + desc GTIM4OC2REFC + 25 + 25 + read-write + + + GTIM4OC1REFC + desc GTIM4OC1REFC + 24 + 24 + read-write + + + GTIM4TRGO + desc GTIM4TRGO + 23 + 23 + read-write + + + GTIM3OC4REFC + desc GTIM3OC4REFC + 22 + 22 + read-write + + + GTIM3OC3REFC + desc GTIM3OC3REFC + 21 + 21 + read-write + + + GTIM3OC2REFC + desc GTIM3OC2REFC + 20 + 20 + read-write + + + GTIM3OC1REFC + desc GTIM3OC1REFC + 19 + 19 + read-write + + + GTIM3TRGO + desc GTIM3TRGO + 18 + 18 + read-write + + + GTIM2OC4REFC + desc GTIM2OC4REFC + 17 + 17 + read-write + + + GTIM2OC3REFC + desc GTIM2OC3REFC + 16 + 16 + read-write + + + GTIM2OC2REFC + desc GTIM2OC2REFC + 15 + 15 + read-write + + + GTIM2OC1REFC + desc GTIM2OC1REFC + 14 + 14 + read-write + + + GTIM2TRGO + desc GTIM2TRGO + 13 + 13 + read-write + + + GTIM1OC4REFC + desc GTIM1OC4REFC + 12 + 12 + read-write + + + GTIM1OC3REFC + desc GTIM1OC3REFC + 11 + 11 + read-write + + + GTIM1OC2REFC + desc GTIM1OC2REFC + 10 + 10 + read-write + + + GTIM1OC1REFC + desc GTIM1OC1REFC + 9 + 9 + read-write + + + GTIM1TRGO + desc GTIM1TRGO + 8 + 8 + read-write + + + ATIMOC6REFC + desc ATIMOC6REFC + 7 + 7 + read-write + + + ATIMOC5REFC + desc ATIMOC5REFC + 6 + 6 + read-write + + + ATIMOC4REFC + desc ATIMOC4REFC + 5 + 5 + read-write + + + ATIMOC3REFC + desc ATIMOC3REFC + 4 + 4 + read-write + + + ATIMOC2REFC + desc ATIMOC2REFC + 3 + 3 + read-write + + + ATIMOC1REFC + desc ATIMOC1REFC + 2 + 2 + read-write + + + ATIMTRGO2 + desc ATIMTRGO2 + 1 + 1 + read-write + + + ATIMTRGO + desc ATIMTRGO + 0 + 0 + read-write + + + + + SR + Status register + 0xC + 32 + read-write + + + FLTV + desc FLTV + 1 + 1 + read-only + + + INTF + desc INTF + 0 + 0 + read-write + + + + + + + VC12REF + desc VC12REF + 0x40000080 + VC + VC2REF + 32 + + 0x0 + 0x4 + registers + + + + REF + VCREF Control register + 0x0 + 32 + read-write + + + VIN + desc VIN + 5 + 5 + read-write + + + EN + desc EN + 4 + 4 + read-write + + + DIV + desc DIV + 2 + 0 + read-write + + + + + + + VC2 + desc VC2 + 0x40000094 + + VC24 + Voltage Comparator 2/4 Interrupt + 15 + + + + VC3 + desc VC3 + 0x40000184 + + VC13 + Voltage Comparator 1/3 Interrupt + 14 + + + + VC34REF + desc VC34REF + 0x40000180 + + + VC4 + desc VC4 + 0x40000194 + + VC24 + Voltage Comparator 2/4 Interrupt + 15 + + + + WWDT + desc WWDT + 0x40005400 + + WDT + Watch Dog Timer Interrupt + 0 + + WDT + WWDT + 32 + + 0x0 + 0x0C + registers + + + + CR0 + Control register0 + 0x0 + 32 + read-write + + + EN + desc EN + 7 + 7 + read-write + + + WCNT + desc WCNT + 6 + 0 + read-write + + + + + CR1 + Control register1 + 0x4 + 32 + read-write + + + IE + desc IE + 10 + 10 + read-write + + + PRS + desc PRESCALE + 9 + 7 + read-write + + + WINR + desc WINR + 6 + 0 + read-write + + + + + SR + status register + 0x8 + 32 + read-write + + + POV + desc POV + 0 + 0 + read-write + + + + + + + \ No newline at end of file diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/debugger/WHXY/CW32L012x8.ddf b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/debugger/WHXY/CW32L012x8.ddf new file mode 100644 index 0000000..918b73e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/debugger/WHXY/CW32L012x8.ddf @@ -0,0 +1,31 @@ + +;; Architecture extensions +#include weak "../ARM/ARMv6-M-SYST.ddf" + +;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Used to define address zones within the ARM address space (Memory). +;; +;; Name may be almost anything +;; AdrSpace must be Memory +;; StartAdr start of memory block +;; EndAdr end of memory block +;; AccType type of access, read-only (R), read-write (RW) or SFR (W) + +[Memory] +;; Name AdrSpace StartAdr EndAdr AccType Width +Memory = OTP Memory 0x00100760 0x00100775 R +Memory = Factory Memory 0x00100776 0x001007FF R +Memory = PeriphAPB1 Memory 0x40000000 0x400037FF RW +Memory = PeriphAPB2 Memory 0x40004000 0x400067FF RW +Memory = PeriphAHB1 Memory 0x40020000 0x40023BFF RW +Memory = PeriphAHB2 Memory 0x48000000 0x480003FF RW +Memory = SystemSFR Memory 0xE0000000 0xE00FFFFF W +Memory = Flash Memory 0x00000000 0x0000FFFF R +Memory = RAM Memory 0x20000000 0x20001FFF RW + +TrustedRanges = true +UseSfrFilter = true + +[SfrInclude] +File = CW32L012.svd diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/devices/WHXY/CW32L012/CW32L012x8.i79 b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/devices/WHXY/CW32L012/CW32L012x8.i79 new file mode 100644 index 0000000..1ba9b00 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/devices/WHXY/CW32L012/CW32L012x8.i79 @@ -0,0 +1,25 @@ +[FILEFORMAT] +rev=1.6 + +[CHIP] +name=CW32L012x8 +endiansupport=le +thumbsupport=true +armsupport=false +fpu=None +SIMD=false +JTAG=false +SWD=true +SWO_TraceD0=false + +[CORE] +name=Cortex-M0+ + +[DDF FILE] +name=WHXY/CW32L012x8.ddf + +[LINKER FILE] +name=$TOOLKIT_DIR$/config/linker/WHXY/CW32L012x8.icf + +[FLASH LOADER] +little=$TOOLKIT_DIR$/config/flashloader/WHXY/FlashCW32L012x8.board diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/devices/WHXY/CW32L012/CW32L012x8.menu b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/devices/WHXY/CW32L012/CW32L012x8.menu new file mode 100644 index 0000000..bbae93d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/devices/WHXY/CW32L012/CW32L012x8.menu @@ -0,0 +1,6 @@ + + + CW32L012x8 + WHXY CW32L012x8 + $CUR_DIR$/CW32L012x8.i79 + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/flashloader/WHXY/FlashCW32L012x8.board b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/flashloader/WHXY/FlashCW32L012x8.board new file mode 100644 index 0000000..ac59f41 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/flashloader/WHXY/FlashCW32L012x8.board @@ -0,0 +1,7 @@ + + + + $TOOLKIT_DIR$/config/flashloader/WHXY/FlashCW32L012x8.flash + CODE 0x00000000 0x0000FFFF + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/flashloader/WHXY/FlashCW32L012x8.flash b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/flashloader/WHXY/FlashCW32L012x8.flash new file mode 100644 index 0000000..7d75fe7 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/flashloader/WHXY/FlashCW32L012x8.flash @@ -0,0 +1,7 @@ + + + $TOOLKIT_DIR$/config/flashloader/WHXY/FlashCW32L012x8.out + 1 + 128 0x200 + 0x00000000 + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/flashloader/WHXY/FlashCW32L012x8.out b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/flashloader/WHXY/FlashCW32L012x8.out new file mode 100644 index 0000000..376f087 Binary files /dev/null and b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/flashloader/WHXY/FlashCW32L012x8.out differ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/linker/WHXY/CW32L012x8.icf b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/linker/WHXY/CW32L012x8.icf new file mode 100644 index 0000000..8e5329c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/config/linker/WHXY/CW32L012x8.icf @@ -0,0 +1,30 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/WHXY/cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/WHXY/cw32l012.h new file mode 100644 index 0000000..a3d94d8 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/WHXY/cw32l012.h @@ -0,0 +1,8733 @@ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * @file CW32L012.h + * @brief CMSIS HeaderFile + * @version 1.2 + * @date Wed Jul 30 11:20:43 2025 + * @note Generated by SVDConv V3.3.46 + * from File 'cw32l012.svd', + * last modified on Wed Jul 30 11:20:28 2025 + */ + + +/** @addtogroup Wuhan Xinyuan Semiconductor Co.Ltd + * @{ + */ + + +/** @addtogroup CW32L012 + * @{ + */ + + +#ifndef __CW32L012_H +#define __CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== cw32l012 Specific Interrupt Numbers ========================================== */ + WDT_IRQn = 0, /*!< 0 Watch Dog Timer Interrupt */ + LVD_IRQn = 1, /*!< 1 Low Voltage Detect Interrupt */ + RTC_IRQn = 2, /*!< 2 Real Time Clock Interrupt */ + FLASHRAM_IRQn = 3, /*!< 3 Flash/RAM Interrupt */ + SYSCTRL_IRQn = 4, /*!< 4 SYSCTRL Interupt */ + GPIOA_IRQn = 5, /*!< 5 GPIOA Interrupt */ + GPIOB_IRQn = 6, /*!< 6 GPIOB Interrupt */ + GPIOC_IRQn = 7, /*!< 7 GPIOC Interrupt */ + GPIOF_IRQn = 8, /*!< 8 GPIOF Interrupt */ + DMACH12_IRQn = 9, /*!< 9 DMA Channel 1/2 Interrupt */ + DMACH34_IRQn = 10, /*!< 10 DMA Channel 3/4 Interrupt */ + CORDIC_IRQn = 11, /*!< 11 desc CORDIC */ + ADC1_IRQn = 12, /*!< 12 ADC Interrupt */ + ATIM_IRQn = 13, /*!< 13 Advanced Timer Interrupt */ + VC13_IRQn = 14, /*!< 14 Voltage Comparator 1/3 Interrupt */ + VC24_IRQn = 15, /*!< 15 Voltage Comparator 2/4 Interrupt */ + GTIM1_IRQn = 16, /*!< 16 General Timer1 Interrupt */ + GTIM2_IRQn = 17, /*!< 17 General Timer1 Interrupt */ + GTIM34_IRQn = 18, /*!< 18 General Timer3_4 Interrupt */ + LPTIM_IRQn = 19, /*!< 19 LPTIM Interrupt */ + BTIM1_IRQn = 20, /*!< 20 Base Timer1 Interrupt */ + BTIM2_IRQn = 21, /*!< 21 Base Timer2 Interrupt */ + BTIM3_HALLTIM_IRQn = 22, /*!< 22 Base Timer3 and Hall timer Interrupt */ + I2C1_IRQn = 23, /*!< 23 I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< 24 I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< 25 SPI1 Interrupt */ + SPI23_IRQn = 26, /*!< 26 SPI23 Interrupt */ + UART1_IRQn = 27, /*!< 27 UART1 Interrupt */ + UART2_IRQn = 28, /*!< 28 UART2 Interrupt */ + UART3_IRQn = 29, /*!< 29 UART3 Interrupt */ + ADC2_DAC_IRQn = 30, /*!< 30 ADC2 and DAC Interrupt */ + CLKFAULT_IRQn = 31 /*!< 31 Clock Fault Interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 0 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 0 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ +#include "system_cw32l012.h" /*!< cw32l012 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc ADC1 (ADC1) + */ + +typedef struct { /*!< (@ 0x40000000) ADC1 Structure */ + + union { + __IOM uint32_t CR; /*!< (@ 0x00000000) desc CR */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t CONT : 1; /*!< [1..1] desc CONT */ + __IOM uint32_t CLK : 2; /*!< [3..2] desc CLK */ + __IOM uint32_t ENS : 3; /*!< [6..4] desc ENS */ + __IOM uint32_t SLAVE : 1; /*!< [7..7] desc SLAVE */ + __IOM uint32_t SAM : 2; /*!< [9..8] desc SAM */ + } CR_f; + } ; + + union { + __IOM uint32_t START; /*!< (@ 0x00000004) desc START */ + + struct { + __IOM uint32_t START : 1; /*!< [0..0] desc START */ + } START_f; + } ; + + union { + __IOM uint32_t AWDTR; /*!< (@ 0x00000008) desc AWDTR */ + + struct { + __IOM uint32_t VTL : 12; /*!< [11..0] desc VTL */ + __IM uint32_t : 4; + __IOM uint32_t VTH : 12; /*!< [27..16] desc VTH */ + } AWDTR_f; + } ; + + union { + __IOM uint32_t AWDCR; /*!< (@ 0x0000000C) desc AWDCR */ + + struct { + __IOM uint32_t IN0 : 1; /*!< [0..0] desc IN0 */ + __IOM uint32_t IN1 : 1; /*!< [1..1] desc IN1 */ + __IOM uint32_t IN2 : 1; /*!< [2..2] desc IN2 */ + __IOM uint32_t IN3 : 1; /*!< [3..3] desc IN3 */ + __IOM uint32_t IN4 : 1; /*!< [4..4] desc IN4 */ + __IOM uint32_t IN5 : 1; /*!< [5..5] desc IN5 */ + __IOM uint32_t IN6 : 1; /*!< [6..6] desc IN6 */ + __IOM uint32_t IN7 : 1; /*!< [7..7] desc IN7 */ + __IOM uint32_t IN8 : 1; /*!< [8..8] desc IN8 */ + __IOM uint32_t IN9 : 1; /*!< [9..9] desc IN9 */ + __IOM uint32_t IN10 : 1; /*!< [10..10] desc IN10 */ + __IOM uint32_t IN11 : 1; /*!< [11..11] desc IN11 */ + __IOM uint32_t IN12 : 1; /*!< [12..12] desc IN12 */ + __IOM uint32_t IN13 : 1; /*!< [13..13] desc IN13 */ + __IOM uint32_t IN14 : 1; /*!< [14..14] desc IN14 */ + __IOM uint32_t IN15 : 1; /*!< [15..15] desc IN15 */ + } AWDCR_f; + } ; + + union { + __IOM uint32_t TRIGGER; /*!< (@ 0x00000010) desc TRIGGER */ + + struct { + __IOM uint32_t ATIMTRGO : 1; /*!< [0..0] desc ATIMTRGO */ + __IOM uint32_t ATIMTRGO2 : 1; /*!< [1..1] desc ATIMTRGO2 */ + __IOM uint32_t ATIMOC1REFC : 1; /*!< [2..2] desc ATIMOC1REFC */ + __IOM uint32_t ATIMOC2REFC : 1; /*!< [3..3] desc ATIMOC2REFC */ + __IOM uint32_t ATIMOC3REFC : 1; /*!< [4..4] desc ATIMOC3REFC */ + __IOM uint32_t ATIMOC4REFC : 1; /*!< [5..5] desc ATIMOC4REFC */ + __IOM uint32_t ATIMOC5REFC : 1; /*!< [6..6] desc ATIMOC5REFC */ + __IOM uint32_t ATIMOC6REFC : 1; /*!< [7..7] desc ATIMOC6REFC */ + __IOM uint32_t GTIM1TRGO : 1; /*!< [8..8] desc GTIM1TRGO */ + __IOM uint32_t GTIM1OC1REFC : 1; /*!< [9..9] desc GTIM1OC1REFC */ + __IOM uint32_t GTIM1OC2REFC : 1; /*!< [10..10] desc GTIM1OC2REFC */ + __IOM uint32_t GTIM1OC3REFC : 1; /*!< [11..11] desc GTIM1OC3REFC */ + __IOM uint32_t GTIM1OC4REFC : 1; /*!< [12..12] desc GTIM1OC4REFC */ + __IOM uint32_t GTIM2TRGO : 1; /*!< [13..13] desc GTIM2TRGO */ + __IOM uint32_t GTIM2OC1REFC : 1; /*!< [14..14] desc GTIM2OC1REFC */ + __IOM uint32_t GTIM2OC2REFC : 1; /*!< [15..15] desc GTIM2OC2REFC */ + __IOM uint32_t GTIM2OC3REFC : 1; /*!< [16..16] desc GTIM2OC3REFC */ + __IOM uint32_t GTIM2OC4REFC : 1; /*!< [17..17] desc GTIM2OC4REFC */ + __IOM uint32_t GTIM3TRGO : 1; /*!< [18..18] desc GTIM3TRGO */ + __IOM uint32_t GTIM3OC1REFC : 1; /*!< [19..19] desc GTIM3OC1REFC */ + __IOM uint32_t GTIM3OC2REFC : 1; /*!< [20..20] desc GTIM3OC2REFC */ + __IOM uint32_t GTIM3OC3REFC : 1; /*!< [21..21] desc GTIM3OC3REFC */ + __IOM uint32_t GTIM3OC4REFC : 1; /*!< [22..22] desc GTIM3OC4REFC */ + __IOM uint32_t GTIM4TRGO : 1; /*!< [23..23] desc GTIM4TRGO */ + __IOM uint32_t GTIM4OC1REFC : 1; /*!< [24..24] desc GTIM4OC1REFC */ + __IOM uint32_t GTIM4OC2REFC : 1; /*!< [25..25] desc GTIM4OC2REFC */ + __IOM uint32_t GTIM4OC3REFC : 1; /*!< [26..26] desc GTIM4OC3REFC */ + __IOM uint32_t GTIM4OC4REFC : 1; /*!< [27..27] desc GTIM4OC4REFC */ + __IOM uint32_t BTIM1TRGO : 1; /*!< [28..28] desc BTIM1TRGO */ + __IOM uint32_t BTIM2TRGO : 1; /*!< [29..29] desc BTIM2TRGO */ + __IOM uint32_t BTIM3TRGO : 1; /*!< [30..30] desc BTIM3TRGO */ + __IOM uint32_t HALLTIMTRGO : 1; /*!< [31..31] desc HALLTIMTRGO */ + } TRIGGER_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t SAMPLE; /*!< (@ 0x00000018) desc SAMPLE */ + + struct { + __IOM uint32_t SQRCH0 : 4; /*!< [3..0] desc SQRCH0 */ + __IOM uint32_t SQRCH1 : 4; /*!< [7..4] desc SQRCH1 */ + __IOM uint32_t SQRCH2 : 4; /*!< [11..8] desc SQRCH2 */ + __IOM uint32_t SQRCH3 : 4; /*!< [15..12] desc SQRCH3 */ + __IOM uint32_t SQRCH4 : 4; /*!< [19..16] desc SQRCH4 */ + __IOM uint32_t SQRCH5 : 4; /*!< [23..20] desc SQRCH5 */ + __IOM uint32_t SQRCH6 : 4; /*!< [27..24] desc SQRCH6 */ + __IOM uint32_t SQRCH7 : 4; /*!< [31..28] desc SQRCH7 */ + } SAMPLE_f; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t SQRCFR; /*!< (@ 0x00000020) desc SQRCFR */ + + struct { + __IOM uint32_t SQRCH0 : 4; /*!< [3..0] desc SQRCH0 */ + __IOM uint32_t SQRCH1 : 4; /*!< [7..4] desc SQRCH1 */ + __IOM uint32_t SQRCH2 : 4; /*!< [11..8] desc SQRCH2 */ + __IOM uint32_t SQRCH3 : 4; /*!< [15..12] desc SQRCH3 */ + __IOM uint32_t SQRCH4 : 4; /*!< [19..16] desc SQRCH4 */ + __IOM uint32_t SQRCH5 : 4; /*!< [23..20] desc SQRCH5 */ + __IOM uint32_t SQRCH6 : 4; /*!< [27..24] desc SQRCH6 */ + __IOM uint32_t SQRCH7 : 4; /*!< [31..28] desc SQRCH7 */ + } SQRCFR_f; + } ; + __IM uint32_t RESERVED2[3]; + + union { + __IM uint32_t RESULT0; /*!< (@ 0x00000030) desc RESULT0 */ + + struct { + __IM uint32_t RESULT : 12; /*!< [15..0] desc RESULT */ + } RESULT0_f; + } ; + + union { + __IM uint32_t RESULT1; /*!< (@ 0x00000034) desc RESULT1 */ + + struct { + __IM uint32_t RESULT : 12; /*!< [15..0] desc RESULT */ + } RESULT1_f; + } ; + + union { + __IM uint32_t RESULT2; /*!< (@ 0x00000038) desc RESULT2 */ + + struct { + __IM uint32_t RESULT : 12; /*!< [15..0] desc RESULT */ + } RESULT2_f; + } ; + + union { + __IM uint32_t RESULT3; /*!< (@ 0x0000003C) desc RESULT3 */ + + struct { + __IM uint32_t RESULT : 12; /*!< [15..0] desc RESULT */ + } RESULT3_f; + } ; + + union { + __IM uint32_t RESULT4; /*!< (@ 0x00000040) desc RESULT4 */ + + struct { + __IM uint32_t RESULT : 12; /*!< [15..0] desc RESULT */ + } RESULT4_f; + } ; + + union { + __IM uint32_t RESULT5; /*!< (@ 0x00000044) desc RESULT5 */ + + struct { + __IM uint32_t RESULT : 12; /*!< [15..0] desc RESULT */ + } RESULT5_f; + } ; + + union { + __IM uint32_t RESULT6; /*!< (@ 0x00000048) desc RESULT6 */ + + struct { + __IM uint32_t RESULT : 12; /*!< [15..0] desc RESULT */ + } RESULT6_f; + } ; + + union { + __IM uint32_t RESULT7; /*!< (@ 0x0000004C) desc RESULT7 */ + + struct { + __IM uint32_t RESULT : 12; /*!< [15..0] desc RESULT */ + } RESULT7_f; + } ; + __IM uint32_t RESERVED3[8]; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000070) desc IER */ + + struct { + __IOM uint32_t EOC : 1; /*!< [0..0] desc EOC */ + __IOM uint32_t EOS : 1; /*!< [1..1] desc EOS */ + __IM uint32_t : 1; + __IOM uint32_t AWDL : 1; /*!< [3..3] desc AWDL */ + __IOM uint32_t AWDH : 1; /*!< [4..4] desc AWDH */ + __IOM uint32_t DMAEOC : 1; /*!< [5..5] desc DMAEOC */ + __IOM uint32_t DMAEOS : 1; /*!< [6..6] desc DMAEOS */ + } IER_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000074) desc ICR */ + + struct { + __IOM uint32_t EOC : 1; /*!< [0..0] desc EOC */ + __IOM uint32_t EOS : 1; /*!< [1..1] desc EOS */ + __IM uint32_t : 1; + __IOM uint32_t AWDL : 1; /*!< [3..3] desc AWDL */ + __IOM uint32_t AWDH : 1; /*!< [4..4] desc AWDH */ + } ICR_f; + } ; + + union { + __IOM uint32_t ISR; /*!< (@ 0x00000078) desc ISR */ + + struct { + __IM uint32_t EOC : 1; /*!< [0..0] desc EOC */ + __IM uint32_t EOS : 1; /*!< [1..1] desc EOS */ + __IM uint32_t : 1; + __IM uint32_t AWDL : 1; /*!< [3..3] desc AWDL */ + __IOM uint32_t AWDH : 1; /*!< [4..4] desc AWDH */ + } ISR_f; + } ; +} ADC_TypeDef; /*!< Size = 124 (0x7c) */ + + + +/* =========================================================================================================================== */ +/* ================ ATIM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc ATIM (ATIM) + */ + +typedef struct { /*!< (@ 0x40001400) ATIM Structure */ + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control Register1 */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] desc CEN */ + __IOM uint32_t UDIS : 1; /*!< [1..1] desc UDIS */ + __IOM uint32_t URS : 1; /*!< [2..2] desc URS */ + __IOM uint32_t OPM : 1; /*!< [3..3] desc OPM */ + __IOM uint32_t DIR : 1; /*!< [4..4] desc DIR */ + __IOM uint32_t CMS : 2; /*!< [6..5] desc CMS */ + __IOM uint32_t ARPE : 1; /*!< [7..7] desc ARPE */ + __IOM uint32_t CKD : 2; /*!< [9..8] desc CKD */ + __IM uint32_t : 1; + __IOM uint32_t UIFREMAP : 1; /*!< [11..11] desc UIFREMAP */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000004) Control Register2 */ + + struct { + __IOM uint32_t CCPC : 1; /*!< [0..0] desc CCPC */ + __IM uint32_t : 1; + __IOM uint32_t CCUS : 1; /*!< [2..2] desc CCUS */ + __IOM uint32_t CCDS : 1; /*!< [3..3] desc CCDS */ + __IOM uint32_t MMS : 3; /*!< [6..4] desc MMS */ + __IOM uint32_t TI1S : 1; /*!< [7..7] desc TI1S */ + __IOM uint32_t OIS1 : 1; /*!< [8..8] desc OIS1 */ + __IOM uint32_t OIS1N : 1; /*!< [9..9] desc OIS1N */ + __IOM uint32_t OIS2 : 1; /*!< [10..10] desc OIS2 */ + __IOM uint32_t OIS2N : 1; /*!< [11..11] desc OIS2N */ + __IOM uint32_t OIS3 : 1; /*!< [12..12] desc OIS3 */ + __IOM uint32_t OIS3N : 1; /*!< [13..13] desc OIS3N */ + __IOM uint32_t OIS4 : 1; /*!< [14..14] desc OIS4 */ + __IOM uint32_t OIS4N : 1; /*!< [15..15] desc OIS4N */ + __IOM uint32_t OIS5 : 1; /*!< [16..16] desc OIS5 */ + __IOM uint32_t OIS5N : 1; /*!< [17..17] desc OIS5N */ + __IOM uint32_t OIS6 : 1; /*!< [18..18] desc OIS6 */ + __IOM uint32_t OIS6N : 1; /*!< [19..19] desc OIS6N */ + __IOM uint32_t MMS2 : 5; /*!< [24..20] desc MMS2 */ + __IOM uint32_t MMSH : 2; /*!< [26..25] desc MMSH */ + } CR2_f; + } ; + + union { + __IOM uint32_t SMCR; /*!< (@ 0x00000008) Slave Mode Control Register */ + + struct { + __IOM uint32_t SMS : 3; /*!< [2..0] desc SMS */ + __IOM uint32_t OCCS : 1; /*!< [3..3] desc OCCS */ + __IOM uint32_t TS : 3; /*!< [6..4] desc TS */ + __IOM uint32_t MSM : 1; /*!< [7..7] desc MSM */ + __IOM uint32_t ETF : 4; /*!< [11..8] desc ETF */ + __IOM uint32_t ETPS : 2; /*!< [13..12] desc ETPS */ + __IOM uint32_t ECE : 1; /*!< [14..14] desc ECE */ + __IOM uint32_t ETP : 1; /*!< [15..15] desc ETP */ + __IOM uint32_t SMSH : 1; /*!< [16..16] desc SMSH */ + __IM uint32_t : 3; + __IOM uint32_t TSH : 2; /*!< [21..20] desc TSH */ + __IM uint32_t : 2; + __IOM uint32_t SMSPE : 1; /*!< [24..24] desc SMSPE */ + __IOM uint32_t SMSPS : 1; /*!< [25..25] desc SMSPS */ + } SMCR_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x0000000C) Interrupt Enable Register */ + + struct { + __IOM uint32_t UIE : 1; /*!< [0..0] desc UIE */ + __IOM uint32_t CC1IE : 1; /*!< [1..1] desc CC1IE */ + __IOM uint32_t CC2IE : 1; /*!< [2..2] desc CC2IE */ + __IOM uint32_t CC3IE : 1; /*!< [3..3] desc CC3IE */ + __IOM uint32_t CC4IE : 1; /*!< [4..4] desc CC4IE */ + __IOM uint32_t COMIE : 1; /*!< [5..5] desc COMIE */ + __IOM uint32_t TIE : 1; /*!< [6..6] desc TIE */ + __IOM uint32_t BIE : 1; /*!< [7..7] desc BIE */ + __IOM uint32_t UDE : 1; /*!< [8..8] desc UDE */ + __IOM uint32_t CC1DE : 1; /*!< [9..9] desc CC1DE */ + __IOM uint32_t CC2DE : 1; /*!< [10..10] desc CC2DE */ + __IOM uint32_t CC3DE : 1; /*!< [11..11] desc CC3DE */ + __IOM uint32_t CC4DE : 1; /*!< [12..12] desc CC4DE */ + __IOM uint32_t COMDE : 1; /*!< [13..13] desc COMDE */ + __IOM uint32_t TDE : 1; /*!< [14..14] desc TDE */ + uint32_t : 1; + __IOM uint32_t CC5IE : 1; /*!< [16..16] desc CC5IE */ + __IOM uint32_t CC6IE : 1; /*!< [17..17] desc CC6IE */ + __IOM uint32_t CC5DE : 1; /*!< [18..18] desc CC5DE */ + __IOM uint32_t CC6DE : 1; /*!< [19..19] desc CC6DE */ + __IOM uint32_t IDXIE : 1; /*!< [20..20] desc IDXIE */ + __IOM uint32_t DIRIE : 1; /*!< [21..21] desc DIRIE */ + __IOM uint32_t IERRIE : 1; /*!< [22..22] desc IERRIE */ + __IOM uint32_t TERRIE : 1; /*!< [23..23] desc TERRIE */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000010) Interrupt status register */ + + struct { + __IM uint32_t UIF : 1; /*!< [0..0] desc UIF */ + __IM uint32_t CC1IF : 1; /*!< [1..1] desc CC1IF */ + __IM uint32_t CC2IF : 1; /*!< [2..2] desc CC2IF */ + __IM uint32_t CC3IF : 1; /*!< [3..3] desc CC3IF */ + __IM uint32_t CC4IF : 1; /*!< [4..4] desc CC4IF */ + __IM uint32_t COMIF : 1; /*!< [5..5] desc COMIF */ + __IM uint32_t TIF : 1; /*!< [6..6] desc TIF */ + __IM uint32_t BIF : 1; /*!< [7..7] desc BIF */ + __IM uint32_t B2IF : 1; /*!< [8..8] desc B2IF */ + __IM uint32_t CC1OF : 1; /*!< [9..9] desc CC1OF */ + __IM uint32_t CC2OF : 1; /*!< [10..10] desc CC2OF */ + __IM uint32_t CC3OF : 1; /*!< [11..11] desc CC3OF */ + __IM uint32_t CC4OF : 1; /*!< [12..12] desc CC4OF */ + __IM uint32_t SBIF : 1; /*!< [13..13] desc SBIF */ + __IM uint32_t : 2; + __IM uint32_t CC5IF : 1; /*!< [16..16] desc CC5IF */ + __IM uint32_t CC6IF : 1; /*!< [17..17] desc CC6IF */ + __IM uint32_t CC5OF : 1; /*!< [18..18] desc CC5OF */ + __IM uint32_t CC6OF : 1; /*!< [19..19] desc CC6OF */ + __IM uint32_t IDXF : 1; /*!< [20..20] desc IDXF */ + __IM uint32_t DIRF : 1; /*!< [21..21] desc DIRF */ + __IM uint32_t IERRF : 1; /*!< [22..22] desc IERRF */ + __IM uint32_t TERRF : 1; /*!< [23..23] desc TERRF */ + } ISR_f; + } ; + + union { + __IOM uint32_t EGR; /*!< (@ 0x00000014) Event generation register */ + + struct { + __IOM uint32_t UG : 1; /*!< [0..0] desc UG */ + __IOM uint32_t CC1G : 1; /*!< [1..1] desc CC1G */ + __IOM uint32_t CC2G : 1; /*!< [2..2] desc CC2G */ + __IOM uint32_t CC3G : 1; /*!< [3..3] desc CC3G */ + __IOM uint32_t CC4G : 1; /*!< [4..4] desc CC4G */ + __IOM uint32_t COMG : 1; /*!< [5..5] desc COMG */ + __IOM uint32_t TG : 1; /*!< [6..6] desc TG */ + __IOM uint32_t BG : 1; /*!< [7..7] desc BG */ + __IOM uint32_t B2G : 1; /*!< [8..8] desc B2G */ + __IM uint32_t : 7; + __IOM uint32_t CC5G : 1; /*!< [16..16] desc CC5G */ + __IOM uint32_t CC6G : 1; /*!< [17..17] desc CC6G */ + } EGR_f; + } ; + + union { + union { + __IOM uint32_t CCMR1CAP; /*!< (@ 0x00000018) capture compare mode register 1 */ + + struct { + __IOM uint32_t CC1S : 2; /*!< [1..0] desc CC1S */ + __IOM uint32_t IC1PSC : 2; /*!< [3..2] desc IC1PSC */ + __IOM uint32_t IC1F : 4; /*!< [7..4] desc IC1F */ + __IOM uint32_t CC2S : 2; /*!< [9..8] desc CC2S */ + __IOM uint32_t IC2PSC : 2; /*!< [11..10] desc IC2PSC */ + __IOM uint32_t IC2F : 4; /*!< [15..12] desc IC2F */ + } CCMR1CAP_f; + } ; + + union { + __IOM uint32_t CCMR1CMP; /*!< (@ 0x00000018) capture compare mode register 1 */ + + struct { + __IOM uint32_t CC1S : 2; /*!< [1..0] desc CC1S */ + __IOM uint32_t OC1FE : 1; /*!< [2..2] desc OC1FE */ + __IOM uint32_t OC1PE : 1; /*!< [3..3] desc OC1PE */ + __IOM uint32_t OC1M : 3; /*!< [6..4] desc OC1M */ + __IOM uint32_t OC1CE : 1; /*!< [7..7] desc OC1CE */ + __IOM uint32_t CC2S : 2; /*!< [9..8] desc CC2S */ + __IOM uint32_t OC2FE : 1; /*!< [10..10] desc OC2FE */ + __IOM uint32_t OC2PE : 1; /*!< [11..11] desc OC2PE */ + __IOM uint32_t OC2M : 3; /*!< [14..12] desc OC2M */ + __IOM uint32_t OC2CE : 1; /*!< [15..15] desc OC2CE */ + __IOM uint32_t OC1MH : 1; /*!< [16..16] desc OC1MH */ + __IM uint32_t : 7; + __IOM uint32_t OC2MH : 1; /*!< [24..24] desc OC2MH */ + } CCMR1CMP_f; + } ; + }; + + union { + union { + __IOM uint32_t CCMR2CAP; /*!< (@ 0x0000001C) capture compare mode register 2 */ + + struct { + __IOM uint32_t CC3S : 2; /*!< [1..0] desc CC3S */ + __IOM uint32_t IC3PSC : 2; /*!< [3..2] desc IC3PSC */ + __IOM uint32_t IC3F : 4; /*!< [7..4] desc IC3F */ + __IOM uint32_t CC4S : 2; /*!< [9..8] desc CC4S */ + __IOM uint32_t IC4PSC : 2; /*!< [11..10] desc IC4PSC */ + __IOM uint32_t IC4F : 4; /*!< [15..12] desc IC4F */ + } CCMR2CAP_f; + } ; + + union { + __IOM uint32_t CCMR2CMP; /*!< (@ 0x0000001C) capture compare mode register 2 */ + + struct { + __IOM uint32_t CC3S : 2; /*!< [1..0] desc CC3S */ + __IOM uint32_t OC3FE : 1; /*!< [2..2] desc OC3FE */ + __IOM uint32_t OC3PE : 1; /*!< [3..3] desc OC3PE */ + __IOM uint32_t OC3M : 3; /*!< [6..4] desc OC3M */ + __IOM uint32_t OC3CE : 1; /*!< [7..7] desc OC3CE */ + __IOM uint32_t CC4S : 2; /*!< [9..8] desc CC4S */ + __IOM uint32_t OC4FE : 1; /*!< [10..10] desc OC4FE */ + __IOM uint32_t OC4PE : 1; /*!< [11..11] desc OC4PE */ + __IOM uint32_t OC4M : 3; /*!< [14..12] desc OC4M */ + __IOM uint32_t OC4CE : 1; /*!< [15..15] desc OC4CE */ + __IOM uint32_t OC3MH : 1; /*!< [16..16] desc OC3MH */ + __IM uint32_t : 7; + __IOM uint32_t OC4MH : 1; /*!< [24..24] desc OC4MH */ + } CCMR2CMP_f; + } ; + }; + + union { + __IOM uint32_t CCER; /*!< (@ 0x00000020) capture compare enable register */ + + struct { + __IOM uint32_t CC1E : 1; /*!< [0..0] desc CC1E */ + __IOM uint32_t CC1P : 1; /*!< [1..1] desc CC1P */ + __IOM uint32_t CC1NE : 1; /*!< [2..2] desc CC1NE */ + __IOM uint32_t CC1NP : 1; /*!< [3..3] desc CC1NP */ + __IOM uint32_t CC2E : 1; /*!< [4..4] desc CC2E */ + __IOM uint32_t CC2P : 1; /*!< [5..5] desc CC2P */ + __IOM uint32_t CC2NE : 1; /*!< [6..6] desc CC2NE */ + __IOM uint32_t CC2NP : 1; /*!< [7..7] desc CC2NP */ + __IOM uint32_t CC3E : 1; /*!< [8..8] desc CC3E */ + __IOM uint32_t CC3P : 1; /*!< [9..9] desc CC3P */ + __IOM uint32_t CC3NE : 1; /*!< [10..10] desc CC3NE */ + __IOM uint32_t CC3NP : 1; /*!< [11..11] desc CC3NP */ + __IOM uint32_t CC4E : 1; /*!< [12..12] desc CC4E */ + __IOM uint32_t CC4P : 1; /*!< [13..13] desc CC4P */ + __IOM uint32_t CC4NE : 1; /*!< [14..14] desc CC4NE */ + __IOM uint32_t CC4NP : 1; /*!< [15..15] desc CC4NP */ + __IOM uint32_t CC5E : 1; /*!< [16..16] desc CC5E */ + __IOM uint32_t CC5P : 1; /*!< [17..17] desc CC5P */ + __IOM uint32_t CC5NE : 1; /*!< [18..18] desc CC5NE */ + __IOM uint32_t CC5NP : 1; /*!< [19..19] desc CC5NP */ + __IOM uint32_t CC6E : 1; /*!< [20..20] desc CC6E */ + __IOM uint32_t CC6P : 1; /*!< [21..21] desc CC6P */ + __IOM uint32_t CC6NE : 1; /*!< [22..22] desc CC6NE */ + __IOM uint32_t CC6NP : 1; /*!< [23..23] desc CC6NP */ + } CCER_f; + } ; + + union { + __IOM uint32_t CNT; /*!< (@ 0x00000024) Counter Register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IM uint32_t : 15; + __IM uint32_t UIFCPY : 1; /*!< [31..31] desc UIFCPY */ + } CNT_f; + } ; + + union { + __IOM uint32_t PSC; /*!< (@ 0x00000028) prescaler Register */ + + struct { + __IOM uint32_t PSC : 16; /*!< [15..0] desc PSC */ + } PSC_f; + } ; + + union { + __IOM uint32_t ARR; /*!< (@ 0x0000002C) Auto reload Register */ + + struct { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } ARR_f; + } ; + + union { + __IOM uint32_t RCR; /*!< (@ 0x00000030) Repetition Counter Register */ + + struct { + __IOM uint32_t REP : 16; /*!< [15..0] desc REP */ + } RCR_f; + } ; + + union { + __IOM uint32_t CCR1; /*!< (@ 0x00000034) capture compare register1 */ + + struct { + __IOM uint32_t CCR1 : 16; /*!< [15..0] desc CCR1 */ + } CCR1_f; + } ; + + union { + __IOM uint32_t CCR2; /*!< (@ 0x00000038) capture compare register2 */ + + struct { + __IOM uint32_t CCR2 : 16; /*!< [15..0] desc CCR2 */ + } CCR2_f; + } ; + + union { + __IOM uint32_t CCR3; /*!< (@ 0x0000003C) capture compare register3 */ + + struct { + __IOM uint32_t CCR3 : 16; /*!< [15..0] desc CCR3 */ + } CCR3_f; + } ; + + union { + __IOM uint32_t CCR4; /*!< (@ 0x00000040) capture compare register4 */ + + struct { + __IOM uint32_t CCR4 : 16; /*!< [15..0] desc CCR4 */ + } CCR4_f; + } ; + + union { + __IOM uint32_t BDTR; /*!< (@ 0x00000044) break and dead-time register */ + + struct { + __IOM uint32_t DTG : 8; /*!< [7..0] desc DTG */ + __IOM uint32_t LOCK : 2; /*!< [9..8] desc LOCK */ + __IOM uint32_t OSSI : 1; /*!< [10..10] desc OSSI */ + __IOM uint32_t OSSR : 1; /*!< [11..11] desc OSSR */ + __IOM uint32_t BKE : 1; /*!< [12..12] desc BKE */ + __IOM uint32_t BKP : 1; /*!< [13..13] desc BKP */ + __IOM uint32_t AOE : 1; /*!< [14..14] desc AOE */ + __IOM uint32_t MOE : 1; /*!< [15..15] desc MOE */ + __IOM uint32_t BKF : 4; /*!< [19..16] desc BKF */ + __IOM uint32_t BK2F : 4; /*!< [23..20] desc BK2F */ + __IOM uint32_t BK2E : 1; /*!< [24..24] desc BK2E */ + __IOM uint32_t BK2P : 1; /*!< [25..25] desc BK2P */ + } BDTR_f; + } ; + + union { + __IOM uint32_t CCR5; /*!< (@ 0x00000048) capture compare register5 */ + + struct { + __IOM uint32_t CCR5 : 16; /*!< [15..0] desc CCR5 */ + __IM uint32_t : 10; + __IOM uint32_t GC5C1 : 1; /*!< [26..26] desc GC5C1 */ + __IOM uint32_t GC5C2 : 1; /*!< [27..27] desc GC5C2 */ + __IOM uint32_t GC5C3 : 1; /*!< [28..28] desc GC5C3 */ + __IOM uint32_t GC5C4 : 1; /*!< [29..29] desc GC5C4 */ + __IOM uint32_t GC5C5 : 1; /*!< [30..30] desc GC5C5 */ + __IOM uint32_t GC5C6 : 1; /*!< [31..31] desc GC5C6 */ + } CCR5_f; + } ; + + union { + __IOM uint32_t CCR6; /*!< (@ 0x0000004C) capture compare register6 */ + + struct { + __IOM uint32_t CCR6 : 16; /*!< [15..0] desc CCR6 */ + __IM uint32_t : 10; + __IOM uint32_t GC6C1 : 1; /*!< [26..26] desc GC6C1 */ + __IOM uint32_t GC6C2 : 1; /*!< [27..27] desc GC6C2 */ + __IOM uint32_t GC6C3 : 1; /*!< [28..28] desc GC6C3 */ + __IOM uint32_t GC6C4 : 1; /*!< [29..29] desc GC6C4 */ + __IOM uint32_t GC6C5 : 1; /*!< [30..30] desc GC6C5 */ + __IOM uint32_t GC6C6 : 1; /*!< [31..31] desc GC6C6 */ + } CCR6_f; + } ; + + union { + union { + __IOM uint32_t CCMR3CAP; /*!< (@ 0x00000050) capture compare mode register 3 */ + + struct { + __IOM uint32_t CC5S : 2; /*!< [1..0] desc CC5S */ + __IOM uint32_t IC5PSC : 2; /*!< [3..2] desc IC5PSC */ + __IOM uint32_t IC5F : 4; /*!< [7..4] desc IC5F */ + __IOM uint32_t CC6S : 2; /*!< [9..8] desc CC6S */ + __IOM uint32_t IC6PSC : 2; /*!< [11..10] desc IC6PSC */ + __IOM uint32_t IC6F : 4; /*!< [15..12] desc IC6F */ + } CCMR3CAP_f; + } ; + + union { + __IOM uint32_t CCMR3CMP; /*!< (@ 0x00000050) capture compare mode register 3 */ + + struct { + __IOM uint32_t CC5S : 2; /*!< [1..0] desc CC5S */ + __IOM uint32_t OC5FE : 1; /*!< [2..2] desc OC5FE */ + __IOM uint32_t OC5PE : 1; /*!< [3..3] desc OC5PE */ + __IOM uint32_t OC5M : 3; /*!< [6..4] desc OC5M */ + __IOM uint32_t OC5CE : 1; /*!< [7..7] desc OC5CE */ + __IOM uint32_t CC6S : 2; /*!< [9..8] desc CC6S */ + __IOM uint32_t OC6FE : 1; /*!< [10..10] desc OC6FE */ + __IOM uint32_t OC6PE : 1; /*!< [11..11] desc OC6PE */ + __IOM uint32_t OC6M : 3; /*!< [14..12] desc OC6M */ + __IOM uint32_t OC6CE : 1; /*!< [15..15] desc OC6CE */ + __IOM uint32_t OC5MH : 1; /*!< [16..16] desc OC5MH */ + __IM uint32_t : 7; + __IOM uint32_t OC6MH : 1; /*!< [24..24] desc OC6MH */ + } CCMR3CMP_f; + } ; + }; + + union { + __IOM uint32_t DTR2; /*!< (@ 0x00000054) dead-time register2 */ + + struct { + __IOM uint32_t DTGF : 8; /*!< [7..0] desc DTGF */ + __IM uint32_t : 8; + __IOM uint32_t DTAE : 1; /*!< [16..16] desc DTAE */ + __IOM uint32_t DTPE : 1; /*!< [17..17] desc DTPE */ + } DTR2_f; + } ; + + union { + __IOM uint32_t ECR; /*!< (@ 0x00000058) Encoder control Register */ + + struct { + __IOM uint32_t IE : 1; /*!< [0..0] desc IE */ + __IOM uint32_t IDIR : 2; /*!< [2..1] desc IDIR */ + __IM uint32_t : 2; + __IOM uint32_t FIDX : 1; /*!< [5..5] desc FIDX */ + __IOM uint32_t IPOS : 2; /*!< [7..6] desc IPOS */ + } ECR_f; + } ; + + union { + __IOM uint32_t TISEL1; /*!< (@ 0x0000005C) Timer Input Select Register1 */ + + struct { + __IOM uint32_t TI1SEL : 4; /*!< [3..0] desc TI1SEL */ + __IM uint32_t : 4; + __IOM uint32_t TI2SEL : 4; /*!< [11..8] desc TI2SEL */ + __IM uint32_t : 4; + __IOM uint32_t TI3SEL : 4; /*!< [19..16] desc TI3SEL */ + __IM uint32_t : 4; + __IOM uint32_t TI4SEL : 4; /*!< [27..24] desc TI4SEL */ + } TISEL1_f; + } ; + + union { + __IOM uint32_t AF1; /*!< (@ 0x00000060) Alternate function Register1 */ + + struct { + __IOM uint32_t BKINE : 1; /*!< [0..0] desc BKINE */ + __IOM uint32_t BKVC1E : 1; /*!< [1..1] desc BKVC1E */ + __IOM uint32_t BKVC2E : 1; /*!< [2..2] desc BKVC2E */ + __IOM uint32_t BKVC3E : 1; /*!< [3..3] desc BKVC3E */ + __IOM uint32_t BKVC4E : 1; /*!< [4..4] desc BKVC4E */ + __IM uint32_t : 4; + __IOM uint32_t BKINP : 1; /*!< [9..9] desc BKINP */ + __IOM uint32_t BKVC1P : 1; /*!< [10..10] desc BKVC1P */ + __IOM uint32_t BKVC2P : 1; /*!< [11..11] desc BKVC2P */ + __IOM uint32_t BKVC3P : 1; /*!< [12..12] desc BKVC3P */ + __IOM uint32_t BKVC4P : 1; /*!< [13..13] desc BKVC4P */ + __IM uint32_t : 2; + __IOM uint32_t ETRSEL : 4; /*!< [19..16] desc ETRSEL */ + } AF1_f; + } ; + + union { + __IOM uint32_t AF2; /*!< (@ 0x00000064) Alternate function Register2 */ + + struct { + __IOM uint32_t BK2INE : 1; /*!< [0..0] desc BK2INE */ + __IOM uint32_t BK2VC1E : 1; /*!< [1..1] desc BK2VC1E */ + __IOM uint32_t BK2VC2E : 1; /*!< [2..2] desc BK2VC2E */ + __IOM uint32_t BK2VC3E : 1; /*!< [3..3] desc BK2VC3E */ + __IOM uint32_t BK2VC4E : 1; /*!< [4..4] desc BK2VC4E */ + __IM uint32_t : 4; + __IOM uint32_t BK2INP : 1; /*!< [9..9] desc BK2INP */ + __IOM uint32_t BK2VC1P : 1; /*!< [10..10] desc BK2VC1P */ + __IOM uint32_t BK2VC2P : 1; /*!< [11..11] desc BK2VC2P */ + __IOM uint32_t BK2VC3P : 1; /*!< [12..12] desc BK2VC3P */ + __IOM uint32_t BK2VC4P : 1; /*!< [13..13] desc BK2VC4P */ + __IM uint32_t : 2; + __IOM uint32_t OCRSEL : 4; /*!< [19..16] desc OCRSEL */ + } AF2_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t TISEL2; /*!< (@ 0x0000006C) Timer Input Select Register2 */ + + struct { + __IOM uint32_t TI5SEL : 4; /*!< [3..0] desc TI5SEL */ + __IM uint32_t : 4; + __IOM uint32_t TI6SEL : 4; /*!< [11..8] desc TI6SEL */ + } TISEL2_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000070) Interrupt clean register */ + + struct { + __IOM uint32_t UIF : 1; /*!< [0..0] desc UIF */ + __IOM uint32_t CC1IF : 1; /*!< [1..1] desc CC1IF */ + __IOM uint32_t CC2IF : 1; /*!< [2..2] desc CC2IF */ + __IOM uint32_t CC3IF : 1; /*!< [3..3] desc CC3IF */ + __IOM uint32_t CC4IF : 1; /*!< [4..4] desc CC4IF */ + __IOM uint32_t COMIF : 1; /*!< [5..5] desc COMIF */ + __IOM uint32_t TIF : 1; /*!< [6..6] desc TIF */ + __IOM uint32_t BIF : 1; /*!< [7..7] desc BIF */ + __IOM uint32_t B2IF : 1; /*!< [8..8] desc B2IF */ + __IOM uint32_t CC1OF : 1; /*!< [9..9] desc CC1OF */ + __IOM uint32_t CC2OF : 1; /*!< [10..10] desc CC2OF */ + __IOM uint32_t CC3OF : 1; /*!< [11..11] desc CC3OF */ + __IOM uint32_t CC4OF : 1; /*!< [12..12] desc CC4OF */ + __IOM uint32_t SBIF : 1; /*!< [13..13] desc SBIF */ + __IM uint32_t : 2; + __IOM uint32_t CC5IF : 1; /*!< [16..16] desc CC5IF */ + __IOM uint32_t CC6IF : 1; /*!< [17..17] desc CC6IF */ + __IOM uint32_t CC5OF : 1; /*!< [18..18] desc CC5OF */ + __IOM uint32_t CC6OF : 1; /*!< [19..19] desc CC6OF */ + __IOM uint32_t IDXF : 1; /*!< [20..20] desc IDXF */ + __IOM uint32_t DIRF : 1; /*!< [21..21] desc DIRF */ + __IOM uint32_t IERRF : 1; /*!< [22..22] desc IERRF */ + __IOM uint32_t TERRF : 1; /*!< [23..23] desc TERRF */ + } ICR_f; + } ; +} ATIM_TypeDef; /*!< Size = 116 (0x74) */ + + + +/* =========================================================================================================================== */ +/* ================ BGR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief BGR (BGR) + */ + +typedef struct { /*!< (@ 0x400000FC) BGR Structure */ + + union { + __IOM uint32_t CR; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t BGREN : 1; /*!< [0..0] desc BGREN */ + __IOM uint32_t TSEN : 1; /*!< [1..1] desc TSEN */ + } CR_f; + } ; +} BGR_TypeDef; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ BTIM1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Base Timer 1 (BTIM1) + */ + +typedef struct { /*!< (@ 0x40004800) BTIM1 Structure */ + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t UDIS : 1; /*!< [1..1] desc UDIS */ + __IOM uint32_t URS : 1; /*!< [2..2] desc URS */ + __IOM uint32_t ONESHOT : 1; /*!< [3..3] desc ONESHOT */ + __IM uint32_t : 7; + __IOM uint32_t UIFREMAP : 1; /*!< [11..11] desc UIFREMAP */ + __IM uint32_t : 3; + __IOM uint32_t TOGEN : 1; /*!< [15..15] desc TOGEN */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000004) Control register2 */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t MMS : 3; /*!< [6..4] desc MMS */ + } CR2_f; + } ; + + union { + __IOM uint32_t SMCR; /*!< (@ 0x00000008) Slave Mode Control register */ + + struct { + __IOM uint32_t SMS : 3; /*!< [2..0] desc SMS */ + __IOM uint32_t RSTISRC : 4; /*!< [6..3] desc RSTISRC */ + __IOM uint32_t TRGISRC : 4; /*!< [10..7] desc TRGISRC */ + __IOM uint32_t MSM : 1; /*!< [11..11] desc MSM */ + __IOM uint32_t TRGIFLT : 3; /*!< [14..12] desc TRGIFLT */ + __IM uint32_t : 1; + __IOM uint32_t RSTIPOL : 1; /*!< [16..16] desc RSTIPOL */ + __IOM uint32_t TRGIPOL : 1; /*!< [17..17] desc TRGIPOL */ + } SMCR_f; + } ; + + union { + __IOM uint32_t DIER; /*!< (@ 0x0000000C) Interrupt enable register */ + + struct { + __IOM uint32_t UIE : 1; /*!< [0..0] desc UIE */ + __IM uint32_t : 5; + __IOM uint32_t TIE : 1; /*!< [6..6] desc TIE */ + uint32_t : 1; + __IOM uint32_t UDE : 1; /*!< [8..8] desc UDE */ + uint32_t : 5; + __IOM uint32_t TDE : 1; /*!< [14..14] desc TDE */ + } DIER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000010) Interrupt status register */ + + struct { + __IM uint32_t UIF : 1; /*!< [0..0] desc UIF */ + __IM uint32_t : 5; + __IM uint32_t TIF : 1; /*!< [6..6] desc TIF */ + } ISR_f; + } ; + + union { + __OM uint32_t EGR; /*!< (@ 0x00000014) Event Generate register */ + + struct { + __OM uint32_t UG : 1; /*!< [0..0] desc UG */ + __IM uint32_t : 5; + __OM uint32_t TG : 1; /*!< [6..6] desc TG */ + } EGR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000018) Interrupt flag clear register */ + + struct { + __IOM uint32_t UIF : 1; /*!< [0..0] desc UIF */ + __IM uint32_t : 5; + __IOM uint32_t TIF : 1; /*!< [6..6] desc TIF */ + } ICR_f; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t CNT; /*!< (@ 0x00000024) Counter Register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IM uint32_t : 15; + __IM uint32_t UIFCPY : 1; /*!< [31..31] desc UIFCPY */ + } CNT_f; + } ; + + union { + __IOM uint32_t PSC; /*!< (@ 0x00000028) Prescaler Control Register */ + + struct { + __IOM uint32_t PSC : 16; /*!< [15..0] desc PSC */ + } PSC_f; + } ; + + union { + __IOM uint32_t ARR; /*!< (@ 0x0000002C) Auto Reload Register */ + + struct { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } ARR_f; + } ; +} BTIM_TypeDef; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ CORDIC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc CORDIC (CORDIC) + */ + +typedef struct { /*!< (@ 0x40023400) CORDIC Structure */ + + union { + __IOM uint32_t CSR; /*!< (@ 0x00000000) Control and State register */ + + struct { + __IOM uint32_t FUNC : 4; /*!< [3..0] desc FUNC */ + __IOM uint32_t SCALE : 3; /*!< [6..4] desc SCALE */ + __IOM uint32_t FORMAT : 1; /*!< [7..7] desc FORMAT */ + __IOM uint32_t ITER : 4; /*!< [11..8] desc ITER */ + __IOM uint32_t COMP : 1; /*!< [12..12] desc COMP */ + __IOM uint32_t IE : 1; /*!< [13..13] desc IE */ + __IOM uint32_t DMAEOC : 1; /*!< [14..14] desc DMAEOC */ + __IOM uint32_t DMAIDLE : 1; /*!< [15..15] desc DMAIDLE */ + __IM uint32_t EOC : 1; /*!< [16..16] desc EOC */ + __IM uint32_t BUSY : 1; /*!< [17..17] desc BUSY */ + } CSR_f; + } ; + + union { + __IOM uint32_t X; /*!< (@ 0x00000004) Data register X */ + + struct { + __IOM uint32_t X : 32; /*!< [31..0] desc DATA */ + } X_f; + } ; + + union { + __IOM uint32_t Y; /*!< (@ 0x00000008) Data register Y */ + + struct { + __IOM uint32_t Y : 32; /*!< [31..0] desc DATA */ + } Y_f; + } ; + + union { + __IOM uint32_t Z; /*!< (@ 0x0000000C) Data register Y */ + + struct { + __IOM uint32_t Z : 32; /*!< [31..0] desc DATA */ + } Z_f; + } ; +} CORDIC_TypeDef; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ CRC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc CRC (CRC) + */ + +typedef struct { /*!< (@ 0x40023000) CRC Structure */ + + union { + __IOM uint32_t CR; /*!< (@ 0x00000000) Control register */ + + struct { + __IOM uint32_t MODE : 4; /*!< [3..0] desc MODE */ + } CR_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t DR; /*!< (@ 0x00000008) Data register */ + + struct { + __IOM uint32_t DR : 8; /*!< [7..0] desc DR */ + } DR_f; + } ; + + union { + __IM uint32_t RESULT; /*!< (@ 0x0000000C) Result register */ + + struct { + __IM uint32_t RESULT : 16; /*!< [15..0] desc RESULT */ + } RESULT_f; + } ; +} CRC_TypeDef; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ DAC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc DAC (DAC) + */ + +typedef struct { /*!< (@ 0x400000C0) DAC Structure */ + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control register */ + + struct { + __IOM uint32_t EN1 : 1; /*!< [0..0] desc EN1 */ + __IOM uint32_t TEN1 : 1; /*!< [1..1] desc TEN1 */ + __IOM uint32_t TSEL1 : 4; /*!< [5..2] desc TSEL1 */ + __IOM uint32_t WAVE1 : 2; /*!< [7..6] desc WAVE1 */ + __IOM uint32_t MAMP1 : 4; /*!< [11..8] desc MAMP1 */ + __IOM uint32_t DMAEN1 : 1; /*!< [12..12] desc DMAEN1 */ + __IOM uint32_t DMAUDRIE1 : 1; /*!< [13..13] desc DMAUDRIE1 */ + __IM uint32_t : 2; + __IOM uint32_t EN2 : 1; /*!< [16..16] desc EN2 */ + __IOM uint32_t TEN2 : 1; /*!< [17..17] desc TEN2 */ + __IOM uint32_t TSEL2 : 4; /*!< [21..18] desc TSEL2 */ + __IOM uint32_t WAVE2 : 2; /*!< [23..22] desc WAVE2 */ + __IOM uint32_t MAMP2 : 4; /*!< [27..24] desc MAMP2 */ + __IOM uint32_t DMAEN2 : 1; /*!< [28..28] desc DMAEN2 */ + __IOM uint32_t DMAUDRIE2 : 1; /*!< [29..29] desc DMAUDRIE2 */ + } CR0_f; + } ; + + union { + __IOM uint32_t SWTRGR; /*!< (@ 0x00000004) Data register */ + + struct { + __IOM uint32_t SWTRIG1 : 1; /*!< [0..0] desc SWTRIG1 */ + __IOM uint32_t SWTRIG2 : 1; /*!< [1..1] desc SWTRIG2 */ + } SWTRGR_f; + } ; + + union { + __IOM uint32_t DHR12R1; /*!< (@ 0x00000008) Result register */ + + struct { + __IOM uint32_t DATA : 12; /*!< [11..0] desc DATA */ + } DHR12R1_f; + } ; + + union { + __IOM uint32_t DHR12L1; /*!< (@ 0x0000000C) Result register */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t DATA : 12; /*!< [15..4] desc DATA */ + }DHR12L1_f; + } ; + + union { + __IOM uint32_t DHR8R1; /*!< (@ 0x00000010) Result register */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t DATA : 4; /*!< [7..4] desc DATA */ + } DHR8R1_f; + } ; + + union { + __IOM uint32_t DHR12R2; /*!< (@ 0x00000014) Result register */ + + struct { + __IOM uint32_t DATA : 12; /*!< [11..0] desc DATA */ + } DHR12R2_f; + } ; + + union { + __IOM uint32_t DHR12L2; /*!< (@ 0x00000018) Result register */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t DATA : 12; /*!< [15..4] desc DATA */ + } DHR12L2_f; + } ; + + union { + __IOM uint32_t DHR8R2; /*!< (@ 0x0000001C) Result register */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t DATA : 4; /*!< [7..4] desc DATA */ + } DHR8R2_f; + } ; + + union { + __IOM uint32_t DHR12RD; /*!< (@ 0x00000020) Result register */ + + struct { + __IOM uint32_t C1DATA : 12; /*!< [11..0] desc C1DATA */ + __IM uint32_t : 4; + __IOM uint32_t C2DATA : 12; /*!< [27..16] desc C2DATA */ + } DHR12RD_f; + } ; + + union { + __IOM uint32_t DHR12LD; /*!< (@ 0x00000024) Result register */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t C1DATA : 12; /*!< [15..4] desc C1DATA */ + __IM uint32_t : 4; + __IOM uint32_t C2DATA : 12; /*!< [31..20] desc C2DATA */ + } DHR12LD_f; + } ; + + union { + __IOM uint32_t DHR8RD; /*!< (@ 0x00000028) Result register */ + + struct { + __IOM uint32_t C1DATA : 8; /*!< [7..0] desc C1DATA */ + __IOM uint32_t C2DATA : 8; /*!< [15..8] desc C2DATA */ + } DHR8RD_f; + } ; + + union { + __IOM uint32_t DOR1; /*!< (@ 0x0000002C) Result register */ + + struct { + __IOM uint32_t DATA : 12; /*!< [12..0] desc DATA */ + __IM uint32_t : 3; + __IOM uint32_t DMAUDR : 1; /*!< [15..15] desc DMAUDR */ + } DOR1_f; + } ; + + union { + __IOM uint32_t DOR2; /*!< (@ 0x00000030) Result register */ + + struct { + __IOM uint32_t DATA : 12; /*!< [11..0] desc DATA */ + __IM uint32_t : 3; + __IOM uint32_t DMAUDR : 1; /*!< [15..15] desc DMAUDR */ + } DOR2_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000034) Result register */ + + struct { + __IOM uint32_t C1OUT : 1; /*!< [0..0] desc C1OUT */ + __IOM uint32_t C2OUT : 1; /*!< [1..1] desc C2OUT */ + } CR1_f; + } ; +} DAC_TypeDef; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc DMA (DMA) + */ + +typedef struct { /*!< (@ 0x40020000) DMA Structure */ + + union { + __IM uint32_t ISR; /*!< (@ 0x00000000) Interrupt status register */ + + struct { + __IM uint32_t TC1 : 1; /*!< [0..0] desc TC1 */ + __IM uint32_t TE1 : 1; /*!< [1..1] desc TE1 */ + __IM uint32_t : 2; + __IM uint32_t TC2 : 1; /*!< [4..4] desc TC2 */ + __IM uint32_t TE2 : 1; /*!< [5..5] desc TE2 */ + __IM uint32_t : 2; + __IM uint32_t TC3 : 1; /*!< [8..8] desc TC3 */ + __IM uint32_t TE3 : 1; /*!< [9..9] desc TE3 */ + __IM uint32_t : 2; + __IM uint32_t TC4 : 1; /*!< [12..12] desc TC4 */ + __IM uint32_t TE4 : 1; /*!< [13..13] desc TE4 */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000004) Interrupt flag clear register */ + + struct { + __IOM uint32_t TC1 : 1; /*!< [0..0] desc TC1 */ + __IOM uint32_t TE1 : 1; /*!< [1..1] desc TE1 */ + __IM uint32_t : 2; + __IOM uint32_t TC2 : 1; /*!< [4..4] desc TC2 */ + __IOM uint32_t TE2 : 1; /*!< [5..5] desc TE2 */ + __IM uint32_t : 2; + __IOM uint32_t TC3 : 1; /*!< [8..8] desc TC3 */ + __IOM uint32_t TE3 : 1; /*!< [9..9] desc TE3 */ + __IM uint32_t : 2; + __IOM uint32_t TC4 : 1; /*!< [12..12] desc TC4 */ + __IOM uint32_t TE4 : 1; /*!< [13..13] desc TE4 */ + } ICR_f; + } ; + __IM uint32_t RESERVED[6]; + + union { + __IOM uint32_t CSR1; /*!< (@ 0x00000020) Channel1 control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IOM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + __IOM uint32_t RESTART : 1; /*!< [11..11] desc RESTART */ + __IM uint32_t TC : 1; /*!< [12..12] desc TC */ + __IM uint32_t TE : 1; /*!< [13..13] desc TE */ + __IOM uint32_t SRCLOAD : 1; /*!< [14..14] desc SRCLOAD */ + __IOM uint32_t DSTLOAD : 1; /*!< [15..15] desc DSTLOAD */ + } CSR1_f; + } ; + + union { + __IOM uint32_t CNT1; /*!< (@ 0x00000024) Channel1 counter register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT1_f; + } ; + + union { + __IOM uint32_t SRCADDR1; /*!< (@ 0x00000028) Channel1 source address register */ + + struct { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR1_f; + } ; + + union { + __IOM uint32_t DSTADDR1; /*!< (@ 0x0000002C) Channel1 destination address register */ + + struct { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR1_f; + } ; + + union { + __IOM uint32_t TRIG1; /*!< (@ 0x00000030) Channel1 trigger register */ + + struct { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG1_f; + } ; + + union { + __IOM uint32_t CCNT1; /*!< (@ 0x00000034) Channel1 trigger register */ + + struct { + __IOM uint32_t CCNT : 16; /*!< [15..0] desc CCNT */ + __IOM uint32_t CREPEAT : 4; /*!< [19..16] desc CREPEAT */ + } CCNT1_f; + } ; + + union { + __IM uint32_t CSRCADDR1; /*!< (@ 0x00000038) Channel1 source address register */ + + struct { + __IM uint32_t CSRCADDR : 32; /*!< [31..0] desc CSRCADDR */ + } CSRCADDR1_f; + } ; + + union { + __IM uint32_t CDSTADDR1; /*!< (@ 0x0000003C) Channel1 destination address register */ + + struct { + __IM uint32_t CDSTADDR : 32; /*!< [31..0] desc CDSTADDR */ + } CDSTADDR1_f; + } ; + + union { + __IOM uint32_t CSR2; /*!< (@ 0x00000040) Channel1 control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IOM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + __IOM uint32_t RESTART : 1; /*!< [11..11] desc RESTART */ + __IM uint32_t TC : 1; /*!< [12..12] desc TC */ + __IM uint32_t TE : 1; /*!< [13..13] desc TE */ + __IOM uint32_t SRCLOAD : 1; /*!< [14..14] desc SRCLOAD */ + __IOM uint32_t DSTLOAD : 1; /*!< [15..15] desc DSTLOAD */ + } CSR2_f; + } ; + + union { + __IOM uint32_t CNT2; /*!< (@ 0x00000044) Channel1 counter register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT2_f; + } ; + + union { + __IOM uint32_t SRCADDR2; /*!< (@ 0x00000048) Channel1 source address register */ + + struct { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR2_f; + } ; + + union { + __IOM uint32_t DSTADDR2; /*!< (@ 0x0000004C) Channel1 destination address register */ + + struct { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR2_f; + } ; + + union { + __IOM uint32_t TRIG2; /*!< (@ 0x00000050) Channel1 trigger register */ + + struct { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG2_f; + } ; + + union { + __IOM uint32_t CCNT2; /*!< (@ 0x00000054) Channel1 trigger register */ + + struct { + __IOM uint32_t CCNT : 16; /*!< [15..0] desc CCNT */ + __IOM uint32_t CREPEAT : 4; /*!< [19..16] desc CREPEAT */ + } CCNT2_f; + } ; + + union { + __IM uint32_t CSRCADDR2; /*!< (@ 0x00000058) Channel1 source address register */ + + struct { + __IM uint32_t CSRCADDR : 32; /*!< [31..0] desc CSRCADDR */ + } CSRCADDR2_f; + } ; + + union { + __IM uint32_t CDSTADDR2; /*!< (@ 0x0000005C) Channel1 destination address register */ + + struct { + __IM uint32_t CDSTADDR : 32; /*!< [31..0] desc CDSTADDR */ + } CDSTADDR2_f; + } ; + + union { + __IOM uint32_t CSR3; /*!< (@ 0x00000060) Channel1 control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IOM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + __IOM uint32_t RESTART : 1; /*!< [11..11] desc RESTART */ + __IM uint32_t TC : 1; /*!< [12..12] desc TC */ + __IM uint32_t TE : 1; /*!< [13..13] desc TE */ + __IOM uint32_t SRCLOAD : 1; /*!< [14..14] desc SRCLOAD */ + __IOM uint32_t DSTLOAD : 1; /*!< [15..15] desc DSTLOAD */ + } CSR3_f; + } ; + + union { + __IOM uint32_t CNT3; /*!< (@ 0x00000064) Channel1 counter register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT3_f; + } ; + + union { + __IOM uint32_t SRCADDR3; /*!< (@ 0x00000068) Channel1 source address register */ + + struct { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR3_f; + } ; + + union { + __IOM uint32_t DSTADDR3; /*!< (@ 0x0000006C) Channel1 destination address register */ + + struct { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR3_f; + } ; + + union { + __IOM uint32_t TRIG3; /*!< (@ 0x00000070) Channel1 trigger register */ + + struct { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG3_f; + } ; + + union { + __IOM uint32_t CCNT3; /*!< (@ 0x00000074) Channel1 trigger register */ + + struct { + __IOM uint32_t CCNT : 16; /*!< [15..0] desc CCNT */ + __IOM uint32_t CREPEAT : 4; /*!< [19..16] desc CREPEAT */ + } CCNT3_f; + } ; + + union { + __IM uint32_t CSRCADDR3; /*!< (@ 0x00000078) Channel1 source address register */ + + struct { + __IM uint32_t CSRCADDR : 32; /*!< [31..0] desc CSRCADDR */ + } CSRCADDR3_f; + } ; + + union { + __IM uint32_t CDSTADDR3; /*!< (@ 0x0000007C) Channel1 destination address register */ + + struct { + __IM uint32_t CDSTADDR : 32; /*!< [31..0] desc CDSTADDR */ + } CDSTADDR3_f; + } ; + + union { + __IOM uint32_t CSR4; /*!< (@ 0x00000080) Channel1 control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IOM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + __IOM uint32_t RESTART : 1; /*!< [11..11] desc RESTART */ + __IM uint32_t TC : 1; /*!< [12..12] desc TC */ + __IM uint32_t TE : 1; /*!< [13..13] desc TE */ + __IOM uint32_t SRCLOAD : 1; /*!< [14..14] desc SRCLOAD */ + __IOM uint32_t DSTLOAD : 1; /*!< [15..15] desc DSTLOAD */ + } CSR4_f; + } ; + + union { + __IOM uint32_t CNT4; /*!< (@ 0x00000084) Channel1 counter register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT4_f; + } ; + + union { + __IOM uint32_t SRCADDR4; /*!< (@ 0x00000088) Channel1 source address register */ + + struct { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR4_f; + } ; + + union { + __IOM uint32_t DSTADDR4; /*!< (@ 0x0000008C) Channel1 destination address register */ + + struct { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR4_f; + } ; + + union { + __IOM uint32_t TRIG4; /*!< (@ 0x00000090) Channel1 trigger register */ + + struct { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG4_f; + } ; + + union { + __IOM uint32_t CCNT4; /*!< (@ 0x00000094) Channel1 trigger register */ + + struct { + __IOM uint32_t CCNT : 16; /*!< [15..0] desc CCNT */ + __IOM uint32_t CREPEAT : 4; /*!< [19..16] desc CREPEAT */ + } CCNT4_f; + } ; + + union { + __IM uint32_t CSRCADDR4; /*!< (@ 0x00000098) Channel1 source address register */ + + struct { + __IM uint32_t CSRCADDR : 32; /*!< [31..0] desc CSRCADDR */ + } CSRCADDR4_f; + } ; + + union { + __IM uint32_t CDSTADDR4; /*!< (@ 0x0000009C) Channel1 destination address register */ + + struct { + __IM uint32_t CDSTADDR : 32; /*!< [31..0] desc CDSTADDR */ + } CDSTADDR4_f; + } ; +} DMA_TypeDef; /*!< Size = 160 (0xa0) */ + + + +/* =========================================================================================================================== */ +/* ================ DMACHANNEL1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DMA Channel 1 (DMACHANNEL1) + */ + +typedef struct { /*!< (@ 0x40020020) DMACHANNEL1 Structure */ + + union { + __IOM uint32_t CSR; /*!< (@ 0x00000000) Channel1 control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IOM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + __IOM uint32_t RESTART : 1; /*!< [11..11] desc RESTART */ + __IM uint32_t TC : 1; /*!< [12..12] desc TC */ + __IM uint32_t TE : 1; /*!< [13..13] desc TE */ + __IOM uint32_t SRCLOAD : 1; /*!< [14..14] desc SRCLOAD */ + __IOM uint32_t DSTLOAD : 1; /*!< [15..15] desc DSTLOAD */ + } CSR_f; + } ; + + union { + __IOM uint32_t CNT; /*!< (@ 0x00000004) Channel1 counter register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT_f; + } ; + + union { + __IOM uint32_t SRCADDR; /*!< (@ 0x00000008) Channel1 source address register */ + + struct { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR_f; + } ; + + union { + __IOM uint32_t DSTADDR; /*!< (@ 0x0000000C) Channel1 destination address register */ + + struct { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR_f; + } ; + + union { + __IOM uint32_t TRIG; /*!< (@ 0x00000010) Channel1 trigger register */ + + struct { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG_f; + } ; + + union { + __IOM uint32_t CCNT; /*!< (@ 0x00000014) Channel1 trigger register */ + + struct { + __IOM uint32_t CCNT : 16; /*!< [15..0] desc CCNT */ + __IOM uint32_t CREPEAT : 4; /*!< [19..16] desc CREPEAT */ + } CCNT_f; + } ; + + union { + __IM uint32_t CSRCADDR; /*!< (@ 0x00000018) Channel1 source address register */ + + struct { + __IM uint32_t CSRCADDR : 32; /*!< [31..0] desc CSRCADDR */ + } CSRCADDR_f; + } ; + + union { + __IM uint32_t CDSTADDR; /*!< (@ 0x0000001C) Channel1 destination address register */ + + struct { + __IM uint32_t CDSTADDR : 32; /*!< [31..0] desc CDSTADDR */ + } CDSTADDR_f; + } ; +} DMACHANNEL_TypeDef; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ EAU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc EAU (EAU) + */ + +typedef struct { /*!< (@ 0x40023200) EAU Structure */ + + union { + __IOM uint32_t CSR; /*!< (@ 0x00000000) desc CSR */ + + struct { + __IOM uint32_t MODE : 2; /*!< [1..0] desc MODE */ + __IM uint32_t OVR : 1; /*!< [2..2] desc OVR */ + __IM uint32_t ZERO : 1; /*!< [3..3] desc ZERO */ + __IM uint32_t BUSY : 1; /*!< [4..4] desc BUSY */ + } CSR_f; + } ; + + union { + __IOM uint32_t DIVIDEND; /*!< (@ 0x00000004) desc DIVIDEND */ + + struct { + __IOM uint32_t DIVIDEND : 32; /*!< [31..0] desc DIVIDEND */ + } DIVIDEND_f; + } ; + + union { + __IOM uint32_t DIVISOR; /*!< (@ 0x00000008) desc DIVISOR */ + + struct { + __IOM uint32_t DIVISOR : 32; /*!< [31..0] desc DIVISOR */ + } DIVISOR_f; + } ; + + union { + __IM uint32_t QUOTIENT; /*!< (@ 0x0000000C) desc QUOTIENT */ + + struct { + __IM uint32_t QUOTIENT : 32; /*!< [31..0] desc QUOTIENT */ + } QUOTIENT_f; + } ; + + union { + __IM uint32_t REMAINDER; /*!< (@ 0x00000010) desc REMAINDER */ + + struct { + __IM uint32_t REMAINDER : 32; /*!< [31..0] desc REMAINDER */ + } REMAINDER_f; + } ; +} EAU_TypeDef; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ FLASH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc FLASH (FLASH) + */ + +typedef struct { /*!< (@ 0x40022000) FLASH Structure */ + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t MODE : 2; /*!< [1..0] desc MODE */ + __IM uint32_t : 3; + __IM uint32_t SECURITY : 2; /*!< [6..5] desc SECURITY */ + __IM uint32_t : 9; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000004) Control register2 */ + + struct { + __IOM uint32_t WAIT : 3; /*!< [2..0] desc WAIT */ + __IOM uint32_t FETCH : 1; /*!< [3..3] desc FETCH */ + __IOM uint32_t CACHE : 1; /*!< [4..4] desc CACHE */ + __IOM uint32_t CACHEINVALID : 1; /*!< [5..5] desc CACHEINVALID */ + __IM uint32_t : 10; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR2_f; + } ; + + union { + __IOM uint32_t PAGELOCK; /*!< (@ 0x00000008) Page Write Erase Lock */ + + struct { + __IOM uint32_t LOCK0 : 1; /*!< [0..0] Page0 - 7 */ + __IOM uint32_t LOCK1 : 1; /*!< [1..1] Page8 - 15 */ + __IOM uint32_t LOCK2 : 1; /*!< [2..2] Page16 - 23 */ + __IOM uint32_t LOCK3 : 1; /*!< [3..3] Page24 - 31 */ + __IOM uint32_t LOCK4 : 1; /*!< [4..4] Page32 - 39 */ + __IOM uint32_t LOCK5 : 1; /*!< [5..5] Page40 - 47 */ + __IOM uint32_t LOCK6 : 1; /*!< [6..6] Page48 - 55 */ + __IOM uint32_t LOCK7 : 1; /*!< [7..7] Page56 - 63 */ + __IOM uint32_t LOCK8 : 1; /*!< [8..8] Page64 - 71 */ + __IOM uint32_t LOCK9 : 1; /*!< [9..9] Page72 - 79 */ + __IOM uint32_t LOCK10 : 1; /*!< [10..10] Page80 - 87 */ + __IOM uint32_t LOCK11 : 1; /*!< [11..11] Page88 - 95 */ + __IOM uint32_t LOCK12 : 1; /*!< [12..12] Page96 - 103 */ + __IOM uint32_t LOCK13 : 1; /*!< [13..13] Page104 - 111 */ + __IOM uint32_t LOCK14 : 1; /*!< [14..14] Page112 - 119 */ + __IOM uint32_t LOCK15 : 1; /*!< [15..15] Page120 - 127 */ + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } PAGELOCK_f; + } ; + __IM uint32_t RESERVED[5]; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000020) Interrupt enable register */ + + struct { + __IOM uint32_t PC : 1; /*!< [0..0] desc PC */ + __IOM uint32_t PAGELOCK : 1; /*!< [1..1] desc PAGELOCK */ + __IOM uint32_t SDKERR : 1; /*!< [2..2] desc SDKERR */ + __IOM uint32_t CACHEON : 1; /*!< [3..3] desc CACHEON */ + __IOM uint32_t PROG : 1; /*!< [4..4] desc PROG */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000024) Interrupt status register */ + + struct { + __IM uint32_t PC : 1; /*!< [0..0] desc PC */ + __IM uint32_t PAGELOCK : 1; /*!< [1..1] desc PAGELOCK */ + __IM uint32_t SDKERR : 1; /*!< [2..2] desc SDKERR */ + __IM uint32_t CACHEON : 1; /*!< [3..3] desc CACHEON */ + __IM uint32_t PROG : 1; /*!< [4..4] desc PROG */ + __IM uint32_t BUSY : 1; /*!< [5..5] desc BUSY */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000028) Interrupt flag clear register */ + + struct { + __IOM uint32_t PC : 1; /*!< [0..0] desc PC */ + __IOM uint32_t PAGELOCK : 1; /*!< [1..1] desc PAGELOCK */ + __IOM uint32_t SDKERR : 1; /*!< [2..2] desc SDKERR */ + __IOM uint32_t CACHEON : 1; /*!< [3..3] desc CACHEON */ + __IOM uint32_t PROG : 1; /*!< [4..4] desc PROG */ + } ICR_f; + } ; + __IM uint32_t RESERVED1[17]; + + union { + __IM uint32_t SDKCFR; /*!< (@ 0x00000070) SDK config register */ + + struct { + __IM uint32_t START : 7; /*!< [6..0] desc START */ + uint32_t : 1; + __IM uint32_t END : 7; /*!< [14..8] desc END */ + } SDKCFR_f; + } ; +} FLASH_TypeDef; /*!< Size = 116 (0x74) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc GPIOA (GPIOA) + */ + +typedef struct { /*!< (@ 0x48000000) GPIOA Structure */ + + union { + __IOM uint32_t DIR; /*!< (@ 0x00000000) desc DIR */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } DIR_f; + } ; + + union { + __IOM uint32_t OPENDRAIN; /*!< (@ 0x00000004) desc OPENDRAIN */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } OPENDRAIN_f; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t PUR; /*!< (@ 0x00000010) desc PUR */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } PUR_f; + } ; + + union { + __IOM uint32_t AFRH; /*!< (@ 0x00000014) desc AFRH */ + + struct { + __IOM uint32_t PIN8 : 4; /*!< [2..0] desc AFR8 */ + __IOM uint32_t PIN9 : 4; /*!< [6..4] desc AFR9 */ + __IOM uint32_t PIN10 : 4; /*!< [10..8] desc AFR10 */ + __IOM uint32_t PIN11 : 4; /*!< [14..12] desc AFR11 */ + __IOM uint32_t PIN12 : 4; /*!< [18..16] desc AFR12 */ + __IOM uint32_t PIN13 : 4; /*!< [22..20] desc AFR13 */ + __IOM uint32_t PIN14 : 4; /*!< [26..24] desc AFR14 */ + __IOM uint32_t PIN15 : 4; /*!< [30..28] desc AFR15 */ + } AFRH_f; + } ; + + union { + __IOM uint32_t AFRL; /*!< (@ 0x00000018) desc AFRL */ + + struct { + __IOM uint32_t PIN0 : 4; /*!< [2..0] desc AFR0 */ + __IOM uint32_t PIN1 : 4; /*!< [6..4] desc AFR1 */ + __IOM uint32_t PIN2 : 4; /*!< [10..8] desc AFR2 */ + __IOM uint32_t PIN3 : 4; /*!< [14..12] desc AFR3 */ + __IOM uint32_t PIN4 : 4; /*!< [18..16] desc AFR4 */ + __IOM uint32_t PIN5 : 4; /*!< [22..20] desc AFR5 */ + __IOM uint32_t PIN6 : 4; /*!< [26..24] desc AFR6 */ + __IOM uint32_t PIN7 : 4; /*!< [30..28] desc AFR7 */ + } AFRL_f; + } ; + + union { + __IOM uint32_t ANALOG; /*!< (@ 0x0000001C) desc ANALOG */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ANALOG_f; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t RISEIE; /*!< (@ 0x00000024) Interrupt enable register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } RISEIE_f; + } ; + + union { + __IOM uint32_t FALLIE; /*!< (@ 0x00000028) Interrupt enable register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } FALLIE_f; + } ; + __IM uint32_t RESERVED2[2]; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000034) Interrupt status register */ + + struct { + __IM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000038) Interrupt flag clear register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ICR_f; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t FILTER; /*!< (@ 0x00000040) desc FILTER */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + __IOM uint32_t FLTCLK : 3; /*!< [18..16] desc FLTCLK */ + } FILTER_f; + } ; + __IM uint32_t RESERVED4[3]; + + union { + __IM uint32_t IDR; /*!< (@ 0x00000050) desc IDR */ + + struct { + __IM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } IDR_f; + } ; + + union { + __IOM uint32_t ODR; /*!< (@ 0x00000054) desc ODR */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ODR_f; + } ; + + union { + __IOM uint32_t BRR; /*!< (@ 0x00000058) desc BRR */ + + struct { + __IOM uint32_t BRR0 : 1; /*!< [0..0] desc BRR0 */ + __IOM uint32_t BRR1 : 1; /*!< [1..1] desc BRR1 */ + __IOM uint32_t BRR2 : 1; /*!< [2..2] desc BRR2 */ + __IOM uint32_t BRR3 : 1; /*!< [3..3] desc BRR3 */ + __IOM uint32_t BRR4 : 1; /*!< [4..4] desc BRR4 */ + __IOM uint32_t BRR5 : 1; /*!< [5..5] desc BRR5 */ + __IOM uint32_t BRR6 : 1; /*!< [6..6] desc BRR6 */ + __IOM uint32_t BRR7 : 1; /*!< [7..7] desc BRR7 */ + __IOM uint32_t BRR8 : 1; /*!< [8..8] desc BRR8 */ + __IOM uint32_t BRR9 : 1; /*!< [9..9] desc BRR9 */ + __IOM uint32_t BRR10 : 1; /*!< [10..10] desc BRR10 */ + __IOM uint32_t BRR11 : 1; /*!< [11..11] desc BRR11 */ + __IOM uint32_t BRR12 : 1; /*!< [12..12] desc BRR12 */ + __IOM uint32_t BRR13 : 1; /*!< [13..13] desc BRR13 */ + __IOM uint32_t BRR14 : 1; /*!< [14..14] desc BRR14 */ + __IOM uint32_t BRR15 : 1; /*!< [15..15] desc BRR15 */ + } BRR_f; + } ; + + union { + __IOM uint32_t BSRR; /*!< (@ 0x0000005C) desc BSRR */ + + struct { + __IOM uint32_t BSS0 : 1; /*!< [0..0] desc BSS0 */ + __IOM uint32_t BSS1 : 1; /*!< [1..1] desc BSS1 */ + __IOM uint32_t BSS2 : 1; /*!< [2..2] desc BSS2 */ + __IOM uint32_t BSS3 : 1; /*!< [3..3] desc BSS3 */ + __IOM uint32_t BSS4 : 1; /*!< [4..4] desc BSS4 */ + __IOM uint32_t BSS5 : 1; /*!< [5..5] desc BSS5 */ + __IOM uint32_t BSS6 : 1; /*!< [6..6] desc BSS6 */ + __IOM uint32_t BSS7 : 1; /*!< [7..7] desc BSS7 */ + __IOM uint32_t BSS8 : 1; /*!< [8..8] desc BSS8 */ + __IOM uint32_t BSS9 : 1; /*!< [9..9] desc BSS9 */ + __IOM uint32_t BSS10 : 1; /*!< [10..10] desc BSS10 */ + __IOM uint32_t BSS11 : 1; /*!< [11..11] desc BSS11 */ + __IOM uint32_t BSS12 : 1; /*!< [12..12] desc BSS12 */ + __IOM uint32_t BSS13 : 1; /*!< [13..13] desc BSS13 */ + __IOM uint32_t BSS14 : 1; /*!< [14..14] desc BSS14 */ + __IOM uint32_t BSS15 : 1; /*!< [15..15] desc BSS15 */ + __IOM uint32_t BRR0 : 1; /*!< [16..16] desc BRR0 */ + __IOM uint32_t BRR1 : 1; /*!< [17..17] desc BRR1 */ + __IOM uint32_t BRR2 : 1; /*!< [18..18] desc BRR2 */ + __IOM uint32_t BRR3 : 1; /*!< [19..19] desc BRR3 */ + __IOM uint32_t BRR4 : 1; /*!< [20..20] desc BRR4 */ + __IOM uint32_t BRR5 : 1; /*!< [21..21] desc BRR5 */ + __IOM uint32_t BRR6 : 1; /*!< [22..22] desc BRR6 */ + __IOM uint32_t BRR7 : 1; /*!< [23..23] desc BRR7 */ + __IOM uint32_t BRR8 : 1; /*!< [24..24] desc BRR8 */ + __IOM uint32_t BRR9 : 1; /*!< [25..25] desc BRR9 */ + __IOM uint32_t BRR10 : 1; /*!< [26..26] desc BRR10 */ + __IOM uint32_t BRR11 : 1; /*!< [27..27] desc BRR11 */ + __IOM uint32_t BRR12 : 1; /*!< [28..28] desc BRR12 */ + __IOM uint32_t BRR13 : 1; /*!< [29..29] desc BRR13 */ + __IOM uint32_t BRR14 : 1; /*!< [30..30] desc BRR14 */ + __IOM uint32_t BRR15 : 1; /*!< [31..31] desc BRR15 */ + } BSRR_f; + } ; + + union { + __IOM uint32_t TOG; /*!< (@ 0x00000060) desc TOG */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } TOG_f; + } ; +} GPIO_TypeDef; /*!< Size = 100 (0x64) */ + + + +/* =========================================================================================================================== */ +/* ================ GTIM1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Timer 1 (GTIM1) + */ + +typedef struct { /*!< (@ 0x40001800) GTIM1 Structure */ + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] desc CEN */ + __IOM uint32_t UDIS : 1; /*!< [1..1] desc UDIS */ + __IOM uint32_t URS : 1; /*!< [2..2] desc URS */ + __IOM uint32_t OPM : 1; /*!< [3..3] desc OPM */ + __IOM uint32_t DIR : 1; /*!< [4..4] desc DIR */ + __IOM uint32_t CMS : 2; /*!< [6..5] desc CMS */ + __IOM uint32_t ARPE : 1; /*!< [7..7] desc ARPE */ + __IOM uint32_t CKD : 2; /*!< [9..8] desc CKD */ + __IM uint32_t : 1; + __IOM uint32_t UIFREMAP : 1; /*!< [11..11] desc UIFREMAP */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000004) Control register2 */ + + struct { + __IM uint32_t : 3; + __IOM uint32_t CCDS : 1; /*!< [3..3] desc CCDS */ + __IOM uint32_t MMS : 3; /*!< [6..4] desc MMS */ + __IOM uint32_t TI1S : 1; /*!< [7..7] desc TI1S */ + __IM uint32_t : 17; + __IOM uint32_t MMSH : 2; /*!< [26..25] desc MMSH */ + } CR2_f; + } ; + + union { + __IOM uint32_t SMCR; /*!< (@ 0x00000008) Slave Mode control register */ + + struct { + __IOM uint32_t SMS : 3; /*!< [2..0] desc SMS */ + __IOM uint32_t OCCS : 1; /*!< [3..3] desc OCCS */ + __IOM uint32_t TS : 3; /*!< [6..4] desc TS */ + __IOM uint32_t MSM : 1; /*!< [7..7] desc MSM */ + __IOM uint32_t ETF : 4; /*!< [11..8] desc ETF */ + __IOM uint32_t ETPS : 2; /*!< [13..12] desc ETPS */ + __IOM uint32_t ECE : 1; /*!< [14..14] desc ECE */ + __IOM uint32_t ETP : 1; /*!< [15..15] desc ETP */ + __IOM uint32_t SMSH : 1; /*!< [16..16] desc SMSH */ + __IM uint32_t : 3; + __IOM uint32_t TSH : 2; /*!< [21..20] desc TSH */ + __IM uint32_t : 2; + __IOM uint32_t SMSPE : 1; /*!< [24..24] desc SMSPE */ + __IOM uint32_t SMSPS : 1; /*!< [25..25] desc SMSPS */ + } SMCR_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x0000000C) Interrupt control register */ + + struct { + __IOM uint32_t UIE : 1; /*!< [0..0] desc UIE */ + __IOM uint32_t CC1IE : 1; /*!< [1..1] desc CC1IE */ + __IOM uint32_t CC2IE : 1; /*!< [2..2] desc CC2IE */ + __IOM uint32_t CC3IE : 1; /*!< [3..3] desc CC3IE */ + __IOM uint32_t CC4IE : 1; /*!< [4..4] desc CC4IE */ + __IM uint32_t : 1; + __IOM uint32_t TIE : 1; /*!< [6..6] desc TIE */ + __IM uint32_t : 1; + __IOM uint32_t UDE : 1; /*!< [8.8] desc UDE */ + __IOM uint32_t CC1DE : 1; /*!< [9.9] desc CC1DE */ + __IOM uint32_t CC2DE : 1; /*!< [10..10] desc CC2DE */ + __IOM uint32_t CC3DE : 1; /*!< [11..11] desc CC3DE */ + __IOM uint32_t CC4DE : 1; /*!< [12..12] desc CC4DE */ + __IM uint32_t : 1; + __IOM uint32_t TDE : 1; /*!< [14..14] desc TDE */ + __IM uint32_t : 5; + __IOM uint32_t IDXIE : 1; /*!< [20..20] desc IDXIE */ + __IOM uint32_t DIRIE : 1; /*!< [21..21] desc DIRIE */ + __IOM uint32_t IERRIE : 1; /*!< [22..22] desc IERRIE */ + __IOM uint32_t TERRIE : 1; /*!< [23..23] desc TERRIE */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000010) Interrupt status register */ + + struct { + __IM uint32_t UIF : 1; /*!< [0..0] desc UIF */ + __IM uint32_t CC1IF : 1; /*!< [1..1] desc CC1IF */ + __IM uint32_t CC2IF : 1; /*!< [2..2] desc CC2IF */ + __IM uint32_t CC3IF : 1; /*!< [3..3] desc CC3IF */ + __IM uint32_t CC4IF : 1; /*!< [4..4] desc CC4IF */ + __IM uint32_t : 1; + __IM uint32_t TIF : 1; /*!< [6..6] desc TIF */ + __IM uint32_t : 2; + __IM uint32_t CC1OF : 1; /*!< [9..9] desc CC1OF */ + __IM uint32_t CC2OF : 1; /*!< [10..10] desc CC2OF */ + __IM uint32_t CC3OF : 1; /*!< [11..11] desc CC3OF */ + __IM uint32_t CC4OF : 1; /*!< [12..12] desc CC4OF */ + __IM uint32_t : 7; + __IM uint32_t IDXF : 1; /*!< [20..20] desc IDXF */ + __IM uint32_t DIRF : 1; /*!< [21..21] desc DIRF */ + __IM uint32_t IERRF : 1; /*!< [22..22] desc IERRF */ + __IM uint32_t TERRF : 1; /*!< [23..23] desc TERRF */ + } ISR_f; + } ; + + union { + __IOM uint32_t EGR; /*!< (@ 0x00000014) Event Generate register */ + + struct { + __IOM uint32_t UG : 1; /*!< [0..0] desc UG */ + __IOM uint32_t CC1G : 1; /*!< [1..1] desc CC1G */ + __IOM uint32_t CC2G : 1; /*!< [2..2] desc CC2G */ + __IOM uint32_t CC3G : 1; /*!< [3..3] desc CC3G */ + __IOM uint32_t CC4G : 1; /*!< [4..4] desc CC4G */ + __IM uint32_t : 1; + __IOM uint32_t TG : 1; /*!< [6..6] desc TG */ + } EGR_f; + } ; + + union { + union { + __IOM uint32_t CCMR1CAP; /*!< (@ 0x00000018) Capture control Register1 */ + + struct { + __IOM uint32_t CC1S : 2; /*!< [1..0] desc CC1S */ + __IOM uint32_t IC1PSC : 2; /*!< [3..2] desc IC1PSC */ + __IOM uint32_t IC1F : 4; /*!< [7..4] desc IC1F */ + __IOM uint32_t CC2S : 2; /*!< [9..8] desc CC2S */ + __IOM uint32_t IC2PSC : 2; /*!< [11..10] desc IC2PSC */ + __IOM uint32_t IC2F : 4; /*!< [15..12] desc IC2F */ + } CCMR1CAP_f; + } ; + + union { + __IOM uint32_t CCMR1CMP; /*!< (@ 0x00000018) Compare control Register1 */ + + struct { + __IOM uint32_t CC1S : 2; /*!< [1..0] desc CC1S */ + __IOM uint32_t OC1FE : 1; /*!< [2..2] desc OC1FE */ + __IOM uint32_t OC1PE : 1; /*!< [3..3] desc OC1PE */ + __IOM uint32_t OC1M : 3; /*!< [6..4] desc OC1M */ + __IOM uint32_t OC1CE : 1; /*!< [7..7] desc OC1CE */ + __IOM uint32_t CC2S : 2; /*!< [9..8] desc CC2S */ + __IOM uint32_t OC2FE : 1; /*!< [10..10] desc OC2FE */ + __IOM uint32_t OC2PE : 1; /*!< [11..11] desc OC2PE */ + __IOM uint32_t OC2M : 3; /*!< [14..12] desc OC2M */ + __IOM uint32_t OC2CE : 1; /*!< [15..15] desc OC2CE */ + __IOM uint32_t OC1MH : 1; /*!< [16..16] desc OC1MH */ + __IM uint32_t : 7; + __IOM uint32_t OC2MH : 1; /*!< [24..24] desc OC2MH */ + } CCMR1CMP_f; + } ; + }; + + union { + union { + __IOM uint32_t CCMR2CAP; /*!< (@ 0x0000001C) Capture control Register2 */ + + struct { + __IOM uint32_t CC3S : 2; /*!< [1..0] desc CC3S */ + __IOM uint32_t IC3PSC : 2; /*!< [3..2] desc IC3PSC */ + __IOM uint32_t IC3F : 4; /*!< [7..4] desc IC3F */ + __IOM uint32_t CC4S : 2; /*!< [9..8] desc CC4S */ + __IOM uint32_t IC4PSC : 2; /*!< [11..10] desc IC4PSC */ + __IOM uint32_t IC4F : 4; /*!< [15..12] desc IC4F */ + } CCMR2CAP_f; + } ; + + union { + __IOM uint32_t CCMR2CMP; /*!< (@ 0x0000001C) Compare control Register2 */ + + struct { + __IOM uint32_t CC3S : 2; /*!< [1..0] desc CC3S */ + __IOM uint32_t OC3FE : 1; /*!< [2..2] desc OC3FE */ + __IOM uint32_t OC3PE : 1; /*!< [3..3] desc OC3PE */ + __IOM uint32_t OC3M : 3; /*!< [6..4] desc OC3M */ + __IOM uint32_t OC3CE : 1; /*!< [7..7] desc OC3CE */ + __IOM uint32_t CC4S : 2; /*!< [9..8] desc CC4S */ + __IOM uint32_t OC4FE : 1; /*!< [10..10] desc OC4FE */ + __IOM uint32_t OC4PE : 1; /*!< [11..11] desc OC4PE */ + __IOM uint32_t OC4M : 3; /*!< [14..12] desc OC4M */ + __IOM uint32_t OC4CE : 1; /*!< [15..15] desc OC4CE */ + __IOM uint32_t OC3MH : 1; /*!< [16..16] desc OC3MH */ + __IM uint32_t : 7; + __IOM uint32_t OC4MH : 1; /*!< [24..24] desc OC4MH */ + } CCMR2CMP_f; + } ; + }; + + union { + __IOM uint32_t CCER; /*!< (@ 0x00000020) Capture compare Enable Register */ + + struct { + __IOM uint32_t CC1E : 1; /*!< [0..0] desc CC1E */ + __IOM uint32_t CC1P : 1; /*!< [1..1] desc CC1P */ + __IM uint32_t : 1; + __IOM uint32_t CC1NP : 1; /*!< [3..3] desc CC1NP */ + __IOM uint32_t CC2E : 1; /*!< [4..4] desc CC2E */ + __IOM uint32_t CC2P : 1; /*!< [5..5] desc CC2P */ + __IM uint32_t : 1; + __IOM uint32_t CC2NP : 1; /*!< [7..7] desc CC2NP */ + __IOM uint32_t CC3E : 1; /*!< [8..8] desc CC3E */ + __IOM uint32_t CC3P : 1; /*!< [9..9] desc CC3P */ + __IM uint32_t : 1; + __IOM uint32_t CC3NP : 1; /*!< [11..11] desc CC3NP */ + __IOM uint32_t CC4E : 1; /*!< [12..12] desc CC4E */ + __IOM uint32_t CC4P : 1; /*!< [13..13] desc CC4P */ + __IM uint32_t : 1; + __IOM uint32_t CC4NP : 1; /*!< [15..15] desc CC4NP */ + } CCER_f; + } ; + + union { + __IOM uint32_t CNT; /*!< (@ 0x00000024) Counter Register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IM uint32_t : 15; + __IM uint32_t UIFCPY : 1; /*!< [31..31] desc UIFCPY */ + } CNT_f; + } ; + + union { + __IOM uint32_t PSC; /*!< (@ 0x00000028) Prescaler Control Register */ + + struct { + __IOM uint32_t PSC : 16; /*!< [15..0] desc PSC */ + } PSC_f; + } ; + + union { + __IOM uint32_t ARR; /*!< (@ 0x0000002C) Auto Reload Register */ + + struct { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } ARR_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t CCR1; /*!< (@ 0x00000034) Capture control Register1 */ + + struct { + __IOM uint32_t CCR1 : 16; /*!< [15..0] desc CCR1 */ + } CCR1_f; + } ; + + union { + __IOM uint32_t CCR2; /*!< (@ 0x00000038) Capture control Register2 */ + + struct { + __IOM uint32_t CCR2 : 16; /*!< [15..0] desc CCR2 */ + } CCR2_f; + } ; + + union { + __IOM uint32_t CCR3; /*!< (@ 0x0000003C) Capture control Register3 */ + + struct { + __IOM uint32_t CCR3 : 16; /*!< [15..0] desc CCR3 */ + } CCR3_f; + } ; + + union { + __IOM uint32_t CCR4; /*!< (@ 0x00000040) Capture control Register4 */ + + struct { + __IOM uint32_t CCR4 : 16; /*!< [15..0] desc CCR4 */ + } CCR4_f; + } ; + __IM uint32_t RESERVED1[5]; + + union { + __IOM uint32_t ECR; /*!< (@ 0x00000058) Encoder control Register */ + + struct { + __IOM uint32_t IE : 1; /*!< [0..0] desc IE */ + __IOM uint32_t IDIR : 2; /*!< [2..1] desc IDIR */ + __IM uint32_t : 2; + __IOM uint32_t FIDX : 1; /*!< [5..5] desc FIDX */ + __IOM uint32_t IPOS : 2; /*!< [7..6] desc IPOS */ + } ECR_f; + } ; + + union { + __IOM uint32_t TISEL; /*!< (@ 0x0000005C) Timer Input Select Register */ + + struct { + __IOM uint32_t TI1SEL : 4; /*!< [3..0] desc TI1SEL */ + __IM uint32_t : 4; + __IOM uint32_t TI2SEL : 4; /*!< [11..8] desc TI2SEL */ + __IM uint32_t : 4; + __IOM uint32_t TI3SEL : 4; /*!< [19..16] desc TI3SEL */ + __IM uint32_t : 4; + __IOM uint32_t TI4SEL : 4; /*!< [27..24] desc TI4SEL */ + } TISEL_f; + } ; + + union { + __IOM uint32_t AF1; /*!< (@ 0x00000060) Alternate function Register1 */ + + struct { + __IM uint32_t : 14; + __IOM uint32_t ETRSEL : 4; /*!< [17..14] desc ETRSEL */ + } AF1_f; + } ; + + union { + __IOM uint32_t AF2; /*!< (@ 0x00000064) Alternate function Register2 */ + + struct { + __IM uint32_t : 16; + __IOM uint32_t OCRSEL : 3; /*!< [18..16] desc OCRSEL */ + } AF2_f; + } ; + __IM uint32_t RESERVED2[2]; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000070) Interrupt flag clear register */ + + struct { + __IOM uint32_t UIF : 1; /*!< [0..0] desc UIF */ + __IOM uint32_t CC1IF : 1; /*!< [1..1] desc CC1IF */ + __IOM uint32_t CC2IF : 1; /*!< [2..2] desc CC2IF */ + __IOM uint32_t CC3IF : 1; /*!< [3..3] desc CC3IF */ + __IOM uint32_t CC4IF : 1; /*!< [4..4] desc CC4IF */ + __IM uint32_t : 1; + __IOM uint32_t TIF : 1; /*!< [6..6] desc TIF */ + __IM uint32_t : 2; + __IOM uint32_t CC1OF : 1; /*!< [9..9] desc CC1OF */ + __IOM uint32_t CC2OF : 1; /*!< [10..10] desc CC2OF */ + __IOM uint32_t CC3OF : 1; /*!< [11..11] desc CC3OF */ + __IOM uint32_t CC4OF : 1; /*!< [12..12] desc CC4OF */ + __IM uint32_t : 7; + __IOM uint32_t IDXF : 1; /*!< [20..20] desc IDXF */ + __IOM uint32_t DIRF : 1; /*!< [21..21] desc DIRF */ + __IOM uint32_t IERRF : 1; /*!< [22..22] desc IERRF */ + __IOM uint32_t TERRF : 1; /*!< [23..23] desc TERRF */ + } ICR_f; + } ; +} GTIM_TypeDef; /*!< Size = 116 (0x74) */ + + + +/* =========================================================================================================================== */ +/* ================ HALLTIM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief HALL Timer (HALLTIM) + */ + +typedef struct { /*!< (@ 0x40006400) HALLTIM Structure */ + + union { + __IOM uint32_t CR; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t FLT1EN : 1; /*!< [1..1] desc FLT1EN */ + __IOM uint32_t DIV : 2; /*!< [3..2] desc DIV */ + __IOM uint32_t MMS : 3; /*!< [6..4] desc MMS */ + __IM uint32_t : 1; + __IOM uint32_t FLT2LEN : 15; /*!< [22..8] desc FLT2LEN */ + __IOM uint32_t SOFTCAP : 1; /*!< [23..23] desc SOFTCAP */ + } CR_f; + } ; + + union { + __IOM uint32_t DIER; /*!< (@ 0x00000004) DMA and Interrupt register2 */ + + struct { + __IOM uint32_t CAPIE : 1; /*!< [0..0] desc CAPIE */ + __IOM uint32_t OVIE : 1; /*!< [1..1] desc OVIE */ + __IOM uint32_t MATCHIE : 1; /*!< [2..2] desc MATCHIE */ + __IM uint32_t : 1; + __IOM uint32_t CAPDMA : 1; /*!< [4..4] desc CAPDMA */ + __IOM uint32_t OVDMA : 1; /*!< [5..5] desc OVDMA */ + __IOM uint32_t MATCHDMA : 1; /*!< [6..6] desc MATCHDMA */ + __IOM uint32_t SOFTDMA : 1; /*!< [7..7] desc SOFTDMA */ + } DIER_f; + } ; + + union { + __IOM uint32_t CNT; /*!< (@ 0x00000008) counter register */ + + struct { + __IOM uint32_t DATA : 24; /*!< [23..0] desc CNT */ + } CNT_f; + } ; + + union { + __IOM uint32_t ARR; /*!< (@ 0x0000000C) Auto Reload Register */ + + struct { + __IOM uint32_t DATA : 24; /*!< [23..0] desc ARR */ + } ARR_f; + } ; + + union { + __IM uint32_t WIDTH; /*!< (@ 0x00000010) Width Register */ + + struct { + __IM uint32_t DATA : 24; /*!< [23..0] desc WIDTH */ + } WIDTH_f; + } ; + + union { + __IOM uint32_t CCR; /*!< (@ 0x00000014) Compare control Register */ + + struct { + __IOM uint32_t DATA : 24; /*!< [23..0] desc CCR */ + } CCR_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000018) Interrupt states register */ + + struct { + __IM uint32_t CAPF : 1; /*!< [0..0] desc CAPF */ + __IM uint32_t OV : 1; /*!< [1..1] desc OV */ + __IM uint32_t MATCH : 1; /*!< [2..2] desc MATCH */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x0000001C) Interrupt clean register */ + + struct { + __IOM uint32_t CAPF : 1; /*!< [0..0] desc CHG */ + __IOM uint32_t OVF : 1; /*!< [1..1] desc OV */ + __IOM uint32_t MATCHF : 1; /*!< [2..2] desc MATCH */ + } ICR_f; + } ; + + union { + __IM uint32_t STATE; /*!< (@ 0x00000020) State register */ + + struct { + __IM uint32_t CH1F : 1; /*!< desc CH1F */ + __IM uint32_t CH2F : 1; /*!< desc CH2F */ + __IM uint32_t CH3F : 1; /*!< desc CH3F */ + uint32_t : 1; + __IM uint32_t CH1S : 1; /*!< desc CH1S */ + __IM uint32_t CH2S : 1; /*!< desc CH2S */ + __IM uint32_t CH3S : 1; /*!< desc CH3S */ + } STATE_f; + } ; +} HALLTIM_TypeDef; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ I2C1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc I2C1 (I2C1) + */ +typedef struct { /*!< (@ 0x40005800) I2C1 Structure */ + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t INSEL; /*!< (@ 0x00000008) Input selection register */ + + struct { + __IOM uint32_t SCLINSEL : 3; /*!< [2..0] desc SCLINSEL */ + __IOM uint32_t SDAINSEL : 3; /*!< [5..3] desc SDAINSEL */ + } INSEL_f; + } ; + + union { + __IOM uint32_t MICR; /*!< (@ 0x0000000C) Master Interrupt Flag Clear Register */ + + struct { + uint32_t : 8; + __IOM uint32_t PACKET : 1; /*!< [8..8] desc PACKET */ + __IOM uint32_t STOP : 1; /*!< [9..9] desc STOP */ + __IOM uint32_t NACK : 1; /*!< [10..10] desc NACK */ + __IOM uint32_t ARBI : 1; /*!< [11..11] desc ARBI */ + __IOM uint32_t FIFO : 1; /*!< [12..12] desc FIFO */ + __IOM uint32_t PINLOW : 1; /*!< [13..13] desc PINLOW */ + __IOM uint32_t MATCH : 1; /*!< [14..14] desc MATCH */ + } MICR_f; + } ; + + union { + __IOM uint32_t MCR0; /*!< (@ 0x00000010) Master Control Register0 */ + + struct { + __IOM uint32_t MEN : 1; /*!< [0..0] desc MEN */ + __IOM uint32_t RESET : 1; /*!< [1..1] desc RESET */ + __IOM uint32_t SLEEPEN : 1; /*!< [2..2] desc SLEEPEN */ + __IOM uint32_t DBGEN : 1; /*!< [3..3] desc DBGEN */ + __IM uint32_t : 2; + __IOM uint32_t CLKSRC : 2; /*!< [7..6] desc CLKSRC */ + __IOM uint32_t TXFIFORST : 1; /*!< [8..8] desc TXFIFORST */ + __IOM uint32_t RXFIFORST : 1; /*!< [9..9] desc RXFIFORST */ + } MCR0_f; + } ; + + union { + __IM uint32_t MISR; /*!< (@ 0x00000014) Master Interrupt Status Register */ + + struct { + __IM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + uint32_t : 6; + __IM uint32_t PACKET : 1; /*!< [8..8] desc PACKET */ + __IM uint32_t STOP : 1; /*!< [9..9] desc STOP */ + __IM uint32_t NACK : 1; /*!< [10..10] desc NACK */ + __IM uint32_t ARBI : 1; /*!< [11..11] desc ARBI */ + __IM uint32_t FIFO : 1; /*!< [12..12] desc FIFO */ + __IM uint32_t PINLOW : 1; /*!< [13..13] desc PINLOW */ + __IM uint32_t MATCH : 1; /*!< [14..14] desc MATCH */ + __IM uint32_t : 9; + __IM uint32_t MSTBUSY : 1; /*!< [24..24] desc MSTBUSY */ + __IM uint32_t BUSBUSY : 1; /*!< [25..25] desc BUSBUSY */ + } MISR_f; + } ; + + union { + __IOM uint32_t MIER; /*!< (@ 0x00000018) Master Interrupt Enable Register */ + + struct { + __IOM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IOM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + uint32_t : 6; + __IOM uint32_t PACKET : 1; /*!< [8..8] desc PACKET */ + __IOM uint32_t STOP : 1; /*!< [9..9] desc STOP */ + __IOM uint32_t NACK : 1; /*!< [10..10] desc NACK */ + __IOM uint32_t ARBI : 1; /*!< [11..11] desc ARBI */ + __IOM uint32_t FIFO : 1; /*!< [12..12] desc FIFO */ + __IOM uint32_t PINLOW : 1; /*!< [13..13] desc PINLOW */ + __IOM uint32_t MATCH : 1; /*!< [14..14] desc MATCH */ + } MIER_f; + } ; + + union { + __IOM uint32_t MDER; /*!< (@ 0x0000001C) Master DMA Enable Register */ + + struct { + __IOM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IOM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + } MDER_f; + } ; + + union { + __IOM uint32_t MCR1; /*!< (@ 0x00000020) Master Control Register1 */ + + struct { + __IM uint32_t : 8; + __IOM uint32_t CIRFIFO : 1; /*!< [8..8] desc CIRFIFO */ + __IOM uint32_t RDMO : 1; /*!< [9..9] desc RDMO */ + } MCR1_f; + } ; + + union { + union { + __IOM uint32_t MCR2; /*!< (@ 0x00000024) Master Control Register2 */ + + struct { + __IOM uint32_t PRESCALE : 3; /*!< [2..0] desc PRESCALE */ + __IM uint32_t : 5; + __IOM uint32_t AUTOSTOP : 1; /*!< [8..8] desc AUTOSTOP */ + __IOM uint32_t IGNACK : 1; /*!< [9..9] desc IGNACK */ + __IOM uint32_t TIMECFG : 1; /*!< [10..10] desc TIMECFG */ + __IM uint32_t : 4; + __IOM uint32_t TRGSEL : 1; /*!< [15..15] desc TRGSEL */ + __IOM uint32_t MATCFG : 3; /*!< [18..16] desc MATCFG */ + uint32_t : 5; + __IOM uint32_t PINCFG : 3; /*!< [26..24] desc PINCFG */ + } MCR2_f; + } ; + + union { + __IOM uint32_t SCR2; /*!< (@ 0x00000024) desc SCR2 */ + + struct { + __IM uint32_t : 24; + __IOM uint32_t PINCFG : 3; /*!< [26..24] desc PINCFG */ + } SCR2_f; + } ; + } ; + + union { + __IOM uint32_t MCR3; /*!< (@ 0x00000028) Master Control Register3 */ + + struct { + __IOM uint32_t BUSIDLE : 12; /*!< [11..0] desc BUSIDLE */ + __IM uint32_t : 4; + __IOM uint32_t FLTSCL : 4; /*!< [19..16] desc FLTSCL */ + __IM uint32_t : 4; + __IOM uint32_t FLTSDA : 4; /*!< [27..24] desc FLTSDA */ + } MCR3_f; + } ; + + union { + __IOM uint32_t MCR4; /*!< (@ 0x0000002C) Master Control Register4 */ + + struct { + __IM uint32_t : 8; + __IOM uint32_t PINLOW : 12; /*!< [19..8] desc PINLOW */ + } MCR4_f; + } ; + __IM uint32_t RESERVED1[4]; + + union { + __IOM uint32_t MMATCH; /*!< (@ 0x00000040) Master Match Register */ + + struct { + __IOM uint32_t MATCH0 : 8; /*!< [7..0] desc MATCH0 */ + __IM uint32_t : 8; + __IOM uint32_t MATCH1 : 8; /*!< [23..16] desc MATCH1 */ + } MMATCH_f; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t MCCR; /*!< (@ 0x00000048) Master Clock Control Register0 */ + + struct { + __IOM uint32_t CLKLO : 6; /*!< [5..0] desc CLKLO */ + __IM uint32_t : 2; + __IOM uint32_t CLKHI : 6; /*!< [13..8] desc CLKHI */ + __IM uint32_t : 2; + __IOM uint32_t SETHOLD : 6; /*!< [21..16] desc SETHOLD */ + __IM uint32_t : 2; + __IOM uint32_t DATAVD : 6; /*!< [29..24] desc DATAVD */ + } MCCR_f; + } ; + __IM uint32_t RESERVED3[3]; + + union { + __IOM uint32_t MFIFOCR; /*!< (@ 0x00000058) Master FIFO Control Register */ + + struct { + __IOM uint32_t TXWATER : 1; /*!< [0..0] desc TXWATER */ + __IM uint32_t : 15; + __IOM uint32_t RXWATER : 1; /*!< [16..16] desc RXWATER */ + } MFIFOCR_f; + } ; + + union { + __IM uint32_t MFIFOSR; /*!< (@ 0x0000005C) Master FIFO Status Register */ + + struct { + __IM uint32_t TXCNT : 2; /*!< [1..0] desc TXCNT */ + __IM uint32_t : 14; + __IM uint32_t RXCNT : 2; /*!< [17..16] desc RXCNT */ + } MFIFOSR_f; + } ; + + union { + __OM uint32_t MTDR; /*!< (@ 0x00000060) Master Tx Data Register */ + + struct { + __OM uint32_t DATA : 8; /*!< [7..0] desc DATA */ + __OM uint32_t CMD : 3; /*!< [10..8] desc CMD */ + } MTDR_f; + } ; + __IM uint32_t RESERVED4[3]; + + union { + __IM uint32_t MRDR; /*!< (@ 0x00000070) Master Rx Data Register */ + + struct { + __IM uint32_t DATA : 8; /*!< [7..0] desc DATA */ + __IM uint32_t : 6; + __IM uint32_t EMPTY : 1; /*!< [14..14] desc EMPTY */ + } MRDR_f; + } ; + __IM uint32_t RESERVED5[38]; + + union { + __IOM uint32_t SICR; /*!< (@ 0x0000010C) desc SICR */ + + struct { + __IM uint32_t : 8; + __IOM uint32_t RESTART : 1; /*!< [8..8] desc RESTART */ + __IOM uint32_t STOP : 1; /*!< [9..9] desc STOP */ + __IOM uint32_t BIT : 1; /*!< [10..10] desc BIT */ + __IOM uint32_t FIFO : 1; /*!< [11..11] desc FIFO */ + } SICR_f; + } ; + + union { + __IOM uint32_t SCR0; /*!< (@ 0x00000110) Slave Control Register0 */ + + struct { + __IOM uint32_t SEN : 1; /*!< [0..0] desc SEN */ + __IOM uint32_t RESET : 1; /*!< [1..1] desc RESET */ + __IM uint32_t : 2; + __IOM uint32_t FLTEN : 1; /*!< [4..4] desc FLTEN */ + __IM uint32_t : 1; + __IOM uint32_t CLKSRC : 2; /*!< [7..6] desc CLKSRC */ + __IOM uint32_t TXFIFORST : 1; /*!< [8..8] desc TXFIFORST */ + __IOM uint32_t RXFIFORST : 1; /*!< [9..9] desc RXFIFORST */ + } SCR0_f; + } ; + + union { + __IM uint32_t SISR; /*!< (@ 0x00000114) desc SISR */ + + struct { + __IM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IM uint32_t ADDR : 1; /*!< [2..2] desc ADDR */ + __IM uint32_t TACK : 1; /*!< [3..3] desc TACK */ + __IM uint32_t : 4; + __IM uint32_t RESTART : 1; /*!< [8..8] desc RESTART */ + __IM uint32_t STOP : 1; /*!< [9..9] desc STOP */ + __IM uint32_t BIT : 1; /*!< [10..10] desc BIT */ + __IM uint32_t FIFO : 1; /*!< [11..11] desc FIFO */ + __IM uint32_t AM0 : 1; /*!< [12..12] desc AM0 */ + __IM uint32_t AM1 : 1; /*!< [13..13] desc AM1 */ + __IM uint32_t GC : 1; /*!< [14..14] desc GC */ + __IM uint32_t ALERT : 1; /*!< [15..15] desc ALERT */ + __IM uint32_t : 8; + __IM uint32_t SLVBUSY : 1; /*!< [24..24] desc SLVBUSY */ + __IM uint32_t BUSBUSY : 1; /*!< [25..25] desc BUSBUSY */ + } SISR_f; + } ; + + union { + __IOM uint32_t SIER; /*!< (@ 0x00000118) desc SIER */ + + struct { + __IOM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IOM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IOM uint32_t ADDR : 1; /*!< [2..2] desc ADDR */ + __IOM uint32_t TACK : 1; /*!< [3..3] desc TACK */ + __IM uint32_t : 4; + __IOM uint32_t RESTART : 1; /*!< [8..8] desc RESTART */ + __IOM uint32_t STOP : 1; /*!< [9..9] desc STOP */ + __IOM uint32_t BIT : 1; /*!< [10..10] desc BIT */ + __IOM uint32_t FIFO : 1; /*!< [11..11] desc FIFO */ + __IOM uint32_t AM0 : 1; /*!< [12..12] desc AM0 */ + __IOM uint32_t AM1 : 1; /*!< [13..13] desc AM1 */ + __IOM uint32_t GC : 1; /*!< [14..14] desc GC */ + __IOM uint32_t ALERT : 1; /*!< [15..15] desc ALERT */ + } SIER_f; + } ; + + union { + __IOM uint32_t SDER; /*!< (@ 0x0000011C) desc SDER */ + + struct { + __IOM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IOM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IOM uint32_t ADDR : 1; /*!< [2..2] desc ADDR */ + } SDER_f; + } ; + __IM uint32_t RESERVED6; + + union { + __IOM uint32_t SCR1; /*!< (@ 0x00000124) desc SCR1 */ + + struct { + __IOM uint32_t ADRSTALL : 1; /*!< [0..0] desc ADRSTALL */ + __IOM uint32_t RXSTALL : 1; /*!< [1..1] desc RXSTALL */ + __IOM uint32_t TXSTALL : 1; /*!< [2..2] desc TXSTALL */ + __IOM uint32_t ACKSTALL : 1; /*!< [3..3] desc ACKSTALL */ + __IM uint32_t : 4; + __IOM uint32_t GCEN : 1; /*!< [8..8] desc GCEN */ + __IOM uint32_t ALERTEN : 1; /*!< [9..9] desc ALERTEN */ + __IOM uint32_t TXCFG : 1; /*!< [10..10] desc TXCFG */ + __IOM uint32_t RXCFG : 1; /*!< [11..11] desc RXCFG */ + __IOM uint32_t IGNACK : 1; /*!< [12..12] desc IGNACK */ + uint32_t : 2; + __IOM uint32_t TRGSEL : 1; /*!< [15..15] desc TRGSEL */ + __IOM uint32_t ADDRCFG : 3; /*!< [18..16] desc ADDRCFG */ + } SCR1_f; + } ; + + union { + __IOM uint32_t SCR3; /*!< (@ 0x00000128) desc SCR3 */ + + struct { + __IOM uint32_t CLKHOLD : 4; /*!< [3..0] desc CLKHOLD */ + __IM uint32_t : 4; + __IOM uint32_t DATAVD : 6; /*!< [13..8] desc DATAVD */ + __IM uint32_t : 2; + __IOM uint32_t FLTSCL : 4; /*!< [19..16] desc FLTSCL */ + __IM uint32_t : 4; + __IOM uint32_t FLTSDA : 4; /*!< [27..24] desc FLTSDA */ + } SCR3_f; + } ; + __IM uint32_t RESERVED7[5]; + + union { + __IOM uint32_t SAMR; /*!< (@ 0x00000140) desc SAMR */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t ADDR0 : 10; /*!< [10..1] desc ADDR0 */ + __IM uint32_t : 6; + __IOM uint32_t ADDR1 : 10; /*!< [26..17] desc ADDR1 */ + } SAMR_f; + } ; + __IM uint32_t RESERVED8[3]; + + union { + __IM uint32_t SASR; /*!< (@ 0x00000150) desc SASR */ + + struct { + __IM uint32_t RADDR : 11; /*!< [10..0] desc RADDR */ + __IM uint32_t : 3; + __IM uint32_t ANV : 1; /*!< [14..14] desc ANV */ + } SASR_f; + } ; + + union { + __IOM uint32_t STAR; /*!< (@ 0x00000154) desc STAR */ + + struct { + __IOM uint32_t TXNACK : 1; /*!< [0..0] desc TXNACK */ + } STAR_f; + } ; + __IM uint32_t RESERVED9[2]; + + union { + __OM uint32_t STDR; /*!< (@ 0x00000160) desc STDR */ + + struct { + __OM uint32_t DATA : 8; /*!< [7..0] desc DATA */ + } STDR_f; + } ; + __IM uint32_t RESERVED10[3]; + + union { + __IM uint32_t SRDR; /*!< (@ 0x00000170) desc SRDR */ + + struct { + __IM uint32_t DATA : 8; /*!< [7..0] desc DATA */ + __IM uint32_t : 6; + __IM uint32_t RXEMPTY : 1; /*!< [14..14] desc RXEMPTY */ + __IM uint32_t SOF : 1; /*!< [15..15] desc SOF */ + } SRDR_f; + } ; +} I2C_TypeDef; /*!< Size = 372 (0x174) */ + + + +/* =========================================================================================================================== */ +/* ================ IRMOD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc IRMOD (IRMOD) + */ + +typedef struct { /*!< (@ 0x40004080) IRMOD Structure */ + union { + __IOM uint32_t CR; /*!< (@ 0x00000000) Input selection register */ + + struct { + __IOM uint32_t MOD : 4; /*!< [3..0] desc MOD */ + __IOM uint32_t IRSW : 1; /*!< [4..4] desc IRSW */ + __IOM uint32_t INV : 1; /*!< [5..5] desc INV */ + } CR_f; + } ; +} IRMOD_TypeDef; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ IWDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc IWDT (IWDT) + */ + +typedef struct { /*!< (@ 0x40005000) IWDT Structure */ + + union { + __OM uint32_t KR; /*!< (@ 0x00000000) Key register */ + + struct { + __OM uint32_t KR : 16; /*!< [15..0] desc KR */ + } KR_f; + } ; + + union { + __IOM uint32_t CR; /*!< (@ 0x00000004) Control register */ + + struct { + __IOM uint32_t PRS : 3; /*!< [2..0] desc PRS */ + __IOM uint32_t ACTION : 1; /*!< [3..3] desc ACTION */ + __IOM uint32_t IE : 1; /*!< [4..4] desc IE */ + __IOM uint32_t PAUSE : 1; /*!< [5..5] desc PAUSE */ + } CR_f; + } ; + + union { + __IOM uint32_t ARR; /*!< (@ 0x00000008) Auto reload register */ + + struct { + __IOM uint32_t ARR : 12; /*!< [11..0] desc ARR */ + } ARR_f; + } ; + + union { + __IOM uint32_t SR; /*!< (@ 0x0000000C) Status register */ + + struct { + __IM uint32_t CRF : 1; /*!< [0..0] desc CRF */ + __IM uint32_t ARRF : 1; /*!< [1..1] desc ARRF */ + __IM uint32_t WINRF : 1; /*!< [2..2] desc WINRF */ + __IOM uint32_t OV : 1; /*!< [3..3] desc OV */ + __IM uint32_t RUN : 1; /*!< [4..4] desc RUN */ + __IM uint32_t RELOAD : 1; /*!< [5..5] desc RELOAD */ + } SR_f; + } ; + + union { + __IOM uint32_t WINR; /*!< (@ 0x00000010) Window register */ + + struct { + __IOM uint32_t WINR : 12; /*!< [11..0] desc WINR */ + } WINR_f; + } ; + __IM uint32_t RESERVED[4]; + + union { + __IM uint32_t CNT; /*!< (@ 0x00000024) counter */ + + struct { + __IM uint32_t CNT : 12; /*!< [11..0] desc CNT */ + } CNT_f; + } ; +} IWDT_TypeDef; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ LPTIM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc LPTIM (LPTIM) + */ + +typedef struct { /*!< (@ 0x40006000) LPTIM Structure */ + + union { + __IM uint32_t ISR; /*!< (@ 0x00000000) desc ISR */ + + struct { + __IM uint32_t CMPM : 1; /*!< [0..0] desc CMPM */ + __IM uint32_t ARRM : 1; /*!< [1..1] desc ARRM */ + __IM uint32_t EXTTRIG : 1; /*!< [2..2] desc EXTTRIG */ + __IM uint32_t CMPOK : 1; /*!< [3..3] desc CMPOK */ + __IM uint32_t ARROK : 1; /*!< [4..4] desc ARROK */ + __IM uint32_t UP : 1; /*!< [5..5] desc UP */ + __IM uint32_t DOWN : 1; /*!< [6..6] desc DOWN */ + __IM uint32_t DIR : 2; /*!< [8..7] desc DIR */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000004) desc ICR */ + + struct { + __IOM uint32_t CMPM : 1; /*!< [0..0] desc CMPM */ + __IOM uint32_t ARRM : 1; /*!< [1..1] desc ARRM */ + __IOM uint32_t EXTTRIG : 1; /*!< [2..2] desc EXTTRIG */ + __IOM uint32_t CMPOK : 1; /*!< [3..3] desc CMPOK */ + __IOM uint32_t ARROK : 1; /*!< [4..4] desc ARROK */ + __IOM uint32_t UP : 1; /*!< [5..5] desc UP */ + __IOM uint32_t DOWN : 1; /*!< [6..6] desc DOWN */ + } ICR_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000008) desc IER */ + + struct { + __IOM uint32_t CMPM : 1; /*!< [0..0] desc CMPM */ + __IOM uint32_t ARRM : 1; /*!< [1..1] desc ARRM */ + __IOM uint32_t EXTTRIG : 1; /*!< [2..2] desc EXTTRIG */ + __IOM uint32_t CMPOK : 1; /*!< [3..3] desc CMPOK */ + __IOM uint32_t ARROK : 1; /*!< [4..4] desc ARROK */ + __IOM uint32_t UP : 1; /*!< [5..5] desc UP */ + __IOM uint32_t DOWN : 1; /*!< [6..6] desc DOWN */ + } IER_f; + } ; + + union { + __IOM uint32_t CFGR; /*!< (@ 0x0000000C) desc CFGR1 */ + + struct { + __IOM uint32_t CKSEL : 1; /*!< [0..0] desc CKSEL */ + __IOM uint32_t ENCMD_CKPOL : 2; /*!< [2..1] desc ENCMD_CKPOL */ + __IOM uint32_t CHFLT : 2; /*!< [4..3] desc CHFLT */ + __IM uint32_t : 1; + __IOM uint32_t TRIGFLT : 2; /*!< [7..6] desc TRIGFLT */ + __IM uint32_t : 1; + __IOM uint32_t PRS : 3; /*!< [11..9] desc PRS */ + __IOM uint32_t TRIGSEL : 4; /*!< [15..12] desc TRIGSEL */ + __IM uint32_t : 1; + __IOM uint32_t TRIGEN : 2; /*!< [18..17] desc TRIGEN */ + __IOM uint32_t TIMOUT : 1; /*!< [19..19] desc TIMOUT */ + __IOM uint32_t WAVE : 1; /*!< [20..20] desc WAVE */ + __IOM uint32_t WAVPOL : 1; /*!< [21..21] desc WAVPOL */ + __IOM uint32_t PRELOAD : 1; /*!< [22..22] desc PRELOAD */ + __IOM uint32_t COUNTMD : 1; /*!< [23..23] desc COUNTMD */ + __IOM uint32_t ENC : 1; /*!< [24..24] desc ENC */ + __IOM uint32_t ICLKSRC : 2; /*!< [26..25] desc ICLKSRC */ + } CFGR_f; + } ; + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000010) desc CR */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t SNGSTART : 1; /*!< [1..1] desc SNGSTART */ + __IOM uint32_t CNTSTART : 1; /*!< [2..2] desc CNTSTART */ + __IOM uint32_t SRST : 1; /*!< [3..3] desc SRST */ + __IOM uint32_t ARST : 1; /*!< [4..4] desc ARST */ + } CR0_f; + } ; + + union { + __IOM uint32_t CMP; /*!< (@ 0x00000014) desc CMP */ + + struct { + __IOM uint32_t CMP : 16; /*!< [15..0] desc CMP */ + } CMP_f; + } ; + + union { + __IOM uint32_t ARR; /*!< (@ 0x00000018) desc ARR */ + + struct { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } ARR_f; + } ; + + union { + __IM uint32_t CNT; /*!< (@ 0x0000001C) desc CNT */ + + struct { + __IM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + } CNT_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000020) desc CFGR2 */ + + struct { + __IOM uint32_t CH1SRC : 3; /*!< [2..0] desc CH1SRC */ + __IOM uint32_t CH2SRC : 3; /*!< [5..3] desc CH2SRC */ + } CR1_f; + } ; +} LPTIM_TypeDef; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ UART1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc UART1 (UART1) + */ + +typedef struct { /*!< (@ 0x40000C00) UART1 Structure */ + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t TXEN : 1; /*!< [0..0] desc TXEN */ + __IOM uint32_t RXEN : 1; /*!< [1..1] desc RXEN */ + __IOM uint32_t PARITY : 1; /*!< [2..2] desc PARITY */ + __IOM uint32_t PARITYEN : 1; /*!< [3..3] desc PARITYEN */ + __IOM uint32_t STOP : 2; /*!< [5..4] desc STOP */ + __IOM uint32_t CHLEN : 1; /*!< [6..6] desc CHLEN */ + __IOM uint32_t MSBF : 1; /*!< [7..7] desc MSBF */ + __IOM uint32_t START : 1; /*!< [8..8] desc START */ + __IOM uint32_t OVER : 2; /*!< [10..9] desc OVER */ + __IOM uint32_t SIGNAL : 1; /*!< [11..11] desc SIGNAL */ + __IOM uint32_t SOURCE : 2; /*!< [13..12] desc SOURCE */ + __IOM uint32_t SYNC : 1; /*!< [14..14] desc SYNC */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000004) Control register2 */ + + struct { + __IOM uint32_t ADDREN : 1; /*!< [0..0] desc ADDREN */ + __IOM uint32_t RXMATCHEN : 1; /*!< [1..1] desc RXMATCHEN */ + __IOM uint32_t CTSEN : 1; /*!< [2..2] desc CTSEN */ + __IOM uint32_t RTSEN : 1; /*!< [3..3] desc RTSEN */ + __IOM uint32_t RXINV : 1; /*!< [4..4] desc RXINV */ + __IOM uint32_t TXINV : 1; /*!< [5..5] desc TXINV */ + __IOM uint32_t DMARX : 1; /*!< [6..6] desc DMARX */ + __IOM uint32_t DMATX : 1; /*!< [7..7] desc DMATX */ + __IOM uint32_t TIMCR : 3; /*!< [10..8] desc TIMCR */ + __IOM uint32_t SWAP : 1; /*!< [11..11] desc SWAP */ + __IOM uint32_t ADCRX : 1; /*!< desc ADCRX */ + __IOM uint32_t ADCTX : 1; /*!< desc ADCTX */ + __IOM uint32_t LOOP : 1; /*!< [14..14] desc LOOP */ + __IOM uint32_t RXSRC : 3; /*!< [17..15] desc RXSRC */ + } CR2_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000008) Interrupt enable register */ + + struct { + __IOM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IOM uint32_t TC : 1; /*!< [1..1] desc TC */ + __IOM uint32_t RC : 1; /*!< [2..2] desc RC */ + __IOM uint32_t RXIDLE : 1; /*!< [3..3] desc RXIDLE */ + __IOM uint32_t RXBRK : 1; /*!< [4..4] desc RXBRK */ + __IOM uint32_t BAUD : 1; /*!< [5..5] desc BAUD */ + __IOM uint32_t TIMOV : 1; /*!< [6..6] desc TIMOV */ + __IOM uint32_t CTS : 1; /*!< [7..7] desc CTS */ + __IOM uint32_t FE : 1; /*!< [8..8] desc FE */ + __IOM uint32_t PE : 1; /*!< [9..9] desc PE */ + __IOM uint32_t NE : 1; /*!< [10..10] desc NE */ + __IOM uint32_t ORE : 1; /*!< [11..11] desc ORE */ + __IOM uint32_t RXMATCH : 1; /*!< [12..12] desc RXMATCH */ + } IER_f; + } ; + + union { + __IOM uint32_t BRRI; /*!< (@ 0x0000000C) desc BRRI */ + + struct { + __IOM uint32_t BRRI : 16; /*!< [15..0] desc BRRI */ + } BRRI_f; + } ; + + union { + __IOM uint32_t BRRF; /*!< (@ 0x00000010) desc BRRF */ + + struct { + __IOM uint32_t BRRF : 4; /*!< [3..0] desc BRRF */ + } BRRF_f; + } ; + + union { + __IOM uint32_t TIMARR; /*!< (@ 0x00000014) desc TIMARR */ + + struct { + __IOM uint32_t TIMARR : 24; /*!< [23..0] desc TIMARR */ + } TIMARR_f; + } ; + + union { + __IM uint32_t TIMCNT; /*!< (@ 0x00000018) desc TIMCNT */ + + struct { + __IM uint32_t TIMCNT : 24; /*!< [23..0] desc TIMCNT */ + } TIMCNT_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x0000001C) Interrupt status register */ + + struct { + __IM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IM uint32_t TC : 1; /*!< [1..1] desc TC */ + __IM uint32_t RC : 1; /*!< [2..2] desc RC */ + __IM uint32_t RXIDLE : 1; /*!< [3..3] desc RXIDLE */ + __IM uint32_t RXBRK : 1; /*!< [4..4] desc RXBRK */ + __IM uint32_t BAUD : 1; /*!< [5..5] desc BAUD */ + __IM uint32_t TIMOV : 1; /*!< [6..6] desc TIMOV */ + __IM uint32_t CTS : 1; /*!< [7..7] desc CTS */ + __IM uint32_t FE : 1; /*!< [8..8] desc FE */ + __IM uint32_t PE : 1; /*!< [9..9] desc PE */ + __IM uint32_t NE : 1; /*!< [10..10] desc NE */ + __IM uint32_t ORE : 1; /*!< [11..11] desc ORE */ + __IM uint32_t RXMATCH : 1; /*!< [12..12] desc RXMATCH */ + __IM uint32_t SLVMATCH : 1; /*!< [13..13] desc SLVMATCH */ + __IM uint32_t TXBUSY : 1; /*!< [14..14] desc TXBUSY */ + __IM uint32_t CTSLV : 1; /*!< [15..15] desc CTSLV */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000020) Interrupt flag clear register */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t TC : 1; /*!< [1..1] desc TC */ + __IOM uint32_t RC : 1; /*!< [2..2] desc RC */ + __IOM uint32_t RXIDLE : 1; /*!< [3..3] desc RXIDLE */ + __IOM uint32_t RXBRK : 1; /*!< [4..4] desc RXBRK */ + __IOM uint32_t BAUD : 1; /*!< [5..5] desc BAUD */ + __IOM uint32_t TIMOV : 1; /*!< [6..6] desc TIMOV */ + __IOM uint32_t CTS : 1; /*!< [7..7] desc CTS */ + __IOM uint32_t FE : 1; /*!< [8..8] desc FE */ + __IOM uint32_t PE : 1; /*!< [9..9] desc PE */ + __IOM uint32_t NE : 1; /*!< [10..10] desc NE */ + __IOM uint32_t ORE : 1; /*!< [11..11] desc ORE */ + __IOM uint32_t RXMATCH : 1; /*!< [12..12] desc RXMATCH */ + } ICR_f; + } ; + + union { + __IM uint32_t RDR; /*!< (@ 0x00000024) Data reg for read */ + + struct { + __IM uint32_t RDR : 9; /*!< [8..0] desc RDR */ + } RDR_f; + } ; + + union { + __OM uint32_t TDR; /*!< (@ 0x00000028) Data reg for write */ + + struct { + __OM uint32_t TDR : 9; /*!< [8..0] desc TDR */ + __OM uint32_t IDLE : 1; /*!< [9..9] desc IDLE */ + __OM uint32_t BREAK : 1; /*!< [10..10] desc BREAK */ + } TDR_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t ADDR; /*!< (@ 0x00000030) Slave addr */ + + struct { + __IOM uint32_t ADDR : 8; /*!< [7..0] desc ADDR */ + } ADDR_f; + } ; + + union { + __IOM uint32_t MASK; /*!< (@ 0x00000034) Slave addr mask */ + + struct { + __IOM uint32_t MASK : 8; /*!< [7..0] desc MASK */ + } MASK_f; + } ; + + union { + __IOM uint32_t CR3; /*!< (@ 0x00000038) Control register3 */ + + struct { + __IOM uint32_t DEM : 1; /*!< [0..0] desc DEM */ + __IOM uint32_t DEP : 1; /*!< desc DEP */ + __IOM uint32_t DETIME : 5; /*!< [6..2] desc DETIME */ + __IOM uint32_t LIN : 1; /*!< [7..7] desc LIN */ + __IOM uint32_t BRKL : 1; /*!< [8..8] desc BRKL */ + } CR3_f; + } ; + + union { + __IOM uint32_t RXMATCH; /*!< (@ 0x0000003C) desc RXMATCH */ + + struct { + __IOM uint32_t RXMATCH : 9; /*!< [8..0] desc RXMATCH */ + } RXMATCH_f; + } ; +} UART_TypeDef; /*!< Size = 64 (0x40) */ + + + +/* =========================================================================================================================== */ +/* ================ LVD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc LVD (LVD) + */ + +typedef struct { /*!< (@ 0x400000A4) LVD Structure */ + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control register0 */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t ACTION : 1; /*!< [1..1] desc ACTION */ + __IOM uint32_t SOURCE : 1; /*!< [2..2] desc SOURCE */ + __IM uint32_t : 1; + __IOM uint32_t VTH : 3; /*!< [6..4] desc VTH */ + __IM uint32_t : 1; + __IOM uint32_t FLTCLK : 1; /*!< [8..8] desc FLTCLK */ + } CR0_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000004) Control register1 */ + + struct { + __IOM uint32_t IE : 1; /*!< [0..0] desc IE */ + __IOM uint32_t LEVEL : 1; /*!< [1..1] desc LEVEL */ + __IOM uint32_t RISE : 1; /*!< [2..2] desc RISE */ + __IOM uint32_t FALL : 1; /*!< [3..3] desc FALL */ + __IOM uint32_t FLTTIME : 4; /*!< [7..4] desc FLTTIME */ + } CR1_f; + } ; + + union { + __IOM uint32_t SR; /*!< (@ 0x00000008) status register */ + + struct { + __IOM uint32_t INTF : 1; /*!< [0..0] desc INTF */ + __IM uint32_t FLTV : 1; /*!< [1..1] desc FLTV */ + } SR_f; + } ; +} LVD_TypeDef; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ OPA1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc OPA1 (OPA1) + */ + +typedef struct { /*!< (@ 0x400000B0) OPA1 Structure */ + + union { + __IOM uint32_t CR; /*!< (@ 0x00000000) Control register0 */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t MODE : 2; /*!< [2..1] desc MODE */ + __IM uint32_t : 1; + __IOM uint32_t INP1EN : 1; /*!< [4..4] desc PCH1EN */ + __IOM uint32_t INP2EN : 1; /*!< [5..5] desc PCH2EN */ + __IOM uint32_t INP3EN : 1; /*!< [6..6] desc PCH3EN */ + __IOM uint32_t INP4EN : 1; /*!< [7..7] desc PCH4EN */ + __IOM uint32_t INN1EN : 1; /*!< [8..8] desc NCH1EN */ + __IOM uint32_t INN2EN : 1; /*!< [9..9] desc NCH2EN */ + __IOM uint32_t AMP : 3; /*!< [12..10] desc GAIN */ + __IOM uint32_t BIAS : 3; /*!< [15..13] desc BIAS */ + } CR_f; + } ; + + union { + __IOM uint32_t CAL; /*!< (@ 0x00000004) Control register1 */ + + struct { + __IOM uint32_t CALEN : 1; /*!< [0..0] desc AZEN */ + __IOM uint32_t CALMODE : 1; /*!< [1..1] desc MODE */ + __IOM uint32_t START : 1; /*!< [2..2] desc START */ + __IOM uint32_t SOFTTRIG : 1; /*!< [3..3] desc SOFTTRIG */ + __IOM uint32_t CALPERIOD : 4; /*!< [7..4] desc PERIOD */ + __IOM uint32_t ADCSTART : 1; /*!< desc ADCSTART */ + uint32_t : 1; + __IM uint32_t AZRUN : 1; /*!< [10..10] desc AZRUN */ + __IOM uint32_t CLKDIV : 3; /*!< [13..11] desc CLKDIV */ + __IOM uint32_t ADC1START1 : 1; /*!< [14..14] desc ADC1START1 */ + __IOM uint32_t ADC2START1 : 1; /*!< [15..15] desc ADC2START1 */ + __IOM uint32_t ATIM1TRGO : 1; /*!< [16..16] desc ATIM1TRGO */ + __IOM uint32_t ATIM1OC4 : 1; /*!< [17..17] desc ATIM1OC4REFC */ + __IOM uint32_t ATIM1OC5 : 1; /*!< [18..18] desc ATIM1OC5REFC */ + __IOM uint32_t ATIM1OC6 : 1; /*!< [19..19] desc ATIM1OC6REFC */ + __IOM uint32_t GTIM1TRGO : 1; /*!< [20..20] desc GTIM1TRGO */ + __IOM uint32_t GTIM1OC1 : 1; /*!< [21..21] desc GTIM1OC1REFC */ + __IOM uint32_t GTIM1OC2 : 1; /*!< [22..22] desc GTIM1OC2REFC */ + __IOM uint32_t GTIM2TRGO : 1; /*!< [23..23] desc GTIM2TRGO */ + __IOM uint32_t GTIM2OC1 : 1; /*!< [24..24] desc GTIM2OC1REFC */ + __IOM uint32_t GTIM2OC2 : 1; /*!< [25..25] desc GTIM2OC2REFC */ + __IOM uint32_t GTIM3TRGO : 1; /*!< [26..26] desc GTIM3TRGO */ + __IOM uint32_t GTIM3OC1 : 1; /*!< [27..27] desc GTIM3OC1REFC */ + __IOM uint32_t GTIM3OC2 : 1; /*!< [28..28] desc GTIM3OC2REFC */ + __IOM uint32_t GTIM4TRGO : 1; /*!< [29..29] desc GTIM4TRGO */ + __IOM uint32_t GTIM4OC1 : 1; /*!< [30..30] desc GTIM4OC1REFC */ + __IOM uint32_t GTIM4OC2 : 1; /*!< [31..31] desc GTIM4OC2REFC */ + } CAL_f; + } ; +} OPA_TypeDef; /*!< Size = 8 (0x8) */ + + +/* =========================================================================================================================== */ +/* ================ RAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc RAM (RAM) + */ + +typedef struct { /*!< (@ 0x40022400) RAM Structure */ + + union { + __IOM uint32_t IER; /*!< (@ 0x00000000) Interrupt enable register */ + + struct { + __IOM uint32_t PARITY : 1; /*!< [0..0] desc PARITY */ + } IER_f; + } ; + + union { + __IM uint32_t ADDR; /*!< (@ 0x00000004) Error address register */ + + struct { + __IM uint32_t ADDR : 32; /*!< [31..0] desc ADDR */ + } ADDR_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000008) Interrupt status register */ + + struct { + __IM uint32_t PARITY : 1; /*!< [0..0] desc PARITY */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x0000000C) Interrupt flag clear register */ + + struct { + __IOM uint32_t PARITY : 1; /*!< [0..0] desc PARITY */ + } ICR_f; + } ; +} RAM_TypeDef; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc RTC (RTC) + */ + +typedef struct { /*!< (@ 0x40004400) RTC Structure */ + + union { + __OM uint32_t KEY; /*!< (@ 0x00000000) desc KEY */ + + struct { + __OM uint32_t KEY : 8; /*!< [7..0] desc KEY */ + } KEY_f; + } ; + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000004) desc CR0 */ + + struct { + __IOM uint32_t INTERVAL : 3; /*!< [2..0] desc INTERVAL */ + __IOM uint32_t H24 : 1; /*!< [3..3] desc H24 */ + __IM uint32_t : 1; + __IOM uint32_t RTC1HZ : 2; /*!< [6..5] desc RTC1HZ */ + __IOM uint32_t START : 1; /*!< [7..7] desc START */ + } CR0_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000008) desc CR1 */ + + struct { + __IM uint32_t : 2; + __IM uint32_t WAIT : 1; /*!< [2..2] desc WAIT */ + __IM uint32_t : 5; + __IOM uint32_t SOURCE : 3; /*!< [10..8] desc SOURCE */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x0000000C) desc CR2 */ + + struct { + __IOM uint32_t AWTPRS : 2; /*!< [1..0] desc AWTPRS */ + __IOM uint32_t AWTSRC : 1; /*!< [2..2] desc AWTSRC */ + __IOM uint32_t TAMPEDGE : 1; /*!< [3..3] desc TAMPEDGE */ + __IOM uint32_t RTCOUT : 2; /*!< [5..4] desc RTCOUT */ + __IOM uint32_t TAMPEN : 1; /*!< [6..6] desc TAMPEN */ + __IOM uint32_t AWTEN : 1; /*!< [7..7] desc AWTEN */ + __IM uint32_t : 1; + __IOM uint32_t ALARMAEN : 1; /*!< [9..9] desc ALARMAEN */ + __IOM uint32_t ALARMBEN : 1; /*!< [10..10] desc ALARMBEN */ + } CR2_f; + } ; + + union { + __IOM uint32_t COMPCFR1; /*!< (@ 0x00000010) desc COMPCFR1 */ + + struct { + __IOM uint32_t COMP : 12; /*!< [11..0] desc COMP */ + __IOM uint32_t PERIOD : 2; /*!< [13..12] desc PERIOD */ + __IOM uint32_t SIGN : 1; /*!< [14..14] desc SIGN */ + __IOM uint32_t EN : 1; /*!< [15..15] desc EN */ + } COMPCFR1_f; + } ; + + union { + __IOM uint32_t DATE; /*!< (@ 0x00000014) desc DATE */ + + struct { + __IOM uint32_t DAY : 6; /*!< [7..0] desc DAY */ + uint32_t : 2; + __IOM uint32_t MONTH : 5; /*!< [15..8] desc MONTH */ + uint32_t : 3; + __IOM uint32_t YEAR : 8; /*!< [23..16] desc YEAR */ + __IOM uint32_t WEEK : 3; /*!< [26..24] desc WEEK */ + } DATE_f; + } ; + + union { + __IOM uint32_t TIME; /*!< (@ 0x00000018) desc TIME */ + + struct { + __IOM uint32_t SECOND : 7; /*!< [6..0] desc SECOND */ + __IM uint32_t : 1; + __IOM uint32_t MINUTE : 7; /*!< [14..8] desc MINUTE */ + __IM uint32_t : 1; + __IOM uint32_t HOUR : 6; /*!< [21..16] desc HOUR */ + } TIME_f; + } ; + + union { + __IOM uint32_t ALARMA; /*!< (@ 0x0000001C) desc ALARMA */ + + struct { + __IOM uint32_t SECOND : 7; /*!< [6..0] desc SECOND */ + __IOM uint32_t SECONDEN : 1; /*!< [7..7] desc SECONDEN */ + __IOM uint32_t MINUTE : 7; /*!< [14..8] desc MINUTE */ + __IOM uint32_t MINUTEEN : 1; /*!< [15..15] desc MINUTEEN */ + __IOM uint32_t HOUR : 6; /*!< [21..16] desc HOUR */ + __IM uint32_t : 1; + __IOM uint32_t HOUREN : 1; /*!< [23..23] desc HOUREN */ + __IOM uint32_t WEEKMASK : 7; /*!< [30..24] desc WEEKMASK */ + } ALARMA_f; + } ; + + union { + __IOM uint32_t ALARMB; /*!< (@ 0x00000020) desc ALARMB */ + + struct { + __IOM uint32_t SECOND : 7; /*!< [6..0] desc SECOND */ + __IOM uint32_t SECONDEN : 1; /*!< [7..7] desc SECONDEN */ + __IOM uint32_t MINUTE : 7; /*!< [14..8] desc MINUTE */ + __IOM uint32_t MINUTEEN : 1; /*!< [15..15] desc MINUTEEN */ + __IOM uint32_t HOUR : 6; /*!< [21..16] desc HOUR */ + __IM uint32_t : 1; + __IOM uint32_t HOUREN : 1; /*!< [23..23] desc HOUREN */ + __IOM uint32_t WEEKMASK : 7; /*!< [30..24] desc WEEKMASK */ + } ALARMB_f; + } ; + + union { + __IM uint32_t TAMPDATE; /*!< (@ 0x00000024) desc TAMPDATE */ + + struct { + __IM uint32_t DAY : 6; /*!< [5..0] desc DAY */ + __IM uint32_t : 2; + __IM uint32_t MONTH : 5; /*!< [12..8] desc MONTH */ + __IM uint32_t WEEK : 3; /*!< [15..13] desc WEEK */ + } TAMPDATE_f; + } ; + + union { + __IM uint32_t TAMPTIME; /*!< (@ 0x00000028) desc TAMPTIME */ + + struct { + __IM uint32_t SECOND : 7; /*!< [6..0] desc SECOND */ + __IM uint32_t : 1; + __IM uint32_t MINUTE : 7; /*!< [14..8] desc MINUTE */ + __IM uint32_t : 1; + __IM uint32_t HOUR : 6; /*!< [21..16] desc HOUR */ + } TAMPTIME_f; + } ; + + union { + __IOM uint32_t AWTARR; /*!< (@ 0x0000002C) desc AWTARR */ + + struct { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } AWTARR_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000030) desc IER */ + + struct { + __IOM uint32_t ALARMA : 1; /*!< [0..0] desc ALARMA */ + __IOM uint32_t ALARMB : 1; /*!< [1..1] desc ALARMB */ + __IOM uint32_t AWTIMER : 1; /*!< [2..2] desc AWTIMER */ + __IOM uint32_t TAMP : 1; /*!< [3..3] desc TAMP */ + __IOM uint32_t TAMPOV : 1; /*!< [4..4] desc TAMPOV */ + __IM uint32_t : 1; + __IOM uint32_t INTERVAL : 1; /*!< [6..6] desc INTERVAL */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000034) desc ISR */ + + struct { + __IM uint32_t ALARMA : 1; /*!< [0..0] desc ALARMA */ + __IM uint32_t ALARMB : 1; /*!< [1..1] desc ALARMB */ + __IM uint32_t AWTIMER : 1; /*!< [2..2] desc AWTIMER */ + __IM uint32_t TAMP : 1; /*!< [3..3] desc TAMP */ + __IM uint32_t TAMPOV : 1; /*!< [4..4] desc TAMPOV */ + __IM uint32_t : 1; + __IM uint32_t INTERVAL : 1; /*!< [6..6] desc INTERVAL */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000038) desc ICR */ + + struct { + __IOM uint32_t ALARMA : 1; /*!< [0..0] desc ALARMA */ + __IOM uint32_t ALARMB : 1; /*!< [1..1] desc ALARMB */ + __IOM uint32_t AWTIMER : 1; /*!< [2..2] desc AWTIMER */ + __IOM uint32_t TAMP : 1; /*!< [3..3] desc TAMP */ + __IOM uint32_t TAMPOV : 1; /*!< [4..4] desc TAMPOV */ + __IM uint32_t : 1; + __IOM uint32_t INTERVAL : 1; /*!< [6..6] desc INTERVAL */ + } ICR_f; + } ; + + union { + __IM uint32_t AWTCNT; /*!< (@ 0x0000003C) desc AWTCNT */ + + struct { + __IM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + } AWTCNT_f; + } ; + + union { + __IOM uint32_t PSC; /*!< (@ 0x00000040) desc PSC */ + + struct { + __IOM uint32_t PSC2 : 20; /*!< [19..0] desc PSC2 */ + __IOM uint32_t PSC1 : 8; /*!< [27..20] desc PSC1 */ + } PSC_f; + } ; + + union { + __IM uint32_t SSCNT; /*!< (@ 0x00000044) desc SSCNT */ + + struct { + __IM uint32_t SSCNT0 : 20; /*!< [19..0] desc SSCNT0 */ + __IM uint32_t SSCNT1 : 1; /*!< [20..20] desc SSCNT1 */ + } SSCNT_f; + } ; +} RTC_TypeDef; /*!< Size = 92 (0x5c) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc SPI1 (SPI1) + */ + +typedef struct { /*!< (@ 0x40000800) SPI1 Structure */ + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t MSTR : 1; /*!< [0..0] desc MSTR */ + __IOM uint32_t SSM : 1; /*!< [1..1] desc SSM */ + __IOM uint32_t CPHA : 1; /*!< [2..2] desc CPHA */ + __IOM uint32_t CPOL : 1; /*!< [3..3] desc CPOL */ + __IM uint32_t : 3; + __IOM uint32_t LSBF : 1; /*!< [7..7] desc LSBF */ + __IOM uint32_t WIDTH : 4; /*!< [11..8] desc WIDTH */ + __IOM uint32_t GAP : 4; /*!< [15..12] desc GAP */ + __IOM uint32_t MODE : 2; /*!< [17..16] desc MODE */ + __IOM uint32_t FLTEN : 1; /*!< [18..18] desc FLTEN */ + __IOM uint32_t MISOHD : 1; /*!< [19..19] desc MISOHD */ + __IOM uint32_t SMP : 1; /*!< [20..20] desc SMP */ + __IM uint32_t : 3; + __IOM uint32_t BR : 7; /*!< [30..24] desc BR */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000004) Control register2 */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t DMARX : 1; /*!< [1..1] desc DMARX */ + __IOM uint32_t DMATX : 1; /*!< [2..2] desc DMATX */ + } CR2_f; + } ; + + union { + __IOM uint32_t CR3; /*!< (@ 0x00000008) desc CR3 */ + + struct { + __IOM uint32_t HDOE : 1; /*!< [0..0] desc HDOE */ + } CR3_f; + } ; + + union { + __IOM uint32_t SSI; /*!< (@ 0x0000000C) Slave slect register */ + + struct { + __IOM uint32_t SSI : 1; /*!< [0..0] desc SSI */ + } SSI_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000010) Interrupt enable register */ + + struct { + __IOM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IOM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IOM uint32_t SSF : 1; /*!< [2..2] desc SSF */ + __IOM uint32_t SSR : 1; /*!< [3..3] desc SSR */ + __IOM uint32_t UD : 1; /*!< [4..4] desc UD */ + __IOM uint32_t OV : 1; /*!< [5..5] desc OV */ + __IOM uint32_t SSERR : 1; /*!< [6..6] desc SSERR */ + __IOM uint32_t MODF : 1; /*!< [7..7] desc MODF */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000014) Interrupt status register */ + + struct { + __IM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IM uint32_t SSF : 1; /*!< [2..2] desc SSF */ + __IM uint32_t SSR : 1; /*!< [3..3] desc SSR */ + __IM uint32_t UD : 1; /*!< [4..4] desc UD */ + __IM uint32_t OV : 1; /*!< [5..5] desc OV */ + __IM uint32_t SSERR : 1; /*!< [6..6] desc SSERR */ + __IM uint32_t MODF : 1; /*!< [7..7] desc MODF */ + __IM uint32_t BUSY : 1; /*!< [8..8] desc BUSY */ + __IM uint32_t SSLVL : 1; /*!< [9..9] desc SSLVL */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000018) Interrupt flag clear register */ + + struct { + __IOM uint32_t FLUSH : 1; /*!< [0..0] desc FLUSH */ + __IOM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IOM uint32_t SSF : 1; /*!< [2..2] desc SSF */ + __IOM uint32_t SSR : 1; /*!< [3..3] desc SSR */ + __IOM uint32_t UD : 1; /*!< [4..4] desc UD */ + __IOM uint32_t OV : 1; /*!< [5..5] desc OV */ + __IOM uint32_t SSERR : 1; /*!< [6..6] desc SSERR */ + __IOM uint32_t MODF : 1; /*!< [7..7] desc MODF */ + } ICR_f; + } ; + + union { + __IOM uint32_t DR; /*!< (@ 0x0000001C) Data register */ + + struct { + __IOM uint32_t DR : 16; /*!< [15..0] desc DR */ + } DR_f; + } ; +} SPI_TypeDef; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Ctrl (SYSCTRL) + */ + +typedef struct { /*!< (@ 0x40004000) SYSCTRL Structure */ + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control Reg0 */ + + struct { + __IOM uint32_t SYSCLK : 3; /*!< [2..0] desc SYSCLK */ + __IOM uint32_t PCLKPRS : 2; /*!< [4..3] desc PCLKPRS */ + __IOM uint32_t HCLKPRS : 3; /*!< [7..5] desc HCLKPRS */ + __IM uint32_t : 8; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR0_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000004) Control Reg1 */ + + struct { + __IOM uint32_t HSIEN : 1; /*!< [0..0] desc HSIEN */ + __IOM uint32_t HSEEN : 1; /*!< [1..1] desc HSEEN */ + __IOM uint32_t PLLEN : 1; /*!< [2..2] desc PLLEN */ + __IOM uint32_t LSIEN : 1; /*!< [3..3] desc LSIEN */ + __IOM uint32_t LSEEN : 1; /*!< [4..4] desc LSEEN */ + __IOM uint32_t LSELOCK : 1; /*!< [5..5] desc LSELOCK */ + __IOM uint32_t LSECCS : 1; /*!< [6..6] desc LSECCS */ + __IOM uint32_t HSECCS : 1; /*!< [7..7] desc HSECCS */ + __IOM uint32_t CLKCCS : 1; /*!< [8..8] desc CLKCCS */ + __IM uint32_t : 7; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000008) Control Reg2 */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t SWDIO : 1; /*!< [1..1] desc SWDIO */ + __IOM uint32_t LOCKUP : 1; /*!< [2..2] desc LOCKUP */ + __IOM uint32_t WAKEUPCLK : 1; /*!< [3..3] desc WAKEUPCLK */ + __IOM uint32_t FLASHWAIT : 3; /*!< [6..4] desc FLASHWAIT */ + __IM uint32_t : 3; + __IOM uint32_t HSEBRKEN : 1; /*!< [10..10] desc HSEBRKEN */ + __IOM uint32_t LSEBRKEN : 1; /*!< [11..11] desc LSEBRKEN */ + __IOM uint32_t CLLBRKEN : 1; /*!< [12..12] desc CLLBRKEN */ + __IOM uint32_t DSBRKEN : 1; /*!< [13..13] desc DSBRKEN */ + __IOM uint32_t LVDBRKEN : 1; /*!< [14..14] desc LVDBRKEN */ + __IOM uint32_t RAMBRKEN : 1; /*!< [15..15] desc RAMBRKEN */ + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR2_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x0000000C) Interupt Enable Reg */ + + struct { + __IOM uint32_t HSIRDY : 1; /*!< [0..0] desc HSIRDY */ + __IOM uint32_t HSERDY : 1; /*!< [1..1] desc HSERDY */ + __IOM uint32_t PLLRDY : 1; /*!< [2..2] desc PLLRDY */ + __IOM uint32_t LSIRDY : 1; /*!< [3..3] desc LSIRDY */ + __IOM uint32_t LSERDY : 1; /*!< [4..4] desc LSERDY */ + __IOM uint32_t LSEFAIL : 1; /*!< [5..5] desc LSEFAIL */ + __IOM uint32_t HSEFAIL : 1; /*!< [6..6] desc HSEFAIL */ + __IOM uint32_t LSEFAULT : 1; /*!< [7..7] desc LSEFAULT */ + __IOM uint32_t HSEFAULT : 1; /*!< [8..8] desc HSEFAULT */ + __IM uint32_t : 7; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000010) Interupt Status Reg */ + + struct { + __IM uint32_t HSIRDY : 1; /*!< [0..0] desc HSIRDY */ + __IM uint32_t HSERDY : 1; /*!< [1..1] desc HSERDY */ + __IM uint32_t PLLRDY : 1; /*!< [2..2] desc PLLRDY */ + __IM uint32_t LSIRDY : 1; /*!< [3..3] desc LSIRDY */ + __IM uint32_t LSERDY : 1; /*!< [4..4] desc LSERDY */ + __IM uint32_t LSEFAIL : 1; /*!< [5..5] desc LSEFAIL */ + __IM uint32_t HSEFAIL : 1; /*!< [6..6] desc HSEFAIL */ + __IM uint32_t LSEFAULT : 1; /*!< [7..7] desc LSEFAULT */ + __IM uint32_t HSEFAULT : 1; /*!< [8..8] desc HSEFAULT */ + __IM uint32_t : 2; + __IM uint32_t HSISTABLE : 1; /*!< [11..11] desc HSISTABLE */ + __IM uint32_t HSESTABLE : 1; /*!< [12..12] desc HSESTABLE */ + __IM uint32_t PLLSTABLE : 1; /*!< [13..13] desc PLLSTABLE */ + __IM uint32_t LSISTABLE : 1; /*!< [14..14] desc LSISTABLE */ + __IM uint32_t LSESTABLE : 1; /*!< [15..15] desc LSESTABLE */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000014) Interupt Clear Reg */ + + struct { + __IOM uint32_t HSIRDY : 1; /*!< [0..0] desc HSIRDY */ + __IOM uint32_t HSERDY : 1; /*!< [1..1] desc HSERDY */ + __IOM uint32_t PLLRDY : 1; /*!< [2..2] desc PLLRDY */ + __IOM uint32_t LSIRDY : 1; /*!< [3..3] desc LSIRDY */ + __IOM uint32_t LSERDY : 1; /*!< [4..4] desc LSERDY */ + __IOM uint32_t LSEFAIL : 1; /*!< [5..5] desc LSEFAIL */ + __IOM uint32_t HSEFAIL : 1; /*!< [6..6] desc HSEFAIL */ + __IOM uint32_t LSEFAULT : 1; /*!< [7..7] desc LSEFAULT */ + __IOM uint32_t HSEFAULT : 1; /*!< [8..8] desc HSEFAULT */ + } ICR_f; + } ; + + union { + __IOM uint32_t HSI; /*!< (@ 0x00000018) HSI Control Reg */ + + struct { + __IOM uint32_t TRIM : 11; /*!< [10..0] desc TRIM */ + __IOM uint32_t DIV : 4; /*!< [14..11] desc DIV */ + __IM uint32_t STABLE : 1; /*!< [15..15] desc STABLE */ + } HSI_f; + } ; + + union { + __IOM uint32_t HSE; /*!< (@ 0x0000001C) HEX Control Reg */ + + struct { + __IOM uint32_t DRIVER : 4; /*!< [3..0] desc DRIVER */ + __IOM uint32_t WAITCYCLE : 2; /*!< [5..4] desc WAITCYCLE */ + __IOM uint32_t MODE : 1; /*!< [6..6] desc MODE */ + __IOM uint32_t HEXENPOL : 1; /*!< [7..7] desc HEXENPOL */ + __IOM uint32_t DETCNT : 11; /*!< [18..8] desc DETCNT */ + __IM uint32_t STABLE : 1; /*!< [19..19] desc STABLE */ + __IOM uint32_t PDRIVER : 4; /*!< [23..20] desc PDRIVER */ + __IOM uint32_t DIGFLT : 1; /*!< [24..24] desc DIGFLT */ + } HSE_f; + } ; + + union { + __IOM uint32_t LSI; /*!< (@ 0x00000020) LSI Control Reg */ + + struct { + __IOM uint32_t TRIM : 9; /*!< [8..0] desc TRIM */ + __IM uint32_t : 1; + __IOM uint32_t WAITCYCLE : 2; /*!< [11..10] desc WAITCYCLE */ + __IM uint32_t : 3; + __IM uint32_t STABLE : 1; /*!< [15..15] desc STABLE */ + } LSI_f; + } ; + + union { + __IOM uint32_t LSE; /*!< (@ 0x00000024) LSE Control Reg */ + + struct { + __IOM uint32_t DRIVER : 4; /*!< [3..0] desc DRIVER */ + __IOM uint32_t WAITCYCLE : 2; /*!< [5..4] desc WAITCYCLE */ + __IOM uint32_t MODE : 1; /*!< [6..6] desc MODE */ + __IM uint32_t : 1; + __IOM uint32_t PDRIVER : 4; /*!< [11..8] desc PDRIVER */ + __IM uint32_t : 5; + __IOM uint32_t PINLOCK : 1; /*!< [17..17] desc PINLOCK */ + __IM uint32_t STABLE : 1; /*!< [18..18] desc STABLE */ + } LSE_f; + } ; + + union { + __IOM uint32_t PLL; /*!< (@ 0x00000028) PLL Control Reg */ + + struct { + __IOM uint32_t SOURCE : 1; /*!< [0..0] desc SOURCE */ + __IOM uint32_t DIV : 4; /*!< [4..1] desc DIV */ + __IOM uint32_t WAITCYCLE : 3; /*!< [7..5] desc WAITCYCLE */ + __IOM uint32_t MUL : 8; /*!< [15..8] desc MUL */ + __IM uint32_t STABLE : 1; /*!< [16..16] desc STABLE */ + } PLL_f; + } ; + + union { + __IOM uint32_t DEBUG; /*!< (@ 0x0000002C) Debug Control Reg */ + + struct { + __IOM uint32_t ATIM : 1; /*!< [0..0] desc ATIM */ + __IOM uint32_t GTIM1 : 1; /*!< [1..1] desc GTIM1 */ + __IOM uint32_t GTIM2 : 1; /*!< [2..2] desc GTIM2 */ + __IOM uint32_t GTIM3 : 1; /*!< [3..3] desc GTIM3 */ + __IOM uint32_t GTIM4 : 1; /*!< [4..4] desc GTIM4 */ + __IOM uint32_t BTIM123 : 1; /*!< [5..5] desc BTIM123 */ + __IOM uint32_t LPTIM : 1; /*!< [6..6] desc LPTIM */ + __IM uint32_t : 1; + __IOM uint32_t RTC : 1; /*!< [8..8] desc RTC */ + __IOM uint32_t IWDT : 1; /*!< [9..9] desc IWDT */ + __IOM uint32_t WWDT : 1; /*!< [10..10] desc WWDT */ + __IOM uint32_t HALLTIM : 1; /*!< [11..11] desc HALLTIM */ + } DEBUG_f; + } ; + + union { + __IOM uint32_t AHBEN; /*!< (@ 0x00000030) AHB Clock Control Reg */ + + struct { + __IOM uint32_t DMA : 1; /*!< [0..0] desc DMA */ + __IOM uint32_t FLASH : 1; /*!< [1..1] desc FLASH */ + __IOM uint32_t CRC : 1; /*!< [2..2] desc CRC */ + __IOM uint32_t EAU : 1; /*!< [3..3] desc EAU */ + __IOM uint32_t GPIOA : 1; /*!< [4..4] desc GPIOA */ + __IOM uint32_t GPIOB : 1; /*!< [5..5] desc GPIOB */ + __IOM uint32_t GPIOC : 1; /*!< [6..6] desc GPIOC */ + __IOM uint32_t GPIOF : 1; /*!< [7..7] desc GPIOF */ + __IOM uint32_t CORDIC : 1; /*!< [8..8] desc CORDIC */ + __IM uint32_t : 7; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } AHBEN_f; + } ; + + union { + __IOM uint32_t APBEN2; /*!< (@ 0x00000034) APB Clock Control Reg2 */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t RTC : 1; /*!< [1..1] desc RTC */ + __IOM uint32_t BTIM123 : 1; /*!< [2..2] desc BTIM123 */ + __IM uint32_t : 1; + __IOM uint32_t IWDT : 1; /*!< [4..4] desc IWDT */ + __IOM uint32_t WWDT : 1; /*!< [5..5] desc WWDT */ + __IOM uint32_t I2C1 : 1; /*!< [6..6] desc I2C1 */ + __IOM uint32_t LPTIM : 1; /*!< [7..7] desc LPTIM */ + __IM uint32_t : 1; + __IOM uint32_t OPA : 1; /*!< [9..9] desc OPA */ + __IOM uint32_t DAC : 1; /*!< [10..10] desc DAC */ + __IOM uint32_t I2C2 : 1; /*!< [11..11] desc I2C2 */ + __IOM uint32_t HALLTIM : 1; /*!< [12..12] desc HALLTIM */ + __IM uint32_t : 3; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } APBEN2_f; + } ; + + union { + __IOM uint32_t APBEN1; /*!< (@ 0x00000038) APB Clock Control Reg1 */ + + struct { + __IOM uint32_t ADC : 1; /*!< [0..0] desc ADC */ + __IOM uint32_t VC : 1; /*!< [1..1] desc VC */ + __IOM uint32_t SPI1 : 1; /*!< [2..2] desc SPI1 */ + __IOM uint32_t UART1 : 1; /*!< [3..3] desc UART1 */ + __IOM uint32_t UART2 : 1; /*!< [4..4] desc UART2 */ + __IOM uint32_t ATIM : 1; /*!< [5..5] desc ATIM */ + __IOM uint32_t GTIM1 : 1; /*!< [6..6] desc GTIM1 */ + __IOM uint32_t GTIM2 : 1; /*!< [7..7] desc GTIM2 */ + __IOM uint32_t UART3 : 1; /*!< [8..8] desc UART3 */ + __IM uint32_t : 2; + __IOM uint32_t GTIM3 : 1; /*!< [11..11] desc GTIM3 */ + __IOM uint32_t GTIM4 : 1; /*!< [12..12] desc GTIM4 */ + __IOM uint32_t SPI2 : 1; /*!< [13..13] desc SPI2 */ + __IOM uint32_t SPI3 : 1; /*!< [14..14] desc SPI3 */ + __IM uint32_t : 1; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } APBEN1_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t AHBRST; /*!< (@ 0x00000040) AHB Reset Control Reg */ + + struct { + __IOM uint32_t DMA : 1; /*!< [0..0] desc DMA */ + __IOM uint32_t FLASH : 1; /*!< [1..1] desc FLASH */ + __IOM uint32_t CRC : 1; /*!< [2..2] desc CRC */ + __IOM uint32_t EAU : 1; /*!< [3..3] desc EAU */ + __IOM uint32_t GPIOA : 1; /*!< [4..4] desc GPIOA */ + __IOM uint32_t GPIOB : 1; /*!< [5..5] desc GPIOB */ + __IOM uint32_t GPIOC : 1; /*!< [6..6] desc GPIOC */ + __IOM uint32_t GPIOF : 1; /*!< [7..7] desc GPIOF */ + __IOM uint32_t CORDIC : 1; /*!< [8..8] desc CORDIC */ + } AHBRST_f; + } ; + + union { + __IOM uint32_t APBRST2; /*!< (@ 0x00000044) APB Reset Control Reg2 */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t RTC : 1; /*!< [1..1] desc RTC */ + __IOM uint32_t BTIM123 : 1; /*!< [2..2] desc BTIM123 */ + __IM uint32_t : 1; + __IOM uint32_t IWDT : 1; /*!< [4..4] desc IWDT */ + __IOM uint32_t WWDT : 1; /*!< [5..5] desc WWDT */ + __IOM uint32_t I2C1 : 1; /*!< [6..6] desc I2C1 */ + __IOM uint32_t LPTIM : 1; /*!< [7..7] desc LPTIM */ + __IM uint32_t : 1; + __IOM uint32_t OPA : 1; /*!< [9..9] desc OPA */ + __IOM uint32_t DAC : 1; /*!< [10..10] desc DAC */ + __IOM uint32_t I2C2 : 1; /*!< [11..11] desc I2C2 */ + __IOM uint32_t HALLTIM : 1; /*!< [12..12] desc HALLTIM */ + } APBRST2_f; + } ; + + union { + __IOM uint32_t APBRST1; /*!< (@ 0x00000048) APB Reset Control Reg1 */ + + struct { + __IOM uint32_t ADC : 1; /*!< [0..0] desc ADC */ + __IOM uint32_t VC : 1; /*!< [1..1] desc VC */ + __IOM uint32_t SPI1 : 1; /*!< [2..2] desc SPI1 */ + __IOM uint32_t UART1 : 1; /*!< [3..3] desc UART1 */ + __IOM uint32_t UART2 : 1; /*!< [4..4] desc UART2 */ + __IOM uint32_t ATIM : 1; /*!< [5..5] desc ATIM */ + __IOM uint32_t GTIM1 : 1; /*!< [6..6] desc GTIM1 */ + __IOM uint32_t GTIM2 : 1; /*!< [7..7] desc GTIM2 */ + __IOM uint32_t UART3 : 1; /*!< [8..8] desc UART3 */ + __IM uint32_t : 2; + __IOM uint32_t GTIM3 : 1; /*!< [11..11] desc GTIM3 */ + __IOM uint32_t GTIM4 : 1; /*!< [12..12] desc GTIM4 */ + __IOM uint32_t SPI2 : 1; /*!< [13..13] desc SPI2 */ + __IOM uint32_t SPI3 : 1; /*!< [14..14] desc SPI3 */ + } APBRST1_f; + } ; + + union { + __IOM uint32_t RESETFLAG; /*!< (@ 0x0000004C) Reset Status Reg */ + + struct { + __IOM uint32_t POR : 1; /*!< [0..0] desc POR */ + __IM uint32_t : 2; + __IOM uint32_t LVD : 1; /*!< [3..3] desc LVD */ + __IOM uint32_t IWDT : 1; /*!< [4..4] desc IWDT */ + __IOM uint32_t WWDT : 1; /*!< [5..5] desc WWDT */ + __IOM uint32_t RSTB : 1; /*!< [6..6] desc RSTB */ + __IM uint32_t : 1; + __IOM uint32_t LOCKUP : 1; /*!< [8..8] desc LOCKUP */ + __IOM uint32_t SYSRESETREQ : 1; /*!< [9..9] desc SYSRESETREQ */ + } RESETFLAG_f; + } ; + __IM uint32_t RESERVED1[8]; + + union { + __IOM uint32_t MCO; /*!< (@ 0x00000070) Master Clock Output Control Reg */ + + struct { + __IOM uint32_t SOURCE : 4; /*!< [3..0] desc SOURCE */ + __IOM uint32_t DIV : 4; /*!< [7..4] desc DIV */ + } MCO_f; + } ; +} SYSCTRL_TypeDef; /*!< Size = 116 (0x74) */ + + + +/* =========================================================================================================================== */ +/* ================ VC1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc VC1 (VC1) + */ + +typedef struct { /*!< (@ 0x40000084) VC1 Structure */ + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control register0 */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t RESP : 1; /*!< [1..1] desc RESP */ + __IM uint32_t : 1; + __IOM uint32_t HYS : 1; /*!< [3..3] desc HYS */ + __IM uint32_t : 1; + __IOM uint32_t IE : 1; /*!< [5..5] desc IE */ + __IOM uint32_t POL : 1; /*!< [6..6] desc POL */ + __IOM uint32_t WINDOW : 1; /*!< [7..7] desc WINDOW */ + __IOM uint32_t INN : 2; /*!< [9..8] desc INN */ + __IM uint32_t : 2; + __IOM uint32_t INP : 2; /*!< [13..12] desc INP */ + } CR0_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000004) Control register1 */ + + struct { + __IOM uint32_t FLTTIME : 4; /*!< [3..0] desc FLTTIME */ + __IOM uint32_t FLTCLK : 1; /*!< [4..4] desc FLTCLK */ + __IOM uint32_t FALLIE : 1; /*!< [5..5] desc FALLIE */ + __IOM uint32_t RISEIE : 1; /*!< [6..6] desc RISEIE */ + __IOM uint32_t HIGHIE : 1; /*!< [7..7] desc HIGHIE */ + __IOM uint32_t BLANKTIME : 3; /*!< [10..8] desc BLANKTIME */ + __IOM uint32_t BLANKLVL : 1; /*!< [11..11] desc BLANKLVL */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000008) Control register1 */ + + struct { + __IOM uint32_t ATIMTRGO : 1; /*!< [0..0] desc ATIM1TRGO */ + __IOM uint32_t ATIMTRGO2 : 1; /*!< [1..1] desc ATIM1TRGO2 */ + __IOM uint32_t ATIMOC1REFC : 1; /*!< [2..2] desc ATIM1OC1REFC */ + __IOM uint32_t ATIMOC2REFC : 1; /*!< [3..3] desc ATIM1OC2REFC */ + __IOM uint32_t ATIMOC3REFC : 1; /*!< [4..4] desc ATIM1OC3REFC */ + __IOM uint32_t ATIMOC4REFC : 1; /*!< [5..5] desc ATIM1OC4REFC */ + __IOM uint32_t ATIMOC5REFC : 1; /*!< [6..6] desc ATIM1OC5REFC */ + __IOM uint32_t ATIMOC6REFC : 1; /*!< [7..7] desc ATIM1OC6REFC */ + __IOM uint32_t GTIM1TRGO : 1; /*!< [8..8] desc GTIM1TRGO */ + __IOM uint32_t GTIM1OC1REFC : 1; /*!< [9..9] desc GTIM1OC1REFC */ + __IOM uint32_t GTIM1OC2REFC : 1; /*!< [10..10] desc GTIM1OC2REFC */ + __IOM uint32_t GTIM1OC3REFC : 1; /*!< [11..11] desc GTIM1OC3REFC */ + __IOM uint32_t GTIM1OC4REFC : 1; /*!< [12..12] desc GTIM1OC4REFC */ + __IOM uint32_t GTIM2TRGO : 1; /*!< [13..13] desc GTIM2TRGO */ + __IOM uint32_t GTIM2OC1REFC : 1; /*!< [14..14] desc GTIM2OC1REFC */ + __IOM uint32_t GTIM2OC2REFC : 1; /*!< [15..15] desc GTIM2OC2REFC */ + __IOM uint32_t GTIM2OC3REFC : 1; /*!< [16..16] desc GTIM2OC3REFC */ + __IOM uint32_t GTIM2OC4REFC : 1; /*!< [17..17] desc GTIM2OC4REFC */ + __IOM uint32_t GTIM3TRGO : 1; /*!< [18..18] desc GTIM3TRGO */ + __IOM uint32_t GTIM3OC1REFC : 1; /*!< [19..19] desc GTIM3OC1REFC */ + __IOM uint32_t GTIM3OC2REFC : 1; /*!< [20..20] desc GTIM3OC2REFC */ + __IOM uint32_t GTIM3OC3REFC : 1; /*!< [21..21] desc GTIM3OC3REFC */ + __IOM uint32_t GTIM3OC4REFC : 1; /*!< [22..22] desc GTIM3OC4REFC */ + __IOM uint32_t GTIM4TRGO : 1; /*!< [23..23] desc GTIM4TRGO */ + __IOM uint32_t GTIM4OC1REFC : 1; /*!< [24..24] desc GTIM4OC1REFC */ + __IOM uint32_t GTIM4OC2REFC : 1; /*!< [25..25] desc GTIM4OC2REFC */ + __IOM uint32_t GTIM4OC3REFC : 1; /*!< [26..26] desc GTIM4OC3REFC */ + __IOM uint32_t GTIM4OC4REFC : 1; /*!< [27..27] desc GTIM4OC4REFC */ + __IOM uint32_t BTIM1TRGO : 1; /*!< [28..28] desc BTIM1TRGO */ + __IOM uint32_t BTIM2TRGO : 1; /*!< [29..29] desc BTIM2TRGO */ + __IOM uint32_t BTIM3TRGO : 1; /*!< [30..30] desc BTIM3TRGO */ + __IOM uint32_t HALLTIM1TRGO : 1; /*!< [31..31] desc HALLTIM1TRGO */ + } CR2_f; + } ; + + union { + __IOM uint32_t SR; /*!< (@ 0x0000000C) Status register */ + + struct { + __IOM uint32_t INTF : 1; /*!< [0..0] desc INTF */ + __IM uint32_t FLTV : 1; /*!< [1..1] desc FLTV */ + } SR_f; + } ; +} VC_TypeDef; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ VC12REF ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc VC12REF (VC12REF) + */ + +typedef struct { /*!< (@ 0x40000080) VC12REF Structure */ + + union { + __IOM uint32_t REF; /*!< (@ 0x00000000) VCREF Control register */ + + struct { + __IOM uint32_t DIV : 3; /*!< [2..0] desc DIV */ + __IM uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [4..4] desc EN */ + __IOM uint32_t VIN : 1; /*!< [5..5] desc VIN */ + } REF_f; + } ; +} VCREF_TypeDef; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ WWDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc WWDT (WWDT) + */ + +typedef struct { /*!< WWDT Structure */ + + union { + __IOM uint32_t CR0; /*!< Control register0 */ + + struct { + __IOM uint32_t WCNT : 7; /*!< desc WCNT */ + __IOM uint32_t EN : 1; /*!< desc EN */ + } CR0_f; + } ; + + union { + __IOM uint32_t CR1; /*!< Control register1 */ + + struct { + __IOM uint32_t WINR : 7; /*!< desc WINR */ + __IOM uint32_t PRS : 3; /*!< desc PRESCALE */ + __IOM uint32_t IE : 1; /*!< desc IE */ + } CR1_f; + } ; + + union { + __IOM uint32_t SR; /*!< status register */ + + struct { + __IOM uint32_t POV : 1; /*!< desc POV */ + } SR_f; + } ; +} WWDT_TypeDef; /*!< Size = 12 (0xc) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define ADC1_BASE 0x40000000UL +#define ADC2_BASE 0x40000100UL +#define ATIM_BASE 0x40001400UL +#define BGR_BASE 0x400000FCUL +#define BTIM1_BASE 0x40004800UL +#define BTIM2_BASE 0x40004840UL +#define BTIM3_BASE 0x40004880UL +#define CORDIC_BASE 0x40023400UL +#define CRC_BASE 0x40023000UL +#define DAC_BASE 0x400000C0UL +#define DMA_BASE 0x40020000UL +#define DMACHANNEL1_BASE 0x40020020UL +#define DMACHANNEL2_BASE 0x40020040UL +#define DMACHANNEL3_BASE 0x40020060UL +#define DMACHANNEL4_BASE 0x40020080UL +#define EAU_BASE 0x40023200UL +#define FLASH_BASE 0x40022000UL +#define GPIOA_BASE 0x48000000UL +#define GPIOB_BASE 0x48000100UL +#define GPIOC_BASE 0x48000200UL +#define GPIOF_BASE 0x48000300UL +#define GTIM1_BASE 0x40001800UL +#define GTIM2_BASE 0x40001C00UL +#define GTIM3_BASE 0x40002400UL +#define GTIM4_BASE 0x40002800UL +#define HALLTIM_BASE 0x40006400UL +#define I2C1_BASE 0x40005800UL +#define I2C2_BASE 0x40005C00UL +#define IRMOD_BASE 0x40004080UL +#define IWDT_BASE 0x40005000UL +#define LPTIM_BASE 0x40006000UL +#define UART1_BASE 0x40000C00UL +#define UART2_BASE 0x40001000UL +#define UART3_BASE 0x40002000UL +#define LVD_BASE 0x400000A4UL +#define OPA1_BASE 0x400000B0UL +#define OPA2_BASE 0x400000B8UL +#define RAM_BASE 0x40022400UL +#define RTC_BASE 0x40004400UL +#define SPI1_BASE 0x40000800UL +#define SPI2_BASE 0x40000400UL +#define SPI3_BASE 0x40003400UL +#define SYSCTRL_BASE 0x40004000UL +#define VC1_BASE 0x40000084UL +#define VC12REF_BASE 0x40000080UL +#define VC2_BASE 0x40000094UL +#define VC3_BASE 0x40000184UL +#define VC34REF_BASE 0x40000180UL +#define VC4_BASE 0x40000194UL +#define WWDT_BASE 0x40005400UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define CW_ADC1 ((ADC_TypeDef*) ADC1_BASE) +#define CW_ADC2 ((ADC_TypeDef*) ADC2_BASE) +#define CW_ATIM ((ATIM_TypeDef*) ATIM_BASE) +#define CW_BGR ((BGR_TypeDef*) BGR_BASE) +#define CW_BTIM1 ((BTIM_TypeDef*) BTIM1_BASE) +#define CW_BTIM2 ((BTIM_TypeDef*) BTIM2_BASE) +#define CW_BTIM3 ((BTIM_TypeDef*) BTIM3_BASE) +#define CW_CORDIC ((CORDIC_TypeDef*) CORDIC_BASE) +#define CW_CRC ((CRC_TypeDef*) CRC_BASE) +#define CW_DAC ((DAC_TypeDef*) DAC_BASE) +#define CW_DMA ((DMA_TypeDef*) DMA_BASE) +#define CW_DMACHANNEL1 ((DMACHANNEL_TypeDef*) DMACHANNEL1_BASE) +#define CW_DMACHANNEL2 ((DMACHANNEL_TypeDef*) DMACHANNEL2_BASE) +#define CW_DMACHANNEL3 ((DMACHANNEL_TypeDef*) DMACHANNEL3_BASE) +#define CW_DMACHANNEL4 ((DMACHANNEL_TypeDef*) DMACHANNEL4_BASE) +#define CW_EAU ((EAU_TypeDef*) EAU_BASE) +#define CW_FLASH ((FLASH_TypeDef*) FLASH_BASE) +#define CW_GPIOA ((GPIO_TypeDef*) GPIOA_BASE) +#define CW_GPIOB ((GPIO_TypeDef*) GPIOB_BASE) +#define CW_GPIOC ((GPIO_TypeDef*) GPIOC_BASE) +#define CW_GPIOF ((GPIO_TypeDef*) GPIOF_BASE) +#define CW_GTIM1 ((GTIM_TypeDef*) GTIM1_BASE) +#define CW_GTIM2 ((GTIM_TypeDef*) GTIM2_BASE) +#define CW_GTIM3 ((GTIM_TypeDef*) GTIM3_BASE) +#define CW_GTIM4 ((GTIM_TypeDef*) GTIM4_BASE) +#define CW_HALLTIM ((HALLTIM_TypeDef*) HALLTIM_BASE) +#define CW_I2C1 ((I2C_TypeDef*) I2C1_BASE) +#define CW_I2C2 ((I2C_TypeDef*) I2C2_BASE) +#define CW_IRMOD ((IRMOD_TypeDef*) IRMOD_BASE) +#define CW_IWDT ((IWDT_TypeDef*) IWDT_BASE) +#define CW_LPTIM ((LPTIM_TypeDef*) LPTIM_BASE) +#define CW_UART1 ((UART_TypeDef*) UART1_BASE) +#define CW_UART2 ((UART_TypeDef*) UART2_BASE) +#define CW_UART3 ((UART_TypeDef*) UART3_BASE) +#define CW_LVD ((LVD_TypeDef*) LVD_BASE) +#define CW_OPA1 ((OPA_TypeDef*) OPA1_BASE) +#define CW_OPA2 ((OPA_TypeDef*) OPA2_BASE) +#define CW_RAM ((RAM_TypeDef*) RAM_BASE) +#define CW_RTC ((RTC_TypeDef*) RTC_BASE) +#define CW_SPI1 ((SPI_TypeDef*) SPI1_BASE) +#define CW_SPI2 ((SPI_TypeDef*) SPI2_BASE) +#define CW_SPI3 ((SPI_TypeDef*) SPI3_BASE) +#define CW_SYSCTRL ((SYSCTRL_TypeDef*) SYSCTRL_BASE) +#define CW_VC1 ((VC_TypeDef*) VC1_BASE) +#define CW_VC12REF ((VCREF_TypeDef*) VC12REF_BASE) +#define CW_VC2 ((VC_TypeDef*) VC2_BASE) +#define CW_VC3 ((VC_TypeDef*) VC3_BASE) +#define CW_VC34REF ((VCREF_TypeDef*) VC34REF_BASE) +#define CW_VC4 ((VC_TypeDef*) VC4_BASE) +#define CW_WWDT ((WWDT_TypeDef*) WWDT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define ADCx_CR_SLAVE_Pos (7UL) /*!< SLAVE (Bit 7) */ +#define ADCx_CR_SLAVE_Msk (0x80UL) /*!< SLAVE (Bitfield-Mask: 0x01) */ +#define ADCx_CR_ENS_Pos (4UL) /*!< ENS (Bit 4) */ +#define ADCx_CR_ENS_Msk (0x70UL) /*!< ENS (Bitfield-Mask: 0x07) */ +#define ADCx_CR_CLK_Pos (2UL) /*!< CLKSRC (Bit 2) */ +#define ADCx_CR_CLK_Msk (0xcUL) /*!< CLKSRC (Bitfield-Mask: 0x03) */ +#define ADCx_CR_CONT_Pos (1UL) /*!< CONT (Bit 1) */ +#define ADCx_CR_CONT_Msk (0x2UL) /*!< CONT (Bitfield-Mask: 0x01) */ +#define ADCx_CR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define ADCx_CR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= START ========================================================= */ +#define ADCx_START_START_Pos (0UL) /*!< START (Bit 0) */ +#define ADCx_START_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= AWDTR ========================================================= */ +#define ADCx_AWDTR_VTH_Pos (16UL) /*!< VTH (Bit 16) */ +#define ADCx_AWDTR_VTH_Msk (0xfff0000UL) /*!< VTH (Bitfield-Mask: 0xfff) */ +#define ADCx_AWDTR_VTL_Pos (0UL) /*!< VTL (Bit 0) */ +#define ADCx_AWDTR_VTL_Msk (0xfffUL) /*!< VTL (Bitfield-Mask: 0xfff) */ +/* ========================================================= AWDCR ========================================================= */ +#define ADCx_AWDCR_IN15_Pos (15UL) /*!< IN15 (Bit 15) */ +#define ADCx_AWDCR_IN15_Msk (0x8000UL) /*!< IN15 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN14_Pos (14UL) /*!< IN14 (Bit 14) */ +#define ADCx_AWDCR_IN14_Msk (0x4000UL) /*!< IN14 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN13_Pos (13UL) /*!< IN13 (Bit 13) */ +#define ADCx_AWDCR_IN13_Msk (0x2000UL) /*!< IN13 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN12_Pos (12UL) /*!< IN12 (Bit 12) */ +#define ADCx_AWDCR_IN12_Msk (0x1000UL) /*!< IN12 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN11_Pos (11UL) /*!< IN11 (Bit 11) */ +#define ADCx_AWDCR_IN11_Msk (0x800UL) /*!< IN11 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN10_Pos (10UL) /*!< IN10 (Bit 10) */ +#define ADCx_AWDCR_IN10_Msk (0x400UL) /*!< IN10 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN9_Pos (9UL) /*!< IN9 (Bit 9) */ +#define ADCx_AWDCR_IN9_Msk (0x200UL) /*!< IN9 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN8_Pos (8UL) /*!< IN8 (Bit 8) */ +#define ADCx_AWDCR_IN8_Msk (0x100UL) /*!< IN8 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN7_Pos (7UL) /*!< IN7 (Bit 7) */ +#define ADCx_AWDCR_IN7_Msk (0x80UL) /*!< IN7 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN6_Pos (6UL) /*!< IN6 (Bit 6) */ +#define ADCx_AWDCR_IN6_Msk (0x40UL) /*!< IN6 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN5_Pos (5UL) /*!< IN5 (Bit 5) */ +#define ADCx_AWDCR_IN5_Msk (0x20UL) /*!< IN5 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN4_Pos (4UL) /*!< IN4 (Bit 4) */ +#define ADCx_AWDCR_IN4_Msk (0x10UL) /*!< IN4 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN3_Pos (3UL) /*!< IN3 (Bit 3) */ +#define ADCx_AWDCR_IN3_Msk (0x8UL) /*!< IN3 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN2_Pos (2UL) /*!< IN2 (Bit 2) */ +#define ADCx_AWDCR_IN2_Msk (0x4UL) /*!< IN2 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN1_Pos (1UL) /*!< IN1 (Bit 1) */ +#define ADCx_AWDCR_IN1_Msk (0x2UL) /*!< IN1 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN0_Pos (0UL) /*!< IN0 (Bit 0) */ +#define ADCx_AWDCR_IN0_Msk (0x1UL) /*!< IN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== TRIGGER ======================================================== */ +#define ADCx_TRIGGER_HALLTIMTRGO_Pos (31UL) /*!< HALLTIMTRGO (Bit 31) */ +#define ADCx_TRIGGER_HALLTIMTRGO_Msk (0x80000000UL) /*!< HALLTIMTRGO (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_BTIM3TRGO_Pos (30UL) /*!< BTIM3TRGO (Bit 30) */ +#define ADCx_TRIGGER_BTIM3TRGO_Msk (0x40000000UL) /*!< BTIM3TRGO (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_BTIM2TRGO_Pos (29UL) /*!< BTIM2TRGO (Bit 29) */ +#define ADCx_TRIGGER_BTIM2TRGO_Msk (0x20000000UL) /*!< BTIM2TRGO (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_BTIM1TRGO_Pos (28UL) /*!< BTIM1TRGO (Bit 28) */ +#define ADCx_TRIGGER_BTIM1TRGO_Msk (0x10000000UL) /*!< BTIM1TRGO (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM4OC4REFC_Pos (27UL) /*!< GTIM4OC4REFC (Bit 27) */ +#define ADCx_TRIGGER_GTIM4OC4REFC_Msk (0x8000000UL) /*!< GTIM4OC4REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM4OC3REFC_Pos (26UL) /*!< GTIM4OC3REFC (Bit 26) */ +#define ADCx_TRIGGER_GTIM4OC3REFC_Msk (0x4000000UL) /*!< GTIM4OC3REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM4OC2REFC_Pos (25UL) /*!< GTIM4OC2REFC (Bit 25) */ +#define ADCx_TRIGGER_GTIM4OC2REFC_Msk (0x2000000UL) /*!< GTIM4OC2REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM4OC1REFC_Pos (24UL) /*!< GTIM4OC1REFC (Bit 24) */ +#define ADCx_TRIGGER_GTIM4OC1REFC_Msk (0x1000000UL) /*!< GTIM4OC1REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM4TRGO_Pos (23UL) /*!< GTIM4TRGO (Bit 23) */ +#define ADCx_TRIGGER_GTIM4TRGO_Msk (0x800000UL) /*!< GTIM4TRGO (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM3OC4REFC_Pos (22UL) /*!< GTIM3OC4REFC (Bit 22) */ +#define ADCx_TRIGGER_GTIM3OC4REFC_Msk (0x400000UL) /*!< GTIM3OC4REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM3OC3REFC_Pos (21UL) /*!< GTIM3OC3REFC (Bit 21) */ +#define ADCx_TRIGGER_GTIM3OC3REFC_Msk (0x200000UL) /*!< GTIM3OC3REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM3OC2REFC_Pos (20UL) /*!< GTIM3OC2REFC (Bit 20) */ +#define ADCx_TRIGGER_GTIM3OC2REFC_Msk (0x100000UL) /*!< GTIM3OC2REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM3OC1REFC_Pos (19UL) /*!< GTIM3OC1REFC (Bit 19) */ +#define ADCx_TRIGGER_GTIM3OC1REFC_Msk (0x80000UL) /*!< GTIM3OC1REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM3TRGO_Pos (18UL) /*!< GTIM3TRGO (Bit 18) */ +#define ADCx_TRIGGER_GTIM3TRGO_Msk (0x40000UL) /*!< GTIM3TRGO (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM2OC4REFC_Pos (17UL) /*!< GTIM2OC4REFC (Bit 17) */ +#define ADCx_TRIGGER_GTIM2OC4REFC_Msk (0x20000UL) /*!< GTIM2OC4REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM2OC3REFC_Pos (16UL) /*!< GTIM2OC3REFC (Bit 16) */ +#define ADCx_TRIGGER_GTIM2OC3REFC_Msk (0x10000UL) /*!< GTIM2OC3REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM2OC2REFC_Pos (15UL) /*!< GTIM2OC2REFC (Bit 15) */ +#define ADCx_TRIGGER_GTIM2OC2REFC_Msk (0x8000UL) /*!< GTIM2OC2REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM2OC1REFC_Pos (14UL) /*!< GTIM2OC1REFC (Bit 14) */ +#define ADCx_TRIGGER_GTIM2OC1REFC_Msk (0x4000UL) /*!< GTIM2OC1REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM2TRGO_Pos (13UL) /*!< GTIM2TRGO (Bit 13) */ +#define ADCx_TRIGGER_GTIM2TRGO_Msk (0x2000UL) /*!< GTIM2TRGO (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM1OC4REFC_Pos (12UL) /*!< GTIM1OC4REFC (Bit 12) */ +#define ADCx_TRIGGER_GTIM1OC4REFC_Msk (0x1000UL) /*!< GTIM1OC4REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM1OC3REFC_Pos (11UL) /*!< GTIM1OC3REFC (Bit 11) */ +#define ADCx_TRIGGER_GTIM1OC3REFC_Msk (0x800UL) /*!< GTIM1OC3REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM1OC2REFC_Pos (10UL) /*!< GTIM1OC2REFC (Bit 10) */ +#define ADCx_TRIGGER_GTIM1OC2REFC_Msk (0x400UL) /*!< GTIM1OC2REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM1OC1REFC_Pos (9UL) /*!< GTIM1OC1REFC (Bit 9) */ +#define ADCx_TRIGGER_GTIM1OC1REFC_Msk (0x200UL) /*!< GTIM1OC1REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM1TRGO_Pos (8UL) /*!< GTIM1TRGO (Bit 8) */ +#define ADCx_TRIGGER_GTIM1TRGO_Msk (0x100UL) /*!< GTIM1TRGO (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_ATIMOC6REFC_Pos (7UL) /*!< ATIMOC6REFC (Bit 7) */ +#define ADCx_TRIGGER_ATIMOC6REFC_Msk (0x80UL) /*!< ATIMOC6REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_ATIMOC5REFC_Pos (6UL) /*!< ATIMOC5REFC (Bit 6) */ +#define ADCx_TRIGGER_ATIMOC5REFC_Msk (0x40UL) /*!< ATIMOC5REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_ATIMOC4REFC_Pos (5UL) /*!< ATIMOC4REFC (Bit 5) */ +#define ADCx_TRIGGER_ATIMOC4REFC_Msk (0x20UL) /*!< ATIMOC4REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_ATIMOC3REFC_Pos (4UL) /*!< ATIMOC3REFC (Bit 4) */ +#define ADCx_TRIGGER_ATIMOC3REFC_Msk (0x10UL) /*!< ATIMOC3REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_ATIMOC2REFC_Pos (3UL) /*!< ATIMOC2REFC (Bit 3) */ +#define ADCx_TRIGGER_ATIMOC2REFC_Msk (0x8UL) /*!< ATIMOC2REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_ATIMOC1REFC_Pos (2UL) /*!< ATIMOC1REFC (Bit 2) */ +#define ADCx_TRIGGER_ATIMOC1REFC_Msk (0x4UL) /*!< ATIMOC1REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_ATIMTRGO2_Pos (1UL) /*!< ATIMTRGO2 (Bit 1) */ +#define ADCx_TRIGGER_ATIMTRGO2_Msk (0x2UL) /*!< ATIMTRGO2 (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_ATIMTRGO_Pos (0UL) /*!< ATIMTRGO (Bit 0) */ +#define ADCx_TRIGGER_ATIMTRGO_Msk (0x1UL) /*!< ATIMTRGO (Bitfield-Mask: 0x01) */ +/* ======================================================== SAMPLE ========================================================= */ +#define ADCx_SAMPLE_SQRCH7_Pos (28UL) /*!< SQRCH7 (Bit 28) */ +#define ADCx_SAMPLE_SQRCH7_Msk (0xf0000000UL) /*!< SQRCH7 (Bitfield-Mask: 0x0f) */ +#define ADCx_SAMPLE_SQRCH6_Pos (24UL) /*!< SQRCH6 (Bit 24) */ +#define ADCx_SAMPLE_SQRCH6_Msk (0xf000000UL) /*!< SQRCH6 (Bitfield-Mask: 0x0f) */ +#define ADCx_SAMPLE_SQRCH5_Pos (20UL) /*!< SQRCH5 (Bit 20) */ +#define ADCx_SAMPLE_SQRCH5_Msk (0xf00000UL) /*!< SQRCH5 (Bitfield-Mask: 0x0f) */ +#define ADCx_SAMPLE_SQRCH4_Pos (16UL) /*!< SQRCH4 (Bit 16) */ +#define ADCx_SAMPLE_SQRCH4_Msk (0xf0000UL) /*!< SQRCH4 (Bitfield-Mask: 0x0f) */ +#define ADCx_SAMPLE_SQRCH3_Pos (12UL) /*!< SQRCH3 (Bit 12) */ +#define ADCx_SAMPLE_SQRCH3_Msk (0xf000UL) /*!< SQRCH3 (Bitfield-Mask: 0x0f) */ +#define ADCx_SAMPLE_SQRCH2_Pos (8UL) /*!< SQRCH2 (Bit 8) */ +#define ADCx_SAMPLE_SQRCH2_Msk (0xf00UL) /*!< SQRCH2 (Bitfield-Mask: 0x0f) */ +#define ADCx_SAMPLE_SQRCH1_Pos (4UL) /*!< SQRCH1 (Bit 4) */ +#define ADCx_SAMPLE_SQRCH1_Msk (0xf0UL) /*!< SQRCH1 (Bitfield-Mask: 0x0f) */ +#define ADCx_SAMPLE_SQRCH0_Pos (0UL) /*!< SQRCH0 (Bit 0) */ +#define ADCx_SAMPLE_SQRCH0_Msk (0xfUL) /*!< SQRCH0 (Bitfield-Mask: 0x0f) */ +/* ======================================================== SQRCFR ========================================================= */ +#define ADCx_SQRCFR_SQRCH7_Pos (28UL) /*!< SQRCH7 (Bit 28) */ +#define ADCx_SQRCFR_SQRCH7_Msk (0xf0000000UL) /*!< SQRCH7 (Bitfield-Mask: 0x0f) */ +#define ADCx_SQRCFR_SQRCH6_Pos (24UL) /*!< SQRCH6 (Bit 24) */ +#define ADCx_SQRCFR_SQRCH6_Msk (0xf000000UL) /*!< SQRCH6 (Bitfield-Mask: 0x0f) */ +#define ADCx_SQRCFR_SQRCH5_Pos (20UL) /*!< SQRCH5 (Bit 20) */ +#define ADCx_SQRCFR_SQRCH5_Msk (0xf00000UL) /*!< SQRCH5 (Bitfield-Mask: 0x0f) */ +#define ADCx_SQRCFR_SQRCH4_Pos (16UL) /*!< SQRCH4 (Bit 16) */ +#define ADCx_SQRCFR_SQRCH4_Msk (0xf0000UL) /*!< SQRCH4 (Bitfield-Mask: 0x0f) */ +#define ADCx_SQRCFR_SQRCH3_Pos (12UL) /*!< SQRCH3 (Bit 12) */ +#define ADCx_SQRCFR_SQRCH3_Msk (0xf000UL) /*!< SQRCH3 (Bitfield-Mask: 0x0f) */ +#define ADCx_SQRCFR_SQRCH2_Pos (8UL) /*!< SQRCH2 (Bit 8) */ +#define ADCx_SQRCFR_SQRCH2_Msk (0xf00UL) /*!< SQRCH2 (Bitfield-Mask: 0x0f) */ +#define ADCx_SQRCFR_SQRCH1_Pos (4UL) /*!< SQRCH1 (Bit 4) */ +#define ADCx_SQRCFR_SQRCH1_Msk (0xf0UL) /*!< SQRCH1 (Bitfield-Mask: 0x0f) */ +#define ADCx_SQRCFR_SQRCH0_Pos (0UL) /*!< SQRCH0 (Bit 0) */ +#define ADCx_SQRCFR_SQRCH0_Msk (0xfUL) /*!< SQRCH0 (Bitfield-Mask: 0x0f) */ +/* ========================================================== IER ========================================================== */ +#define ADCx_IER_DMAEOS_Pos (6UL) /*!< DMAEOS (Bit 6) */ +#define ADCx_IER_DMAEOS_Msk (0x40UL) /*!< DMAEOS (Bitfield-Mask: 0x01) */ +#define ADCx_IER_DMAEOC_Pos (5UL) /*!< DMAEOC (Bit 5) */ +#define ADCx_IER_DMAEOC_Msk (0x20UL) /*!< DMAEOC (Bitfield-Mask: 0x01) */ +#define ADCx_IER_AWDH_Pos (4UL) /*!< AWDH (Bit 4) */ +#define ADCx_IER_AWDH_Msk (0x10UL) /*!< AWDH (Bitfield-Mask: 0x01) */ +#define ADCx_IER_AWDL_Pos (3UL) /*!< AWDL (Bit 3) */ +#define ADCx_IER_AWDL_Msk (0x8UL) /*!< AWDL (Bitfield-Mask: 0x01) */ +#define ADCx_IER_EOS_Pos (1UL) /*!< EOS (Bit 1) */ +#define ADCx_IER_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */ +#define ADCx_IER_EOC_Pos (0UL) /*!< EOC (Bit 0) */ +#define ADCx_IER_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define ADCx_ISR_AWDH_Pos (4UL) /*!< AWDH (Bit 4) */ +#define ADCx_ISR_AWDH_Msk (0x10UL) /*!< AWDH (Bitfield-Mask: 0x01) */ +#define ADCx_ISR_AWDL_Pos (3UL) /*!< AWDL (Bit 3) */ +#define ADCx_ISR_AWDL_Msk (0x8UL) /*!< AWDL (Bitfield-Mask: 0x01) */ +#define ADCx_ISR_EOS_Pos (1UL) /*!< EOS (Bit 1) */ +#define ADCx_ISR_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */ +#define ADCx_ISR_EOC_Pos (0UL) /*!< EOC (Bit 0) */ +#define ADCx_ISR_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define ADCx_ICR_AWDH_Pos (4UL) /*!< AWDH (Bit 4) */ +#define ADCx_ICR_AWDH_Msk (0x10UL) /*!< AWDH (Bitfield-Mask: 0x01) */ +#define ADCx_ICR_AWDL_Pos (3UL) /*!< AWDL (Bit 3) */ +#define ADCx_ICR_AWDL_Msk (0x8UL) /*!< AWDL (Bitfield-Mask: 0x01) */ +#define ADCx_ICR_EOS_Pos (1UL) /*!< EOS (Bit 1) */ +#define ADCx_ICR_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */ +#define ADCx_ICR_EOC_Pos (0UL) /*!< EOC (Bit 0) */ +#define ADCx_ICR_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */ +/* ======================================================== RESULT0 ======================================================== */ +#define ADCx_RESULT0_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADCx_RESULT0_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT1 ======================================================== */ +#define ADCx_RESULT1_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADCx_RESULT1_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT2 ======================================================== */ +#define ADCx_RESULT2_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADCx_RESULT2_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT3 ======================================================== */ +#define ADCx_RESULT3_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADCx_RESULT3_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT4 ======================================================== */ +#define ADCx_RESULT4_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADCx_RESULT4_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT5 ======================================================== */ +#define ADCx_RESULT5_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADCx_RESULT5_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT6 ======================================================== */ +#define ADCx_RESULT6_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADCx_RESULT6_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT7 ======================================================== */ +#define ADCx_RESULT7_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADCx_RESULT7_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ ATIM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define ATIM_CR1_UIFREMAP_Pos (11UL) /*!< UIFREMAP (Bit 11) */ +#define ATIM_CR1_UIFREMAP_Msk (0x800UL) /*!< UIFREMAP (Bitfield-Mask: 0x01) */ +#define ATIM_CR1_CKD_Pos (8UL) /*!< CKD (Bit 8) */ +#define ATIM_CR1_CKD_Msk (0x300UL) /*!< CKD (Bitfield-Mask: 0x03) */ +#define ATIM_CR1_ARPE_Pos (7UL) /*!< ARPE (Bit 7) */ +#define ATIM_CR1_ARPE_Msk (0x80UL) /*!< ARPE (Bitfield-Mask: 0x01) */ +#define ATIM_CR1_CMS_Pos (5UL) /*!< CMS (Bit 5) */ +#define ATIM_CR1_CMS_Msk (0x60UL) /*!< CMS (Bitfield-Mask: 0x03) */ +#define ATIM_CR1_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define ATIM_CR1_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define ATIM_CR1_OPM_Pos (3UL) /*!< OPM (Bit 3) */ +#define ATIM_CR1_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */ +#define ATIM_CR1_URS_Pos (2UL) /*!< URS (Bit 2) */ +#define ATIM_CR1_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */ +#define ATIM_CR1_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */ +#define ATIM_CR1_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */ +#define ATIM_CR1_CEN_Pos (0UL) /*!< CEN (Bit 0) */ +#define ATIM_CR1_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define ATIM_CR2_MMSH_Pos (25UL) /*!< MMSH (Bit 25) */ +#define ATIM_CR2_MMSH_Msk (0x6000000UL) /*!< MMSH (Bitfield-Mask: 0x03) */ +#define ATIM_CR2_MMS2_Pos (20UL) /*!< MMS2 (Bit 20) */ +#define ATIM_CR2_MMS2_Msk (0x1f00000UL) /*!< MMS2 (Bitfield-Mask: 0x1f) */ +#define ATIM_CR2_OIS6N_Pos (19UL) /*!< OIS6N (Bit 19) */ +#define ATIM_CR2_OIS6N_Msk (0x80000UL) /*!< OIS6N (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS6_Pos (18UL) /*!< OIS6 (Bit 18) */ +#define ATIM_CR2_OIS6_Msk (0x40000UL) /*!< OIS6 (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS5N_Pos (17UL) /*!< OIS5N (Bit 17) */ +#define ATIM_CR2_OIS5N_Msk (0x20000UL) /*!< OIS5N (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS5_Pos (16UL) /*!< OIS5 (Bit 16) */ +#define ATIM_CR2_OIS5_Msk (0x10000UL) /*!< OIS5 (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS4N_Pos (15UL) /*!< OIS4N (Bit 15) */ +#define ATIM_CR2_OIS4N_Msk (0x8000UL) /*!< OIS4N (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS4_Pos (14UL) /*!< OIS4 (Bit 14) */ +#define ATIM_CR2_OIS4_Msk (0x4000UL) /*!< OIS4 (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS3N_Pos (13UL) /*!< OIS3N (Bit 13) */ +#define ATIM_CR2_OIS3N_Msk (0x2000UL) /*!< OIS3N (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS3_Pos (12UL) /*!< OIS3 (Bit 12) */ +#define ATIM_CR2_OIS3_Msk (0x1000UL) /*!< OIS3 (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS2N_Pos (11UL) /*!< OIS2N (Bit 11) */ +#define ATIM_CR2_OIS2N_Msk (0x800UL) /*!< OIS2N (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS2_Pos (10UL) /*!< OIS2 (Bit 10) */ +#define ATIM_CR2_OIS2_Msk (0x400UL) /*!< OIS2 (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS1N_Pos (9UL) /*!< OIS1N (Bit 9) */ +#define ATIM_CR2_OIS1N_Msk (0x200UL) /*!< OIS1N (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS1_Pos (8UL) /*!< OIS1 (Bit 8) */ +#define ATIM_CR2_OIS1_Msk (0x100UL) /*!< OIS1 (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_TI1S_Pos (7UL) /*!< TI1S (Bit 7) */ +#define ATIM_CR2_TI1S_Msk (0x80UL) /*!< TI1S (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_MMS_Pos (4UL) /*!< MMS (Bit 4) */ +#define ATIM_CR2_MMS_Msk (0x70UL) /*!< MMS (Bitfield-Mask: 0x07) */ +#define ATIM_CR2_CCDS_Pos (3UL) /*!< CCDS (Bit 3) */ +#define ATIM_CR2_CCDS_Msk (0x8UL) /*!< CCDS (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_CCUS_Pos (2UL) /*!< CCUS (Bit 2) */ +#define ATIM_CR2_CCUS_Msk (0x4UL) /*!< CCUS (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_CCPC_Pos (0UL) /*!< CCPC (Bit 0) */ +#define ATIM_CR2_CCPC_Msk (0x1UL) /*!< CCPC (Bitfield-Mask: 0x01) */ +/* ========================================================= SMCR ========================================================== */ +#define ATIM_SMCR_SMSPS_Pos (25UL) /*!< SMSPS (Bit 25) */ +#define ATIM_SMCR_SMSPS_Msk (0x2000000UL) /*!< SMSPS (Bitfield-Mask: 0x01) */ +#define ATIM_SMCR_SMSPE_Pos (24UL) /*!< SMSPE (Bit 24) */ +#define ATIM_SMCR_SMSPE_Msk (0x1000000UL) /*!< SMSPE (Bitfield-Mask: 0x01) */ +#define ATIM_SMCR_TSH_Pos (20UL) /*!< TSH (Bit 20) */ +#define ATIM_SMCR_TSH_Msk (0x300000UL) /*!< TSH (Bitfield-Mask: 0x03) */ +#define ATIM_SMCR_SMSH_Pos (16UL) /*!< SMSH (Bit 16) */ +#define ATIM_SMCR_SMSH_Msk (0x10000UL) /*!< SMSH (Bitfield-Mask: 0x01) */ +#define ATIM_SMCR_ETP_Pos (15UL) /*!< ETP (Bit 15) */ +#define ATIM_SMCR_ETP_Msk (0x8000UL) /*!< ETP (Bitfield-Mask: 0x01) */ +#define ATIM_SMCR_ECE_Pos (14UL) /*!< ECE (Bit 14) */ +#define ATIM_SMCR_ECE_Msk (0x4000UL) /*!< ECE (Bitfield-Mask: 0x01) */ +#define ATIM_SMCR_ETPS_Pos (12UL) /*!< ETPS (Bit 12) */ +#define ATIM_SMCR_ETPS_Msk (0x3000UL) /*!< ETPS (Bitfield-Mask: 0x03) */ +#define ATIM_SMCR_ETF_Pos (8UL) /*!< ETF (Bit 8) */ +#define ATIM_SMCR_ETF_Msk (0xf00UL) /*!< ETF (Bitfield-Mask: 0x0f) */ +#define ATIM_SMCR_MSM_Pos (7UL) /*!< MSM (Bit 7) */ +#define ATIM_SMCR_MSM_Msk (0x80UL) /*!< MSM (Bitfield-Mask: 0x01) */ +#define ATIM_SMCR_TS_Pos (4UL) /*!< TS (Bit 4) */ +#define ATIM_SMCR_TS_Msk (0x70UL) /*!< TS (Bitfield-Mask: 0x07) */ +#define ATIM_SMCR_OCCS_Pos (3UL) /*!< OCCS (Bit 3) */ +#define ATIM_SMCR_OCCS_Msk (0x8UL) /*!< OCCS (Bitfield-Mask: 0x01) */ +#define ATIM_SMCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */ +#define ATIM_SMCR_SMS_Msk (0x7UL) /*!< SMS (Bitfield-Mask: 0x07) */ +/* ========================================================== IER ========================================================== */ +#define ATIM_IER_TERRIE_Pos (23UL) /*!< TERRIE (Bit 23) */ +#define ATIM_IER_TERRIE_Msk (0x800000UL) /*!< TERRIE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_IERRIE_Pos (22UL) /*!< IERRIE (Bit 22) */ +#define ATIM_IER_IERRIE_Msk (0x400000UL) /*!< IERRIE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_DIRIE_Pos (21UL) /*!< DIRIE (Bit 21) */ +#define ATIM_IER_DIRIE_Msk (0x200000UL) /*!< DIRIE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_IDXIE_Pos (20UL) /*!< IDXIE (Bit 20) */ +#define ATIM_IER_IDXIE_Msk (0x100000UL) /*!< IDXIE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC6DE_Pos (19UL) /*!< CC6DE (Bit 19) */ +#define ATIM_IER_CC6DE_Msk (0x80000UL) /*!< CC6DE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC5DE_Pos (18UL) /*!< CC5DE (Bit 18) */ +#define ATIM_IER_CC5DE_Msk (0x40000UL) /*!< CC5DE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC6IE_Pos (17UL) /*!< CC6IE (Bit 17) */ +#define ATIM_IER_CC6IE_Msk (0x20000UL) /*!< CC6IE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC5IE_Pos (16UL) /*!< CC5IE (Bit 16) */ +#define ATIM_IER_CC5IE_Msk (0x10000UL) /*!< CC5IE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_TDE_Pos (14UL) /*!< TDE (Bit 14) */ +#define ATIM_IER_TDE_Msk (0x4000UL) /*!< TDE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_COMDE_Pos (13UL) /*!< COMDE (Bit 13) */ +#define ATIM_IER_COMDE_Msk (0x2000UL) /*!< COMDE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC4DE_Pos (12UL) /*!< CC4DE (Bit 12) */ +#define ATIM_IER_CC4DE_Msk (0x1000UL) /*!< CC4DE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC3DE_Pos (11UL) /*!< CC3DE (Bit 11) */ +#define ATIM_IER_CC3DE_Msk (0x800UL) /*!< CC3DE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC2DE_Pos (10UL) /*!< CC2DE (Bit 10) */ +#define ATIM_IER_CC2DE_Msk (0x400UL) /*!< CC2DE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC1DE_Pos (9UL) /*!< CC1DE (Bit 9) */ +#define ATIM_IER_CC1DE_Msk (0x200UL) /*!< CC1DE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_UDE_Pos (8UL) /*!< UDE (Bit 8) */ +#define ATIM_IER_UDE_Msk (0x100UL) /*!< UDE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_BIE_Pos (7UL) /*!< BIE (Bit 7) */ +#define ATIM_IER_BIE_Msk (0x80UL) /*!< BIE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_TIE_Pos (6UL) /*!< TIE (Bit 6) */ +#define ATIM_IER_TIE_Msk (0x40UL) /*!< TIE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_COMIE_Pos (5UL) /*!< COMIE (Bit 5) */ +#define ATIM_IER_COMIE_Msk (0x20UL) /*!< COMIE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC4IE_Pos (4UL) /*!< CC4IE (Bit 4) */ +#define ATIM_IER_CC4IE_Msk (0x10UL) /*!< CC4IE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC3IE_Pos (3UL) /*!< CC3IE (Bit 3) */ +#define ATIM_IER_CC3IE_Msk (0x8UL) /*!< CC3IE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC2IE_Pos (2UL) /*!< CC2IE (Bit 2) */ +#define ATIM_IER_CC2IE_Msk (0x4UL) /*!< CC2IE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC1IE_Pos (1UL) /*!< CC1IE (Bit 1) */ +#define ATIM_IER_CC1IE_Msk (0x2UL) /*!< CC1IE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_UIE_Pos (0UL) /*!< UIE (Bit 0) */ +#define ATIM_IER_UIE_Msk (0x1UL) /*!< UIE (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define ATIM_ISR_TERRF_Pos (23UL) /*!< TERRF (Bit 23) */ +#define ATIM_ISR_TERRF_Msk (0x800000UL) /*!< TERRF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_IERRF_Pos (22UL) /*!< IERRF (Bit 22) */ +#define ATIM_ISR_IERRF_Msk (0x400000UL) /*!< IERRF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_DIRF_Pos (21UL) /*!< DIRF (Bit 21) */ +#define ATIM_ISR_DIRF_Msk (0x200000UL) /*!< DIRF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_IDXF_Pos (20UL) /*!< IDXF (Bit 20) */ +#define ATIM_ISR_IDXF_Msk (0x100000UL) /*!< IDXF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC6OF_Pos (19UL) /*!< CC6OF (Bit 19) */ +#define ATIM_ISR_CC6OF_Msk (0x80000UL) /*!< CC6OF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC5OF_Pos (18UL) /*!< CC5OF (Bit 18) */ +#define ATIM_ISR_CC5OF_Msk (0x40000UL) /*!< CC5OF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC6IF_Pos (17UL) /*!< CC6IF (Bit 17) */ +#define ATIM_ISR_CC6IF_Msk (0x20000UL) /*!< CC6IF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC5IF_Pos (16UL) /*!< CC5IF (Bit 16) */ +#define ATIM_ISR_CC5IF_Msk (0x10000UL) /*!< CC5IF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_SBIF_Pos (13UL) /*!< SBIF (Bit 13) */ +#define ATIM_ISR_SBIF_Msk (0x2000UL) /*!< SBIF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC4OF_Pos (12UL) /*!< CC4OF (Bit 12) */ +#define ATIM_ISR_CC4OF_Msk (0x1000UL) /*!< CC4OF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC3OF_Pos (11UL) /*!< CC3OF (Bit 11) */ +#define ATIM_ISR_CC3OF_Msk (0x800UL) /*!< CC3OF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC2OF_Pos (10UL) /*!< CC2OF (Bit 10) */ +#define ATIM_ISR_CC2OF_Msk (0x400UL) /*!< CC2OF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC1OF_Pos (9UL) /*!< CC1OF (Bit 9) */ +#define ATIM_ISR_CC1OF_Msk (0x200UL) /*!< CC1OF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_B2IF_Pos (8UL) /*!< B2IF (Bit 8) */ +#define ATIM_ISR_B2IF_Msk (0x100UL) /*!< B2IF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_BIF_Pos (7UL) /*!< BIF (Bit 7) */ +#define ATIM_ISR_BIF_Msk (0x80UL) /*!< BIF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_TIF_Pos (6UL) /*!< TIF (Bit 6) */ +#define ATIM_ISR_TIF_Msk (0x40UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_COMIF_Pos (5UL) /*!< COMIF (Bit 5) */ +#define ATIM_ISR_COMIF_Msk (0x20UL) /*!< COMIF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC4IF_Pos (4UL) /*!< CC4IF (Bit 4) */ +#define ATIM_ISR_CC4IF_Msk (0x10UL) /*!< CC4IF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC3IF_Pos (3UL) /*!< CC3IF (Bit 3) */ +#define ATIM_ISR_CC3IF_Msk (0x8UL) /*!< CC3IF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC2IF_Pos (2UL) /*!< CC2IF (Bit 2) */ +#define ATIM_ISR_CC2IF_Msk (0x4UL) /*!< CC2IF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC1IF_Pos (1UL) /*!< CC1IF (Bit 1) */ +#define ATIM_ISR_CC1IF_Msk (0x2UL) /*!< CC1IF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_UIF_Pos (0UL) /*!< UIF (Bit 0) */ +#define ATIM_ISR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */ +/* ========================================================== EGR ========================================================== */ +#define ATIM_EGR_CC6G_Pos (17UL) /*!< CC6G (Bit 17) */ +#define ATIM_EGR_CC6G_Msk (0x20000UL) /*!< CC6G (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_CC5G_Pos (16UL) /*!< CC5G (Bit 16) */ +#define ATIM_EGR_CC5G_Msk (0x10000UL) /*!< CC5G (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_B2G_Pos (8UL) /*!< B2G (Bit 8) */ +#define ATIM_EGR_B2G_Msk (0x100UL) /*!< B2G (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_BG_Pos (7UL) /*!< BG (Bit 7) */ +#define ATIM_EGR_BG_Msk (0x80UL) /*!< BG (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_TG_Pos (6UL) /*!< TG (Bit 6) */ +#define ATIM_EGR_TG_Msk (0x40UL) /*!< TG (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_COMG_Pos (5UL) /*!< COMG (Bit 5) */ +#define ATIM_EGR_COMG_Msk (0x20UL) /*!< COMG (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_CC4G_Pos (4UL) /*!< CC4G (Bit 4) */ +#define ATIM_EGR_CC4G_Msk (0x10UL) /*!< CC4G (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_CC3G_Pos (3UL) /*!< CC3G (Bit 3) */ +#define ATIM_EGR_CC3G_Msk (0x8UL) /*!< CC3G (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_CC2G_Pos (2UL) /*!< CC2G (Bit 2) */ +#define ATIM_EGR_CC2G_Msk (0x4UL) /*!< CC2G (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_CC1G_Pos (1UL) /*!< CC1G (Bit 1) */ +#define ATIM_EGR_CC1G_Msk (0x2UL) /*!< CC1G (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_UG_Pos (0UL) /*!< UG (Bit 0) */ +#define ATIM_EGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */ +/* ======================================================= CCMR1CAP ======================================================== */ +#define ATIM_CCMR1CAP_IC2F_Pos (12UL) /*!< IC2F (Bit 12) */ +#define ATIM_CCMR1CAP_IC2F_Msk (0xf000UL) /*!< IC2F (Bitfield-Mask: 0x0f) */ +#define ATIM_CCMR1CAP_IC2PSC_Pos (10UL) /*!< IC2PSC (Bit 10) */ +#define ATIM_CCMR1CAP_IC2PSC_Msk (0xc00UL) /*!< IC2PSC (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR1CAP_CC2S_Pos (8UL) /*!< CC2S (Bit 8) */ +#define ATIM_CCMR1CAP_CC2S_Msk (0x300UL) /*!< CC2S (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR1CAP_IC1F_Pos (4UL) /*!< IC1F (Bit 4) */ +#define ATIM_CCMR1CAP_IC1F_Msk (0xf0UL) /*!< IC1F (Bitfield-Mask: 0x0f) */ +#define ATIM_CCMR1CAP_IC1PSC_Pos (2UL) /*!< IC1PSC (Bit 2) */ +#define ATIM_CCMR1CAP_IC1PSC_Msk (0xcUL) /*!< IC1PSC (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR1CAP_CC1S_Pos (0UL) /*!< CC1S (Bit 0) */ +#define ATIM_CCMR1CAP_CC1S_Msk (0x3UL) /*!< CC1S (Bitfield-Mask: 0x03) */ +/* ======================================================= CCMR1CMP ======================================================== */ +#define ATIM_CCMR1CMP_OC2MH_Pos (24UL) /*!< OC2MH (Bit 24) */ +#define ATIM_CCMR1CMP_OC2MH_Msk (0x1000000UL) /*!< OC2MH (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR1CMP_OC1MH_Pos (16UL) /*!< OC1MH (Bit 16) */ +#define ATIM_CCMR1CMP_OC1MH_Msk (0x10000UL) /*!< OC1MH (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR1CMP_OC2CE_Pos (15UL) /*!< OC2CE (Bit 15) */ +#define ATIM_CCMR1CMP_OC2CE_Msk (0x8000UL) /*!< OC2CE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR1CMP_OC2M_Pos (12UL) /*!< OC2M (Bit 12) */ +#define ATIM_CCMR1CMP_OC2M_Msk (0x7000UL) /*!< OC2M (Bitfield-Mask: 0x07) */ +#define ATIM_CCMR1CMP_OC2PE_Pos (11UL) /*!< OC2PE (Bit 11) */ +#define ATIM_CCMR1CMP_OC2PE_Msk (0x800UL) /*!< OC2PE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR1CMP_OC2FE_Pos (10UL) /*!< OC2FE (Bit 10) */ +#define ATIM_CCMR1CMP_OC2FE_Msk (0x400UL) /*!< OC2FE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR1CMP_CC2S_Pos (8UL) /*!< CC2S (Bit 8) */ +#define ATIM_CCMR1CMP_CC2S_Msk (0x300UL) /*!< CC2S (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR1CMP_OC1CE_Pos (7UL) /*!< OC1CE (Bit 7) */ +#define ATIM_CCMR1CMP_OC1CE_Msk (0x80UL) /*!< OC1CE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR1CMP_OC1M_Pos (4UL) /*!< OC1M (Bit 4) */ +#define ATIM_CCMR1CMP_OC1M_Msk (0x70UL) /*!< OC1M (Bitfield-Mask: 0x07) */ +#define ATIM_CCMR1CMP_OC1PE_Pos (3UL) /*!< OC1PE (Bit 3) */ +#define ATIM_CCMR1CMP_OC1PE_Msk (0x8UL) /*!< OC1PE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR1CMP_OC1FE_Pos (2UL) /*!< OC1FE (Bit 2) */ +#define ATIM_CCMR1CMP_OC1FE_Msk (0x4UL) /*!< OC1FE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR1CMP_CC1S_Pos (0UL) /*!< CC1S (Bit 0) */ +#define ATIM_CCMR1CMP_CC1S_Msk (0x3UL) /*!< CC1S (Bitfield-Mask: 0x03) */ +/* ======================================================= CCMR2CAP ======================================================== */ +#define ATIM_CCMR2CAP_IC4F_Pos (12UL) /*!< IC4F (Bit 12) */ +#define ATIM_CCMR2CAP_IC4F_Msk (0xf000UL) /*!< IC4F (Bitfield-Mask: 0x0f) */ +#define ATIM_CCMR2CAP_IC4PSC_Pos (10UL) /*!< IC4PSC (Bit 10) */ +#define ATIM_CCMR2CAP_IC4PSC_Msk (0xc00UL) /*!< IC4PSC (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR2CAP_CC4S_Pos (8UL) /*!< CC4S (Bit 8) */ +#define ATIM_CCMR2CAP_CC4S_Msk (0x300UL) /*!< CC4S (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR2CAP_IC3F_Pos (4UL) /*!< IC3F (Bit 4) */ +#define ATIM_CCMR2CAP_IC3F_Msk (0xf0UL) /*!< IC3F (Bitfield-Mask: 0x0f) */ +#define ATIM_CCMR2CAP_IC3PSC_Pos (2UL) /*!< IC3PSC (Bit 2) */ +#define ATIM_CCMR2CAP_IC3PSC_Msk (0xcUL) /*!< IC3PSC (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR2CAP_CC3S_Pos (0UL) /*!< CC3S (Bit 0) */ +#define ATIM_CCMR2CAP_CC3S_Msk (0x3UL) /*!< CC3S (Bitfield-Mask: 0x03) */ +/* ======================================================= CCMR2CMP ======================================================== */ +#define ATIM_CCMR2CMP_OC4MH_Pos (24UL) /*!< OC4MH (Bit 24) */ +#define ATIM_CCMR2CMP_OC4MH_Msk (0x1000000UL) /*!< OC4MH (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR2CMP_OC3MH_Pos (16UL) /*!< OC3MH (Bit 16) */ +#define ATIM_CCMR2CMP_OC3MH_Msk (0x10000UL) /*!< OC3MH (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR2CMP_OC4CE_Pos (15UL) /*!< OC4CE (Bit 15) */ +#define ATIM_CCMR2CMP_OC4CE_Msk (0x8000UL) /*!< OC4CE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR2CMP_OC4M_Pos (12UL) /*!< OC4M (Bit 12) */ +#define ATIM_CCMR2CMP_OC4M_Msk (0x7000UL) /*!< OC4M (Bitfield-Mask: 0x07) */ +#define ATIM_CCMR2CMP_OC4PE_Pos (11UL) /*!< OC4PE (Bit 11) */ +#define ATIM_CCMR2CMP_OC4PE_Msk (0x800UL) /*!< OC4PE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR2CMP_OC4FE_Pos (10UL) /*!< OC4FE (Bit 10) */ +#define ATIM_CCMR2CMP_OC4FE_Msk (0x400UL) /*!< OC4FE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR2CMP_CC4S_Pos (8UL) /*!< CC4S (Bit 8) */ +#define ATIM_CCMR2CMP_CC4S_Msk (0x300UL) /*!< CC4S (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR2CMP_OC3CE_Pos (7UL) /*!< OC3CE (Bit 7) */ +#define ATIM_CCMR2CMP_OC3CE_Msk (0x80UL) /*!< OC3CE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR2CMP_OC3M_Pos (4UL) /*!< OC3M (Bit 4) */ +#define ATIM_CCMR2CMP_OC3M_Msk (0x70UL) /*!< OC3M (Bitfield-Mask: 0x07) */ +#define ATIM_CCMR2CMP_OC3PE_Pos (3UL) /*!< OC3PE (Bit 3) */ +#define ATIM_CCMR2CMP_OC3PE_Msk (0x8UL) /*!< OC3PE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR2CMP_OC3FE_Pos (2UL) /*!< OC3FE (Bit 2) */ +#define ATIM_CCMR2CMP_OC3FE_Msk (0x4UL) /*!< OC3FE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR2CMP_CC3S_Pos (0UL) /*!< CC3S (Bit 0) */ +#define ATIM_CCMR2CMP_CC3S_Msk (0x3UL) /*!< CC3S (Bitfield-Mask: 0x03) */ +/* ======================================================= CCMR3CAP ======================================================== */ +#define ATIM_CCMR3CAP_IC6F_Pos (12UL) /*!< IC6F (Bit 12) */ +#define ATIM_CCMR3CAP_IC6F_Msk (0xf000UL) /*!< IC6F (Bitfield-Mask: 0x0f) */ +#define ATIM_CCMR3CAP_IC6PSC_Pos (10UL) /*!< IC6PSC (Bit 10) */ +#define ATIM_CCMR3CAP_IC6PSC_Msk (0xc00UL) /*!< IC6PSC (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR3CAP_CC6S_Pos (8UL) /*!< CC6S (Bit 8) */ +#define ATIM_CCMR3CAP_CC6S_Msk (0x300UL) /*!< CC6S (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR3CAP_IC5F_Pos (4UL) /*!< IC5F (Bit 4) */ +#define ATIM_CCMR3CAP_IC5F_Msk (0xf0UL) /*!< IC5F (Bitfield-Mask: 0x0f) */ +#define ATIM_CCMR3CAP_IC5PSC_Pos (2UL) /*!< IC5PSC (Bit 2) */ +#define ATIM_CCMR3CAP_IC5PSC_Msk (0xcUL) /*!< IC5PSC (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR3CAP_CC5S_Pos (0UL) /*!< CC5S (Bit 0) */ +#define ATIM_CCMR3CAP_CC5S_Msk (0x3UL) /*!< CC5S (Bitfield-Mask: 0x03) */ +/* ======================================================= CCMR3CMP ======================================================== */ +#define ATIM_CCMR3CMP_OC6MH_Pos (24UL) /*!< OC6MH (Bit 24) */ +#define ATIM_CCMR3CMP_OC6MH_Msk (0x1000000UL) /*!< OC6MH (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR3CMP_OC5MH_Pos (16UL) /*!< OC5MH (Bit 16) */ +#define ATIM_CCMR3CMP_OC5MH_Msk (0x10000UL) /*!< OC5MH (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR3CMP_OC6CE_Pos (15UL) /*!< OC6CE (Bit 15) */ +#define ATIM_CCMR3CMP_OC6CE_Msk (0x8000UL) /*!< OC6CE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR3CMP_OC6M_Pos (12UL) /*!< OC6M (Bit 12) */ +#define ATIM_CCMR3CMP_OC6M_Msk (0x7000UL) /*!< OC6M (Bitfield-Mask: 0x07) */ +#define ATIM_CCMR3CMP_OC6PE_Pos (11UL) /*!< OC6PE (Bit 11) */ +#define ATIM_CCMR3CMP_OC6PE_Msk (0x800UL) /*!< OC6PE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR3CMP_OC6FE_Pos (10UL) /*!< OC6FE (Bit 10) */ +#define ATIM_CCMR3CMP_OC6FE_Msk (0x400UL) /*!< OC6FE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR3CMP_CC6S_Pos (8UL) /*!< CC6S (Bit 8) */ +#define ATIM_CCMR3CMP_CC6S_Msk (0x300UL) /*!< CC6S (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR3CMP_OC5CE_Pos (7UL) /*!< OC5CE (Bit 7) */ +#define ATIM_CCMR3CMP_OC5CE_Msk (0x80UL) /*!< OC5CE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR3CMP_OC5M_Pos (4UL) /*!< OC5M (Bit 4) */ +#define ATIM_CCMR3CMP_OC5M_Msk (0x70UL) /*!< OC5M (Bitfield-Mask: 0x07) */ +#define ATIM_CCMR3CMP_OC5PE_Pos (3UL) /*!< OC5PE (Bit 3) */ +#define ATIM_CCMR3CMP_OC5PE_Msk (0x8UL) /*!< OC5PE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR3CMP_OC5FE_Pos (2UL) /*!< OC5FE (Bit 2) */ +#define ATIM_CCMR3CMP_OC5FE_Msk (0x4UL) /*!< OC5FE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR3CMP_CC5S_Pos (0UL) /*!< CC5S (Bit 0) */ +#define ATIM_CCMR3CMP_CC5S_Msk (0x3UL) /*!< CC5S (Bitfield-Mask: 0x03) */ +/* ========================================================= CCER ========================================================== */ +#define ATIM_CCER_CC6NP_Pos (23UL) /*!< CC6NP (Bit 23) */ +#define ATIM_CCER_CC6NP_Msk (0x800000UL) /*!< CC6NP (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC6NE_Pos (22UL) /*!< CC6NE (Bit 22) */ +#define ATIM_CCER_CC6NE_Msk (0x400000UL) /*!< CC6NE (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC6P_Pos (21UL) /*!< CC6P (Bit 21) */ +#define ATIM_CCER_CC6P_Msk (0x200000UL) /*!< CC6P (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC6E_Pos (20UL) /*!< CC6E (Bit 20) */ +#define ATIM_CCER_CC6E_Msk (0x100000UL) /*!< CC6E (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC5NP_Pos (19UL) /*!< CC5NP (Bit 19) */ +#define ATIM_CCER_CC5NP_Msk (0x80000UL) /*!< CC5NP (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC5NE_Pos (18UL) /*!< CC5NE (Bit 18) */ +#define ATIM_CCER_CC5NE_Msk (0x40000UL) /*!< CC5NE (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC5P_Pos (17UL) /*!< CC5P (Bit 17) */ +#define ATIM_CCER_CC5P_Msk (0x20000UL) /*!< CC5P (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC5E_Pos (16UL) /*!< CC5E (Bit 16) */ +#define ATIM_CCER_CC5E_Msk (0x10000UL) /*!< CC5E (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC4NP_Pos (15UL) /*!< CC4NP (Bit 15) */ +#define ATIM_CCER_CC4NP_Msk (0x8000UL) /*!< CC4NP (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC4NE_Pos (14UL) /*!< CC4NE (Bit 14) */ +#define ATIM_CCER_CC4NE_Msk (0x4000UL) /*!< CC4NE (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC4P_Pos (13UL) /*!< CC4P (Bit 13) */ +#define ATIM_CCER_CC4P_Msk (0x2000UL) /*!< CC4P (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC4E_Pos (12UL) /*!< CC4E (Bit 12) */ +#define ATIM_CCER_CC4E_Msk (0x1000UL) /*!< CC4E (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC3NP_Pos (11UL) /*!< CC3NP (Bit 11) */ +#define ATIM_CCER_CC3NP_Msk (0x800UL) /*!< CC3NP (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC3NE_Pos (10UL) /*!< CC3NE (Bit 10) */ +#define ATIM_CCER_CC3NE_Msk (0x400UL) /*!< CC3NE (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC3P_Pos (9UL) /*!< CC3P (Bit 9) */ +#define ATIM_CCER_CC3P_Msk (0x200UL) /*!< CC3P (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC3E_Pos (8UL) /*!< CC3E (Bit 8) */ +#define ATIM_CCER_CC3E_Msk (0x100UL) /*!< CC3E (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC2NP_Pos (7UL) /*!< CC2NP (Bit 7) */ +#define ATIM_CCER_CC2NP_Msk (0x80UL) /*!< CC2NP (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC2NE_Pos (6UL) /*!< CC2NE (Bit 6) */ +#define ATIM_CCER_CC2NE_Msk (0x40UL) /*!< CC2NE (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC2P_Pos (5UL) /*!< CC2P (Bit 5) */ +#define ATIM_CCER_CC2P_Msk (0x20UL) /*!< CC2P (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC2E_Pos (4UL) /*!< CC2E (Bit 4) */ +#define ATIM_CCER_CC2E_Msk (0x10UL) /*!< CC2E (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC1NP_Pos (3UL) /*!< CC1NP (Bit 3) */ +#define ATIM_CCER_CC1NP_Msk (0x8UL) /*!< CC1NP (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC1NE_Pos (2UL) /*!< CC1NE (Bit 2) */ +#define ATIM_CCER_CC1NE_Msk (0x4UL) /*!< CC1NE (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC1P_Pos (1UL) /*!< CC1P (Bit 1) */ +#define ATIM_CCER_CC1P_Msk (0x2UL) /*!< CC1P (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC1E_Pos (0UL) /*!< CC1E (Bit 0) */ +#define ATIM_CCER_CC1E_Msk (0x1UL) /*!< CC1E (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +#define ATIM_CNT_UIFCPY_Pos (31UL) /*!< UIFCPY (Bit 31) */ +#define ATIM_CNT_UIFCPY_Msk (0x80000000UL) /*!< UIFCPY (Bitfield-Mask: 0x01) */ +#define ATIM_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define ATIM_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== PSC ========================================================== */ +#define ATIM_PSC_PSC_Pos (0UL) /*!< PSC (Bit 0) */ +#define ATIM_PSC_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */ +/* ========================================================== ARR ========================================================== */ +#define ATIM_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define ATIM_ARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ========================================================== RCR ========================================================== */ +#define ATIM_RCR_REP_Pos (0UL) /*!< REP (Bit 0) */ +#define ATIM_RCR_REP_Msk (0xffffUL) /*!< REP (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR1 ========================================================== */ +#define ATIM_CCR1_CCR1_Pos (0UL) /*!< CCR1 (Bit 0) */ +#define ATIM_CCR1_CCR1_Msk (0xffffUL) /*!< CCR1 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR2 ========================================================== */ +#define ATIM_CCR2_CCR2_Pos (0UL) /*!< CCR2 (Bit 0) */ +#define ATIM_CCR2_CCR2_Msk (0xffffUL) /*!< CCR2 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR3 ========================================================== */ +#define ATIM_CCR3_CCR3_Pos (0UL) /*!< CCR3 (Bit 0) */ +#define ATIM_CCR3_CCR3_Msk (0xffffUL) /*!< CCR3 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR4 ========================================================== */ +#define ATIM_CCR4_CCR4_Pos (0UL) /*!< CCR4 (Bit 0) */ +#define ATIM_CCR4_CCR4_Msk (0xffffUL) /*!< CCR4 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR5 ========================================================== */ +#define ATIM_CCR5_GC5C6_Pos (31UL) /*!< GC5C6 (Bit 31) */ +#define ATIM_CCR5_GC5C6_Msk (0x80000000UL) /*!< GC5C6 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR5_GC5C5_Pos (30UL) /*!< GC5C5 (Bit 30) */ +#define ATIM_CCR5_GC5C5_Msk (0x40000000UL) /*!< GC5C5 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR5_GC5C4_Pos (29UL) /*!< GC5C4 (Bit 29) */ +#define ATIM_CCR5_GC5C4_Msk (0x20000000UL) /*!< GC5C4 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR5_GC5C3_Pos (28UL) /*!< GC5C3 (Bit 28) */ +#define ATIM_CCR5_GC5C3_Msk (0x10000000UL) /*!< GC5C3 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR5_GC5C2_Pos (27UL) /*!< GC5C2 (Bit 27) */ +#define ATIM_CCR5_GC5C2_Msk (0x8000000UL) /*!< GC5C2 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR5_GC5C1_Pos (26UL) /*!< GC5C1 (Bit 26) */ +#define ATIM_CCR5_GC5C1_Msk (0x4000000UL) /*!< GC5C1 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR5_CCR5_Pos (0UL) /*!< CCR5 (Bit 0) */ +#define ATIM_CCR5_CCR5_Msk (0xffffUL) /*!< CCR5 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR6 ========================================================== */ +#define ATIM_CCR6_GC6C6_Pos (31UL) /*!< GC6C6 (Bit 31) */ +#define ATIM_CCR6_GC6C6_Msk (0x80000000UL) /*!< GC6C6 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR6_GC6C5_Pos (30UL) /*!< GC6C5 (Bit 30) */ +#define ATIM_CCR6_GC6C5_Msk (0x40000000UL) /*!< GC6C5 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR6_GC6C4_Pos (29UL) /*!< GC6C4 (Bit 29) */ +#define ATIM_CCR6_GC6C4_Msk (0x20000000UL) /*!< GC6C4 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR6_GC6C3_Pos (28UL) /*!< GC6C3 (Bit 28) */ +#define ATIM_CCR6_GC6C3_Msk (0x10000000UL) /*!< GC6C3 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR6_GC6C2_Pos (27UL) /*!< GC6C2 (Bit 27) */ +#define ATIM_CCR6_GC6C2_Msk (0x8000000UL) /*!< GC6C2 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR6_GC6C1_Pos (26UL) /*!< GC6C1 (Bit 26) */ +#define ATIM_CCR6_GC6C1_Msk (0x4000000UL) /*!< GC6C1 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR6_CCR6_Pos (0UL) /*!< CCR6 (Bit 0) */ +#define ATIM_CCR6_CCR6_Msk (0xffffUL) /*!< CCR6 (Bitfield-Mask: 0xffff) */ +/* ========================================================= BDTR ========================================================== */ +#define ATIM_BDTR_BK2P_Pos (25UL) /*!< BK2P (Bit 25) */ +#define ATIM_BDTR_BK2P_Msk (0x2000000UL) /*!< BK2P (Bitfield-Mask: 0x01) */ +#define ATIM_BDTR_BK2E_Pos (24UL) /*!< BK2E (Bit 24) */ +#define ATIM_BDTR_BK2E_Msk (0x1000000UL) /*!< BK2E (Bitfield-Mask: 0x01) */ +#define ATIM_BDTR_BK2F_Pos (20UL) /*!< BK2F (Bit 20) */ +#define ATIM_BDTR_BK2F_Msk (0xf00000UL) /*!< BK2F (Bitfield-Mask: 0x0f) */ +#define ATIM_BDTR_BKF_Pos (16UL) /*!< BKF (Bit 16) */ +#define ATIM_BDTR_BKF_Msk (0xf0000UL) /*!< BKF (Bitfield-Mask: 0x0f) */ +#define ATIM_BDTR_MOE_Pos (15UL) /*!< MOE (Bit 15) */ +#define ATIM_BDTR_MOE_Msk (0x8000UL) /*!< MOE (Bitfield-Mask: 0x01) */ +#define ATIM_BDTR_AOE_Pos (14UL) /*!< AOE (Bit 14) */ +#define ATIM_BDTR_AOE_Msk (0x4000UL) /*!< AOE (Bitfield-Mask: 0x01) */ +#define ATIM_BDTR_BKP_Pos (13UL) /*!< BKP (Bit 13) */ +#define ATIM_BDTR_BKP_Msk (0x2000UL) /*!< BKP (Bitfield-Mask: 0x01) */ +#define ATIM_BDTR_BKE_Pos (12UL) /*!< BKE (Bit 12) */ +#define ATIM_BDTR_BKE_Msk (0x1000UL) /*!< BKE (Bitfield-Mask: 0x01) */ +#define ATIM_BDTR_OSSR_Pos (11UL) /*!< OSSR (Bit 11) */ +#define ATIM_BDTR_OSSR_Msk (0x800UL) /*!< OSSR (Bitfield-Mask: 0x01) */ +#define ATIM_BDTR_OSSI_Pos (10UL) /*!< OSSI (Bit 10) */ +#define ATIM_BDTR_OSSI_Msk (0x400UL) /*!< OSSI (Bitfield-Mask: 0x01) */ +#define ATIM_BDTR_LOCK_Pos (8UL) /*!< LOCK (Bit 8) */ +#define ATIM_BDTR_LOCK_Msk (0x300UL) /*!< LOCK (Bitfield-Mask: 0x03) */ +#define ATIM_BDTR_DTG_Pos (0UL) /*!< DTG (Bit 0) */ +#define ATIM_BDTR_DTG_Msk (0xffUL) /*!< DTG (Bitfield-Mask: 0xff) */ +/* ========================================================= DTR2 ========================================================== */ +#define ATIM_DTR2_DTPE_Pos (17UL) /*!< DTPE (Bit 17) */ +#define ATIM_DTR2_DTPE_Msk (0x20000UL) /*!< DTPE (Bitfield-Mask: 0x01) */ +#define ATIM_DTR2_DTAE_Pos (16UL) /*!< DTAE (Bit 16) */ +#define ATIM_DTR2_DTAE_Msk (0x10000UL) /*!< DTAE (Bitfield-Mask: 0x01) */ +#define ATIM_DTR2_DTGF_Pos (0UL) /*!< DTGF (Bit 0) */ +#define ATIM_DTR2_DTGF_Msk (0xffUL) /*!< DTGF (Bitfield-Mask: 0xff) */ +/* ========================================================== ECR ========================================================== */ +#define ATIM_ECR_IPOS_Pos (6UL) /*!< IPOS (Bit 6) */ +#define ATIM_ECR_IPOS_Msk (0xc0UL) /*!< IPOS (Bitfield-Mask: 0x03) */ +#define ATIM_ECR_FIDX_Pos (5UL) /*!< FIDX (Bit 5) */ +#define ATIM_ECR_FIDX_Msk (0x20UL) /*!< FIDX (Bitfield-Mask: 0x01) */ +#define ATIM_ECR_IDIR_Pos (1UL) /*!< IDIR (Bit 1) */ +#define ATIM_ECR_IDIR_Msk (0x6UL) /*!< IDIR (Bitfield-Mask: 0x03) */ +#define ATIM_ECR_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ATIM_ECR_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ======================================================== TISEL1 ========================================================= */ +#define ATIM_TISEL1_TI4SEL_Pos (24UL) /*!< TI4SEL (Bit 24) */ +#define ATIM_TISEL1_TI4SEL_Msk (0xf000000UL) /*!< TI4SEL (Bitfield-Mask: 0x0f) */ +#define ATIM_TISEL1_TI3SEL_Pos (16UL) /*!< TI3SEL (Bit 16) */ +#define ATIM_TISEL1_TI3SEL_Msk (0xf0000UL) /*!< TI3SEL (Bitfield-Mask: 0x0f) */ +#define ATIM_TISEL1_TI2SEL_Pos (8UL) /*!< TI2SEL (Bit 8) */ +#define ATIM_TISEL1_TI2SEL_Msk (0xf00UL) /*!< TI2SEL (Bitfield-Mask: 0x0f) */ +#define ATIM_TISEL1_TI1SEL_Pos (0UL) /*!< TI1SEL (Bit 0) */ +#define ATIM_TISEL1_TI1SEL_Msk (0xfUL) /*!< TI1SEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== TISEL2 ========================================================= */ +#define ATIM_TISEL2_TI6SEL_Pos (8UL) /*!< TI6SEL (Bit 8) */ +#define ATIM_TISEL2_TI6SEL_Msk (0xf00UL) /*!< TI6SEL (Bitfield-Mask: 0x0f) */ +#define ATIM_TISEL2_TI5SEL_Pos (0UL) /*!< TI5SEL (Bit 0) */ +#define ATIM_TISEL2_TI5SEL_Msk (0xfUL) /*!< TI5SEL (Bitfield-Mask: 0x0f) */ +/* ========================================================== AF1 ========================================================== */ +#define ATIM_AF1_ETRSEL_Pos (16UL) /*!< ETRSEL (Bit 16) */ +#define ATIM_AF1_ETRSEL_Msk (0xf0000UL) /*!< ETRSEL (Bitfield-Mask: 0x0f) */ +#define ATIM_AF1_BKVC4P_Pos (13UL) /*!< BKVC4P (Bit 13) */ +#define ATIM_AF1_BKVC4P_Msk (0x2000UL) /*!< BKVC4P (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKVC3P_Pos (12UL) /*!< BKVC3P (Bit 12) */ +#define ATIM_AF1_BKVC3P_Msk (0x1000UL) /*!< BKVC3P (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKVC2P_Pos (11UL) /*!< BKVC2P (Bit 11) */ +#define ATIM_AF1_BKVC2P_Msk (0x800UL) /*!< BKVC2P (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKVC1P_Pos (10UL) /*!< BKVC1P (Bit 10) */ +#define ATIM_AF1_BKVC1P_Msk (0x400UL) /*!< BKVC1P (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKINP_Pos (9UL) /*!< BKINP (Bit 9) */ +#define ATIM_AF1_BKINP_Msk (0x200UL) /*!< BKINP (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKVC4E_Pos (4UL) /*!< BKVC4E (Bit 4) */ +#define ATIM_AF1_BKVC4E_Msk (0x10UL) /*!< BKVC4E (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKVC3E_Pos (3UL) /*!< BKVC3E (Bit 3) */ +#define ATIM_AF1_BKVC3E_Msk (0x8UL) /*!< BKVC3E (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKVC2E_Pos (2UL) /*!< BKVC2E (Bit 2) */ +#define ATIM_AF1_BKVC2E_Msk (0x4UL) /*!< BKVC2E (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKVC1E_Pos (1UL) /*!< BKVC1E (Bit 1) */ +#define ATIM_AF1_BKVC1E_Msk (0x2UL) /*!< BKVC1E (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKINE_Pos (0UL) /*!< BKINE (Bit 0) */ +#define ATIM_AF1_BKINE_Msk (0x1UL) /*!< BKINE (Bitfield-Mask: 0x01) */ +/* ========================================================== AF2 ========================================================== */ +#define ATIM_AF2_OCRSEL_Pos (16UL) /*!< OCRSEL (Bit 16) */ +#define ATIM_AF2_OCRSEL_Msk (0xf0000UL) /*!< OCRSEL (Bitfield-Mask: 0x0f) */ +#define ATIM_AF2_BK2VC4P_Pos (13UL) /*!< BK2VC4P (Bit 13) */ +#define ATIM_AF2_BK2VC4P_Msk (0x2000UL) /*!< BK2VC4P (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2VC3P_Pos (12UL) /*!< BK2VC3P (Bit 12) */ +#define ATIM_AF2_BK2VC3P_Msk (0x1000UL) /*!< BK2VC3P (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2VC2P_Pos (11UL) /*!< BK2VC2P (Bit 11) */ +#define ATIM_AF2_BK2VC2P_Msk (0x800UL) /*!< BK2VC2P (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2VC1P_Pos (10UL) /*!< BK2VC1P (Bit 10) */ +#define ATIM_AF2_BK2VC1P_Msk (0x400UL) /*!< BK2VC1P (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2INP_Pos (9UL) /*!< BK2INP (Bit 9) */ +#define ATIM_AF2_BK2INP_Msk (0x200UL) /*!< BK2INP (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2VC4E_Pos (4UL) /*!< BK2VC4E (Bit 4) */ +#define ATIM_AF2_BK2VC4E_Msk (0x10UL) /*!< BK2VC4E (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2VC3E_Pos (3UL) /*!< BK2VC3E (Bit 3) */ +#define ATIM_AF2_BK2VC3E_Msk (0x8UL) /*!< BK2VC3E (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2VC2E_Pos (2UL) /*!< BK2VC2E (Bit 2) */ +#define ATIM_AF2_BK2VC2E_Msk (0x4UL) /*!< BK2VC2E (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2VC1E_Pos (1UL) /*!< BK2VC1E (Bit 1) */ +#define ATIM_AF2_BK2VC1E_Msk (0x2UL) /*!< BK2VC1E (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2INE_Pos (0UL) /*!< BK2INE (Bit 0) */ +#define ATIM_AF2_BK2INE_Msk (0x1UL) /*!< BK2INE (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define ATIM_ICR_TERRF_Pos (23UL) /*!< TERRF (Bit 23) */ +#define ATIM_ICR_TERRF_Msk (0x800000UL) /*!< TERRF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_IERRF_Pos (22UL) /*!< IERRF (Bit 22) */ +#define ATIM_ICR_IERRF_Msk (0x400000UL) /*!< IERRF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_DIRF_Pos (21UL) /*!< DIRF (Bit 21) */ +#define ATIM_ICR_DIRF_Msk (0x200000UL) /*!< DIRF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_IDXF_Pos (20UL) /*!< IDXF (Bit 20) */ +#define ATIM_ICR_IDXF_Msk (0x100000UL) /*!< IDXF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC6OF_Pos (19UL) /*!< CC6OF (Bit 19) */ +#define ATIM_ICR_CC6OF_Msk (0x80000UL) /*!< CC6OF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC5OF_Pos (18UL) /*!< CC5OF (Bit 18) */ +#define ATIM_ICR_CC5OF_Msk (0x40000UL) /*!< CC5OF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC6IF_Pos (17UL) /*!< CC6IF (Bit 17) */ +#define ATIM_ICR_CC6IF_Msk (0x20000UL) /*!< CC6IF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC5IF_Pos (16UL) /*!< CC5IF (Bit 16) */ +#define ATIM_ICR_CC5IF_Msk (0x10000UL) /*!< CC5IF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_SBIF_Pos (13UL) /*!< SBIF (Bit 13) */ +#define ATIM_ICR_SBIF_Msk (0x2000UL) /*!< SBIF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC4OF_Pos (12UL) /*!< CC4OF (Bit 12) */ +#define ATIM_ICR_CC4OF_Msk (0x1000UL) /*!< CC4OF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC3OF_Pos (11UL) /*!< CC3OF (Bit 11) */ +#define ATIM_ICR_CC3OF_Msk (0x800UL) /*!< CC3OF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC2OF_Pos (10UL) /*!< CC2OF (Bit 10) */ +#define ATIM_ICR_CC2OF_Msk (0x400UL) /*!< CC2OF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC1OF_Pos (9UL) /*!< CC1OF (Bit 9) */ +#define ATIM_ICR_CC1OF_Msk (0x200UL) /*!< CC1OF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_B2IF_Pos (8UL) /*!< B2IF (Bit 8) */ +#define ATIM_ICR_B2IF_Msk (0x100UL) /*!< B2IF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_BIF_Pos (7UL) /*!< BIF (Bit 7) */ +#define ATIM_ICR_BIF_Msk (0x80UL) /*!< BIF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_TIF_Pos (6UL) /*!< TIF (Bit 6) */ +#define ATIM_ICR_TIF_Msk (0x40UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_COMIF_Pos (5UL) /*!< COMIF (Bit 5) */ +#define ATIM_ICR_COMIF_Msk (0x20UL) /*!< COMIF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC4IF_Pos (4UL) /*!< CC4IF (Bit 4) */ +#define ATIM_ICR_CC4IF_Msk (0x10UL) /*!< CC4IF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC3IF_Pos (3UL) /*!< CC3IF (Bit 3) */ +#define ATIM_ICR_CC3IF_Msk (0x8UL) /*!< CC3IF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC2IF_Pos (2UL) /*!< CC2IF (Bit 2) */ +#define ATIM_ICR_CC2IF_Msk (0x4UL) /*!< CC2IF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC1IF_Pos (1UL) /*!< CC1IF (Bit 1) */ +#define ATIM_ICR_CC1IF_Msk (0x2UL) /*!< CC1IF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_UIF_Pos (0UL) /*!< UIF (Bit 0) */ +#define ATIM_ICR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ BGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define BGR_CR_TSEN_Pos (1UL) /*!< TSEN (Bit 1) */ +#define BGR_CR_TSEN_Msk (0x2UL) /*!< TSEN (Bitfield-Mask: 0x01) */ +#define BGR_CR_BGREN_Pos (0UL) /*!< BGREN (Bit 0) */ +#define BGR_CR_BGREN_Msk (0x1UL) /*!< BGREN (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ BTIM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define BTIMx_CR1_TOGEN_Pos (15UL) /*!< TOGEN (Bit 15) */ +#define BTIMx_CR1_TOGEN_Msk (0x8000UL) /*!< TOGEN (Bitfield-Mask: 0x01) */ +#define BTIMx_CR1_UIFREMAP_Pos (11UL) /*!< UIFREMAP (Bit 11) */ +#define BTIMx_CR1_UIFREMAP_Msk (0x800UL) /*!< UIFREMAP (Bitfield-Mask: 0x01) */ +#define BTIMx_CR1_ONESHOT_Pos (3UL) /*!< ONESHOT (Bit 3) */ +#define BTIMx_CR1_ONESHOT_Msk (0x8UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ +#define BTIMx_CR1_URS_Pos (2UL) /*!< URS (Bit 2) */ +#define BTIMx_CR1_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */ +#define BTIMx_CR1_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */ +#define BTIMx_CR1_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */ +#define BTIMx_CR1_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define BTIMx_CR1_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define BTIMx_CR2_MMS_Pos (4UL) /*!< MMS (Bit 4) */ +#define BTIMx_CR2_MMS_Msk (0x70UL) /*!< MMS (Bitfield-Mask: 0x07) */ +/* ========================================================= SMCR ========================================================== */ +#define BTIMx_SMCR_TRGIPOL_Pos (17UL) /*!< TRGIPOL (Bit 17) */ +#define BTIMx_SMCR_TRGIPOL_Msk (0x20000UL) /*!< TRGIPOL (Bitfield-Mask: 0x01) */ +#define BTIMx_SMCR_RSTIPOL_Pos (16UL) /*!< RSTIPOL (Bit 16) */ +#define BTIMx_SMCR_RSTIPOL_Msk (0x10000UL) /*!< RSTIPOL (Bitfield-Mask: 0x01) */ +#define BTIMx_SMCR_TRGIFLT_Pos (12UL) /*!< TRGIFLT (Bit 12) */ +#define BTIMx_SMCR_TRGIFLT_Msk (0x7000UL) /*!< TRGIFLT (Bitfield-Mask: 0x07) */ +#define BTIMx_SMCR_MSM_Pos (11UL) /*!< MSM (Bit 11) */ +#define BTIMx_SMCR_MSM_Msk (0x800UL) /*!< MSM (Bitfield-Mask: 0x01) */ +#define BTIMx_SMCR_TRGISRC_Pos (7UL) /*!< TRGISRC (Bit 7) */ +#define BTIMx_SMCR_TRGISRC_Msk (0x780UL) /*!< TRGISRC (Bitfield-Mask: 0x0f) */ +#define BTIMx_SMCR_RSTISRC_Pos (3UL) /*!< RSTISRC (Bit 3) */ +#define BTIMx_SMCR_RSTISRC_Msk (0x78UL) /*!< RSTISRC (Bitfield-Mask: 0x0f) */ +#define BTIMx_SMCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */ +#define BTIMx_SMCR_SMS_Msk (0x7UL) /*!< SMS (Bitfield-Mask: 0x07) */ +/* ========================================================= DIER ========================================================== */ +#define BTIMx_DIER_TDE_Pos (14UL) /*!< TDE (Bit 14) */ +#define BTIMx_DIER_TDE_Msk (0x4000UL) /*!< TDE (Bitfield-Mask: 0x01) */ +#define BTIMx_DIER_UDE_Pos (8UL) /*!< UDE (Bit 8) */ +#define BTIMx_DIER_UDE_Msk (0x100UL) /*!< UDE (Bitfield-Mask: 0x01) */ +#define BTIMx_DIER_TIE_Pos (6UL) /*!< TIE (Bit 6) */ +#define BTIMx_DIER_TIE_Msk (0x40UL) /*!< TIE (Bitfield-Mask: 0x01) */ +#define BTIMx_DIER_UIE_Pos (0UL) /*!< UIE (Bit 0) */ +#define BTIMx_DIER_UIE_Msk (0x1UL) /*!< UIE (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define BTIMx_ISR_TIF_Pos (6UL) /*!< TIF (Bit 6) */ +#define BTIMx_ISR_TIF_Msk (0x40UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define BTIMx_ISR_UIF_Pos (0UL) /*!< UIF (Bit 0) */ +#define BTIMx_ISR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define BTIMx_ICR_TIF_Pos (6UL) /*!< TIF (Bit 6) */ +#define BTIMx_ICR_TIF_Msk (0x40UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define BTIMx_ICR_UIF_Pos (0UL) /*!< UIF (Bit 0) */ +#define BTIMx_ICR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */ +/* ========================================================== EGR ========================================================== */ +#define BTIMx_EGR_TG_Pos (6UL) /*!< TG (Bit 6) */ +#define BTIMx_EGR_TG_Msk (0x40UL) /*!< TG (Bitfield-Mask: 0x01) */ +#define BTIMx_EGR_UG_Pos (0UL) /*!< UG (Bit 0) */ +#define BTIMx_EGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +#define BTIMx_CNT_UIFCPY_Pos (31UL) /*!< UIFCPY (Bit 31) */ +#define BTIMx_CNT_UIFCPY_Msk (0x80000000UL) /*!< UIFCPY (Bitfield-Mask: 0x01) */ +#define BTIMx_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define BTIMx_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== PSC ========================================================== */ +#define BTIMx_PSC_PSC_Pos (0UL) /*!< PSC (Bit 0) */ +#define BTIMx_PSC_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */ +/* ========================================================== ARR ========================================================== */ +#define BTIMx_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define BTIMx_ARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ CORDIC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CSR ========================================================== */ +#define CORDIC_CSR_BUSY_Pos (17UL) /*!< BUSY (Bit 17) */ +#define CORDIC_CSR_BUSY_Msk (0x20000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define CORDIC_CSR_EOC_Pos (16UL) /*!< EOC (Bit 16) */ +#define CORDIC_CSR_EOC_Msk (0x10000UL) /*!< EOC (Bitfield-Mask: 0x01) */ +#define CORDIC_CSR_DMAIDLE_Pos (15UL) /*!< DMAIDLE (Bit 15) */ +#define CORDIC_CSR_DMAIDLE_Msk (0x8000UL) /*!< DMAIDLE (Bitfield-Mask: 0x01) */ +#define CORDIC_CSR_DMAEOC_Pos (14UL) /*!< DMAEOC (Bit 14) */ +#define CORDIC_CSR_DMAEOC_Msk (0x4000UL) /*!< DMAEOC (Bitfield-Mask: 0x01) */ +#define CORDIC_CSR_IE_Pos (13UL) /*!< IE (Bit 13) */ +#define CORDIC_CSR_IE_Msk (0x2000UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define CORDIC_CSR_COMP_Pos (12UL) /*!< COMP (Bit 12) */ +#define CORDIC_CSR_COMP_Msk (0x1000UL) /*!< COMP (Bitfield-Mask: 0x01) */ +#define CORDIC_CSR_ITER_Pos (8UL) /*!< ITER (Bit 8) */ +#define CORDIC_CSR_ITER_Msk (0xf00UL) /*!< ITER (Bitfield-Mask: 0x0f) */ +#define CORDIC_CSR_FORMAT_Pos (7UL) /*!< SIZE (Bit 7) */ +#define CORDIC_CSR_FORMAT_Msk (0x80UL) /*!< SIZE (Bitfield-Mask: 0x01) */ +#define CORDIC_CSR_SCALE_Pos (4UL) /*!< SCALE (Bit 4) */ +#define CORDIC_CSR_SCALE_Msk (0x70UL) /*!< SCALE (Bitfield-Mask: 0x07) */ +#define CORDIC_CSR_FUNC_Pos (0UL) /*!< FUNC (Bit 0) */ +#define CORDIC_CSR_FUNC_Msk (0xfUL) /*!< FUNC (Bitfield-Mask: 0x0f) */ +/* ========================================================== DRX ========================================================== */ +#define CORDIC_X_X_Pos (0UL) /*!< DATA (Bit 0) */ +#define CORDIC_X_X_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== DRY ========================================================== */ +#define CORDIC_Y_Y_Pos (0UL) /*!< DATA (Bit 0) */ +#define CORDIC_Y_Y_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== DRZ ========================================================== */ +#define CORDIC_Z_Z_Pos (0UL) /*!< DATA (Bit 0) */ +#define CORDIC_Z_Z_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ CRC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define CRC_CR_MODE_Pos (0UL) /*!< MODE (Bit 0) */ +#define CRC_CR_MODE_Msk (0xfUL) /*!< MODE (Bitfield-Mask: 0x0f) */ +/* ========================================================== DR =========================================================== */ +#define CRC_DR_DR_Pos (0UL) /*!< DR (Bit 0) */ +#define CRC_DR_DR_Msk (0xffUL) /*!< DR (Bitfield-Mask: 0xff) */ +/* ======================================================== RESULT ========================================================= */ +#define CRC_RESULT_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define CRC_RESULT_RESULT_Msk (0xffffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define DAC_CR0_DMAUDRIE2_Pos (29UL) /*!< DMAUDRIE2 (Bit 29) */ +#define DAC_CR0_DMAUDRIE2_Msk (0x20000000UL) /*!< DMAUDRIE2 (Bitfield-Mask: 0x01) */ +#define DAC_CR0_DMAEN2_Pos (28UL) /*!< DMAEN2 (Bit 28) */ +#define DAC_CR0_DMAEN2_Msk (0x10000000UL) /*!< DMAEN2 (Bitfield-Mask: 0x01) */ +#define DAC_CR0_MAMP2_Pos (24UL) /*!< MAMP2 (Bit 24) */ +#define DAC_CR0_MAMP2_Msk (0xf000000UL) /*!< MAMP2 (Bitfield-Mask: 0x0f) */ +#define DAC_CR0_WAVE2_Pos (22UL) /*!< WAVE2 (Bit 22) */ +#define DAC_CR0_WAVE2_Msk (0xc00000UL) /*!< WAVE2 (Bitfield-Mask: 0x03) */ +#define DAC_CR0_TSEL2_Pos (18UL) /*!< TSEL2 (Bit 18) */ +#define DAC_CR0_TSEL2_Msk (0x3c0000UL) /*!< TSEL2 (Bitfield-Mask: 0x0f) */ +#define DAC_CR0_TEN2_Pos (17UL) /*!< TEN2 (Bit 17) */ +#define DAC_CR0_TEN2_Msk (0x20000UL) /*!< TEN2 (Bitfield-Mask: 0x01) */ +#define DAC_CR0_EN2_Pos (16UL) /*!< EN2 (Bit 16) */ +#define DAC_CR0_EN2_Msk (0x10000UL) /*!< EN2 (Bitfield-Mask: 0x01) */ +#define DAC_CR0_DMAUDRIE1_Pos (13UL) /*!< DMAUDRIE1 (Bit 13) */ +#define DAC_CR0_DMAUDRIE1_Msk (0x2000UL) /*!< DMAUDRIE1 (Bitfield-Mask: 0x01) */ +#define DAC_CR0_DMAEN1_Pos (12UL) /*!< DMAEN1 (Bit 12) */ +#define DAC_CR0_DMAEN1_Msk (0x1000UL) /*!< DMAEN1 (Bitfield-Mask: 0x01) */ +#define DAC_CR0_MAMP1_Pos (8UL) /*!< MAMP1 (Bit 8) */ +#define DAC_CR0_MAMP1_Msk (0xf00UL) /*!< MAMP1 (Bitfield-Mask: 0x0f) */ +#define DAC_CR0_WAVE1_Pos (6UL) /*!< WAVE1 (Bit 6) */ +#define DAC_CR0_WAVE1_Msk (0xc0UL) /*!< WAVE1 (Bitfield-Mask: 0x03) */ +#define DAC_CR0_TSEL1_Pos (2UL) /*!< TSEL1 (Bit 2) */ +#define DAC_CR0_TSEL1_Msk (0x3cUL) /*!< TSEL1 (Bitfield-Mask: 0x0f) */ +#define DAC_CR0_TEN1_Pos (1UL) /*!< TEN1 (Bit 1) */ +#define DAC_CR0_TEN1_Msk (0x2UL) /*!< TEN1 (Bitfield-Mask: 0x01) */ +#define DAC_CR0_EN1_Pos (0UL) /*!< EN1 (Bit 0) */ +#define DAC_CR0_EN1_Msk (0x1UL) /*!< EN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== SWTRGR ========================================================= */ +#define DAC_SWTRGR_SWTRIG2_Pos (1UL) /*!< SWTRIG2 (Bit 1) */ +#define DAC_SWTRGR_SWTRIG2_Msk (0x2UL) /*!< SWTRIG2 (Bitfield-Mask: 0x01) */ +#define DAC_SWTRGR_SWTRIG1_Pos (0UL) /*!< SWTRIG1 (Bit 0) */ +#define DAC_SWTRGR_SWTRIG1_Msk (0x1UL) /*!< SWTRIG1 (Bitfield-Mask: 0x01) */ +/* ======================================================== DHR12R1 ======================================================== */ +#define DAC_DHR12R1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define DAC_DHR12R1_DATA_Msk (0xfffUL) /*!< DATA (Bitfield-Mask: 0xfff) */ +/* ======================================================== DHR12L1 ======================================================== */ +#define DAC_DHR12L1_DATA_Pos (4UL) /*!< DATA (Bit 4) */ +#define DAC_DHR12L1_DATA_Msk (0xfff0UL) /*!< DATA (Bitfield-Mask: 0xfff) */ +/* ======================================================== DHR8R1 ========================================================= */ +#define DAC_DHR8R1_DATA_Pos (4UL) /*!< DATA (Bit 4) */ +#define DAC_DHR8R1_DATA_Msk (0xf0UL) /*!< DATA (Bitfield-Mask: 0x0f) */ +/* ======================================================== DHR12R2 ======================================================== */ +#define DAC_DHR12R2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define DAC_DHR12R2_DATA_Msk (0xfffUL) /*!< DATA (Bitfield-Mask: 0xfff) */ +/* ======================================================== DHR12L2 ======================================================== */ +#define DAC_DHR12L2_DATA_Pos (4UL) /*!< DATA (Bit 4) */ +#define DAC_DHR12L2_DATA_Msk (0xfff0UL) /*!< DATA (Bitfield-Mask: 0xfff) */ +/* ======================================================== DHR8R2 ========================================================= */ +#define DAC_DHR8R2_DATA_Pos (4UL) /*!< DATA (Bit 4) */ +#define DAC_DHR8R2_DATA_Msk (0xf0UL) /*!< DATA (Bitfield-Mask: 0x0f) */ +/* ======================================================== DHR12RD ======================================================== */ +#define DAC_DHR12RD_C2DATA_Pos (16UL) /*!< C2DATA (Bit 16) */ +#define DAC_DHR12RD_C2DATA_Msk (0xfff0000UL) /*!< C2DATA (Bitfield-Mask: 0xfff) */ +#define DAC_DHR12RD_C1DATA_Pos (0UL) /*!< C1DATA (Bit 0) */ +#define DAC_DHR12RD_C1DATA_Msk (0xfffUL) /*!< C1DATA (Bitfield-Mask: 0xfff) */ +/* ======================================================== DHR12LD ======================================================== */ +#define DAC_DHR12LD_C2DATA_Pos (20UL) /*!< C2DATA (Bit 20) */ +#define DAC_DHR12LD_C2DATA_Msk (0xfff00000UL) /*!< C2DATA (Bitfield-Mask: 0xfff) */ +#define DAC_DHR12LD_C1DATA_Pos (4UL) /*!< C1DATA (Bit 4) */ +#define DAC_DHR12LD_C1DATA_Msk (0xfff0UL) /*!< C1DATA (Bitfield-Mask: 0xfff) */ +/* ======================================================== DHR8RD ========================================================= */ +#define DAC_DHR8RD_C2DATA_Pos (8UL) /*!< C2DATA (Bit 8) */ +#define DAC_DHR8RD_C2DATA_Msk (0xff00UL) /*!< C2DATA (Bitfield-Mask: 0xff) */ +#define DAC_DHR8RD_C1DATA_Pos (0UL) /*!< C1DATA (Bit 0) */ +#define DAC_DHR8RD_C1DATA_Msk (0xffUL) /*!< C1DATA (Bitfield-Mask: 0xff) */ +/* ========================================================= DOR1 ========================================================== */ +#define DAC_DOR1_DMAUDR_Pos (15UL) /*!< DMAUDR (Bit 15) */ +#define DAC_DOR1_DMAUDR_Msk (0x8000UL) /*!< DMAUDR (Bitfield-Mask: 0x01) */ +#define DAC_DOR1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define DAC_DOR1_DATA_Msk (0xfffUL) /*!< DATA (Bitfield-Mask: 0xfff) */ +/* ========================================================= DOR2 ========================================================== */ +#define DAC_DOR2_DMAUDR_Pos (15UL) /*!< DMAUDR (Bit 15) */ +#define DAC_DOR2_DMAUDR_Msk (0x8000UL) /*!< DMAUDR (Bitfield-Mask: 0x01) */ +#define DAC_DOR2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define DAC_DOR2_DATA_Msk (0xfffUL) /*!< DATA (Bitfield-Mask: 0xfff) */ +/* ========================================================== CR1 ========================================================== */ +#define DAC_CR1_C2OUT_Pos (1UL) /*!< C2OUT (Bit 1) */ +#define DAC_CR1_C2OUT_Msk (0x2UL) /*!< C2OUT (Bitfield-Mask: 0x01) */ +#define DAC_CR1_C1OUT_Pos (0UL) /*!< C1OUT (Bit 0) */ +#define DAC_CR1_C1OUT_Msk (0x1UL) /*!< C1OUT (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ISR ========================================================== */ +#define DMA_ISR_TE4_Pos (13UL) /*!< TE4 (Bit 13) */ +#define DMA_ISR_TE4_Msk (0x2000UL) /*!< TE4 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC4_Pos (12UL) /*!< TC4 (Bit 12) */ +#define DMA_ISR_TC4_Msk (0x1000UL) /*!< TC4 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TE3_Pos (9UL) /*!< TE3 (Bit 9) */ +#define DMA_ISR_TE3_Msk (0x200UL) /*!< TE3 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC3_Pos (8UL) /*!< TC3 (Bit 8) */ +#define DMA_ISR_TC3_Msk (0x100UL) /*!< TC3 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TE2_Pos (5UL) /*!< TE2 (Bit 5) */ +#define DMA_ISR_TE2_Msk (0x20UL) /*!< TE2 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC2_Pos (4UL) /*!< TC2 (Bit 4) */ +#define DMA_ISR_TC2_Msk (0x10UL) /*!< TC2 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TE1_Pos (1UL) /*!< TE1 (Bit 1) */ +#define DMA_ISR_TE1_Msk (0x2UL) /*!< TE1 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC1_Pos (0UL) /*!< TC1 (Bit 0) */ +#define DMA_ISR_TC1_Msk (0x1UL) /*!< TC1 (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define DMA_ICR_TE4_Pos (13UL) /*!< TE4 (Bit 13) */ +#define DMA_ICR_TE4_Msk (0x2000UL) /*!< TE4 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC4_Pos (12UL) /*!< TC4 (Bit 12) */ +#define DMA_ICR_TC4_Msk (0x1000UL) /*!< TC4 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TE3_Pos (9UL) /*!< TE3 (Bit 9) */ +#define DMA_ICR_TE3_Msk (0x200UL) /*!< TE3 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC3_Pos (8UL) /*!< TC3 (Bit 8) */ +#define DMA_ICR_TC3_Msk (0x100UL) /*!< TC3 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TE2_Pos (5UL) /*!< TE2 (Bit 5) */ +#define DMA_ICR_TE2_Msk (0x20UL) /*!< TE2 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC2_Pos (4UL) /*!< TC2 (Bit 4) */ +#define DMA_ICR_TC2_Msk (0x10UL) /*!< TC2 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TE1_Pos (1UL) /*!< TE1 (Bit 1) */ +#define DMA_ICR_TE1_Msk (0x2UL) /*!< TE1 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC1_Pos (0UL) /*!< TC1 (Bit 0) */ +#define DMA_ICR_TC1_Msk (0x1UL) /*!< TC1 (Bitfield-Mask: 0x01) */ +/* ========================================================= CSR1 ========================================================== */ +#define DMA_CSR1_DSTLOAD_Pos (15UL) /*!< DSTLOAD (Bit 15) */ +#define DMA_CSR1_DSTLOAD_Msk (0x8000UL) /*!< DSTLOAD (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_SRCLOAD_Pos (14UL) /*!< SRCLOAD (Bit 14) */ +#define DMA_CSR1_SRCLOAD_Msk (0x4000UL) /*!< SRCLOAD (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_TE_Pos (13UL) /*!< TE (Bit 13) */ +#define DMA_CSR1_TE_Msk (0x2000UL) /*!< TE (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_TC_Pos (12UL) /*!< TC (Bit 12) */ +#define DMA_CSR1_TC_Msk (0x1000UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_RESTART_Pos (11UL) /*!< RESTART (Bit 11) */ +#define DMA_CSR1_RESTART_Msk (0x800UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR1_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR1_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR1_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR1_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR1_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR1_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR1_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR1_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR1_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR1_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= TRIG1 ========================================================= */ +#define DMA_TRIG1_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG1_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG1_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG1_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG1_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG1_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT1 ========================================================== */ +#define DMA_CNT1_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT1_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT1_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT1_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR1 ======================================================== */ +#define DMA_SRCADDR1_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR1_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR1 ======================================================== */ +#define DMA_DSTADDR1_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR1_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CCNT1 ========================================================= */ +#define DMA_CCNT1_CREPEAT_Pos (16UL) /*!< CREPEAT (Bit 16) */ +#define DMA_CCNT1_CREPEAT_Msk (0xf0000UL) /*!< CREPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CCNT1_CCNT_Pos (0UL) /*!< CCNT (Bit 0) */ +#define DMA_CCNT1_CCNT_Msk (0xffffUL) /*!< CCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CSRCADDR1 ======================================================= */ +#define DMA_CSRCADDR1_CSRCADDR_Pos (0UL) /*!< CSRCADDR (Bit 0) */ +#define DMA_CSRCADDR1_CSRCADDR_Msk (0xffffffffUL) /*!< CSRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDSTADDR1 ======================================================= */ +#define DMA_CDSTADDR1_CDSTADDR_Pos (0UL) /*!< CDSTADDR (Bit 0) */ +#define DMA_CDSTADDR1_CDSTADDR_Msk (0xffffffffUL) /*!< CDSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CSR2 ========================================================== */ +#define DMA_CSR2_DSTLOAD_Pos (15UL) /*!< DSTLOAD (Bit 15) */ +#define DMA_CSR2_DSTLOAD_Msk (0x8000UL) /*!< DSTLOAD (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_SRCLOAD_Pos (14UL) /*!< SRCLOAD (Bit 14) */ +#define DMA_CSR2_SRCLOAD_Msk (0x4000UL) /*!< SRCLOAD (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_TE_Pos (13UL) /*!< TE (Bit 13) */ +#define DMA_CSR2_TE_Msk (0x2000UL) /*!< TE (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_TC_Pos (12UL) /*!< TC (Bit 12) */ +#define DMA_CSR2_TC_Msk (0x1000UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_RESTART_Pos (11UL) /*!< RESTART (Bit 11) */ +#define DMA_CSR2_RESTART_Msk (0x800UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR2_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR2_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR2_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR2_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR2_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR2_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR2_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR2_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR2_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR2_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT2 ========================================================== */ +#define DMA_CNT2_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT2_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT2_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT2_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR2 ======================================================== */ +#define DMA_SRCADDR2_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR2_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR2 ======================================================== */ +#define DMA_DSTADDR2_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR2_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG2 ========================================================= */ +#define DMA_TRIG2_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG2_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG2_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG2_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG2_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG2_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCNT2 ========================================================= */ +#define DMA_CCNT2_CREPEAT_Pos (16UL) /*!< CREPEAT (Bit 16) */ +#define DMA_CCNT2_CREPEAT_Msk (0xf0000UL) /*!< CREPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CCNT2_CCNT_Pos (0UL) /*!< CCNT (Bit 0) */ +#define DMA_CCNT2_CCNT_Msk (0xffffUL) /*!< CCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CSRCADDR2 ======================================================= */ +#define DMA_CSRCADDR2_CSRCADDR_Pos (0UL) /*!< CSRCADDR (Bit 0) */ +#define DMA_CSRCADDR2_CSRCADDR_Msk (0xffffffffUL) /*!< CSRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDSTADDR2 ======================================================= */ +#define DMA_CDSTADDR2_CDSTADDR_Pos (0UL) /*!< CDSTADDR (Bit 0) */ +#define DMA_CDSTADDR2_CDSTADDR_Msk (0xffffffffUL) /*!< CDSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CSR3 ========================================================== */ +#define DMA_CSR3_DSTLOAD_Pos (15UL) /*!< DSTLOAD (Bit 15) */ +#define DMA_CSR3_DSTLOAD_Msk (0x8000UL) /*!< DSTLOAD (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_SRCLOAD_Pos (14UL) /*!< SRCLOAD (Bit 14) */ +#define DMA_CSR3_SRCLOAD_Msk (0x4000UL) /*!< SRCLOAD (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_TE_Pos (13UL) /*!< TE (Bit 13) */ +#define DMA_CSR3_TE_Msk (0x2000UL) /*!< TE (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_TC_Pos (12UL) /*!< TC (Bit 12) */ +#define DMA_CSR3_TC_Msk (0x1000UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_RESTART_Pos (11UL) /*!< RESTART (Bit 11) */ +#define DMA_CSR3_RESTART_Msk (0x800UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR3_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR3_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR3_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR3_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR3_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR3_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR3_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR3_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR3_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR3_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT3 ========================================================== */ +#define DMA_CNT3_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT3_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT3_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT3_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR3 ======================================================== */ +#define DMA_SRCADDR3_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR3_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR3 ======================================================== */ +#define DMA_DSTADDR3_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR3_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG3 ========================================================= */ +#define DMA_TRIG3_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG3_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG3_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG3_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG3_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG3_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCNT3 ========================================================= */ +#define DMA_CCNT3_CREPEAT_Pos (16UL) /*!< CREPEAT (Bit 16) */ +#define DMA_CCNT3_CREPEAT_Msk (0xf0000UL) /*!< CREPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CCNT3_CCNT_Pos (0UL) /*!< CCNT (Bit 0) */ +#define DMA_CCNT3_CCNT_Msk (0xffffUL) /*!< CCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CSRCADDR3 ======================================================= */ +#define DMA_CSRCADDR3_CSRCADDR_Pos (0UL) /*!< CSRCADDR (Bit 0) */ +#define DMA_CSRCADDR3_CSRCADDR_Msk (0xffffffffUL) /*!< CSRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDSTADDR3 ======================================================= */ +#define DMA_CDSTADDR3_CDSTADDR_Pos (0UL) /*!< CDSTADDR (Bit 0) */ +#define DMA_CDSTADDR3_CDSTADDR_Msk (0xffffffffUL) /*!< CDSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CSR4 ========================================================== */ +#define DMA_CSR4_DSTLOAD_Pos (15UL) /*!< DSTLOAD (Bit 15) */ +#define DMA_CSR4_DSTLOAD_Msk (0x8000UL) /*!< DSTLOAD (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_SRCLOAD_Pos (14UL) /*!< SRCLOAD (Bit 14) */ +#define DMA_CSR4_SRCLOAD_Msk (0x4000UL) /*!< SRCLOAD (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_TE_Pos (13UL) /*!< TE (Bit 13) */ +#define DMA_CSR4_TE_Msk (0x2000UL) /*!< TE (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_TC_Pos (12UL) /*!< TC (Bit 12) */ +#define DMA_CSR4_TC_Msk (0x1000UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_RESTART_Pos (11UL) /*!< RESTART (Bit 11) */ +#define DMA_CSR4_RESTART_Msk (0x800UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR4_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR4_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR4_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR4_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR4_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR4_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR4_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR4_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR4_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR4_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT4 ========================================================== */ +#define DMA_CNT4_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT4_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT4_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT4_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR4 ======================================================== */ +#define DMA_SRCADDR4_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR4_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR4 ======================================================== */ +#define DMA_DSTADDR4_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR4_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG4 ========================================================= */ +#define DMA_TRIG4_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG4_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG4_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG4_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG4_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG4_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCNT4 ========================================================= */ +#define DMA_CCNT4_CREPEAT_Pos (16UL) /*!< CREPEAT (Bit 16) */ +#define DMA_CCNT4_CREPEAT_Msk (0xf0000UL) /*!< CREPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CCNT4_CCNT_Pos (0UL) /*!< CCNT (Bit 0) */ +#define DMA_CCNT4_CCNT_Msk (0xffffUL) /*!< CCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CSRCADDR4 ======================================================= */ +#define DMA_CSRCADDR4_CSRCADDR_Pos (0UL) /*!< CSRCADDR (Bit 0) */ +#define DMA_CSRCADDR4_CSRCADDR_Msk (0xffffffffUL) /*!< CSRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDSTADDR4 ======================================================= */ +#define DMA_CDSTADDR4_CDSTADDR_Pos (0UL) /*!< CDSTADDR (Bit 0) */ +#define DMA_CDSTADDR4_CDSTADDR_Msk (0xffffffffUL) /*!< CDSTADDR (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ DMACHANNEL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CSR ========================================================== */ +#define DMACHx_CSR_DSTLOAD_Pos (15UL) /*!< DSTLOAD (Bit 15) */ +#define DMACHx_CSR_DSTLOAD_Msk (0x8000UL) /*!< DSTLOAD (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_SRCLOAD_Pos (14UL) /*!< SRCLOAD (Bit 14) */ +#define DMACHx_CSR_SRCLOAD_Msk (0x4000UL) /*!< SRCLOAD (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_TE_Pos (13UL) /*!< TE (Bit 13) */ +#define DMACHx_CSR_TE_Msk (0x2000UL) /*!< TE (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_TC_Pos (12UL) /*!< TC (Bit 12) */ +#define DMACHx_CSR_TC_Msk (0x1000UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_RESTART_Pos (11UL) /*!< RESTART (Bit 11) */ +#define DMACHx_CSR_RESTART_Msk (0x800UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMACHx_CSR_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMACHx_CSR_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMACHx_CSR_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMACHx_CSR_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMACHx_CSR_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMACHx_CSR_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMACHx_CSR_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMACHx_CSR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMACHx_CSR_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMACHx_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +#define DMACHx_CNT_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMACHx_CNT_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMACHx_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMACHx_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================== SRCADDR ======================================================== */ +#define DMACHx_SRCADDR_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMACHx_SRCADDR_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DSTADDR ======================================================== */ +#define DMACHx_DSTADDR_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMACHx_DSTADDR_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG ========================================================== */ +#define DMACHx_TRIG_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMACHx_TRIG_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMACHx_TRIG_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMACHx_TRIG_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMACHx_TRIG_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMACHx_TRIG_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCNT ========================================================== */ +#define DMACHx_CCNT_CREPEAT_Pos (16UL) /*!< CREPEAT (Bit 16) */ +#define DMACHx_CCNT_CREPEAT_Msk (0xf0000UL) /*!< CREPEAT (Bitfield-Mask: 0x0f) */ +#define DMACHx_CCNT_CCNT_Pos (0UL) /*!< CCNT (Bit 0) */ +#define DMACHx_CCNT_CCNT_Msk (0xffffUL) /*!< CCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CSRCADDR ======================================================== */ +#define DMACHx_CSRCADDR_CSRCADDR_Pos (0UL) /*!< CSRCADDR (Bit 0) */ +#define DMACHx_CSRCADDR_CSRCADDR_Msk (0xffffffffUL) /*!< CSRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDSTADDR ======================================================== */ +#define DMACHx_CDSTADDR_CDSTADDR_Pos (0UL) /*!< CDSTADDR (Bit 0) */ +#define DMACHx_CDSTADDR_CDSTADDR_Msk (0xffffffffUL) /*!< CDSTADDR (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ EAU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CSR ========================================================== */ +#define EAU_CSR_BUSY_Pos (4UL) /*!< BUSY (Bit 4) */ +#define EAU_CSR_BUSY_Msk (0x10UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define EAU_CSR_ZERO_Pos (3UL) /*!< ZERO (Bit 3) */ +#define EAU_CSR_ZERO_Msk (0x8UL) /*!< ZERO (Bitfield-Mask: 0x01) */ +#define EAU_CSR_OVR_Pos (2UL) /*!< OVR (Bit 2) */ +#define EAU_CSR_OVR_Msk (0x4UL) /*!< OVR (Bitfield-Mask: 0x01) */ +#define EAU_CSR_MODE_Pos (0UL) /*!< MODE (Bit 0) */ +#define EAU_CSR_MODE_Msk (0x3UL) /*!< MODE (Bitfield-Mask: 0x03) */ +/* ======================================================= DIVIDEND ======================================================== */ +#define EAU_DIVIDEND_DIVIDEND_Pos (0UL) /*!< DIVIDEND (Bit 0) */ +#define EAU_DIVIDEND_DIVIDEND_Msk (0xffffffffUL) /*!< DIVIDEND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DIVISOR ======================================================== */ +#define EAU_DIVISOR_DIVISOR_Pos (0UL) /*!< DIVISOR (Bit 0) */ +#define EAU_DIVISOR_DIVISOR_Msk (0xffffffffUL) /*!< DIVISOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= QUOTIENT ======================================================== */ +#define EAU_QUOTIENT_QUOTIENT_Pos (0UL) /*!< QUOTIENT (Bit 0) */ +#define EAU_QUOTIENT_QUOTIENT_Msk (0xffffffffUL) /*!< QUOTIENT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= REMAINDER ======================================================= */ +#define EAU_REMAINDER_REMAINDER_Pos (0UL) /*!< REMAINDER (Bit 0) */ +#define EAU_REMAINDER_REMAINDER_Msk (0xffffffffUL) /*!< REMAINDER (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ FLASH ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define FLASH_CR1_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define FLASH_CR1_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define FLASH_CR1_SECURITY_Pos (5UL) /*!< SECURITY (Bit 5) */ +#define FLASH_CR1_SECURITY_Msk (0x60UL) /*!< SECURITY (Bitfield-Mask: 0x03) */ +#define FLASH_CR1_MODE_Pos (0UL) /*!< MODE (Bit 0) */ +#define FLASH_CR1_MODE_Msk (0x3UL) /*!< MODE (Bitfield-Mask: 0x03) */ +/* ========================================================== CR2 ========================================================== */ +#define FLASH_CR2_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define FLASH_CR2_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define FLASH_CR2_CACHEINVALID_Pos (5UL) /*!< CACHEINVALID (Bit 5) */ +#define FLASH_CR2_CACHEINVALID_Msk (0x20UL) /*!< CACHEINVALID (Bitfield-Mask: 0x01) */ +#define FLASH_CR2_CACHE_Pos (4UL) /*!< CACHE (Bit 4) */ +#define FLASH_CR2_CACHE_Msk (0x10UL) /*!< CACHE (Bitfield-Mask: 0x01) */ +#define FLASH_CR2_FETCH_Pos (3UL) /*!< FETCH (Bit 3) */ +#define FLASH_CR2_FETCH_Msk (0x8UL) /*!< FETCH (Bitfield-Mask: 0x01) */ +#define FLASH_CR2_WAIT_Pos (0UL) /*!< WAIT (Bit 0) */ +#define FLASH_CR2_WAIT_Msk (0x7UL) /*!< WAIT (Bitfield-Mask: 0x07) */ +/* ======================================================= PAGELOCK ======================================================== */ +#define FLASH_PAGELOCK_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define FLASH_PAGELOCK_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define FLASH_PAGELOCK_LOCK15_Pos (15UL) /*!< LOCK15 (Bit 15) */ +#define FLASH_PAGELOCK_LOCK15_Msk (0x8000UL) /*!< LOCK15 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK14_Pos (14UL) /*!< LOCK14 (Bit 14) */ +#define FLASH_PAGELOCK_LOCK14_Msk (0x4000UL) /*!< LOCK14 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK13_Pos (13UL) /*!< LOCK13 (Bit 13) */ +#define FLASH_PAGELOCK_LOCK13_Msk (0x2000UL) /*!< LOCK13 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK12_Pos (12UL) /*!< LOCK12 (Bit 12) */ +#define FLASH_PAGELOCK_LOCK12_Msk (0x1000UL) /*!< LOCK12 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK11_Pos (11UL) /*!< LOCK11 (Bit 11) */ +#define FLASH_PAGELOCK_LOCK11_Msk (0x800UL) /*!< LOCK11 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK10_Pos (10UL) /*!< LOCK10 (Bit 10) */ +#define FLASH_PAGELOCK_LOCK10_Msk (0x400UL) /*!< LOCK10 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK9_Pos (9UL) /*!< LOCK9 (Bit 9) */ +#define FLASH_PAGELOCK_LOCK9_Msk (0x200UL) /*!< LOCK9 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK8_Pos (8UL) /*!< LOCK8 (Bit 8) */ +#define FLASH_PAGELOCK_LOCK8_Msk (0x100UL) /*!< LOCK8 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK7_Pos (7UL) /*!< LOCK7 (Bit 7) */ +#define FLASH_PAGELOCK_LOCK7_Msk (0x80UL) /*!< LOCK7 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK6_Pos (6UL) /*!< LOCK6 (Bit 6) */ +#define FLASH_PAGELOCK_LOCK6_Msk (0x40UL) /*!< LOCK6 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK5_Pos (5UL) /*!< LOCK5 (Bit 5) */ +#define FLASH_PAGELOCK_LOCK5_Msk (0x20UL) /*!< LOCK5 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK4_Pos (4UL) /*!< LOCK4 (Bit 4) */ +#define FLASH_PAGELOCK_LOCK4_Msk (0x10UL) /*!< LOCK4 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK3_Pos (3UL) /*!< LOCK3 (Bit 3) */ +#define FLASH_PAGELOCK_LOCK3_Msk (0x8UL) /*!< LOCK3 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK2_Pos (2UL) /*!< LOCK2 (Bit 2) */ +#define FLASH_PAGELOCK_LOCK2_Msk (0x4UL) /*!< LOCK2 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK1_Pos (1UL) /*!< LOCK1 (Bit 1) */ +#define FLASH_PAGELOCK_LOCK1_Msk (0x2UL) /*!< LOCK1 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK0_Pos (0UL) /*!< LOCK0 (Bit 0) */ +#define FLASH_PAGELOCK_LOCK0_Msk (0x1UL) /*!< LOCK0 (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define FLASH_IER_PROG_Pos (4UL) /*!< PROG (Bit 4) */ +#define FLASH_IER_PROG_Msk (0x10UL) /*!< PROG (Bitfield-Mask: 0x01) */ +#define FLASH_IER_CACHEON_Pos (3UL) /*!< CACHEON (Bit 3) */ +#define FLASH_IER_CACHEON_Msk (0x8UL) /*!< CACHEON (Bitfield-Mask: 0x01) */ +#define FLASH_IER_SDKERR_Pos (2UL) /*!< SDKERR (Bit 2) */ +#define FLASH_IER_SDKERR_Msk (0x4UL) /*!< SDKERR (Bitfield-Mask: 0x01) */ +#define FLASH_IER_PAGELOCK_Pos (1UL) /*!< PAGELOCK (Bit 1) */ +#define FLASH_IER_PAGELOCK_Msk (0x2UL) /*!< PAGELOCK (Bitfield-Mask: 0x01) */ +#define FLASH_IER_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define FLASH_IER_PC_Msk (0x1UL) /*!< PC (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define FLASH_ISR_BUSY_Pos (5UL) /*!< BUSY (Bit 5) */ +#define FLASH_ISR_BUSY_Msk (0x20UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define FLASH_ISR_PROG_Pos (4UL) /*!< PROG (Bit 4) */ +#define FLASH_ISR_PROG_Msk (0x10UL) /*!< PROG (Bitfield-Mask: 0x01) */ +#define FLASH_ISR_CACHEON_Pos (3UL) /*!< CACHEON (Bit 3) */ +#define FLASH_ISR_CACHEON_Msk (0x8UL) /*!< CACHEON (Bitfield-Mask: 0x01) */ +#define FLASH_ISR_SDKERR_Pos (2UL) /*!< SDKERR (Bit 2) */ +#define FLASH_ISR_SDKERR_Msk (0x4UL) /*!< SDKERR (Bitfield-Mask: 0x01) */ +#define FLASH_ISR_PAGELOCK_Pos (1UL) /*!< PAGELOCK (Bit 1) */ +#define FLASH_ISR_PAGELOCK_Msk (0x2UL) /*!< PAGELOCK (Bitfield-Mask: 0x01) */ +#define FLASH_ISR_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define FLASH_ISR_PC_Msk (0x1UL) /*!< PC (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define FLASH_ICR_PROG_Pos (4UL) /*!< PROG (Bit 4) */ +#define FLASH_ICR_PROG_Msk (0x10UL) /*!< PROG (Bitfield-Mask: 0x01) */ +#define FLASH_ICR_CACHEON_Pos (3UL) /*!< CACHEON (Bit 3) */ +#define FLASH_ICR_CACHEON_Msk (0x8UL) /*!< CACHEON (Bitfield-Mask: 0x01) */ +#define FLASH_ICR_SDKERR_Pos (2UL) /*!< SDKERR (Bit 2) */ +#define FLASH_ICR_SDKERR_Msk (0x4UL) /*!< SDKERR (Bitfield-Mask: 0x01) */ +#define FLASH_ICR_PAGELOCK_Pos (1UL) /*!< PAGELOCK (Bit 1) */ +#define FLASH_ICR_PAGELOCK_Msk (0x2UL) /*!< PAGELOCK (Bitfield-Mask: 0x01) */ +#define FLASH_ICR_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define FLASH_ICR_PC_Msk (0x1UL) /*!< PC (Bitfield-Mask: 0x01) */ +/* ======================================================== SDKCFR ========================================================= */ +#define FLASH_SDKCFR_END_Pos (8UL) /*!< END (Bit 8) */ +#define FLASH_SDKCFR_END_Msk (0x7f00UL) /*!< END (Bitfield-Mask: 0x7f) */ +#define FLASH_SDKCFR_START_Pos (0UL) /*!< START (Bit 0) */ +#define FLASH_SDKCFR_START_Msk (0x7fUL) /*!< START (Bitfield-Mask: 0x7f) */ + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DIR ========================================================== */ +#define GPIOx_DIR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_DIR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_DIR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_DIR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_DIR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_DIR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_DIR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_DIR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_DIR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_DIR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_DIR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_DIR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_DIR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_DIR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_DIR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_DIR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_DIR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================= OPENDRAIN ======================================================= */ +#define GPIOx_OPENDRAIN_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_OPENDRAIN_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_OPENDRAIN_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_OPENDRAIN_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_OPENDRAIN_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_OPENDRAIN_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_OPENDRAIN_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_OPENDRAIN_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_OPENDRAIN_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_OPENDRAIN_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_OPENDRAIN_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_OPENDRAIN_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_OPENDRAIN_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_OPENDRAIN_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_OPENDRAIN_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_OPENDRAIN_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_OPENDRAIN_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== PUR ========================================================== */ +#define GPIOx_PUR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_PUR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_PUR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_PUR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_PUR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_PUR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_PUR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_PUR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_PUR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_PUR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_PUR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_PUR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_PUR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_PUR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_PUR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_PUR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_PUR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= AFRH ========================================================== */ +#define GPIOx_AFRH_PIN15_Pos (28UL) /*!< PIN15 (Bit 28) */ +#define GPIOx_AFRH_PIN15_Msk (0xf0000000UL) /*!< PIN15 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_PIN14_Pos (24UL) /*!< PIN14 (Bit 24) */ +#define GPIOx_AFRH_PIN14_Msk (0xf000000UL) /*!< PIN14 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_PIN13_Pos (20UL) /*!< PIN13 (Bit 20) */ +#define GPIOx_AFRH_PIN13_Msk (0xf00000UL) /*!< PIN13 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_PIN12_Pos (16UL) /*!< PIN12 (Bit 16) */ +#define GPIOx_AFRH_PIN12_Msk (0xf0000UL) /*!< PIN12 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_PIN11_Pos (12UL) /*!< PIN11 (Bit 12) */ +#define GPIOx_AFRH_PIN11_Msk (0xf000UL) /*!< PIN11 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_PIN10_Pos (8UL) /*!< PIN10 (Bit 8) */ +#define GPIOx_AFRH_PIN10_Msk (0xf00UL) /*!< PIN10 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_PIN9_Pos (4UL) /*!< PIN9 (Bit 4) */ +#define GPIOx_AFRH_PIN9_Msk (0xf0UL) /*!< PIN9 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_PIN8_Pos (0UL) /*!< PIN8 (Bit 0) */ +#define GPIOx_AFRH_PIN8_Msk (0xfUL) /*!< PIN8 (Bitfield-Mask: 0x0f) */ +/* ========================================================= AFRL ========================================================== */ +#define GPIOx_AFRL_PIN7_Pos (28UL) /*!< PIN7 (Bit 28) */ +#define GPIOx_AFRL_PIN7_Msk (0xf0000000UL) /*!< PIN7 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_PIN6_Pos (24UL) /*!< PIN6 (Bit 24) */ +#define GPIOx_AFRL_PIN6_Msk (0xf000000UL) /*!< PIN6 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_PIN5_Pos (20UL) /*!< PIN5 (Bit 20) */ +#define GPIOx_AFRL_PIN5_Msk (0xf00000UL) /*!< PIN5 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_PIN4_Pos (16UL) /*!< PIN4 (Bit 16) */ +#define GPIOx_AFRL_PIN4_Msk (0xf0000UL) /*!< PIN4 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_PIN3_Pos (12UL) /*!< PIN3 (Bit 12) */ +#define GPIOx_AFRL_PIN3_Msk (0xf000UL) /*!< PIN3 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_PIN2_Pos (8UL) /*!< PIN2 (Bit 8) */ +#define GPIOx_AFRL_PIN2_Msk (0xf00UL) /*!< PIN2 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_PIN1_Pos (4UL) /*!< PIN1 (Bit 4) */ +#define GPIOx_AFRL_PIN1_Msk (0xf0UL) /*!< PIN1 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_AFRL_PIN0_Msk (0xfUL) /*!< PIN0 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ANALOG ========================================================= */ +#define GPIOx_ANALOG_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_ANALOG_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_ANALOG_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_ANALOG_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_ANALOG_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_ANALOG_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_ANALOG_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_ANALOG_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_ANALOG_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_ANALOG_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_ANALOG_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_ANALOG_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_ANALOG_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_ANALOG_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_ANALOG_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_ANALOG_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_ANALOG_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== RISEIE ========================================================= */ +#define GPIOx_RISEIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_RISEIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_RISEIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_RISEIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_RISEIE_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_RISEIE_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_RISEIE_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_RISEIE_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_RISEIE_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_RISEIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_RISEIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_RISEIE_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_RISEIE_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_RISEIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_RISEIE_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_RISEIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_RISEIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FALLIE ========================================================= */ +#define GPIOx_FALLIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_FALLIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_FALLIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_FALLIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_FALLIE_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_FALLIE_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_FALLIE_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_FALLIE_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_FALLIE_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_FALLIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_FALLIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_FALLIE_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_FALLIE_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_FALLIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_FALLIE_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_FALLIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_FALLIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define GPIOx_ISR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_ISR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_ISR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_ISR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_ISR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_ISR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_ISR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_ISR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_ISR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_ISR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_ISR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_ISR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_ISR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_ISR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_ISR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_ISR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_ISR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define GPIOx_ICR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_ICR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_ICR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_ICR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_ICR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_ICR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_ICR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_ICR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_ICR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_ICR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_ICR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_ICR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_ICR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_ICR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_ICR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_ICR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_ICR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FILTER ========================================================= */ +#define GPIOx_FILTER_FLTCLK_Pos (16UL) /*!< FLTCLK (Bit 16) */ +#define GPIOx_FILTER_FLTCLK_Msk (0x70000UL) /*!< FLTCLK (Bitfield-Mask: 0x07) */ +#define GPIOx_FILTER_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_FILTER_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_FILTER_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_FILTER_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_FILTER_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_FILTER_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_FILTER_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_FILTER_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_FILTER_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_FILTER_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_FILTER_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_FILTER_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_FILTER_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_FILTER_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_FILTER_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_FILTER_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_FILTER_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== IDR ========================================================== */ +#define GPIOx_IDR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_IDR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_IDR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_IDR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_IDR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_IDR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_IDR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_IDR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_IDR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_IDR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_IDR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_IDR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_IDR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_IDR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_IDR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_IDR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_IDR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ODR ========================================================== */ +#define GPIOx_ODR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_ODR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_ODR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_ODR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_ODR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_ODR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_ODR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_ODR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_ODR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_ODR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_ODR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_ODR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_ODR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_ODR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_ODR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_ODR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_ODR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== BRR ========================================================== */ +#define GPIOx_BRR_BRR15_Pos (15UL) /*!< BRR15 (Bit 15) */ +#define GPIOx_BRR_BRR15_Msk (0x8000UL) /*!< BRR15 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR14_Pos (14UL) /*!< BRR14 (Bit 14) */ +#define GPIOx_BRR_BRR14_Msk (0x4000UL) /*!< BRR14 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR13_Pos (13UL) /*!< BRR13 (Bit 13) */ +#define GPIOx_BRR_BRR13_Msk (0x2000UL) /*!< BRR13 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR12_Pos (12UL) /*!< BRR12 (Bit 12) */ +#define GPIOx_BRR_BRR12_Msk (0x1000UL) /*!< BRR12 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR11_Pos (11UL) /*!< BRR11 (Bit 11) */ +#define GPIOx_BRR_BRR11_Msk (0x800UL) /*!< BRR11 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR10_Pos (10UL) /*!< BRR10 (Bit 10) */ +#define GPIOx_BRR_BRR10_Msk (0x400UL) /*!< BRR10 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR9_Pos (9UL) /*!< BRR9 (Bit 9) */ +#define GPIOx_BRR_BRR9_Msk (0x200UL) /*!< BRR9 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR8_Pos (8UL) /*!< BRR8 (Bit 8) */ +#define GPIOx_BRR_BRR8_Msk (0x100UL) /*!< BRR8 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR7_Pos (7UL) /*!< BRR7 (Bit 7) */ +#define GPIOx_BRR_BRR7_Msk (0x80UL) /*!< BRR7 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR6_Pos (6UL) /*!< BRR6 (Bit 6) */ +#define GPIOx_BRR_BRR6_Msk (0x40UL) /*!< BRR6 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR5_Pos (5UL) /*!< BRR5 (Bit 5) */ +#define GPIOx_BRR_BRR5_Msk (0x20UL) /*!< BRR5 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR4_Pos (4UL) /*!< BRR4 (Bit 4) */ +#define GPIOx_BRR_BRR4_Msk (0x10UL) /*!< BRR4 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR3_Pos (3UL) /*!< BRR3 (Bit 3) */ +#define GPIOx_BRR_BRR3_Msk (0x8UL) /*!< BRR3 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR2_Pos (2UL) /*!< BRR2 (Bit 2) */ +#define GPIOx_BRR_BRR2_Msk (0x4UL) /*!< BRR2 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR1_Pos (1UL) /*!< BRR1 (Bit 1) */ +#define GPIOx_BRR_BRR1_Msk (0x2UL) /*!< BRR1 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR0_Pos (0UL) /*!< BRR0 (Bit 0) */ +#define GPIOx_BRR_BRR0_Msk (0x1UL) /*!< BRR0 (Bitfield-Mask: 0x01) */ +/* ========================================================= BSRR ========================================================== */ +#define GPIOx_BSRR_BRR15_Pos (31UL) /*!< BRR15 (Bit 31) */ +#define GPIOx_BSRR_BRR15_Msk (0x80000000UL) /*!< BRR15 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR14_Pos (30UL) /*!< BRR14 (Bit 30) */ +#define GPIOx_BSRR_BRR14_Msk (0x40000000UL) /*!< BRR14 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR13_Pos (29UL) /*!< BRR13 (Bit 29) */ +#define GPIOx_BSRR_BRR13_Msk (0x20000000UL) /*!< BRR13 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR12_Pos (28UL) /*!< BRR12 (Bit 28) */ +#define GPIOx_BSRR_BRR12_Msk (0x10000000UL) /*!< BRR12 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR11_Pos (27UL) /*!< BRR11 (Bit 27) */ +#define GPIOx_BSRR_BRR11_Msk (0x8000000UL) /*!< BRR11 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR10_Pos (26UL) /*!< BRR10 (Bit 26) */ +#define GPIOx_BSRR_BRR10_Msk (0x4000000UL) /*!< BRR10 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR9_Pos (25UL) /*!< BRR9 (Bit 25) */ +#define GPIOx_BSRR_BRR9_Msk (0x2000000UL) /*!< BRR9 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR8_Pos (24UL) /*!< BRR8 (Bit 24) */ +#define GPIOx_BSRR_BRR8_Msk (0x1000000UL) /*!< BRR8 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR7_Pos (23UL) /*!< BRR7 (Bit 23) */ +#define GPIOx_BSRR_BRR7_Msk (0x800000UL) /*!< BRR7 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR6_Pos (22UL) /*!< BRR6 (Bit 22) */ +#define GPIOx_BSRR_BRR6_Msk (0x400000UL) /*!< BRR6 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR5_Pos (21UL) /*!< BRR5 (Bit 21) */ +#define GPIOx_BSRR_BRR5_Msk (0x200000UL) /*!< BRR5 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR4_Pos (20UL) /*!< BRR4 (Bit 20) */ +#define GPIOx_BSRR_BRR4_Msk (0x100000UL) /*!< BRR4 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR3_Pos (19UL) /*!< BRR3 (Bit 19) */ +#define GPIOx_BSRR_BRR3_Msk (0x80000UL) /*!< BRR3 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR2_Pos (18UL) /*!< BRR2 (Bit 18) */ +#define GPIOx_BSRR_BRR2_Msk (0x40000UL) /*!< BRR2 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR1_Pos (17UL) /*!< BRR1 (Bit 17) */ +#define GPIOx_BSRR_BRR1_Msk (0x20000UL) /*!< BRR1 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR0_Pos (16UL) /*!< BRR0 (Bit 16) */ +#define GPIOx_BSRR_BRR0_Msk (0x10000UL) /*!< BRR0 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS15_Pos (15UL) /*!< BSS15 (Bit 15) */ +#define GPIOx_BSRR_BSS15_Msk (0x8000UL) /*!< BSS15 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS14_Pos (14UL) /*!< BSS14 (Bit 14) */ +#define GPIOx_BSRR_BSS14_Msk (0x4000UL) /*!< BSS14 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS13_Pos (13UL) /*!< BSS13 (Bit 13) */ +#define GPIOx_BSRR_BSS13_Msk (0x2000UL) /*!< BSS13 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS12_Pos (12UL) /*!< BSS12 (Bit 12) */ +#define GPIOx_BSRR_BSS12_Msk (0x1000UL) /*!< BSS12 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS11_Pos (11UL) /*!< BSS11 (Bit 11) */ +#define GPIOx_BSRR_BSS11_Msk (0x800UL) /*!< BSS11 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS10_Pos (10UL) /*!< BSS10 (Bit 10) */ +#define GPIOx_BSRR_BSS10_Msk (0x400UL) /*!< BSS10 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS9_Pos (9UL) /*!< BSS9 (Bit 9) */ +#define GPIOx_BSRR_BSS9_Msk (0x200UL) /*!< BSS9 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS8_Pos (8UL) /*!< BSS8 (Bit 8) */ +#define GPIOx_BSRR_BSS8_Msk (0x100UL) /*!< BSS8 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS7_Pos (7UL) /*!< BSS7 (Bit 7) */ +#define GPIOx_BSRR_BSS7_Msk (0x80UL) /*!< BSS7 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS6_Pos (6UL) /*!< BSS6 (Bit 6) */ +#define GPIOx_BSRR_BSS6_Msk (0x40UL) /*!< BSS6 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS5_Pos (5UL) /*!< BSS5 (Bit 5) */ +#define GPIOx_BSRR_BSS5_Msk (0x20UL) /*!< BSS5 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS4_Pos (4UL) /*!< BSS4 (Bit 4) */ +#define GPIOx_BSRR_BSS4_Msk (0x10UL) /*!< BSS4 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS3_Pos (3UL) /*!< BSS3 (Bit 3) */ +#define GPIOx_BSRR_BSS3_Msk (0x8UL) /*!< BSS3 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS2_Pos (2UL) /*!< BSS2 (Bit 2) */ +#define GPIOx_BSRR_BSS2_Msk (0x4UL) /*!< BSS2 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS1_Pos (1UL) /*!< BSS1 (Bit 1) */ +#define GPIOx_BSRR_BSS1_Msk (0x2UL) /*!< BSS1 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS0_Pos (0UL) /*!< BSS0 (Bit 0) */ +#define GPIOx_BSRR_BSS0_Msk (0x1UL) /*!< BSS0 (Bitfield-Mask: 0x01) */ +/* ========================================================== TOG ========================================================== */ +#define GPIOx_TOG_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_TOG_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_TOG_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_TOG_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_TOG_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_TOG_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_TOG_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_TOG_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_TOG_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_TOG_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_TOG_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_TOG_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_TOG_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_TOG_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_TOG_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_TOG_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_TOG_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GTIM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define GTIMx_CR1_UIFREMAP_Pos (11UL) /*!< UIFREMAP (Bit 11) */ +#define GTIMx_CR1_UIFREMAP_Msk (0x800UL) /*!< UIFREMAP (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_CKD_Pos (8UL) /*!< CKD (Bit 8) */ +#define GTIMx_CR1_CKD_Msk (0x300UL) /*!< CKD (Bitfield-Mask: 0x03) */ +#define GTIMx_CR1_ARPE_Pos (7UL) /*!< ARPE (Bit 7) */ +#define GTIMx_CR1_ARPE_Msk (0x80UL) /*!< ARPE (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_CMS_Pos (5UL) /*!< CMS (Bit 5) */ +#define GTIMx_CR1_CMS_Msk (0x60UL) /*!< CMS (Bitfield-Mask: 0x03) */ +#define GTIMx_CR1_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define GTIMx_CR1_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_OPM_Pos (3UL) /*!< OPM (Bit 3) */ +#define GTIMx_CR1_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_URS_Pos (2UL) /*!< URS (Bit 2) */ +#define GTIMx_CR1_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */ +#define GTIMx_CR1_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_CEN_Pos (0UL) /*!< CEN (Bit 0) */ +#define GTIMx_CR1_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define GTIMx_CR2_MMSH_Pos (25UL) /*!< MMSH (Bit 25) */ +#define GTIMx_CR2_MMSH_Msk (0x6000000UL) /*!< MMSH (Bitfield-Mask: 0x03) */ +#define GTIMx_CR2_TI1S_Pos (7UL) /*!< TI1S (Bit 7) */ +#define GTIMx_CR2_TI1S_Msk (0x80UL) /*!< TI1S (Bitfield-Mask: 0x01) */ +#define GTIMx_CR2_MMS_Pos (4UL) /*!< MMS (Bit 4) */ +#define GTIMx_CR2_MMS_Msk (0x70UL) /*!< MMS (Bitfield-Mask: 0x07) */ +#define GTIMx_CR2_CCDS_Pos (3UL) /*!< CCDS (Bit 3) */ +#define GTIMx_CR2_CCDS_Msk (0x8UL) /*!< CCDS (Bitfield-Mask: 0x01) */ +/* ========================================================= SMCR ========================================================== */ +#define GTIMx_SMCR_SMSPS_Pos (25UL) /*!< SMSPS (Bit 25) */ +#define GTIMx_SMCR_SMSPS_Msk (0x2000000UL) /*!< SMSPS (Bitfield-Mask: 0x01) */ +#define GTIMx_SMCR_SMSPE_Pos (24UL) /*!< SMSPE (Bit 24) */ +#define GTIMx_SMCR_SMSPE_Msk (0x1000000UL) /*!< SMSPE (Bitfield-Mask: 0x01) */ +#define GTIMx_SMCR_TSH_Pos (20UL) /*!< TSH (Bit 20) */ +#define GTIMx_SMCR_TSH_Msk (0x300000UL) /*!< TSH (Bitfield-Mask: 0x03) */ +#define GTIMx_SMCR_SMSH_Pos (16UL) /*!< SMSH (Bit 16) */ +#define GTIMx_SMCR_SMSH_Msk (0x10000UL) /*!< SMSH (Bitfield-Mask: 0x01) */ +#define GTIMx_SMCR_ETP_Pos (15UL) /*!< ETP (Bit 15) */ +#define GTIMx_SMCR_ETP_Msk (0x8000UL) /*!< ETP (Bitfield-Mask: 0x01) */ +#define GTIMx_SMCR_ECE_Pos (14UL) /*!< ECE (Bit 14) */ +#define GTIMx_SMCR_ECE_Msk (0x4000UL) /*!< ECE (Bitfield-Mask: 0x01) */ +#define GTIMx_SMCR_ETPS_Pos (12UL) /*!< ETPS (Bit 12) */ +#define GTIMx_SMCR_ETPS_Msk (0x3000UL) /*!< ETPS (Bitfield-Mask: 0x03) */ +#define GTIMx_SMCR_ETF_Pos (8UL) /*!< ETF (Bit 8) */ +#define GTIMx_SMCR_ETF_Msk (0xf00UL) /*!< ETF (Bitfield-Mask: 0x0f) */ +#define GTIMx_SMCR_MSM_Pos (7UL) /*!< MSM (Bit 7) */ +#define GTIMx_SMCR_MSM_Msk (0x80UL) /*!< MSM (Bitfield-Mask: 0x01) */ +#define GTIMx_SMCR_TS_Pos (4UL) /*!< TS (Bit 4) */ +#define GTIMx_SMCR_TS_Msk (0x70UL) /*!< TS (Bitfield-Mask: 0x07) */ +#define GTIMx_SMCR_OCCS_Pos (3UL) /*!< OCCS (Bit 3) */ +#define GTIMx_SMCR_OCCS_Msk (0x8UL) /*!< OCCS (Bitfield-Mask: 0x01) */ +#define GTIMx_SMCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */ +#define GTIMx_SMCR_SMS_Msk (0x7UL) /*!< SMS (Bitfield-Mask: 0x07) */ +/* ========================================================== IER ========================================================== */ +#define GTIMx_IER_TERRIE_Pos (23UL) /*!< TERRIE (Bit 23) */ +#define GTIMx_IER_TERRIE_Msk (0x800000UL) /*!< TERRIE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_IERRIE_Pos (22UL) /*!< IERRIE (Bit 22) */ +#define GTIMx_IER_IERRIE_Msk (0x400000UL) /*!< IERRIE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_DIRIE_Pos (21UL) /*!< DIRIE (Bit 21) */ +#define GTIMx_IER_DIRIE_Msk (0x200000UL) /*!< DIRIE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_IDXIE_Pos (20UL) /*!< IDXIE (Bit 20) */ +#define GTIMx_IER_IDXIE_Msk (0x100000UL) /*!< IDXIE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_TDE_Pos (14UL) /*!< TDE (Bit 14) */ +#define GTIMx_IER_TDE_Msk (0x4000UL) /*!< TDE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC4DE_Pos (12UL) /*!< CC4DE (Bit 12) */ +#define GTIMx_IER_CC4DE_Msk (0x1000UL) /*!< CC4DE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC3DE_Pos (11UL) /*!< CC3DE (Bit 11) */ +#define GTIMx_IER_CC3DE_Msk (0x800UL) /*!< CC3DE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC2DE_Pos (10UL) /*!< CC2DE (Bit 10) */ +#define GTIMx_IER_CC2DE_Msk (0x400UL) /*!< CC2DE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC1DE_Pos (9UL) /*!< CC1DE (Bit 9) */ +#define GTIMx_IER_CC1DE_Msk (0x200UL) /*!< CC1DE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_UDE_Pos (8UL) /*!< UDE (Bit 8) */ +#define GTIMx_IER_UDE_Msk (0x100UL) /*!< UDE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_TIE_Pos (6UL) /*!< TIE (Bit 6) */ +#define GTIMx_IER_TIE_Msk (0x40UL) /*!< TIE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC4IE_Pos (4UL) /*!< CC4IE (Bit 4) */ +#define GTIMx_IER_CC4IE_Msk (0x10UL) /*!< CC4IE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC3IE_Pos (3UL) /*!< CC3IE (Bit 3) */ +#define GTIMx_IER_CC3IE_Msk (0x8UL) /*!< CC3IE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC2IE_Pos (2UL) /*!< CC2IE (Bit 2) */ +#define GTIMx_IER_CC2IE_Msk (0x4UL) /*!< CC2IE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC1IE_Pos (1UL) /*!< CC1IE (Bit 1) */ +#define GTIMx_IER_CC1IE_Msk (0x2UL) /*!< CC1IE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_UIE_Pos (0UL) /*!< UIE (Bit 0) */ +#define GTIMx_IER_UIE_Msk (0x1UL) /*!< UIE (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define GTIMx_ISR_TERRF_Pos (23UL) /*!< TERRF (Bit 23) */ +#define GTIMx_ISR_TERRF_Msk (0x800000UL) /*!< TERRF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_IERRF_Pos (22UL) /*!< IERRF (Bit 22) */ +#define GTIMx_ISR_IERRF_Msk (0x400000UL) /*!< IERRF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_DIRF_Pos (21UL) /*!< DIRF (Bit 21) */ +#define GTIMx_ISR_DIRF_Msk (0x200000UL) /*!< DIRF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_IDXF_Pos (20UL) /*!< IDXF (Bit 20) */ +#define GTIMx_ISR_IDXF_Msk (0x100000UL) /*!< IDXF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC4OF_Pos (12UL) /*!< CC4OF (Bit 12) */ +#define GTIMx_ISR_CC4OF_Msk (0x1000UL) /*!< CC4OF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC3OF_Pos (11UL) /*!< CC3OF (Bit 11) */ +#define GTIMx_ISR_CC3OF_Msk (0x800UL) /*!< CC3OF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC2OF_Pos (10UL) /*!< CC2OF (Bit 10) */ +#define GTIMx_ISR_CC2OF_Msk (0x400UL) /*!< CC2OF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC1OF_Pos (9UL) /*!< CC1OF (Bit 9) */ +#define GTIMx_ISR_CC1OF_Msk (0x200UL) /*!< CC1OF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_TIF_Pos (6UL) /*!< TIF (Bit 6) */ +#define GTIMx_ISR_TIF_Msk (0x40UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC4IF_Pos (4UL) /*!< CC4IF (Bit 4) */ +#define GTIMx_ISR_CC4IF_Msk (0x10UL) /*!< CC4IF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC3IF_Pos (3UL) /*!< CC3IF (Bit 3) */ +#define GTIMx_ISR_CC3IF_Msk (0x8UL) /*!< CC3IF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC2IF_Pos (2UL) /*!< CC2IF (Bit 2) */ +#define GTIMx_ISR_CC2IF_Msk (0x4UL) /*!< CC2IF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC1IF_Pos (1UL) /*!< CC1IF (Bit 1) */ +#define GTIMx_ISR_CC1IF_Msk (0x2UL) /*!< CC1IF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_UIF_Pos (0UL) /*!< UIF (Bit 0) */ +#define GTIMx_ISR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define GTIMx_ICR_TERRF_Pos (23UL) /*!< TERRF (Bit 23) */ +#define GTIMx_ICR_TERRF_Msk (0x800000UL) /*!< TERRF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_IERRF_Pos (22UL) /*!< IERRF (Bit 22) */ +#define GTIMx_ICR_IERRF_Msk (0x400000UL) /*!< IERRF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_DIRF_Pos (21UL) /*!< DIRF (Bit 21) */ +#define GTIMx_ICR_DIRF_Msk (0x200000UL) /*!< DIRF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_IDXF_Pos (20UL) /*!< IDXF (Bit 20) */ +#define GTIMx_ICR_IDXF_Msk (0x100000UL) /*!< IDXF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC4OF_Pos (12UL) /*!< CC4OF (Bit 12) */ +#define GTIMx_ICR_CC4OF_Msk (0x1000UL) /*!< CC4OF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC3OF_Pos (11UL) /*!< CC3OF (Bit 11) */ +#define GTIMx_ICR_CC3OF_Msk (0x800UL) /*!< CC3OF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC2OF_Pos (10UL) /*!< CC2OF (Bit 10) */ +#define GTIMx_ICR_CC2OF_Msk (0x400UL) /*!< CC2OF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC1OF_Pos (9UL) /*!< CC1OF (Bit 9) */ +#define GTIMx_ICR_CC1OF_Msk (0x200UL) /*!< CC1OF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_TIF_Pos (6UL) /*!< TIF (Bit 6) */ +#define GTIMx_ICR_TIF_Msk (0x40UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC4IF_Pos (4UL) /*!< CC4IF (Bit 4) */ +#define GTIMx_ICR_CC4IF_Msk (0x10UL) /*!< CC4IF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC3IF_Pos (3UL) /*!< CC3IF (Bit 3) */ +#define GTIMx_ICR_CC3IF_Msk (0x8UL) /*!< CC3IF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC2IF_Pos (2UL) /*!< CC2IF (Bit 2) */ +#define GTIMx_ICR_CC2IF_Msk (0x4UL) /*!< CC2IF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC1IF_Pos (1UL) /*!< CC1IF (Bit 1) */ +#define GTIMx_ICR_CC1IF_Msk (0x2UL) /*!< CC1IF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_UIF_Pos (0UL) /*!< UIF (Bit 0) */ +#define GTIMx_ICR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */ +/* ========================================================== EGR ========================================================== */ +#define GTIMx_EGR_TG_Pos (6UL) /*!< TG (Bit 6) */ +#define GTIMx_EGR_TG_Msk (0x40UL) /*!< TG (Bitfield-Mask: 0x01) */ +#define GTIMx_EGR_CC4G_Pos (4UL) /*!< CC4G (Bit 4) */ +#define GTIMx_EGR_CC4G_Msk (0x10UL) /*!< CC4G (Bitfield-Mask: 0x01) */ +#define GTIMx_EGR_CC3G_Pos (3UL) /*!< CC3G (Bit 3) */ +#define GTIMx_EGR_CC3G_Msk (0x8UL) /*!< CC3G (Bitfield-Mask: 0x01) */ +#define GTIMx_EGR_CC2G_Pos (2UL) /*!< CC2G (Bit 2) */ +#define GTIMx_EGR_CC2G_Msk (0x4UL) /*!< CC2G (Bitfield-Mask: 0x01) */ +#define GTIMx_EGR_CC1G_Pos (1UL) /*!< CC1G (Bit 1) */ +#define GTIMx_EGR_CC1G_Msk (0x2UL) /*!< CC1G (Bitfield-Mask: 0x01) */ +#define GTIMx_EGR_UG_Pos (0UL) /*!< UG (Bit 0) */ +#define GTIMx_EGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */ +/* ======================================================= CCMR1CAP ======================================================== */ +#define GTIMx_CCMR1CAP_IC2F_Pos (12UL) /*!< IC2F (Bit 12) */ +#define GTIMx_CCMR1CAP_IC2F_Msk (0xf000UL) /*!< IC2F (Bitfield-Mask: 0x0f) */ +#define GTIMx_CCMR1CAP_IC2PSC_Pos (10UL) /*!< IC2PSC (Bit 10) */ +#define GTIMx_CCMR1CAP_IC2PSC_Msk (0xc00UL) /*!< IC2PSC (Bitfield-Mask: 0x03) */ +#define GTIMx_CCMR1CAP_CC2S_Pos (8UL) /*!< CC2S (Bit 8) */ +#define GTIMx_CCMR1CAP_CC2S_Msk (0x300UL) /*!< CC2S (Bitfield-Mask: 0x03) */ +#define GTIMx_CCMR1CAP_IC1F_Pos (4UL) /*!< IC1F (Bit 4) */ +#define GTIMx_CCMR1CAP_IC1F_Msk (0xf0UL) /*!< IC1F (Bitfield-Mask: 0x0f) */ +#define GTIMx_CCMR1CAP_IC1PSC_Pos (2UL) /*!< IC1PSC (Bit 2) */ +#define GTIMx_CCMR1CAP_IC1PSC_Msk (0xcUL) /*!< IC1PSC (Bitfield-Mask: 0x03) */ +#define GTIMx_CCMR1CAP_CC1S_Pos (0UL) /*!< CC1S (Bit 0) */ +#define GTIMx_CCMR1CAP_CC1S_Msk (0x3UL) /*!< CC1S (Bitfield-Mask: 0x03) */ +/* ======================================================= CCMR1CMP ======================================================== */ +#define GTIMx_CCMR1CMP_OC2MH_Pos (24UL) /*!< OC2MH (Bit 24) */ +#define GTIMx_CCMR1CMP_OC2MH_Msk (0x1000000UL) /*!< OC2MH (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR1CMP_OC1MH_Pos (16UL) /*!< OC1MH (Bit 16) */ +#define GTIMx_CCMR1CMP_OC1MH_Msk (0x10000UL) /*!< OC1MH (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR1CMP_OC2CE_Pos (15UL) /*!< OC2CE (Bit 15) */ +#define GTIMx_CCMR1CMP_OC2CE_Msk (0x8000UL) /*!< OC2CE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR1CMP_OC2M_Pos (12UL) /*!< OC2M (Bit 12) */ +#define GTIMx_CCMR1CMP_OC2M_Msk (0x7000UL) /*!< OC2M (Bitfield-Mask: 0x07) */ +#define GTIMx_CCMR1CMP_OC2PE_Pos (11UL) /*!< OC2PE (Bit 11) */ +#define GTIMx_CCMR1CMP_OC2PE_Msk (0x800UL) /*!< OC2PE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR1CMP_OC2FE_Pos (10UL) /*!< OC2FE (Bit 10) */ +#define GTIMx_CCMR1CMP_OC2FE_Msk (0x400UL) /*!< OC2FE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR1CMP_CC2S_Pos (8UL) /*!< CC2S (Bit 8) */ +#define GTIMx_CCMR1CMP_CC2S_Msk (0x300UL) /*!< CC2S (Bitfield-Mask: 0x03) */ +#define GTIMx_CCMR1CMP_OC1CE_Pos (7UL) /*!< OC1CE (Bit 7) */ +#define GTIMx_CCMR1CMP_OC1CE_Msk (0x80UL) /*!< OC1CE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR1CMP_OC1M_Pos (4UL) /*!< OC1M (Bit 4) */ +#define GTIMx_CCMR1CMP_OC1M_Msk (0x70UL) /*!< OC1M (Bitfield-Mask: 0x07) */ +#define GTIMx_CCMR1CMP_OC1PE_Pos (3UL) /*!< OC1PE (Bit 3) */ +#define GTIMx_CCMR1CMP_OC1PE_Msk (0x8UL) /*!< OC1PE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR1CMP_OC1FE_Pos (2UL) /*!< OC1FE (Bit 2) */ +#define GTIMx_CCMR1CMP_OC1FE_Msk (0x4UL) /*!< OC1FE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR1CMP_CC1S_Pos (0UL) /*!< CC1S (Bit 0) */ +#define GTIMx_CCMR1CMP_CC1S_Msk (0x3UL) /*!< CC1S (Bitfield-Mask: 0x03) */ +/* ======================================================= CCMR2CAP ======================================================== */ +#define GTIMx_CCMR2CAP_IC4F_Pos (12UL) /*!< IC4F (Bit 12) */ +#define GTIMx_CCMR2CAP_IC4F_Msk (0xf000UL) /*!< IC4F (Bitfield-Mask: 0x0f) */ +#define GTIMx_CCMR2CAP_IC4PSC_Pos (10UL) /*!< IC4PSC (Bit 10) */ +#define GTIMx_CCMR2CAP_IC4PSC_Msk (0xc00UL) /*!< IC4PSC (Bitfield-Mask: 0x03) */ +#define GTIMx_CCMR2CAP_CC4S_Pos (8UL) /*!< CC4S (Bit 8) */ +#define GTIMx_CCMR2CAP_CC4S_Msk (0x300UL) /*!< CC4S (Bitfield-Mask: 0x03) */ +#define GTIMx_CCMR2CAP_IC3F_Pos (4UL) /*!< IC3F (Bit 4) */ +#define GTIMx_CCMR2CAP_IC3F_Msk (0xf0UL) /*!< IC3F (Bitfield-Mask: 0x0f) */ +#define GTIMx_CCMR2CAP_IC3PSC_Pos (2UL) /*!< IC3PSC (Bit 2) */ +#define GTIMx_CCMR2CAP_IC3PSC_Msk (0xcUL) /*!< IC3PSC (Bitfield-Mask: 0x03) */ +#define GTIMx_CCMR2CAP_CC3S_Pos (0UL) /*!< CC3S (Bit 0) */ +#define GTIMx_CCMR2CAP_CC3S_Msk (0x3UL) /*!< CC3S (Bitfield-Mask: 0x03) */ +/* ======================================================= CCMR2CMP ======================================================== */ +#define GTIMx_CCMR2CMP_OC4MH_Pos (24UL) /*!< OC4MH (Bit 24) */ +#define GTIMx_CCMR2CMP_OC4MH_Msk (0x1000000UL) /*!< OC4MH (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR2CMP_OC3MH_Pos (16UL) /*!< OC3MH (Bit 16) */ +#define GTIMx_CCMR2CMP_OC3MH_Msk (0x10000UL) /*!< OC3MH (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR2CMP_OC4CE_Pos (15UL) /*!< OC4CE (Bit 15) */ +#define GTIMx_CCMR2CMP_OC4CE_Msk (0x8000UL) /*!< OC4CE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR2CMP_OC4M_Pos (12UL) /*!< OC4M (Bit 12) */ +#define GTIMx_CCMR2CMP_OC4M_Msk (0x7000UL) /*!< OC4M (Bitfield-Mask: 0x07) */ +#define GTIMx_CCMR2CMP_OC4PE_Pos (11UL) /*!< OC4PE (Bit 11) */ +#define GTIMx_CCMR2CMP_OC4PE_Msk (0x800UL) /*!< OC4PE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR2CMP_OC4FE_Pos (10UL) /*!< OC4FE (Bit 10) */ +#define GTIMx_CCMR2CMP_OC4FE_Msk (0x400UL) /*!< OC4FE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR2CMP_CC4S_Pos (8UL) /*!< CC4S (Bit 8) */ +#define GTIMx_CCMR2CMP_CC4S_Msk (0x300UL) /*!< CC4S (Bitfield-Mask: 0x03) */ +#define GTIMx_CCMR2CMP_OC3CE_Pos (7UL) /*!< OC3CE (Bit 7) */ +#define GTIMx_CCMR2CMP_OC3CE_Msk (0x80UL) /*!< OC3CE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR2CMP_OC3M_Pos (4UL) /*!< OC3M (Bit 4) */ +#define GTIMx_CCMR2CMP_OC3M_Msk (0x70UL) /*!< OC3M (Bitfield-Mask: 0x07) */ +#define GTIMx_CCMR2CMP_OC3PE_Pos (3UL) /*!< OC3PE (Bit 3) */ +#define GTIMx_CCMR2CMP_OC3PE_Msk (0x8UL) /*!< OC3PE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR2CMP_OC3FE_Pos (2UL) /*!< OC3FE (Bit 2) */ +#define GTIMx_CCMR2CMP_OC3FE_Msk (0x4UL) /*!< OC3FE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR2CMP_CC3S_Pos (0UL) /*!< CC3S (Bit 0) */ +#define GTIMx_CCMR2CMP_CC3S_Msk (0x3UL) /*!< CC3S (Bitfield-Mask: 0x03) */ +/* ========================================================= CCER ========================================================== */ +#define GTIMx_CCER_CC4NP_Pos (15UL) /*!< CC4NP (Bit 15) */ +#define GTIMx_CCER_CC4NP_Msk (0x8000UL) /*!< CC4NP (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC4P_Pos (13UL) /*!< CC4P (Bit 13) */ +#define GTIMx_CCER_CC4P_Msk (0x2000UL) /*!< CC4P (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC4E_Pos (12UL) /*!< CC4E (Bit 12) */ +#define GTIMx_CCER_CC4E_Msk (0x1000UL) /*!< CC4E (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC3NP_Pos (11UL) /*!< CC3NP (Bit 11) */ +#define GTIMx_CCER_CC3NP_Msk (0x800UL) /*!< CC3NP (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC3P_Pos (9UL) /*!< CC3P (Bit 9) */ +#define GTIMx_CCER_CC3P_Msk (0x200UL) /*!< CC3P (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC3E_Pos (8UL) /*!< CC3E (Bit 8) */ +#define GTIMx_CCER_CC3E_Msk (0x100UL) /*!< CC3E (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC2NP_Pos (7UL) /*!< CC2NP (Bit 7) */ +#define GTIMx_CCER_CC2NP_Msk (0x80UL) /*!< CC2NP (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC2P_Pos (5UL) /*!< CC2P (Bit 5) */ +#define GTIMx_CCER_CC2P_Msk (0x20UL) /*!< CC2P (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC2E_Pos (4UL) /*!< CC2E (Bit 4) */ +#define GTIMx_CCER_CC2E_Msk (0x10UL) /*!< CC2E (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC1NP_Pos (3UL) /*!< CC1NP (Bit 3) */ +#define GTIMx_CCER_CC1NP_Msk (0x8UL) /*!< CC1NP (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC1P_Pos (1UL) /*!< CC1P (Bit 1) */ +#define GTIMx_CCER_CC1P_Msk (0x2UL) /*!< CC1P (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC1E_Pos (0UL) /*!< CC1E (Bit 0) */ +#define GTIMx_CCER_CC1E_Msk (0x1UL) /*!< CC1E (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +#define GTIMx_CNT_UIFCPY_Pos (31UL) /*!< UIFCPY (Bit 31) */ +#define GTIMx_CNT_UIFCPY_Msk (0x80000000UL) /*!< UIFCPY (Bitfield-Mask: 0x01) */ +#define GTIMx_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define GTIMx_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== PSC ========================================================== */ +#define GTIMx_PSC_PSC_Pos (0UL) /*!< PSC (Bit 0) */ +#define GTIMx_PSC_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */ +/* ========================================================== ARR ========================================================== */ +#define GTIMx_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define GTIMx_ARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR1 ========================================================== */ +#define GTIMx_CCR1_CCR1_Pos (0UL) /*!< CCR1 (Bit 0) */ +#define GTIMx_CCR1_CCR1_Msk (0xffffUL) /*!< CCR1 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR2 ========================================================== */ +#define GTIMx_CCR2_CCR2_Pos (0UL) /*!< CCR2 (Bit 0) */ +#define GTIMx_CCR2_CCR2_Msk (0xffffUL) /*!< CCR2 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR3 ========================================================== */ +#define GTIMx_CCR3_CCR3_Pos (0UL) /*!< CCR3 (Bit 0) */ +#define GTIMx_CCR3_CCR3_Msk (0xffffUL) /*!< CCR3 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR4 ========================================================== */ +#define GTIMx_CCR4_CCR4_Pos (0UL) /*!< CCR4 (Bit 0) */ +#define GTIMx_CCR4_CCR4_Msk (0xffffUL) /*!< CCR4 (Bitfield-Mask: 0xffff) */ +/* ========================================================== ECR ========================================================== */ +#define GTIMx_ECR_IPOS_Pos (6UL) /*!< IPOS (Bit 6) */ +#define GTIMx_ECR_IPOS_Msk (0xc0UL) /*!< IPOS (Bitfield-Mask: 0x03) */ +#define GTIMx_ECR_FIDX_Pos (5UL) /*!< FIDX (Bit 5) */ +#define GTIMx_ECR_FIDX_Msk (0x20UL) /*!< FIDX (Bitfield-Mask: 0x01) */ +#define GTIMx_ECR_IDIR_Pos (1UL) /*!< IDIR (Bit 1) */ +#define GTIMx_ECR_IDIR_Msk (0x6UL) /*!< IDIR (Bitfield-Mask: 0x03) */ +#define GTIMx_ECR_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define GTIMx_ECR_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ========================================================= TISEL ========================================================= */ +#define GTIMx_TISEL_TI4SEL_Pos (24UL) /*!< TI4SEL (Bit 24) */ +#define GTIMx_TISEL_TI4SEL_Msk (0xf000000UL) /*!< TI4SEL (Bitfield-Mask: 0x0f) */ +#define GTIMx_TISEL_TI3SEL_Pos (16UL) /*!< TI3SEL (Bit 16) */ +#define GTIMx_TISEL_TI3SEL_Msk (0xf0000UL) /*!< TI3SEL (Bitfield-Mask: 0x0f) */ +#define GTIMx_TISEL_TI2SEL_Pos (8UL) /*!< TI2SEL (Bit 8) */ +#define GTIMx_TISEL_TI2SEL_Msk (0xf00UL) /*!< TI2SEL (Bitfield-Mask: 0x0f) */ +#define GTIMx_TISEL_TI1SEL_Pos (0UL) /*!< TI1SEL (Bit 0) */ +#define GTIMx_TISEL_TI1SEL_Msk (0xfUL) /*!< TI1SEL (Bitfield-Mask: 0x0f) */ +/* ========================================================== AF1 ========================================================== */ +#define GTIMx_AF1_ETRSEL_Pos (14UL) /*!< ETRSEL (Bit 14) */ +#define GTIMx_AF1_ETRSEL_Msk (0x3c000UL) /*!< ETRSEL (Bitfield-Mask: 0x0f) */ +/* ========================================================== AF2 ========================================================== */ +#define GTIMx_AF2_OCRSEL_Pos (16UL) /*!< OCRSEL (Bit 16) */ +#define GTIMx_AF2_OCRSEL_Msk (0x70000UL) /*!< OCRSEL (Bitfield-Mask: 0x07) */ + + +/* =========================================================================================================================== */ +/* ================ HALLTIM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define HALLTIM_CR_SOFTCAP_Pos (23UL) /*!< SOFTCAP (Bit 23) */ +#define HALLTIM_CR_SOFTCAP_Msk (0x800000UL) /*!< SOFTCAP (Bitfield-Mask: 0x01) */ +#define HALLTIM_CR_FLT2LEN_Pos (8UL) /*!< FLT2LEN (Bit 8) */ +#define HALLTIM_CR_FLT2LEN_Msk (0x7fff00UL) /*!< FLT2LEN (Bitfield-Mask: 0x7fff) */ +#define HALLTIM_CR_MMS_Pos (4UL) /*!< MMS (Bit 4) */ +#define HALLTIM_CR_MMS_Msk (0x70UL) /*!< MMS (Bitfield-Mask: 0x07) */ +#define HALLTIM_CR_DIV_Pos (2UL) /*!< DIV (Bit 2) */ +#define HALLTIM_CR_DIV_Msk (0xcUL) /*!< DIV (Bitfield-Mask: 0x03) */ +#define HALLTIM_CR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */ +#define HALLTIM_CR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */ +#define HALLTIM_CR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define HALLTIM_CR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= DIER ========================================================== */ +#define HALLTIM_DIER_SOFTDMA_Pos (7UL) /*!< SOFTDMA (Bit 7) */ +#define HALLTIM_DIER_SOFTDMA_Msk (0x80UL) /*!< SOFTDMA (Bitfield-Mask: 0x01) */ +#define HALLTIM_DIER_MATCHDMA_Pos (6UL) /*!< MATCHDMA (Bit 6) */ +#define HALLTIM_DIER_MATCHDMA_Msk (0x40UL) /*!< MATCHDMA (Bitfield-Mask: 0x01) */ +#define HALLTIM_DIER_OVDMA_Pos (5UL) /*!< OVDMA (Bit 5) */ +#define HALLTIM_DIER_OVDMA_Msk (0x20UL) /*!< OVDMA (Bitfield-Mask: 0x01) */ +#define HALLTIM_DIER_CAPDMA_Pos (4UL) /*!< CAPDMA (Bit 4) */ +#define HALLTIM_DIER_CAPDMA_Msk (0x10UL) /*!< CAPDMA (Bitfield-Mask: 0x01) */ +#define HALLTIM_DIER_MATCHIE_Pos (2UL) /*!< MATCHIE (Bit 2) */ +#define HALLTIM_DIER_MATCHIE_Msk (0x4UL) /*!< MATCHIE (Bitfield-Mask: 0x01) */ +#define HALLTIM_DIER_OVIE_Pos (1UL) /*!< OVIE (Bit 1) */ +#define HALLTIM_DIER_OVIE_Msk (0x2UL) /*!< OVIE (Bitfield-Mask: 0x01) */ +#define HALLTIM_DIER_CAPIE_Pos (0UL) /*!< CAPIE (Bit 0) */ +#define HALLTIM_DIER_CAPIE_Msk (0x1UL) /*!< CAPIE (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +#define HALLTIM_CNT_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define HALLTIM_CNT_DATA_Msk (0xffffffUL) /*!< DATA (Bitfield-Mask: 0xffffff) */ +/* ========================================================== ARR ========================================================== */ +#define HALLTIM_ARR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define HALLTIM_ARR_DATA_Msk (0xffffffUL) /*!< DATA (Bitfield-Mask: 0xffffff) */ +/* ========================================================= WIDTH ========================================================= */ +#define HALLTIM_WIDTH_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define HALLTIM_WIDTH_DATA_Msk (0xffffffUL) /*!< DATA (Bitfield-Mask: 0xffffff) */ +/* ========================================================== CCR ========================================================== */ +#define HALLTIM_CCR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define HALLTIM_CCR_DATA_Msk (0xffffffUL) /*!< DATA (Bitfield-Mask: 0xffffff) */ +/* ========================================================== ISR ========================================================== */ +#define HALLTIM_ISR_MATCH_Pos (2UL) /*!< MATCH (Bit 2) */ +#define HALLTIM_ISR_MATCH_Msk (0x4UL) /*!< MATCH (Bitfield-Mask: 0x01) */ +#define HALLTIM_ISR_OV_Pos (1UL) /*!< OV (Bit 1) */ +#define HALLTIM_ISR_OV_Msk (0x2UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define HALLTIM_ISR_CAPF_Pos (0UL) /*!< CAPF (Bit 0) */ +#define HALLTIM_ISR_CAPF_Msk (0x1UL) /*!< CAPF (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define HALLTIM_ICR_MATCHF_Pos (2UL) /*!< MATCHF (Bit 2) */ +#define HALLTIM_ICR_MATCHF_Msk (0x4UL) /*!< MATCHF (Bitfield-Mask: 0x01) */ +#define HALLTIM_ICR_OVF_Pos (1UL) /*!< OVF (Bit 1) */ +#define HALLTIM_ICR_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define HALLTIM_ICR_CAPF_Pos (0UL) /*!< CAPF (Bit 0) */ +#define HALLTIM_ICR_CAPF_Msk (0x1UL) /*!< CAPF (Bitfield-Mask: 0x01) */ +/* ========================================================= STATE ========================================================= */ +#define HALLTIM_STATE_CH3S_Pos (6UL) /*!< CH3S (Bit 6) */ +#define HALLTIM_STATE_CH3S_Msk (0x40UL) /*!< CH3S (Bitfield-Mask: 0x01) */ +#define HALLTIM_STATE_CH2S_Pos (5UL) /*!< CH2S (Bit 5) */ +#define HALLTIM_STATE_CH2S_Msk (0x20UL) /*!< CH2S (Bitfield-Mask: 0x01) */ +#define HALLTIM_STATE_CH1S_Pos (4UL) /*!< CH1S (Bit 4) */ +#define HALLTIM_STATE_CH1S_Msk (0x10UL) /*!< CH1S (Bitfield-Mask: 0x01) */ +#define HALLTIM_STATE_CH3F_Pos (2UL) /*!< CH3F (Bit 2) */ +#define HALLTIM_STATE_CH3F_Msk (0x4UL) /*!< CH3F (Bitfield-Mask: 0x01) */ +#define HALLTIM_STATE_CH2F_Pos (1UL) /*!< CH2F (Bit 1) */ +#define HALLTIM_STATE_CH2F_Msk (0x2UL) /*!< CH2F (Bitfield-Mask: 0x01) */ +#define HALLTIM_STATE_CH1F_Pos (0UL) /*!< CH1F (Bit 0) */ +#define HALLTIM_STATE_CH1F_Msk (0x1UL) /*!< CH1F (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ I2C ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= INSEL ========================================================= */ +#define I2Cx_INSEL_SDAINSEL_Pos (3UL) /*!< SDAINSEL (Bit 3) */ +#define I2Cx_INSEL_SDAINSEL_Msk (0x38UL) /*!< SDAINSEL (Bitfield-Mask: 0x07) */ +#define I2Cx_INSEL_SCLINSEL_Pos (0UL) /*!< SCLINSEL (Bit 0) */ +#define I2Cx_INSEL_SCLINSEL_Msk (0x7UL) /*!< SCLINSEL (Bitfield-Mask: 0x07) */ +/* ========================================================= MCR0 ========================================================== */ +#define I2Cx_MCR0_RXFIFORST_Pos (9UL) /*!< RXFIFORST (Bit 9) */ +#define I2Cx_MCR0_RXFIFORST_Msk (0x200UL) /*!< RXFIFORST (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR0_TXFIFORST_Pos (8UL) /*!< TXFIFORST (Bit 8) */ +#define I2Cx_MCR0_TXFIFORST_Msk (0x100UL) /*!< TXFIFORST (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR0_CLKSRC_Pos (6UL) /*!< CLKSRC (Bit 6) */ +#define I2Cx_MCR0_CLKSRC_Msk (0xc0UL) /*!< CLKSRC (Bitfield-Mask: 0x03) */ +#define I2Cx_MCR0_DBGEN_Pos (3UL) /*!< DBGEN (Bit 3) */ +#define I2Cx_MCR0_DBGEN_Msk (0x8UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR0_SLEEPEN_Pos (2UL) /*!< SLEEPEN (Bit 2) */ +#define I2Cx_MCR0_SLEEPEN_Msk (0x4UL) /*!< SLEEPEN (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR0_RESET_Pos (1UL) /*!< RESET (Bit 1) */ +#define I2Cx_MCR0_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR0_MEN_Pos (0UL) /*!< MEN (Bit 0) */ +#define I2Cx_MCR0_MEN_Msk (0x1UL) /*!< MEN (Bitfield-Mask: 0x01) */ +/* ========================================================= MCR1 ========================================================== */ +#define I2Cx_MCR1_RDMO_Pos (9UL) /*!< RDMO (Bit 9) */ +#define I2Cx_MCR1_RDMO_Msk (0x200UL) /*!< RDMO (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR1_CIRFIFO_Pos (8UL) /*!< CIRFIFO (Bit 8) */ +#define I2Cx_MCR1_CIRFIFO_Msk (0x100UL) /*!< CIRFIFO (Bitfield-Mask: 0x01) */ +/* ========================================================= MCR2 ========================================================== */ +#define I2Cx_MCR2_PINCFG_Pos (24UL) /*!< PINCFG (Bit 24) */ +#define I2Cx_MCR2_PINCFG_Msk (0x7000000UL) /*!< PINCFG (Bitfield-Mask: 0x07) */ +#define I2Cx_MCR2_MATCFG_Pos (16UL) /*!< MATCFG (Bit 16) */ +#define I2Cx_MCR2_MATCFG_Msk (0x70000UL) /*!< MATCFG (Bitfield-Mask: 0x07) */ +#define I2Cx_MCR2_TRGSEL_Pos (15UL) /*!< TRGSEL (Bit 15) */ +#define I2Cx_MCR2_TRGSEL_Msk (0x8000UL) /*!< TRGSEL (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR2_TIMECFG_Pos (10UL) /*!< TIMECFG (Bit 10) */ +#define I2Cx_MCR2_TIMECFG_Msk (0x400UL) /*!< TIMECFG (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR2_IGNACK_Pos (9UL) /*!< IGNACK (Bit 9) */ +#define I2Cx_MCR2_IGNACK_Msk (0x200UL) /*!< IGNACK (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR2_AUTOSTOP_Pos (8UL) /*!< AUTOSTOP (Bit 8) */ +#define I2Cx_MCR2_AUTOSTOP_Msk (0x100UL) /*!< AUTOSTOP (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR2_PRESCALE_Pos (0UL) /*!< PRESCALE (Bit 0) */ +#define I2Cx_MCR2_PRESCALE_Msk (0x7UL) /*!< PRESCALE (Bitfield-Mask: 0x07) */ +/* ========================================================= MCR3 ========================================================== */ +#define I2Cx_MCR3_FLTSDA_Pos (24UL) /*!< FLTSDA (Bit 24) */ +#define I2Cx_MCR3_FLTSDA_Msk (0xf000000UL) /*!< FLTSDA (Bitfield-Mask: 0x0f) */ +#define I2Cx_MCR3_FLTSCL_Pos (16UL) /*!< FLTSCL (Bit 16) */ +#define I2Cx_MCR3_FLTSCL_Msk (0xf0000UL) /*!< FLTSCL (Bitfield-Mask: 0x0f) */ +#define I2Cx_MCR3_BUSIDLE_Pos (0UL) /*!< BUSIDLE (Bit 0) */ +#define I2Cx_MCR3_BUSIDLE_Msk (0xfffUL) /*!< BUSIDLE (Bitfield-Mask: 0xfff) */ +/* ========================================================= MCR4 ========================================================== */ +#define I2Cx_MCR4_PINLOW_Pos (8UL) /*!< PINLOW (Bit 8) */ +#define I2Cx_MCR4_PINLOW_Msk (0xfff00UL) /*!< PINLOW (Bitfield-Mask: 0xfff) */ +/* ========================================================= MCCR ========================================================= */ +#define I2Cx_MCCR_DATAVD_Pos (24UL) /*!< DATAVD (Bit 24) */ +#define I2Cx_MCCR_DATAVD_Msk (0x3f000000UL) /*!< DATAVD (Bitfield-Mask: 0x3f) */ +#define I2Cx_MCCR_SETHOLD_Pos (16UL) /*!< SETHOLD (Bit 16) */ +#define I2Cx_MCCR_SETHOLD_Msk (0x3f0000UL) /*!< SETHOLD (Bitfield-Mask: 0x3f) */ +#define I2Cx_MCCR_CLKHI_Pos (8UL) /*!< CLKHI (Bit 8) */ +#define I2Cx_MCCR_CLKHI_Msk (0x3f00UL) /*!< CLKHI (Bitfield-Mask: 0x3f) */ +#define I2Cx_MCCR_CLKLO_Pos (0UL) /*!< CLKLO (Bit 0) */ +#define I2Cx_MCCR_CLKLO_Msk (0x3fUL) /*!< CLKLO (Bitfield-Mask: 0x3f) */ +/* ======================================================== MMATCH ========================================================= */ +#define I2Cx_MMATCH_MATCH1_Pos (16UL) /*!< MATCH1 (Bit 16) */ +#define I2Cx_MMATCH_MATCH1_Msk (0xff0000UL) /*!< MATCH1 (Bitfield-Mask: 0xff) */ +#define I2Cx_MMATCH_MATCH0_Pos (0UL) /*!< MATCH0 (Bit 0) */ +#define I2Cx_MMATCH_MATCH0_Msk (0xffUL) /*!< MATCH0 (Bitfield-Mask: 0xff) */ +/* ======================================================== MFIFOCR ======================================================== */ +#define I2Cx_MFIFOCR_RXWATER_Pos (16UL) /*!< RXWATER (Bit 16) */ +#define I2Cx_MFIFOCR_RXWATER_Msk (0x10000UL) /*!< RXWATER (Bitfield-Mask: 0x01) */ +#define I2Cx_MFIFOCR_TXWATER_Pos (0UL) /*!< TXWATER (Bit 0) */ +#define I2Cx_MFIFOCR_TXWATER_Msk (0x1UL) /*!< TXWATER (Bitfield-Mask: 0x01) */ +/* ======================================================== MFIFOSR ======================================================== */ +#define I2Cx_MFIFOSR_RXCNT_Pos (16UL) /*!< RXCNT (Bit 16) */ +#define I2Cx_MFIFOSR_RXCNT_Msk (0x10000UL) /*!< RXCNT (Bitfield-Mask: 0x01) */ +#define I2Cx_MFIFOSR_TXCNT_Pos (0UL) /*!< TXCNT (Bit 0) */ +#define I2Cx_MFIFOSR_TXCNT_Msk (0x1UL) /*!< TXCNT (Bitfield-Mask: 0x01) */ +/* ========================================================= MTDR ========================================================== */ +#define I2Cx_MTDR_CMD_Pos (8UL) /*!< CMD (Bit 8) */ +#define I2Cx_MTDR_CMD_Msk (0x700UL) /*!< CMD (Bitfield-Mask: 0x07) */ +#define I2Cx_MTDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define I2Cx_MTDR_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================= MRDR ========================================================== */ +#define I2Cx_MRDR_EMPTY_Pos (14UL) /*!< EMPTY (Bit 14) */ +#define I2Cx_MRDR_EMPTY_Msk (0x4000UL) /*!< EMPTY (Bitfield-Mask: 0x01) */ +#define I2Cx_MRDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define I2Cx_MRDR_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================= MDER ========================================================== */ +#define I2Cx_MDER_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define I2Cx_MDER_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define I2Cx_MDER_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define I2Cx_MDER_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ +#define I2Cx_MIER_MATCH_Pos (14UL) /*!< MATCH (Bit 14) */ +#define I2Cx_MIER_MATCH_Msk (0x4000UL) /*!< MATCH (Bitfield-Mask: 0x01) */ +#define I2Cx_MIER_PINLOW_Pos (13UL) /*!< PINLOW (Bit 13) */ +#define I2Cx_MIER_PINLOW_Msk (0x2000UL) /*!< PINLOW (Bitfield-Mask: 0x01) */ +#define I2Cx_MIER_FIFO_Pos (12UL) /*!< FIFO (Bit 12) */ +#define I2Cx_MIER_FIFO_Msk (0x1000UL) /*!< FIFO (Bitfield-Mask: 0x01) */ +#define I2Cx_MIER_ARBI_Pos (11UL) /*!< ARBI (Bit 11) */ +#define I2Cx_MIER_ARBI_Msk (0x800UL) /*!< ARBI (Bitfield-Mask: 0x01) */ +#define I2Cx_MIER_NACK_Pos (10UL) /*!< NACK (Bit 10) */ +#define I2Cx_MIER_NACK_Msk (0x400UL) /*!< NACK (Bitfield-Mask: 0x01) */ +#define I2Cx_MIER_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define I2Cx_MIER_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define I2Cx_MIER_PACKET_Pos (8UL) /*!< PACKET (Bit 8) */ +#define I2Cx_MIER_PACKET_Msk (0x100UL) /*!< PACKET (Bitfield-Mask: 0x01) */ +#define I2Cx_MIER_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define I2Cx_MIER_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define I2Cx_MIER_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define I2Cx_MIER_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================= MISR ========================================================== */ +#define I2Cx_MISR_BUSBUSY_Pos (25UL) /*!< BUSBUSY (Bit 25) */ +#define I2Cx_MISR_BUSBUSY_Msk (0x2000000UL) /*!< BUSBUSY (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_MSTBUSY_Pos (24UL) /*!< MSTBUSY (Bit 24) */ +#define I2Cx_MISR_MSTBUSY_Msk (0x1000000UL) /*!< MSTBUSY (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_MATCH_Pos (14UL) /*!< MATCH (Bit 14) */ +#define I2Cx_MISR_MATCH_Msk (0x4000UL) /*!< MATCH (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_PINLOW_Pos (13UL) /*!< PINLOW (Bit 13) */ +#define I2Cx_MISR_PINLOW_Msk (0x2000UL) /*!< PINLOW (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_FIFO_Pos (12UL) /*!< FIFO (Bit 12) */ +#define I2Cx_MISR_FIFO_Msk (0x1000UL) /*!< FIFO (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_ARBI_Pos (11UL) /*!< ARBI (Bit 11) */ +#define I2Cx_MISR_ARBI_Msk (0x800UL) /*!< ARBI (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_NACK_Pos (10UL) /*!< NACK (Bit 10) */ +#define I2Cx_MISR_NACK_Msk (0x400UL) /*!< NACK (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define I2Cx_MISR_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_PACKET_Pos (8UL) /*!< PACKET (Bit 8) */ +#define I2Cx_MISR_PACKET_Msk (0x100UL) /*!< PACKET (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define I2Cx_MISR_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define I2Cx_MISR_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================= MICR ========================================================== */ +#define I2Cx_MICR_MATCH_Pos (14UL) /*!< MATCH (Bit 14) */ +#define I2Cx_MICR_MATCH_Msk (0x4000UL) /*!< MATCH (Bitfield-Mask: 0x01) */ +#define I2Cx_MICR_PINLOW_Pos (13UL) /*!< PINLOW (Bit 13) */ +#define I2Cx_MICR_PINLOW_Msk (0x2000UL) /*!< PINLOW (Bitfield-Mask: 0x01) */ +#define I2Cx_MICR_FIFO_Pos (12UL) /*!< FIFO (Bit 12) */ +#define I2Cx_MICR_FIFO_Msk (0x1000UL) /*!< FIFO (Bitfield-Mask: 0x01) */ +#define I2Cx_MICR_ARBI_Pos (11UL) /*!< ARBI (Bit 11) */ +#define I2Cx_MICR_ARBI_Msk (0x800UL) /*!< ARBI (Bitfield-Mask: 0x01) */ +#define I2Cx_MICR_NACK_Pos (10UL) /*!< NACK (Bit 10) */ +#define I2Cx_MICR_NACK_Msk (0x400UL) /*!< NACK (Bitfield-Mask: 0x01) */ +#define I2Cx_MICR_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define I2Cx_MICR_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define I2Cx_MICR_PACKET_Pos (8UL) /*!< PACKET (Bit 8) */ +#define I2Cx_MICR_PACKET_Msk (0x100UL) /*!< PACKET (Bitfield-Mask: 0x01) */ +/* ========================================================= SCR0 ========================================================== */ +#define I2Cx_SCR0_RXFIFORST_Pos (9UL) /*!< RXFIFORST (Bit 9) */ +#define I2Cx_SCR0_RXFIFORST_Msk (0x200UL) /*!< RXFIFORST (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR0_TXFIFORST_Pos (8UL) /*!< TXFIFORST (Bit 8) */ +#define I2Cx_SCR0_TXFIFORST_Msk (0x100UL) /*!< TXFIFORST (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR0_CLKSRC_Pos (6UL) /*!< CLKSRC (Bit 6) */ +#define I2Cx_SCR0_CLKSRC_Msk (0xc0UL) /*!< CLKSRC (Bitfield-Mask: 0x03) */ +#define I2Cx_SCR0_FLTEN_Pos (4UL) /*!< FLTEN (Bit 4) */ +#define I2Cx_SCR0_FLTEN_Msk (0x10UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR0_RESET_Pos (1UL) /*!< RESET (Bit 1) */ +#define I2Cx_SCR0_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR0_SEN_Pos (0UL) /*!< SEN (Bit 0) */ +#define I2Cx_SCR0_SEN_Msk (0x1UL) /*!< SEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SCR1 ========================================================== */ +#define I2Cx_SCR1_ADDRCFG_Pos (16UL) /*!< ADDRCFG (Bit 16) */ +#define I2Cx_SCR1_ADDRCFG_Msk (0x70000UL) /*!< ADDRCFG (Bitfield-Mask: 0x07) */ +#define I2Cx_SCR1_TRGSEL_Pos (15UL) /*!< TRGSEL (Bit 15) */ +#define I2Cx_SCR1_TRGSEL_Msk (0x8000UL) /*!< TRGSEL (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_IGNACK_Pos (12UL) /*!< IGNACK (Bit 12) */ +#define I2Cx_SCR1_IGNACK_Msk (0x1000UL) /*!< IGNACK (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_RXCFG_Pos (11UL) /*!< RXCFG (Bit 11) */ +#define I2Cx_SCR1_RXCFG_Msk (0x800UL) /*!< RXCFG (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_TXCFG_Pos (10UL) /*!< TXCFG (Bit 10) */ +#define I2Cx_SCR1_TXCFG_Msk (0x400UL) /*!< TXCFG (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_ALERTEN_Pos (9UL) /*!< ALERTEN (Bit 9) */ +#define I2Cx_SCR1_ALERTEN_Msk (0x200UL) /*!< ALERTEN (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_GCEN_Pos (8UL) /*!< GCEN (Bit 8) */ +#define I2Cx_SCR1_GCEN_Msk (0x100UL) /*!< GCEN (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_ACKSTALL_Pos (3UL) /*!< ACKSTALL (Bit 3) */ +#define I2Cx_SCR1_ACKSTALL_Msk (0x8UL) /*!< ACKSTALL (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_TXSTALL_Pos (2UL) /*!< TXSTALL (Bit 2) */ +#define I2Cx_SCR1_TXSTALL_Msk (0x4UL) /*!< TXSTALL (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_RXSTALL_Pos (1UL) /*!< RXSTALL (Bit 1) */ +#define I2Cx_SCR1_RXSTALL_Msk (0x2UL) /*!< RXSTALL (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_ADRSTALL_Pos (0UL) /*!< ADRSTALL (Bit 0) */ +#define I2Cx_SCR1_ADRSTALL_Msk (0x1UL) /*!< ADRSTALL (Bitfield-Mask: 0x01) */ +/* ========================================================= SCR2 ========================================================== */ +#define I2Cx_SCR2_PINCFG_Pos (24UL) /*!< PINCFG (Bit 24) */ +#define I2Cx_SCR2_PINCFG_Msk (0x7000000UL) /*!< PINCFG (Bitfield-Mask: 0x07) */ +/* ========================================================= SCR3 ========================================================== */ +#define I2Cx_SCR3_FLTSDA_Pos (24UL) /*!< FLTSDA (Bit 24) */ +#define I2Cx_SCR3_FLTSDA_Msk (0xf000000UL) /*!< FLTSDA (Bitfield-Mask: 0x0f) */ +#define I2Cx_SCR3_FLTSCL_Pos (16UL) /*!< FLTSCL (Bit 16) */ +#define I2Cx_SCR3_FLTSCL_Msk (0xf0000UL) /*!< FLTSCL (Bitfield-Mask: 0x0f) */ +#define I2Cx_SCR3_DATAVD_Pos (8UL) /*!< DATAVD (Bit 8) */ +#define I2Cx_SCR3_DATAVD_Msk (0x3f00UL) /*!< DATAVD (Bitfield-Mask: 0x3f) */ +#define I2Cx_SCR3_CLKHOLD_Pos (0UL) /*!< CLKHOLD (Bit 0) */ +#define I2Cx_SCR3_CLKHOLD_Msk (0xfUL) /*!< CLKHOLD (Bitfield-Mask: 0x0f) */ +/* ========================================================= SAMR ========================================================== */ +#define I2Cx_SAMR_ADDR1_Pos (17UL) /*!< ADDR1 (Bit 17) */ +#define I2Cx_SAMR_ADDR1_Msk (0x7fe0000UL) /*!< ADDR1 (Bitfield-Mask: 0x3ff) */ +#define I2Cx_SAMR_ADDR0_Pos (1UL) /*!< ADDR0 (Bit 1) */ +#define I2Cx_SAMR_ADDR0_Msk (0x7feUL) /*!< ADDR0 (Bitfield-Mask: 0x3ff) */ +/* ========================================================= STAR ========================================================== */ +#define I2Cx_STAR_TXNACK_Pos (0UL) /*!< TXNACK (Bit 0) */ +#define I2Cx_STAR_TXNACK_Msk (0x1UL) /*!< TXNACK (Bitfield-Mask: 0x01) */ +/* ========================================================= STDR ========================================================== */ +#define I2Cx_STDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define I2Cx_STDR_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================= SRDR ========================================================== */ +#define I2Cx_SRDR_SOF_Pos (15UL) /*!< SOF (Bit 15) */ +#define I2Cx_SRDR_SOF_Msk (0x8000UL) /*!< SOF (Bitfield-Mask: 0x01) */ +#define I2Cx_SRDR_RXEMPTY_Pos (14UL) /*!< RXEMPTY (Bit 14) */ +#define I2Cx_SRDR_RXEMPTY_Msk (0x4000UL) /*!< RXEMPTY (Bitfield-Mask: 0x01) */ +#define I2Cx_SRDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define I2Cx_SRDR_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================= SASR ========================================================== */ +#define I2Cx_SASR_ANV_Pos (14UL) /*!< ANV (Bit 14) */ +#define I2Cx_SASR_ANV_Msk (0x4000UL) /*!< ANV (Bitfield-Mask: 0x01) */ +#define I2Cx_SASR_RADDR_Pos (0UL) /*!< RADDR (Bit 0) */ +#define I2Cx_SASR_RADDR_Msk (0x7ffUL) /*!< RADDR (Bitfield-Mask: 0x7ff) */ +/* ========================================================= SDER ========================================================== */ +#define I2Cx_SDER_ADDR_Pos (2UL) /*!< ADDR (Bit 2) */ +#define I2Cx_SDER_ADDR_Msk (0x4UL) /*!< ADDR (Bitfield-Mask: 0x01) */ +#define I2Cx_SDER_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define I2Cx_SDER_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define I2Cx_SDER_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define I2Cx_SDER_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================= SIER ========================================================== */ +#define I2Cx_SIER_ALERT_Pos (15UL) /*!< ALERT (Bit 15) */ +#define I2Cx_SIER_ALERT_Msk (0x8000UL) /*!< ALERT (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_GC_Pos (14UL) /*!< GC (Bit 14) */ +#define I2Cx_SIER_GC_Msk (0x4000UL) /*!< GC (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_AM1_Pos (13UL) /*!< AM1 (Bit 13) */ +#define I2Cx_SIER_AM1_Msk (0x2000UL) /*!< AM1 (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_AM0_Pos (12UL) /*!< AM0 (Bit 12) */ +#define I2Cx_SIER_AM0_Msk (0x1000UL) /*!< AM0 (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_FIFO_Pos (11UL) /*!< FIFO (Bit 11) */ +#define I2Cx_SIER_FIFO_Msk (0x800UL) /*!< FIFO (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_BIT_Pos (10UL) /*!< BIT (Bit 10) */ +#define I2Cx_SIER_BIT_Msk (0x400UL) /*!< BIT (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define I2Cx_SIER_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_RESTART_Pos (8UL) /*!< RESTART (Bit 8) */ +#define I2Cx_SIER_RESTART_Msk (0x100UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_TACK_Pos (3UL) /*!< TACK (Bit 3) */ +#define I2Cx_SIER_TACK_Msk (0x8UL) /*!< TACK (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_ADDR_Pos (2UL) /*!< ADDR (Bit 2) */ +#define I2Cx_SIER_ADDR_Msk (0x4UL) /*!< ADDR (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define I2Cx_SIER_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define I2Cx_SIER_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ +#define I2Cx_SISR_BUSBUSY_Pos (25UL) /*!< BUSBUSY (Bit 25) */ +#define I2Cx_SISR_BUSBUSY_Msk (0x2000000UL) /*!< BUSBUSY (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_SLVBUSY_Pos (24UL) /*!< SLVBUSY (Bit 24) */ +#define I2Cx_SISR_SLVBUSY_Msk (0x1000000UL) /*!< SLVBUSY (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_ALERT_Pos (15UL) /*!< ALERT (Bit 15) */ +#define I2Cx_SISR_ALERT_Msk (0x8000UL) /*!< ALERT (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_GC_Pos (14UL) /*!< GC (Bit 14) */ +#define I2Cx_SISR_GC_Msk (0x4000UL) /*!< GC (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_AM1_Pos (13UL) /*!< AM1 (Bit 13) */ +#define I2Cx_SISR_AM1_Msk (0x2000UL) /*!< AM1 (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_AM0_Pos (12UL) /*!< AM0 (Bit 12) */ +#define I2Cx_SISR_AM0_Msk (0x1000UL) /*!< AM0 (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_FIFO_Pos (11UL) /*!< FIFO (Bit 11) */ +#define I2Cx_SISR_FIFO_Msk (0x800UL) /*!< FIFO (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_BIT_Pos (10UL) /*!< BIT (Bit 10) */ +#define I2Cx_SISR_BIT_Msk (0x400UL) /*!< BIT (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define I2Cx_SISR_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_RESTART_Pos (8UL) /*!< RESTART (Bit 8) */ +#define I2Cx_SISR_RESTART_Msk (0x100UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_TACK_Pos (3UL) /*!< TACK (Bit 3) */ +#define I2Cx_SISR_TACK_Msk (0x8UL) /*!< TACK (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_ADDR_Pos (2UL) /*!< ADDR (Bit 2) */ +#define I2Cx_SISR_ADDR_Msk (0x4UL) /*!< ADDR (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define I2Cx_SISR_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define I2Cx_SISR_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================= SICR ========================================================== */ +#define I2Cx_SICR_FIFO_Pos (11UL) /*!< FIFO (Bit 11) */ +#define I2Cx_SICR_FIFO_Msk (0x800UL) /*!< FIFO (Bitfield-Mask: 0x01) */ +#define I2Cx_SICR_BIT_Pos (10UL) /*!< BIT (Bit 10) */ +#define I2Cx_SICR_BIT_Msk (0x400UL) /*!< BIT (Bitfield-Mask: 0x01) */ +#define I2Cx_SICR_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define I2Cx_SICR_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define I2Cx_SICR_RESTART_Pos (8UL) /*!< RESTART (Bit 8) */ +#define I2Cx_SICR_RESTART_Msk (0x100UL) /*!< RESTART (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ IRMOD ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define IRMOD_CR_INV_Pos (5UL) /*!< INV (Bit 5) */ +#define IRMOD_CR_INV_Msk (0x20UL) /*!< INV (Bitfield-Mask: 0x01) */ +#define IRMOD_CR_IRSW_Pos (4UL) /*!< IRSW (Bit 4) */ +#define IRMOD_CR_IRSW_Msk (0x10UL) /*!< IRSW (Bitfield-Mask: 0x01) */ +#define IRMOD_CR_MOD_Pos (0UL) /*!< MOD (Bit 0) */ +#define IRMOD_CR_MOD_Msk (0xfUL) /*!< MOD (Bitfield-Mask: 0x0f) */ + + +/* =========================================================================================================================== */ +/* ================ IWDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== KR =========================================================== */ +#define IWDT_KR_KR_Pos (0UL) /*!< KR (Bit 0) */ +#define IWDT_KR_KR_Msk (0xffffUL) /*!< KR (Bitfield-Mask: 0xffff) */ +/* ========================================================== CR =========================================================== */ +#define IWDT_CR_PAUSE_Pos (5UL) /*!< PAUSE (Bit 5) */ +#define IWDT_CR_PAUSE_Msk (0x20UL) /*!< PAUSE (Bitfield-Mask: 0x01) */ +#define IWDT_CR_IE_Pos (4UL) /*!< IE (Bit 4) */ +#define IWDT_CR_IE_Msk (0x10UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define IWDT_CR_ACTION_Pos (3UL) /*!< ACTION (Bit 3) */ +#define IWDT_CR_ACTION_Msk (0x8UL) /*!< ACTION (Bitfield-Mask: 0x01) */ +#define IWDT_CR_PRS_Pos (0UL) /*!< PRS (Bit 0) */ +#define IWDT_CR_PRS_Msk (0x7UL) /*!< PRS (Bitfield-Mask: 0x07) */ +/* ========================================================== ARR ========================================================== */ +#define IWDT_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define IWDT_ARR_ARR_Msk (0xfffUL) /*!< ARR (Bitfield-Mask: 0xfff) */ +/* ========================================================== CNT ========================================================== */ +#define IWDT_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define IWDT_CNT_CNT_Msk (0xfffUL) /*!< CNT (Bitfield-Mask: 0xfff) */ +/* ========================================================= WINR ========================================================== */ +#define IWDT_WINR_WINR_Pos (0UL) /*!< WINR (Bit 0) */ +#define IWDT_WINR_WINR_Msk (0xfffUL) /*!< WINR (Bitfield-Mask: 0xfff) */ +/* ========================================================== SR =========================================================== */ +#define IWDT_SR_RELOAD_Pos (5UL) /*!< RELOAD (Bit 5) */ +#define IWDT_SR_RELOAD_Msk (0x20UL) /*!< RELOAD (Bitfield-Mask: 0x01) */ +#define IWDT_SR_RUN_Pos (4UL) /*!< RUN (Bit 4) */ +#define IWDT_SR_RUN_Msk (0x10UL) /*!< RUN (Bitfield-Mask: 0x01) */ +#define IWDT_SR_OV_Pos (3UL) /*!< OV (Bit 3) */ +#define IWDT_SR_OV_Msk (0x8UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define IWDT_SR_WINRF_Pos (2UL) /*!< WINRF (Bit 2) */ +#define IWDT_SR_WINRF_Msk (0x4UL) /*!< WINRF (Bitfield-Mask: 0x01) */ +#define IWDT_SR_ARRF_Pos (1UL) /*!< ARRF (Bit 1) */ +#define IWDT_SR_ARRF_Msk (0x2UL) /*!< ARRF (Bitfield-Mask: 0x01) */ +#define IWDT_SR_CRF_Pos (0UL) /*!< CRF (Bit 0) */ +#define IWDT_SR_CRF_Msk (0x1UL) /*!< CRF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LPTIM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CFGR ========================================================== */ +#define LPTIM_CFGR_ICLKSRC_Pos (25UL) /*!< ICLKSRC (Bit 25) */ +#define LPTIM_CFGR_ICLKSRC_Msk (0x6000000UL) /*!< ICLKSRC (Bitfield-Mask: 0x03) */ +#define LPTIM_CFGR_ENC_Pos (24UL) /*!< ENC (Bit 24) */ +#define LPTIM_CFGR_ENC_Msk (0x1000000UL) /*!< ENC (Bitfield-Mask: 0x01) */ +#define LPTIM_CFGR_COUNTMD_Pos (23UL) /*!< COUNTMD (Bit 23) */ +#define LPTIM_CFGR_COUNTMD_Msk (0x800000UL) /*!< COUNTMD (Bitfield-Mask: 0x01) */ +#define LPTIM_CFGR_PRELOAD_Pos (22UL) /*!< PRELOAD (Bit 22) */ +#define LPTIM_CFGR_PRELOAD_Msk (0x400000UL) /*!< PRELOAD (Bitfield-Mask: 0x01) */ +#define LPTIM_CFGR_WAVPOL_Pos (21UL) /*!< WAVPOL (Bit 21) */ +#define LPTIM_CFGR_WAVPOL_Msk (0x200000UL) /*!< WAVPOL (Bitfield-Mask: 0x01) */ +#define LPTIM_CFGR_WAVE_Pos (20UL) /*!< WAVE (Bit 20) */ +#define LPTIM_CFGR_WAVE_Msk (0x100000UL) /*!< WAVE (Bitfield-Mask: 0x01) */ +#define LPTIM_CFGR_TIMOUT_Pos (19UL) /*!< TIMOUT (Bit 19) */ +#define LPTIM_CFGR_TIMOUT_Msk (0x80000UL) /*!< TIMOUT (Bitfield-Mask: 0x01) */ +#define LPTIM_CFGR_TRIGEN_Pos (17UL) /*!< TRIGEN (Bit 17) */ +#define LPTIM_CFGR_TRIGEN_Msk (0x60000UL) /*!< TRIGEN (Bitfield-Mask: 0x03) */ +#define LPTIM_CFGR_TRIGSEL_Pos (12UL) /*!< TRIGSEL (Bit 12) */ +#define LPTIM_CFGR_TRIGSEL_Msk (0xf000UL) /*!< TRIGSEL (Bitfield-Mask: 0x0f) */ +#define LPTIM_CFGR_PRS_Pos (9UL) /*!< PRS (Bit 9) */ +#define LPTIM_CFGR_PRS_Msk (0xe00UL) /*!< PRS (Bitfield-Mask: 0x07) */ +#define LPTIM_CFGR_TRIGFLT_Pos (6UL) /*!< TRIGFLT (Bit 6) */ +#define LPTIM_CFGR_TRIGFLT_Msk (0xc0UL) /*!< TRIGFLT (Bitfield-Mask: 0x03) */ +#define LPTIM_CFGR_CHFLT_Pos (3UL) /*!< CHFLT (Bit 3) */ +#define LPTIM_CFGR_CHFLT_Msk (0x18UL) /*!< CHFLT (Bitfield-Mask: 0x03) */ +#define LPTIM_CFGR_ENCMD_CKPOL_Pos (1UL) /*!< ENCMD_CKPOL (Bit 1) */ +#define LPTIM_CFGR_ENCMD_CKPOL_Msk (0x6UL) /*!< ENCMD_CKPOL (Bitfield-Mask: 0x03) */ +#define LPTIM_CFGR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ +#define LPTIM_CFGR_CKSEL_Msk (0x1UL) /*!< CKSEL (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ +#define LPTIM_CR0_ARST_Pos (4UL) /*!< ARST (Bit 4) */ +#define LPTIM_CR0_ARST_Msk (0x10UL) /*!< ARST (Bitfield-Mask: 0x01) */ +#define LPTIM_CR0_SRST_Pos (3UL) /*!< SRST (Bit 3) */ +#define LPTIM_CR0_SRST_Msk (0x8UL) /*!< SRST (Bitfield-Mask: 0x01) */ +#define LPTIM_CR0_CNTSTART_Pos (2UL) /*!< CNTSTART (Bit 2) */ +#define LPTIM_CR0_CNTSTART_Msk (0x4UL) /*!< CNTSTART (Bitfield-Mask: 0x01) */ +#define LPTIM_CR0_SNGSTART_Pos (1UL) /*!< SNGSTART (Bit 1) */ +#define LPTIM_CR0_SNGSTART_Msk (0x2UL) /*!< SNGSTART (Bitfield-Mask: 0x01) */ +#define LPTIM_CR0_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define LPTIM_CR0_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== ARR ========================================================== */ +#define LPTIM_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define LPTIM_ARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ========================================================== CNT ========================================================== */ +#define LPTIM_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define LPTIM_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== CMP ========================================================== */ +#define LPTIM_CMP_CMP_Pos (0UL) /*!< CMP (Bit 0) */ +#define LPTIM_CMP_CMP_Msk (0xffffUL) /*!< CMP (Bitfield-Mask: 0xffff) */ +/* ========================================================== IER ========================================================== */ +#define LPTIM_IER_DOWN_Pos (6UL) /*!< DOWN (Bit 6) */ +#define LPTIM_IER_DOWN_Msk (0x40UL) /*!< DOWN (Bitfield-Mask: 0x01) */ +#define LPTIM_IER_UP_Pos (5UL) /*!< UP (Bit 5) */ +#define LPTIM_IER_UP_Msk (0x20UL) /*!< UP (Bitfield-Mask: 0x01) */ +#define LPTIM_IER_ARROK_Pos (4UL) /*!< ARROK (Bit 4) */ +#define LPTIM_IER_ARROK_Msk (0x10UL) /*!< ARROK (Bitfield-Mask: 0x01) */ +#define LPTIM_IER_CMPOK_Pos (3UL) /*!< CMPOK (Bit 3) */ +#define LPTIM_IER_CMPOK_Msk (0x8UL) /*!< CMPOK (Bitfield-Mask: 0x01) */ +#define LPTIM_IER_EXTTRIG_Pos (2UL) /*!< EXTTRIG (Bit 2) */ +#define LPTIM_IER_EXTTRIG_Msk (0x4UL) /*!< EXTTRIG (Bitfield-Mask: 0x01) */ +#define LPTIM_IER_ARRM_Pos (1UL) /*!< ARRM (Bit 1) */ +#define LPTIM_IER_ARRM_Msk (0x2UL) /*!< ARRM (Bitfield-Mask: 0x01) */ +#define LPTIM_IER_CMPM_Pos (0UL) /*!< CMPM (Bit 0) */ +#define LPTIM_IER_CMPM_Msk (0x1UL) /*!< CMPM (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define LPTIM_ISR_DIR_Pos (7UL) /*!< DIR (Bit 7) */ +#define LPTIM_ISR_DIR_Msk (0x180UL) /*!< DIR (Bitfield-Mask: 0x03) */ +#define LPTIM_ISR_DOWN_Pos (6UL) /*!< DOWN (Bit 6) */ +#define LPTIM_ISR_DOWN_Msk (0x40UL) /*!< DOWN (Bitfield-Mask: 0x01) */ +#define LPTIM_ISR_UP_Pos (5UL) /*!< UP (Bit 5) */ +#define LPTIM_ISR_UP_Msk (0x20UL) /*!< UP (Bitfield-Mask: 0x01) */ +#define LPTIM_ISR_ARROK_Pos (4UL) /*!< ARROK (Bit 4) */ +#define LPTIM_ISR_ARROK_Msk (0x10UL) /*!< ARROK (Bitfield-Mask: 0x01) */ +#define LPTIM_ISR_CMPOK_Pos (3UL) /*!< CMPOK (Bit 3) */ +#define LPTIM_ISR_CMPOK_Msk (0x8UL) /*!< CMPOK (Bitfield-Mask: 0x01) */ +#define LPTIM_ISR_EXTTRIG_Pos (2UL) /*!< EXTTRIG (Bit 2) */ +#define LPTIM_ISR_EXTTRIG_Msk (0x4UL) /*!< EXTTRIG (Bitfield-Mask: 0x01) */ +#define LPTIM_ISR_ARRM_Pos (1UL) /*!< ARRM (Bit 1) */ +#define LPTIM_ISR_ARRM_Msk (0x2UL) /*!< ARRM (Bitfield-Mask: 0x01) */ +#define LPTIM_ISR_CMPM_Pos (0UL) /*!< CMPM (Bit 0) */ +#define LPTIM_ISR_CMPM_Msk (0x1UL) /*!< CMPM (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define LPTIM_ICR_DOWN_Pos (6UL) /*!< DOWN (Bit 6) */ +#define LPTIM_ICR_DOWN_Msk (0x40UL) /*!< DOWN (Bitfield-Mask: 0x01) */ +#define LPTIM_ICR_UP_Pos (5UL) /*!< UP (Bit 5) */ +#define LPTIM_ICR_UP_Msk (0x20UL) /*!< UP (Bitfield-Mask: 0x01) */ +#define LPTIM_ICR_ARROK_Pos (4UL) /*!< ARROK (Bit 4) */ +#define LPTIM_ICR_ARROK_Msk (0x10UL) /*!< ARROK (Bitfield-Mask: 0x01) */ +#define LPTIM_ICR_CMPOK_Pos (3UL) /*!< CMPOK (Bit 3) */ +#define LPTIM_ICR_CMPOK_Msk (0x8UL) /*!< CMPOK (Bitfield-Mask: 0x01) */ +#define LPTIM_ICR_EXTTRIG_Pos (2UL) /*!< EXTTRIG (Bit 2) */ +#define LPTIM_ICR_EXTTRIG_Msk (0x4UL) /*!< EXTTRIG (Bitfield-Mask: 0x01) */ +#define LPTIM_ICR_ARRM_Pos (1UL) /*!< ARRM (Bit 1) */ +#define LPTIM_ICR_ARRM_Msk (0x2UL) /*!< ARRM (Bitfield-Mask: 0x01) */ +#define LPTIM_ICR_CMPM_Pos (0UL) /*!< CMPM (Bit 0) */ +#define LPTIM_ICR_CMPM_Msk (0x1UL) /*!< CMPM (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ +#define LPTIM_CR1_CH2SRC_Pos (3UL) /*!< CH2SRC (Bit 3) */ +#define LPTIM_CR1_CH2SRC_Msk (0x38UL) /*!< CH2SRC (Bitfield-Mask: 0x07) */ +#define LPTIM_CR1_CH1SRC_Pos (0UL) /*!< CH1SRC (Bit 0) */ +#define LPTIM_CR1_CH1SRC_Msk (0x7UL) /*!< CH1SRC (Bitfield-Mask: 0x07) */ + + +/* =========================================================================================================================== */ +/* ================ UART ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define UARTx_CR1_SYNC_Pos (14UL) /*!< SYNC (Bit 14) */ +#define UARTx_CR1_SYNC_Msk (0x4000UL) /*!< SYNC (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_SOURCE_Pos (12UL) /*!< SOURCE (Bit 12) */ +#define UARTx_CR1_SOURCE_Msk (0x3000UL) /*!< SOURCE (Bitfield-Mask: 0x03) */ +#define UARTx_CR1_SIGNAL_Pos (11UL) /*!< SIGNAL (Bit 11) */ +#define UARTx_CR1_SIGNAL_Msk (0x800UL) /*!< SIGNAL (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_OVER_Pos (9UL) /*!< OVER (Bit 9) */ +#define UARTx_CR1_OVER_Msk (0x600UL) /*!< OVER (Bitfield-Mask: 0x03) */ +#define UARTx_CR1_START_Pos (8UL) /*!< START (Bit 8) */ +#define UARTx_CR1_START_Msk (0x100UL) /*!< START (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_MSBF_Pos (7UL) /*!< MSBF (Bit 7) */ +#define UARTx_CR1_MSBF_Msk (0x80UL) /*!< MSBF (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_CHLEN_Pos (6UL) /*!< CHLEN (Bit 6) */ +#define UARTx_CR1_CHLEN_Msk (0x40UL) /*!< CHLEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_STOP_Pos (4UL) /*!< STOP (Bit 4) */ +#define UARTx_CR1_STOP_Msk (0x30UL) /*!< STOP (Bitfield-Mask: 0x03) */ +#define UARTx_CR1_PARITYEN_Pos (3UL) /*!< PARITYEN (Bit 3) */ +#define UARTx_CR1_PARITYEN_Msk (0x8UL) /*!< PARITYEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_PARITY_Pos (2UL) /*!< PARITY (Bit 2) */ +#define UARTx_CR1_PARITY_Msk (0x4UL) /*!< PARITY (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_RXEN_Pos (1UL) /*!< RXEN (Bit 1) */ +#define UARTx_CR1_RXEN_Msk (0x2UL) /*!< RXEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_TXEN_Pos (0UL) /*!< TXEN (Bit 0) */ +#define UARTx_CR1_TXEN_Msk (0x1UL) /*!< TXEN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define UARTx_CR2_RXSRC_Pos (15UL) /*!< RXSRC (Bit 15) */ +#define UARTx_CR2_RXSRC_Msk (0x38000UL) /*!< RXSRC (Bitfield-Mask: 0x07) */ +#define UARTx_CR2_LOOP_Pos (14UL) /*!< LOOP (Bit 14) */ +#define UARTx_CR2_LOOP_Msk (0x4000UL) /*!< LOOP (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_ADCTX_Pos (13UL) /*!< ADCTX (Bit 13) */ +#define UARTx_CR2_ADCTX_Msk (0x2000UL) /*!< ADCTX (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_ADCRX_Pos (12UL) /*!< ADCRX (Bit 12) */ +#define UARTx_CR2_ADCRX_Msk (0x1000UL) /*!< ADCRX (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_SWAP_Pos (11UL) /*!< SWAP (Bit 11) */ +#define UARTx_CR2_SWAP_Msk (0x800UL) /*!< SWAP (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_TIMCR_Pos (8UL) /*!< TIMCR (Bit 8) */ +#define UARTx_CR2_TIMCR_Msk (0x700UL) /*!< TIMCR (Bitfield-Mask: 0x07) */ +#define UARTx_CR2_DMATX_Pos (7UL) /*!< DMATX (Bit 7) */ +#define UARTx_CR2_DMATX_Msk (0x80UL) /*!< DMATX (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_DMARX_Pos (6UL) /*!< DMARX (Bit 6) */ +#define UARTx_CR2_DMARX_Msk (0x40UL) /*!< DMARX (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_TXINV_Pos (5UL) /*!< TXINV (Bit 5) */ +#define UARTx_CR2_TXINV_Msk (0x20UL) /*!< TXINV (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_RXINV_Pos (4UL) /*!< RXINV (Bit 4) */ +#define UARTx_CR2_RXINV_Msk (0x10UL) /*!< RXINV (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_RTSEN_Pos (3UL) /*!< RTSEN (Bit 3) */ +#define UARTx_CR2_RTSEN_Msk (0x8UL) /*!< RTSEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_CTSEN_Pos (2UL) /*!< CTSEN (Bit 2) */ +#define UARTx_CR2_CTSEN_Msk (0x4UL) /*!< CTSEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_RXMATCHEN_Pos (1UL) /*!< RXMATCHEN (Bit 1) */ +#define UARTx_CR2_RXMATCHEN_Msk (0x2UL) /*!< RXMATCHEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_ADDREN_Pos (0UL) /*!< ADDREN (Bit 0) */ +#define UARTx_CR2_ADDREN_Msk (0x1UL) /*!< ADDREN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR3 ========================================================== */ +#define UARTx_CR3_BRKL_Pos (8UL) /*!< BRKL (Bit 8) */ +#define UARTx_CR3_BRKL_Msk (0x100UL) /*!< BRKL (Bitfield-Mask: 0x01) */ +#define UARTx_CR3_LIN_Pos (7UL) /*!< LIN (Bit 7) */ +#define UARTx_CR3_LIN_Msk (0x80UL) /*!< LIN (Bitfield-Mask: 0x01) */ +#define UARTx_CR3_DETIME_Pos (2UL) /*!< DETIME (Bit 2) */ +#define UARTx_CR3_DETIME_Msk (0x7cUL) /*!< DETIME (Bitfield-Mask: 0x1f) */ +#define UARTx_CR3_DEP_Pos (1UL) /*!< DEP (Bit 1) */ +#define UARTx_CR3_DEP_Msk (0x2UL) /*!< DEP (Bitfield-Mask: 0x01) */ +#define UARTx_CR3_DEM_Pos (0UL) /*!< DEM (Bit 0) */ +#define UARTx_CR3_DEM_Msk (0x1UL) /*!< DEM (Bitfield-Mask: 0x01) */ +/* ========================================================= BRRI ========================================================== */ +#define UARTx_BRRI_BRRI_Pos (0UL) /*!< BRRI (Bit 0) */ +#define UARTx_BRRI_BRRI_Msk (0xffffUL) /*!< BRRI (Bitfield-Mask: 0xffff) */ +/* ========================================================= BRRF ========================================================== */ +#define UARTx_BRRF_BRRF_Pos (0UL) /*!< BRRF (Bit 0) */ +#define UARTx_BRRF_BRRF_Msk (0xfUL) /*!< BRRF (Bitfield-Mask: 0x0f) */ +/* ======================================================== TIMARR ========================================================= */ +#define UARTx_TIMARR_TIMARR_Pos (0UL) /*!< TIMARR (Bit 0) */ +#define UARTx_TIMARR_TIMARR_Msk (0xffffffUL) /*!< TIMARR (Bitfield-Mask: 0xffffff) */ +/* ======================================================== TIMCNT ========================================================= */ +#define UARTx_TIMCNT_TIMCNT_Pos (0UL) /*!< TIMCNT (Bit 0) */ +#define UARTx_TIMCNT_TIMCNT_Msk (0xffffffUL) /*!< TIMCNT (Bitfield-Mask: 0xffffff) */ +/* ========================================================== TDR ========================================================== */ +#define UARTx_TDR_BREAK_Pos (10UL) /*!< BREAK (Bit 10) */ +#define UARTx_TDR_BREAK_Msk (0x400UL) /*!< BREAK (Bitfield-Mask: 0x01) */ +#define UARTx_TDR_IDLE_Pos (9UL) /*!< IDLE (Bit 9) */ +#define UARTx_TDR_IDLE_Msk (0x200UL) /*!< IDLE (Bitfield-Mask: 0x01) */ +#define UARTx_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ +#define UARTx_TDR_TDR_Msk (0x1ffUL) /*!< TDR (Bitfield-Mask: 0x1ff) */ +/* ========================================================== RDR ========================================================== */ +#define UARTx_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ +#define UARTx_RDR_RDR_Msk (0x1ffUL) /*!< RDR (Bitfield-Mask: 0x1ff) */ +/* ========================================================== IER ========================================================== */ +#define UARTx_IER_RXMATCH_Pos (12UL) /*!< RXMATCH (Bit 12) */ +#define UARTx_IER_RXMATCH_Msk (0x1000UL) /*!< RXMATCH (Bitfield-Mask: 0x01) */ +#define UARTx_IER_ORE_Pos (11UL) /*!< ORE (Bit 11) */ +#define UARTx_IER_ORE_Msk (0x800UL) /*!< ORE (Bitfield-Mask: 0x01) */ +#define UARTx_IER_NE_Pos (10UL) /*!< NE (Bit 10) */ +#define UARTx_IER_NE_Msk (0x400UL) /*!< NE (Bitfield-Mask: 0x01) */ +#define UARTx_IER_PE_Pos (9UL) /*!< PE (Bit 9) */ +#define UARTx_IER_PE_Msk (0x200UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UARTx_IER_FE_Pos (8UL) /*!< FE (Bit 8) */ +#define UARTx_IER_FE_Msk (0x100UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UARTx_IER_CTS_Pos (7UL) /*!< CTS (Bit 7) */ +#define UARTx_IER_CTS_Msk (0x80UL) /*!< CTS (Bitfield-Mask: 0x01) */ +#define UARTx_IER_TIMOV_Pos (6UL) /*!< TIMOV (Bit 6) */ +#define UARTx_IER_TIMOV_Msk (0x40UL) /*!< TIMOV (Bitfield-Mask: 0x01) */ +#define UARTx_IER_BAUD_Pos (5UL) /*!< BAUD (Bit 5) */ +#define UARTx_IER_BAUD_Msk (0x20UL) /*!< BAUD (Bitfield-Mask: 0x01) */ +#define UARTx_IER_RXBRK_Pos (4UL) /*!< RXBRK (Bit 4) */ +#define UARTx_IER_RXBRK_Msk (0x10UL) /*!< RXBRK (Bitfield-Mask: 0x01) */ +#define UARTx_IER_RXIDLE_Pos (3UL) /*!< RXIDLE (Bit 3) */ +#define UARTx_IER_RXIDLE_Msk (0x8UL) /*!< RXIDLE (Bitfield-Mask: 0x01) */ +#define UARTx_IER_RC_Pos (2UL) /*!< RC (Bit 2) */ +#define UARTx_IER_RC_Msk (0x4UL) /*!< RC (Bitfield-Mask: 0x01) */ +#define UARTx_IER_TC_Pos (1UL) /*!< TC (Bit 1) */ +#define UARTx_IER_TC_Msk (0x2UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define UARTx_IER_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define UARTx_IER_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define UARTx_ISR_CTSLV_Pos (15UL) /*!< CTSLV (Bit 15) */ +#define UARTx_ISR_CTSLV_Msk (0x8000UL) /*!< CTSLV (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_TXBUSY_Pos (14UL) /*!< TXBUSY (Bit 14) */ +#define UARTx_ISR_TXBUSY_Msk (0x4000UL) /*!< TXBUSY (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_SLVMATCH_Pos (13UL) /*!< SLVMATCH (Bit 13) */ +#define UARTx_ISR_SLVMATCH_Msk (0x2000UL) /*!< SLVMATCH (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_RXMATCH_Pos (12UL) /*!< RXMATCH (Bit 12) */ +#define UARTx_ISR_RXMATCH_Msk (0x1000UL) /*!< RXMATCH (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_ORE_Pos (11UL) /*!< ORE (Bit 11) */ +#define UARTx_ISR_ORE_Msk (0x800UL) /*!< ORE (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_NE_Pos (10UL) /*!< NE (Bit 10) */ +#define UARTx_ISR_NE_Msk (0x400UL) /*!< NE (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_PE_Pos (9UL) /*!< PE (Bit 9) */ +#define UARTx_ISR_PE_Msk (0x200UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_FE_Pos (8UL) /*!< FE (Bit 8) */ +#define UARTx_ISR_FE_Msk (0x100UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_CTS_Pos (7UL) /*!< CTS (Bit 7) */ +#define UARTx_ISR_CTS_Msk (0x80UL) /*!< CTS (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_TIMOV_Pos (6UL) /*!< TIMOV (Bit 6) */ +#define UARTx_ISR_TIMOV_Msk (0x40UL) /*!< TIMOV (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_BAUD_Pos (5UL) /*!< BAUD (Bit 5) */ +#define UARTx_ISR_BAUD_Msk (0x20UL) /*!< BAUD (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_RXBRK_Pos (4UL) /*!< RXBRK (Bit 4) */ +#define UARTx_ISR_RXBRK_Msk (0x10UL) /*!< RXBRK (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_RXIDLE_Pos (3UL) /*!< RXIDLE (Bit 3) */ +#define UARTx_ISR_RXIDLE_Msk (0x8UL) /*!< RXIDLE (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_RC_Pos (2UL) /*!< RC (Bit 2) */ +#define UARTx_ISR_RC_Msk (0x4UL) /*!< RC (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_TC_Pos (1UL) /*!< TC (Bit 1) */ +#define UARTx_ISR_TC_Msk (0x2UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define UARTx_ISR_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define UARTx_ICR_RXMATCH_Pos (12UL) /*!< RXMATCH (Bit 12) */ +#define UARTx_ICR_RXMATCH_Msk (0x1000UL) /*!< RXMATCH (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_ORE_Pos (11UL) /*!< ORE (Bit 11) */ +#define UARTx_ICR_ORE_Msk (0x800UL) /*!< ORE (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_NE_Pos (10UL) /*!< NE (Bit 10) */ +#define UARTx_ICR_NE_Msk (0x400UL) /*!< NE (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_PE_Pos (9UL) /*!< PE (Bit 9) */ +#define UARTx_ICR_PE_Msk (0x200UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_FE_Pos (8UL) /*!< FE (Bit 8) */ +#define UARTx_ICR_FE_Msk (0x100UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_CTS_Pos (7UL) /*!< CTS (Bit 7) */ +#define UARTx_ICR_CTS_Msk (0x80UL) /*!< CTS (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_TIMOV_Pos (6UL) /*!< TIMOV (Bit 6) */ +#define UARTx_ICR_TIMOV_Msk (0x40UL) /*!< TIMOV (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_BAUD_Pos (5UL) /*!< BAUD (Bit 5) */ +#define UARTx_ICR_BAUD_Msk (0x20UL) /*!< BAUD (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_RXBRK_Pos (4UL) /*!< RXBRK (Bit 4) */ +#define UARTx_ICR_RXBRK_Msk (0x10UL) /*!< RXBRK (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_RXIDLE_Pos (3UL) /*!< RXIDLE (Bit 3) */ +#define UARTx_ICR_RXIDLE_Msk (0x8UL) /*!< RXIDLE (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_RC_Pos (2UL) /*!< RC (Bit 2) */ +#define UARTx_ICR_RC_Msk (0x4UL) /*!< RC (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_TC_Pos (1UL) /*!< TC (Bit 1) */ +#define UARTx_ICR_TC_Msk (0x2UL) /*!< TC (Bitfield-Mask: 0x01) */ +/* ========================================================= ADDR ========================================================== */ +#define UARTx_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define UARTx_ADDR_ADDR_Msk (0xffUL) /*!< ADDR (Bitfield-Mask: 0xff) */ +/* ========================================================= MASK ========================================================== */ +#define UARTx_MASK_MASK_Pos (0UL) /*!< MASK (Bit 0) */ +#define UARTx_MASK_MASK_Msk (0xffUL) /*!< MASK (Bitfield-Mask: 0xff) */ +/* ======================================================== RXMATCH ======================================================== */ +#define UARTx_RXMATCH_RXMATCH_Pos (0UL) /*!< RXMATCH (Bit 0) */ +#define UARTx_RXMATCH_RXMATCH_Msk (0x1ffUL) /*!< RXMATCH (Bitfield-Mask: 0x1ff) */ + + +/* =========================================================================================================================== */ +/* ================ LVD ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define LVD_CR0_FLTCLK_Pos (8UL) /*!< FLTCLK (Bit 8) */ +#define LVD_CR0_FLTCLK_Msk (0x100UL) /*!< FLTCLK (Bitfield-Mask: 0x01) */ +#define LVD_CR0_VTH_Pos (4UL) /*!< VTH (Bit 4) */ +#define LVD_CR0_VTH_Msk (0x70UL) /*!< VTH (Bitfield-Mask: 0x07) */ +#define LVD_CR0_SOURCE_Pos (2UL) /*!< SOURCE (Bit 2) */ +#define LVD_CR0_SOURCE_Msk (0x4UL) /*!< SOURCE (Bitfield-Mask: 0x01) */ +#define LVD_CR0_ACTION_Pos (1UL) /*!< ACTION (Bit 1) */ +#define LVD_CR0_ACTION_Msk (0x2UL) /*!< ACTION (Bitfield-Mask: 0x01) */ +#define LVD_CR0_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define LVD_CR0_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ +#define LVD_CR1_FLTTIME_Pos (4UL) /*!< FLTTIME (Bit 4) */ +#define LVD_CR1_FLTTIME_Msk (0xf0UL) /*!< FLTTIME (Bitfield-Mask: 0x0f) */ +#define LVD_CR1_FALL_Pos (3UL) /*!< FALL (Bit 3) */ +#define LVD_CR1_FALL_Msk (0x8UL) /*!< FALL (Bitfield-Mask: 0x01) */ +#define LVD_CR1_RISE_Pos (2UL) /*!< RISE (Bit 2) */ +#define LVD_CR1_RISE_Msk (0x4UL) /*!< RISE (Bitfield-Mask: 0x01) */ +#define LVD_CR1_LEVEL_Pos (1UL) /*!< LEVEL (Bit 1) */ +#define LVD_CR1_LEVEL_Msk (0x2UL) /*!< LEVEL (Bitfield-Mask: 0x01) */ +#define LVD_CR1_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define LVD_CR1_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ========================================================== SR =========================================================== */ +#define LVD_SR_FLTV_Pos (1UL) /*!< FLTV (Bit 1) */ +#define LVD_SR_FLTV_Msk (0x2UL) /*!< FLTV (Bitfield-Mask: 0x01) */ +#define LVD_SR_INTF_Pos (0UL) /*!< INTF (Bit 0) */ +#define LVD_SR_INTF_Msk (0x1UL) /*!< INTF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ OPA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define OPAx_CR_BIAS_Pos (13UL) /*!< BIAS (Bit 13) */ +#define OPAx_CR_BIAS_Msk (0xe000UL) /*!< BIAS (Bitfield-Mask: 0x07) */ +#define OPAx_CR_AMP_Pos (10UL) /*!< AMP (Bit 10) */ +#define OPAx_CR_AMP_Msk (0x1c00UL) /*!< AMP (Bitfield-Mask: 0x07) */ +#define OPAx_CR_INN2EN_Pos (9UL) /*!< INN2EN (Bit 9) */ +#define OPAx_CR_INN2EN_Msk (0x200UL) /*!< INN2EN (Bitfield-Mask: 0x01) */ +#define OPAx_CR_INN1EN_Pos (8UL) /*!< INN1EN (Bit 8) */ +#define OPAx_CR_INN1EN_Msk (0x100UL) /*!< INN1EN (Bitfield-Mask: 0x01) */ +#define OPAx_CR_INP4EN_Pos (7UL) /*!< INP4EN (Bit 7) */ +#define OPAx_CR_INP4EN_Msk (0x80UL) /*!< INP4EN (Bitfield-Mask: 0x01) */ +#define OPAx_CR_INP3EN_Pos (6UL) /*!< INP3EN (Bit 6) */ +#define OPAx_CR_INP3EN_Msk (0x40UL) /*!< INP3EN (Bitfield-Mask: 0x01) */ +#define OPAx_CR_INP2EN_Pos (5UL) /*!< INP2EN (Bit 5) */ +#define OPAx_CR_INP2EN_Msk (0x20UL) /*!< INP2EN (Bitfield-Mask: 0x01) */ +#define OPAx_CR_INP1EN_Pos (4UL) /*!< INP1EN (Bit 4) */ +#define OPAx_CR_INP1EN_Msk (0x10UL) /*!< INP1EN (Bitfield-Mask: 0x01) */ +#define OPAx_CR_MODE_Pos (1UL) /*!< MODE (Bit 1) */ +#define OPAx_CR_MODE_Msk (0x6UL) /*!< MODE (Bitfield-Mask: 0x03) */ +#define OPAx_CR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define OPAx_CR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CAL ========================================================== */ +#define OPAx_CAL_GTIM4OC2_Pos (31UL) /*!< GTIM4OC2 (Bit 31) */ +#define OPAx_CAL_GTIM4OC2_Msk (0x80000000UL) /*!< GTIM4OC2 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM4OC1_Pos (30UL) /*!< GTIM4OC1 (Bit 30) */ +#define OPAx_CAL_GTIM4OC1_Msk (0x40000000UL) /*!< GTIM4OC1 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM4TRGO_Pos (29UL) /*!< GTIM4TRGO (Bit 29) */ +#define OPAx_CAL_GTIM4TRGO_Msk (0x20000000UL) /*!< GTIM4TRGO (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM3OC2_Pos (28UL) /*!< GTIM3OC2 (Bit 28) */ +#define OPAx_CAL_GTIM3OC2_Msk (0x10000000UL) /*!< GTIM3OC2 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM3OC1_Pos (27UL) /*!< GTIM3OC1 (Bit 27) */ +#define OPAx_CAL_GTIM3OC1_Msk (0x8000000UL) /*!< GTIM3OC1 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM3TRGO_Pos (26UL) /*!< GTIM3TRGO (Bit 26) */ +#define OPAx_CAL_GTIM3TRGO_Msk (0x4000000UL) /*!< GTIM3TRGO (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM2OC2_Pos (25UL) /*!< GTIM2OC2 (Bit 25) */ +#define OPAx_CAL_GTIM2OC2_Msk (0x2000000UL) /*!< GTIM2OC2 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM2OC1_Pos (24UL) /*!< GTIM2OC1 (Bit 24) */ +#define OPAx_CAL_GTIM2OC1_Msk (0x1000000UL) /*!< GTIM2OC1 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM2TRGO_Pos (23UL) /*!< GTIM2TRGO (Bit 23) */ +#define OPAx_CAL_GTIM2TRGO_Msk (0x800000UL) /*!< GTIM2TRGO (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM1OC2_Pos (22UL) /*!< GTIM1OC2 (Bit 22) */ +#define OPAx_CAL_GTIM1OC2_Msk (0x400000UL) /*!< GTIM1OC2 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM1OC1_Pos (21UL) /*!< GTIM1OC1 (Bit 21) */ +#define OPAx_CAL_GTIM1OC1_Msk (0x200000UL) /*!< GTIM1OC1 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM1TRGO_Pos (20UL) /*!< GTIM1TRGO (Bit 20) */ +#define OPAx_CAL_GTIM1TRGO_Msk (0x100000UL) /*!< GTIM1TRGO (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_ATIM1OC6_Pos (19UL) /*!< ATIM1OC6 (Bit 19) */ +#define OPAx_CAL_ATIM1OC6_Msk (0x80000UL) /*!< ATIM1OC6 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_ATIM1OC5_Pos (18UL) /*!< ATIM1OC5 (Bit 18) */ +#define OPAx_CAL_ATIM1OC5_Msk (0x40000UL) /*!< ATIM1OC5 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_ATIM1OC4_Pos (17UL) /*!< ATIM1OC4 (Bit 17) */ +#define OPAx_CAL_ATIM1OC4_Msk (0x20000UL) /*!< ATIM1OC4 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_ATIM1TRGO_Pos (16UL) /*!< ATIM1TRGO (Bit 16) */ +#define OPAx_CAL_ATIM1TRGO_Msk (0x10000UL) /*!< ATIM1TRGO (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_ADC2START1_Pos (15UL) /*!< ADC2START1 (Bit 15) */ +#define OPAx_CAL_ADC2START1_Msk (0x8000UL) /*!< ADC2START1 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_ADC1START1_Pos (14UL) /*!< ADC1START1 (Bit 14) */ +#define OPAx_CAL_ADC1START1_Msk (0x4000UL) /*!< ADC1START1 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_CLKDIV_Pos (11UL) /*!< CLKDIV (Bit 11) */ +#define OPAx_CAL_CLKDIV_Msk (0x3800UL) /*!< CLKDIV (Bitfield-Mask: 0x07) */ +#define OPAx_CAL_AZRUN_Pos (10UL) /*!< AZRUN (Bit 10) */ +#define OPAx_CAL_AZRUN_Msk (0x400UL) /*!< AZRUN (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_ADCSTART_Pos (8UL) /*!< ADCSTART (Bit 8) */ +#define OPAx_CAL_ADCSTART_Msk (0x100UL) /*!< ADCSTART (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_CALPERIOD_Pos (4UL) /*!< CALPERIOD (Bit 4) */ +#define OPAx_CAL_CALPERIOD_Msk (0xf0UL) /*!< CALPERIOD (Bitfield-Mask: 0x0f) */ +#define OPAx_CAL_SOFTTRIG_Pos (3UL) /*!< SOFTTRIG (Bit 3) */ +#define OPAx_CAL_SOFTTRIG_Msk (0x8UL) /*!< SOFTTRIG (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_START_Pos (2UL) /*!< START (Bit 2) */ +#define OPAx_CAL_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_CALMODE_Pos (1UL) /*!< CALMODE (Bit 1) */ +#define OPAx_CAL_CALMODE_Msk (0x2UL) /*!< CALMODE (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_CALEN_Pos (0UL) /*!< CALEN (Bit 0) */ +#define OPAx_CAL_CALEN_Msk (0x1UL) /*!< CALEN (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ RAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== IER ========================================================== */ +#define RAM_IER_PARITY_Pos (0UL) /*!< PARITY (Bit 0) */ +#define RAM_IER_PARITY_Msk (0x1UL) /*!< PARITY (Bitfield-Mask: 0x01) */ +/* ========================================================= ADDR ========================================================== */ +#define RAM_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define RAM_ADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== ISR ========================================================== */ +#define RAM_ISR_PARITY_Pos (0UL) /*!< PARITY (Bit 0) */ +#define RAM_ISR_PARITY_Msk (0x1UL) /*!< PARITY (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define RAM_ICR_PARITY_Pos (0UL) /*!< PARITY (Bit 0) */ +#define RAM_ICR_PARITY_Msk (0x1UL) /*!< PARITY (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== KEY ========================================================== */ +#define RTC_KEY_KEY_Pos (0UL) /*!< KEY (Bit 0) */ +#define RTC_KEY_KEY_Msk (0xffUL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================== CR0 ========================================================== */ +#define RTC_CR0_START_Pos (7UL) /*!< START (Bit 7) */ +#define RTC_CR0_START_Msk (0x80UL) /*!< START (Bitfield-Mask: 0x01) */ +#define RTC_CR0_RTC1HZ_Pos (5UL) /*!< RTC1HZ (Bit 5) */ +#define RTC_CR0_RTC1HZ_Msk (0x60UL) /*!< RTC1HZ (Bitfield-Mask: 0x03) */ +#define RTC_CR0_H24_Pos (3UL) /*!< H24 (Bit 3) */ +#define RTC_CR0_H24_Msk (0x8UL) /*!< H24 (Bitfield-Mask: 0x01) */ +#define RTC_CR0_INTERVAL_Pos (0UL) /*!< INTERVAL (Bit 0) */ +#define RTC_CR0_INTERVAL_Msk (0x7UL) /*!< INTERVAL (Bitfield-Mask: 0x07) */ +/* ========================================================== CR1 ========================================================== */ +#define RTC_CR1_SOURCE_Pos (8UL) /*!< SOURCE (Bit 8) */ +#define RTC_CR1_SOURCE_Msk (0x700UL) /*!< SOURCE (Bitfield-Mask: 0x07) */ +#define RTC_CR1_WAIT_Pos (2UL) /*!< WAIT (Bit 2) */ +#define RTC_CR1_WAIT_Msk (0x4UL) /*!< WAIT (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define RTC_CR2_ALARMBEN_Pos (10UL) /*!< ALARMBEN (Bit 10) */ +#define RTC_CR2_ALARMBEN_Msk (0x400UL) /*!< ALARMBEN (Bitfield-Mask: 0x01) */ +#define RTC_CR2_ALARMAEN_Pos (9UL) /*!< ALARMAEN (Bit 9) */ +#define RTC_CR2_ALARMAEN_Msk (0x200UL) /*!< ALARMAEN (Bitfield-Mask: 0x01) */ +#define RTC_CR2_AWTEN_Pos (7UL) /*!< AWTEN (Bit 7) */ +#define RTC_CR2_AWTEN_Msk (0x80UL) /*!< AWTEN (Bitfield-Mask: 0x01) */ +#define RTC_CR2_TAMPEN_Pos (6UL) /*!< TAMPEN (Bit 6) */ +#define RTC_CR2_TAMPEN_Msk (0x40UL) /*!< TAMPEN (Bitfield-Mask: 0x01) */ +#define RTC_CR2_RTCOUT_Pos (4UL) /*!< RTCOUT (Bit 4) */ +#define RTC_CR2_RTCOUT_Msk (0x30UL) /*!< RTCOUT (Bitfield-Mask: 0x03) */ +#define RTC_CR2_TAMPEDGE_Pos (3UL) /*!< TAMPEDGE (Bit 3) */ +#define RTC_CR2_TAMPEDGE_Msk (0x8UL) /*!< TAMPEDGE (Bitfield-Mask: 0x01) */ +#define RTC_CR2_AWTSRC_Pos (2UL) /*!< AWTSRC (Bit 2) */ +#define RTC_CR2_AWTSRC_Msk (0x4UL) /*!< AWTSRC (Bitfield-Mask: 0x01) */ +#define RTC_CR2_AWTPRS_Pos (0UL) /*!< AWTPRS (Bit 0) */ +#define RTC_CR2_AWTPRS_Msk (0x3UL) /*!< AWTPRS (Bitfield-Mask: 0x03) */ +/* ========================================================== PSC ========================================================== */ +#define RTC_PSC_PSC1_Pos (20UL) /*!< PSC1 (Bit 20) */ +#define RTC_PSC_PSC1_Msk (0xff00000UL) /*!< PSC1 (Bitfield-Mask: 0xff) */ +#define RTC_PSC_PSC2_Pos (0UL) /*!< PSC2 (Bit 0) */ +#define RTC_PSC_PSC2_Msk (0xfffffUL) /*!< PSC2 (Bitfield-Mask: 0xfffff) */ +/* ========================================================= DATE ========================================================== */ +#define RTC_DATE_WEEK_Pos (24UL) /*!< WEEK (Bit 24) */ +#define RTC_DATE_WEEK_Msk (0x7000000UL) /*!< WEEK (Bitfield-Mask: 0x07) */ +#define RTC_DATE_YEAR_Pos (16UL) /*!< YEAR (Bit 16) */ +#define RTC_DATE_YEAR_Msk (0xff0000UL) /*!< YEAR (Bitfield-Mask: 0xff) */ +#define RTC_DATE_MONTH_Pos (8UL) /*!< MONTH (Bit 8) */ +#define RTC_DATE_MONTH_Msk (0x1f00UL) /*!< MONTH (Bitfield-Mask: 0x1f) */ +#define RTC_DATE_DAY_Pos (0UL) /*!< DAY (Bit 0) */ +#define RTC_DATE_DAY_Msk (0x3fUL) /*!< DAY (Bitfield-Mask: 0x3f) */ +/* ========================================================= TIME ========================================================== */ +#define RTC_TIME_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */ +#define RTC_TIME_HOUR_Msk (0x3f0000UL) /*!< HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_TIME_MINUTE_Pos (8UL) /*!< MINUTE (Bit 8) */ +#define RTC_TIME_MINUTE_Msk (0x7f00UL) /*!< MINUTE (Bitfield-Mask: 0x7f) */ +#define RTC_TIME_SECOND_Pos (0UL) /*!< SECOND (Bit 0) */ +#define RTC_TIME_SECOND_Msk (0x7fUL) /*!< SECOND (Bitfield-Mask: 0x7f) */ +/* ========================================================= SSCNT ========================================================= */ +#define RTC_SSCNT_SSCNT1_Pos (20UL) /*!< SSCNT1 (Bit 20) */ +#define RTC_SSCNT_SSCNT1_Msk (0x100000UL) /*!< SSCNT1 (Bitfield-Mask: 0x01) */ +#define RTC_SSCNT_SSCNT0_Pos (0UL) /*!< SSCNT0 (Bit 0) */ +#define RTC_SSCNT_SSCNT0_Msk (0xfffffUL) /*!< SSCNT0 (Bitfield-Mask: 0xfffff) */ +/* ======================================================== ALARMA ========================================================= */ +#define RTC_ALARMA_WEEKMASK_Pos (24UL) /*!< WEEKMASK (Bit 24) */ +#define RTC_ALARMA_WEEKMASK_Msk (0x7f000000UL) /*!< WEEKMASK (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMA_HOUREN_Pos (23UL) /*!< HOUREN (Bit 23) */ +#define RTC_ALARMA_HOUREN_Msk (0x800000UL) /*!< HOUREN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMA_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */ +#define RTC_ALARMA_HOUR_Msk (0x3f0000UL) /*!< HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_ALARMA_MINUTEEN_Pos (15UL) /*!< MINUTEEN (Bit 15) */ +#define RTC_ALARMA_MINUTEEN_Msk (0x8000UL) /*!< MINUTEEN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMA_MINUTE_Pos (8UL) /*!< MINUTE (Bit 8) */ +#define RTC_ALARMA_MINUTE_Msk (0x7f00UL) /*!< MINUTE (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMA_SECONDEN_Pos (7UL) /*!< SECONDEN (Bit 7) */ +#define RTC_ALARMA_SECONDEN_Msk (0x80UL) /*!< SECONDEN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMA_SECOND_Pos (0UL) /*!< SECOND (Bit 0) */ +#define RTC_ALARMA_SECOND_Msk (0x7fUL) /*!< SECOND (Bitfield-Mask: 0x7f) */ +/* ======================================================== ALARMB ========================================================= */ +#define RTC_ALARMB_WEEKMASK_Pos (24UL) /*!< WEEKMASK (Bit 24) */ +#define RTC_ALARMB_WEEKMASK_Msk (0x7f000000UL) /*!< WEEKMASK (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMB_HOUREN_Pos (23UL) /*!< HOUREN (Bit 23) */ +#define RTC_ALARMB_HOUREN_Msk (0x800000UL) /*!< HOUREN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMB_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */ +#define RTC_ALARMB_HOUR_Msk (0x3f0000UL) /*!< HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_ALARMB_MINUTEEN_Pos (15UL) /*!< MINUTEEN (Bit 15) */ +#define RTC_ALARMB_MINUTEEN_Msk (0x8000UL) /*!< MINUTEEN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMB_MINUTE_Pos (8UL) /*!< MINUTE (Bit 8) */ +#define RTC_ALARMB_MINUTE_Msk (0x7f00UL) /*!< MINUTE (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMB_SECONDEN_Pos (7UL) /*!< SECONDEN (Bit 7) */ +#define RTC_ALARMB_SECONDEN_Msk (0x80UL) /*!< SECONDEN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMB_SECOND_Pos (0UL) /*!< SECOND (Bit 0) */ +#define RTC_ALARMB_SECOND_Msk (0x7fUL) /*!< SECOND (Bitfield-Mask: 0x7f) */ +/* ======================================================= TAMPDATE ======================================================== */ +#define RTC_TAMPDATE_WEEK_Pos (13UL) /*!< WEEK (Bit 13) */ +#define RTC_TAMPDATE_WEEK_Msk (0xe000UL) /*!< WEEK (Bitfield-Mask: 0x07) */ +#define RTC_TAMPDATE_MONTH_Pos (8UL) /*!< MONTH (Bit 8) */ +#define RTC_TAMPDATE_MONTH_Msk (0x1f00UL) /*!< MONTH (Bitfield-Mask: 0x1f) */ +#define RTC_TAMPDATE_DAY_Pos (0UL) /*!< DAY (Bit 0) */ +#define RTC_TAMPDATE_DAY_Msk (0x3fUL) /*!< DAY (Bitfield-Mask: 0x3f) */ +/* ======================================================= TAMPTIME ======================================================== */ +#define RTC_TAMPTIME_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */ +#define RTC_TAMPTIME_HOUR_Msk (0x3f0000UL) /*!< HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_TAMPTIME_MINUTE_Pos (8UL) /*!< MINUTE (Bit 8) */ +#define RTC_TAMPTIME_MINUTE_Msk (0x7f00UL) /*!< MINUTE (Bitfield-Mask: 0x7f) */ +#define RTC_TAMPTIME_SECOND_Pos (0UL) /*!< SECOND (Bit 0) */ +#define RTC_TAMPTIME_SECOND_Msk (0x7fUL) /*!< SECOND (Bitfield-Mask: 0x7f) */ +/* ========================================================== IER ========================================================== */ +#define RTC_IER_INTERVAL_Pos (6UL) /*!< INTERVAL (Bit 6) */ +#define RTC_IER_INTERVAL_Msk (0x40UL) /*!< INTERVAL (Bitfield-Mask: 0x01) */ +#define RTC_IER_TAMPOV_Pos (4UL) /*!< TAMPOV (Bit 4) */ +#define RTC_IER_TAMPOV_Msk (0x10UL) /*!< TAMPOV (Bitfield-Mask: 0x01) */ +#define RTC_IER_TAMP_Pos (3UL) /*!< TAMP (Bit 3) */ +#define RTC_IER_TAMP_Msk (0x8UL) /*!< TAMP (Bitfield-Mask: 0x01) */ +#define RTC_IER_AWTIMER_Pos (2UL) /*!< AWTIMER (Bit 2) */ +#define RTC_IER_AWTIMER_Msk (0x4UL) /*!< AWTIMER (Bitfield-Mask: 0x01) */ +#define RTC_IER_ALARMB_Pos (1UL) /*!< ALARMB (Bit 1) */ +#define RTC_IER_ALARMB_Msk (0x2UL) /*!< ALARMB (Bitfield-Mask: 0x01) */ +#define RTC_IER_ALARMA_Pos (0UL) /*!< ALARMA (Bit 0) */ +#define RTC_IER_ALARMA_Msk (0x1UL) /*!< ALARMA (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define RTC_ISR_INTERVAL_Pos (6UL) /*!< INTERVAL (Bit 6) */ +#define RTC_ISR_INTERVAL_Msk (0x40UL) /*!< INTERVAL (Bitfield-Mask: 0x01) */ +#define RTC_ISR_TAMPOV_Pos (4UL) /*!< TAMPOV (Bit 4) */ +#define RTC_ISR_TAMPOV_Msk (0x10UL) /*!< TAMPOV (Bitfield-Mask: 0x01) */ +#define RTC_ISR_TAMP_Pos (3UL) /*!< TAMP (Bit 3) */ +#define RTC_ISR_TAMP_Msk (0x8UL) /*!< TAMP (Bitfield-Mask: 0x01) */ +#define RTC_ISR_AWTIMER_Pos (2UL) /*!< AWTIMER (Bit 2) */ +#define RTC_ISR_AWTIMER_Msk (0x4UL) /*!< AWTIMER (Bitfield-Mask: 0x01) */ +#define RTC_ISR_ALARMB_Pos (1UL) /*!< ALARMB (Bit 1) */ +#define RTC_ISR_ALARMB_Msk (0x2UL) /*!< ALARMB (Bitfield-Mask: 0x01) */ +#define RTC_ISR_ALARMA_Pos (0UL) /*!< ALARMA (Bit 0) */ +#define RTC_ISR_ALARMA_Msk (0x1UL) /*!< ALARMA (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define RTC_ICR_INTERVAL_Pos (6UL) /*!< INTERVAL (Bit 6) */ +#define RTC_ICR_INTERVAL_Msk (0x40UL) /*!< INTERVAL (Bitfield-Mask: 0x01) */ +#define RTC_ICR_TAMPOV_Pos (4UL) /*!< TAMPOV (Bit 4) */ +#define RTC_ICR_TAMPOV_Msk (0x10UL) /*!< TAMPOV (Bitfield-Mask: 0x01) */ +#define RTC_ICR_TAMP_Pos (3UL) /*!< TAMP (Bit 3) */ +#define RTC_ICR_TAMP_Msk (0x8UL) /*!< TAMP (Bitfield-Mask: 0x01) */ +#define RTC_ICR_AWTIMER_Pos (2UL) /*!< AWTIMER (Bit 2) */ +#define RTC_ICR_AWTIMER_Msk (0x4UL) /*!< AWTIMER (Bitfield-Mask: 0x01) */ +#define RTC_ICR_ALARMB_Pos (1UL) /*!< ALARMB (Bit 1) */ +#define RTC_ICR_ALARMB_Msk (0x2UL) /*!< ALARMB (Bitfield-Mask: 0x01) */ +#define RTC_ICR_ALARMA_Pos (0UL) /*!< ALARMA (Bit 0) */ +#define RTC_ICR_ALARMA_Msk (0x1UL) /*!< ALARMA (Bitfield-Mask: 0x01) */ +/* ======================================================== AWTARR ========================================================= */ +#define RTC_AWTARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define RTC_AWTARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ======================================================== AWTCNT ========================================================= */ +#define RTC_AWTCNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define RTC_AWTCNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= COMPCFR1 ======================================================== */ +#define RTC_COMPCFR1_EN_Pos (15UL) /*!< EN (Bit 15) */ +#define RTC_COMPCFR1_EN_Msk (0x8000UL) /*!< EN (Bitfield-Mask: 0x01) */ +#define RTC_COMPCFR1_SIGN_Pos (14UL) /*!< SIGN (Bit 14) */ +#define RTC_COMPCFR1_SIGN_Msk (0x4000UL) /*!< SIGN (Bitfield-Mask: 0x01) */ +#define RTC_COMPCFR1_PERIOD_Pos (12UL) /*!< PERIOD (Bit 12) */ +#define RTC_COMPCFR1_PERIOD_Msk (0x3000UL) /*!< PERIOD (Bitfield-Mask: 0x03) */ +#define RTC_COMPCFR1_COMP_Pos (0UL) /*!< COMP (Bit 0) */ +#define RTC_COMPCFR1_COMP_Msk (0xfffUL) /*!< COMP (Bitfield-Mask: 0xfff) */ + + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define SPIx_CR1_BR_Pos (24UL) /*!< BR (Bit 24) */ +#define SPIx_CR1_BR_Msk (0x7f000000UL) /*!< BR (Bitfield-Mask: 0x7f) */ +#define SPIx_CR1_SMP_Pos (20UL) /*!< SMP (Bit 20) */ +#define SPIx_CR1_SMP_Msk (0x100000UL) /*!< SMP (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_MISOHD_Pos (19UL) /*!< MISOHD (Bit 19) */ +#define SPIx_CR1_MISOHD_Msk (0x80000UL) /*!< MISOHD (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_FLTEN_Pos (18UL) /*!< FLTEN (Bit 18) */ +#define SPIx_CR1_FLTEN_Msk (0x40000UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_MODE_Pos (16UL) /*!< MODE (Bit 16) */ +#define SPIx_CR1_MODE_Msk (0x30000UL) /*!< MODE (Bitfield-Mask: 0x03) */ +#define SPIx_CR1_GAP_Pos (12UL) /*!< GAP (Bit 12) */ +#define SPIx_CR1_GAP_Msk (0xf000UL) /*!< GAP (Bitfield-Mask: 0x0f) */ +#define SPIx_CR1_WIDTH_Pos (8UL) /*!< WIDTH (Bit 8) */ +#define SPIx_CR1_WIDTH_Msk (0xf00UL) /*!< WIDTH (Bitfield-Mask: 0x0f) */ +#define SPIx_CR1_LSBF_Pos (7UL) /*!< LSBF (Bit 7) */ +#define SPIx_CR1_LSBF_Msk (0x80UL) /*!< LSBF (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_CPOL_Pos (3UL) /*!< CPOL (Bit 3) */ +#define SPIx_CR1_CPOL_Msk (0x8UL) /*!< CPOL (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_CPHA_Pos (2UL) /*!< CPHA (Bit 2) */ +#define SPIx_CR1_CPHA_Msk (0x4UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_SSM_Pos (1UL) /*!< SSM (Bit 1) */ +#define SPIx_CR1_SSM_Msk (0x2UL) /*!< SSM (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_MSTR_Pos (0UL) /*!< MSTR (Bit 0) */ +#define SPIx_CR1_MSTR_Msk (0x1UL) /*!< MSTR (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define SPIx_CR2_DMATX_Pos (2UL) /*!< DMATX (Bit 2) */ +#define SPIx_CR2_DMATX_Msk (0x4UL) /*!< DMATX (Bitfield-Mask: 0x01) */ +#define SPIx_CR2_DMARX_Pos (1UL) /*!< DMARX (Bit 1) */ +#define SPIx_CR2_DMARX_Msk (0x2UL) /*!< DMARX (Bitfield-Mask: 0x01) */ +#define SPIx_CR2_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define SPIx_CR2_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR3 ========================================================== */ +#define SPIx_CR3_HDOE_Pos (0UL) /*!< HDOE (Bit 0) */ +#define SPIx_CR3_HDOE_Msk (0x1UL) /*!< HDOE (Bitfield-Mask: 0x01) */ +/* ========================================================== SSI ========================================================== */ +#define SPIx_SSI_SSI_Pos (0UL) /*!< SSI (Bit 0) */ +#define SPIx_SSI_SSI_Msk (0x1UL) /*!< SSI (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define SPIx_IER_MODF_Pos (7UL) /*!< MODF (Bit 7) */ +#define SPIx_IER_MODF_Msk (0x80UL) /*!< MODF (Bitfield-Mask: 0x01) */ +#define SPIx_IER_SSERR_Pos (6UL) /*!< SSERR (Bit 6) */ +#define SPIx_IER_SSERR_Msk (0x40UL) /*!< SSERR (Bitfield-Mask: 0x01) */ +#define SPIx_IER_OV_Pos (5UL) /*!< OV (Bit 5) */ +#define SPIx_IER_OV_Msk (0x20UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define SPIx_IER_UD_Pos (4UL) /*!< UD (Bit 4) */ +#define SPIx_IER_UD_Msk (0x10UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define SPIx_IER_SSR_Pos (3UL) /*!< SSR (Bit 3) */ +#define SPIx_IER_SSR_Msk (0x8UL) /*!< SSR (Bitfield-Mask: 0x01) */ +#define SPIx_IER_SSF_Pos (2UL) /*!< SSF (Bit 2) */ +#define SPIx_IER_SSF_Msk (0x4UL) /*!< SSF (Bitfield-Mask: 0x01) */ +#define SPIx_IER_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define SPIx_IER_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define SPIx_IER_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define SPIx_IER_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define SPIx_ISR_SSLVL_Pos (9UL) /*!< SSLVL (Bit 9) */ +#define SPIx_ISR_SSLVL_Msk (0x200UL) /*!< SSLVL (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_BUSY_Pos (8UL) /*!< BUSY (Bit 8) */ +#define SPIx_ISR_BUSY_Msk (0x100UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_MODF_Pos (7UL) /*!< MODF (Bit 7) */ +#define SPIx_ISR_MODF_Msk (0x80UL) /*!< MODF (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_SSERR_Pos (6UL) /*!< SSERR (Bit 6) */ +#define SPIx_ISR_SSERR_Msk (0x40UL) /*!< SSERR (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_OV_Pos (5UL) /*!< OV (Bit 5) */ +#define SPIx_ISR_OV_Msk (0x20UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_UD_Pos (4UL) /*!< UD (Bit 4) */ +#define SPIx_ISR_UD_Msk (0x10UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_SSR_Pos (3UL) /*!< SSR (Bit 3) */ +#define SPIx_ISR_SSR_Msk (0x8UL) /*!< SSR (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_SSF_Pos (2UL) /*!< SSF (Bit 2) */ +#define SPIx_ISR_SSF_Msk (0x4UL) /*!< SSF (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define SPIx_ISR_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define SPIx_ISR_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define SPIx_ICR_MODF_Pos (7UL) /*!< MODF (Bit 7) */ +#define SPIx_ICR_MODF_Msk (0x80UL) /*!< MODF (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_SSERR_Pos (6UL) /*!< SSERR (Bit 6) */ +#define SPIx_ICR_SSERR_Msk (0x40UL) /*!< SSERR (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_OV_Pos (5UL) /*!< OV (Bit 5) */ +#define SPIx_ICR_OV_Msk (0x20UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_UD_Pos (4UL) /*!< UD (Bit 4) */ +#define SPIx_ICR_UD_Msk (0x10UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_SSR_Pos (3UL) /*!< SSR (Bit 3) */ +#define SPIx_ICR_SSR_Msk (0x8UL) /*!< SSR (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_SSF_Pos (2UL) /*!< SSF (Bit 2) */ +#define SPIx_ICR_SSF_Msk (0x4UL) /*!< SSF (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define SPIx_ICR_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_FLUSH_Pos (0UL) /*!< FLUSH (Bit 0) */ +#define SPIx_ICR_FLUSH_Msk (0x1UL) /*!< FLUSH (Bitfield-Mask: 0x01) */ +/* ========================================================== DR =========================================================== */ +#define SPIx_DR_DR_Pos (0UL) /*!< DR (Bit 0) */ +#define SPIx_DR_DR_Msk (0xffffUL) /*!< DR (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ SYSCTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define SYSCTRL_CR0_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_CR0_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_CR0_HCLKPRS_Pos (5UL) /*!< HCLKPRS (Bit 5) */ +#define SYSCTRL_CR0_HCLKPRS_Msk (0xe0UL) /*!< HCLKPRS (Bitfield-Mask: 0x07) */ +#define SYSCTRL_CR0_PCLKPRS_Pos (3UL) /*!< PCLKPRS (Bit 3) */ +#define SYSCTRL_CR0_PCLKPRS_Msk (0x18UL) /*!< PCLKPRS (Bitfield-Mask: 0x03) */ +#define SYSCTRL_CR0_SYSCLK_Pos (0UL) /*!< SYSCLK (Bit 0) */ +#define SYSCTRL_CR0_SYSCLK_Msk (0x7UL) /*!< SYSCLK (Bitfield-Mask: 0x07) */ +/* ========================================================== CR1 ========================================================== */ +#define SYSCTRL_CR1_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_CR1_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_CR1_CLKCCS_Pos (8UL) /*!< CLKCCS (Bit 8) */ +#define SYSCTRL_CR1_CLKCCS_Msk (0x100UL) /*!< CLKCCS (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_HSECCS_Pos (7UL) /*!< HSECCS (Bit 7) */ +#define SYSCTRL_CR1_HSECCS_Msk (0x80UL) /*!< HSECCS (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_LSECCS_Pos (6UL) /*!< LSECCS (Bit 6) */ +#define SYSCTRL_CR1_LSECCS_Msk (0x40UL) /*!< LSECCS (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_LSELOCK_Pos (5UL) /*!< LSELOCK (Bit 5) */ +#define SYSCTRL_CR1_LSELOCK_Msk (0x20UL) /*!< LSELOCK (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_LSEEN_Pos (4UL) /*!< LSEEN (Bit 4) */ +#define SYSCTRL_CR1_LSEEN_Msk (0x10UL) /*!< LSEEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_LSIEN_Pos (3UL) /*!< LSIEN (Bit 3) */ +#define SYSCTRL_CR1_LSIEN_Msk (0x8UL) /*!< LSIEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_PLLEN_Pos (2UL) /*!< PLLEN (Bit 2) */ +#define SYSCTRL_CR1_PLLEN_Msk (0x4UL) /*!< PLLEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_HSEEN_Pos (1UL) /*!< HSEEN (Bit 1) */ +#define SYSCTRL_CR1_HSEEN_Msk (0x2UL) /*!< HSEEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_HSIEN_Pos (0UL) /*!< HSIEN (Bit 0) */ +#define SYSCTRL_CR1_HSIEN_Msk (0x1UL) /*!< HSIEN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define SYSCTRL_CR2_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_CR2_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_CR2_RAMBRKEN_Pos (15UL) /*!< RAMBRKEN (Bit 15) */ +#define SYSCTRL_CR2_RAMBRKEN_Msk (0x8000UL) /*!< RAMBRKEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_LVDBRKEN_Pos (14UL) /*!< LVDBRKEN (Bit 14) */ +#define SYSCTRL_CR2_LVDBRKEN_Msk (0x4000UL) /*!< LVDBRKEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_DSBRKEN_Pos (13UL) /*!< DSBRKEN (Bit 13) */ +#define SYSCTRL_CR2_DSBRKEN_Msk (0x2000UL) /*!< DSBRKEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_CLLBRKEN_Pos (12UL) /*!< CLLBRKEN (Bit 12) */ +#define SYSCTRL_CR2_CLLBRKEN_Msk (0x1000UL) /*!< CLLBRKEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_LSEBRKEN_Pos (11UL) /*!< LSEBRKEN (Bit 11) */ +#define SYSCTRL_CR2_LSEBRKEN_Msk (0x800UL) /*!< LSEBRKEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_HSEBRKEN_Pos (10UL) /*!< HSEBRKEN (Bit 10) */ +#define SYSCTRL_CR2_HSEBRKEN_Msk (0x400UL) /*!< HSEBRKEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_FLASHWAIT_Pos (4UL) /*!< FLASHWAIT (Bit 4) */ +#define SYSCTRL_CR2_FLASHWAIT_Msk (0x70UL) /*!< FLASHWAIT (Bitfield-Mask: 0x07) */ +#define SYSCTRL_CR2_WAKEUPCLK_Pos (3UL) /*!< WAKEUPCLK (Bit 3) */ +#define SYSCTRL_CR2_WAKEUPCLK_Msk (0x8UL) /*!< WAKEUPCLK (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_LOCKUP_Pos (2UL) /*!< LOCKUP (Bit 2) */ +#define SYSCTRL_CR2_LOCKUP_Msk (0x4UL) /*!< LOCKUP (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_SWDIO_Pos (1UL) /*!< SWDIO (Bit 1) */ +#define SYSCTRL_CR2_SWDIO_Msk (0x2UL) /*!< SWDIO (Bitfield-Mask: 0x01) */ +/* ========================================================== HSI ========================================================== */ +#define SYSCTRL_HSI_STABLE_Pos (15UL) /*!< STABLE (Bit 15) */ +#define SYSCTRL_HSI_STABLE_Msk (0x8000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSI_DIV_Pos (11UL) /*!< DIV (Bit 11) */ +#define SYSCTRL_HSI_DIV_Msk (0x7800UL) /*!< DIV (Bitfield-Mask: 0x0f) */ +#define SYSCTRL_HSI_TRIM_Pos (0UL) /*!< TRIM (Bit 0) */ +#define SYSCTRL_HSI_TRIM_Msk (0x7ffUL) /*!< TRIM (Bitfield-Mask: 0x7ff) */ +/* ========================================================== LSI ========================================================== */ +#define SYSCTRL_LSI_STABLE_Pos (15UL) /*!< STABLE (Bit 15) */ +#define SYSCTRL_LSI_STABLE_Msk (0x8000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_LSI_WAITCYCLE_Pos (10UL) /*!< WAITCYCLE (Bit 10) */ +#define SYSCTRL_LSI_WAITCYCLE_Msk (0xc00UL) /*!< WAITCYCLE (Bitfield-Mask: 0x03) */ +#define SYSCTRL_LSI_TRIM_Pos (0UL) /*!< TRIM (Bit 0) */ +#define SYSCTRL_LSI_TRIM_Msk (0x1ffUL) /*!< TRIM (Bitfield-Mask: 0x1ff) */ +/* ========================================================== HSE ========================================================== */ +#define SYSCTRL_HSE_DIGFLT_Pos (24UL) /*!< DIGFLT (Bit 24) */ +#define SYSCTRL_HSE_DIGFLT_Msk (0x1000000UL) /*!< DIGFLT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSE_PDRIVER_Pos (20UL) /*!< PDRIVER (Bit 20) */ +#define SYSCTRL_HSE_PDRIVER_Msk (0xf00000UL) /*!< PDRIVER (Bitfield-Mask: 0x0f) */ +#define SYSCTRL_HSE_STABLE_Pos (19UL) /*!< STABLE (Bit 19) */ +#define SYSCTRL_HSE_STABLE_Msk (0x80000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSE_DETCNT_Pos (8UL) /*!< DETCNT (Bit 8) */ +#define SYSCTRL_HSE_DETCNT_Msk (0x7ff00UL) /*!< DETCNT (Bitfield-Mask: 0x7ff) */ +#define SYSCTRL_HSE_HEXENPOL_Pos (7UL) /*!< HEXENPOL (Bit 7) */ +#define SYSCTRL_HSE_HEXENPOL_Msk (0x80UL) /*!< HEXENPOL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSE_MODE_Pos (6UL) /*!< MODE (Bit 6) */ +#define SYSCTRL_HSE_MODE_Msk (0x40UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSE_WAITCYCLE_Pos (4UL) /*!< WAITCYCLE (Bit 4) */ +#define SYSCTRL_HSE_WAITCYCLE_Msk (0x30UL) /*!< WAITCYCLE (Bitfield-Mask: 0x03) */ +#define SYSCTRL_HSE_DRIVER_Pos (0UL) /*!< DRIVER (Bit 0) */ +#define SYSCTRL_HSE_DRIVER_Msk (0xfUL) /*!< DRIVER (Bitfield-Mask: 0x0f) */ +/* ========================================================== LSE ========================================================== */ +#define SYSCTRL_LSE_STABLE_Pos (18UL) /*!< STABLE (Bit 18) */ +#define SYSCTRL_LSE_STABLE_Msk (0x40000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_LSE_PINLOCK_Pos (17UL) /*!< PINLOCK (Bit 17) */ +#define SYSCTRL_LSE_PINLOCK_Msk (0x20000UL) /*!< PINLOCK (Bitfield-Mask: 0x01) */ +#define SYSCTRL_LSE_PDRIVER_Pos (8UL) /*!< PDRIVER (Bit 8) */ +#define SYSCTRL_LSE_PDRIVER_Msk (0xf00UL) /*!< PDRIVER (Bitfield-Mask: 0x0f) */ +#define SYSCTRL_LSE_MODE_Pos (6UL) /*!< MODE (Bit 6) */ +#define SYSCTRL_LSE_MODE_Msk (0x40UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_LSE_WAITCYCLE_Pos (4UL) /*!< WAITCYCLE (Bit 4) */ +#define SYSCTRL_LSE_WAITCYCLE_Msk (0x30UL) /*!< WAITCYCLE (Bitfield-Mask: 0x03) */ +#define SYSCTRL_LSE_DRIVER_Pos (0UL) /*!< DRIVER (Bit 0) */ +#define SYSCTRL_LSE_DRIVER_Msk (0xfUL) /*!< DRIVER (Bitfield-Mask: 0x0f) */ +/* ========================================================== IER ========================================================== */ +#define SYSCTRL_IER_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_IER_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_IER_HSEFAULT_Pos (8UL) /*!< HSEFAULT (Bit 8) */ +#define SYSCTRL_IER_HSEFAULT_Msk (0x100UL) /*!< HSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_LSEFAULT_Pos (7UL) /*!< LSEFAULT (Bit 7) */ +#define SYSCTRL_IER_LSEFAULT_Msk (0x80UL) /*!< LSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_HSEFAIL_Pos (6UL) /*!< HSEFAIL (Bit 6) */ +#define SYSCTRL_IER_HSEFAIL_Msk (0x40UL) /*!< HSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_LSEFAIL_Pos (5UL) /*!< LSEFAIL (Bit 5) */ +#define SYSCTRL_IER_LSEFAIL_Msk (0x20UL) /*!< LSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_LSERDY_Pos (4UL) /*!< LSERDY (Bit 4) */ +#define SYSCTRL_IER_LSERDY_Msk (0x10UL) /*!< LSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_LSIRDY_Pos (3UL) /*!< LSIRDY (Bit 3) */ +#define SYSCTRL_IER_LSIRDY_Msk (0x8UL) /*!< LSIRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_PLLRDY_Pos (2UL) /*!< PLLRDY (Bit 2) */ +#define SYSCTRL_IER_PLLRDY_Msk (0x4UL) /*!< PLLRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_HSERDY_Pos (1UL) /*!< HSERDY (Bit 1) */ +#define SYSCTRL_IER_HSERDY_Msk (0x2UL) /*!< HSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_HSIRDY_Pos (0UL) /*!< HSIRDY (Bit 0) */ +#define SYSCTRL_IER_HSIRDY_Msk (0x1UL) /*!< HSIRDY (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define SYSCTRL_ISR_LSESTABLE_Pos (15UL) /*!< LSESTABLE (Bit 15) */ +#define SYSCTRL_ISR_LSESTABLE_Msk (0x8000UL) /*!< LSESTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSISTABLE_Pos (14UL) /*!< LSISTABLE (Bit 14) */ +#define SYSCTRL_ISR_LSISTABLE_Msk (0x4000UL) /*!< LSISTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_PLLSTABLE_Pos (13UL) /*!< PLLSTABLE (Bit 13) */ +#define SYSCTRL_ISR_PLLSTABLE_Msk (0x2000UL) /*!< PLLSTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSESTABLE_Pos (12UL) /*!< HSESTABLE (Bit 12) */ +#define SYSCTRL_ISR_HSESTABLE_Msk (0x1000UL) /*!< HSESTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSISTABLE_Pos (11UL) /*!< HSISTABLE (Bit 11) */ +#define SYSCTRL_ISR_HSISTABLE_Msk (0x800UL) /*!< HSISTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSEFAULT_Pos (8UL) /*!< HSEFAULT (Bit 8) */ +#define SYSCTRL_ISR_HSEFAULT_Msk (0x100UL) /*!< HSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSEFAULT_Pos (7UL) /*!< LSEFAULT (Bit 7) */ +#define SYSCTRL_ISR_LSEFAULT_Msk (0x80UL) /*!< LSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSEFAIL_Pos (6UL) /*!< HSEFAIL (Bit 6) */ +#define SYSCTRL_ISR_HSEFAIL_Msk (0x40UL) /*!< HSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSEFAIL_Pos (5UL) /*!< LSEFAIL (Bit 5) */ +#define SYSCTRL_ISR_LSEFAIL_Msk (0x20UL) /*!< LSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSERDY_Pos (4UL) /*!< LSERDY (Bit 4) */ +#define SYSCTRL_ISR_LSERDY_Msk (0x10UL) /*!< LSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSIRDY_Pos (3UL) /*!< LSIRDY (Bit 3) */ +#define SYSCTRL_ISR_LSIRDY_Msk (0x8UL) /*!< LSIRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_PLLRDY_Pos (2UL) /*!< PLLRDY (Bit 2) */ +#define SYSCTRL_ISR_PLLRDY_Msk (0x4UL) /*!< PLLRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSERDY_Pos (1UL) /*!< HSERDY (Bit 1) */ +#define SYSCTRL_ISR_HSERDY_Msk (0x2UL) /*!< HSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSIRDY_Pos (0UL) /*!< HSIRDY (Bit 0) */ +#define SYSCTRL_ISR_HSIRDY_Msk (0x1UL) /*!< HSIRDY (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define SYSCTRL_ICR_HSEFAULT_Pos (8UL) /*!< HSEFAULT (Bit 8) */ +#define SYSCTRL_ICR_HSEFAULT_Msk (0x100UL) /*!< HSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_LSEFAULT_Pos (7UL) /*!< LSEFAULT (Bit 7) */ +#define SYSCTRL_ICR_LSEFAULT_Msk (0x80UL) /*!< LSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_HSEFAIL_Pos (6UL) /*!< HSEFAIL (Bit 6) */ +#define SYSCTRL_ICR_HSEFAIL_Msk (0x40UL) /*!< HSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_LSEFAIL_Pos (5UL) /*!< LSEFAIL (Bit 5) */ +#define SYSCTRL_ICR_LSEFAIL_Msk (0x20UL) /*!< LSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_LSERDY_Pos (4UL) /*!< LSERDY (Bit 4) */ +#define SYSCTRL_ICR_LSERDY_Msk (0x10UL) /*!< LSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_LSIRDY_Pos (3UL) /*!< LSIRDY (Bit 3) */ +#define SYSCTRL_ICR_LSIRDY_Msk (0x8UL) /*!< LSIRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_PLLRDY_Pos (2UL) /*!< PLLRDY (Bit 2) */ +#define SYSCTRL_ICR_PLLRDY_Msk (0x4UL) /*!< PLLRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_HSERDY_Pos (1UL) /*!< HSERDY (Bit 1) */ +#define SYSCTRL_ICR_HSERDY_Msk (0x2UL) /*!< HSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_HSIRDY_Pos (0UL) /*!< HSIRDY (Bit 0) */ +#define SYSCTRL_ICR_HSIRDY_Msk (0x1UL) /*!< HSIRDY (Bitfield-Mask: 0x01) */ +/* ========================================================= AHBEN ========================================================= */ +#define SYSCTRL_AHBEN_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_AHBEN_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_AHBEN_CORDIC_Pos (8UL) /*!< CORDIC (Bit 8) */ +#define SYSCTRL_AHBEN_CORDIC_Msk (0x100UL) /*!< CORDIC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_GPIOF_Pos (7UL) /*!< GPIOF (Bit 7) */ +#define SYSCTRL_AHBEN_GPIOF_Msk (0x80UL) /*!< GPIOF (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_GPIOC_Pos (6UL) /*!< GPIOC (Bit 6) */ +#define SYSCTRL_AHBEN_GPIOC_Msk (0x40UL) /*!< GPIOC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_GPIOB_Pos (5UL) /*!< GPIOB (Bit 5) */ +#define SYSCTRL_AHBEN_GPIOB_Msk (0x20UL) /*!< GPIOB (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_GPIOA_Pos (4UL) /*!< GPIOA (Bit 4) */ +#define SYSCTRL_AHBEN_GPIOA_Msk (0x10UL) /*!< GPIOA (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_EAU_Pos (3UL) /*!< EAU (Bit 3) */ +#define SYSCTRL_AHBEN_EAU_Msk (0x8UL) /*!< EAU (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_CRC_Pos (2UL) /*!< CRC (Bit 2) */ +#define SYSCTRL_AHBEN_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_FLASH_Pos (1UL) /*!< FLASH (Bit 1) */ +#define SYSCTRL_AHBEN_FLASH_Msk (0x2UL) /*!< FLASH (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_DMA_Pos (0UL) /*!< DMA (Bit 0) */ +#define SYSCTRL_AHBEN_DMA_Msk (0x1UL) /*!< DMA (Bitfield-Mask: 0x01) */ +/* ======================================================== APBEN1 ========================================================= */ +#define SYSCTRL_APBEN1_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_APBEN1_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_APBEN1_SPI3_Pos (14UL) /*!< SPI3 (Bit 14) */ +#define SYSCTRL_APBEN1_SPI3_Msk (0x4000UL) /*!< SPI3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_SPI2_Pos (13UL) /*!< SPI2 (Bit 13) */ +#define SYSCTRL_APBEN1_SPI2_Msk (0x2000UL) /*!< SPI2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_GTIM4_Pos (12UL) /*!< GTIM4 (Bit 12) */ +#define SYSCTRL_APBEN1_GTIM4_Msk (0x1000UL) /*!< GTIM4 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_GTIM3_Pos (11UL) /*!< GTIM3 (Bit 11) */ +#define SYSCTRL_APBEN1_GTIM3_Msk (0x800UL) /*!< GTIM3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_UART3_Pos (8UL) /*!< UART3 (Bit 8) */ +#define SYSCTRL_APBEN1_UART3_Msk (0x100UL) /*!< UART3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_GTIM2_Pos (7UL) /*!< GTIM2 (Bit 7) */ +#define SYSCTRL_APBEN1_GTIM2_Msk (0x80UL) /*!< GTIM2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_GTIM1_Pos (6UL) /*!< GTIM1 (Bit 6) */ +#define SYSCTRL_APBEN1_GTIM1_Msk (0x40UL) /*!< GTIM1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_ATIM_Pos (5UL) /*!< ATIM (Bit 5) */ +#define SYSCTRL_APBEN1_ATIM_Msk (0x20UL) /*!< ATIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_UART2_Pos (4UL) /*!< UART2 (Bit 4) */ +#define SYSCTRL_APBEN1_UART2_Msk (0x10UL) /*!< UART2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_UART1_Pos (3UL) /*!< UART1 (Bit 3) */ +#define SYSCTRL_APBEN1_UART1_Msk (0x8UL) /*!< UART1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_SPI1_Pos (2UL) /*!< SPI1 (Bit 2) */ +#define SYSCTRL_APBEN1_SPI1_Msk (0x4UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_VC_Pos (1UL) /*!< VC (Bit 1) */ +#define SYSCTRL_APBEN1_VC_Msk (0x2UL) /*!< VC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_ADC_Pos (0UL) /*!< ADC (Bit 0) */ +#define SYSCTRL_APBEN1_ADC_Msk (0x1UL) /*!< ADC (Bitfield-Mask: 0x01) */ +/* ======================================================== APBEN2 ========================================================= */ +#define SYSCTRL_APBEN2_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_APBEN2_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_APBEN2_HALLTIM_Pos (12UL) /*!< HALLTIM (Bit 12) */ +#define SYSCTRL_APBEN2_HALLTIM_Msk (0x1000UL) /*!< HALLTIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_I2C2_Pos (11UL) /*!< I2C2 (Bit 11) */ +#define SYSCTRL_APBEN2_I2C2_Msk (0x800UL) /*!< I2C2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_DAC_Pos (10UL) /*!< DAC (Bit 10) */ +#define SYSCTRL_APBEN2_DAC_Msk (0x400UL) /*!< DAC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_OPA_Pos (9UL) /*!< OPA (Bit 9) */ +#define SYSCTRL_APBEN2_OPA_Msk (0x200UL) /*!< OPA (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_LPTIM_Pos (7UL) /*!< LPTIM (Bit 7) */ +#define SYSCTRL_APBEN2_LPTIM_Msk (0x80UL) /*!< LPTIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_I2C1_Pos (6UL) /*!< I2C1 (Bit 6) */ +#define SYSCTRL_APBEN2_I2C1_Msk (0x40UL) /*!< I2C1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_WWDT_Pos (5UL) /*!< WWDT (Bit 5) */ +#define SYSCTRL_APBEN2_WWDT_Msk (0x20UL) /*!< WWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_IWDT_Pos (4UL) /*!< IWDT (Bit 4) */ +#define SYSCTRL_APBEN2_IWDT_Msk (0x10UL) /*!< IWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_BTIM123_Pos (2UL) /*!< BTIM123 (Bit 2) */ +#define SYSCTRL_APBEN2_BTIM123_Msk (0x4UL) /*!< BTIM123 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_RTC_Pos (1UL) /*!< RTC (Bit 1) */ +#define SYSCTRL_APBEN2_RTC_Msk (0x2UL) /*!< RTC (Bitfield-Mask: 0x01) */ +/* ======================================================== AHBRST ========================================================= */ +#define SYSCTRL_AHBRST_CORDIC_Pos (8UL) /*!< CORDIC (Bit 8) */ +#define SYSCTRL_AHBRST_CORDIC_Msk (0x100UL) /*!< CORDIC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_GPIOF_Pos (7UL) /*!< GPIOF (Bit 7) */ +#define SYSCTRL_AHBRST_GPIOF_Msk (0x80UL) /*!< GPIOF (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_GPIOC_Pos (6UL) /*!< GPIOC (Bit 6) */ +#define SYSCTRL_AHBRST_GPIOC_Msk (0x40UL) /*!< GPIOC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_GPIOB_Pos (5UL) /*!< GPIOB (Bit 5) */ +#define SYSCTRL_AHBRST_GPIOB_Msk (0x20UL) /*!< GPIOB (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_GPIOA_Pos (4UL) /*!< GPIOA (Bit 4) */ +#define SYSCTRL_AHBRST_GPIOA_Msk (0x10UL) /*!< GPIOA (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_EAU_Pos (3UL) /*!< EAU (Bit 3) */ +#define SYSCTRL_AHBRST_EAU_Msk (0x8UL) /*!< EAU (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_CRC_Pos (2UL) /*!< CRC (Bit 2) */ +#define SYSCTRL_AHBRST_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_FLASH_Pos (1UL) /*!< FLASH (Bit 1) */ +#define SYSCTRL_AHBRST_FLASH_Msk (0x2UL) /*!< FLASH (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_DMA_Pos (0UL) /*!< DMA (Bit 0) */ +#define SYSCTRL_AHBRST_DMA_Msk (0x1UL) /*!< DMA (Bitfield-Mask: 0x01) */ +/* ======================================================== APBRST1 ======================================================== */ +#define SYSCTRL_APBRST1_SPI3_Pos (14UL) /*!< SPI3 (Bit 14) */ +#define SYSCTRL_APBRST1_SPI3_Msk (0x4000UL) /*!< SPI3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_SPI2_Pos (13UL) /*!< SPI2 (Bit 13) */ +#define SYSCTRL_APBRST1_SPI2_Msk (0x2000UL) /*!< SPI2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_GTIM4_Pos (12UL) /*!< GTIM4 (Bit 12) */ +#define SYSCTRL_APBRST1_GTIM4_Msk (0x1000UL) /*!< GTIM4 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_GTIM3_Pos (11UL) /*!< GTIM3 (Bit 11) */ +#define SYSCTRL_APBRST1_GTIM3_Msk (0x800UL) /*!< GTIM3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_UART3_Pos (8UL) /*!< UART3 (Bit 8) */ +#define SYSCTRL_APBRST1_UART3_Msk (0x100UL) /*!< UART3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_GTIM2_Pos (7UL) /*!< GTIM2 (Bit 7) */ +#define SYSCTRL_APBRST1_GTIM2_Msk (0x80UL) /*!< GTIM2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_GTIM1_Pos (6UL) /*!< GTIM1 (Bit 6) */ +#define SYSCTRL_APBRST1_GTIM1_Msk (0x40UL) /*!< GTIM1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_ATIM_Pos (5UL) /*!< ATIM (Bit 5) */ +#define SYSCTRL_APBRST1_ATIM_Msk (0x20UL) /*!< ATIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_UART2_Pos (4UL) /*!< UART2 (Bit 4) */ +#define SYSCTRL_APBRST1_UART2_Msk (0x10UL) /*!< UART2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_UART1_Pos (3UL) /*!< UART1 (Bit 3) */ +#define SYSCTRL_APBRST1_UART1_Msk (0x8UL) /*!< UART1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_SPI1_Pos (2UL) /*!< SPI1 (Bit 2) */ +#define SYSCTRL_APBRST1_SPI1_Msk (0x4UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_VC_Pos (1UL) /*!< VC (Bit 1) */ +#define SYSCTRL_APBRST1_VC_Msk (0x2UL) /*!< VC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_ADC_Pos (0UL) /*!< ADC (Bit 0) */ +#define SYSCTRL_APBRST1_ADC_Msk (0x1UL) /*!< ADC (Bitfield-Mask: 0x01) */ +/* ======================================================== APBRST2 ======================================================== */ +#define SYSCTRL_APBRST2_HALLTIM_Pos (12UL) /*!< HALLTIM (Bit 12) */ +#define SYSCTRL_APBRST2_HALLTIM_Msk (0x1000UL) /*!< HALLTIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_I2C2_Pos (11UL) /*!< I2C2 (Bit 11) */ +#define SYSCTRL_APBRST2_I2C2_Msk (0x800UL) /*!< I2C2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_DAC_Pos (10UL) /*!< DAC (Bit 10) */ +#define SYSCTRL_APBRST2_DAC_Msk (0x400UL) /*!< DAC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_OPA_Pos (9UL) /*!< OPA (Bit 9) */ +#define SYSCTRL_APBRST2_OPA_Msk (0x200UL) /*!< OPA (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_LPTIM_Pos (7UL) /*!< LPTIM (Bit 7) */ +#define SYSCTRL_APBRST2_LPTIM_Msk (0x80UL) /*!< LPTIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_I2C1_Pos (6UL) /*!< I2C1 (Bit 6) */ +#define SYSCTRL_APBRST2_I2C1_Msk (0x40UL) /*!< I2C1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_WWDT_Pos (5UL) /*!< WWDT (Bit 5) */ +#define SYSCTRL_APBRST2_WWDT_Msk (0x20UL) /*!< WWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_IWDT_Pos (4UL) /*!< IWDT (Bit 4) */ +#define SYSCTRL_APBRST2_IWDT_Msk (0x10UL) /*!< IWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_BTIM123_Pos (2UL) /*!< BTIM123 (Bit 2) */ +#define SYSCTRL_APBRST2_BTIM123_Msk (0x4UL) /*!< BTIM123 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_RTC_Pos (1UL) /*!< RTC (Bit 1) */ +#define SYSCTRL_APBRST2_RTC_Msk (0x2UL) /*!< RTC (Bitfield-Mask: 0x01) */ +/* ======================================================= RESETFLAG ======================================================= */ +#define SYSCTRL_RESETFLAG_SYSRESETREQ_Pos (9UL) /*!< SYSRESETREQ (Bit 9) */ +#define SYSCTRL_RESETFLAG_SYSRESETREQ_Msk (0x200UL) /*!< SYSRESETREQ (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_LOCKUP_Pos (8UL) /*!< LOCKUP (Bit 8) */ +#define SYSCTRL_RESETFLAG_LOCKUP_Msk (0x100UL) /*!< LOCKUP (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_RSTB_Pos (6UL) /*!< RSTB (Bit 6) */ +#define SYSCTRL_RESETFLAG_RSTB_Msk (0x40UL) /*!< RSTB (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_WWDT_Pos (5UL) /*!< WWDT (Bit 5) */ +#define SYSCTRL_RESETFLAG_WWDT_Msk (0x20UL) /*!< WWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_IWDT_Pos (4UL) /*!< IWDT (Bit 4) */ +#define SYSCTRL_RESETFLAG_IWDT_Msk (0x10UL) /*!< IWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_LVD_Pos (3UL) /*!< LVD (Bit 3) */ +#define SYSCTRL_RESETFLAG_LVD_Msk (0x8UL) /*!< LVD (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_POR_Pos (0UL) /*!< POR (Bit 0) */ +#define SYSCTRL_RESETFLAG_POR_Msk (0x1UL) /*!< POR (Bitfield-Mask: 0x01) */ +/* ========================================================= DEBUG ========================================================= */ +#define SYSCTRL_DEBUG_HALLTIM_Pos (11UL) /*!< HALLTIM (Bit 11) */ +#define SYSCTRL_DEBUG_HALLTIM_Msk (0x800UL) /*!< HALLTIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_WWDT_Pos (10UL) /*!< WWDT (Bit 10) */ +#define SYSCTRL_DEBUG_WWDT_Msk (0x400UL) /*!< WWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_IWDT_Pos (9UL) /*!< IWDT (Bit 9) */ +#define SYSCTRL_DEBUG_IWDT_Msk (0x200UL) /*!< IWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_RTC_Pos (8UL) /*!< RTC (Bit 8) */ +#define SYSCTRL_DEBUG_RTC_Msk (0x100UL) /*!< RTC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_LPTIM_Pos (6UL) /*!< LPTIM (Bit 6) */ +#define SYSCTRL_DEBUG_LPTIM_Msk (0x40UL) /*!< LPTIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_BTIM123_Pos (5UL) /*!< BTIM123 (Bit 5) */ +#define SYSCTRL_DEBUG_BTIM123_Msk (0x20UL) /*!< BTIM123 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_GTIM4_Pos (4UL) /*!< GTIM4 (Bit 4) */ +#define SYSCTRL_DEBUG_GTIM4_Msk (0x10UL) /*!< GTIM4 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_GTIM3_Pos (3UL) /*!< GTIM3 (Bit 3) */ +#define SYSCTRL_DEBUG_GTIM3_Msk (0x8UL) /*!< GTIM3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_GTIM2_Pos (2UL) /*!< GTIM2 (Bit 2) */ +#define SYSCTRL_DEBUG_GTIM2_Msk (0x4UL) /*!< GTIM2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_GTIM1_Pos (1UL) /*!< GTIM1 (Bit 1) */ +#define SYSCTRL_DEBUG_GTIM1_Msk (0x2UL) /*!< GTIM1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_ATIM_Pos (0UL) /*!< ATIM (Bit 0) */ +#define SYSCTRL_DEBUG_ATIM_Msk (0x1UL) /*!< ATIM (Bitfield-Mask: 0x01) */ +/* ========================================================== MCO ========================================================== */ +#define SYSCTRL_MCO_DIV_Pos (4UL) /*!< DIV (Bit 4) */ +#define SYSCTRL_MCO_DIV_Msk (0xf0UL) /*!< DIV (Bitfield-Mask: 0x0f) */ +#define SYSCTRL_MCO_SOURCE_Pos (0UL) /*!< SOURCE (Bit 0) */ +#define SYSCTRL_MCO_SOURCE_Msk (0xfUL) /*!< SOURCE (Bitfield-Mask: 0x0f) */ +/* ========================================================== PLL ========================================================== */ +#define SYSCTRL_PLL_STABLE_Pos (16UL) /*!< STABLE (Bit 16) */ +#define SYSCTRL_PLL_STABLE_Msk (0x10000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_PLL_MUL_Pos (8UL) /*!< MUL (Bit 8) */ +#define SYSCTRL_PLL_MUL_Msk (0xff00UL) /*!< MUL (Bitfield-Mask: 0xff) */ +#define SYSCTRL_PLL_WAITCYCLE_Pos (5UL) /*!< WAITCYCLE (Bit 5) */ +#define SYSCTRL_PLL_WAITCYCLE_Msk (0xe0UL) /*!< WAITCYCLE (Bitfield-Mask: 0x07) */ +#define SYSCTRL_PLL_DIV_Pos (1UL) /*!< DIV (Bit 1) */ +#define SYSCTRL_PLL_DIV_Msk (0x1eUL) /*!< DIV (Bitfield-Mask: 0x0f) */ +#define SYSCTRL_PLL_SOURCE_Pos (0UL) /*!< SOURCE (Bit 0) */ +#define SYSCTRL_PLL_SOURCE_Msk (0x1UL) /*!< SOURCE (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ VC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define VCx_CR0_INP_Pos (12UL) /*!< INP (Bit 12) */ +#define VCx_CR0_INP_Msk (0x3000UL) /*!< INP (Bitfield-Mask: 0x03) */ +#define VCx_CR0_INN_Pos (8UL) /*!< INN (Bit 8) */ +#define VCx_CR0_INN_Msk (0x300UL) /*!< INN (Bitfield-Mask: 0x03) */ +#define VCx_CR0_WINDOW_Pos (7UL) /*!< WINDOW (Bit 7) */ +#define VCx_CR0_WINDOW_Msk (0x80UL) /*!< WINDOW (Bitfield-Mask: 0x01) */ +#define VCx_CR0_POL_Pos (6UL) /*!< POL (Bit 6) */ +#define VCx_CR0_POL_Msk (0x40UL) /*!< POL (Bitfield-Mask: 0x01) */ +#define VCx_CR0_IE_Pos (5UL) /*!< IE (Bit 5) */ +#define VCx_CR0_IE_Msk (0x20UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define VCx_CR0_HYS_Pos (3UL) /*!< HYS (Bit 3) */ +#define VCx_CR0_HYS_Msk (0x8UL) /*!< HYS (Bitfield-Mask: 0x01) */ +#define VCx_CR0_RESP_Pos (1UL) /*!< RESP (Bit 1) */ +#define VCx_CR0_RESP_Msk (0x2UL) /*!< RESP (Bitfield-Mask: 0x01) */ +#define VCx_CR0_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define VCx_CR0_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ +#define VCx_CR1_BLANKLVL_Pos (11UL) /*!< BLANKLVL (Bit 11) */ +#define VCx_CR1_BLANKLVL_Msk (0x800UL) /*!< BLANKLVL (Bitfield-Mask: 0x01) */ +#define VCx_CR1_BLANKTIME_Pos (8UL) /*!< BLANKTIME (Bit 8) */ +#define VCx_CR1_BLANKTIME_Msk (0x700UL) /*!< BLANKTIME (Bitfield-Mask: 0x07) */ +#define VCx_CR1_HIGHIE_Pos (7UL) /*!< HIGHIE (Bit 7) */ +#define VCx_CR1_HIGHIE_Msk (0x80UL) /*!< HIGHIE (Bitfield-Mask: 0x01) */ +#define VCx_CR1_RISEIE_Pos (6UL) /*!< RISEIE (Bit 6) */ +#define VCx_CR1_RISEIE_Msk (0x40UL) /*!< RISEIE (Bitfield-Mask: 0x01) */ +#define VCx_CR1_FALLIE_Pos (5UL) /*!< FALLIE (Bit 5) */ +#define VCx_CR1_FALLIE_Msk (0x20UL) /*!< FALLIE (Bitfield-Mask: 0x01) */ +#define VCx_CR1_FLTCLK_Pos (4UL) /*!< FLTCLK (Bit 4) */ +#define VCx_CR1_FLTCLK_Msk (0x10UL) /*!< FLTCLK (Bitfield-Mask: 0x01) */ +#define VCx_CR1_FLTTIME_Pos (0UL) /*!< FLTTIME (Bit 0) */ +#define VCx_CR1_FLTTIME_Msk (0xfUL) /*!< FLTTIME (Bitfield-Mask: 0x0f) */ +/* ========================================================== CR2 ========================================================== */ +#define VCx_CR2_HALLTIM1TRGO_Pos (31UL) /*!< HALLTIM1TRGO (Bit 31) */ +#define VCx_CR2_HALLTIM1TRGO_Msk (0x80000000UL) /*!< HALLTIM1TRGO (Bitfield-Mask: 0x01) */ +#define VCx_CR2_BTIM3TRGO_Pos (30UL) /*!< BTIM3TRGO (Bit 30) */ +#define VCx_CR2_BTIM3TRGO_Msk (0x40000000UL) /*!< BTIM3TRGO (Bitfield-Mask: 0x01) */ +#define VCx_CR2_BTIM2TRGO_Pos (29UL) /*!< BTIM2TRGO (Bit 29) */ +#define VCx_CR2_BTIM2TRGO_Msk (0x20000000UL) /*!< BTIM2TRGO (Bitfield-Mask: 0x01) */ +#define VCx_CR2_BTIM1TRGO_Pos (28UL) /*!< BTIM1TRGO (Bit 28) */ +#define VCx_CR2_BTIM1TRGO_Msk (0x10000000UL) /*!< BTIM1TRGO (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM4OC4REFC_Pos (27UL) /*!< GTIM4OC4REFC (Bit 27) */ +#define VCx_CR2_GTIM4OC4REFC_Msk (0x8000000UL) /*!< GTIM4OC4REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM4OC3REFC_Pos (26UL) /*!< GTIM4OC3REFC (Bit 26) */ +#define VCx_CR2_GTIM4OC3REFC_Msk (0x4000000UL) /*!< GTIM4OC3REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM4OC2REFC_Pos (25UL) /*!< GTIM4OC2REFC (Bit 25) */ +#define VCx_CR2_GTIM4OC2REFC_Msk (0x2000000UL) /*!< GTIM4OC2REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM4OC1REFC_Pos (24UL) /*!< GTIM4OC1REFC (Bit 24) */ +#define VCx_CR2_GTIM4OC1REFC_Msk (0x1000000UL) /*!< GTIM4OC1REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM4TRGO_Pos (23UL) /*!< GTIM4TRGO (Bit 23) */ +#define VCx_CR2_GTIM4TRGO_Msk (0x800000UL) /*!< GTIM4TRGO (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM3OC4REFC_Pos (22UL) /*!< GTIM3OC4REFC (Bit 22) */ +#define VCx_CR2_GTIM3OC4REFC_Msk (0x400000UL) /*!< GTIM3OC4REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM3OC3REFC_Pos (21UL) /*!< GTIM3OC3REFC (Bit 21) */ +#define VCx_CR2_GTIM3OC3REFC_Msk (0x200000UL) /*!< GTIM3OC3REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM3OC2REFC_Pos (20UL) /*!< GTIM3OC2REFC (Bit 20) */ +#define VCx_CR2_GTIM3OC2REFC_Msk (0x100000UL) /*!< GTIM3OC2REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM3OC1REFC_Pos (19UL) /*!< GTIM3OC1REFC (Bit 19) */ +#define VCx_CR2_GTIM3OC1REFC_Msk (0x80000UL) /*!< GTIM3OC1REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM3TRGO_Pos (18UL) /*!< GTIM3TRGO (Bit 18) */ +#define VCx_CR2_GTIM3TRGO_Msk (0x40000UL) /*!< GTIM3TRGO (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM2OC4REFC_Pos (17UL) /*!< GTIM2OC4REFC (Bit 17) */ +#define VCx_CR2_GTIM2OC4REFC_Msk (0x20000UL) /*!< GTIM2OC4REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM2OC3REFC_Pos (16UL) /*!< GTIM2OC3REFC (Bit 16) */ +#define VCx_CR2_GTIM2OC3REFC_Msk (0x10000UL) /*!< GTIM2OC3REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM2OC2REFC_Pos (15UL) /*!< GTIM2OC2REFC (Bit 15) */ +#define VCx_CR2_GTIM2OC2REFC_Msk (0x8000UL) /*!< GTIM2OC2REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM2OC1REFC_Pos (14UL) /*!< GTIM2OC1REFC (Bit 14) */ +#define VCx_CR2_GTIM2OC1REFC_Msk (0x4000UL) /*!< GTIM2OC1REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM2TRGO_Pos (13UL) /*!< GTIM2TRGO (Bit 13) */ +#define VCx_CR2_GTIM2TRGO_Msk (0x2000UL) /*!< GTIM2TRGO (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM1OC4REFC_Pos (12UL) /*!< GTIM1OC4REFC (Bit 12) */ +#define VCx_CR2_GTIM1OC4REFC_Msk (0x1000UL) /*!< GTIM1OC4REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM1OC3REFC_Pos (11UL) /*!< GTIM1OC3REFC (Bit 11) */ +#define VCx_CR2_GTIM1OC3REFC_Msk (0x800UL) /*!< GTIM1OC3REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM1OC2REFC_Pos (10UL) /*!< GTIM1OC2REFC (Bit 10) */ +#define VCx_CR2_GTIM1OC2REFC_Msk (0x400UL) /*!< GTIM1OC2REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM1OC1REFC_Pos (9UL) /*!< GTIM1OC1REFC (Bit 9) */ +#define VCx_CR2_GTIM1OC1REFC_Msk (0x200UL) /*!< GTIM1OC1REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM1TRGO_Pos (8UL) /*!< GTIM1TRGO (Bit 8) */ +#define VCx_CR2_GTIM1TRGO_Msk (0x100UL) /*!< GTIM1TRGO (Bitfield-Mask: 0x01) */ +#define VCx_CR2_ATIMOC6REFC_Pos (7UL) /*!< ATIM1OC6REFC (Bit 7) */ +#define VCx_CR2_ATIMOC6REFC_Msk (0x80UL) /*!< ATIM1OC6REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_ATIMOC5REFC_Pos (6UL) /*!< ATIM1OC5REFC (Bit 6) */ +#define VCx_CR2_ATIMOC5REFC_Msk (0x40UL) /*!< ATIM1OC5REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_ATIMOC4REFC_Pos (5UL) /*!< ATIM1OC4REFC (Bit 5) */ +#define VCx_CR2_ATIMOC4REFC_Msk (0x20UL) /*!< ATIM1OC4REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_ATIMOC3REFC_Pos (4UL) /*!< ATIM1OC3REFC (Bit 4) */ +#define VCx_CR2_ATIMOC3REFC_Msk (0x10UL) /*!< ATIM1OC3REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_ATIMOC2REFC_Pos (3UL) /*!< ATIM1OC2REFC (Bit 3) */ +#define VCx_CR2_ATIMOC2REFC_Msk (0x8UL) /*!< ATIM1OC2REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_ATIMOC1REFC_Pos (2UL) /*!< ATIM1OC1REFC (Bit 2) */ +#define VCx_CR2_ATIMOC1REFC_Msk (0x4UL) /*!< ATIM1OC1REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_ATIMTRGO2_Pos (1UL) /*!< ATIM1TRGO2 (Bit 1) */ +#define VCx_CR2_ATIMTRGO2_Msk (0x2UL) /*!< ATIM1TRGO2 (Bitfield-Mask: 0x01) */ +#define VCx_CR2_ATIMTRGO_Pos (0UL) /*!< ATIM1TRGO (Bit 0) */ +#define VCx_CR2_ATIMTRGO_Msk (0x1UL) /*!< ATIM1TRGO (Bitfield-Mask: 0x01) */ +/* ========================================================== SR =========================================================== */ +#define VCx_SR_FLTV_Pos (1UL) /*!< FLTV (Bit 1) */ +#define VCx_SR_FLTV_Msk (0x2UL) /*!< FLTV (Bitfield-Mask: 0x01) */ +#define VCx_SR_INTF_Pos (0UL) /*!< INTF (Bit 0) */ +#define VCx_SR_INTF_Msk (0x1UL) /*!< INTF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ VCREF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DIV ========================================================== */ +#define VC12REF_DIV_VIN_Pos (5UL) /*!< VIN (Bit 5) */ +#define VC12REF_DIV_VIN_Msk (0x20UL) /*!< VIN (Bitfield-Mask: 0x01) */ +#define VC12REF_DIV_EN_Pos (4UL) /*!< EN (Bit 4) */ +#define VC12REF_DIV_EN_Msk (0x10UL) /*!< EN (Bitfield-Mask: 0x01) */ +#define VC12REF_DIV_DIV_Pos (0UL) /*!< DIV (Bit 0) */ +#define VC12REF_DIV_DIV_Msk (0x7UL) /*!< DIV (Bitfield-Mask: 0x07) */ + + +/* =========================================================================================================================== */ +/* ================ WWDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define WWDT_CR0_EN_Pos (7UL) /*!< EN (Bit 7) */ +#define WWDT_CR0_EN_Msk (0x80UL) /*!< EN (Bitfield-Mask: 0x01) */ +#define WWDT_CR0_WCNT_Pos (0UL) /*!< WCNT (Bit 0) */ +#define WWDT_CR0_WCNT_Msk (0x7fUL) /*!< WCNT (Bitfield-Mask: 0x7f) */ +/* ========================================================== CR1 ========================================================== */ +#define WWDT_CR1_IE_Pos (10UL) /*!< IE (Bit 10) */ +#define WWDT_CR1_IE_Msk (0x400UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define WWDT_CR1_PRS_Pos (7UL) /*!< PRS (Bit 7) */ +#define WWDT_CR1_PRS_Msk (0x380UL) /*!< PRS (Bitfield-Mask: 0x07) */ +#define WWDT_CR1_WINR_Pos (0UL) /*!< WINR (Bit 0) */ +#define WWDT_CR1_WINR_Msk (0x7fUL) /*!< WINR (Bitfield-Mask: 0x7f) */ +/* ========================================================== SR =========================================================== */ +#define WWDT_SR_POV_Pos (0UL) /*!< POV (Bit 0) */ +#define WWDT_SR_POV_Msk (0x1UL) /*!< POV (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CW32L012_H */ + + +/** @} */ /* End of group cw32l012 */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/Application/main.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/Application/main.c new file mode 100644 index 0000000..8bc59ba --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/Application/main.c @@ -0,0 +1,101 @@ +/******************************************************************************/ +/** \file main.c + ** + ** A detailed description is available at + ** @link Sample Group Some description @endlink + ** + ** - 2021-03-12 1.0 xiebin First version for Device Driver Library of Module. + ** + ******************************************************************************/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "cw32l012.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') * + ******************************************************************************/ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +void Delay(uint16_t nCount); +/** + ****************************************************************************** + ** \brief Main function of project + ** + ** \return uint32_t return value, if needed + ** + ** LED1闪烁 + ** + ******************************************************************************/ +int32_t main(void) +{ + CW_SYSCTRL->AHBEN |= 0x5A5A0000 | SYSCTRL_AHBEN_GPIOB_Msk ; + + CW_GPIOB->ANALOG_f.PIN8 = 0; // Set PB8 as Digital + CW_GPIOB->DIR_f.PIN8 = 0; // Set PB8 output + CW_GPIOB->OPENDRAIN_f.PIN8 = 0; // Set PB8 Push-Pull + + while (1) + { + CW_GPIOB->TOG_f.PIN8 = 1; // Toggle + + Delay(0xFFFF); + } +} + +/** + * @brief 循环延时 + * + * @param nCount + */ +void Delay(__IO uint16_t nCount) +{ + /* Decrement nCount value */ + while (nCount != 0) + { + nCount--; + } +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/Blinking_LED.ewp b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/Blinking_LED.ewp new file mode 100644 index 0000000..986b9e4 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/Blinking_LED.ewp @@ -0,0 +1,2218 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + Application + + $PROJ_DIR$\Application\main.c + + + + CMSIS + + $PROJ_DIR$\CMSIS\startup_cw32l012.s + + + $PROJ_DIR$\CMSIS\system_cw32l012.c + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/Blinking_LED.eww b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/Blinking_LED.eww new file mode 100644 index 0000000..b96fac7 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/Blinking_LED.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\Blinking_LED.ewp + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/CMSIS/base_types.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/CMSIS/base_types.h new file mode 100644 index 0000000..b3aebad --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/CMSIS/base_types.h @@ -0,0 +1,145 @@ + +#ifndef __BASE_TYPES_H +#define __BASE_TYPES_H + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include +#include +#include + + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +#ifndef TRUE + /** Value is true (boolean_t type) */ + #define TRUE ((boolean_t) 1u) +#endif + +#ifndef FALSE + /** Value is false (boolean_t type) */ + #define FALSE ((boolean_t) 0u) +#endif + +/** Returns the minimum value out of two values */ +#define MINIMUM( X, Y ) ((X) < (Y) ? (X) : (Y)) + +/** Returns the maximum value out of two values */ +#define MAXIMUM( X, Y ) ((X) > (Y) ? (X) : (Y)) + +/** Returns the dimension of an array */ +#define ARRAY_SZ( X ) (sizeof(X) / sizeof((X)[0])) + +#ifdef __DEBUG_ASSERT + #define ASSERT(x) do{ assert((x)> 0u) ; }while(0); +#else + #define ASSERT(x) {} +#endif +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** logical datatype (only values are TRUE and FALSE) */ +typedef uint8_t boolean_t; + +/** single precision floating point number (4 byte) */ +typedef float float32_t; + +/** double precision floating point number (8 byte) */ +typedef double float64_t; + +/** ASCII character for string generation (8 bit) */ +typedef char char_t; + +/** function pointer type to void/void function */ +typedef void (*func_ptr_t)(void); + +/** function pointer type to void/uint8_t function */ +typedef void (*func_ptr_arg1_t)(uint8_t u8Param); + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + + + +#define bv(n) ((uint32_t)1u << (n)) + +#define bv0 (((uint32_t)1u) << 0) +#define bv1 (((uint32_t)1u) << 1) +#define bv2 (((uint32_t)1u) << 2) +#define bv3 (((uint32_t)1u) << 3) +#define bv4 (((uint32_t)1u) << 4) +#define bv5 (((uint32_t)1u) << 5) +#define bv6 (((uint32_t)1u) << 6) +#define bv7 (((uint32_t)1u) << 7) +#define bv8 (((uint32_t)1u) << 8) +#define bv9 (((uint32_t)1u) << 9) +#define bv10 (((uint32_t)1u) << 10) +#define bv11 (((uint32_t)1u) << 11) +#define bv12 (((uint32_t)1u) << 12) +#define bv13 (((uint32_t)1u) << 13) +#define bv14 (((uint32_t)1u) << 14) +#define bv15 (((uint32_t)1u) << 15) +#define bv16 (((uint32_t)1u) << 16) +#define bv17 (((uint32_t)1u) << 17) +#define bv18 (((uint32_t)1u) << 18) +#define bv19 (((uint32_t)1u) << 19) +#define bv20 (((uint32_t)1u) << 20) +#define bv21 (((uint32_t)1u) << 21) +#define bv22 (((uint32_t)1u) << 22) +#define bv23 (((uint32_t)1u) << 23) +#define bv24 (((uint32_t)1u) << 24) +#define bv25 (((uint32_t)1u) << 25) +#define bv26 (((uint32_t)1u) << 26) +#define bv27 (((uint32_t)1u) << 27) +#define bv28 (((uint32_t)1u) << 28) +#define bv29 (((uint32_t)1u) << 29) +#define bv30 (((uint32_t)1u) << 30) +#define bv31 (((uint32_t)1u) << 31) + +#define REGBITS_SET( Reg , Mask ) ( (Reg) |= (Mask) ) +#define REGBITS_CLR( Reg , Mask ) ( (Reg) &= (~((uint32_t)(Mask))) ) +#define REGBITS_GET( Reg , Mask ) ( (Reg) & (Mask) ) +#define REGBITS_MODIFY( Reg , Mask , Value ) ( (Reg) = ((Reg) & (~(uint32_t)(Mask))) | (Value) ) + +/* Exported macro ------------------------------------------------------------*/ +#define USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT + /** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) + /* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +#endif /* __BASE_TYPES_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/CMSIS/startup_cw32l012.s b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/CMSIS/startup_cw32l012.s new file mode 100644 index 0000000..8dc1807 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/CMSIS/startup_cw32l012.s @@ -0,0 +1,307 @@ + +;/*****************************************************************************/ +;/* Startup for IAR */ +;/* Version V1.0 */ +;/* Date 2021-02-24 */ +;/* Target-mcu M0+ Device */ +;/*****************************************************************************/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + SECTION .intvec:CODE:ROOT(8) + DATA +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset + DCD NMI_Handler ; NMI + DCD HardFault_Handler ; Hard Fault + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV + DCD SysTick_Handler ; SysTick + +; Numbered IRQ handler vectors + +; Note: renaming to device dependent ISR function names are done in + + DCD WDT_IRQHandler + DCD LVD_IRQHandler + DCD RTC_IRQHandler + DCD FLASHRAM_IRQHandler + DCD SYSCTRL_IRQHandler + DCD GPIOA_IRQHandler + DCD GPIOB_IRQHandler + DCD GPIOC_IRQHandler + DCD GPIOF_IRQHandler + DCD DMACH12_IRQHandler + DCD DMACH34_IRQHandler + DCD CORDIC_IRQHandler + DCD ADC1_IRQHandler + DCD ATIM_IRQHandler + DCD VC13_IRQHandler + DCD VC24_IRQHandler + DCD GTIM1_IRQHandler + DCD GTIM2_IRQHandler + DCD GTIM34_IRQHandler + DCD LPTIM_IRQHandle + DCD BTIM1_IRQHandler + DCD BTIM2_IRQHandler + DCD BTIM3_HALLTIM_IRQHandler + DCD I2C1_IRQHandler + DCD I2C2_IRQHandler + DCD SPI1_IRQHandler + DCD SPI23_IRQHandler + DCD UART1_IRQHandler + DCD UART2_IRQHandler + DCD UART3_IRQHandler + DCD ADC2_DAC_IRQHandler + DCD CLKFAULT_IRQHandler + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R1, =0x0 + LDR R0, [R1] + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WDT_IRQHandler + B WDT_IRQHandler + + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK FLASHRAM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASHRAM_IRQHandler + B FLASHRAM_IRQHandler + + + PUBWEAK SYSCTRL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SYSCTRL_IRQHandler + B SYSCTRL_IRQHandler + + + PUBWEAK GPIOA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOA_IRQHandler + B GPIOA_IRQHandler + + + PUBWEAK GPIOB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOB_IRQHandler + B GPIOB_IRQHandler + + + PUBWEAK GPIOC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOC_IRQHandler + B GPIOC_IRQHandler + + + PUBWEAK GPIOF_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOF_IRQHandler + B GPIOF_IRQHandler + + + PUBWEAK DMACH12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMACH12_IRQHandler + B DMACH12_IRQHandler + + + PUBWEAK DMACH34_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMACH34_IRQHandler + B DMACH34_IRQHandler + + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + + PUBWEAK ATIM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ATIM_IRQHandler + B ATIM_IRQHandler + + + PUBWEAK VC13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +VC13_IRQHandler + B VC13_IRQHandler + + + PUBWEAK VC24_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +VC24_IRQHandler + B VC24_IRQHandler + + + PUBWEAK GTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GTIM1_IRQHandler + B GTIM1_IRQHandler + + + PUBWEAK GTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GTIM2_IRQHandler + B GTIM2_IRQHandler + + + PUBWEAK GTIM34_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GTIM34_IRQHandler + B GTIM34_IRQHandler + + + PUBWEAK LPTIM_IRQHandle + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM_IRQHandle + B LPTIM_IRQHandle + + + PUBWEAK BTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BTIM1_IRQHandler + B BTIM1_IRQHandler + + + PUBWEAK BTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BTIM2_IRQHandler + B BTIM2_IRQHandler + + + PUBWEAK BTIM3_HALLTIM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BTIM3_HALLTIM_IRQHandler + B BTIM3_HALLTIM_IRQHandler + + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI23_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI23_IRQHandler + B SPI23_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK ADC2_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC2_DAC_IRQHandler + B ADC2_DAC_IRQHandler + + + PUBWEAK CLKFAULT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CLKFAULT_IRQHandler + B CLKFAULT_IRQHandler + + END diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/CMSIS/system_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/CMSIS/system_cw32l012.c new file mode 100644 index 0000000..eb2516a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/CMSIS/system_cw32l012.c @@ -0,0 +1,75 @@ +/****************************************************************************** +* Include files * +******************************************************************************/ +#include "system_cw32l012.h" + +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS 0x20000000U /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS 0x00000000U /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +/****************************************************************************** + ** System Clock Frequency (Core Clock) Variable according CMSIS + ******************************************************************************/ + +uint32_t SystemCoreClock = 4000000; + +void SystemCoreClockUpdate(void) // Update SystemCoreClock variable +{ + SystemCoreClock = 4000000; +} + +/** + ****************************************************************************** + ** \brief Setup the microcontroller system. Initialize the System and update + ** the SystemCoreClock variable. + ** + ** \param none + ** \return none + ******************************************************************************/ +void SystemInit(void) +{ +/* Configure the Vector Table location add offset address ------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + + //Load TrimCode in this. + CW_SYSCTRL->HSI_f.TRIM = *((volatile uint16_t *)SYSCTRL_HSI_TRIMCODEADDR); + CW_SYSCTRL->LSI_f.TRIM = *((volatile uint16_t *)SYSCTRL_LSI_TRIMCODEADDR); + if (CW_SYSCTRL->HSI_f.TRIM == 0x7FF) + { + CW_SYSCTRL->HSI_f.TRIM = 0x77A; + } + if (CW_SYSCTRL->LSI_f.TRIM == 0x1FF) + { + CW_SYSCTRL->LSI_f.TRIM= 0x0059; + } + + SystemCoreClockUpdate(); + + //Init Hide thing. + //... +} + +void FirmwareDelay(uint32_t DlyCnt) +{ + volatile uint32_t thisCnt = DlyCnt; + while( thisCnt-- ) + { + ; + } +} diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/CMSIS/system_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/CMSIS/system_cw32l012.h new file mode 100644 index 0000000..bec303e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/arm/inc/examples/WHXY/CW32L012/CW32L012C8T6_StartKit/Blinking_LED/CMSIS/system_cw32l012.h @@ -0,0 +1,84 @@ +/** + ****************************************************************************** + * @file system_cw32l012.h + * @author WHXY Application Team + * @brief + ****************************************************************************** + */ + +#ifndef __SYSTEM_CW32l012_H +#define __SYSTEM_CW32l012_H + +#define SYSCTRL_HSI_TRIMCODEADDR (0x001007C0U) // +#define SYSCTRL_LSI_TRIMCODEADDR (0x001007C2U) // + +#ifdef __cplusplus +extern "C" { +#endif +/** @addtogroup Includes + * @{ + */ + +#include "cw32l012.h" +#include "base_types.h" +/** + * @} + */ + +/** @addtogroup Exported_Variables + * @{ + */ +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) + +/** + * @} + */ + +/** @addtogroup Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup Exported_Macros + * @{ + */ +#define HWWD_DISABLE (1) +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u +/** + * @} + */ + +/** @addtogroup Exported_Functions + * @{ + */ + +extern void SystemInit (void); // Initialize the system +extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable +extern void FirmwareDelay(uint32_t DlyCnt); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_CW32l010_H__ */ + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/startup_cw32l012.s b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/startup_cw32l012.s new file mode 100644 index 0000000..8dc1807 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/EWARM/startup_cw32l012.s @@ -0,0 +1,307 @@ + +;/*****************************************************************************/ +;/* Startup for IAR */ +;/* Version V1.0 */ +;/* Date 2021-02-24 */ +;/* Target-mcu M0+ Device */ +;/*****************************************************************************/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + SECTION .intvec:CODE:ROOT(8) + DATA +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset + DCD NMI_Handler ; NMI + DCD HardFault_Handler ; Hard Fault + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV + DCD SysTick_Handler ; SysTick + +; Numbered IRQ handler vectors + +; Note: renaming to device dependent ISR function names are done in + + DCD WDT_IRQHandler + DCD LVD_IRQHandler + DCD RTC_IRQHandler + DCD FLASHRAM_IRQHandler + DCD SYSCTRL_IRQHandler + DCD GPIOA_IRQHandler + DCD GPIOB_IRQHandler + DCD GPIOC_IRQHandler + DCD GPIOF_IRQHandler + DCD DMACH12_IRQHandler + DCD DMACH34_IRQHandler + DCD CORDIC_IRQHandler + DCD ADC1_IRQHandler + DCD ATIM_IRQHandler + DCD VC13_IRQHandler + DCD VC24_IRQHandler + DCD GTIM1_IRQHandler + DCD GTIM2_IRQHandler + DCD GTIM34_IRQHandler + DCD LPTIM_IRQHandle + DCD BTIM1_IRQHandler + DCD BTIM2_IRQHandler + DCD BTIM3_HALLTIM_IRQHandler + DCD I2C1_IRQHandler + DCD I2C2_IRQHandler + DCD SPI1_IRQHandler + DCD SPI23_IRQHandler + DCD UART1_IRQHandler + DCD UART2_IRQHandler + DCD UART3_IRQHandler + DCD ADC2_DAC_IRQHandler + DCD CLKFAULT_IRQHandler + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R1, =0x0 + LDR R0, [R1] + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WDT_IRQHandler + B WDT_IRQHandler + + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK FLASHRAM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASHRAM_IRQHandler + B FLASHRAM_IRQHandler + + + PUBWEAK SYSCTRL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SYSCTRL_IRQHandler + B SYSCTRL_IRQHandler + + + PUBWEAK GPIOA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOA_IRQHandler + B GPIOA_IRQHandler + + + PUBWEAK GPIOB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOB_IRQHandler + B GPIOB_IRQHandler + + + PUBWEAK GPIOC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOC_IRQHandler + B GPIOC_IRQHandler + + + PUBWEAK GPIOF_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOF_IRQHandler + B GPIOF_IRQHandler + + + PUBWEAK DMACH12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMACH12_IRQHandler + B DMACH12_IRQHandler + + + PUBWEAK DMACH34_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMACH34_IRQHandler + B DMACH34_IRQHandler + + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + + PUBWEAK ATIM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ATIM_IRQHandler + B ATIM_IRQHandler + + + PUBWEAK VC13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +VC13_IRQHandler + B VC13_IRQHandler + + + PUBWEAK VC24_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +VC24_IRQHandler + B VC24_IRQHandler + + + PUBWEAK GTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GTIM1_IRQHandler + B GTIM1_IRQHandler + + + PUBWEAK GTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GTIM2_IRQHandler + B GTIM2_IRQHandler + + + PUBWEAK GTIM34_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GTIM34_IRQHandler + B GTIM34_IRQHandler + + + PUBWEAK LPTIM_IRQHandle + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM_IRQHandle + B LPTIM_IRQHandle + + + PUBWEAK BTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BTIM1_IRQHandler + B BTIM1_IRQHandler + + + PUBWEAK BTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BTIM2_IRQHandler + B BTIM2_IRQHandler + + + PUBWEAK BTIM3_HALLTIM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BTIM3_HALLTIM_IRQHandler + B BTIM3_HALLTIM_IRQHandler + + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI23_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI23_IRQHandler + B SPI23_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK ADC2_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC2_DAC_IRQHandler + B ADC2_DAC_IRQHandler + + + PUBWEAK CLKFAULT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CLKFAULT_IRQHandler + B CLKFAULT_IRQHandler + + END diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/MDK/WHXY.CW32L012_DFP.1.0.2.pack b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/MDK/WHXY.CW32L012_DFP.1.0.2.pack new file mode 100644 index 0000000..85e076d Binary files /dev/null and b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/MDK/WHXY.CW32L012_DFP.1.0.2.pack differ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/MDK/startup_cw32l012.s b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/MDK/startup_cw32l012.s new file mode 100644 index 0000000..998b955 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/IDEsupport/MDK/startup_cw32l012.s @@ -0,0 +1,245 @@ + +;/*****************************************************************************/ +;/* Startup for ARM */ +;/* Version V1.0 */ +;/* Date 2024-02-26 */ +;/* Target-mcu {MCU_PN_H} */ +;/*****************************************************************************/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors + DCD __initial_sp ; Top of Stack + DCD Reset_Handler ;< -15 Reset Vector, invoked on Power up and warm reset + DCD NMI_Handler ;< -14 Non maskable Interrupt, cannot be stopped or preempted + DCD HardFault_Handler ;< -13 Hard Fault, all classes of Fault + DCD 0 ;< -12 Reserved + DCD 0 ;< -11 Reserved + DCD 0 ;< -10 Reserved + DCD 0 ;< -9 Reserved + DCD 0 ;< -8 Reserved + DCD 0 ;< -7 Reserved + DCD 0 ;< -6 Reserved + DCD SVC_Handler ;< -5 System Service Call via SVC instruction + DCD 0 ;< -4 Reserved + DCD 0 ;< -3 Reserved + DCD PendSV_Handler ;< -2 Pendable request for system service + DCD SysTick_Handler ;< -1 System Tick Timer + + DCD WDT_IRQHandler ;< 0 Watch Dog Timer Interrupt Handler + DCD LVD_IRQHandler ;< 1 Low Voltage Detect Interrupt Handler + DCD RTC_IRQHandler ;< 2 RTC Interrupt Handler + DCD FLASHRAM_IRQHandler ;< 3 Flash/RAM Interrupt Handler + DCD SYSCTRL_IRQHandler ;< 4 SysCtrl Interupt Handler + DCD GPIOA_IRQHandler ;< 5 GPIOA Interrupt Handler + DCD GPIOB_IRQHandler ;< 6 GPIOB Interrupt Handler + DCD GPIOC_IRQHandler ;< 7 GPIOC Interrupt Handler + DCD GPIOF_IRQHandler ;< 8 GPIOF Interrupt Handler + DCD DMACH12_IRQHandler ;< 9 DMA CH1 and CH2 Interrupt Handler + DCD DMACH34_IRQHandler ;< 10 DMA CH3 and CH4 Interrupt Handler + DCD CORDIC_IRQHandler ;< 11 CORDIC Interrupt Handler + DCD ADC1_IRQHandler ;< 12 ADC1 Interrupt Handler + DCD ATIM_IRQHandler ;< 13 Advanced Timer Interrupt Handler + DCD VC13_IRQHandler ;< 14 Voltage Comparator 1 and Comparator 3 Interrupt Handler + DCD VC24_IRQHandler ;< 15 Voltage Comparator 2 and Comparator 4 Interrupt Handler + DCD GTIM1_IRQHandler ;< 16 General Timer1 Interrupt Handler + DCD GTIM2_IRQHandler ;< 17 General Timer2 Interrupt Handler + DCD GTIM34_IRQHandler ;< 18 General Timer3 and General Timer4 Interrupt Handler + DCD LPTIM_IRQHandler ;< 19 LPTIM Interrupt Handle + DCD BTIM1_IRQHandler ;< 20 BTIM1 Interrupt Handler + DCD BTIM2_IRQHandler ;< 21 BTIM2 Interrupt Handler + DCD BTIM3_HALLTIM_IRQHandler ;< 22 BTIM3 and Hall timer Interrupt Handler + DCD I2C1_IRQHandler ;< 23 I2C1 Interrupt Handler + DCD I2C2_IRQHandler ;< 24 I2C2 Interrupt Handler + DCD SPI1_IRQHandler ;< 25 SPI1 Interrupt Handler + DCD SPI23_IRQHandler ;< 26 SPI2 and SPI3 Interrupt Handler + DCD UART1_IRQHandler ;< 27 UART1 Interrupt Handler + DCD UART2_IRQHandler ;< 28 UART2 Interrupt Handler + DCD UART3_IRQHandler ;< 29 UART3 Interrupt Handler + DCD ADC2_DAC_IRQHandler ;< 30 ADC2 and DAC Interrupt Handler + DCD CLKFAULT_IRQHandler ;< 31 CLKFAULT Interrupt Handler + + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R1, =0x0 + LDR R0, [R1] + MOV SP, R0 + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + + +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT WDT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASHRAM_IRQHandler [WEAK] + EXPORT SYSCTRL_IRQHandler [WEAK] + EXPORT GPIOA_IRQHandler [WEAK] + EXPORT GPIOB_IRQHandler [WEAK] + EXPORT GPIOC_IRQHandler [WEAK] + EXPORT GPIOF_IRQHandler [WEAK] + EXPORT DMACH12_IRQHandler [WEAK] + EXPORT DMACH34_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT ATIM_IRQHandler [WEAK] + EXPORT VC13_IRQHandler [WEAK] + EXPORT VC24_IRQHandler [WEAK] + EXPORT GTIM1_IRQHandler [WEAK] + EXPORT GTIM2_IRQHandler [WEAK] + EXPORT GTIM34_IRQHandler [WEAK] + EXPORT LPTIM_IRQHandler [WEAK] + EXPORT BTIM1_IRQHandler [WEAK] + EXPORT BTIM2_IRQHandler [WEAK] + EXPORT BTIM3_HALLTIM_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI23_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT ADC2_DAC_IRQHandler [WEAK] + EXPORT CLKFAULT_IRQHandler [WEAK] + +WDT_IRQHandler +LVD_IRQHandler +RTC_IRQHandler +FLASHRAM_IRQHandler +SYSCTRL_IRQHandler +GPIOA_IRQHandler +GPIOB_IRQHandler +GPIOC_IRQHandler +GPIOF_IRQHandler +DMACH12_IRQHandler +DMACH34_IRQHandler +CORDIC_IRQHandler +ADC1_IRQHandler +ATIM_IRQHandler +VC13_IRQHandler +VC24_IRQHandler +GTIM1_IRQHandler +GTIM2_IRQHandler +GTIM34_IRQHandler +LPTIM_IRQHandler +BTIM1_IRQHandler +BTIM2_IRQHandler +BTIM3_HALLTIM_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI23_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +ADC2_DAC_IRQHandler +CLKFAULT_IRQHandler + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/base_types.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/base_types.h new file mode 100644 index 0000000..b3aebad --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/base_types.h @@ -0,0 +1,145 @@ + +#ifndef __BASE_TYPES_H +#define __BASE_TYPES_H + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include +#include +#include + + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +#ifndef TRUE + /** Value is true (boolean_t type) */ + #define TRUE ((boolean_t) 1u) +#endif + +#ifndef FALSE + /** Value is false (boolean_t type) */ + #define FALSE ((boolean_t) 0u) +#endif + +/** Returns the minimum value out of two values */ +#define MINIMUM( X, Y ) ((X) < (Y) ? (X) : (Y)) + +/** Returns the maximum value out of two values */ +#define MAXIMUM( X, Y ) ((X) > (Y) ? (X) : (Y)) + +/** Returns the dimension of an array */ +#define ARRAY_SZ( X ) (sizeof(X) / sizeof((X)[0])) + +#ifdef __DEBUG_ASSERT + #define ASSERT(x) do{ assert((x)> 0u) ; }while(0); +#else + #define ASSERT(x) {} +#endif +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** logical datatype (only values are TRUE and FALSE) */ +typedef uint8_t boolean_t; + +/** single precision floating point number (4 byte) */ +typedef float float32_t; + +/** double precision floating point number (8 byte) */ +typedef double float64_t; + +/** ASCII character for string generation (8 bit) */ +typedef char char_t; + +/** function pointer type to void/void function */ +typedef void (*func_ptr_t)(void); + +/** function pointer type to void/uint8_t function */ +typedef void (*func_ptr_arg1_t)(uint8_t u8Param); + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + + + +#define bv(n) ((uint32_t)1u << (n)) + +#define bv0 (((uint32_t)1u) << 0) +#define bv1 (((uint32_t)1u) << 1) +#define bv2 (((uint32_t)1u) << 2) +#define bv3 (((uint32_t)1u) << 3) +#define bv4 (((uint32_t)1u) << 4) +#define bv5 (((uint32_t)1u) << 5) +#define bv6 (((uint32_t)1u) << 6) +#define bv7 (((uint32_t)1u) << 7) +#define bv8 (((uint32_t)1u) << 8) +#define bv9 (((uint32_t)1u) << 9) +#define bv10 (((uint32_t)1u) << 10) +#define bv11 (((uint32_t)1u) << 11) +#define bv12 (((uint32_t)1u) << 12) +#define bv13 (((uint32_t)1u) << 13) +#define bv14 (((uint32_t)1u) << 14) +#define bv15 (((uint32_t)1u) << 15) +#define bv16 (((uint32_t)1u) << 16) +#define bv17 (((uint32_t)1u) << 17) +#define bv18 (((uint32_t)1u) << 18) +#define bv19 (((uint32_t)1u) << 19) +#define bv20 (((uint32_t)1u) << 20) +#define bv21 (((uint32_t)1u) << 21) +#define bv22 (((uint32_t)1u) << 22) +#define bv23 (((uint32_t)1u) << 23) +#define bv24 (((uint32_t)1u) << 24) +#define bv25 (((uint32_t)1u) << 25) +#define bv26 (((uint32_t)1u) << 26) +#define bv27 (((uint32_t)1u) << 27) +#define bv28 (((uint32_t)1u) << 28) +#define bv29 (((uint32_t)1u) << 29) +#define bv30 (((uint32_t)1u) << 30) +#define bv31 (((uint32_t)1u) << 31) + +#define REGBITS_SET( Reg , Mask ) ( (Reg) |= (Mask) ) +#define REGBITS_CLR( Reg , Mask ) ( (Reg) &= (~((uint32_t)(Mask))) ) +#define REGBITS_GET( Reg , Mask ) ( (Reg) & (Mask) ) +#define REGBITS_MODIFY( Reg , Mask , Value ) ( (Reg) = ((Reg) & (~(uint32_t)(Mask))) | (Value) ) + +/* Exported macro ------------------------------------------------------------*/ +#define USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT + /** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) + /* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +#endif /* __BASE_TYPES_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012.h new file mode 100644 index 0000000..96e6e0c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012.h @@ -0,0 +1,8732 @@ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * @file CW32L012.h + * @brief CMSIS HeaderFile + * @version 1.2 + * @date Wed Jul 30 11:20:43 2025 + * @note Generated by SVDConv V3.3.46 + * from File 'cw32l012.svd', + * last modified on Wed Jul 30 11:20:28 2025 + */ + + +/** @addtogroup Wuhan Xinyuan Semiconductor Co.Ltd + * @{ + */ + + +/** @addtogroup CW32L012 + * @{ + */ + + +#ifndef __CW32L012_H +#define __CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== cw32l012 Specific Interrupt Numbers ========================================== */ + WDT_IRQn = 0, /*!< 0 Watch Dog Timer Interrupt */ + LVD_IRQn = 1, /*!< 1 Low Voltage Detect Interrupt */ + RTC_IRQn = 2, /*!< 2 Real Time Clock Interrupt */ + FLASHRAM_IRQn = 3, /*!< 3 Flash/RAM Interrupt */ + SYSCTRL_IRQn = 4, /*!< 4 SYSCTRL Interupt */ + GPIOA_IRQn = 5, /*!< 5 GPIOA Interrupt */ + GPIOB_IRQn = 6, /*!< 6 GPIOB Interrupt */ + GPIOC_IRQn = 7, /*!< 7 GPIOC Interrupt */ + GPIOF_IRQn = 8, /*!< 8 GPIOF Interrupt */ + DMACH12_IRQn = 9, /*!< 9 DMA Channel 1/2 Interrupt */ + DMACH34_IRQn = 10, /*!< 10 DMA Channel 3/4 Interrupt */ + CORDIC_IRQn = 11, /*!< 11 desc CORDIC */ + ADC1_IRQn = 12, /*!< 12 ADC Interrupt */ + ATIM_IRQn = 13, /*!< 13 Advanced Timer Interrupt */ + VC13_IRQn = 14, /*!< 14 Voltage Comparator 1/3 Interrupt */ + VC24_IRQn = 15, /*!< 15 Voltage Comparator 2/4 Interrupt */ + GTIM1_IRQn = 16, /*!< 16 General Timer1 Interrupt */ + GTIM2_IRQn = 17, /*!< 17 General Timer1 Interrupt */ + GTIM34_IRQn = 18, /*!< 18 General Timer3_4 Interrupt */ + LPTIM_IRQn = 19, /*!< 19 LPTIM Interrupt */ + BTIM1_IRQn = 20, /*!< 20 Base Timer1 Interrupt */ + BTIM2_IRQn = 21, /*!< 21 Base Timer2 Interrupt */ + BTIM3_HALLTIM_IRQn = 22, /*!< 22 Base Timer3 and Hall timer Interrupt */ + I2C1_IRQn = 23, /*!< 23 I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< 24 I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< 25 SPI1 Interrupt */ + SPI23_IRQn = 26, /*!< 26 SPI23 Interrupt */ + UART1_IRQn = 27, /*!< 27 UART1 Interrupt */ + UART2_IRQn = 28, /*!< 28 UART2 Interrupt */ + UART3_IRQn = 29, /*!< 29 UART3 Interrupt */ + ADC2_DAC_IRQn = 30, /*!< 30 ADC2 and DAC Interrupt */ + CLKFAULT_IRQn = 31 /*!< 31 Clock Fault Interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 0 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 0 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ +#include "system_cw32l012.h" /*!< cw32l012 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc ADC1 (ADC1) + */ + +typedef struct { /*!< (@ 0x40000000) ADC1 Structure */ + + union { + __IOM uint32_t CR; /*!< (@ 0x00000000) desc CR */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t CONT : 1; /*!< [1..1] desc CONT */ + __IOM uint32_t CLK : 2; /*!< [3..2] desc CLK */ + __IOM uint32_t ENS : 3; /*!< [6..4] desc ENS */ + __IOM uint32_t SLAVE : 1; /*!< [7..7] desc SLAVE */ + } CR_f; + } ; + + union { + __IOM uint32_t START; /*!< (@ 0x00000004) desc START */ + + struct { + __IOM uint32_t START : 1; /*!< [0..0] desc START */ + } START_f; + } ; + + union { + __IOM uint32_t AWDTR; /*!< (@ 0x00000008) desc AWDTR */ + + struct { + __IOM uint32_t VTL : 12; /*!< [11..0] desc VTL */ + __IM uint32_t : 4; + __IOM uint32_t VTH : 12; /*!< [27..16] desc VTH */ + } AWDTR_f; + } ; + + union { + __IOM uint32_t AWDCR; /*!< (@ 0x0000000C) desc AWDCR */ + + struct { + __IOM uint32_t IN0 : 1; /*!< [0..0] desc IN0 */ + __IOM uint32_t IN1 : 1; /*!< [1..1] desc IN1 */ + __IOM uint32_t IN2 : 1; /*!< [2..2] desc IN2 */ + __IOM uint32_t IN3 : 1; /*!< [3..3] desc IN3 */ + __IOM uint32_t IN4 : 1; /*!< [4..4] desc IN4 */ + __IOM uint32_t IN5 : 1; /*!< [5..5] desc IN5 */ + __IOM uint32_t IN6 : 1; /*!< [6..6] desc IN6 */ + __IOM uint32_t IN7 : 1; /*!< [7..7] desc IN7 */ + __IOM uint32_t IN8 : 1; /*!< [8..8] desc IN8 */ + __IOM uint32_t IN9 : 1; /*!< [9..9] desc IN9 */ + __IOM uint32_t IN10 : 1; /*!< [10..10] desc IN10 */ + __IOM uint32_t IN11 : 1; /*!< [11..11] desc IN11 */ + __IOM uint32_t IN12 : 1; /*!< [12..12] desc IN12 */ + __IOM uint32_t IN13 : 1; /*!< [13..13] desc IN13 */ + __IOM uint32_t IN14 : 1; /*!< [14..14] desc IN14 */ + __IOM uint32_t IN15 : 1; /*!< [15..15] desc IN15 */ + } AWDCR_f; + } ; + + union { + __IOM uint32_t TRIGGER; /*!< (@ 0x00000010) desc TRIGGER */ + + struct { + __IOM uint32_t ATIMTRGO : 1; /*!< [0..0] desc ATIMTRGO */ + __IOM uint32_t ATIMTRGO2 : 1; /*!< [1..1] desc ATIMTRGO2 */ + __IOM uint32_t ATIMOC1REFC : 1; /*!< [2..2] desc ATIMOC1REFC */ + __IOM uint32_t ATIMOC2REFC : 1; /*!< [3..3] desc ATIMOC2REFC */ + __IOM uint32_t ATIMOC3REFC : 1; /*!< [4..4] desc ATIMOC3REFC */ + __IOM uint32_t ATIMOC4REFC : 1; /*!< [5..5] desc ATIMOC4REFC */ + __IOM uint32_t ATIMOC5REFC : 1; /*!< [6..6] desc ATIMOC5REFC */ + __IOM uint32_t ATIMOC6REFC : 1; /*!< [7..7] desc ATIMOC6REFC */ + __IOM uint32_t GTIM1TRGO : 1; /*!< [8..8] desc GTIM1TRGO */ + __IOM uint32_t GTIM1OC1REFC : 1; /*!< [9..9] desc GTIM1OC1REFC */ + __IOM uint32_t GTIM1OC2REFC : 1; /*!< [10..10] desc GTIM1OC2REFC */ + __IOM uint32_t GTIM1OC3REFC : 1; /*!< [11..11] desc GTIM1OC3REFC */ + __IOM uint32_t GTIM1OC4REFC : 1; /*!< [12..12] desc GTIM1OC4REFC */ + __IOM uint32_t GTIM2TRGO : 1; /*!< [13..13] desc GTIM2TRGO */ + __IOM uint32_t GTIM2OC1REFC : 1; /*!< [14..14] desc GTIM2OC1REFC */ + __IOM uint32_t GTIM2OC2REFC : 1; /*!< [15..15] desc GTIM2OC2REFC */ + __IOM uint32_t GTIM2OC3REFC : 1; /*!< [16..16] desc GTIM2OC3REFC */ + __IOM uint32_t GTIM2OC4REFC : 1; /*!< [17..17] desc GTIM2OC4REFC */ + __IOM uint32_t GTIM3TRGO : 1; /*!< [18..18] desc GTIM3TRGO */ + __IOM uint32_t GTIM3OC1REFC : 1; /*!< [19..19] desc GTIM3OC1REFC */ + __IOM uint32_t GTIM3OC2REFC : 1; /*!< [20..20] desc GTIM3OC2REFC */ + __IOM uint32_t GTIM3OC3REFC : 1; /*!< [21..21] desc GTIM3OC3REFC */ + __IOM uint32_t GTIM3OC4REFC : 1; /*!< [22..22] desc GTIM3OC4REFC */ + __IOM uint32_t GTIM4TRGO : 1; /*!< [23..23] desc GTIM4TRGO */ + __IOM uint32_t GTIM4OC1REFC : 1; /*!< [24..24] desc GTIM4OC1REFC */ + __IOM uint32_t GTIM4OC2REFC : 1; /*!< [25..25] desc GTIM4OC2REFC */ + __IOM uint32_t GTIM4OC3REFC : 1; /*!< [26..26] desc GTIM4OC3REFC */ + __IOM uint32_t GTIM4OC4REFC : 1; /*!< [27..27] desc GTIM4OC4REFC */ + __IOM uint32_t BTIM1TRGO : 1; /*!< [28..28] desc BTIM1TRGO */ + __IOM uint32_t BTIM2TRGO : 1; /*!< [29..29] desc BTIM2TRGO */ + __IOM uint32_t BTIM3TRGO : 1; /*!< [30..30] desc BTIM3TRGO */ + __IOM uint32_t HALLTIMTRGO : 1; /*!< [31..31] desc HALLTIMTRGO */ + } TRIGGER_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t SAMPLE; /*!< (@ 0x00000018) desc SAMPLE */ + + struct { + __IOM uint32_t SQRCH0 : 4; /*!< [3..0] desc SQRCH0 */ + __IOM uint32_t SQRCH1 : 4; /*!< [7..4] desc SQRCH1 */ + __IOM uint32_t SQRCH2 : 4; /*!< [11..8] desc SQRCH2 */ + __IOM uint32_t SQRCH3 : 4; /*!< [15..12] desc SQRCH3 */ + __IOM uint32_t SQRCH4 : 4; /*!< [19..16] desc SQRCH4 */ + __IOM uint32_t SQRCH5 : 4; /*!< [23..20] desc SQRCH5 */ + __IOM uint32_t SQRCH6 : 4; /*!< [27..24] desc SQRCH6 */ + __IOM uint32_t SQRCH7 : 4; /*!< [31..28] desc SQRCH7 */ + } SAMPLE_f; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t SQRCFR; /*!< (@ 0x00000020) desc SQRCFR */ + + struct { + __IOM uint32_t SQRCH0 : 4; /*!< [3..0] desc SQRCH0 */ + __IOM uint32_t SQRCH1 : 4; /*!< [7..4] desc SQRCH1 */ + __IOM uint32_t SQRCH2 : 4; /*!< [11..8] desc SQRCH2 */ + __IOM uint32_t SQRCH3 : 4; /*!< [15..12] desc SQRCH3 */ + __IOM uint32_t SQRCH4 : 4; /*!< [19..16] desc SQRCH4 */ + __IOM uint32_t SQRCH5 : 4; /*!< [23..20] desc SQRCH5 */ + __IOM uint32_t SQRCH6 : 4; /*!< [27..24] desc SQRCH6 */ + __IOM uint32_t SQRCH7 : 4; /*!< [31..28] desc SQRCH7 */ + } SQRCFR_f; + } ; + __IM uint32_t RESERVED2[3]; + + union { + __IM uint32_t RESULT0; /*!< (@ 0x00000030) desc RESULT0 */ + + struct { + __IM uint32_t RESULT : 12; /*!< [15..0] desc RESULT */ + } RESULT0_f; + } ; + + union { + __IM uint32_t RESULT1; /*!< (@ 0x00000034) desc RESULT1 */ + + struct { + __IM uint32_t RESULT : 12; /*!< [15..0] desc RESULT */ + } RESULT1_f; + } ; + + union { + __IM uint32_t RESULT2; /*!< (@ 0x00000038) desc RESULT2 */ + + struct { + __IM uint32_t RESULT : 12; /*!< [15..0] desc RESULT */ + } RESULT2_f; + } ; + + union { + __IM uint32_t RESULT3; /*!< (@ 0x0000003C) desc RESULT3 */ + + struct { + __IM uint32_t RESULT : 12; /*!< [15..0] desc RESULT */ + } RESULT3_f; + } ; + + union { + __IM uint32_t RESULT4; /*!< (@ 0x00000040) desc RESULT4 */ + + struct { + __IM uint32_t RESULT : 12; /*!< [15..0] desc RESULT */ + } RESULT4_f; + } ; + + union { + __IM uint32_t RESULT5; /*!< (@ 0x00000044) desc RESULT5 */ + + struct { + __IM uint32_t RESULT : 12; /*!< [15..0] desc RESULT */ + } RESULT5_f; + } ; + + union { + __IM uint32_t RESULT6; /*!< (@ 0x00000048) desc RESULT6 */ + + struct { + __IM uint32_t RESULT : 12; /*!< [15..0] desc RESULT */ + } RESULT6_f; + } ; + + union { + __IM uint32_t RESULT7; /*!< (@ 0x0000004C) desc RESULT7 */ + + struct { + __IM uint32_t RESULT : 12; /*!< [15..0] desc RESULT */ + } RESULT7_f; + } ; + __IM uint32_t RESERVED3[8]; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000070) desc IER */ + + struct { + __IOM uint32_t EOC : 1; /*!< [0..0] desc EOC */ + __IOM uint32_t EOS : 1; /*!< [1..1] desc EOS */ + __IM uint32_t : 1; + __IOM uint32_t AWDL : 1; /*!< [3..3] desc AWDL */ + __IOM uint32_t AWDH : 1; /*!< [4..4] desc AWDH */ + __IOM uint32_t DMAEOC : 1; /*!< [5..5] desc DMAEOC */ + __IOM uint32_t DMAEOS : 1; /*!< [6..6] desc DMAEOS */ + } IER_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000074) desc ICR */ + + struct { + __IOM uint32_t EOC : 1; /*!< [0..0] desc EOC */ + __IOM uint32_t EOS : 1; /*!< [1..1] desc EOS */ + __IM uint32_t : 1; + __IOM uint32_t AWDL : 1; /*!< [3..3] desc AWDL */ + __IOM uint32_t AWDH : 1; /*!< [4..4] desc AWDH */ + } ICR_f; + } ; + + union { + __IOM uint32_t ISR; /*!< (@ 0x00000078) desc ISR */ + + struct { + __IM uint32_t EOC : 1; /*!< [0..0] desc EOC */ + __IM uint32_t EOS : 1; /*!< [1..1] desc EOS */ + __IM uint32_t : 1; + __IM uint32_t AWDL : 1; /*!< [3..3] desc AWDL */ + __IOM uint32_t AWDH : 1; /*!< [4..4] desc AWDH */ + } ISR_f; + } ; +} ADC_TypeDef; /*!< Size = 124 (0x7c) */ + + + +/* =========================================================================================================================== */ +/* ================ ATIM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc ATIM (ATIM) + */ + +typedef struct { /*!< (@ 0x40001400) ATIM Structure */ + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control Register1 */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] desc CEN */ + __IOM uint32_t UDIS : 1; /*!< [1..1] desc UDIS */ + __IOM uint32_t URS : 1; /*!< [2..2] desc URS */ + __IOM uint32_t OPM : 1; /*!< [3..3] desc OPM */ + __IOM uint32_t DIR : 1; /*!< [4..4] desc DIR */ + __IOM uint32_t CMS : 2; /*!< [6..5] desc CMS */ + __IOM uint32_t ARPE : 1; /*!< [7..7] desc ARPE */ + __IOM uint32_t CKD : 2; /*!< [9..8] desc CKD */ + __IM uint32_t : 1; + __IOM uint32_t UIFREMAP : 1; /*!< [11..11] desc UIFREMAP */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000004) Control Register2 */ + + struct { + __IOM uint32_t CCPC : 1; /*!< [0..0] desc CCPC */ + __IM uint32_t : 1; + __IOM uint32_t CCUS : 1; /*!< [2..2] desc CCUS */ + __IOM uint32_t CCDS : 1; /*!< [3..3] desc CCDS */ + __IOM uint32_t MMS : 3; /*!< [6..4] desc MMS */ + __IOM uint32_t TI1S : 1; /*!< [7..7] desc TI1S */ + __IOM uint32_t OIS1 : 1; /*!< [8..8] desc OIS1 */ + __IOM uint32_t OIS1N : 1; /*!< [9..9] desc OIS1N */ + __IOM uint32_t OIS2 : 1; /*!< [10..10] desc OIS2 */ + __IOM uint32_t OIS2N : 1; /*!< [11..11] desc OIS2N */ + __IOM uint32_t OIS3 : 1; /*!< [12..12] desc OIS3 */ + __IOM uint32_t OIS3N : 1; /*!< [13..13] desc OIS3N */ + __IOM uint32_t OIS4 : 1; /*!< [14..14] desc OIS4 */ + __IOM uint32_t OIS4N : 1; /*!< [15..15] desc OIS4N */ + __IOM uint32_t OIS5 : 1; /*!< [16..16] desc OIS5 */ + __IOM uint32_t OIS5N : 1; /*!< [17..17] desc OIS5N */ + __IOM uint32_t OIS6 : 1; /*!< [18..18] desc OIS6 */ + __IOM uint32_t OIS6N : 1; /*!< [19..19] desc OIS6N */ + __IOM uint32_t MMS2 : 5; /*!< [24..20] desc MMS2 */ + __IOM uint32_t MMSH : 2; /*!< [26..25] desc MMSH */ + } CR2_f; + } ; + + union { + __IOM uint32_t SMCR; /*!< (@ 0x00000008) Slave Mode Control Register */ + + struct { + __IOM uint32_t SMS : 3; /*!< [2..0] desc SMS */ + __IOM uint32_t OCCS : 1; /*!< [3..3] desc OCCS */ + __IOM uint32_t TS : 3; /*!< [6..4] desc TS */ + __IOM uint32_t MSM : 1; /*!< [7..7] desc MSM */ + __IOM uint32_t ETF : 4; /*!< [11..8] desc ETF */ + __IOM uint32_t ETPS : 2; /*!< [13..12] desc ETPS */ + __IOM uint32_t ECE : 1; /*!< [14..14] desc ECE */ + __IOM uint32_t ETP : 1; /*!< [15..15] desc ETP */ + __IOM uint32_t SMSH : 1; /*!< [16..16] desc SMSH */ + __IM uint32_t : 3; + __IOM uint32_t TSH : 2; /*!< [21..20] desc TSH */ + __IM uint32_t : 2; + __IOM uint32_t SMSPE : 1; /*!< [24..24] desc SMSPE */ + __IOM uint32_t SMSPS : 1; /*!< [25..25] desc SMSPS */ + } SMCR_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x0000000C) Interrupt Enable Register */ + + struct { + __IOM uint32_t UIE : 1; /*!< [0..0] desc UIE */ + __IOM uint32_t CC1IE : 1; /*!< [1..1] desc CC1IE */ + __IOM uint32_t CC2IE : 1; /*!< [2..2] desc CC2IE */ + __IOM uint32_t CC3IE : 1; /*!< [3..3] desc CC3IE */ + __IOM uint32_t CC4IE : 1; /*!< [4..4] desc CC4IE */ + __IOM uint32_t COMIE : 1; /*!< [5..5] desc COMIE */ + __IOM uint32_t TIE : 1; /*!< [6..6] desc TIE */ + __IOM uint32_t BIE : 1; /*!< [7..7] desc BIE */ + __IOM uint32_t UDE : 1; /*!< [8..8] desc UDE */ + __IOM uint32_t CC1DE : 1; /*!< [9..9] desc CC1DE */ + __IOM uint32_t CC2DE : 1; /*!< [10..10] desc CC2DE */ + __IOM uint32_t CC3DE : 1; /*!< [11..11] desc CC3DE */ + __IOM uint32_t CC4DE : 1; /*!< [12..12] desc CC4DE */ + __IOM uint32_t COMDE : 1; /*!< [13..13] desc COMDE */ + __IOM uint32_t TDE : 1; /*!< [14..14] desc TDE */ + uint32_t : 1; + __IOM uint32_t CC5IE : 1; /*!< [16..16] desc CC5IE */ + __IOM uint32_t CC6IE : 1; /*!< [17..17] desc CC6IE */ + __IOM uint32_t CC5DE : 1; /*!< [18..18] desc CC5DE */ + __IOM uint32_t CC6DE : 1; /*!< [19..19] desc CC6DE */ + __IOM uint32_t IDXIE : 1; /*!< [20..20] desc IDXIE */ + __IOM uint32_t DIRIE : 1; /*!< [21..21] desc DIRIE */ + __IOM uint32_t IERRIE : 1; /*!< [22..22] desc IERRIE */ + __IOM uint32_t TERRIE : 1; /*!< [23..23] desc TERRIE */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000010) Interrupt status register */ + + struct { + __IM uint32_t UIF : 1; /*!< [0..0] desc UIF */ + __IM uint32_t CC1IF : 1; /*!< [1..1] desc CC1IF */ + __IM uint32_t CC2IF : 1; /*!< [2..2] desc CC2IF */ + __IM uint32_t CC3IF : 1; /*!< [3..3] desc CC3IF */ + __IM uint32_t CC4IF : 1; /*!< [4..4] desc CC4IF */ + __IM uint32_t COMIF : 1; /*!< [5..5] desc COMIF */ + __IM uint32_t TIF : 1; /*!< [6..6] desc TIF */ + __IM uint32_t BIF : 1; /*!< [7..7] desc BIF */ + __IM uint32_t B2IF : 1; /*!< [8..8] desc B2IF */ + __IM uint32_t CC1OF : 1; /*!< [9..9] desc CC1OF */ + __IM uint32_t CC2OF : 1; /*!< [10..10] desc CC2OF */ + __IM uint32_t CC3OF : 1; /*!< [11..11] desc CC3OF */ + __IM uint32_t CC4OF : 1; /*!< [12..12] desc CC4OF */ + __IM uint32_t SBIF : 1; /*!< [13..13] desc SBIF */ + __IM uint32_t : 2; + __IM uint32_t CC5IF : 1; /*!< [16..16] desc CC5IF */ + __IM uint32_t CC6IF : 1; /*!< [17..17] desc CC6IF */ + __IM uint32_t CC5OF : 1; /*!< [18..18] desc CC5OF */ + __IM uint32_t CC6OF : 1; /*!< [19..19] desc CC6OF */ + __IM uint32_t IDXF : 1; /*!< [20..20] desc IDXF */ + __IM uint32_t DIRF : 1; /*!< [21..21] desc DIRF */ + __IM uint32_t IERRF : 1; /*!< [22..22] desc IERRF */ + __IM uint32_t TERRF : 1; /*!< [23..23] desc TERRF */ + } ISR_f; + } ; + + union { + __IOM uint32_t EGR; /*!< (@ 0x00000014) Event generation register */ + + struct { + __IOM uint32_t UG : 1; /*!< [0..0] desc UG */ + __IOM uint32_t CC1G : 1; /*!< [1..1] desc CC1G */ + __IOM uint32_t CC2G : 1; /*!< [2..2] desc CC2G */ + __IOM uint32_t CC3G : 1; /*!< [3..3] desc CC3G */ + __IOM uint32_t CC4G : 1; /*!< [4..4] desc CC4G */ + __IOM uint32_t COMG : 1; /*!< [5..5] desc COMG */ + __IOM uint32_t TG : 1; /*!< [6..6] desc TG */ + __IOM uint32_t BG : 1; /*!< [7..7] desc BG */ + __IOM uint32_t B2G : 1; /*!< [8..8] desc B2G */ + __IM uint32_t : 7; + __IOM uint32_t CC5G : 1; /*!< [16..16] desc CC5G */ + __IOM uint32_t CC6G : 1; /*!< [17..17] desc CC6G */ + } EGR_f; + } ; + + union { + union { + __IOM uint32_t CCMR1CAP; /*!< (@ 0x00000018) capture compare mode register 1 */ + + struct { + __IOM uint32_t CC1S : 2; /*!< [1..0] desc CC1S */ + __IOM uint32_t IC1PSC : 2; /*!< [3..2] desc IC1PSC */ + __IOM uint32_t IC1F : 4; /*!< [7..4] desc IC1F */ + __IOM uint32_t CC2S : 2; /*!< [9..8] desc CC2S */ + __IOM uint32_t IC2PSC : 2; /*!< [11..10] desc IC2PSC */ + __IOM uint32_t IC2F : 4; /*!< [15..12] desc IC2F */ + } CCMR1CAP_f; + } ; + + union { + __IOM uint32_t CCMR1CMP; /*!< (@ 0x00000018) capture compare mode register 1 */ + + struct { + __IOM uint32_t CC1S : 2; /*!< [1..0] desc CC1S */ + __IOM uint32_t OC1FE : 1; /*!< [2..2] desc OC1FE */ + __IOM uint32_t OC1PE : 1; /*!< [3..3] desc OC1PE */ + __IOM uint32_t OC1M : 3; /*!< [6..4] desc OC1M */ + __IOM uint32_t OC1CE : 1; /*!< [7..7] desc OC1CE */ + __IOM uint32_t CC2S : 2; /*!< [9..8] desc CC2S */ + __IOM uint32_t OC2FE : 1; /*!< [10..10] desc OC2FE */ + __IOM uint32_t OC2PE : 1; /*!< [11..11] desc OC2PE */ + __IOM uint32_t OC2M : 3; /*!< [14..12] desc OC2M */ + __IOM uint32_t OC2CE : 1; /*!< [15..15] desc OC2CE */ + __IOM uint32_t OC1MH : 1; /*!< [16..16] desc OC1MH */ + __IM uint32_t : 7; + __IOM uint32_t OC2MH : 1; /*!< [24..24] desc OC2MH */ + } CCMR1CMP_f; + } ; + }; + + union { + union { + __IOM uint32_t CCMR2CAP; /*!< (@ 0x0000001C) capture compare mode register 2 */ + + struct { + __IOM uint32_t CC3S : 2; /*!< [1..0] desc CC3S */ + __IOM uint32_t IC3PSC : 2; /*!< [3..2] desc IC3PSC */ + __IOM uint32_t IC3F : 4; /*!< [7..4] desc IC3F */ + __IOM uint32_t CC4S : 2; /*!< [9..8] desc CC4S */ + __IOM uint32_t IC4PSC : 2; /*!< [11..10] desc IC4PSC */ + __IOM uint32_t IC4F : 4; /*!< [15..12] desc IC4F */ + } CCMR2CAP_f; + } ; + + union { + __IOM uint32_t CCMR2CMP; /*!< (@ 0x0000001C) capture compare mode register 2 */ + + struct { + __IOM uint32_t CC3S : 2; /*!< [1..0] desc CC3S */ + __IOM uint32_t OC3FE : 1; /*!< [2..2] desc OC3FE */ + __IOM uint32_t OC3PE : 1; /*!< [3..3] desc OC3PE */ + __IOM uint32_t OC3M : 3; /*!< [6..4] desc OC3M */ + __IOM uint32_t OC3CE : 1; /*!< [7..7] desc OC3CE */ + __IOM uint32_t CC4S : 2; /*!< [9..8] desc CC4S */ + __IOM uint32_t OC4FE : 1; /*!< [10..10] desc OC4FE */ + __IOM uint32_t OC4PE : 1; /*!< [11..11] desc OC4PE */ + __IOM uint32_t OC4M : 3; /*!< [14..12] desc OC4M */ + __IOM uint32_t OC4CE : 1; /*!< [15..15] desc OC4CE */ + __IOM uint32_t OC3MH : 1; /*!< [16..16] desc OC3MH */ + __IM uint32_t : 7; + __IOM uint32_t OC4MH : 1; /*!< [24..24] desc OC4MH */ + } CCMR2CMP_f; + } ; + }; + + union { + __IOM uint32_t CCER; /*!< (@ 0x00000020) capture compare enable register */ + + struct { + __IOM uint32_t CC1E : 1; /*!< [0..0] desc CC1E */ + __IOM uint32_t CC1P : 1; /*!< [1..1] desc CC1P */ + __IOM uint32_t CC1NE : 1; /*!< [2..2] desc CC1NE */ + __IOM uint32_t CC1NP : 1; /*!< [3..3] desc CC1NP */ + __IOM uint32_t CC2E : 1; /*!< [4..4] desc CC2E */ + __IOM uint32_t CC2P : 1; /*!< [5..5] desc CC2P */ + __IOM uint32_t CC2NE : 1; /*!< [6..6] desc CC2NE */ + __IOM uint32_t CC2NP : 1; /*!< [7..7] desc CC2NP */ + __IOM uint32_t CC3E : 1; /*!< [8..8] desc CC3E */ + __IOM uint32_t CC3P : 1; /*!< [9..9] desc CC3P */ + __IOM uint32_t CC3NE : 1; /*!< [10..10] desc CC3NE */ + __IOM uint32_t CC3NP : 1; /*!< [11..11] desc CC3NP */ + __IOM uint32_t CC4E : 1; /*!< [12..12] desc CC4E */ + __IOM uint32_t CC4P : 1; /*!< [13..13] desc CC4P */ + __IOM uint32_t CC4NE : 1; /*!< [14..14] desc CC4NE */ + __IOM uint32_t CC4NP : 1; /*!< [15..15] desc CC4NP */ + __IOM uint32_t CC5E : 1; /*!< [16..16] desc CC5E */ + __IOM uint32_t CC5P : 1; /*!< [17..17] desc CC5P */ + __IOM uint32_t CC5NE : 1; /*!< [18..18] desc CC5NE */ + __IOM uint32_t CC5NP : 1; /*!< [19..19] desc CC5NP */ + __IOM uint32_t CC6E : 1; /*!< [20..20] desc CC6E */ + __IOM uint32_t CC6P : 1; /*!< [21..21] desc CC6P */ + __IOM uint32_t CC6NE : 1; /*!< [22..22] desc CC6NE */ + __IOM uint32_t CC6NP : 1; /*!< [23..23] desc CC6NP */ + } CCER_f; + } ; + + union { + __IOM uint32_t CNT; /*!< (@ 0x00000024) Counter Register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IM uint32_t : 15; + __IM uint32_t UIFCPY : 1; /*!< [31..31] desc UIFCPY */ + } CNT_f; + } ; + + union { + __IOM uint32_t PSC; /*!< (@ 0x00000028) prescaler Register */ + + struct { + __IOM uint32_t PSC : 16; /*!< [15..0] desc PSC */ + } PSC_f; + } ; + + union { + __IOM uint32_t ARR; /*!< (@ 0x0000002C) Auto reload Register */ + + struct { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } ARR_f; + } ; + + union { + __IOM uint32_t RCR; /*!< (@ 0x00000030) Repetition Counter Register */ + + struct { + __IOM uint32_t REP : 16; /*!< [15..0] desc REP */ + } RCR_f; + } ; + + union { + __IOM uint32_t CCR1; /*!< (@ 0x00000034) capture compare register1 */ + + struct { + __IOM uint32_t CCR1 : 16; /*!< [15..0] desc CCR1 */ + } CCR1_f; + } ; + + union { + __IOM uint32_t CCR2; /*!< (@ 0x00000038) capture compare register2 */ + + struct { + __IOM uint32_t CCR2 : 16; /*!< [15..0] desc CCR2 */ + } CCR2_f; + } ; + + union { + __IOM uint32_t CCR3; /*!< (@ 0x0000003C) capture compare register3 */ + + struct { + __IOM uint32_t CCR3 : 16; /*!< [15..0] desc CCR3 */ + } CCR3_f; + } ; + + union { + __IOM uint32_t CCR4; /*!< (@ 0x00000040) capture compare register4 */ + + struct { + __IOM uint32_t CCR4 : 16; /*!< [15..0] desc CCR4 */ + } CCR4_f; + } ; + + union { + __IOM uint32_t BDTR; /*!< (@ 0x00000044) break and dead-time register */ + + struct { + __IOM uint32_t DTG : 8; /*!< [7..0] desc DTG */ + __IOM uint32_t LOCK : 2; /*!< [9..8] desc LOCK */ + __IOM uint32_t OSSI : 1; /*!< [10..10] desc OSSI */ + __IOM uint32_t OSSR : 1; /*!< [11..11] desc OSSR */ + __IOM uint32_t BKE : 1; /*!< [12..12] desc BKE */ + __IOM uint32_t BKP : 1; /*!< [13..13] desc BKP */ + __IOM uint32_t AOE : 1; /*!< [14..14] desc AOE */ + __IOM uint32_t MOE : 1; /*!< [15..15] desc MOE */ + __IOM uint32_t BKF : 4; /*!< [19..16] desc BKF */ + __IOM uint32_t BK2F : 4; /*!< [23..20] desc BK2F */ + __IOM uint32_t BK2E : 1; /*!< [24..24] desc BK2E */ + __IOM uint32_t BK2P : 1; /*!< [25..25] desc BK2P */ + } BDTR_f; + } ; + + union { + __IOM uint32_t CCR5; /*!< (@ 0x00000048) capture compare register5 */ + + struct { + __IOM uint32_t CCR5 : 16; /*!< [15..0] desc CCR5 */ + __IM uint32_t : 10; + __IOM uint32_t GC5C1 : 1; /*!< [26..26] desc GC5C1 */ + __IOM uint32_t GC5C2 : 1; /*!< [27..27] desc GC5C2 */ + __IOM uint32_t GC5C3 : 1; /*!< [28..28] desc GC5C3 */ + __IOM uint32_t GC5C4 : 1; /*!< [29..29] desc GC5C4 */ + __IOM uint32_t GC5C5 : 1; /*!< [30..30] desc GC5C5 */ + __IOM uint32_t GC5C6 : 1; /*!< [31..31] desc GC5C6 */ + } CCR5_f; + } ; + + union { + __IOM uint32_t CCR6; /*!< (@ 0x0000004C) capture compare register6 */ + + struct { + __IOM uint32_t CCR6 : 16; /*!< [15..0] desc CCR6 */ + __IM uint32_t : 10; + __IOM uint32_t GC6C1 : 1; /*!< [26..26] desc GC6C1 */ + __IOM uint32_t GC6C2 : 1; /*!< [27..27] desc GC6C2 */ + __IOM uint32_t GC6C3 : 1; /*!< [28..28] desc GC6C3 */ + __IOM uint32_t GC6C4 : 1; /*!< [29..29] desc GC6C4 */ + __IOM uint32_t GC6C5 : 1; /*!< [30..30] desc GC6C5 */ + __IOM uint32_t GC6C6 : 1; /*!< [31..31] desc GC6C6 */ + } CCR6_f; + } ; + + union { + union { + __IOM uint32_t CCMR3CAP; /*!< (@ 0x00000050) capture compare mode register 3 */ + + struct { + __IOM uint32_t CC5S : 2; /*!< [1..0] desc CC5S */ + __IOM uint32_t IC5PSC : 2; /*!< [3..2] desc IC5PSC */ + __IOM uint32_t IC5F : 4; /*!< [7..4] desc IC5F */ + __IOM uint32_t CC6S : 2; /*!< [9..8] desc CC6S */ + __IOM uint32_t IC6PSC : 2; /*!< [11..10] desc IC6PSC */ + __IOM uint32_t IC6F : 4; /*!< [15..12] desc IC6F */ + } CCMR3CAP_f; + } ; + + union { + __IOM uint32_t CCMR3CMP; /*!< (@ 0x00000050) capture compare mode register 3 */ + + struct { + __IOM uint32_t CC5S : 2; /*!< [1..0] desc CC5S */ + __IOM uint32_t OC5FE : 1; /*!< [2..2] desc OC5FE */ + __IOM uint32_t OC5PE : 1; /*!< [3..3] desc OC5PE */ + __IOM uint32_t OC5M : 3; /*!< [6..4] desc OC5M */ + __IOM uint32_t OC5CE : 1; /*!< [7..7] desc OC5CE */ + __IOM uint32_t CC6S : 2; /*!< [9..8] desc CC6S */ + __IOM uint32_t OC6FE : 1; /*!< [10..10] desc OC6FE */ + __IOM uint32_t OC6PE : 1; /*!< [11..11] desc OC6PE */ + __IOM uint32_t OC6M : 3; /*!< [14..12] desc OC6M */ + __IOM uint32_t OC6CE : 1; /*!< [15..15] desc OC6CE */ + __IOM uint32_t OC5MH : 1; /*!< [16..16] desc OC5MH */ + __IM uint32_t : 7; + __IOM uint32_t OC6MH : 1; /*!< [24..24] desc OC6MH */ + } CCMR3CMP_f; + } ; + }; + + union { + __IOM uint32_t DTR2; /*!< (@ 0x00000054) dead-time register2 */ + + struct { + __IOM uint32_t DTGF : 8; /*!< [7..0] desc DTGF */ + __IM uint32_t : 8; + __IOM uint32_t DTAE : 1; /*!< [16..16] desc DTAE */ + __IOM uint32_t DTPE : 1; /*!< [17..17] desc DTPE */ + } DTR2_f; + } ; + + union { + __IOM uint32_t ECR; /*!< (@ 0x00000058) Encoder control Register */ + + struct { + __IOM uint32_t IE : 1; /*!< [0..0] desc IE */ + __IOM uint32_t IDIR : 2; /*!< [2..1] desc IDIR */ + __IM uint32_t : 2; + __IOM uint32_t FIDX : 1; /*!< [5..5] desc FIDX */ + __IOM uint32_t IPOS : 2; /*!< [7..6] desc IPOS */ + } ECR_f; + } ; + + union { + __IOM uint32_t TISEL1; /*!< (@ 0x0000005C) Timer Input Select Register1 */ + + struct { + __IOM uint32_t TI1SEL : 4; /*!< [3..0] desc TI1SEL */ + __IM uint32_t : 4; + __IOM uint32_t TI2SEL : 4; /*!< [11..8] desc TI2SEL */ + __IM uint32_t : 4; + __IOM uint32_t TI3SEL : 4; /*!< [19..16] desc TI3SEL */ + __IM uint32_t : 4; + __IOM uint32_t TI4SEL : 4; /*!< [27..24] desc TI4SEL */ + } TISEL1_f; + } ; + + union { + __IOM uint32_t AF1; /*!< (@ 0x00000060) Alternate function Register1 */ + + struct { + __IOM uint32_t BKINE : 1; /*!< [0..0] desc BKINE */ + __IOM uint32_t BKVC1E : 1; /*!< [1..1] desc BKVC1E */ + __IOM uint32_t BKVC2E : 1; /*!< [2..2] desc BKVC2E */ + __IOM uint32_t BKVC3E : 1; /*!< [3..3] desc BKVC3E */ + __IOM uint32_t BKVC4E : 1; /*!< [4..4] desc BKVC4E */ + __IM uint32_t : 4; + __IOM uint32_t BKINP : 1; /*!< [9..9] desc BKINP */ + __IOM uint32_t BKVC1P : 1; /*!< [10..10] desc BKVC1P */ + __IOM uint32_t BKVC2P : 1; /*!< [11..11] desc BKVC2P */ + __IOM uint32_t BKVC3P : 1; /*!< [12..12] desc BKVC3P */ + __IOM uint32_t BKVC4P : 1; /*!< [13..13] desc BKVC4P */ + __IM uint32_t : 2; + __IOM uint32_t ETRSEL : 4; /*!< [19..16] desc ETRSEL */ + } AF1_f; + } ; + + union { + __IOM uint32_t AF2; /*!< (@ 0x00000064) Alternate function Register2 */ + + struct { + __IOM uint32_t BK2INE : 1; /*!< [0..0] desc BK2INE */ + __IOM uint32_t BK2VC1E : 1; /*!< [1..1] desc BK2VC1E */ + __IOM uint32_t BK2VC2E : 1; /*!< [2..2] desc BK2VC2E */ + __IOM uint32_t BK2VC3E : 1; /*!< [3..3] desc BK2VC3E */ + __IOM uint32_t BK2VC4E : 1; /*!< [4..4] desc BK2VC4E */ + __IM uint32_t : 4; + __IOM uint32_t BK2INP : 1; /*!< [9..9] desc BK2INP */ + __IOM uint32_t BK2VC1P : 1; /*!< [10..10] desc BK2VC1P */ + __IOM uint32_t BK2VC2P : 1; /*!< [11..11] desc BK2VC2P */ + __IOM uint32_t BK2VC3P : 1; /*!< [12..12] desc BK2VC3P */ + __IOM uint32_t BK2VC4P : 1; /*!< [13..13] desc BK2VC4P */ + __IM uint32_t : 2; + __IOM uint32_t OCRSEL : 4; /*!< [19..16] desc OCRSEL */ + } AF2_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t TISEL2; /*!< (@ 0x0000006C) Timer Input Select Register2 */ + + struct { + __IOM uint32_t TI5SEL : 4; /*!< [3..0] desc TI5SEL */ + __IM uint32_t : 4; + __IOM uint32_t TI6SEL : 4; /*!< [11..8] desc TI6SEL */ + } TISEL2_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000070) Interrupt clean register */ + + struct { + __IOM uint32_t UIF : 1; /*!< [0..0] desc UIF */ + __IOM uint32_t CC1IF : 1; /*!< [1..1] desc CC1IF */ + __IOM uint32_t CC2IF : 1; /*!< [2..2] desc CC2IF */ + __IOM uint32_t CC3IF : 1; /*!< [3..3] desc CC3IF */ + __IOM uint32_t CC4IF : 1; /*!< [4..4] desc CC4IF */ + __IOM uint32_t COMIF : 1; /*!< [5..5] desc COMIF */ + __IOM uint32_t TIF : 1; /*!< [6..6] desc TIF */ + __IOM uint32_t BIF : 1; /*!< [7..7] desc BIF */ + __IOM uint32_t B2IF : 1; /*!< [8..8] desc B2IF */ + __IOM uint32_t CC1OF : 1; /*!< [9..9] desc CC1OF */ + __IOM uint32_t CC2OF : 1; /*!< [10..10] desc CC2OF */ + __IOM uint32_t CC3OF : 1; /*!< [11..11] desc CC3OF */ + __IOM uint32_t CC4OF : 1; /*!< [12..12] desc CC4OF */ + __IOM uint32_t SBIF : 1; /*!< [13..13] desc SBIF */ + __IM uint32_t : 2; + __IOM uint32_t CC5IF : 1; /*!< [16..16] desc CC5IF */ + __IOM uint32_t CC6IF : 1; /*!< [17..17] desc CC6IF */ + __IOM uint32_t CC5OF : 1; /*!< [18..18] desc CC5OF */ + __IOM uint32_t CC6OF : 1; /*!< [19..19] desc CC6OF */ + __IOM uint32_t IDXF : 1; /*!< [20..20] desc IDXF */ + __IOM uint32_t DIRF : 1; /*!< [21..21] desc DIRF */ + __IOM uint32_t IERRF : 1; /*!< [22..22] desc IERRF */ + __IOM uint32_t TERRF : 1; /*!< [23..23] desc TERRF */ + } ICR_f; + } ; +} ATIM_TypeDef; /*!< Size = 116 (0x74) */ + + + +/* =========================================================================================================================== */ +/* ================ BGR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief BGR (BGR) + */ + +typedef struct { /*!< (@ 0x400000FC) BGR Structure */ + + union { + __IOM uint32_t CR; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t BGREN : 1; /*!< [0..0] desc BGREN */ + __IOM uint32_t TSEN : 1; /*!< [1..1] desc TSEN */ + } CR_f; + } ; +} BGR_TypeDef; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ BTIM1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Base Timer 1 (BTIM1) + */ + +typedef struct { /*!< (@ 0x40004800) BTIM1 Structure */ + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t UDIS : 1; /*!< [1..1] desc UDIS */ + __IOM uint32_t URS : 1; /*!< [2..2] desc URS */ + __IOM uint32_t ONESHOT : 1; /*!< [3..3] desc ONESHOT */ + __IM uint32_t : 7; + __IOM uint32_t UIFREMAP : 1; /*!< [11..11] desc UIFREMAP */ + __IM uint32_t : 3; + __IOM uint32_t TOGEN : 1; /*!< [15..15] desc TOGEN */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000004) Control register2 */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t MMS : 3; /*!< [6..4] desc MMS */ + } CR2_f; + } ; + + union { + __IOM uint32_t SMCR; /*!< (@ 0x00000008) Slave Mode Control register */ + + struct { + __IOM uint32_t SMS : 3; /*!< [2..0] desc SMS */ + __IOM uint32_t RSTISRC : 4; /*!< [6..3] desc RSTISRC */ + __IOM uint32_t TRGISRC : 4; /*!< [10..7] desc TRGISRC */ + __IOM uint32_t MSM : 1; /*!< [11..11] desc MSM */ + __IOM uint32_t TRGIFLT : 3; /*!< [14..12] desc TRGIFLT */ + __IM uint32_t : 1; + __IOM uint32_t RSTIPOL : 1; /*!< [16..16] desc RSTIPOL */ + __IOM uint32_t TRGIPOL : 1; /*!< [17..17] desc TRGIPOL */ + } SMCR_f; + } ; + + union { + __IOM uint32_t DIER; /*!< (@ 0x0000000C) Interrupt enable register */ + + struct { + __IOM uint32_t UIE : 1; /*!< [0..0] desc UIE */ + __IM uint32_t : 5; + __IOM uint32_t TIE : 1; /*!< [6..6] desc TIE */ + uint32_t : 1; + __IOM uint32_t UDE : 1; /*!< [8..8] desc UDE */ + uint32_t : 5; + __IOM uint32_t TDE : 1; /*!< [14..14] desc TDE */ + } DIER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000010) Interrupt status register */ + + struct { + __IM uint32_t UIF : 1; /*!< [0..0] desc UIF */ + __IM uint32_t : 5; + __IM uint32_t TIF : 1; /*!< [6..6] desc TIF */ + } ISR_f; + } ; + + union { + __OM uint32_t EGR; /*!< (@ 0x00000014) Event Generate register */ + + struct { + __OM uint32_t UG : 1; /*!< [0..0] desc UG */ + __IM uint32_t : 5; + __OM uint32_t TG : 1; /*!< [6..6] desc TG */ + } EGR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000018) Interrupt flag clear register */ + + struct { + __IOM uint32_t UIF : 1; /*!< [0..0] desc UIF */ + __IM uint32_t : 5; + __IOM uint32_t TIF : 1; /*!< [6..6] desc TIF */ + } ICR_f; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t CNT; /*!< (@ 0x00000024) Counter Register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IM uint32_t : 15; + __IM uint32_t UIFCPY : 1; /*!< [31..31] desc UIFCPY */ + } CNT_f; + } ; + + union { + __IOM uint32_t PSC; /*!< (@ 0x00000028) Prescaler Control Register */ + + struct { + __IOM uint32_t PSC : 16; /*!< [15..0] desc PSC */ + } PSC_f; + } ; + + union { + __IOM uint32_t ARR; /*!< (@ 0x0000002C) Auto Reload Register */ + + struct { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } ARR_f; + } ; +} BTIM_TypeDef; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ CORDIC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc CORDIC (CORDIC) + */ + +typedef struct { /*!< (@ 0x40023400) CORDIC Structure */ + + union { + __IOM uint32_t CSR; /*!< (@ 0x00000000) Control and State register */ + + struct { + __IOM uint32_t FUNC : 4; /*!< [3..0] desc FUNC */ + __IOM uint32_t SCALE : 3; /*!< [6..4] desc SCALE */ + __IOM uint32_t FORMAT : 1; /*!< [7..7] desc FORMAT */ + __IOM uint32_t ITER : 4; /*!< [11..8] desc ITER */ + __IOM uint32_t COMP : 1; /*!< [12..12] desc COMP */ + __IOM uint32_t IE : 1; /*!< [13..13] desc IE */ + __IOM uint32_t DMAEOC : 1; /*!< [14..14] desc DMAEOC */ + __IOM uint32_t DMAIDLE : 1; /*!< [15..15] desc DMAIDLE */ + __IM uint32_t EOC : 1; /*!< [16..16] desc EOC */ + __IM uint32_t BUSY : 1; /*!< [17..17] desc BUSY */ + } CSR_f; + } ; + + union { + __IOM uint32_t X; /*!< (@ 0x00000004) Data register X */ + + struct { + __IOM uint32_t X : 32; /*!< [31..0] desc DATA */ + } X_f; + } ; + + union { + __IOM uint32_t Y; /*!< (@ 0x00000008) Data register Y */ + + struct { + __IOM uint32_t Y : 32; /*!< [31..0] desc DATA */ + } Y_f; + } ; + + union { + __IOM uint32_t Z; /*!< (@ 0x0000000C) Data register Y */ + + struct { + __IOM uint32_t Z : 32; /*!< [31..0] desc DATA */ + } Z_f; + } ; +} CORDIC_TypeDef; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ CRC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc CRC (CRC) + */ + +typedef struct { /*!< (@ 0x40023000) CRC Structure */ + + union { + __IOM uint32_t CR; /*!< (@ 0x00000000) Control register */ + + struct { + __IOM uint32_t MODE : 4; /*!< [3..0] desc MODE */ + } CR_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t DR; /*!< (@ 0x00000008) Data register */ + + struct { + __IOM uint32_t DR : 8; /*!< [7..0] desc DR */ + } DR_f; + } ; + + union { + __IM uint32_t RESULT; /*!< (@ 0x0000000C) Result register */ + + struct { + __IM uint32_t RESULT : 16; /*!< [15..0] desc RESULT */ + } RESULT_f; + } ; +} CRC_TypeDef; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ DAC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc DAC (DAC) + */ + +typedef struct { /*!< (@ 0x400000C0) DAC Structure */ + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control register */ + + struct { + __IOM uint32_t EN1 : 1; /*!< [0..0] desc EN1 */ + __IOM uint32_t TEN1 : 1; /*!< [1..1] desc TEN1 */ + __IOM uint32_t TSEL1 : 4; /*!< [5..2] desc TSEL1 */ + __IOM uint32_t WAVE1 : 2; /*!< [7..6] desc WAVE1 */ + __IOM uint32_t MAMP1 : 4; /*!< [11..8] desc MAMP1 */ + __IOM uint32_t DMAEN1 : 1; /*!< [12..12] desc DMAEN1 */ + __IOM uint32_t DMAUDRIE1 : 1; /*!< [13..13] desc DMAUDRIE1 */ + __IM uint32_t : 2; + __IOM uint32_t EN2 : 1; /*!< [16..16] desc EN2 */ + __IOM uint32_t TEN2 : 1; /*!< [17..17] desc TEN2 */ + __IOM uint32_t TSEL2 : 4; /*!< [21..18] desc TSEL2 */ + __IOM uint32_t WAVE2 : 2; /*!< [23..22] desc WAVE2 */ + __IOM uint32_t MAMP2 : 4; /*!< [27..24] desc MAMP2 */ + __IOM uint32_t DMAEN2 : 1; /*!< [28..28] desc DMAEN2 */ + __IOM uint32_t DMAUDRIE2 : 1; /*!< [29..29] desc DMAUDRIE2 */ + } CR0_f; + } ; + + union { + __IOM uint32_t SWTRGR; /*!< (@ 0x00000004) Data register */ + + struct { + __IOM uint32_t SWTRIG1 : 1; /*!< [0..0] desc SWTRIG1 */ + __IOM uint32_t SWTRIG2 : 1; /*!< [1..1] desc SWTRIG2 */ + } SWTRGR_f; + } ; + + union { + __IOM uint32_t DHR12R1; /*!< (@ 0x00000008) Result register */ + + struct { + __IOM uint32_t DATA : 12; /*!< [11..0] desc DATA */ + } DHR12R1_f; + } ; + + union { + __IOM uint32_t DHR12L1; /*!< (@ 0x0000000C) Result register */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t DATA : 12; /*!< [15..4] desc DATA */ + }DHR12L1_f; + } ; + + union { + __IOM uint32_t DHR8R1; /*!< (@ 0x00000010) Result register */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t DATA : 4; /*!< [7..4] desc DATA */ + } DHR8R1_f; + } ; + + union { + __IOM uint32_t DHR12R2; /*!< (@ 0x00000014) Result register */ + + struct { + __IOM uint32_t DATA : 12; /*!< [11..0] desc DATA */ + } DHR12R2_f; + } ; + + union { + __IOM uint32_t DHR12L2; /*!< (@ 0x00000018) Result register */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t DATA : 12; /*!< [15..4] desc DATA */ + } DHR12L2_f; + } ; + + union { + __IOM uint32_t DHR8R2; /*!< (@ 0x0000001C) Result register */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t DATA : 4; /*!< [7..4] desc DATA */ + } DHR8R2_f; + } ; + + union { + __IOM uint32_t DHR12RD; /*!< (@ 0x00000020) Result register */ + + struct { + __IOM uint32_t C1DATA : 12; /*!< [11..0] desc C1DATA */ + __IM uint32_t : 4; + __IOM uint32_t C2DATA : 12; /*!< [27..16] desc C2DATA */ + } DHR12RD_f; + } ; + + union { + __IOM uint32_t DHR12LD; /*!< (@ 0x00000024) Result register */ + + struct { + __IM uint32_t : 4; + __IOM uint32_t C1DATA : 12; /*!< [15..4] desc C1DATA */ + __IM uint32_t : 4; + __IOM uint32_t C2DATA : 12; /*!< [31..20] desc C2DATA */ + } DHR12LD_f; + } ; + + union { + __IOM uint32_t DHR8RD; /*!< (@ 0x00000028) Result register */ + + struct { + __IOM uint32_t C1DATA : 8; /*!< [7..0] desc C1DATA */ + __IOM uint32_t C2DATA : 8; /*!< [15..8] desc C2DATA */ + } DHR8RD_f; + } ; + + union { + __IOM uint32_t DOR1; /*!< (@ 0x0000002C) Result register */ + + struct { + __IOM uint32_t DATA : 12; /*!< [12..0] desc DATA */ + __IM uint32_t : 3; + __IOM uint32_t DMAUDR : 1; /*!< [15..15] desc DMAUDR */ + } DOR1_f; + } ; + + union { + __IOM uint32_t DOR2; /*!< (@ 0x00000030) Result register */ + + struct { + __IOM uint32_t DATA : 12; /*!< [11..0] desc DATA */ + __IM uint32_t : 3; + __IOM uint32_t DMAUDR : 1; /*!< [15..15] desc DMAUDR */ + } DOR2_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000034) Result register */ + + struct { + __IOM uint32_t C1OUT : 1; /*!< [0..0] desc C1OUT */ + __IOM uint32_t C2OUT : 1; /*!< [1..1] desc C2OUT */ + } CR1_f; + } ; +} DAC_TypeDef; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc DMA (DMA) + */ + +typedef struct { /*!< (@ 0x40020000) DMA Structure */ + + union { + __IM uint32_t ISR; /*!< (@ 0x00000000) Interrupt status register */ + + struct { + __IM uint32_t TC1 : 1; /*!< [0..0] desc TC1 */ + __IM uint32_t TE1 : 1; /*!< [1..1] desc TE1 */ + __IM uint32_t : 2; + __IM uint32_t TC2 : 1; /*!< [4..4] desc TC2 */ + __IM uint32_t TE2 : 1; /*!< [5..5] desc TE2 */ + __IM uint32_t : 2; + __IM uint32_t TC3 : 1; /*!< [8..8] desc TC3 */ + __IM uint32_t TE3 : 1; /*!< [9..9] desc TE3 */ + __IM uint32_t : 2; + __IM uint32_t TC4 : 1; /*!< [12..12] desc TC4 */ + __IM uint32_t TE4 : 1; /*!< [13..13] desc TE4 */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000004) Interrupt flag clear register */ + + struct { + __IOM uint32_t TC1 : 1; /*!< [0..0] desc TC1 */ + __IOM uint32_t TE1 : 1; /*!< [1..1] desc TE1 */ + __IM uint32_t : 2; + __IOM uint32_t TC2 : 1; /*!< [4..4] desc TC2 */ + __IOM uint32_t TE2 : 1; /*!< [5..5] desc TE2 */ + __IM uint32_t : 2; + __IOM uint32_t TC3 : 1; /*!< [8..8] desc TC3 */ + __IOM uint32_t TE3 : 1; /*!< [9..9] desc TE3 */ + __IM uint32_t : 2; + __IOM uint32_t TC4 : 1; /*!< [12..12] desc TC4 */ + __IOM uint32_t TE4 : 1; /*!< [13..13] desc TE4 */ + } ICR_f; + } ; + __IM uint32_t RESERVED[6]; + + union { + __IOM uint32_t CSR1; /*!< (@ 0x00000020) Channel1 control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IOM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + __IOM uint32_t RESTART : 1; /*!< [11..11] desc RESTART */ + __IM uint32_t TC : 1; /*!< [12..12] desc TC */ + __IM uint32_t TE : 1; /*!< [13..13] desc TE */ + __IOM uint32_t SRCLOAD : 1; /*!< [14..14] desc SRCLOAD */ + __IOM uint32_t DSTLOAD : 1; /*!< [15..15] desc DSTLOAD */ + } CSR1_f; + } ; + + union { + __IOM uint32_t CNT1; /*!< (@ 0x00000024) Channel1 counter register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT1_f; + } ; + + union { + __IOM uint32_t SRCADDR1; /*!< (@ 0x00000028) Channel1 source address register */ + + struct { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR1_f; + } ; + + union { + __IOM uint32_t DSTADDR1; /*!< (@ 0x0000002C) Channel1 destination address register */ + + struct { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR1_f; + } ; + + union { + __IOM uint32_t TRIG1; /*!< (@ 0x00000030) Channel1 trigger register */ + + struct { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG1_f; + } ; + + union { + __IOM uint32_t CCNT1; /*!< (@ 0x00000034) Channel1 trigger register */ + + struct { + __IOM uint32_t CCNT : 16; /*!< [15..0] desc CCNT */ + __IOM uint32_t CREPEAT : 4; /*!< [19..16] desc CREPEAT */ + } CCNT1_f; + } ; + + union { + __IM uint32_t CSRCADDR1; /*!< (@ 0x00000038) Channel1 source address register */ + + struct { + __IM uint32_t CSRCADDR : 32; /*!< [31..0] desc CSRCADDR */ + } CSRCADDR1_f; + } ; + + union { + __IM uint32_t CDSTADDR1; /*!< (@ 0x0000003C) Channel1 destination address register */ + + struct { + __IM uint32_t CDSTADDR : 32; /*!< [31..0] desc CDSTADDR */ + } CDSTADDR1_f; + } ; + + union { + __IOM uint32_t CSR2; /*!< (@ 0x00000040) Channel1 control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IOM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + __IOM uint32_t RESTART : 1; /*!< [11..11] desc RESTART */ + __IM uint32_t TC : 1; /*!< [12..12] desc TC */ + __IM uint32_t TE : 1; /*!< [13..13] desc TE */ + __IOM uint32_t SRCLOAD : 1; /*!< [14..14] desc SRCLOAD */ + __IOM uint32_t DSTLOAD : 1; /*!< [15..15] desc DSTLOAD */ + } CSR2_f; + } ; + + union { + __IOM uint32_t CNT2; /*!< (@ 0x00000044) Channel1 counter register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT2_f; + } ; + + union { + __IOM uint32_t SRCADDR2; /*!< (@ 0x00000048) Channel1 source address register */ + + struct { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR2_f; + } ; + + union { + __IOM uint32_t DSTADDR2; /*!< (@ 0x0000004C) Channel1 destination address register */ + + struct { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR2_f; + } ; + + union { + __IOM uint32_t TRIG2; /*!< (@ 0x00000050) Channel1 trigger register */ + + struct { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG2_f; + } ; + + union { + __IOM uint32_t CCNT2; /*!< (@ 0x00000054) Channel1 trigger register */ + + struct { + __IOM uint32_t CCNT : 16; /*!< [15..0] desc CCNT */ + __IOM uint32_t CREPEAT : 4; /*!< [19..16] desc CREPEAT */ + } CCNT2_f; + } ; + + union { + __IM uint32_t CSRCADDR2; /*!< (@ 0x00000058) Channel1 source address register */ + + struct { + __IM uint32_t CSRCADDR : 32; /*!< [31..0] desc CSRCADDR */ + } CSRCADDR2_f; + } ; + + union { + __IM uint32_t CDSTADDR2; /*!< (@ 0x0000005C) Channel1 destination address register */ + + struct { + __IM uint32_t CDSTADDR : 32; /*!< [31..0] desc CDSTADDR */ + } CDSTADDR2_f; + } ; + + union { + __IOM uint32_t CSR3; /*!< (@ 0x00000060) Channel1 control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IOM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + __IOM uint32_t RESTART : 1; /*!< [11..11] desc RESTART */ + __IM uint32_t TC : 1; /*!< [12..12] desc TC */ + __IM uint32_t TE : 1; /*!< [13..13] desc TE */ + __IOM uint32_t SRCLOAD : 1; /*!< [14..14] desc SRCLOAD */ + __IOM uint32_t DSTLOAD : 1; /*!< [15..15] desc DSTLOAD */ + } CSR3_f; + } ; + + union { + __IOM uint32_t CNT3; /*!< (@ 0x00000064) Channel1 counter register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT3_f; + } ; + + union { + __IOM uint32_t SRCADDR3; /*!< (@ 0x00000068) Channel1 source address register */ + + struct { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR3_f; + } ; + + union { + __IOM uint32_t DSTADDR3; /*!< (@ 0x0000006C) Channel1 destination address register */ + + struct { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR3_f; + } ; + + union { + __IOM uint32_t TRIG3; /*!< (@ 0x00000070) Channel1 trigger register */ + + struct { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG3_f; + } ; + + union { + __IOM uint32_t CCNT3; /*!< (@ 0x00000074) Channel1 trigger register */ + + struct { + __IOM uint32_t CCNT : 16; /*!< [15..0] desc CCNT */ + __IOM uint32_t CREPEAT : 4; /*!< [19..16] desc CREPEAT */ + } CCNT3_f; + } ; + + union { + __IM uint32_t CSRCADDR3; /*!< (@ 0x00000078) Channel1 source address register */ + + struct { + __IM uint32_t CSRCADDR : 32; /*!< [31..0] desc CSRCADDR */ + } CSRCADDR3_f; + } ; + + union { + __IM uint32_t CDSTADDR3; /*!< (@ 0x0000007C) Channel1 destination address register */ + + struct { + __IM uint32_t CDSTADDR : 32; /*!< [31..0] desc CDSTADDR */ + } CDSTADDR3_f; + } ; + + union { + __IOM uint32_t CSR4; /*!< (@ 0x00000080) Channel1 control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IOM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + __IOM uint32_t RESTART : 1; /*!< [11..11] desc RESTART */ + __IM uint32_t TC : 1; /*!< [12..12] desc TC */ + __IM uint32_t TE : 1; /*!< [13..13] desc TE */ + __IOM uint32_t SRCLOAD : 1; /*!< [14..14] desc SRCLOAD */ + __IOM uint32_t DSTLOAD : 1; /*!< [15..15] desc DSTLOAD */ + } CSR4_f; + } ; + + union { + __IOM uint32_t CNT4; /*!< (@ 0x00000084) Channel1 counter register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT4_f; + } ; + + union { + __IOM uint32_t SRCADDR4; /*!< (@ 0x00000088) Channel1 source address register */ + + struct { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR4_f; + } ; + + union { + __IOM uint32_t DSTADDR4; /*!< (@ 0x0000008C) Channel1 destination address register */ + + struct { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR4_f; + } ; + + union { + __IOM uint32_t TRIG4; /*!< (@ 0x00000090) Channel1 trigger register */ + + struct { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG4_f; + } ; + + union { + __IOM uint32_t CCNT4; /*!< (@ 0x00000094) Channel1 trigger register */ + + struct { + __IOM uint32_t CCNT : 16; /*!< [15..0] desc CCNT */ + __IOM uint32_t CREPEAT : 4; /*!< [19..16] desc CREPEAT */ + } CCNT4_f; + } ; + + union { + __IM uint32_t CSRCADDR4; /*!< (@ 0x00000098) Channel1 source address register */ + + struct { + __IM uint32_t CSRCADDR : 32; /*!< [31..0] desc CSRCADDR */ + } CSRCADDR4_f; + } ; + + union { + __IM uint32_t CDSTADDR4; /*!< (@ 0x0000009C) Channel1 destination address register */ + + struct { + __IM uint32_t CDSTADDR : 32; /*!< [31..0] desc CDSTADDR */ + } CDSTADDR4_f; + } ; +} DMA_TypeDef; /*!< Size = 160 (0xa0) */ + + + +/* =========================================================================================================================== */ +/* ================ DMACHANNEL1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DMA Channel 1 (DMACHANNEL1) + */ + +typedef struct { /*!< (@ 0x40020020) DMACHANNEL1 Structure */ + + union { + __IOM uint32_t CSR; /*!< (@ 0x00000000) Channel1 control and status register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t TCIE : 1; /*!< [1..1] desc TCIE */ + __IOM uint32_t TEIE : 1; /*!< [2..2] desc TEIE */ + __IOM uint32_t TRANS : 1; /*!< [3..3] desc TRANS */ + __IOM uint32_t SRCINC : 1; /*!< [4..4] desc SRCINC */ + __IOM uint32_t DSTINC : 1; /*!< [5..5] desc DSTINC */ + __IOM uint32_t SIZE : 2; /*!< [7..6] desc SIZE */ + __IOM uint32_t STATUS : 3; /*!< [10..8] desc STATUS */ + __IOM uint32_t RESTART : 1; /*!< [11..11] desc RESTART */ + __IM uint32_t TC : 1; /*!< [12..12] desc TC */ + __IM uint32_t TE : 1; /*!< [13..13] desc TE */ + __IOM uint32_t SRCLOAD : 1; /*!< [14..14] desc SRCLOAD */ + __IOM uint32_t DSTLOAD : 1; /*!< [15..15] desc DSTLOAD */ + } CSR_f; + } ; + + union { + __IOM uint32_t CNT; /*!< (@ 0x00000004) Channel1 counter register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IOM uint32_t REPEAT : 4; /*!< [19..16] desc REPEAT */ + } CNT_f; + } ; + + union { + __IOM uint32_t SRCADDR; /*!< (@ 0x00000008) Channel1 source address register */ + + struct { + __IOM uint32_t SRCADDR : 32; /*!< [31..0] desc SRCADDR */ + } SRCADDR_f; + } ; + + union { + __IOM uint32_t DSTADDR; /*!< (@ 0x0000000C) Channel1 destination address register */ + + struct { + __IOM uint32_t DSTADDR : 32; /*!< [31..0] desc DSTADDR */ + } DSTADDR_f; + } ; + + union { + __IOM uint32_t TRIG; /*!< (@ 0x00000010) Channel1 trigger register */ + + struct { + __IOM uint32_t TYPE : 1; /*!< [0..0] desc TYPE */ + __IOM uint32_t SOFTSRC : 1; /*!< [1..1] desc SOFTSRC */ + __IOM uint32_t HARDSRC : 6; /*!< [7..2] desc HARDSRC */ + } TRIG_f; + } ; + + union { + __IOM uint32_t CCNT; /*!< (@ 0x00000014) Channel1 trigger register */ + + struct { + __IOM uint32_t CCNT : 16; /*!< [15..0] desc CCNT */ + __IOM uint32_t CREPEAT : 4; /*!< [19..16] desc CREPEAT */ + } CCNT_f; + } ; + + union { + __IM uint32_t CSRCADDR; /*!< (@ 0x00000018) Channel1 source address register */ + + struct { + __IM uint32_t CSRCADDR : 32; /*!< [31..0] desc CSRCADDR */ + } CSRCADDR_f; + } ; + + union { + __IM uint32_t CDSTADDR; /*!< (@ 0x0000001C) Channel1 destination address register */ + + struct { + __IM uint32_t CDSTADDR : 32; /*!< [31..0] desc CDSTADDR */ + } CDSTADDR_f; + } ; +} DMACHANNEL_TypeDef; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ EAU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc EAU (EAU) + */ + +typedef struct { /*!< (@ 0x40023200) EAU Structure */ + + union { + __IOM uint32_t CSR; /*!< (@ 0x00000000) desc CSR */ + + struct { + __IOM uint32_t MODE : 2; /*!< [1..0] desc MODE */ + __IM uint32_t OVR : 1; /*!< [2..2] desc OVR */ + __IM uint32_t ZERO : 1; /*!< [3..3] desc ZERO */ + __IM uint32_t BUSY : 1; /*!< [4..4] desc BUSY */ + } CSR_f; + } ; + + union { + __IOM uint32_t DIVIDEND; /*!< (@ 0x00000004) desc DIVIDEND */ + + struct { + __IOM uint32_t DIVIDEND : 32; /*!< [31..0] desc DIVIDEND */ + } DIVIDEND_f; + } ; + + union { + __IOM uint32_t DIVISOR; /*!< (@ 0x00000008) desc DIVISOR */ + + struct { + __IOM uint32_t DIVISOR : 32; /*!< [31..0] desc DIVISOR */ + } DIVISOR_f; + } ; + + union { + __IM uint32_t QUOTIENT; /*!< (@ 0x0000000C) desc QUOTIENT */ + + struct { + __IM uint32_t QUOTIENT : 32; /*!< [31..0] desc QUOTIENT */ + } QUOTIENT_f; + } ; + + union { + __IM uint32_t REMAINDER; /*!< (@ 0x00000010) desc REMAINDER */ + + struct { + __IM uint32_t REMAINDER : 32; /*!< [31..0] desc REMAINDER */ + } REMAINDER_f; + } ; +} EAU_TypeDef; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ FLASH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc FLASH (FLASH) + */ + +typedef struct { /*!< (@ 0x40022000) FLASH Structure */ + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t MODE : 2; /*!< [1..0] desc MODE */ + __IM uint32_t : 3; + __IM uint32_t SECURITY : 2; /*!< [6..5] desc SECURITY */ + __IM uint32_t : 9; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000004) Control register2 */ + + struct { + __IOM uint32_t WAIT : 3; /*!< [2..0] desc WAIT */ + __IOM uint32_t FETCH : 1; /*!< [3..3] desc FETCH */ + __IOM uint32_t CACHE : 1; /*!< [4..4] desc CACHE */ + __IOM uint32_t CACHEINVALID : 1; /*!< [5..5] desc CACHEINVALID */ + __IM uint32_t : 10; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR2_f; + } ; + + union { + __IOM uint32_t PAGELOCK; /*!< (@ 0x00000008) Page Write Erase Lock */ + + struct { + __IOM uint32_t LOCK0 : 1; /*!< [0..0] Page0 - 7 */ + __IOM uint32_t LOCK1 : 1; /*!< [1..1] Page8 - 15 */ + __IOM uint32_t LOCK2 : 1; /*!< [2..2] Page16 - 23 */ + __IOM uint32_t LOCK3 : 1; /*!< [3..3] Page24 - 31 */ + __IOM uint32_t LOCK4 : 1; /*!< [4..4] Page32 - 39 */ + __IOM uint32_t LOCK5 : 1; /*!< [5..5] Page40 - 47 */ + __IOM uint32_t LOCK6 : 1; /*!< [6..6] Page48 - 55 */ + __IOM uint32_t LOCK7 : 1; /*!< [7..7] Page56 - 63 */ + __IOM uint32_t LOCK8 : 1; /*!< [8..8] Page64 - 71 */ + __IOM uint32_t LOCK9 : 1; /*!< [9..9] Page72 - 79 */ + __IOM uint32_t LOCK10 : 1; /*!< [10..10] Page80 - 87 */ + __IOM uint32_t LOCK11 : 1; /*!< [11..11] Page88 - 95 */ + __IOM uint32_t LOCK12 : 1; /*!< [12..12] Page96 - 103 */ + __IOM uint32_t LOCK13 : 1; /*!< [13..13] Page104 - 111 */ + __IOM uint32_t LOCK14 : 1; /*!< [14..14] Page112 - 119 */ + __IOM uint32_t LOCK15 : 1; /*!< [15..15] Page120 - 127 */ + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } PAGELOCK_f; + } ; + __IM uint32_t RESERVED[5]; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000020) Interrupt enable register */ + + struct { + __IOM uint32_t PC : 1; /*!< [0..0] desc PC */ + __IOM uint32_t PAGELOCK : 1; /*!< [1..1] desc PAGELOCK */ + __IOM uint32_t SDKERR : 1; /*!< [2..2] desc SDKERR */ + __IOM uint32_t CACHEON : 1; /*!< [3..3] desc CACHEON */ + __IOM uint32_t PROG : 1; /*!< [4..4] desc PROG */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000024) Interrupt status register */ + + struct { + __IM uint32_t PC : 1; /*!< [0..0] desc PC */ + __IM uint32_t PAGELOCK : 1; /*!< [1..1] desc PAGELOCK */ + __IM uint32_t SDKERR : 1; /*!< [2..2] desc SDKERR */ + __IM uint32_t CACHEON : 1; /*!< [3..3] desc CACHEON */ + __IM uint32_t PROG : 1; /*!< [4..4] desc PROG */ + __IM uint32_t BUSY : 1; /*!< [5..5] desc BUSY */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000028) Interrupt flag clear register */ + + struct { + __IOM uint32_t PC : 1; /*!< [0..0] desc PC */ + __IOM uint32_t PAGELOCK : 1; /*!< [1..1] desc PAGELOCK */ + __IOM uint32_t SDKERR : 1; /*!< [2..2] desc SDKERR */ + __IOM uint32_t CACHEON : 1; /*!< [3..3] desc CACHEON */ + __IOM uint32_t PROG : 1; /*!< [4..4] desc PROG */ + } ICR_f; + } ; + __IM uint32_t RESERVED1[17]; + + union { + __IM uint32_t SDKCFR; /*!< (@ 0x00000070) SDK config register */ + + struct { + __IM uint32_t START : 7; /*!< [6..0] desc START */ + uint32_t : 1; + __IM uint32_t END : 7; /*!< [14..8] desc END */ + } SDKCFR_f; + } ; +} FLASH_TypeDef; /*!< Size = 116 (0x74) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc GPIOA (GPIOA) + */ + +typedef struct { /*!< (@ 0x48000000) GPIOA Structure */ + + union { + __IOM uint32_t DIR; /*!< (@ 0x00000000) desc DIR */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } DIR_f; + } ; + + union { + __IOM uint32_t OPENDRAIN; /*!< (@ 0x00000004) desc OPENDRAIN */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } OPENDRAIN_f; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t PUR; /*!< (@ 0x00000010) desc PUR */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } PUR_f; + } ; + + union { + __IOM uint32_t AFRH; /*!< (@ 0x00000014) desc AFRH */ + + struct { + __IOM uint32_t PIN8 : 4; /*!< [2..0] desc AFR8 */ + __IOM uint32_t PIN9 : 4; /*!< [6..4] desc AFR9 */ + __IOM uint32_t PIN10 : 4; /*!< [10..8] desc AFR10 */ + __IOM uint32_t PIN11 : 4; /*!< [14..12] desc AFR11 */ + __IOM uint32_t PIN12 : 4; /*!< [18..16] desc AFR12 */ + __IOM uint32_t PIN13 : 4; /*!< [22..20] desc AFR13 */ + __IOM uint32_t PIN14 : 4; /*!< [26..24] desc AFR14 */ + __IOM uint32_t PIN15 : 4; /*!< [30..28] desc AFR15 */ + } AFRH_f; + } ; + + union { + __IOM uint32_t AFRL; /*!< (@ 0x00000018) desc AFRL */ + + struct { + __IOM uint32_t PIN0 : 4; /*!< [2..0] desc AFR0 */ + __IOM uint32_t PIN1 : 4; /*!< [6..4] desc AFR1 */ + __IOM uint32_t PIN2 : 4; /*!< [10..8] desc AFR2 */ + __IOM uint32_t PIN3 : 4; /*!< [14..12] desc AFR3 */ + __IOM uint32_t PIN4 : 4; /*!< [18..16] desc AFR4 */ + __IOM uint32_t PIN5 : 4; /*!< [22..20] desc AFR5 */ + __IOM uint32_t PIN6 : 4; /*!< [26..24] desc AFR6 */ + __IOM uint32_t PIN7 : 4; /*!< [30..28] desc AFR7 */ + } AFRL_f; + } ; + + union { + __IOM uint32_t ANALOG; /*!< (@ 0x0000001C) desc ANALOG */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ANALOG_f; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t RISEIE; /*!< (@ 0x00000024) Interrupt enable register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } RISEIE_f; + } ; + + union { + __IOM uint32_t FALLIE; /*!< (@ 0x00000028) Interrupt enable register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } FALLIE_f; + } ; + __IM uint32_t RESERVED2[2]; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000034) Interrupt status register */ + + struct { + __IM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000038) Interrupt flag clear register */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ICR_f; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t FILTER; /*!< (@ 0x00000040) desc FILTER */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + __IOM uint32_t FLTCLK : 3; /*!< [18..16] desc FLTCLK */ + } FILTER_f; + } ; + __IM uint32_t RESERVED4[3]; + + union { + __IM uint32_t IDR; /*!< (@ 0x00000050) desc IDR */ + + struct { + __IM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } IDR_f; + } ; + + union { + __IOM uint32_t ODR; /*!< (@ 0x00000054) desc ODR */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } ODR_f; + } ; + + union { + __IOM uint32_t BRR; /*!< (@ 0x00000058) desc BRR */ + + struct { + __IOM uint32_t BRR0 : 1; /*!< [0..0] desc BRR0 */ + __IOM uint32_t BRR1 : 1; /*!< [1..1] desc BRR1 */ + __IOM uint32_t BRR2 : 1; /*!< [2..2] desc BRR2 */ + __IOM uint32_t BRR3 : 1; /*!< [3..3] desc BRR3 */ + __IOM uint32_t BRR4 : 1; /*!< [4..4] desc BRR4 */ + __IOM uint32_t BRR5 : 1; /*!< [5..5] desc BRR5 */ + __IOM uint32_t BRR6 : 1; /*!< [6..6] desc BRR6 */ + __IOM uint32_t BRR7 : 1; /*!< [7..7] desc BRR7 */ + __IOM uint32_t BRR8 : 1; /*!< [8..8] desc BRR8 */ + __IOM uint32_t BRR9 : 1; /*!< [9..9] desc BRR9 */ + __IOM uint32_t BRR10 : 1; /*!< [10..10] desc BRR10 */ + __IOM uint32_t BRR11 : 1; /*!< [11..11] desc BRR11 */ + __IOM uint32_t BRR12 : 1; /*!< [12..12] desc BRR12 */ + __IOM uint32_t BRR13 : 1; /*!< [13..13] desc BRR13 */ + __IOM uint32_t BRR14 : 1; /*!< [14..14] desc BRR14 */ + __IOM uint32_t BRR15 : 1; /*!< [15..15] desc BRR15 */ + } BRR_f; + } ; + + union { + __IOM uint32_t BSRR; /*!< (@ 0x0000005C) desc BSRR */ + + struct { + __IOM uint32_t BSS0 : 1; /*!< [0..0] desc BSS0 */ + __IOM uint32_t BSS1 : 1; /*!< [1..1] desc BSS1 */ + __IOM uint32_t BSS2 : 1; /*!< [2..2] desc BSS2 */ + __IOM uint32_t BSS3 : 1; /*!< [3..3] desc BSS3 */ + __IOM uint32_t BSS4 : 1; /*!< [4..4] desc BSS4 */ + __IOM uint32_t BSS5 : 1; /*!< [5..5] desc BSS5 */ + __IOM uint32_t BSS6 : 1; /*!< [6..6] desc BSS6 */ + __IOM uint32_t BSS7 : 1; /*!< [7..7] desc BSS7 */ + __IOM uint32_t BSS8 : 1; /*!< [8..8] desc BSS8 */ + __IOM uint32_t BSS9 : 1; /*!< [9..9] desc BSS9 */ + __IOM uint32_t BSS10 : 1; /*!< [10..10] desc BSS10 */ + __IOM uint32_t BSS11 : 1; /*!< [11..11] desc BSS11 */ + __IOM uint32_t BSS12 : 1; /*!< [12..12] desc BSS12 */ + __IOM uint32_t BSS13 : 1; /*!< [13..13] desc BSS13 */ + __IOM uint32_t BSS14 : 1; /*!< [14..14] desc BSS14 */ + __IOM uint32_t BSS15 : 1; /*!< [15..15] desc BSS15 */ + __IOM uint32_t BRR0 : 1; /*!< [16..16] desc BRR0 */ + __IOM uint32_t BRR1 : 1; /*!< [17..17] desc BRR1 */ + __IOM uint32_t BRR2 : 1; /*!< [18..18] desc BRR2 */ + __IOM uint32_t BRR3 : 1; /*!< [19..19] desc BRR3 */ + __IOM uint32_t BRR4 : 1; /*!< [20..20] desc BRR4 */ + __IOM uint32_t BRR5 : 1; /*!< [21..21] desc BRR5 */ + __IOM uint32_t BRR6 : 1; /*!< [22..22] desc BRR6 */ + __IOM uint32_t BRR7 : 1; /*!< [23..23] desc BRR7 */ + __IOM uint32_t BRR8 : 1; /*!< [24..24] desc BRR8 */ + __IOM uint32_t BRR9 : 1; /*!< [25..25] desc BRR9 */ + __IOM uint32_t BRR10 : 1; /*!< [26..26] desc BRR10 */ + __IOM uint32_t BRR11 : 1; /*!< [27..27] desc BRR11 */ + __IOM uint32_t BRR12 : 1; /*!< [28..28] desc BRR12 */ + __IOM uint32_t BRR13 : 1; /*!< [29..29] desc BRR13 */ + __IOM uint32_t BRR14 : 1; /*!< [30..30] desc BRR14 */ + __IOM uint32_t BRR15 : 1; /*!< [31..31] desc BRR15 */ + } BSRR_f; + } ; + + union { + __IOM uint32_t TOG; /*!< (@ 0x00000060) desc TOG */ + + struct { + __IOM uint32_t PIN0 : 1; /*!< [0..0] desc PIN0 */ + __IOM uint32_t PIN1 : 1; /*!< [1..1] desc PIN1 */ + __IOM uint32_t PIN2 : 1; /*!< [2..2] desc PIN2 */ + __IOM uint32_t PIN3 : 1; /*!< [3..3] desc PIN3 */ + __IOM uint32_t PIN4 : 1; /*!< [4..4] desc PIN4 */ + __IOM uint32_t PIN5 : 1; /*!< [5..5] desc PIN5 */ + __IOM uint32_t PIN6 : 1; /*!< [6..6] desc PIN6 */ + __IOM uint32_t PIN7 : 1; /*!< [7..7] desc PIN7 */ + __IOM uint32_t PIN8 : 1; /*!< [8..8] desc PIN8 */ + __IOM uint32_t PIN9 : 1; /*!< [9..9] desc PIN9 */ + __IOM uint32_t PIN10 : 1; /*!< [10..10] desc PIN10 */ + __IOM uint32_t PIN11 : 1; /*!< [11..11] desc PIN11 */ + __IOM uint32_t PIN12 : 1; /*!< [12..12] desc PIN12 */ + __IOM uint32_t PIN13 : 1; /*!< [13..13] desc PIN13 */ + __IOM uint32_t PIN14 : 1; /*!< [14..14] desc PIN14 */ + __IOM uint32_t PIN15 : 1; /*!< [15..15] desc PIN15 */ + } TOG_f; + } ; +} GPIO_TypeDef; /*!< Size = 100 (0x64) */ + + + +/* =========================================================================================================================== */ +/* ================ GTIM1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Timer 1 (GTIM1) + */ + +typedef struct { /*!< (@ 0x40001800) GTIM1 Structure */ + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] desc CEN */ + __IOM uint32_t UDIS : 1; /*!< [1..1] desc UDIS */ + __IOM uint32_t URS : 1; /*!< [2..2] desc URS */ + __IOM uint32_t OPM : 1; /*!< [3..3] desc OPM */ + __IOM uint32_t DIR : 1; /*!< [4..4] desc DIR */ + __IOM uint32_t CMS : 2; /*!< [6..5] desc CMS */ + __IOM uint32_t ARPE : 1; /*!< [7..7] desc ARPE */ + __IOM uint32_t CKD : 2; /*!< [9..8] desc CKD */ + __IM uint32_t : 1; + __IOM uint32_t UIFREMAP : 1; /*!< [11..11] desc UIFREMAP */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000004) Control register2 */ + + struct { + __IM uint32_t : 3; + __IOM uint32_t CCDS : 1; /*!< [3..3] desc CCDS */ + __IOM uint32_t MMS : 3; /*!< [6..4] desc MMS */ + __IOM uint32_t TI1S : 1; /*!< [7..7] desc TI1S */ + __IM uint32_t : 17; + __IOM uint32_t MMSH : 2; /*!< [26..25] desc MMSH */ + } CR2_f; + } ; + + union { + __IOM uint32_t SMCR; /*!< (@ 0x00000008) Slave Mode control register */ + + struct { + __IOM uint32_t SMS : 3; /*!< [2..0] desc SMS */ + __IOM uint32_t OCCS : 1; /*!< [3..3] desc OCCS */ + __IOM uint32_t TS : 3; /*!< [6..4] desc TS */ + __IOM uint32_t MSM : 1; /*!< [7..7] desc MSM */ + __IOM uint32_t ETF : 4; /*!< [11..8] desc ETF */ + __IOM uint32_t ETPS : 2; /*!< [13..12] desc ETPS */ + __IOM uint32_t ECE : 1; /*!< [14..14] desc ECE */ + __IOM uint32_t ETP : 1; /*!< [15..15] desc ETP */ + __IOM uint32_t SMSH : 1; /*!< [16..16] desc SMSH */ + __IM uint32_t : 3; + __IOM uint32_t TSH : 2; /*!< [21..20] desc TSH */ + __IM uint32_t : 2; + __IOM uint32_t SMSPE : 1; /*!< [24..24] desc SMSPE */ + __IOM uint32_t SMSPS : 1; /*!< [25..25] desc SMSPS */ + } SMCR_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x0000000C) Interrupt control register */ + + struct { + __IOM uint32_t UIE : 1; /*!< [0..0] desc UIE */ + __IOM uint32_t CC1IE : 1; /*!< [1..1] desc CC1IE */ + __IOM uint32_t CC2IE : 1; /*!< [2..2] desc CC2IE */ + __IOM uint32_t CC3IE : 1; /*!< [3..3] desc CC3IE */ + __IOM uint32_t CC4IE : 1; /*!< [4..4] desc CC4IE */ + __IM uint32_t : 1; + __IOM uint32_t TIE : 1; /*!< [6..6] desc TIE */ + __IM uint32_t : 1; + __IOM uint32_t UDE : 1; /*!< [8.8] desc UDE */ + __IOM uint32_t CC1DE : 1; /*!< [9.9] desc CC1DE */ + __IOM uint32_t CC2DE : 1; /*!< [10..10] desc CC2DE */ + __IOM uint32_t CC3DE : 1; /*!< [11..11] desc CC3DE */ + __IOM uint32_t CC4DE : 1; /*!< [12..12] desc CC4DE */ + __IM uint32_t : 1; + __IOM uint32_t TDE : 1; /*!< [14..14] desc TDE */ + __IM uint32_t : 5; + __IOM uint32_t IDXIE : 1; /*!< [20..20] desc IDXIE */ + __IOM uint32_t DIRIE : 1; /*!< [21..21] desc DIRIE */ + __IOM uint32_t IERRIE : 1; /*!< [22..22] desc IERRIE */ + __IOM uint32_t TERRIE : 1; /*!< [23..23] desc TERRIE */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000010) Interrupt status register */ + + struct { + __IM uint32_t UIF : 1; /*!< [0..0] desc UIF */ + __IM uint32_t CC1IF : 1; /*!< [1..1] desc CC1IF */ + __IM uint32_t CC2IF : 1; /*!< [2..2] desc CC2IF */ + __IM uint32_t CC3IF : 1; /*!< [3..3] desc CC3IF */ + __IM uint32_t CC4IF : 1; /*!< [4..4] desc CC4IF */ + __IM uint32_t : 1; + __IM uint32_t TIF : 1; /*!< [6..6] desc TIF */ + __IM uint32_t : 2; + __IM uint32_t CC1OF : 1; /*!< [9..9] desc CC1OF */ + __IM uint32_t CC2OF : 1; /*!< [10..10] desc CC2OF */ + __IM uint32_t CC3OF : 1; /*!< [11..11] desc CC3OF */ + __IM uint32_t CC4OF : 1; /*!< [12..12] desc CC4OF */ + __IM uint32_t : 7; + __IM uint32_t IDXF : 1; /*!< [20..20] desc IDXF */ + __IM uint32_t DIRF : 1; /*!< [21..21] desc DIRF */ + __IM uint32_t IERRF : 1; /*!< [22..22] desc IERRF */ + __IM uint32_t TERRF : 1; /*!< [23..23] desc TERRF */ + } ISR_f; + } ; + + union { + __IOM uint32_t EGR; /*!< (@ 0x00000014) Event Generate register */ + + struct { + __IOM uint32_t UG : 1; /*!< [0..0] desc UG */ + __IOM uint32_t CC1G : 1; /*!< [1..1] desc CC1G */ + __IOM uint32_t CC2G : 1; /*!< [2..2] desc CC2G */ + __IOM uint32_t CC3G : 1; /*!< [3..3] desc CC3G */ + __IOM uint32_t CC4G : 1; /*!< [4..4] desc CC4G */ + __IM uint32_t : 1; + __IOM uint32_t TG : 1; /*!< [6..6] desc TG */ + } EGR_f; + } ; + + union { + union { + __IOM uint32_t CCMR1CAP; /*!< (@ 0x00000018) Capture control Register1 */ + + struct { + __IOM uint32_t CC1S : 2; /*!< [1..0] desc CC1S */ + __IOM uint32_t IC1PSC : 2; /*!< [3..2] desc IC1PSC */ + __IOM uint32_t IC1F : 4; /*!< [7..4] desc IC1F */ + __IOM uint32_t CC2S : 2; /*!< [9..8] desc CC2S */ + __IOM uint32_t IC2PSC : 2; /*!< [11..10] desc IC2PSC */ + __IOM uint32_t IC2F : 4; /*!< [15..12] desc IC2F */ + } CCMR1CAP_f; + } ; + + union { + __IOM uint32_t CCMR1CMP; /*!< (@ 0x00000018) Compare control Register1 */ + + struct { + __IOM uint32_t CC1S : 2; /*!< [1..0] desc CC1S */ + __IOM uint32_t OC1FE : 1; /*!< [2..2] desc OC1FE */ + __IOM uint32_t OC1PE : 1; /*!< [3..3] desc OC1PE */ + __IOM uint32_t OC1M : 3; /*!< [6..4] desc OC1M */ + __IOM uint32_t OC1CE : 1; /*!< [7..7] desc OC1CE */ + __IOM uint32_t CC2S : 2; /*!< [9..8] desc CC2S */ + __IOM uint32_t OC2FE : 1; /*!< [10..10] desc OC2FE */ + __IOM uint32_t OC2PE : 1; /*!< [11..11] desc OC2PE */ + __IOM uint32_t OC2M : 3; /*!< [14..12] desc OC2M */ + __IOM uint32_t OC2CE : 1; /*!< [15..15] desc OC2CE */ + __IOM uint32_t OC1MH : 1; /*!< [16..16] desc OC1MH */ + __IM uint32_t : 7; + __IOM uint32_t OC2MH : 1; /*!< [24..24] desc OC2MH */ + } CCMR1CMP_f; + } ; + }; + + union { + union { + __IOM uint32_t CCMR2CAP; /*!< (@ 0x0000001C) Capture control Register2 */ + + struct { + __IOM uint32_t CC3S : 2; /*!< [1..0] desc CC3S */ + __IOM uint32_t IC3PSC : 2; /*!< [3..2] desc IC3PSC */ + __IOM uint32_t IC3F : 4; /*!< [7..4] desc IC3F */ + __IOM uint32_t CC4S : 2; /*!< [9..8] desc CC4S */ + __IOM uint32_t IC4PSC : 2; /*!< [11..10] desc IC4PSC */ + __IOM uint32_t IC4F : 4; /*!< [15..12] desc IC4F */ + } CCMR2CAP_f; + } ; + + union { + __IOM uint32_t CCMR2CMP; /*!< (@ 0x0000001C) Compare control Register2 */ + + struct { + __IOM uint32_t CC3S : 2; /*!< [1..0] desc CC3S */ + __IOM uint32_t OC3FE : 1; /*!< [2..2] desc OC3FE */ + __IOM uint32_t OC3PE : 1; /*!< [3..3] desc OC3PE */ + __IOM uint32_t OC3M : 3; /*!< [6..4] desc OC3M */ + __IOM uint32_t OC3CE : 1; /*!< [7..7] desc OC3CE */ + __IOM uint32_t CC4S : 2; /*!< [9..8] desc CC4S */ + __IOM uint32_t OC4FE : 1; /*!< [10..10] desc OC4FE */ + __IOM uint32_t OC4PE : 1; /*!< [11..11] desc OC4PE */ + __IOM uint32_t OC4M : 3; /*!< [14..12] desc OC4M */ + __IOM uint32_t OC4CE : 1; /*!< [15..15] desc OC4CE */ + __IOM uint32_t OC3MH : 1; /*!< [16..16] desc OC3MH */ + __IM uint32_t : 7; + __IOM uint32_t OC4MH : 1; /*!< [24..24] desc OC4MH */ + } CCMR2CMP_f; + } ; + }; + + union { + __IOM uint32_t CCER; /*!< (@ 0x00000020) Capture compare Enable Register */ + + struct { + __IOM uint32_t CC1E : 1; /*!< [0..0] desc CC1E */ + __IOM uint32_t CC1P : 1; /*!< [1..1] desc CC1P */ + __IM uint32_t : 1; + __IOM uint32_t CC1NP : 1; /*!< [3..3] desc CC1NP */ + __IOM uint32_t CC2E : 1; /*!< [4..4] desc CC2E */ + __IOM uint32_t CC2P : 1; /*!< [5..5] desc CC2P */ + __IM uint32_t : 1; + __IOM uint32_t CC2NP : 1; /*!< [7..7] desc CC2NP */ + __IOM uint32_t CC3E : 1; /*!< [8..8] desc CC3E */ + __IOM uint32_t CC3P : 1; /*!< [9..9] desc CC3P */ + __IM uint32_t : 1; + __IOM uint32_t CC3NP : 1; /*!< [11..11] desc CC3NP */ + __IOM uint32_t CC4E : 1; /*!< [12..12] desc CC4E */ + __IOM uint32_t CC4P : 1; /*!< [13..13] desc CC4P */ + __IM uint32_t : 1; + __IOM uint32_t CC4NP : 1; /*!< [15..15] desc CC4NP */ + } CCER_f; + } ; + + union { + __IOM uint32_t CNT; /*!< (@ 0x00000024) Counter Register */ + + struct { + __IOM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + __IM uint32_t : 15; + __IM uint32_t UIFCPY : 1; /*!< [31..31] desc UIFCPY */ + } CNT_f; + } ; + + union { + __IOM uint32_t PSC; /*!< (@ 0x00000028) Prescaler Control Register */ + + struct { + __IOM uint32_t PSC : 16; /*!< [15..0] desc PSC */ + } PSC_f; + } ; + + union { + __IOM uint32_t ARR; /*!< (@ 0x0000002C) Auto Reload Register */ + + struct { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } ARR_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t CCR1; /*!< (@ 0x00000034) Capture control Register1 */ + + struct { + __IOM uint32_t CCR1 : 16; /*!< [15..0] desc CCR1 */ + } CCR1_f; + } ; + + union { + __IOM uint32_t CCR2; /*!< (@ 0x00000038) Capture control Register2 */ + + struct { + __IOM uint32_t CCR2 : 16; /*!< [15..0] desc CCR2 */ + } CCR2_f; + } ; + + union { + __IOM uint32_t CCR3; /*!< (@ 0x0000003C) Capture control Register3 */ + + struct { + __IOM uint32_t CCR3 : 16; /*!< [15..0] desc CCR3 */ + } CCR3_f; + } ; + + union { + __IOM uint32_t CCR4; /*!< (@ 0x00000040) Capture control Register4 */ + + struct { + __IOM uint32_t CCR4 : 16; /*!< [15..0] desc CCR4 */ + } CCR4_f; + } ; + __IM uint32_t RESERVED1[5]; + + union { + __IOM uint32_t ECR; /*!< (@ 0x00000058) Encoder control Register */ + + struct { + __IOM uint32_t IE : 1; /*!< [0..0] desc IE */ + __IOM uint32_t IDIR : 2; /*!< [2..1] desc IDIR */ + __IM uint32_t : 2; + __IOM uint32_t FIDX : 1; /*!< [5..5] desc FIDX */ + __IOM uint32_t IPOS : 2; /*!< [7..6] desc IPOS */ + } ECR_f; + } ; + + union { + __IOM uint32_t TISEL; /*!< (@ 0x0000005C) Timer Input Select Register */ + + struct { + __IOM uint32_t TI1SEL : 4; /*!< [3..0] desc TI1SEL */ + __IM uint32_t : 4; + __IOM uint32_t TI2SEL : 4; /*!< [11..8] desc TI2SEL */ + __IM uint32_t : 4; + __IOM uint32_t TI3SEL : 4; /*!< [19..16] desc TI3SEL */ + __IM uint32_t : 4; + __IOM uint32_t TI4SEL : 4; /*!< [27..24] desc TI4SEL */ + } TISEL_f; + } ; + + union { + __IOM uint32_t AF1; /*!< (@ 0x00000060) Alternate function Register1 */ + + struct { + __IM uint32_t : 14; + __IOM uint32_t ETRSEL : 4; /*!< [17..14] desc ETRSEL */ + } AF1_f; + } ; + + union { + __IOM uint32_t AF2; /*!< (@ 0x00000064) Alternate function Register2 */ + + struct { + __IM uint32_t : 16; + __IOM uint32_t OCRSEL : 3; /*!< [18..16] desc OCRSEL */ + } AF2_f; + } ; + __IM uint32_t RESERVED2[2]; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000070) Interrupt flag clear register */ + + struct { + __IOM uint32_t UIF : 1; /*!< [0..0] desc UIF */ + __IOM uint32_t CC1IF : 1; /*!< [1..1] desc CC1IF */ + __IOM uint32_t CC2IF : 1; /*!< [2..2] desc CC2IF */ + __IOM uint32_t CC3IF : 1; /*!< [3..3] desc CC3IF */ + __IOM uint32_t CC4IF : 1; /*!< [4..4] desc CC4IF */ + __IM uint32_t : 1; + __IOM uint32_t TIF : 1; /*!< [6..6] desc TIF */ + __IM uint32_t : 2; + __IOM uint32_t CC1OF : 1; /*!< [9..9] desc CC1OF */ + __IOM uint32_t CC2OF : 1; /*!< [10..10] desc CC2OF */ + __IOM uint32_t CC3OF : 1; /*!< [11..11] desc CC3OF */ + __IOM uint32_t CC4OF : 1; /*!< [12..12] desc CC4OF */ + __IM uint32_t : 7; + __IOM uint32_t IDXF : 1; /*!< [20..20] desc IDXF */ + __IOM uint32_t DIRF : 1; /*!< [21..21] desc DIRF */ + __IOM uint32_t IERRF : 1; /*!< [22..22] desc IERRF */ + __IOM uint32_t TERRF : 1; /*!< [23..23] desc TERRF */ + } ICR_f; + } ; +} GTIM_TypeDef; /*!< Size = 116 (0x74) */ + + + +/* =========================================================================================================================== */ +/* ================ HALLTIM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief HALL Timer (HALLTIM) + */ + +typedef struct { /*!< (@ 0x40006400) HALLTIM Structure */ + + union { + __IOM uint32_t CR; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t FLT1EN : 1; /*!< [1..1] desc FLT1EN */ + __IOM uint32_t DIV : 2; /*!< [3..2] desc DIV */ + __IOM uint32_t MMS : 3; /*!< [6..4] desc MMS */ + __IM uint32_t : 1; + __IOM uint32_t FLT2LEN : 15; /*!< [22..8] desc FLT2LEN */ + __IOM uint32_t SOFTCAP : 1; /*!< [23..23] desc SOFTCAP */ + } CR_f; + } ; + + union { + __IOM uint32_t DIER; /*!< (@ 0x00000004) DMA and Interrupt register2 */ + + struct { + __IOM uint32_t CAPIE : 1; /*!< [0..0] desc CAPIE */ + __IOM uint32_t OVIE : 1; /*!< [1..1] desc OVIE */ + __IOM uint32_t MATCHIE : 1; /*!< [2..2] desc MATCHIE */ + __IM uint32_t : 1; + __IOM uint32_t CAPDMA : 1; /*!< [4..4] desc CAPDMA */ + __IOM uint32_t OVDMA : 1; /*!< [5..5] desc OVDMA */ + __IOM uint32_t MATCHDMA : 1; /*!< [6..6] desc MATCHDMA */ + __IOM uint32_t SOFTDMA : 1; /*!< [7..7] desc SOFTDMA */ + } DIER_f; + } ; + + union { + __IOM uint32_t CNT; /*!< (@ 0x00000008) counter register */ + + struct { + __IOM uint32_t DATA : 24; /*!< [23..0] desc CNT */ + } CNT_f; + } ; + + union { + __IOM uint32_t ARR; /*!< (@ 0x0000000C) Auto Reload Register */ + + struct { + __IOM uint32_t DATA : 24; /*!< [23..0] desc ARR */ + } ARR_f; + } ; + + union { + __IM uint32_t WIDTH; /*!< (@ 0x00000010) Width Register */ + + struct { + __IM uint32_t DATA : 24; /*!< [23..0] desc WIDTH */ + } WIDTH_f; + } ; + + union { + __IOM uint32_t CCR; /*!< (@ 0x00000014) Compare control Register */ + + struct { + __IOM uint32_t DATA : 24; /*!< [23..0] desc CCR */ + } CCR_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000018) Interrupt states register */ + + struct { + __IM uint32_t CAPF : 1; /*!< [0..0] desc CAPF */ + __IM uint32_t OV : 1; /*!< [1..1] desc OV */ + __IM uint32_t MATCH : 1; /*!< [2..2] desc MATCH */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x0000001C) Interrupt clean register */ + + struct { + __IOM uint32_t CAPF : 1; /*!< [0..0] desc CHG */ + __IOM uint32_t OVF : 1; /*!< [1..1] desc OV */ + __IOM uint32_t MATCHF : 1; /*!< [2..2] desc MATCH */ + } ICR_f; + } ; + + union { + __IM uint32_t STATE; /*!< (@ 0x00000020) State register */ + + struct { + __IM uint32_t CH1F : 1; /*!< desc CH1F */ + __IM uint32_t CH2F : 1; /*!< desc CH2F */ + __IM uint32_t CH3F : 1; /*!< desc CH3F */ + uint32_t : 1; + __IM uint32_t CH1S : 1; /*!< desc CH1S */ + __IM uint32_t CH2S : 1; /*!< desc CH2S */ + __IM uint32_t CH3S : 1; /*!< desc CH3S */ + } STATE_f; + } ; +} HALLTIM_TypeDef; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ I2C1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc I2C1 (I2C1) + */ +typedef struct { /*!< (@ 0x40005800) I2C1 Structure */ + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t INSEL; /*!< (@ 0x00000008) Input selection register */ + + struct { + __IOM uint32_t SCLINSEL : 3; /*!< [2..0] desc SCLINSEL */ + __IOM uint32_t SDAINSEL : 3; /*!< [5..3] desc SDAINSEL */ + } INSEL_f; + } ; + + union { + __IOM uint32_t MICR; /*!< (@ 0x0000000C) Master Interrupt Flag Clear Register */ + + struct { + uint32_t : 8; + __IOM uint32_t PACKET : 1; /*!< [8..8] desc PACKET */ + __IOM uint32_t STOP : 1; /*!< [9..9] desc STOP */ + __IOM uint32_t NACK : 1; /*!< [10..10] desc NACK */ + __IOM uint32_t ARBI : 1; /*!< [11..11] desc ARBI */ + __IOM uint32_t FIFO : 1; /*!< [12..12] desc FIFO */ + __IOM uint32_t PINLOW : 1; /*!< [13..13] desc PINLOW */ + __IOM uint32_t MATCH : 1; /*!< [14..14] desc MATCH */ + } MICR_f; + } ; + + union { + __IOM uint32_t MCR0; /*!< (@ 0x00000010) Master Control Register0 */ + + struct { + __IOM uint32_t MEN : 1; /*!< [0..0] desc MEN */ + __IOM uint32_t RESET : 1; /*!< [1..1] desc RESET */ + __IOM uint32_t SLEEPEN : 1; /*!< [2..2] desc SLEEPEN */ + __IOM uint32_t DBGEN : 1; /*!< [3..3] desc DBGEN */ + __IM uint32_t : 2; + __IOM uint32_t CLKSRC : 2; /*!< [7..6] desc CLKSRC */ + __IOM uint32_t TXFIFORST : 1; /*!< [8..8] desc TXFIFORST */ + __IOM uint32_t RXFIFORST : 1; /*!< [9..9] desc RXFIFORST */ + } MCR0_f; + } ; + + union { + __IM uint32_t MISR; /*!< (@ 0x00000014) Master Interrupt Status Register */ + + struct { + __IM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + uint32_t : 6; + __IM uint32_t PACKET : 1; /*!< [8..8] desc PACKET */ + __IM uint32_t STOP : 1; /*!< [9..9] desc STOP */ + __IM uint32_t NACK : 1; /*!< [10..10] desc NACK */ + __IM uint32_t ARBI : 1; /*!< [11..11] desc ARBI */ + __IM uint32_t FIFO : 1; /*!< [12..12] desc FIFO */ + __IM uint32_t PINLOW : 1; /*!< [13..13] desc PINLOW */ + __IM uint32_t MATCH : 1; /*!< [14..14] desc MATCH */ + __IM uint32_t : 9; + __IM uint32_t MSTBUSY : 1; /*!< [24..24] desc MSTBUSY */ + __IM uint32_t BUSBUSY : 1; /*!< [25..25] desc BUSBUSY */ + } MISR_f; + } ; + + union { + __IOM uint32_t MIER; /*!< (@ 0x00000018) Master Interrupt Enable Register */ + + struct { + __IOM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IOM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + uint32_t : 6; + __IOM uint32_t PACKET : 1; /*!< [8..8] desc PACKET */ + __IOM uint32_t STOP : 1; /*!< [9..9] desc STOP */ + __IOM uint32_t NACK : 1; /*!< [10..10] desc NACK */ + __IOM uint32_t ARBI : 1; /*!< [11..11] desc ARBI */ + __IOM uint32_t FIFO : 1; /*!< [12..12] desc FIFO */ + __IOM uint32_t PINLOW : 1; /*!< [13..13] desc PINLOW */ + __IOM uint32_t MATCH : 1; /*!< [14..14] desc MATCH */ + } MIER_f; + } ; + + union { + __IOM uint32_t MDER; /*!< (@ 0x0000001C) Master DMA Enable Register */ + + struct { + __IOM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IOM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + } MDER_f; + } ; + + union { + __IOM uint32_t MCR1; /*!< (@ 0x00000020) Master Control Register1 */ + + struct { + __IM uint32_t : 8; + __IOM uint32_t CIRFIFO : 1; /*!< [8..8] desc CIRFIFO */ + __IOM uint32_t RDMO : 1; /*!< [9..9] desc RDMO */ + } MCR1_f; + } ; + + union { + union { + __IOM uint32_t MCR2; /*!< (@ 0x00000024) Master Control Register2 */ + + struct { + __IOM uint32_t PRESCALE : 3; /*!< [2..0] desc PRESCALE */ + __IM uint32_t : 5; + __IOM uint32_t AUTOSTOP : 1; /*!< [8..8] desc AUTOSTOP */ + __IOM uint32_t IGNACK : 1; /*!< [9..9] desc IGNACK */ + __IOM uint32_t TIMECFG : 1; /*!< [10..10] desc TIMECFG */ + __IM uint32_t : 4; + __IOM uint32_t TRGSEL : 1; /*!< [15..15] desc TRGSEL */ + __IOM uint32_t MATCFG : 3; /*!< [18..16] desc MATCFG */ + uint32_t : 5; + __IOM uint32_t PINCFG : 3; /*!< [26..24] desc PINCFG */ + } MCR2_f; + } ; + + union { + __IOM uint32_t SCR2; /*!< (@ 0x00000024) desc SCR2 */ + + struct { + __IM uint32_t : 24; + __IOM uint32_t PINCFG : 3; /*!< [26..24] desc PINCFG */ + } SCR2_f; + } ; + } ; + + union { + __IOM uint32_t MCR3; /*!< (@ 0x00000028) Master Control Register3 */ + + struct { + __IOM uint32_t BUSIDLE : 12; /*!< [11..0] desc BUSIDLE */ + __IM uint32_t : 4; + __IOM uint32_t FLTSCL : 4; /*!< [19..16] desc FLTSCL */ + __IM uint32_t : 4; + __IOM uint32_t FLTSDA : 4; /*!< [27..24] desc FLTSDA */ + } MCR3_f; + } ; + + union { + __IOM uint32_t MCR4; /*!< (@ 0x0000002C) Master Control Register4 */ + + struct { + __IM uint32_t : 8; + __IOM uint32_t PINLOW : 12; /*!< [19..8] desc PINLOW */ + } MCR4_f; + } ; + __IM uint32_t RESERVED1[4]; + + union { + __IOM uint32_t MMATCH; /*!< (@ 0x00000040) Master Match Register */ + + struct { + __IOM uint32_t MATCH0 : 8; /*!< [7..0] desc MATCH0 */ + __IM uint32_t : 8; + __IOM uint32_t MATCH1 : 8; /*!< [23..16] desc MATCH1 */ + } MMATCH_f; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t MCCR; /*!< (@ 0x00000048) Master Clock Control Register0 */ + + struct { + __IOM uint32_t CLKLO : 6; /*!< [5..0] desc CLKLO */ + __IM uint32_t : 2; + __IOM uint32_t CLKHI : 6; /*!< [13..8] desc CLKHI */ + __IM uint32_t : 2; + __IOM uint32_t SETHOLD : 6; /*!< [21..16] desc SETHOLD */ + __IM uint32_t : 2; + __IOM uint32_t DATAVD : 6; /*!< [29..24] desc DATAVD */ + } MCCR_f; + } ; + __IM uint32_t RESERVED3[3]; + + union { + __IOM uint32_t MFIFOCR; /*!< (@ 0x00000058) Master FIFO Control Register */ + + struct { + __IOM uint32_t TXWATER : 1; /*!< [0..0] desc TXWATER */ + __IM uint32_t : 15; + __IOM uint32_t RXWATER : 1; /*!< [16..16] desc RXWATER */ + } MFIFOCR_f; + } ; + + union { + __IM uint32_t MFIFOSR; /*!< (@ 0x0000005C) Master FIFO Status Register */ + + struct { + __IM uint32_t TXCNT : 2; /*!< [1..0] desc TXCNT */ + __IM uint32_t : 14; + __IM uint32_t RXCNT : 2; /*!< [17..16] desc RXCNT */ + } MFIFOSR_f; + } ; + + union { + __OM uint32_t MTDR; /*!< (@ 0x00000060) Master Tx Data Register */ + + struct { + __OM uint32_t DATA : 8; /*!< [7..0] desc DATA */ + __OM uint32_t CMD : 3; /*!< [10..8] desc CMD */ + } MTDR_f; + } ; + __IM uint32_t RESERVED4[3]; + + union { + __IM uint32_t MRDR; /*!< (@ 0x00000070) Master Rx Data Register */ + + struct { + __IM uint32_t DATA : 8; /*!< [7..0] desc DATA */ + __IM uint32_t : 6; + __IM uint32_t EMPTY : 1; /*!< [14..14] desc EMPTY */ + } MRDR_f; + } ; + __IM uint32_t RESERVED5[38]; + + union { + __IOM uint32_t SICR; /*!< (@ 0x0000010C) desc SICR */ + + struct { + __IM uint32_t : 8; + __IOM uint32_t RESTART : 1; /*!< [8..8] desc RESTART */ + __IOM uint32_t STOP : 1; /*!< [9..9] desc STOP */ + __IOM uint32_t BIT : 1; /*!< [10..10] desc BIT */ + __IOM uint32_t FIFO : 1; /*!< [11..11] desc FIFO */ + } SICR_f; + } ; + + union { + __IOM uint32_t SCR0; /*!< (@ 0x00000110) Slave Control Register0 */ + + struct { + __IOM uint32_t SEN : 1; /*!< [0..0] desc SEN */ + __IOM uint32_t RESET : 1; /*!< [1..1] desc RESET */ + __IM uint32_t : 2; + __IOM uint32_t FLTEN : 1; /*!< [4..4] desc FLTEN */ + __IM uint32_t : 1; + __IOM uint32_t CLKSRC : 2; /*!< [7..6] desc CLKSRC */ + __IOM uint32_t TXFIFORST : 1; /*!< [8..8] desc TXFIFORST */ + __IOM uint32_t RXFIFORST : 1; /*!< [9..9] desc RXFIFORST */ + } SCR0_f; + } ; + + union { + __IM uint32_t SISR; /*!< (@ 0x00000114) desc SISR */ + + struct { + __IM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IM uint32_t ADDR : 1; /*!< [2..2] desc ADDR */ + __IM uint32_t TACK : 1; /*!< [3..3] desc TACK */ + __IM uint32_t : 4; + __IM uint32_t RESTART : 1; /*!< [8..8] desc RESTART */ + __IM uint32_t STOP : 1; /*!< [9..9] desc STOP */ + __IM uint32_t BIT : 1; /*!< [10..10] desc BIT */ + __IM uint32_t FIFO : 1; /*!< [11..11] desc FIFO */ + __IM uint32_t AM0 : 1; /*!< [12..12] desc AM0 */ + __IM uint32_t AM1 : 1; /*!< [13..13] desc AM1 */ + __IM uint32_t GC : 1; /*!< [14..14] desc GC */ + __IM uint32_t ALERT : 1; /*!< [15..15] desc ALERT */ + __IM uint32_t : 8; + __IM uint32_t SLVBUSY : 1; /*!< [24..24] desc SLVBUSY */ + __IM uint32_t BUSBUSY : 1; /*!< [25..25] desc BUSBUSY */ + } SISR_f; + } ; + + union { + __IOM uint32_t SIER; /*!< (@ 0x00000118) desc SIER */ + + struct { + __IOM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IOM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IOM uint32_t ADDR : 1; /*!< [2..2] desc ADDR */ + __IOM uint32_t TACK : 1; /*!< [3..3] desc TACK */ + __IM uint32_t : 4; + __IOM uint32_t RESTART : 1; /*!< [8..8] desc RESTART */ + __IOM uint32_t STOP : 1; /*!< [9..9] desc STOP */ + __IOM uint32_t BIT : 1; /*!< [10..10] desc BIT */ + __IOM uint32_t FIFO : 1; /*!< [11..11] desc FIFO */ + __IOM uint32_t AM0 : 1; /*!< [12..12] desc AM0 */ + __IOM uint32_t AM1 : 1; /*!< [13..13] desc AM1 */ + __IOM uint32_t GC : 1; /*!< [14..14] desc GC */ + __IOM uint32_t ALERT : 1; /*!< [15..15] desc ALERT */ + } SIER_f; + } ; + + union { + __IOM uint32_t SDER; /*!< (@ 0x0000011C) desc SDER */ + + struct { + __IOM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IOM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IOM uint32_t ADDR : 1; /*!< [2..2] desc ADDR */ + } SDER_f; + } ; + __IM uint32_t RESERVED6; + + union { + __IOM uint32_t SCR1; /*!< (@ 0x00000124) desc SCR1 */ + + struct { + __IOM uint32_t ADRSTALL : 1; /*!< [0..0] desc ADRSTALL */ + __IOM uint32_t RXSTALL : 1; /*!< [1..1] desc RXSTALL */ + __IOM uint32_t TXSTALL : 1; /*!< [2..2] desc TXSTALL */ + __IOM uint32_t ACKSTALL : 1; /*!< [3..3] desc ACKSTALL */ + __IM uint32_t : 4; + __IOM uint32_t GCEN : 1; /*!< [8..8] desc GCEN */ + __IOM uint32_t ALERTEN : 1; /*!< [9..9] desc ALERTEN */ + __IOM uint32_t TXCFG : 1; /*!< [10..10] desc TXCFG */ + __IOM uint32_t RXCFG : 1; /*!< [11..11] desc RXCFG */ + __IOM uint32_t IGNACK : 1; /*!< [12..12] desc IGNACK */ + uint32_t : 2; + __IOM uint32_t TRGSEL : 1; /*!< [15..15] desc TRGSEL */ + __IOM uint32_t ADDRCFG : 3; /*!< [18..16] desc ADDRCFG */ + } SCR1_f; + } ; + + union { + __IOM uint32_t SCR3; /*!< (@ 0x00000128) desc SCR3 */ + + struct { + __IOM uint32_t CLKHOLD : 4; /*!< [3..0] desc CLKHOLD */ + __IM uint32_t : 4; + __IOM uint32_t DATAVD : 6; /*!< [13..8] desc DATAVD */ + __IM uint32_t : 2; + __IOM uint32_t FLTSCL : 4; /*!< [19..16] desc FLTSCL */ + __IM uint32_t : 4; + __IOM uint32_t FLTSDA : 4; /*!< [27..24] desc FLTSDA */ + } SCR3_f; + } ; + __IM uint32_t RESERVED7[5]; + + union { + __IOM uint32_t SAMR; /*!< (@ 0x00000140) desc SAMR */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t ADDR0 : 10; /*!< [10..1] desc ADDR0 */ + __IM uint32_t : 6; + __IOM uint32_t ADDR1 : 10; /*!< [26..17] desc ADDR1 */ + } SAMR_f; + } ; + __IM uint32_t RESERVED8[3]; + + union { + __IM uint32_t SASR; /*!< (@ 0x00000150) desc SASR */ + + struct { + __IM uint32_t RADDR : 11; /*!< [10..0] desc RADDR */ + __IM uint32_t : 3; + __IM uint32_t ANV : 1; /*!< [14..14] desc ANV */ + } SASR_f; + } ; + + union { + __IOM uint32_t STAR; /*!< (@ 0x00000154) desc STAR */ + + struct { + __IOM uint32_t TXNACK : 1; /*!< [0..0] desc TXNACK */ + } STAR_f; + } ; + __IM uint32_t RESERVED9[2]; + + union { + __OM uint32_t STDR; /*!< (@ 0x00000160) desc STDR */ + + struct { + __OM uint32_t DATA : 8; /*!< [7..0] desc DATA */ + } STDR_f; + } ; + __IM uint32_t RESERVED10[3]; + + union { + __IM uint32_t SRDR; /*!< (@ 0x00000170) desc SRDR */ + + struct { + __IM uint32_t DATA : 8; /*!< [7..0] desc DATA */ + __IM uint32_t : 6; + __IM uint32_t RXEMPTY : 1; /*!< [14..14] desc RXEMPTY */ + __IM uint32_t SOF : 1; /*!< [15..15] desc SOF */ + } SRDR_f; + } ; +} I2C_TypeDef; /*!< Size = 372 (0x174) */ + + + +/* =========================================================================================================================== */ +/* ================ IRMOD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc IRMOD (IRMOD) + */ + +typedef struct { /*!< (@ 0x40004080) IRMOD Structure */ + union { + __IOM uint32_t CR; /*!< (@ 0x00000000) Input selection register */ + + struct { + __IOM uint32_t MOD : 4; /*!< [3..0] desc MOD */ + __IOM uint32_t IRSW : 1; /*!< [4..4] desc IRSW */ + __IOM uint32_t INV : 1; /*!< [5..5] desc INV */ + } CR_f; + } ; +} IRMOD_TypeDef; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ IWDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc IWDT (IWDT) + */ + +typedef struct { /*!< (@ 0x40005000) IWDT Structure */ + + union { + __OM uint32_t KR; /*!< (@ 0x00000000) Key register */ + + struct { + __OM uint32_t KR : 16; /*!< [15..0] desc KR */ + } KR_f; + } ; + + union { + __IOM uint32_t CR; /*!< (@ 0x00000004) Control register */ + + struct { + __IOM uint32_t PRS : 3; /*!< [2..0] desc PRS */ + __IOM uint32_t ACTION : 1; /*!< [3..3] desc ACTION */ + __IOM uint32_t IE : 1; /*!< [4..4] desc IE */ + __IOM uint32_t PAUSE : 1; /*!< [5..5] desc PAUSE */ + } CR_f; + } ; + + union { + __IOM uint32_t ARR; /*!< (@ 0x00000008) Auto reload register */ + + struct { + __IOM uint32_t ARR : 12; /*!< [11..0] desc ARR */ + } ARR_f; + } ; + + union { + __IOM uint32_t SR; /*!< (@ 0x0000000C) Status register */ + + struct { + __IM uint32_t CRF : 1; /*!< [0..0] desc CRF */ + __IM uint32_t ARRF : 1; /*!< [1..1] desc ARRF */ + __IM uint32_t WINRF : 1; /*!< [2..2] desc WINRF */ + __IOM uint32_t OV : 1; /*!< [3..3] desc OV */ + __IM uint32_t RUN : 1; /*!< [4..4] desc RUN */ + __IM uint32_t RELOAD : 1; /*!< [5..5] desc RELOAD */ + } SR_f; + } ; + + union { + __IOM uint32_t WINR; /*!< (@ 0x00000010) Window register */ + + struct { + __IOM uint32_t WINR : 12; /*!< [11..0] desc WINR */ + } WINR_f; + } ; + __IM uint32_t RESERVED[4]; + + union { + __IM uint32_t CNT; /*!< (@ 0x00000024) counter */ + + struct { + __IM uint32_t CNT : 12; /*!< [11..0] desc CNT */ + } CNT_f; + } ; +} IWDT_TypeDef; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ LPTIM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc LPTIM (LPTIM) + */ + +typedef struct { /*!< (@ 0x40006000) LPTIM Structure */ + + union { + __IM uint32_t ISR; /*!< (@ 0x00000000) desc ISR */ + + struct { + __IM uint32_t CMPM : 1; /*!< [0..0] desc CMPM */ + __IM uint32_t ARRM : 1; /*!< [1..1] desc ARRM */ + __IM uint32_t EXTTRIG : 1; /*!< [2..2] desc EXTTRIG */ + __IM uint32_t CMPOK : 1; /*!< [3..3] desc CMPOK */ + __IM uint32_t ARROK : 1; /*!< [4..4] desc ARROK */ + __IM uint32_t UP : 1; /*!< [5..5] desc UP */ + __IM uint32_t DOWN : 1; /*!< [6..6] desc DOWN */ + __IM uint32_t DIR : 2; /*!< [8..7] desc DIR */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000004) desc ICR */ + + struct { + __IOM uint32_t CMPM : 1; /*!< [0..0] desc CMPM */ + __IOM uint32_t ARRM : 1; /*!< [1..1] desc ARRM */ + __IOM uint32_t EXTTRIG : 1; /*!< [2..2] desc EXTTRIG */ + __IOM uint32_t CMPOK : 1; /*!< [3..3] desc CMPOK */ + __IOM uint32_t ARROK : 1; /*!< [4..4] desc ARROK */ + __IOM uint32_t UP : 1; /*!< [5..5] desc UP */ + __IOM uint32_t DOWN : 1; /*!< [6..6] desc DOWN */ + } ICR_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000008) desc IER */ + + struct { + __IOM uint32_t CMPM : 1; /*!< [0..0] desc CMPM */ + __IOM uint32_t ARRM : 1; /*!< [1..1] desc ARRM */ + __IOM uint32_t EXTTRIG : 1; /*!< [2..2] desc EXTTRIG */ + __IOM uint32_t CMPOK : 1; /*!< [3..3] desc CMPOK */ + __IOM uint32_t ARROK : 1; /*!< [4..4] desc ARROK */ + __IOM uint32_t UP : 1; /*!< [5..5] desc UP */ + __IOM uint32_t DOWN : 1; /*!< [6..6] desc DOWN */ + } IER_f; + } ; + + union { + __IOM uint32_t CFGR; /*!< (@ 0x0000000C) desc CFGR1 */ + + struct { + __IOM uint32_t CKSEL : 1; /*!< [0..0] desc CKSEL */ + __IOM uint32_t ENCMD_CKPOL : 2; /*!< [2..1] desc ENCMD_CKPOL */ + __IOM uint32_t CHFLT : 2; /*!< [4..3] desc CHFLT */ + __IM uint32_t : 1; + __IOM uint32_t TRIGFLT : 2; /*!< [7..6] desc TRIGFLT */ + __IM uint32_t : 1; + __IOM uint32_t PRS : 3; /*!< [11..9] desc PRS */ + __IOM uint32_t TRIGSEL : 4; /*!< [15..12] desc TRIGSEL */ + __IM uint32_t : 1; + __IOM uint32_t TRIGEN : 2; /*!< [18..17] desc TRIGEN */ + __IOM uint32_t TIMOUT : 1; /*!< [19..19] desc TIMOUT */ + __IOM uint32_t WAVE : 1; /*!< [20..20] desc WAVE */ + __IOM uint32_t WAVPOL : 1; /*!< [21..21] desc WAVPOL */ + __IOM uint32_t PRELOAD : 1; /*!< [22..22] desc PRELOAD */ + __IOM uint32_t COUNTMD : 1; /*!< [23..23] desc COUNTMD */ + __IOM uint32_t ENC : 1; /*!< [24..24] desc ENC */ + __IOM uint32_t ICLKSRC : 2; /*!< [26..25] desc ICLKSRC */ + } CFGR_f; + } ; + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000010) desc CR */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t SNGSTART : 1; /*!< [1..1] desc SNGSTART */ + __IOM uint32_t CNTSTART : 1; /*!< [2..2] desc CNTSTART */ + __IOM uint32_t SRST : 1; /*!< [3..3] desc SRST */ + __IOM uint32_t ARST : 1; /*!< [4..4] desc ARST */ + } CR0_f; + } ; + + union { + __IOM uint32_t CMP; /*!< (@ 0x00000014) desc CMP */ + + struct { + __IOM uint32_t CMP : 16; /*!< [15..0] desc CMP */ + } CMP_f; + } ; + + union { + __IOM uint32_t ARR; /*!< (@ 0x00000018) desc ARR */ + + struct { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } ARR_f; + } ; + + union { + __IM uint32_t CNT; /*!< (@ 0x0000001C) desc CNT */ + + struct { + __IM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + } CNT_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000020) desc CFGR2 */ + + struct { + __IOM uint32_t CH1SRC : 3; /*!< [2..0] desc CH1SRC */ + __IOM uint32_t CH2SRC : 3; /*!< [5..3] desc CH2SRC */ + } CR1_f; + } ; +} LPTIM_TypeDef; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ UART1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc UART1 (UART1) + */ + +typedef struct { /*!< (@ 0x40000C00) UART1 Structure */ + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t TXEN : 1; /*!< [0..0] desc TXEN */ + __IOM uint32_t RXEN : 1; /*!< [1..1] desc RXEN */ + __IOM uint32_t PARITY : 1; /*!< [2..2] desc PARITY */ + __IOM uint32_t PARITYEN : 1; /*!< [3..3] desc PARITYEN */ + __IOM uint32_t STOP : 2; /*!< [5..4] desc STOP */ + __IOM uint32_t CHLEN : 1; /*!< [6..6] desc CHLEN */ + __IOM uint32_t MSBF : 1; /*!< [7..7] desc MSBF */ + __IOM uint32_t START : 1; /*!< [8..8] desc START */ + __IOM uint32_t OVER : 2; /*!< [10..9] desc OVER */ + __IOM uint32_t SIGNAL : 1; /*!< [11..11] desc SIGNAL */ + __IOM uint32_t SOURCE : 2; /*!< [13..12] desc SOURCE */ + __IOM uint32_t SYNC : 1; /*!< [14..14] desc SYNC */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000004) Control register2 */ + + struct { + __IOM uint32_t ADDREN : 1; /*!< [0..0] desc ADDREN */ + __IOM uint32_t RXMATCHEN : 1; /*!< [1..1] desc RXMATCHEN */ + __IOM uint32_t CTSEN : 1; /*!< [2..2] desc CTSEN */ + __IOM uint32_t RTSEN : 1; /*!< [3..3] desc RTSEN */ + __IOM uint32_t RXINV : 1; /*!< [4..4] desc RXINV */ + __IOM uint32_t TXINV : 1; /*!< [5..5] desc TXINV */ + __IOM uint32_t DMARX : 1; /*!< [6..6] desc DMARX */ + __IOM uint32_t DMATX : 1; /*!< [7..7] desc DMATX */ + __IOM uint32_t TIMCR : 3; /*!< [10..8] desc TIMCR */ + __IOM uint32_t SWAP : 1; /*!< [11..11] desc SWAP */ + __IOM uint32_t ADCRX : 1; /*!< desc ADCRX */ + __IOM uint32_t ADCTX : 1; /*!< desc ADCTX */ + __IOM uint32_t LOOP : 1; /*!< [14..14] desc LOOP */ + __IOM uint32_t RXSRC : 3; /*!< [17..15] desc RXSRC */ + } CR2_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000008) Interrupt enable register */ + + struct { + __IOM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IOM uint32_t TC : 1; /*!< [1..1] desc TC */ + __IOM uint32_t RC : 1; /*!< [2..2] desc RC */ + __IOM uint32_t RXIDLE : 1; /*!< [3..3] desc RXIDLE */ + __IOM uint32_t RXBRK : 1; /*!< [4..4] desc RXBRK */ + __IOM uint32_t BAUD : 1; /*!< [5..5] desc BAUD */ + __IOM uint32_t TIMOV : 1; /*!< [6..6] desc TIMOV */ + __IOM uint32_t CTS : 1; /*!< [7..7] desc CTS */ + __IOM uint32_t FE : 1; /*!< [8..8] desc FE */ + __IOM uint32_t PE : 1; /*!< [9..9] desc PE */ + __IOM uint32_t NE : 1; /*!< [10..10] desc NE */ + __IOM uint32_t ORE : 1; /*!< [11..11] desc ORE */ + __IOM uint32_t RXMATCH : 1; /*!< [12..12] desc RXMATCH */ + } IER_f; + } ; + + union { + __IOM uint32_t BRRI; /*!< (@ 0x0000000C) desc BRRI */ + + struct { + __IOM uint32_t BRRI : 16; /*!< [15..0] desc BRRI */ + } BRRI_f; + } ; + + union { + __IOM uint32_t BRRF; /*!< (@ 0x00000010) desc BRRF */ + + struct { + __IOM uint32_t BRRF : 4; /*!< [3..0] desc BRRF */ + } BRRF_f; + } ; + + union { + __IOM uint32_t TIMARR; /*!< (@ 0x00000014) desc TIMARR */ + + struct { + __IOM uint32_t TIMARR : 24; /*!< [23..0] desc TIMARR */ + } TIMARR_f; + } ; + + union { + __IM uint32_t TIMCNT; /*!< (@ 0x00000018) desc TIMCNT */ + + struct { + __IM uint32_t TIMCNT : 24; /*!< [23..0] desc TIMCNT */ + } TIMCNT_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x0000001C) Interrupt status register */ + + struct { + __IM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IM uint32_t TC : 1; /*!< [1..1] desc TC */ + __IM uint32_t RC : 1; /*!< [2..2] desc RC */ + __IM uint32_t RXIDLE : 1; /*!< [3..3] desc RXIDLE */ + __IM uint32_t RXBRK : 1; /*!< [4..4] desc RXBRK */ + __IM uint32_t BAUD : 1; /*!< [5..5] desc BAUD */ + __IM uint32_t TIMOV : 1; /*!< [6..6] desc TIMOV */ + __IM uint32_t CTS : 1; /*!< [7..7] desc CTS */ + __IM uint32_t FE : 1; /*!< [8..8] desc FE */ + __IM uint32_t PE : 1; /*!< [9..9] desc PE */ + __IM uint32_t NE : 1; /*!< [10..10] desc NE */ + __IM uint32_t ORE : 1; /*!< [11..11] desc ORE */ + __IM uint32_t RXMATCH : 1; /*!< [12..12] desc RXMATCH */ + __IM uint32_t SLVMATCH : 1; /*!< [13..13] desc SLVMATCH */ + __IM uint32_t TXBUSY : 1; /*!< [14..14] desc TXBUSY */ + __IM uint32_t CTSLV : 1; /*!< [15..15] desc CTSLV */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000020) Interrupt flag clear register */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t TC : 1; /*!< [1..1] desc TC */ + __IOM uint32_t RC : 1; /*!< [2..2] desc RC */ + __IOM uint32_t RXIDLE : 1; /*!< [3..3] desc RXIDLE */ + __IOM uint32_t RXBRK : 1; /*!< [4..4] desc RXBRK */ + __IOM uint32_t BAUD : 1; /*!< [5..5] desc BAUD */ + __IOM uint32_t TIMOV : 1; /*!< [6..6] desc TIMOV */ + __IOM uint32_t CTS : 1; /*!< [7..7] desc CTS */ + __IOM uint32_t FE : 1; /*!< [8..8] desc FE */ + __IOM uint32_t PE : 1; /*!< [9..9] desc PE */ + __IOM uint32_t NE : 1; /*!< [10..10] desc NE */ + __IOM uint32_t ORE : 1; /*!< [11..11] desc ORE */ + __IOM uint32_t RXMATCH : 1; /*!< [12..12] desc RXMATCH */ + } ICR_f; + } ; + + union { + __IM uint32_t RDR; /*!< (@ 0x00000024) Data reg for read */ + + struct { + __IM uint32_t RDR : 9; /*!< [8..0] desc RDR */ + } RDR_f; + } ; + + union { + __OM uint32_t TDR; /*!< (@ 0x00000028) Data reg for write */ + + struct { + __OM uint32_t TDR : 9; /*!< [8..0] desc TDR */ + __OM uint32_t IDLE : 1; /*!< [9..9] desc IDLE */ + __OM uint32_t BREAK : 1; /*!< [10..10] desc BREAK */ + } TDR_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t ADDR; /*!< (@ 0x00000030) Slave addr */ + + struct { + __IOM uint32_t ADDR : 8; /*!< [7..0] desc ADDR */ + } ADDR_f; + } ; + + union { + __IOM uint32_t MASK; /*!< (@ 0x00000034) Slave addr mask */ + + struct { + __IOM uint32_t MASK : 8; /*!< [7..0] desc MASK */ + } MASK_f; + } ; + + union { + __IOM uint32_t CR3; /*!< (@ 0x00000038) Control register3 */ + + struct { + __IOM uint32_t DEM : 1; /*!< [0..0] desc DEM */ + __IOM uint32_t DEP : 1; /*!< desc DEP */ + __IOM uint32_t DETIME : 5; /*!< [6..2] desc DETIME */ + __IOM uint32_t LIN : 1; /*!< [7..7] desc LIN */ + __IOM uint32_t BRKL : 1; /*!< [8..8] desc BRKL */ + } CR3_f; + } ; + + union { + __IOM uint32_t RXMATCH; /*!< (@ 0x0000003C) desc RXMATCH */ + + struct { + __IOM uint32_t RXMATCH : 9; /*!< [8..0] desc RXMATCH */ + } RXMATCH_f; + } ; +} UART_TypeDef; /*!< Size = 64 (0x40) */ + + + +/* =========================================================================================================================== */ +/* ================ LVD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc LVD (LVD) + */ + +typedef struct { /*!< (@ 0x400000A4) LVD Structure */ + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control register0 */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t ACTION : 1; /*!< [1..1] desc ACTION */ + __IOM uint32_t SOURCE : 1; /*!< [2..2] desc SOURCE */ + __IM uint32_t : 1; + __IOM uint32_t VTH : 3; /*!< [6..4] desc VTH */ + __IM uint32_t : 1; + __IOM uint32_t FLTCLK : 1; /*!< [8..8] desc FLTCLK */ + } CR0_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000004) Control register1 */ + + struct { + __IOM uint32_t IE : 1; /*!< [0..0] desc IE */ + __IOM uint32_t LEVEL : 1; /*!< [1..1] desc LEVEL */ + __IOM uint32_t RISE : 1; /*!< [2..2] desc RISE */ + __IOM uint32_t FALL : 1; /*!< [3..3] desc FALL */ + __IOM uint32_t FLTTIME : 4; /*!< [7..4] desc FLTTIME */ + } CR1_f; + } ; + + union { + __IOM uint32_t SR; /*!< (@ 0x00000008) status register */ + + struct { + __IOM uint32_t INTF : 1; /*!< [0..0] desc INTF */ + __IM uint32_t FLTV : 1; /*!< [1..1] desc FLTV */ + } SR_f; + } ; +} LVD_TypeDef; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ OPA1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc OPA1 (OPA1) + */ + +typedef struct { /*!< (@ 0x400000B0) OPA1 Structure */ + + union { + __IOM uint32_t CR; /*!< (@ 0x00000000) Control register0 */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t MODE : 2; /*!< [2..1] desc MODE */ + __IM uint32_t : 1; + __IOM uint32_t INP1EN : 1; /*!< [4..4] desc PCH1EN */ + __IOM uint32_t INP2EN : 1; /*!< [5..5] desc PCH2EN */ + __IOM uint32_t INP3EN : 1; /*!< [6..6] desc PCH3EN */ + __IOM uint32_t INP4EN : 1; /*!< [7..7] desc PCH4EN */ + __IOM uint32_t INN1EN : 1; /*!< [8..8] desc NCH1EN */ + __IOM uint32_t INN2EN : 1; /*!< [9..9] desc NCH2EN */ + __IOM uint32_t AMP : 3; /*!< [12..10] desc GAIN */ + __IOM uint32_t BIAS : 3; /*!< [15..13] desc BIAS */ + } CR_f; + } ; + + union { + __IOM uint32_t CAL; /*!< (@ 0x00000004) Control register1 */ + + struct { + __IOM uint32_t CALEN : 1; /*!< [0..0] desc AZEN */ + __IOM uint32_t CALMODE : 1; /*!< [1..1] desc MODE */ + __IOM uint32_t START : 1; /*!< [2..2] desc START */ + __IOM uint32_t SOFTTRIG : 1; /*!< [3..3] desc SOFTTRIG */ + __IOM uint32_t CALPERIOD : 4; /*!< [7..4] desc PERIOD */ + __IOM uint32_t ADCSTART : 1; /*!< desc ADCSTART */ + uint32_t : 1; + __IM uint32_t AZRUN : 1; /*!< [10..10] desc AZRUN */ + __IOM uint32_t CLKDIV : 3; /*!< [13..11] desc CLKDIV */ + __IOM uint32_t ADC1START1 : 1; /*!< [14..14] desc ADC1START1 */ + __IOM uint32_t ADC2START1 : 1; /*!< [15..15] desc ADC2START1 */ + __IOM uint32_t ATIM1TRGO : 1; /*!< [16..16] desc ATIM1TRGO */ + __IOM uint32_t ATIM1OC4 : 1; /*!< [17..17] desc ATIM1OC4REFC */ + __IOM uint32_t ATIM1OC5 : 1; /*!< [18..18] desc ATIM1OC5REFC */ + __IOM uint32_t ATIM1OC6 : 1; /*!< [19..19] desc ATIM1OC6REFC */ + __IOM uint32_t GTIM1TRGO : 1; /*!< [20..20] desc GTIM1TRGO */ + __IOM uint32_t GTIM1OC1 : 1; /*!< [21..21] desc GTIM1OC1REFC */ + __IOM uint32_t GTIM1OC2 : 1; /*!< [22..22] desc GTIM1OC2REFC */ + __IOM uint32_t GTIM2TRGO : 1; /*!< [23..23] desc GTIM2TRGO */ + __IOM uint32_t GTIM2OC1 : 1; /*!< [24..24] desc GTIM2OC1REFC */ + __IOM uint32_t GTIM2OC2 : 1; /*!< [25..25] desc GTIM2OC2REFC */ + __IOM uint32_t GTIM3TRGO : 1; /*!< [26..26] desc GTIM3TRGO */ + __IOM uint32_t GTIM3OC1 : 1; /*!< [27..27] desc GTIM3OC1REFC */ + __IOM uint32_t GTIM3OC2 : 1; /*!< [28..28] desc GTIM3OC2REFC */ + __IOM uint32_t GTIM4TRGO : 1; /*!< [29..29] desc GTIM4TRGO */ + __IOM uint32_t GTIM4OC1 : 1; /*!< [30..30] desc GTIM4OC1REFC */ + __IOM uint32_t GTIM4OC2 : 1; /*!< [31..31] desc GTIM4OC2REFC */ + } CAL_f; + } ; +} OPA_TypeDef; /*!< Size = 8 (0x8) */ + + +/* =========================================================================================================================== */ +/* ================ RAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc RAM (RAM) + */ + +typedef struct { /*!< (@ 0x40022400) RAM Structure */ + + union { + __IOM uint32_t IER; /*!< (@ 0x00000000) Interrupt enable register */ + + struct { + __IOM uint32_t PARITY : 1; /*!< [0..0] desc PARITY */ + } IER_f; + } ; + + union { + __IM uint32_t ADDR; /*!< (@ 0x00000004) Error address register */ + + struct { + __IM uint32_t ADDR : 32; /*!< [31..0] desc ADDR */ + } ADDR_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000008) Interrupt status register */ + + struct { + __IM uint32_t PARITY : 1; /*!< [0..0] desc PARITY */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x0000000C) Interrupt flag clear register */ + + struct { + __IOM uint32_t PARITY : 1; /*!< [0..0] desc PARITY */ + } ICR_f; + } ; +} RAM_TypeDef; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc RTC (RTC) + */ + +typedef struct { /*!< (@ 0x40004400) RTC Structure */ + + union { + __OM uint32_t KEY; /*!< (@ 0x00000000) desc KEY */ + + struct { + __OM uint32_t KEY : 8; /*!< [7..0] desc KEY */ + } KEY_f; + } ; + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000004) desc CR0 */ + + struct { + __IOM uint32_t INTERVAL : 3; /*!< [2..0] desc INTERVAL */ + __IOM uint32_t H24 : 1; /*!< [3..3] desc H24 */ + __IM uint32_t : 1; + __IOM uint32_t RTC1HZ : 2; /*!< [6..5] desc RTC1HZ */ + __IOM uint32_t START : 1; /*!< [7..7] desc START */ + } CR0_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000008) desc CR1 */ + + struct { + __IM uint32_t : 2; + __IM uint32_t WAIT : 1; /*!< [2..2] desc WAIT */ + __IM uint32_t : 5; + __IOM uint32_t SOURCE : 3; /*!< [10..8] desc SOURCE */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x0000000C) desc CR2 */ + + struct { + __IOM uint32_t AWTPRS : 2; /*!< [1..0] desc AWTPRS */ + __IOM uint32_t AWTSRC : 1; /*!< [2..2] desc AWTSRC */ + __IOM uint32_t TAMPEDGE : 1; /*!< [3..3] desc TAMPEDGE */ + __IOM uint32_t RTCOUT : 2; /*!< [5..4] desc RTCOUT */ + __IOM uint32_t TAMPEN : 1; /*!< [6..6] desc TAMPEN */ + __IOM uint32_t AWTEN : 1; /*!< [7..7] desc AWTEN */ + __IM uint32_t : 1; + __IOM uint32_t ALARMAEN : 1; /*!< [9..9] desc ALARMAEN */ + __IOM uint32_t ALARMBEN : 1; /*!< [10..10] desc ALARMBEN */ + } CR2_f; + } ; + + union { + __IOM uint32_t COMPCFR1; /*!< (@ 0x00000010) desc COMPCFR1 */ + + struct { + __IOM uint32_t COMP : 12; /*!< [11..0] desc COMP */ + __IOM uint32_t PERIOD : 2; /*!< [13..12] desc PERIOD */ + __IOM uint32_t SIGN : 1; /*!< [14..14] desc SIGN */ + __IOM uint32_t EN : 1; /*!< [15..15] desc EN */ + } COMPCFR1_f; + } ; + + union { + __IOM uint32_t DATE; /*!< (@ 0x00000014) desc DATE */ + + struct { + __IOM uint32_t DAY : 6; /*!< [7..0] desc DAY */ + uint32_t : 2; + __IOM uint32_t MONTH : 5; /*!< [15..8] desc MONTH */ + uint32_t : 3; + __IOM uint32_t YEAR : 8; /*!< [23..16] desc YEAR */ + __IOM uint32_t WEEK : 3; /*!< [26..24] desc WEEK */ + } DATE_f; + } ; + + union { + __IOM uint32_t TIME; /*!< (@ 0x00000018) desc TIME */ + + struct { + __IOM uint32_t SECOND : 7; /*!< [6..0] desc SECOND */ + __IM uint32_t : 1; + __IOM uint32_t MINUTE : 7; /*!< [14..8] desc MINUTE */ + __IM uint32_t : 1; + __IOM uint32_t HOUR : 6; /*!< [21..16] desc HOUR */ + } TIME_f; + } ; + + union { + __IOM uint32_t ALARMA; /*!< (@ 0x0000001C) desc ALARMA */ + + struct { + __IOM uint32_t SECOND : 7; /*!< [6..0] desc SECOND */ + __IOM uint32_t SECONDEN : 1; /*!< [7..7] desc SECONDEN */ + __IOM uint32_t MINUTE : 7; /*!< [14..8] desc MINUTE */ + __IOM uint32_t MINUTEEN : 1; /*!< [15..15] desc MINUTEEN */ + __IOM uint32_t HOUR : 6; /*!< [21..16] desc HOUR */ + __IM uint32_t : 1; + __IOM uint32_t HOUREN : 1; /*!< [23..23] desc HOUREN */ + __IOM uint32_t WEEKMASK : 7; /*!< [30..24] desc WEEKMASK */ + } ALARMA_f; + } ; + + union { + __IOM uint32_t ALARMB; /*!< (@ 0x00000020) desc ALARMB */ + + struct { + __IOM uint32_t SECOND : 7; /*!< [6..0] desc SECOND */ + __IOM uint32_t SECONDEN : 1; /*!< [7..7] desc SECONDEN */ + __IOM uint32_t MINUTE : 7; /*!< [14..8] desc MINUTE */ + __IOM uint32_t MINUTEEN : 1; /*!< [15..15] desc MINUTEEN */ + __IOM uint32_t HOUR : 6; /*!< [21..16] desc HOUR */ + __IM uint32_t : 1; + __IOM uint32_t HOUREN : 1; /*!< [23..23] desc HOUREN */ + __IOM uint32_t WEEKMASK : 7; /*!< [30..24] desc WEEKMASK */ + } ALARMB_f; + } ; + + union { + __IM uint32_t TAMPDATE; /*!< (@ 0x00000024) desc TAMPDATE */ + + struct { + __IM uint32_t DAY : 6; /*!< [5..0] desc DAY */ + __IM uint32_t : 2; + __IM uint32_t MONTH : 5; /*!< [12..8] desc MONTH */ + __IM uint32_t WEEK : 3; /*!< [15..13] desc WEEK */ + } TAMPDATE_f; + } ; + + union { + __IM uint32_t TAMPTIME; /*!< (@ 0x00000028) desc TAMPTIME */ + + struct { + __IM uint32_t SECOND : 7; /*!< [6..0] desc SECOND */ + __IM uint32_t : 1; + __IM uint32_t MINUTE : 7; /*!< [14..8] desc MINUTE */ + __IM uint32_t : 1; + __IM uint32_t HOUR : 6; /*!< [21..16] desc HOUR */ + } TAMPTIME_f; + } ; + + union { + __IOM uint32_t AWTARR; /*!< (@ 0x0000002C) desc AWTARR */ + + struct { + __IOM uint32_t ARR : 16; /*!< [15..0] desc ARR */ + } AWTARR_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000030) desc IER */ + + struct { + __IOM uint32_t ALARMA : 1; /*!< [0..0] desc ALARMA */ + __IOM uint32_t ALARMB : 1; /*!< [1..1] desc ALARMB */ + __IOM uint32_t AWTIMER : 1; /*!< [2..2] desc AWTIMER */ + __IOM uint32_t TAMP : 1; /*!< [3..3] desc TAMP */ + __IOM uint32_t TAMPOV : 1; /*!< [4..4] desc TAMPOV */ + __IM uint32_t : 1; + __IOM uint32_t INTERVAL : 1; /*!< [6..6] desc INTERVAL */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000034) desc ISR */ + + struct { + __IM uint32_t ALARMA : 1; /*!< [0..0] desc ALARMA */ + __IM uint32_t ALARMB : 1; /*!< [1..1] desc ALARMB */ + __IM uint32_t AWTIMER : 1; /*!< [2..2] desc AWTIMER */ + __IM uint32_t TAMP : 1; /*!< [3..3] desc TAMP */ + __IM uint32_t TAMPOV : 1; /*!< [4..4] desc TAMPOV */ + __IM uint32_t : 1; + __IM uint32_t INTERVAL : 1; /*!< [6..6] desc INTERVAL */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000038) desc ICR */ + + struct { + __IOM uint32_t ALARMA : 1; /*!< [0..0] desc ALARMA */ + __IOM uint32_t ALARMB : 1; /*!< [1..1] desc ALARMB */ + __IOM uint32_t AWTIMER : 1; /*!< [2..2] desc AWTIMER */ + __IOM uint32_t TAMP : 1; /*!< [3..3] desc TAMP */ + __IOM uint32_t TAMPOV : 1; /*!< [4..4] desc TAMPOV */ + __IM uint32_t : 1; + __IOM uint32_t INTERVAL : 1; /*!< [6..6] desc INTERVAL */ + } ICR_f; + } ; + + union { + __IM uint32_t AWTCNT; /*!< (@ 0x0000003C) desc AWTCNT */ + + struct { + __IM uint32_t CNT : 16; /*!< [15..0] desc CNT */ + } AWTCNT_f; + } ; + + union { + __IOM uint32_t PSC; /*!< (@ 0x00000040) desc PSC */ + + struct { + __IOM uint32_t PSC2 : 20; /*!< [19..0] desc PSC2 */ + __IOM uint32_t PSC1 : 8; /*!< [27..20] desc PSC1 */ + } PSC_f; + } ; + + union { + __IM uint32_t SSCNT; /*!< (@ 0x00000044) desc SSCNT */ + + struct { + __IM uint32_t SSCNT0 : 20; /*!< [19..0] desc SSCNT0 */ + __IM uint32_t SSCNT1 : 1; /*!< [20..20] desc SSCNT1 */ + } SSCNT_f; + } ; +} RTC_TypeDef; /*!< Size = 92 (0x5c) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc SPI1 (SPI1) + */ + +typedef struct { /*!< (@ 0x40000800) SPI1 Structure */ + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000000) Control register1 */ + + struct { + __IOM uint32_t MSTR : 1; /*!< [0..0] desc MSTR */ + __IOM uint32_t SSM : 1; /*!< [1..1] desc SSM */ + __IOM uint32_t CPHA : 1; /*!< [2..2] desc CPHA */ + __IOM uint32_t CPOL : 1; /*!< [3..3] desc CPOL */ + __IM uint32_t : 3; + __IOM uint32_t LSBF : 1; /*!< [7..7] desc LSBF */ + __IOM uint32_t WIDTH : 4; /*!< [11..8] desc WIDTH */ + __IOM uint32_t GAP : 4; /*!< [15..12] desc GAP */ + __IOM uint32_t MODE : 2; /*!< [17..16] desc MODE */ + __IOM uint32_t FLTEN : 1; /*!< [18..18] desc FLTEN */ + __IOM uint32_t MISOHD : 1; /*!< [19..19] desc MISOHD */ + __IOM uint32_t SMP : 1; /*!< [20..20] desc SMP */ + __IM uint32_t : 3; + __IOM uint32_t BR : 7; /*!< [30..24] desc BR */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000004) Control register2 */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t DMARX : 1; /*!< [1..1] desc DMARX */ + __IOM uint32_t DMATX : 1; /*!< [2..2] desc DMATX */ + } CR2_f; + } ; + + union { + __IOM uint32_t CR3; /*!< (@ 0x00000008) desc CR3 */ + + struct { + __IOM uint32_t HDOE : 1; /*!< [0..0] desc HDOE */ + } CR3_f; + } ; + + union { + __IOM uint32_t SSI; /*!< (@ 0x0000000C) Slave slect register */ + + struct { + __IOM uint32_t SSI : 1; /*!< [0..0] desc SSI */ + } SSI_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000010) Interrupt enable register */ + + struct { + __IOM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IOM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IOM uint32_t SSF : 1; /*!< [2..2] desc SSF */ + __IOM uint32_t SSR : 1; /*!< [3..3] desc SSR */ + __IOM uint32_t UD : 1; /*!< [4..4] desc UD */ + __IOM uint32_t OV : 1; /*!< [5..5] desc OV */ + __IOM uint32_t SSERR : 1; /*!< [6..6] desc SSERR */ + __IOM uint32_t MODF : 1; /*!< [7..7] desc MODF */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000014) Interrupt status register */ + + struct { + __IM uint32_t TXE : 1; /*!< [0..0] desc TXE */ + __IM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IM uint32_t SSF : 1; /*!< [2..2] desc SSF */ + __IM uint32_t SSR : 1; /*!< [3..3] desc SSR */ + __IM uint32_t UD : 1; /*!< [4..4] desc UD */ + __IM uint32_t OV : 1; /*!< [5..5] desc OV */ + __IM uint32_t SSERR : 1; /*!< [6..6] desc SSERR */ + __IM uint32_t MODF : 1; /*!< [7..7] desc MODF */ + __IM uint32_t BUSY : 1; /*!< [8..8] desc BUSY */ + __IM uint32_t SSLVL : 1; /*!< [9..9] desc SSLVL */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000018) Interrupt flag clear register */ + + struct { + __IOM uint32_t FLUSH : 1; /*!< [0..0] desc FLUSH */ + __IOM uint32_t RXNE : 1; /*!< [1..1] desc RXNE */ + __IOM uint32_t SSF : 1; /*!< [2..2] desc SSF */ + __IOM uint32_t SSR : 1; /*!< [3..3] desc SSR */ + __IOM uint32_t UD : 1; /*!< [4..4] desc UD */ + __IOM uint32_t OV : 1; /*!< [5..5] desc OV */ + __IOM uint32_t SSERR : 1; /*!< [6..6] desc SSERR */ + __IOM uint32_t MODF : 1; /*!< [7..7] desc MODF */ + } ICR_f; + } ; + + union { + __IOM uint32_t DR; /*!< (@ 0x0000001C) Data register */ + + struct { + __IOM uint32_t DR : 16; /*!< [15..0] desc DR */ + } DR_f; + } ; +} SPI_TypeDef; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Ctrl (SYSCTRL) + */ + +typedef struct { /*!< (@ 0x40004000) SYSCTRL Structure */ + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control Reg0 */ + + struct { + __IOM uint32_t SYSCLK : 3; /*!< [2..0] desc SYSCLK */ + __IOM uint32_t PCLKPRS : 2; /*!< [4..3] desc PCLKPRS */ + __IOM uint32_t HCLKPRS : 3; /*!< [7..5] desc HCLKPRS */ + __IM uint32_t : 8; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR0_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000004) Control Reg1 */ + + struct { + __IOM uint32_t HSIEN : 1; /*!< [0..0] desc HSIEN */ + __IOM uint32_t HSEEN : 1; /*!< [1..1] desc HSEEN */ + __IOM uint32_t PLLEN : 1; /*!< [2..2] desc PLLEN */ + __IOM uint32_t LSIEN : 1; /*!< [3..3] desc LSIEN */ + __IOM uint32_t LSEEN : 1; /*!< [4..4] desc LSEEN */ + __IOM uint32_t LSELOCK : 1; /*!< [5..5] desc LSELOCK */ + __IOM uint32_t LSECCS : 1; /*!< [6..6] desc LSECCS */ + __IOM uint32_t HSECCS : 1; /*!< [7..7] desc HSECCS */ + __IOM uint32_t CLKCCS : 1; /*!< [8..8] desc CLKCCS */ + __IM uint32_t : 7; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000008) Control Reg2 */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t SWDIO : 1; /*!< [1..1] desc SWDIO */ + __IOM uint32_t LOCKUP : 1; /*!< [2..2] desc LOCKUP */ + __IOM uint32_t WAKEUPCLK : 1; /*!< [3..3] desc WAKEUPCLK */ + __IOM uint32_t FLASHWAIT : 3; /*!< [6..4] desc FLASHWAIT */ + __IM uint32_t : 3; + __IOM uint32_t HSEBRKEN : 1; /*!< [10..10] desc HSEBRKEN */ + __IOM uint32_t LSEBRKEN : 1; /*!< [11..11] desc LSEBRKEN */ + __IOM uint32_t CLLBRKEN : 1; /*!< [12..12] desc CLLBRKEN */ + __IOM uint32_t DSBRKEN : 1; /*!< [13..13] desc DSBRKEN */ + __IOM uint32_t LVDBRKEN : 1; /*!< [14..14] desc LVDBRKEN */ + __IOM uint32_t RAMBRKEN : 1; /*!< [15..15] desc RAMBRKEN */ + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } CR2_f; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x0000000C) Interupt Enable Reg */ + + struct { + __IOM uint32_t HSIRDY : 1; /*!< [0..0] desc HSIRDY */ + __IOM uint32_t HSERDY : 1; /*!< [1..1] desc HSERDY */ + __IOM uint32_t PLLRDY : 1; /*!< [2..2] desc PLLRDY */ + __IOM uint32_t LSIRDY : 1; /*!< [3..3] desc LSIRDY */ + __IOM uint32_t LSERDY : 1; /*!< [4..4] desc LSERDY */ + __IOM uint32_t LSEFAIL : 1; /*!< [5..5] desc LSEFAIL */ + __IOM uint32_t HSEFAIL : 1; /*!< [6..6] desc HSEFAIL */ + __IOM uint32_t LSEFAULT : 1; /*!< [7..7] desc LSEFAULT */ + __IOM uint32_t HSEFAULT : 1; /*!< [8..8] desc HSEFAULT */ + __IM uint32_t : 7; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } IER_f; + } ; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000010) Interupt Status Reg */ + + struct { + __IM uint32_t HSIRDY : 1; /*!< [0..0] desc HSIRDY */ + __IM uint32_t HSERDY : 1; /*!< [1..1] desc HSERDY */ + __IM uint32_t PLLRDY : 1; /*!< [2..2] desc PLLRDY */ + __IM uint32_t LSIRDY : 1; /*!< [3..3] desc LSIRDY */ + __IM uint32_t LSERDY : 1; /*!< [4..4] desc LSERDY */ + __IM uint32_t LSEFAIL : 1; /*!< [5..5] desc LSEFAIL */ + __IM uint32_t HSEFAIL : 1; /*!< [6..6] desc HSEFAIL */ + __IM uint32_t LSEFAULT : 1; /*!< [7..7] desc LSEFAULT */ + __IM uint32_t HSEFAULT : 1; /*!< [8..8] desc HSEFAULT */ + __IM uint32_t : 2; + __IM uint32_t HSISTABLE : 1; /*!< [11..11] desc HSISTABLE */ + __IM uint32_t HSESTABLE : 1; /*!< [12..12] desc HSESTABLE */ + __IM uint32_t PLLSTABLE : 1; /*!< [13..13] desc PLLSTABLE */ + __IM uint32_t LSISTABLE : 1; /*!< [14..14] desc LSISTABLE */ + __IM uint32_t LSESTABLE : 1; /*!< [15..15] desc LSESTABLE */ + } ISR_f; + } ; + + union { + __IOM uint32_t ICR; /*!< (@ 0x00000014) Interupt Clear Reg */ + + struct { + __IOM uint32_t HSIRDY : 1; /*!< [0..0] desc HSIRDY */ + __IOM uint32_t HSERDY : 1; /*!< [1..1] desc HSERDY */ + __IOM uint32_t PLLRDY : 1; /*!< [2..2] desc PLLRDY */ + __IOM uint32_t LSIRDY : 1; /*!< [3..3] desc LSIRDY */ + __IOM uint32_t LSERDY : 1; /*!< [4..4] desc LSERDY */ + __IOM uint32_t LSEFAIL : 1; /*!< [5..5] desc LSEFAIL */ + __IOM uint32_t HSEFAIL : 1; /*!< [6..6] desc HSEFAIL */ + __IOM uint32_t LSEFAULT : 1; /*!< [7..7] desc LSEFAULT */ + __IOM uint32_t HSEFAULT : 1; /*!< [8..8] desc HSEFAULT */ + } ICR_f; + } ; + + union { + __IOM uint32_t HSI; /*!< (@ 0x00000018) HSI Control Reg */ + + struct { + __IOM uint32_t TRIM : 11; /*!< [10..0] desc TRIM */ + __IOM uint32_t DIV : 4; /*!< [14..11] desc DIV */ + __IM uint32_t STABLE : 1; /*!< [15..15] desc STABLE */ + } HSI_f; + } ; + + union { + __IOM uint32_t HSE; /*!< (@ 0x0000001C) HEX Control Reg */ + + struct { + __IOM uint32_t DRIVER : 4; /*!< [3..0] desc DRIVER */ + __IOM uint32_t WAITCYCLE : 2; /*!< [5..4] desc WAITCYCLE */ + __IOM uint32_t MODE : 1; /*!< [6..6] desc MODE */ + __IOM uint32_t HEXENPOL : 1; /*!< [7..7] desc HEXENPOL */ + __IOM uint32_t DETCNT : 11; /*!< [18..8] desc DETCNT */ + __IM uint32_t STABLE : 1; /*!< [19..19] desc STABLE */ + __IOM uint32_t PDRIVER : 4; /*!< [23..20] desc PDRIVER */ + __IOM uint32_t DIGFLT : 1; /*!< [24..24] desc DIGFLT */ + } HSE_f; + } ; + + union { + __IOM uint32_t LSI; /*!< (@ 0x00000020) LSI Control Reg */ + + struct { + __IOM uint32_t TRIM : 9; /*!< [8..0] desc TRIM */ + __IM uint32_t : 1; + __IOM uint32_t WAITCYCLE : 2; /*!< [11..10] desc WAITCYCLE */ + __IM uint32_t : 3; + __IM uint32_t STABLE : 1; /*!< [15..15] desc STABLE */ + } LSI_f; + } ; + + union { + __IOM uint32_t LSE; /*!< (@ 0x00000024) LSE Control Reg */ + + struct { + __IOM uint32_t DRIVER : 4; /*!< [3..0] desc DRIVER */ + __IOM uint32_t WAITCYCLE : 2; /*!< [5..4] desc WAITCYCLE */ + __IOM uint32_t MODE : 1; /*!< [6..6] desc MODE */ + __IM uint32_t : 1; + __IOM uint32_t PDRIVER : 4; /*!< [11..8] desc PDRIVER */ + __IM uint32_t : 5; + __IOM uint32_t PINLOCK : 1; /*!< [17..17] desc PINLOCK */ + __IM uint32_t STABLE : 1; /*!< [18..18] desc STABLE */ + } LSE_f; + } ; + + union { + __IOM uint32_t PLL; /*!< (@ 0x00000028) PLL Control Reg */ + + struct { + __IOM uint32_t SOURCE : 1; /*!< [0..0] desc SOURCE */ + __IOM uint32_t DIV : 4; /*!< [4..1] desc DIV */ + __IOM uint32_t WAITCYCLE : 3; /*!< [7..5] desc WAITCYCLE */ + __IOM uint32_t MUL : 8; /*!< [15..8] desc MUL */ + __IM uint32_t STABLE : 1; /*!< [16..16] desc STABLE */ + } PLL_f; + } ; + + union { + __IOM uint32_t DEBUG; /*!< (@ 0x0000002C) Debug Control Reg */ + + struct { + __IOM uint32_t ATIM : 1; /*!< [0..0] desc ATIM */ + __IOM uint32_t GTIM1 : 1; /*!< [1..1] desc GTIM1 */ + __IOM uint32_t GTIM2 : 1; /*!< [2..2] desc GTIM2 */ + __IOM uint32_t GTIM3 : 1; /*!< [3..3] desc GTIM3 */ + __IOM uint32_t GTIM4 : 1; /*!< [4..4] desc GTIM4 */ + __IOM uint32_t BTIM123 : 1; /*!< [5..5] desc BTIM123 */ + __IOM uint32_t LPTIM : 1; /*!< [6..6] desc LPTIM */ + __IM uint32_t : 1; + __IOM uint32_t RTC : 1; /*!< [8..8] desc RTC */ + __IOM uint32_t IWDT : 1; /*!< [9..9] desc IWDT */ + __IOM uint32_t WWDT : 1; /*!< [10..10] desc WWDT */ + __IOM uint32_t HALLTIM : 1; /*!< [11..11] desc HALLTIM */ + } DEBUG_f; + } ; + + union { + __IOM uint32_t AHBEN; /*!< (@ 0x00000030) AHB Clock Control Reg */ + + struct { + __IOM uint32_t DMA : 1; /*!< [0..0] desc DMA */ + __IOM uint32_t FLASH : 1; /*!< [1..1] desc FLASH */ + __IOM uint32_t CRC : 1; /*!< [2..2] desc CRC */ + __IOM uint32_t EAU : 1; /*!< [3..3] desc EAU */ + __IOM uint32_t GPIOA : 1; /*!< [4..4] desc GPIOA */ + __IOM uint32_t GPIOB : 1; /*!< [5..5] desc GPIOB */ + __IOM uint32_t GPIOC : 1; /*!< [6..6] desc GPIOC */ + __IOM uint32_t GPIOF : 1; /*!< [7..7] desc GPIOF */ + __IOM uint32_t CORDIC : 1; /*!< [8..8] desc CORDIC */ + __IM uint32_t : 7; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } AHBEN_f; + } ; + + union { + __IOM uint32_t APBEN2; /*!< (@ 0x00000034) APB Clock Control Reg2 */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t RTC : 1; /*!< [1..1] desc RTC */ + __IOM uint32_t BTIM123 : 1; /*!< [2..2] desc BTIM123 */ + __IM uint32_t : 1; + __IOM uint32_t IWDT : 1; /*!< [4..4] desc IWDT */ + __IOM uint32_t WWDT : 1; /*!< [5..5] desc WWDT */ + __IOM uint32_t I2C1 : 1; /*!< [6..6] desc I2C1 */ + __IOM uint32_t LPTIM : 1; /*!< [7..7] desc LPTIM */ + __IM uint32_t : 1; + __IOM uint32_t OPA : 1; /*!< [9..9] desc OPA */ + __IOM uint32_t DAC : 1; /*!< [10..10] desc DAC */ + __IOM uint32_t I2C2 : 1; /*!< [11..11] desc I2C2 */ + __IOM uint32_t HALLTIM : 1; /*!< [12..12] desc HALLTIM */ + __IM uint32_t : 3; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } APBEN2_f; + } ; + + union { + __IOM uint32_t APBEN1; /*!< (@ 0x00000038) APB Clock Control Reg1 */ + + struct { + __IOM uint32_t ADC : 1; /*!< [0..0] desc ADC */ + __IOM uint32_t VC : 1; /*!< [1..1] desc VC */ + __IOM uint32_t SPI1 : 1; /*!< [2..2] desc SPI1 */ + __IOM uint32_t UART1 : 1; /*!< [3..3] desc UART1 */ + __IOM uint32_t UART2 : 1; /*!< [4..4] desc UART2 */ + __IOM uint32_t ATIM : 1; /*!< [5..5] desc ATIM */ + __IOM uint32_t GTIM1 : 1; /*!< [6..6] desc GTIM1 */ + __IOM uint32_t GTIM2 : 1; /*!< [7..7] desc GTIM2 */ + __IOM uint32_t UART3 : 1; /*!< [8..8] desc UART3 */ + __IM uint32_t : 2; + __IOM uint32_t GTIM3 : 1; /*!< [11..11] desc GTIM3 */ + __IOM uint32_t GTIM4 : 1; /*!< [12..12] desc GTIM4 */ + __IOM uint32_t SPI2 : 1; /*!< [13..13] desc SPI2 */ + __IOM uint32_t SPI3 : 1; /*!< [14..14] desc SPI3 */ + __IM uint32_t : 1; + __OM uint32_t KEY : 16; /*!< [31..16] desc KEY */ + } APBEN1_f; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t AHBRST; /*!< (@ 0x00000040) AHB Reset Control Reg */ + + struct { + __IOM uint32_t DMA : 1; /*!< [0..0] desc DMA */ + __IOM uint32_t FLASH : 1; /*!< [1..1] desc FLASH */ + __IOM uint32_t CRC : 1; /*!< [2..2] desc CRC */ + __IOM uint32_t EAU : 1; /*!< [3..3] desc EAU */ + __IOM uint32_t GPIOA : 1; /*!< [4..4] desc GPIOA */ + __IOM uint32_t GPIOB : 1; /*!< [5..5] desc GPIOB */ + __IOM uint32_t GPIOC : 1; /*!< [6..6] desc GPIOC */ + __IOM uint32_t GPIOF : 1; /*!< [7..7] desc GPIOF */ + __IOM uint32_t CORDIC : 1; /*!< [8..8] desc CORDIC */ + } AHBRST_f; + } ; + + union { + __IOM uint32_t APBRST2; /*!< (@ 0x00000044) APB Reset Control Reg2 */ + + struct { + __IM uint32_t : 1; + __IOM uint32_t RTC : 1; /*!< [1..1] desc RTC */ + __IOM uint32_t BTIM123 : 1; /*!< [2..2] desc BTIM123 */ + __IM uint32_t : 1; + __IOM uint32_t IWDT : 1; /*!< [4..4] desc IWDT */ + __IOM uint32_t WWDT : 1; /*!< [5..5] desc WWDT */ + __IOM uint32_t I2C1 : 1; /*!< [6..6] desc I2C1 */ + __IOM uint32_t LPTIM : 1; /*!< [7..7] desc LPTIM */ + __IM uint32_t : 1; + __IOM uint32_t OPA : 1; /*!< [9..9] desc OPA */ + __IOM uint32_t DAC : 1; /*!< [10..10] desc DAC */ + __IOM uint32_t I2C2 : 1; /*!< [11..11] desc I2C2 */ + __IOM uint32_t HALLTIM : 1; /*!< [12..12] desc HALLTIM */ + } APBRST2_f; + } ; + + union { + __IOM uint32_t APBRST1; /*!< (@ 0x00000048) APB Reset Control Reg1 */ + + struct { + __IOM uint32_t ADC : 1; /*!< [0..0] desc ADC */ + __IOM uint32_t VC : 1; /*!< [1..1] desc VC */ + __IOM uint32_t SPI1 : 1; /*!< [2..2] desc SPI1 */ + __IOM uint32_t UART1 : 1; /*!< [3..3] desc UART1 */ + __IOM uint32_t UART2 : 1; /*!< [4..4] desc UART2 */ + __IOM uint32_t ATIM : 1; /*!< [5..5] desc ATIM */ + __IOM uint32_t GTIM1 : 1; /*!< [6..6] desc GTIM1 */ + __IOM uint32_t GTIM2 : 1; /*!< [7..7] desc GTIM2 */ + __IOM uint32_t UART3 : 1; /*!< [8..8] desc UART3 */ + __IM uint32_t : 2; + __IOM uint32_t GTIM3 : 1; /*!< [11..11] desc GTIM3 */ + __IOM uint32_t GTIM4 : 1; /*!< [12..12] desc GTIM4 */ + __IOM uint32_t SPI2 : 1; /*!< [13..13] desc SPI2 */ + __IOM uint32_t SPI3 : 1; /*!< [14..14] desc SPI3 */ + } APBRST1_f; + } ; + + union { + __IOM uint32_t RESETFLAG; /*!< (@ 0x0000004C) Reset Status Reg */ + + struct { + __IOM uint32_t POR : 1; /*!< [0..0] desc POR */ + __IM uint32_t : 2; + __IOM uint32_t LVD : 1; /*!< [3..3] desc LVD */ + __IOM uint32_t IWDT : 1; /*!< [4..4] desc IWDT */ + __IOM uint32_t WWDT : 1; /*!< [5..5] desc WWDT */ + __IOM uint32_t RSTB : 1; /*!< [6..6] desc RSTB */ + __IM uint32_t : 1; + __IOM uint32_t LOCKUP : 1; /*!< [8..8] desc LOCKUP */ + __IOM uint32_t SYSRESETREQ : 1; /*!< [9..9] desc SYSRESETREQ */ + } RESETFLAG_f; + } ; + __IM uint32_t RESERVED1[8]; + + union { + __IOM uint32_t MCO; /*!< (@ 0x00000070) Master Clock Output Control Reg */ + + struct { + __IOM uint32_t SOURCE : 4; /*!< [3..0] desc SOURCE */ + __IOM uint32_t DIV : 4; /*!< [7..4] desc DIV */ + } MCO_f; + } ; +} SYSCTRL_TypeDef; /*!< Size = 116 (0x74) */ + + + +/* =========================================================================================================================== */ +/* ================ VC1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc VC1 (VC1) + */ + +typedef struct { /*!< (@ 0x40000084) VC1 Structure */ + + union { + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control register0 */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] desc EN */ + __IOM uint32_t RESP : 1; /*!< [1..1] desc RESP */ + __IM uint32_t : 1; + __IOM uint32_t HYS : 1; /*!< [3..3] desc HYS */ + __IM uint32_t : 1; + __IOM uint32_t IE : 1; /*!< [5..5] desc IE */ + __IOM uint32_t POL : 1; /*!< [6..6] desc POL */ + __IOM uint32_t WINDOW : 1; /*!< [7..7] desc WINDOW */ + __IOM uint32_t INN : 2; /*!< [9..8] desc INN */ + __IM uint32_t : 2; + __IOM uint32_t INP : 2; /*!< [13..12] desc INP */ + } CR0_f; + } ; + + union { + __IOM uint32_t CR1; /*!< (@ 0x00000004) Control register1 */ + + struct { + __IOM uint32_t FLTTIME : 4; /*!< [3..0] desc FLTTIME */ + __IOM uint32_t FLTCLK : 1; /*!< [4..4] desc FLTCLK */ + __IOM uint32_t FALLIE : 1; /*!< [5..5] desc FALLIE */ + __IOM uint32_t RISEIE : 1; /*!< [6..6] desc RISEIE */ + __IOM uint32_t HIGHIE : 1; /*!< [7..7] desc HIGHIE */ + __IOM uint32_t BLANKTIME : 3; /*!< [10..8] desc BLANKTIME */ + __IOM uint32_t BLANKLVL : 1; /*!< [11..11] desc BLANKLVL */ + } CR1_f; + } ; + + union { + __IOM uint32_t CR2; /*!< (@ 0x00000008) Control register1 */ + + struct { + __IOM uint32_t ATIMTRGO : 1; /*!< [0..0] desc ATIM1TRGO */ + __IOM uint32_t ATIMTRGO2 : 1; /*!< [1..1] desc ATIM1TRGO2 */ + __IOM uint32_t ATIMOC1REFC : 1; /*!< [2..2] desc ATIM1OC1REFC */ + __IOM uint32_t ATIMOC2REFC : 1; /*!< [3..3] desc ATIM1OC2REFC */ + __IOM uint32_t ATIMOC3REFC : 1; /*!< [4..4] desc ATIM1OC3REFC */ + __IOM uint32_t ATIMOC4REFC : 1; /*!< [5..5] desc ATIM1OC4REFC */ + __IOM uint32_t ATIMOC5REFC : 1; /*!< [6..6] desc ATIM1OC5REFC */ + __IOM uint32_t ATIMOC6REFC : 1; /*!< [7..7] desc ATIM1OC6REFC */ + __IOM uint32_t GTIM1TRGO : 1; /*!< [8..8] desc GTIM1TRGO */ + __IOM uint32_t GTIM1OC1REFC : 1; /*!< [9..9] desc GTIM1OC1REFC */ + __IOM uint32_t GTIM1OC2REFC : 1; /*!< [10..10] desc GTIM1OC2REFC */ + __IOM uint32_t GTIM1OC3REFC : 1; /*!< [11..11] desc GTIM1OC3REFC */ + __IOM uint32_t GTIM1OC4REFC : 1; /*!< [12..12] desc GTIM1OC4REFC */ + __IOM uint32_t GTIM2TRGO : 1; /*!< [13..13] desc GTIM2TRGO */ + __IOM uint32_t GTIM2OC1REFC : 1; /*!< [14..14] desc GTIM2OC1REFC */ + __IOM uint32_t GTIM2OC2REFC : 1; /*!< [15..15] desc GTIM2OC2REFC */ + __IOM uint32_t GTIM2OC3REFC : 1; /*!< [16..16] desc GTIM2OC3REFC */ + __IOM uint32_t GTIM2OC4REFC : 1; /*!< [17..17] desc GTIM2OC4REFC */ + __IOM uint32_t GTIM3TRGO : 1; /*!< [18..18] desc GTIM3TRGO */ + __IOM uint32_t GTIM3OC1REFC : 1; /*!< [19..19] desc GTIM3OC1REFC */ + __IOM uint32_t GTIM3OC2REFC : 1; /*!< [20..20] desc GTIM3OC2REFC */ + __IOM uint32_t GTIM3OC3REFC : 1; /*!< [21..21] desc GTIM3OC3REFC */ + __IOM uint32_t GTIM3OC4REFC : 1; /*!< [22..22] desc GTIM3OC4REFC */ + __IOM uint32_t GTIM4TRGO : 1; /*!< [23..23] desc GTIM4TRGO */ + __IOM uint32_t GTIM4OC1REFC : 1; /*!< [24..24] desc GTIM4OC1REFC */ + __IOM uint32_t GTIM4OC2REFC : 1; /*!< [25..25] desc GTIM4OC2REFC */ + __IOM uint32_t GTIM4OC3REFC : 1; /*!< [26..26] desc GTIM4OC3REFC */ + __IOM uint32_t GTIM4OC4REFC : 1; /*!< [27..27] desc GTIM4OC4REFC */ + __IOM uint32_t BTIM1TRGO : 1; /*!< [28..28] desc BTIM1TRGO */ + __IOM uint32_t BTIM2TRGO : 1; /*!< [29..29] desc BTIM2TRGO */ + __IOM uint32_t BTIM3TRGO : 1; /*!< [30..30] desc BTIM3TRGO */ + __IOM uint32_t HALLTIM1TRGO : 1; /*!< [31..31] desc HALLTIM1TRGO */ + } CR2_f; + } ; + + union { + __IOM uint32_t SR; /*!< (@ 0x0000000C) Status register */ + + struct { + __IOM uint32_t INTF : 1; /*!< [0..0] desc INTF */ + __IM uint32_t FLTV : 1; /*!< [1..1] desc FLTV */ + } SR_f; + } ; +} VC_TypeDef; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ VC12REF ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc VC12REF (VC12REF) + */ + +typedef struct { /*!< (@ 0x40000080) VC12REF Structure */ + + union { + __IOM uint32_t REF; /*!< (@ 0x00000000) VCREF Control register */ + + struct { + __IOM uint32_t DIV : 3; /*!< [2..0] desc DIV */ + __IM uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [4..4] desc EN */ + __IOM uint32_t VIN : 1; /*!< [5..5] desc VIN */ + } REF_f; + } ; +} VCREF_TypeDef; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ WWDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief desc WWDT (WWDT) + */ + +typedef struct { /*!< WWDT Structure */ + + union { + __IOM uint32_t CR0; /*!< Control register0 */ + + struct { + __IOM uint32_t WCNT : 7; /*!< desc WCNT */ + __IOM uint32_t EN : 1; /*!< desc EN */ + } CR0_f; + } ; + + union { + __IOM uint32_t CR1; /*!< Control register1 */ + + struct { + __IOM uint32_t WINR : 7; /*!< desc WINR */ + __IOM uint32_t PRS : 3; /*!< desc PRESCALE */ + __IOM uint32_t IE : 1; /*!< desc IE */ + } CR1_f; + } ; + + union { + __IOM uint32_t SR; /*!< status register */ + + struct { + __IOM uint32_t POV : 1; /*!< desc POV */ + } SR_f; + } ; +} WWDT_TypeDef; /*!< Size = 12 (0xc) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define ADC1_BASE 0x40000000UL +#define ADC2_BASE 0x40000100UL +#define ATIM_BASE 0x40001400UL +#define BGR_BASE 0x400000FCUL +#define BTIM1_BASE 0x40004800UL +#define BTIM2_BASE 0x40004840UL +#define BTIM3_BASE 0x40004880UL +#define CORDIC_BASE 0x40023400UL +#define CRC_BASE 0x40023000UL +#define DAC_BASE 0x400000C0UL +#define DMA_BASE 0x40020000UL +#define DMACHANNEL1_BASE 0x40020020UL +#define DMACHANNEL2_BASE 0x40020040UL +#define DMACHANNEL3_BASE 0x40020060UL +#define DMACHANNEL4_BASE 0x40020080UL +#define EAU_BASE 0x40023200UL +#define FLASH_BASE 0x40022000UL +#define GPIOA_BASE 0x48000000UL +#define GPIOB_BASE 0x48000100UL +#define GPIOC_BASE 0x48000200UL +#define GPIOF_BASE 0x48000300UL +#define GTIM1_BASE 0x40001800UL +#define GTIM2_BASE 0x40001C00UL +#define GTIM3_BASE 0x40002400UL +#define GTIM4_BASE 0x40002800UL +#define HALLTIM_BASE 0x40006400UL +#define I2C1_BASE 0x40005800UL +#define I2C2_BASE 0x40005C00UL +#define IRMOD_BASE 0x40004080UL +#define IWDT_BASE 0x40005000UL +#define LPTIM_BASE 0x40006000UL +#define UART1_BASE 0x40000C00UL +#define UART2_BASE 0x40001000UL +#define UART3_BASE 0x40002000UL +#define LVD_BASE 0x400000A4UL +#define OPA1_BASE 0x400000B0UL +#define OPA2_BASE 0x400000B8UL +#define RAM_BASE 0x40022400UL +#define RTC_BASE 0x40004400UL +#define SPI1_BASE 0x40000800UL +#define SPI2_BASE 0x40000400UL +#define SPI3_BASE 0x40003400UL +#define SYSCTRL_BASE 0x40004000UL +#define VC1_BASE 0x40000084UL +#define VC12REF_BASE 0x40000080UL +#define VC2_BASE 0x40000094UL +#define VC3_BASE 0x40000184UL +#define VC34REF_BASE 0x40000180UL +#define VC4_BASE 0x40000194UL +#define WWDT_BASE 0x40005400UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define CW_ADC1 ((ADC_TypeDef*) ADC1_BASE) +#define CW_ADC2 ((ADC_TypeDef*) ADC2_BASE) +#define CW_ATIM ((ATIM_TypeDef*) ATIM_BASE) +#define CW_BGR ((BGR_TypeDef*) BGR_BASE) +#define CW_BTIM1 ((BTIM_TypeDef*) BTIM1_BASE) +#define CW_BTIM2 ((BTIM_TypeDef*) BTIM2_BASE) +#define CW_BTIM3 ((BTIM_TypeDef*) BTIM3_BASE) +#define CW_CORDIC ((CORDIC_TypeDef*) CORDIC_BASE) +#define CW_CRC ((CRC_TypeDef*) CRC_BASE) +#define CW_DAC ((DAC_TypeDef*) DAC_BASE) +#define CW_DMA ((DMA_TypeDef*) DMA_BASE) +#define CW_DMACHANNEL1 ((DMACHANNEL_TypeDef*) DMACHANNEL1_BASE) +#define CW_DMACHANNEL2 ((DMACHANNEL_TypeDef*) DMACHANNEL2_BASE) +#define CW_DMACHANNEL3 ((DMACHANNEL_TypeDef*) DMACHANNEL3_BASE) +#define CW_DMACHANNEL4 ((DMACHANNEL_TypeDef*) DMACHANNEL4_BASE) +#define CW_EAU ((EAU_TypeDef*) EAU_BASE) +#define CW_FLASH ((FLASH_TypeDef*) FLASH_BASE) +#define CW_GPIOA ((GPIO_TypeDef*) GPIOA_BASE) +#define CW_GPIOB ((GPIO_TypeDef*) GPIOB_BASE) +#define CW_GPIOC ((GPIO_TypeDef*) GPIOC_BASE) +#define CW_GPIOF ((GPIO_TypeDef*) GPIOF_BASE) +#define CW_GTIM1 ((GTIM_TypeDef*) GTIM1_BASE) +#define CW_GTIM2 ((GTIM_TypeDef*) GTIM2_BASE) +#define CW_GTIM3 ((GTIM_TypeDef*) GTIM3_BASE) +#define CW_GTIM4 ((GTIM_TypeDef*) GTIM4_BASE) +#define CW_HALLTIM ((HALLTIM_TypeDef*) HALLTIM_BASE) +#define CW_I2C1 ((I2C_TypeDef*) I2C1_BASE) +#define CW_I2C2 ((I2C_TypeDef*) I2C2_BASE) +#define CW_IRMOD ((IRMOD_TypeDef*) IRMOD_BASE) +#define CW_IWDT ((IWDT_TypeDef*) IWDT_BASE) +#define CW_LPTIM ((LPTIM_TypeDef*) LPTIM_BASE) +#define CW_UART1 ((UART_TypeDef*) UART1_BASE) +#define CW_UART2 ((UART_TypeDef*) UART2_BASE) +#define CW_UART3 ((UART_TypeDef*) UART3_BASE) +#define CW_LVD ((LVD_TypeDef*) LVD_BASE) +#define CW_OPA1 ((OPA_TypeDef*) OPA1_BASE) +#define CW_OPA2 ((OPA_TypeDef*) OPA2_BASE) +#define CW_RAM ((RAM_TypeDef*) RAM_BASE) +#define CW_RTC ((RTC_TypeDef*) RTC_BASE) +#define CW_SPI1 ((SPI_TypeDef*) SPI1_BASE) +#define CW_SPI2 ((SPI_TypeDef*) SPI2_BASE) +#define CW_SPI3 ((SPI_TypeDef*) SPI3_BASE) +#define CW_SYSCTRL ((SYSCTRL_TypeDef*) SYSCTRL_BASE) +#define CW_VC1 ((VC_TypeDef*) VC1_BASE) +#define CW_VC12REF ((VCREF_TypeDef*) VC12REF_BASE) +#define CW_VC2 ((VC_TypeDef*) VC2_BASE) +#define CW_VC3 ((VC_TypeDef*) VC3_BASE) +#define CW_VC34REF ((VCREF_TypeDef*) VC34REF_BASE) +#define CW_VC4 ((VC_TypeDef*) VC4_BASE) +#define CW_WWDT ((WWDT_TypeDef*) WWDT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define ADCx_CR_SLAVE_Pos (7UL) /*!< SLAVE (Bit 7) */ +#define ADCx_CR_SLAVE_Msk (0x80UL) /*!< SLAVE (Bitfield-Mask: 0x01) */ +#define ADCx_CR_ENS_Pos (4UL) /*!< ENS (Bit 4) */ +#define ADCx_CR_ENS_Msk (0x70UL) /*!< ENS (Bitfield-Mask: 0x07) */ +#define ADCx_CR_CLK_Pos (2UL) /*!< CLKSRC (Bit 2) */ +#define ADCx_CR_CLK_Msk (0xcUL) /*!< CLKSRC (Bitfield-Mask: 0x03) */ +#define ADCx_CR_CONT_Pos (1UL) /*!< CONT (Bit 1) */ +#define ADCx_CR_CONT_Msk (0x2UL) /*!< CONT (Bitfield-Mask: 0x01) */ +#define ADCx_CR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define ADCx_CR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= START ========================================================= */ +#define ADCx_START_START_Pos (0UL) /*!< START (Bit 0) */ +#define ADCx_START_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= AWDTR ========================================================= */ +#define ADCx_AWDTR_VTH_Pos (16UL) /*!< VTH (Bit 16) */ +#define ADCx_AWDTR_VTH_Msk (0xfff0000UL) /*!< VTH (Bitfield-Mask: 0xfff) */ +#define ADCx_AWDTR_VTL_Pos (0UL) /*!< VTL (Bit 0) */ +#define ADCx_AWDTR_VTL_Msk (0xfffUL) /*!< VTL (Bitfield-Mask: 0xfff) */ +/* ========================================================= AWDCR ========================================================= */ +#define ADCx_AWDCR_IN15_Pos (15UL) /*!< IN15 (Bit 15) */ +#define ADCx_AWDCR_IN15_Msk (0x8000UL) /*!< IN15 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN14_Pos (14UL) /*!< IN14 (Bit 14) */ +#define ADCx_AWDCR_IN14_Msk (0x4000UL) /*!< IN14 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN13_Pos (13UL) /*!< IN13 (Bit 13) */ +#define ADCx_AWDCR_IN13_Msk (0x2000UL) /*!< IN13 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN12_Pos (12UL) /*!< IN12 (Bit 12) */ +#define ADCx_AWDCR_IN12_Msk (0x1000UL) /*!< IN12 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN11_Pos (11UL) /*!< IN11 (Bit 11) */ +#define ADCx_AWDCR_IN11_Msk (0x800UL) /*!< IN11 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN10_Pos (10UL) /*!< IN10 (Bit 10) */ +#define ADCx_AWDCR_IN10_Msk (0x400UL) /*!< IN10 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN9_Pos (9UL) /*!< IN9 (Bit 9) */ +#define ADCx_AWDCR_IN9_Msk (0x200UL) /*!< IN9 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN8_Pos (8UL) /*!< IN8 (Bit 8) */ +#define ADCx_AWDCR_IN8_Msk (0x100UL) /*!< IN8 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN7_Pos (7UL) /*!< IN7 (Bit 7) */ +#define ADCx_AWDCR_IN7_Msk (0x80UL) /*!< IN7 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN6_Pos (6UL) /*!< IN6 (Bit 6) */ +#define ADCx_AWDCR_IN6_Msk (0x40UL) /*!< IN6 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN5_Pos (5UL) /*!< IN5 (Bit 5) */ +#define ADCx_AWDCR_IN5_Msk (0x20UL) /*!< IN5 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN4_Pos (4UL) /*!< IN4 (Bit 4) */ +#define ADCx_AWDCR_IN4_Msk (0x10UL) /*!< IN4 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN3_Pos (3UL) /*!< IN3 (Bit 3) */ +#define ADCx_AWDCR_IN3_Msk (0x8UL) /*!< IN3 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN2_Pos (2UL) /*!< IN2 (Bit 2) */ +#define ADCx_AWDCR_IN2_Msk (0x4UL) /*!< IN2 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN1_Pos (1UL) /*!< IN1 (Bit 1) */ +#define ADCx_AWDCR_IN1_Msk (0x2UL) /*!< IN1 (Bitfield-Mask: 0x01) */ +#define ADCx_AWDCR_IN0_Pos (0UL) /*!< IN0 (Bit 0) */ +#define ADCx_AWDCR_IN0_Msk (0x1UL) /*!< IN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== TRIGGER ======================================================== */ +#define ADCx_TRIGGER_HALLTIMTRGO_Pos (31UL) /*!< HALLTIMTRGO (Bit 31) */ +#define ADCx_TRIGGER_HALLTIMTRGO_Msk (0x80000000UL) /*!< HALLTIMTRGO (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_BTIM3TRGO_Pos (30UL) /*!< BTIM3TRGO (Bit 30) */ +#define ADCx_TRIGGER_BTIM3TRGO_Msk (0x40000000UL) /*!< BTIM3TRGO (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_BTIM2TRGO_Pos (29UL) /*!< BTIM2TRGO (Bit 29) */ +#define ADCx_TRIGGER_BTIM2TRGO_Msk (0x20000000UL) /*!< BTIM2TRGO (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_BTIM1TRGO_Pos (28UL) /*!< BTIM1TRGO (Bit 28) */ +#define ADCx_TRIGGER_BTIM1TRGO_Msk (0x10000000UL) /*!< BTIM1TRGO (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM4OC4REFC_Pos (27UL) /*!< GTIM4OC4REFC (Bit 27) */ +#define ADCx_TRIGGER_GTIM4OC4REFC_Msk (0x8000000UL) /*!< GTIM4OC4REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM4OC3REFC_Pos (26UL) /*!< GTIM4OC3REFC (Bit 26) */ +#define ADCx_TRIGGER_GTIM4OC3REFC_Msk (0x4000000UL) /*!< GTIM4OC3REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM4OC2REFC_Pos (25UL) /*!< GTIM4OC2REFC (Bit 25) */ +#define ADCx_TRIGGER_GTIM4OC2REFC_Msk (0x2000000UL) /*!< GTIM4OC2REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM4OC1REFC_Pos (24UL) /*!< GTIM4OC1REFC (Bit 24) */ +#define ADCx_TRIGGER_GTIM4OC1REFC_Msk (0x1000000UL) /*!< GTIM4OC1REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM4TRGO_Pos (23UL) /*!< GTIM4TRGO (Bit 23) */ +#define ADCx_TRIGGER_GTIM4TRGO_Msk (0x800000UL) /*!< GTIM4TRGO (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM3OC4REFC_Pos (22UL) /*!< GTIM3OC4REFC (Bit 22) */ +#define ADCx_TRIGGER_GTIM3OC4REFC_Msk (0x400000UL) /*!< GTIM3OC4REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM3OC3REFC_Pos (21UL) /*!< GTIM3OC3REFC (Bit 21) */ +#define ADCx_TRIGGER_GTIM3OC3REFC_Msk (0x200000UL) /*!< GTIM3OC3REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM3OC2REFC_Pos (20UL) /*!< GTIM3OC2REFC (Bit 20) */ +#define ADCx_TRIGGER_GTIM3OC2REFC_Msk (0x100000UL) /*!< GTIM3OC2REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM3OC1REFC_Pos (19UL) /*!< GTIM3OC1REFC (Bit 19) */ +#define ADCx_TRIGGER_GTIM3OC1REFC_Msk (0x80000UL) /*!< GTIM3OC1REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM3TRGO_Pos (18UL) /*!< GTIM3TRGO (Bit 18) */ +#define ADCx_TRIGGER_GTIM3TRGO_Msk (0x40000UL) /*!< GTIM3TRGO (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM2OC4REFC_Pos (17UL) /*!< GTIM2OC4REFC (Bit 17) */ +#define ADCx_TRIGGER_GTIM2OC4REFC_Msk (0x20000UL) /*!< GTIM2OC4REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM2OC3REFC_Pos (16UL) /*!< GTIM2OC3REFC (Bit 16) */ +#define ADCx_TRIGGER_GTIM2OC3REFC_Msk (0x10000UL) /*!< GTIM2OC3REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM2OC2REFC_Pos (15UL) /*!< GTIM2OC2REFC (Bit 15) */ +#define ADCx_TRIGGER_GTIM2OC2REFC_Msk (0x8000UL) /*!< GTIM2OC2REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM2OC1REFC_Pos (14UL) /*!< GTIM2OC1REFC (Bit 14) */ +#define ADCx_TRIGGER_GTIM2OC1REFC_Msk (0x4000UL) /*!< GTIM2OC1REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM2TRGO_Pos (13UL) /*!< GTIM2TRGO (Bit 13) */ +#define ADCx_TRIGGER_GTIM2TRGO_Msk (0x2000UL) /*!< GTIM2TRGO (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM1OC4REFC_Pos (12UL) /*!< GTIM1OC4REFC (Bit 12) */ +#define ADCx_TRIGGER_GTIM1OC4REFC_Msk (0x1000UL) /*!< GTIM1OC4REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM1OC3REFC_Pos (11UL) /*!< GTIM1OC3REFC (Bit 11) */ +#define ADCx_TRIGGER_GTIM1OC3REFC_Msk (0x800UL) /*!< GTIM1OC3REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM1OC2REFC_Pos (10UL) /*!< GTIM1OC2REFC (Bit 10) */ +#define ADCx_TRIGGER_GTIM1OC2REFC_Msk (0x400UL) /*!< GTIM1OC2REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM1OC1REFC_Pos (9UL) /*!< GTIM1OC1REFC (Bit 9) */ +#define ADCx_TRIGGER_GTIM1OC1REFC_Msk (0x200UL) /*!< GTIM1OC1REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_GTIM1TRGO_Pos (8UL) /*!< GTIM1TRGO (Bit 8) */ +#define ADCx_TRIGGER_GTIM1TRGO_Msk (0x100UL) /*!< GTIM1TRGO (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_ATIMOC6REFC_Pos (7UL) /*!< ATIMOC6REFC (Bit 7) */ +#define ADCx_TRIGGER_ATIMOC6REFC_Msk (0x80UL) /*!< ATIMOC6REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_ATIMOC5REFC_Pos (6UL) /*!< ATIMOC5REFC (Bit 6) */ +#define ADCx_TRIGGER_ATIMOC5REFC_Msk (0x40UL) /*!< ATIMOC5REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_ATIMOC4REFC_Pos (5UL) /*!< ATIMOC4REFC (Bit 5) */ +#define ADCx_TRIGGER_ATIMOC4REFC_Msk (0x20UL) /*!< ATIMOC4REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_ATIMOC3REFC_Pos (4UL) /*!< ATIMOC3REFC (Bit 4) */ +#define ADCx_TRIGGER_ATIMOC3REFC_Msk (0x10UL) /*!< ATIMOC3REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_ATIMOC2REFC_Pos (3UL) /*!< ATIMOC2REFC (Bit 3) */ +#define ADCx_TRIGGER_ATIMOC2REFC_Msk (0x8UL) /*!< ATIMOC2REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_ATIMOC1REFC_Pos (2UL) /*!< ATIMOC1REFC (Bit 2) */ +#define ADCx_TRIGGER_ATIMOC1REFC_Msk (0x4UL) /*!< ATIMOC1REFC (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_ATIMTRGO2_Pos (1UL) /*!< ATIMTRGO2 (Bit 1) */ +#define ADCx_TRIGGER_ATIMTRGO2_Msk (0x2UL) /*!< ATIMTRGO2 (Bitfield-Mask: 0x01) */ +#define ADCx_TRIGGER_ATIMTRGO_Pos (0UL) /*!< ATIMTRGO (Bit 0) */ +#define ADCx_TRIGGER_ATIMTRGO_Msk (0x1UL) /*!< ATIMTRGO (Bitfield-Mask: 0x01) */ +/* ======================================================== SAMPLE ========================================================= */ +#define ADCx_SAMPLE_SQRCH7_Pos (28UL) /*!< SQRCH7 (Bit 28) */ +#define ADCx_SAMPLE_SQRCH7_Msk (0xf0000000UL) /*!< SQRCH7 (Bitfield-Mask: 0x0f) */ +#define ADCx_SAMPLE_SQRCH6_Pos (24UL) /*!< SQRCH6 (Bit 24) */ +#define ADCx_SAMPLE_SQRCH6_Msk (0xf000000UL) /*!< SQRCH6 (Bitfield-Mask: 0x0f) */ +#define ADCx_SAMPLE_SQRCH5_Pos (20UL) /*!< SQRCH5 (Bit 20) */ +#define ADCx_SAMPLE_SQRCH5_Msk (0xf00000UL) /*!< SQRCH5 (Bitfield-Mask: 0x0f) */ +#define ADCx_SAMPLE_SQRCH4_Pos (16UL) /*!< SQRCH4 (Bit 16) */ +#define ADCx_SAMPLE_SQRCH4_Msk (0xf0000UL) /*!< SQRCH4 (Bitfield-Mask: 0x0f) */ +#define ADCx_SAMPLE_SQRCH3_Pos (12UL) /*!< SQRCH3 (Bit 12) */ +#define ADCx_SAMPLE_SQRCH3_Msk (0xf000UL) /*!< SQRCH3 (Bitfield-Mask: 0x0f) */ +#define ADCx_SAMPLE_SQRCH2_Pos (8UL) /*!< SQRCH2 (Bit 8) */ +#define ADCx_SAMPLE_SQRCH2_Msk (0xf00UL) /*!< SQRCH2 (Bitfield-Mask: 0x0f) */ +#define ADCx_SAMPLE_SQRCH1_Pos (4UL) /*!< SQRCH1 (Bit 4) */ +#define ADCx_SAMPLE_SQRCH1_Msk (0xf0UL) /*!< SQRCH1 (Bitfield-Mask: 0x0f) */ +#define ADCx_SAMPLE_SQRCH0_Pos (0UL) /*!< SQRCH0 (Bit 0) */ +#define ADCx_SAMPLE_SQRCH0_Msk (0xfUL) /*!< SQRCH0 (Bitfield-Mask: 0x0f) */ +/* ======================================================== SQRCFR ========================================================= */ +#define ADCx_SQRCFR_SQRCH7_Pos (28UL) /*!< SQRCH7 (Bit 28) */ +#define ADCx_SQRCFR_SQRCH7_Msk (0xf0000000UL) /*!< SQRCH7 (Bitfield-Mask: 0x0f) */ +#define ADCx_SQRCFR_SQRCH6_Pos (24UL) /*!< SQRCH6 (Bit 24) */ +#define ADCx_SQRCFR_SQRCH6_Msk (0xf000000UL) /*!< SQRCH6 (Bitfield-Mask: 0x0f) */ +#define ADCx_SQRCFR_SQRCH5_Pos (20UL) /*!< SQRCH5 (Bit 20) */ +#define ADCx_SQRCFR_SQRCH5_Msk (0xf00000UL) /*!< SQRCH5 (Bitfield-Mask: 0x0f) */ +#define ADCx_SQRCFR_SQRCH4_Pos (16UL) /*!< SQRCH4 (Bit 16) */ +#define ADCx_SQRCFR_SQRCH4_Msk (0xf0000UL) /*!< SQRCH4 (Bitfield-Mask: 0x0f) */ +#define ADCx_SQRCFR_SQRCH3_Pos (12UL) /*!< SQRCH3 (Bit 12) */ +#define ADCx_SQRCFR_SQRCH3_Msk (0xf000UL) /*!< SQRCH3 (Bitfield-Mask: 0x0f) */ +#define ADCx_SQRCFR_SQRCH2_Pos (8UL) /*!< SQRCH2 (Bit 8) */ +#define ADCx_SQRCFR_SQRCH2_Msk (0xf00UL) /*!< SQRCH2 (Bitfield-Mask: 0x0f) */ +#define ADCx_SQRCFR_SQRCH1_Pos (4UL) /*!< SQRCH1 (Bit 4) */ +#define ADCx_SQRCFR_SQRCH1_Msk (0xf0UL) /*!< SQRCH1 (Bitfield-Mask: 0x0f) */ +#define ADCx_SQRCFR_SQRCH0_Pos (0UL) /*!< SQRCH0 (Bit 0) */ +#define ADCx_SQRCFR_SQRCH0_Msk (0xfUL) /*!< SQRCH0 (Bitfield-Mask: 0x0f) */ +/* ========================================================== IER ========================================================== */ +#define ADCx_IER_DMAEOS_Pos (6UL) /*!< DMAEOS (Bit 6) */ +#define ADCx_IER_DMAEOS_Msk (0x40UL) /*!< DMAEOS (Bitfield-Mask: 0x01) */ +#define ADCx_IER_DMAEOC_Pos (5UL) /*!< DMAEOC (Bit 5) */ +#define ADCx_IER_DMAEOC_Msk (0x20UL) /*!< DMAEOC (Bitfield-Mask: 0x01) */ +#define ADCx_IER_AWDH_Pos (4UL) /*!< AWDH (Bit 4) */ +#define ADCx_IER_AWDH_Msk (0x10UL) /*!< AWDH (Bitfield-Mask: 0x01) */ +#define ADCx_IER_AWDL_Pos (3UL) /*!< AWDL (Bit 3) */ +#define ADCx_IER_AWDL_Msk (0x8UL) /*!< AWDL (Bitfield-Mask: 0x01) */ +#define ADCx_IER_EOS_Pos (1UL) /*!< EOS (Bit 1) */ +#define ADCx_IER_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */ +#define ADCx_IER_EOC_Pos (0UL) /*!< EOC (Bit 0) */ +#define ADCx_IER_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define ADCx_ISR_AWDH_Pos (4UL) /*!< AWDH (Bit 4) */ +#define ADCx_ISR_AWDH_Msk (0x10UL) /*!< AWDH (Bitfield-Mask: 0x01) */ +#define ADCx_ISR_AWDL_Pos (3UL) /*!< AWDL (Bit 3) */ +#define ADCx_ISR_AWDL_Msk (0x8UL) /*!< AWDL (Bitfield-Mask: 0x01) */ +#define ADCx_ISR_EOS_Pos (1UL) /*!< EOS (Bit 1) */ +#define ADCx_ISR_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */ +#define ADCx_ISR_EOC_Pos (0UL) /*!< EOC (Bit 0) */ +#define ADCx_ISR_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define ADCx_ICR_AWDH_Pos (4UL) /*!< AWDH (Bit 4) */ +#define ADCx_ICR_AWDH_Msk (0x10UL) /*!< AWDH (Bitfield-Mask: 0x01) */ +#define ADCx_ICR_AWDL_Pos (3UL) /*!< AWDL (Bit 3) */ +#define ADCx_ICR_AWDL_Msk (0x8UL) /*!< AWDL (Bitfield-Mask: 0x01) */ +#define ADCx_ICR_EOS_Pos (1UL) /*!< EOS (Bit 1) */ +#define ADCx_ICR_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */ +#define ADCx_ICR_EOC_Pos (0UL) /*!< EOC (Bit 0) */ +#define ADCx_ICR_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */ +/* ======================================================== RESULT0 ======================================================== */ +#define ADCx_RESULT0_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADCx_RESULT0_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT1 ======================================================== */ +#define ADCx_RESULT1_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADCx_RESULT1_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT2 ======================================================== */ +#define ADCx_RESULT2_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADCx_RESULT2_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT3 ======================================================== */ +#define ADCx_RESULT3_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADCx_RESULT3_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT4 ======================================================== */ +#define ADCx_RESULT4_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADCx_RESULT4_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT5 ======================================================== */ +#define ADCx_RESULT5_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADCx_RESULT5_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT6 ======================================================== */ +#define ADCx_RESULT6_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADCx_RESULT6_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ +/* ======================================================== RESULT7 ======================================================== */ +#define ADCx_RESULT7_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define ADCx_RESULT7_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ ATIM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define ATIM_CR1_UIFREMAP_Pos (11UL) /*!< UIFREMAP (Bit 11) */ +#define ATIM_CR1_UIFREMAP_Msk (0x800UL) /*!< UIFREMAP (Bitfield-Mask: 0x01) */ +#define ATIM_CR1_CKD_Pos (8UL) /*!< CKD (Bit 8) */ +#define ATIM_CR1_CKD_Msk (0x300UL) /*!< CKD (Bitfield-Mask: 0x03) */ +#define ATIM_CR1_ARPE_Pos (7UL) /*!< ARPE (Bit 7) */ +#define ATIM_CR1_ARPE_Msk (0x80UL) /*!< ARPE (Bitfield-Mask: 0x01) */ +#define ATIM_CR1_CMS_Pos (5UL) /*!< CMS (Bit 5) */ +#define ATIM_CR1_CMS_Msk (0x60UL) /*!< CMS (Bitfield-Mask: 0x03) */ +#define ATIM_CR1_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define ATIM_CR1_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define ATIM_CR1_OPM_Pos (3UL) /*!< OPM (Bit 3) */ +#define ATIM_CR1_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */ +#define ATIM_CR1_URS_Pos (2UL) /*!< URS (Bit 2) */ +#define ATIM_CR1_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */ +#define ATIM_CR1_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */ +#define ATIM_CR1_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */ +#define ATIM_CR1_CEN_Pos (0UL) /*!< CEN (Bit 0) */ +#define ATIM_CR1_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define ATIM_CR2_MMSH_Pos (25UL) /*!< MMSH (Bit 25) */ +#define ATIM_CR2_MMSH_Msk (0x6000000UL) /*!< MMSH (Bitfield-Mask: 0x03) */ +#define ATIM_CR2_MMS2_Pos (20UL) /*!< MMS2 (Bit 20) */ +#define ATIM_CR2_MMS2_Msk (0x1f00000UL) /*!< MMS2 (Bitfield-Mask: 0x1f) */ +#define ATIM_CR2_OIS6N_Pos (19UL) /*!< OIS6N (Bit 19) */ +#define ATIM_CR2_OIS6N_Msk (0x80000UL) /*!< OIS6N (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS6_Pos (18UL) /*!< OIS6 (Bit 18) */ +#define ATIM_CR2_OIS6_Msk (0x40000UL) /*!< OIS6 (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS5N_Pos (17UL) /*!< OIS5N (Bit 17) */ +#define ATIM_CR2_OIS5N_Msk (0x20000UL) /*!< OIS5N (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS5_Pos (16UL) /*!< OIS5 (Bit 16) */ +#define ATIM_CR2_OIS5_Msk (0x10000UL) /*!< OIS5 (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS4N_Pos (15UL) /*!< OIS4N (Bit 15) */ +#define ATIM_CR2_OIS4N_Msk (0x8000UL) /*!< OIS4N (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS4_Pos (14UL) /*!< OIS4 (Bit 14) */ +#define ATIM_CR2_OIS4_Msk (0x4000UL) /*!< OIS4 (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS3N_Pos (13UL) /*!< OIS3N (Bit 13) */ +#define ATIM_CR2_OIS3N_Msk (0x2000UL) /*!< OIS3N (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS3_Pos (12UL) /*!< OIS3 (Bit 12) */ +#define ATIM_CR2_OIS3_Msk (0x1000UL) /*!< OIS3 (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS2N_Pos (11UL) /*!< OIS2N (Bit 11) */ +#define ATIM_CR2_OIS2N_Msk (0x800UL) /*!< OIS2N (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS2_Pos (10UL) /*!< OIS2 (Bit 10) */ +#define ATIM_CR2_OIS2_Msk (0x400UL) /*!< OIS2 (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS1N_Pos (9UL) /*!< OIS1N (Bit 9) */ +#define ATIM_CR2_OIS1N_Msk (0x200UL) /*!< OIS1N (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_OIS1_Pos (8UL) /*!< OIS1 (Bit 8) */ +#define ATIM_CR2_OIS1_Msk (0x100UL) /*!< OIS1 (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_TI1S_Pos (7UL) /*!< TI1S (Bit 7) */ +#define ATIM_CR2_TI1S_Msk (0x80UL) /*!< TI1S (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_MMS_Pos (4UL) /*!< MMS (Bit 4) */ +#define ATIM_CR2_MMS_Msk (0x70UL) /*!< MMS (Bitfield-Mask: 0x07) */ +#define ATIM_CR2_CCDS_Pos (3UL) /*!< CCDS (Bit 3) */ +#define ATIM_CR2_CCDS_Msk (0x8UL) /*!< CCDS (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_CCUS_Pos (2UL) /*!< CCUS (Bit 2) */ +#define ATIM_CR2_CCUS_Msk (0x4UL) /*!< CCUS (Bitfield-Mask: 0x01) */ +#define ATIM_CR2_CCPC_Pos (0UL) /*!< CCPC (Bit 0) */ +#define ATIM_CR2_CCPC_Msk (0x1UL) /*!< CCPC (Bitfield-Mask: 0x01) */ +/* ========================================================= SMCR ========================================================== */ +#define ATIM_SMCR_SMSPS_Pos (25UL) /*!< SMSPS (Bit 25) */ +#define ATIM_SMCR_SMSPS_Msk (0x2000000UL) /*!< SMSPS (Bitfield-Mask: 0x01) */ +#define ATIM_SMCR_SMSPE_Pos (24UL) /*!< SMSPE (Bit 24) */ +#define ATIM_SMCR_SMSPE_Msk (0x1000000UL) /*!< SMSPE (Bitfield-Mask: 0x01) */ +#define ATIM_SMCR_TSH_Pos (20UL) /*!< TSH (Bit 20) */ +#define ATIM_SMCR_TSH_Msk (0x300000UL) /*!< TSH (Bitfield-Mask: 0x03) */ +#define ATIM_SMCR_SMSH_Pos (16UL) /*!< SMSH (Bit 16) */ +#define ATIM_SMCR_SMSH_Msk (0x10000UL) /*!< SMSH (Bitfield-Mask: 0x01) */ +#define ATIM_SMCR_ETP_Pos (15UL) /*!< ETP (Bit 15) */ +#define ATIM_SMCR_ETP_Msk (0x8000UL) /*!< ETP (Bitfield-Mask: 0x01) */ +#define ATIM_SMCR_ECE_Pos (14UL) /*!< ECE (Bit 14) */ +#define ATIM_SMCR_ECE_Msk (0x4000UL) /*!< ECE (Bitfield-Mask: 0x01) */ +#define ATIM_SMCR_ETPS_Pos (12UL) /*!< ETPS (Bit 12) */ +#define ATIM_SMCR_ETPS_Msk (0x3000UL) /*!< ETPS (Bitfield-Mask: 0x03) */ +#define ATIM_SMCR_ETF_Pos (8UL) /*!< ETF (Bit 8) */ +#define ATIM_SMCR_ETF_Msk (0xf00UL) /*!< ETF (Bitfield-Mask: 0x0f) */ +#define ATIM_SMCR_MSM_Pos (7UL) /*!< MSM (Bit 7) */ +#define ATIM_SMCR_MSM_Msk (0x80UL) /*!< MSM (Bitfield-Mask: 0x01) */ +#define ATIM_SMCR_TS_Pos (4UL) /*!< TS (Bit 4) */ +#define ATIM_SMCR_TS_Msk (0x70UL) /*!< TS (Bitfield-Mask: 0x07) */ +#define ATIM_SMCR_OCCS_Pos (3UL) /*!< OCCS (Bit 3) */ +#define ATIM_SMCR_OCCS_Msk (0x8UL) /*!< OCCS (Bitfield-Mask: 0x01) */ +#define ATIM_SMCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */ +#define ATIM_SMCR_SMS_Msk (0x7UL) /*!< SMS (Bitfield-Mask: 0x07) */ +/* ========================================================== IER ========================================================== */ +#define ATIM_IER_TERRIE_Pos (23UL) /*!< TERRIE (Bit 23) */ +#define ATIM_IER_TERRIE_Msk (0x800000UL) /*!< TERRIE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_IERRIE_Pos (22UL) /*!< IERRIE (Bit 22) */ +#define ATIM_IER_IERRIE_Msk (0x400000UL) /*!< IERRIE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_DIRIE_Pos (21UL) /*!< DIRIE (Bit 21) */ +#define ATIM_IER_DIRIE_Msk (0x200000UL) /*!< DIRIE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_IDXIE_Pos (20UL) /*!< IDXIE (Bit 20) */ +#define ATIM_IER_IDXIE_Msk (0x100000UL) /*!< IDXIE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC6DE_Pos (19UL) /*!< CC6DE (Bit 19) */ +#define ATIM_IER_CC6DE_Msk (0x80000UL) /*!< CC6DE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC5DE_Pos (18UL) /*!< CC5DE (Bit 18) */ +#define ATIM_IER_CC5DE_Msk (0x40000UL) /*!< CC5DE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC6IE_Pos (17UL) /*!< CC6IE (Bit 17) */ +#define ATIM_IER_CC6IE_Msk (0x20000UL) /*!< CC6IE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC5IE_Pos (16UL) /*!< CC5IE (Bit 16) */ +#define ATIM_IER_CC5IE_Msk (0x10000UL) /*!< CC5IE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_TDE_Pos (14UL) /*!< TDE (Bit 14) */ +#define ATIM_IER_TDE_Msk (0x4000UL) /*!< TDE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_COMDE_Pos (13UL) /*!< COMDE (Bit 13) */ +#define ATIM_IER_COMDE_Msk (0x2000UL) /*!< COMDE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC4DE_Pos (12UL) /*!< CC4DE (Bit 12) */ +#define ATIM_IER_CC4DE_Msk (0x1000UL) /*!< CC4DE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC3DE_Pos (11UL) /*!< CC3DE (Bit 11) */ +#define ATIM_IER_CC3DE_Msk (0x800UL) /*!< CC3DE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC2DE_Pos (10UL) /*!< CC2DE (Bit 10) */ +#define ATIM_IER_CC2DE_Msk (0x400UL) /*!< CC2DE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC1DE_Pos (9UL) /*!< CC1DE (Bit 9) */ +#define ATIM_IER_CC1DE_Msk (0x200UL) /*!< CC1DE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_UDE_Pos (8UL) /*!< UDE (Bit 8) */ +#define ATIM_IER_UDE_Msk (0x100UL) /*!< UDE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_BIE_Pos (7UL) /*!< BIE (Bit 7) */ +#define ATIM_IER_BIE_Msk (0x80UL) /*!< BIE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_TIE_Pos (6UL) /*!< TIE (Bit 6) */ +#define ATIM_IER_TIE_Msk (0x40UL) /*!< TIE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_COMIE_Pos (5UL) /*!< COMIE (Bit 5) */ +#define ATIM_IER_COMIE_Msk (0x20UL) /*!< COMIE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC4IE_Pos (4UL) /*!< CC4IE (Bit 4) */ +#define ATIM_IER_CC4IE_Msk (0x10UL) /*!< CC4IE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC3IE_Pos (3UL) /*!< CC3IE (Bit 3) */ +#define ATIM_IER_CC3IE_Msk (0x8UL) /*!< CC3IE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC2IE_Pos (2UL) /*!< CC2IE (Bit 2) */ +#define ATIM_IER_CC2IE_Msk (0x4UL) /*!< CC2IE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_CC1IE_Pos (1UL) /*!< CC1IE (Bit 1) */ +#define ATIM_IER_CC1IE_Msk (0x2UL) /*!< CC1IE (Bitfield-Mask: 0x01) */ +#define ATIM_IER_UIE_Pos (0UL) /*!< UIE (Bit 0) */ +#define ATIM_IER_UIE_Msk (0x1UL) /*!< UIE (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define ATIM_ISR_TERRF_Pos (23UL) /*!< TERRF (Bit 23) */ +#define ATIM_ISR_TERRF_Msk (0x800000UL) /*!< TERRF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_IERRF_Pos (22UL) /*!< IERRF (Bit 22) */ +#define ATIM_ISR_IERRF_Msk (0x400000UL) /*!< IERRF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_DIRF_Pos (21UL) /*!< DIRF (Bit 21) */ +#define ATIM_ISR_DIRF_Msk (0x200000UL) /*!< DIRF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_IDXF_Pos (20UL) /*!< IDXF (Bit 20) */ +#define ATIM_ISR_IDXF_Msk (0x100000UL) /*!< IDXF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC6OF_Pos (19UL) /*!< CC6OF (Bit 19) */ +#define ATIM_ISR_CC6OF_Msk (0x80000UL) /*!< CC6OF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC5OF_Pos (18UL) /*!< CC5OF (Bit 18) */ +#define ATIM_ISR_CC5OF_Msk (0x40000UL) /*!< CC5OF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC6IF_Pos (17UL) /*!< CC6IF (Bit 17) */ +#define ATIM_ISR_CC6IF_Msk (0x20000UL) /*!< CC6IF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC5IF_Pos (16UL) /*!< CC5IF (Bit 16) */ +#define ATIM_ISR_CC5IF_Msk (0x10000UL) /*!< CC5IF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_SBIF_Pos (13UL) /*!< SBIF (Bit 13) */ +#define ATIM_ISR_SBIF_Msk (0x2000UL) /*!< SBIF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC4OF_Pos (12UL) /*!< CC4OF (Bit 12) */ +#define ATIM_ISR_CC4OF_Msk (0x1000UL) /*!< CC4OF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC3OF_Pos (11UL) /*!< CC3OF (Bit 11) */ +#define ATIM_ISR_CC3OF_Msk (0x800UL) /*!< CC3OF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC2OF_Pos (10UL) /*!< CC2OF (Bit 10) */ +#define ATIM_ISR_CC2OF_Msk (0x400UL) /*!< CC2OF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC1OF_Pos (9UL) /*!< CC1OF (Bit 9) */ +#define ATIM_ISR_CC1OF_Msk (0x200UL) /*!< CC1OF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_B2IF_Pos (8UL) /*!< B2IF (Bit 8) */ +#define ATIM_ISR_B2IF_Msk (0x100UL) /*!< B2IF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_BIF_Pos (7UL) /*!< BIF (Bit 7) */ +#define ATIM_ISR_BIF_Msk (0x80UL) /*!< BIF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_TIF_Pos (6UL) /*!< TIF (Bit 6) */ +#define ATIM_ISR_TIF_Msk (0x40UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_COMIF_Pos (5UL) /*!< COMIF (Bit 5) */ +#define ATIM_ISR_COMIF_Msk (0x20UL) /*!< COMIF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC4IF_Pos (4UL) /*!< CC4IF (Bit 4) */ +#define ATIM_ISR_CC4IF_Msk (0x10UL) /*!< CC4IF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC3IF_Pos (3UL) /*!< CC3IF (Bit 3) */ +#define ATIM_ISR_CC3IF_Msk (0x8UL) /*!< CC3IF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC2IF_Pos (2UL) /*!< CC2IF (Bit 2) */ +#define ATIM_ISR_CC2IF_Msk (0x4UL) /*!< CC2IF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_CC1IF_Pos (1UL) /*!< CC1IF (Bit 1) */ +#define ATIM_ISR_CC1IF_Msk (0x2UL) /*!< CC1IF (Bitfield-Mask: 0x01) */ +#define ATIM_ISR_UIF_Pos (0UL) /*!< UIF (Bit 0) */ +#define ATIM_ISR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */ +/* ========================================================== EGR ========================================================== */ +#define ATIM_EGR_CC6G_Pos (17UL) /*!< CC6G (Bit 17) */ +#define ATIM_EGR_CC6G_Msk (0x20000UL) /*!< CC6G (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_CC5G_Pos (16UL) /*!< CC5G (Bit 16) */ +#define ATIM_EGR_CC5G_Msk (0x10000UL) /*!< CC5G (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_B2G_Pos (8UL) /*!< B2G (Bit 8) */ +#define ATIM_EGR_B2G_Msk (0x100UL) /*!< B2G (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_BG_Pos (7UL) /*!< BG (Bit 7) */ +#define ATIM_EGR_BG_Msk (0x80UL) /*!< BG (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_TG_Pos (6UL) /*!< TG (Bit 6) */ +#define ATIM_EGR_TG_Msk (0x40UL) /*!< TG (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_COMG_Pos (5UL) /*!< COMG (Bit 5) */ +#define ATIM_EGR_COMG_Msk (0x20UL) /*!< COMG (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_CC4G_Pos (4UL) /*!< CC4G (Bit 4) */ +#define ATIM_EGR_CC4G_Msk (0x10UL) /*!< CC4G (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_CC3G_Pos (3UL) /*!< CC3G (Bit 3) */ +#define ATIM_EGR_CC3G_Msk (0x8UL) /*!< CC3G (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_CC2G_Pos (2UL) /*!< CC2G (Bit 2) */ +#define ATIM_EGR_CC2G_Msk (0x4UL) /*!< CC2G (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_CC1G_Pos (1UL) /*!< CC1G (Bit 1) */ +#define ATIM_EGR_CC1G_Msk (0x2UL) /*!< CC1G (Bitfield-Mask: 0x01) */ +#define ATIM_EGR_UG_Pos (0UL) /*!< UG (Bit 0) */ +#define ATIM_EGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */ +/* ======================================================= CCMR1CAP ======================================================== */ +#define ATIM_CCMR1CAP_IC2F_Pos (12UL) /*!< IC2F (Bit 12) */ +#define ATIM_CCMR1CAP_IC2F_Msk (0xf000UL) /*!< IC2F (Bitfield-Mask: 0x0f) */ +#define ATIM_CCMR1CAP_IC2PSC_Pos (10UL) /*!< IC2PSC (Bit 10) */ +#define ATIM_CCMR1CAP_IC2PSC_Msk (0xc00UL) /*!< IC2PSC (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR1CAP_CC2S_Pos (8UL) /*!< CC2S (Bit 8) */ +#define ATIM_CCMR1CAP_CC2S_Msk (0x300UL) /*!< CC2S (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR1CAP_IC1F_Pos (4UL) /*!< IC1F (Bit 4) */ +#define ATIM_CCMR1CAP_IC1F_Msk (0xf0UL) /*!< IC1F (Bitfield-Mask: 0x0f) */ +#define ATIM_CCMR1CAP_IC1PSC_Pos (2UL) /*!< IC1PSC (Bit 2) */ +#define ATIM_CCMR1CAP_IC1PSC_Msk (0xcUL) /*!< IC1PSC (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR1CAP_CC1S_Pos (0UL) /*!< CC1S (Bit 0) */ +#define ATIM_CCMR1CAP_CC1S_Msk (0x3UL) /*!< CC1S (Bitfield-Mask: 0x03) */ +/* ======================================================= CCMR1CMP ======================================================== */ +#define ATIM_CCMR1CMP_OC2MH_Pos (24UL) /*!< OC2MH (Bit 24) */ +#define ATIM_CCMR1CMP_OC2MH_Msk (0x1000000UL) /*!< OC2MH (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR1CMP_OC1MH_Pos (16UL) /*!< OC1MH (Bit 16) */ +#define ATIM_CCMR1CMP_OC1MH_Msk (0x10000UL) /*!< OC1MH (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR1CMP_OC2CE_Pos (15UL) /*!< OC2CE (Bit 15) */ +#define ATIM_CCMR1CMP_OC2CE_Msk (0x8000UL) /*!< OC2CE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR1CMP_OC2M_Pos (12UL) /*!< OC2M (Bit 12) */ +#define ATIM_CCMR1CMP_OC2M_Msk (0x7000UL) /*!< OC2M (Bitfield-Mask: 0x07) */ +#define ATIM_CCMR1CMP_OC2PE_Pos (11UL) /*!< OC2PE (Bit 11) */ +#define ATIM_CCMR1CMP_OC2PE_Msk (0x800UL) /*!< OC2PE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR1CMP_OC2FE_Pos (10UL) /*!< OC2FE (Bit 10) */ +#define ATIM_CCMR1CMP_OC2FE_Msk (0x400UL) /*!< OC2FE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR1CMP_CC2S_Pos (8UL) /*!< CC2S (Bit 8) */ +#define ATIM_CCMR1CMP_CC2S_Msk (0x300UL) /*!< CC2S (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR1CMP_OC1CE_Pos (7UL) /*!< OC1CE (Bit 7) */ +#define ATIM_CCMR1CMP_OC1CE_Msk (0x80UL) /*!< OC1CE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR1CMP_OC1M_Pos (4UL) /*!< OC1M (Bit 4) */ +#define ATIM_CCMR1CMP_OC1M_Msk (0x70UL) /*!< OC1M (Bitfield-Mask: 0x07) */ +#define ATIM_CCMR1CMP_OC1PE_Pos (3UL) /*!< OC1PE (Bit 3) */ +#define ATIM_CCMR1CMP_OC1PE_Msk (0x8UL) /*!< OC1PE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR1CMP_OC1FE_Pos (2UL) /*!< OC1FE (Bit 2) */ +#define ATIM_CCMR1CMP_OC1FE_Msk (0x4UL) /*!< OC1FE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR1CMP_CC1S_Pos (0UL) /*!< CC1S (Bit 0) */ +#define ATIM_CCMR1CMP_CC1S_Msk (0x3UL) /*!< CC1S (Bitfield-Mask: 0x03) */ +/* ======================================================= CCMR2CAP ======================================================== */ +#define ATIM_CCMR2CAP_IC4F_Pos (12UL) /*!< IC4F (Bit 12) */ +#define ATIM_CCMR2CAP_IC4F_Msk (0xf000UL) /*!< IC4F (Bitfield-Mask: 0x0f) */ +#define ATIM_CCMR2CAP_IC4PSC_Pos (10UL) /*!< IC4PSC (Bit 10) */ +#define ATIM_CCMR2CAP_IC4PSC_Msk (0xc00UL) /*!< IC4PSC (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR2CAP_CC4S_Pos (8UL) /*!< CC4S (Bit 8) */ +#define ATIM_CCMR2CAP_CC4S_Msk (0x300UL) /*!< CC4S (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR2CAP_IC3F_Pos (4UL) /*!< IC3F (Bit 4) */ +#define ATIM_CCMR2CAP_IC3F_Msk (0xf0UL) /*!< IC3F (Bitfield-Mask: 0x0f) */ +#define ATIM_CCMR2CAP_IC3PSC_Pos (2UL) /*!< IC3PSC (Bit 2) */ +#define ATIM_CCMR2CAP_IC3PSC_Msk (0xcUL) /*!< IC3PSC (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR2CAP_CC3S_Pos (0UL) /*!< CC3S (Bit 0) */ +#define ATIM_CCMR2CAP_CC3S_Msk (0x3UL) /*!< CC3S (Bitfield-Mask: 0x03) */ +/* ======================================================= CCMR2CMP ======================================================== */ +#define ATIM_CCMR2CMP_OC4MH_Pos (24UL) /*!< OC4MH (Bit 24) */ +#define ATIM_CCMR2CMP_OC4MH_Msk (0x1000000UL) /*!< OC4MH (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR2CMP_OC3MH_Pos (16UL) /*!< OC3MH (Bit 16) */ +#define ATIM_CCMR2CMP_OC3MH_Msk (0x10000UL) /*!< OC3MH (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR2CMP_OC4CE_Pos (15UL) /*!< OC4CE (Bit 15) */ +#define ATIM_CCMR2CMP_OC4CE_Msk (0x8000UL) /*!< OC4CE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR2CMP_OC4M_Pos (12UL) /*!< OC4M (Bit 12) */ +#define ATIM_CCMR2CMP_OC4M_Msk (0x7000UL) /*!< OC4M (Bitfield-Mask: 0x07) */ +#define ATIM_CCMR2CMP_OC4PE_Pos (11UL) /*!< OC4PE (Bit 11) */ +#define ATIM_CCMR2CMP_OC4PE_Msk (0x800UL) /*!< OC4PE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR2CMP_OC4FE_Pos (10UL) /*!< OC4FE (Bit 10) */ +#define ATIM_CCMR2CMP_OC4FE_Msk (0x400UL) /*!< OC4FE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR2CMP_CC4S_Pos (8UL) /*!< CC4S (Bit 8) */ +#define ATIM_CCMR2CMP_CC4S_Msk (0x300UL) /*!< CC4S (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR2CMP_OC3CE_Pos (7UL) /*!< OC3CE (Bit 7) */ +#define ATIM_CCMR2CMP_OC3CE_Msk (0x80UL) /*!< OC3CE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR2CMP_OC3M_Pos (4UL) /*!< OC3M (Bit 4) */ +#define ATIM_CCMR2CMP_OC3M_Msk (0x70UL) /*!< OC3M (Bitfield-Mask: 0x07) */ +#define ATIM_CCMR2CMP_OC3PE_Pos (3UL) /*!< OC3PE (Bit 3) */ +#define ATIM_CCMR2CMP_OC3PE_Msk (0x8UL) /*!< OC3PE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR2CMP_OC3FE_Pos (2UL) /*!< OC3FE (Bit 2) */ +#define ATIM_CCMR2CMP_OC3FE_Msk (0x4UL) /*!< OC3FE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR2CMP_CC3S_Pos (0UL) /*!< CC3S (Bit 0) */ +#define ATIM_CCMR2CMP_CC3S_Msk (0x3UL) /*!< CC3S (Bitfield-Mask: 0x03) */ +/* ======================================================= CCMR3CAP ======================================================== */ +#define ATIM_CCMR3CAP_IC6F_Pos (12UL) /*!< IC6F (Bit 12) */ +#define ATIM_CCMR3CAP_IC6F_Msk (0xf000UL) /*!< IC6F (Bitfield-Mask: 0x0f) */ +#define ATIM_CCMR3CAP_IC6PSC_Pos (10UL) /*!< IC6PSC (Bit 10) */ +#define ATIM_CCMR3CAP_IC6PSC_Msk (0xc00UL) /*!< IC6PSC (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR3CAP_CC6S_Pos (8UL) /*!< CC6S (Bit 8) */ +#define ATIM_CCMR3CAP_CC6S_Msk (0x300UL) /*!< CC6S (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR3CAP_IC5F_Pos (4UL) /*!< IC5F (Bit 4) */ +#define ATIM_CCMR3CAP_IC5F_Msk (0xf0UL) /*!< IC5F (Bitfield-Mask: 0x0f) */ +#define ATIM_CCMR3CAP_IC5PSC_Pos (2UL) /*!< IC5PSC (Bit 2) */ +#define ATIM_CCMR3CAP_IC5PSC_Msk (0xcUL) /*!< IC5PSC (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR3CAP_CC5S_Pos (0UL) /*!< CC5S (Bit 0) */ +#define ATIM_CCMR3CAP_CC5S_Msk (0x3UL) /*!< CC5S (Bitfield-Mask: 0x03) */ +/* ======================================================= CCMR3CMP ======================================================== */ +#define ATIM_CCMR3CMP_OC6MH_Pos (24UL) /*!< OC6MH (Bit 24) */ +#define ATIM_CCMR3CMP_OC6MH_Msk (0x1000000UL) /*!< OC6MH (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR3CMP_OC5MH_Pos (16UL) /*!< OC5MH (Bit 16) */ +#define ATIM_CCMR3CMP_OC5MH_Msk (0x10000UL) /*!< OC5MH (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR3CMP_OC6CE_Pos (15UL) /*!< OC6CE (Bit 15) */ +#define ATIM_CCMR3CMP_OC6CE_Msk (0x8000UL) /*!< OC6CE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR3CMP_OC6M_Pos (12UL) /*!< OC6M (Bit 12) */ +#define ATIM_CCMR3CMP_OC6M_Msk (0x7000UL) /*!< OC6M (Bitfield-Mask: 0x07) */ +#define ATIM_CCMR3CMP_OC6PE_Pos (11UL) /*!< OC6PE (Bit 11) */ +#define ATIM_CCMR3CMP_OC6PE_Msk (0x800UL) /*!< OC6PE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR3CMP_OC6FE_Pos (10UL) /*!< OC6FE (Bit 10) */ +#define ATIM_CCMR3CMP_OC6FE_Msk (0x400UL) /*!< OC6FE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR3CMP_CC6S_Pos (8UL) /*!< CC6S (Bit 8) */ +#define ATIM_CCMR3CMP_CC6S_Msk (0x300UL) /*!< CC6S (Bitfield-Mask: 0x03) */ +#define ATIM_CCMR3CMP_OC5CE_Pos (7UL) /*!< OC5CE (Bit 7) */ +#define ATIM_CCMR3CMP_OC5CE_Msk (0x80UL) /*!< OC5CE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR3CMP_OC5M_Pos (4UL) /*!< OC5M (Bit 4) */ +#define ATIM_CCMR3CMP_OC5M_Msk (0x70UL) /*!< OC5M (Bitfield-Mask: 0x07) */ +#define ATIM_CCMR3CMP_OC5PE_Pos (3UL) /*!< OC5PE (Bit 3) */ +#define ATIM_CCMR3CMP_OC5PE_Msk (0x8UL) /*!< OC5PE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR3CMP_OC5FE_Pos (2UL) /*!< OC5FE (Bit 2) */ +#define ATIM_CCMR3CMP_OC5FE_Msk (0x4UL) /*!< OC5FE (Bitfield-Mask: 0x01) */ +#define ATIM_CCMR3CMP_CC5S_Pos (0UL) /*!< CC5S (Bit 0) */ +#define ATIM_CCMR3CMP_CC5S_Msk (0x3UL) /*!< CC5S (Bitfield-Mask: 0x03) */ +/* ========================================================= CCER ========================================================== */ +#define ATIM_CCER_CC6NP_Pos (23UL) /*!< CC6NP (Bit 23) */ +#define ATIM_CCER_CC6NP_Msk (0x800000UL) /*!< CC6NP (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC6NE_Pos (22UL) /*!< CC6NE (Bit 22) */ +#define ATIM_CCER_CC6NE_Msk (0x400000UL) /*!< CC6NE (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC6P_Pos (21UL) /*!< CC6P (Bit 21) */ +#define ATIM_CCER_CC6P_Msk (0x200000UL) /*!< CC6P (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC6E_Pos (20UL) /*!< CC6E (Bit 20) */ +#define ATIM_CCER_CC6E_Msk (0x100000UL) /*!< CC6E (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC5NP_Pos (19UL) /*!< CC5NP (Bit 19) */ +#define ATIM_CCER_CC5NP_Msk (0x80000UL) /*!< CC5NP (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC5NE_Pos (18UL) /*!< CC5NE (Bit 18) */ +#define ATIM_CCER_CC5NE_Msk (0x40000UL) /*!< CC5NE (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC5P_Pos (17UL) /*!< CC5P (Bit 17) */ +#define ATIM_CCER_CC5P_Msk (0x20000UL) /*!< CC5P (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC5E_Pos (16UL) /*!< CC5E (Bit 16) */ +#define ATIM_CCER_CC5E_Msk (0x10000UL) /*!< CC5E (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC4NP_Pos (15UL) /*!< CC4NP (Bit 15) */ +#define ATIM_CCER_CC4NP_Msk (0x8000UL) /*!< CC4NP (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC4NE_Pos (14UL) /*!< CC4NE (Bit 14) */ +#define ATIM_CCER_CC4NE_Msk (0x4000UL) /*!< CC4NE (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC4P_Pos (13UL) /*!< CC4P (Bit 13) */ +#define ATIM_CCER_CC4P_Msk (0x2000UL) /*!< CC4P (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC4E_Pos (12UL) /*!< CC4E (Bit 12) */ +#define ATIM_CCER_CC4E_Msk (0x1000UL) /*!< CC4E (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC3NP_Pos (11UL) /*!< CC3NP (Bit 11) */ +#define ATIM_CCER_CC3NP_Msk (0x800UL) /*!< CC3NP (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC3NE_Pos (10UL) /*!< CC3NE (Bit 10) */ +#define ATIM_CCER_CC3NE_Msk (0x400UL) /*!< CC3NE (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC3P_Pos (9UL) /*!< CC3P (Bit 9) */ +#define ATIM_CCER_CC3P_Msk (0x200UL) /*!< CC3P (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC3E_Pos (8UL) /*!< CC3E (Bit 8) */ +#define ATIM_CCER_CC3E_Msk (0x100UL) /*!< CC3E (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC2NP_Pos (7UL) /*!< CC2NP (Bit 7) */ +#define ATIM_CCER_CC2NP_Msk (0x80UL) /*!< CC2NP (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC2NE_Pos (6UL) /*!< CC2NE (Bit 6) */ +#define ATIM_CCER_CC2NE_Msk (0x40UL) /*!< CC2NE (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC2P_Pos (5UL) /*!< CC2P (Bit 5) */ +#define ATIM_CCER_CC2P_Msk (0x20UL) /*!< CC2P (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC2E_Pos (4UL) /*!< CC2E (Bit 4) */ +#define ATIM_CCER_CC2E_Msk (0x10UL) /*!< CC2E (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC1NP_Pos (3UL) /*!< CC1NP (Bit 3) */ +#define ATIM_CCER_CC1NP_Msk (0x8UL) /*!< CC1NP (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC1NE_Pos (2UL) /*!< CC1NE (Bit 2) */ +#define ATIM_CCER_CC1NE_Msk (0x4UL) /*!< CC1NE (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC1P_Pos (1UL) /*!< CC1P (Bit 1) */ +#define ATIM_CCER_CC1P_Msk (0x2UL) /*!< CC1P (Bitfield-Mask: 0x01) */ +#define ATIM_CCER_CC1E_Pos (0UL) /*!< CC1E (Bit 0) */ +#define ATIM_CCER_CC1E_Msk (0x1UL) /*!< CC1E (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +#define ATIM_CNT_UIFCPY_Pos (31UL) /*!< UIFCPY (Bit 31) */ +#define ATIM_CNT_UIFCPY_Msk (0x80000000UL) /*!< UIFCPY (Bitfield-Mask: 0x01) */ +#define ATIM_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define ATIM_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== PSC ========================================================== */ +#define ATIM_PSC_PSC_Pos (0UL) /*!< PSC (Bit 0) */ +#define ATIM_PSC_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */ +/* ========================================================== ARR ========================================================== */ +#define ATIM_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define ATIM_ARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ========================================================== RCR ========================================================== */ +#define ATIM_RCR_REP_Pos (0UL) /*!< REP (Bit 0) */ +#define ATIM_RCR_REP_Msk (0xffffUL) /*!< REP (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR1 ========================================================== */ +#define ATIM_CCR1_CCR1_Pos (0UL) /*!< CCR1 (Bit 0) */ +#define ATIM_CCR1_CCR1_Msk (0xffffUL) /*!< CCR1 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR2 ========================================================== */ +#define ATIM_CCR2_CCR2_Pos (0UL) /*!< CCR2 (Bit 0) */ +#define ATIM_CCR2_CCR2_Msk (0xffffUL) /*!< CCR2 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR3 ========================================================== */ +#define ATIM_CCR3_CCR3_Pos (0UL) /*!< CCR3 (Bit 0) */ +#define ATIM_CCR3_CCR3_Msk (0xffffUL) /*!< CCR3 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR4 ========================================================== */ +#define ATIM_CCR4_CCR4_Pos (0UL) /*!< CCR4 (Bit 0) */ +#define ATIM_CCR4_CCR4_Msk (0xffffUL) /*!< CCR4 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR5 ========================================================== */ +#define ATIM_CCR5_GC5C6_Pos (31UL) /*!< GC5C6 (Bit 31) */ +#define ATIM_CCR5_GC5C6_Msk (0x80000000UL) /*!< GC5C6 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR5_GC5C5_Pos (30UL) /*!< GC5C5 (Bit 30) */ +#define ATIM_CCR5_GC5C5_Msk (0x40000000UL) /*!< GC5C5 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR5_GC5C4_Pos (29UL) /*!< GC5C4 (Bit 29) */ +#define ATIM_CCR5_GC5C4_Msk (0x20000000UL) /*!< GC5C4 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR5_GC5C3_Pos (28UL) /*!< GC5C3 (Bit 28) */ +#define ATIM_CCR5_GC5C3_Msk (0x10000000UL) /*!< GC5C3 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR5_GC5C2_Pos (27UL) /*!< GC5C2 (Bit 27) */ +#define ATIM_CCR5_GC5C2_Msk (0x8000000UL) /*!< GC5C2 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR5_GC5C1_Pos (26UL) /*!< GC5C1 (Bit 26) */ +#define ATIM_CCR5_GC5C1_Msk (0x4000000UL) /*!< GC5C1 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR5_CCR5_Pos (0UL) /*!< CCR5 (Bit 0) */ +#define ATIM_CCR5_CCR5_Msk (0xffffUL) /*!< CCR5 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR6 ========================================================== */ +#define ATIM_CCR6_GC6C6_Pos (31UL) /*!< GC6C6 (Bit 31) */ +#define ATIM_CCR6_GC6C6_Msk (0x80000000UL) /*!< GC6C6 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR6_GC6C5_Pos (30UL) /*!< GC6C5 (Bit 30) */ +#define ATIM_CCR6_GC6C5_Msk (0x40000000UL) /*!< GC6C5 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR6_GC6C4_Pos (29UL) /*!< GC6C4 (Bit 29) */ +#define ATIM_CCR6_GC6C4_Msk (0x20000000UL) /*!< GC6C4 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR6_GC6C3_Pos (28UL) /*!< GC6C3 (Bit 28) */ +#define ATIM_CCR6_GC6C3_Msk (0x10000000UL) /*!< GC6C3 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR6_GC6C2_Pos (27UL) /*!< GC6C2 (Bit 27) */ +#define ATIM_CCR6_GC6C2_Msk (0x8000000UL) /*!< GC6C2 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR6_GC6C1_Pos (26UL) /*!< GC6C1 (Bit 26) */ +#define ATIM_CCR6_GC6C1_Msk (0x4000000UL) /*!< GC6C1 (Bitfield-Mask: 0x01) */ +#define ATIM_CCR6_CCR6_Pos (0UL) /*!< CCR6 (Bit 0) */ +#define ATIM_CCR6_CCR6_Msk (0xffffUL) /*!< CCR6 (Bitfield-Mask: 0xffff) */ +/* ========================================================= BDTR ========================================================== */ +#define ATIM_BDTR_BK2P_Pos (25UL) /*!< BK2P (Bit 25) */ +#define ATIM_BDTR_BK2P_Msk (0x2000000UL) /*!< BK2P (Bitfield-Mask: 0x01) */ +#define ATIM_BDTR_BK2E_Pos (24UL) /*!< BK2E (Bit 24) */ +#define ATIM_BDTR_BK2E_Msk (0x1000000UL) /*!< BK2E (Bitfield-Mask: 0x01) */ +#define ATIM_BDTR_BK2F_Pos (20UL) /*!< BK2F (Bit 20) */ +#define ATIM_BDTR_BK2F_Msk (0xf00000UL) /*!< BK2F (Bitfield-Mask: 0x0f) */ +#define ATIM_BDTR_BKF_Pos (16UL) /*!< BKF (Bit 16) */ +#define ATIM_BDTR_BKF_Msk (0xf0000UL) /*!< BKF (Bitfield-Mask: 0x0f) */ +#define ATIM_BDTR_MOE_Pos (15UL) /*!< MOE (Bit 15) */ +#define ATIM_BDTR_MOE_Msk (0x8000UL) /*!< MOE (Bitfield-Mask: 0x01) */ +#define ATIM_BDTR_AOE_Pos (14UL) /*!< AOE (Bit 14) */ +#define ATIM_BDTR_AOE_Msk (0x4000UL) /*!< AOE (Bitfield-Mask: 0x01) */ +#define ATIM_BDTR_BKP_Pos (13UL) /*!< BKP (Bit 13) */ +#define ATIM_BDTR_BKP_Msk (0x2000UL) /*!< BKP (Bitfield-Mask: 0x01) */ +#define ATIM_BDTR_BKE_Pos (12UL) /*!< BKE (Bit 12) */ +#define ATIM_BDTR_BKE_Msk (0x1000UL) /*!< BKE (Bitfield-Mask: 0x01) */ +#define ATIM_BDTR_OSSR_Pos (11UL) /*!< OSSR (Bit 11) */ +#define ATIM_BDTR_OSSR_Msk (0x800UL) /*!< OSSR (Bitfield-Mask: 0x01) */ +#define ATIM_BDTR_OSSI_Pos (10UL) /*!< OSSI (Bit 10) */ +#define ATIM_BDTR_OSSI_Msk (0x400UL) /*!< OSSI (Bitfield-Mask: 0x01) */ +#define ATIM_BDTR_LOCK_Pos (8UL) /*!< LOCK (Bit 8) */ +#define ATIM_BDTR_LOCK_Msk (0x300UL) /*!< LOCK (Bitfield-Mask: 0x03) */ +#define ATIM_BDTR_DTG_Pos (0UL) /*!< DTG (Bit 0) */ +#define ATIM_BDTR_DTG_Msk (0xffUL) /*!< DTG (Bitfield-Mask: 0xff) */ +/* ========================================================= DTR2 ========================================================== */ +#define ATIM_DTR2_DTPE_Pos (17UL) /*!< DTPE (Bit 17) */ +#define ATIM_DTR2_DTPE_Msk (0x20000UL) /*!< DTPE (Bitfield-Mask: 0x01) */ +#define ATIM_DTR2_DTAE_Pos (16UL) /*!< DTAE (Bit 16) */ +#define ATIM_DTR2_DTAE_Msk (0x10000UL) /*!< DTAE (Bitfield-Mask: 0x01) */ +#define ATIM_DTR2_DTGF_Pos (0UL) /*!< DTGF (Bit 0) */ +#define ATIM_DTR2_DTGF_Msk (0xffUL) /*!< DTGF (Bitfield-Mask: 0xff) */ +/* ========================================================== ECR ========================================================== */ +#define ATIM_ECR_IPOS_Pos (6UL) /*!< IPOS (Bit 6) */ +#define ATIM_ECR_IPOS_Msk (0xc0UL) /*!< IPOS (Bitfield-Mask: 0x03) */ +#define ATIM_ECR_FIDX_Pos (5UL) /*!< FIDX (Bit 5) */ +#define ATIM_ECR_FIDX_Msk (0x20UL) /*!< FIDX (Bitfield-Mask: 0x01) */ +#define ATIM_ECR_IDIR_Pos (1UL) /*!< IDIR (Bit 1) */ +#define ATIM_ECR_IDIR_Msk (0x6UL) /*!< IDIR (Bitfield-Mask: 0x03) */ +#define ATIM_ECR_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ATIM_ECR_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ======================================================== TISEL1 ========================================================= */ +#define ATIM_TISEL1_TI4SEL_Pos (24UL) /*!< TI4SEL (Bit 24) */ +#define ATIM_TISEL1_TI4SEL_Msk (0xf000000UL) /*!< TI4SEL (Bitfield-Mask: 0x0f) */ +#define ATIM_TISEL1_TI3SEL_Pos (16UL) /*!< TI3SEL (Bit 16) */ +#define ATIM_TISEL1_TI3SEL_Msk (0xf0000UL) /*!< TI3SEL (Bitfield-Mask: 0x0f) */ +#define ATIM_TISEL1_TI2SEL_Pos (8UL) /*!< TI2SEL (Bit 8) */ +#define ATIM_TISEL1_TI2SEL_Msk (0xf00UL) /*!< TI2SEL (Bitfield-Mask: 0x0f) */ +#define ATIM_TISEL1_TI1SEL_Pos (0UL) /*!< TI1SEL (Bit 0) */ +#define ATIM_TISEL1_TI1SEL_Msk (0xfUL) /*!< TI1SEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== TISEL2 ========================================================= */ +#define ATIM_TISEL2_TI6SEL_Pos (8UL) /*!< TI6SEL (Bit 8) */ +#define ATIM_TISEL2_TI6SEL_Msk (0xf00UL) /*!< TI6SEL (Bitfield-Mask: 0x0f) */ +#define ATIM_TISEL2_TI5SEL_Pos (0UL) /*!< TI5SEL (Bit 0) */ +#define ATIM_TISEL2_TI5SEL_Msk (0xfUL) /*!< TI5SEL (Bitfield-Mask: 0x0f) */ +/* ========================================================== AF1 ========================================================== */ +#define ATIM_AF1_ETRSEL_Pos (16UL) /*!< ETRSEL (Bit 16) */ +#define ATIM_AF1_ETRSEL_Msk (0xf0000UL) /*!< ETRSEL (Bitfield-Mask: 0x0f) */ +#define ATIM_AF1_BKVC4P_Pos (13UL) /*!< BKVC4P (Bit 13) */ +#define ATIM_AF1_BKVC4P_Msk (0x2000UL) /*!< BKVC4P (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKVC3P_Pos (12UL) /*!< BKVC3P (Bit 12) */ +#define ATIM_AF1_BKVC3P_Msk (0x1000UL) /*!< BKVC3P (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKVC2P_Pos (11UL) /*!< BKVC2P (Bit 11) */ +#define ATIM_AF1_BKVC2P_Msk (0x800UL) /*!< BKVC2P (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKVC1P_Pos (10UL) /*!< BKVC1P (Bit 10) */ +#define ATIM_AF1_BKVC1P_Msk (0x400UL) /*!< BKVC1P (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKINP_Pos (9UL) /*!< BKINP (Bit 9) */ +#define ATIM_AF1_BKINP_Msk (0x200UL) /*!< BKINP (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKVC4E_Pos (4UL) /*!< BKVC4E (Bit 4) */ +#define ATIM_AF1_BKVC4E_Msk (0x10UL) /*!< BKVC4E (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKVC3E_Pos (3UL) /*!< BKVC3E (Bit 3) */ +#define ATIM_AF1_BKVC3E_Msk (0x8UL) /*!< BKVC3E (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKVC2E_Pos (2UL) /*!< BKVC2E (Bit 2) */ +#define ATIM_AF1_BKVC2E_Msk (0x4UL) /*!< BKVC2E (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKVC1E_Pos (1UL) /*!< BKVC1E (Bit 1) */ +#define ATIM_AF1_BKVC1E_Msk (0x2UL) /*!< BKVC1E (Bitfield-Mask: 0x01) */ +#define ATIM_AF1_BKINE_Pos (0UL) /*!< BKINE (Bit 0) */ +#define ATIM_AF1_BKINE_Msk (0x1UL) /*!< BKINE (Bitfield-Mask: 0x01) */ +/* ========================================================== AF2 ========================================================== */ +#define ATIM_AF2_OCRSEL_Pos (16UL) /*!< OCRSEL (Bit 16) */ +#define ATIM_AF2_OCRSEL_Msk (0xf0000UL) /*!< OCRSEL (Bitfield-Mask: 0x0f) */ +#define ATIM_AF2_BK2VC4P_Pos (13UL) /*!< BK2VC4P (Bit 13) */ +#define ATIM_AF2_BK2VC4P_Msk (0x2000UL) /*!< BK2VC4P (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2VC3P_Pos (12UL) /*!< BK2VC3P (Bit 12) */ +#define ATIM_AF2_BK2VC3P_Msk (0x1000UL) /*!< BK2VC3P (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2VC2P_Pos (11UL) /*!< BK2VC2P (Bit 11) */ +#define ATIM_AF2_BK2VC2P_Msk (0x800UL) /*!< BK2VC2P (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2VC1P_Pos (10UL) /*!< BK2VC1P (Bit 10) */ +#define ATIM_AF2_BK2VC1P_Msk (0x400UL) /*!< BK2VC1P (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2INP_Pos (9UL) /*!< BK2INP (Bit 9) */ +#define ATIM_AF2_BK2INP_Msk (0x200UL) /*!< BK2INP (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2VC4E_Pos (4UL) /*!< BK2VC4E (Bit 4) */ +#define ATIM_AF2_BK2VC4E_Msk (0x10UL) /*!< BK2VC4E (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2VC3E_Pos (3UL) /*!< BK2VC3E (Bit 3) */ +#define ATIM_AF2_BK2VC3E_Msk (0x8UL) /*!< BK2VC3E (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2VC2E_Pos (2UL) /*!< BK2VC2E (Bit 2) */ +#define ATIM_AF2_BK2VC2E_Msk (0x4UL) /*!< BK2VC2E (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2VC1E_Pos (1UL) /*!< BK2VC1E (Bit 1) */ +#define ATIM_AF2_BK2VC1E_Msk (0x2UL) /*!< BK2VC1E (Bitfield-Mask: 0x01) */ +#define ATIM_AF2_BK2INE_Pos (0UL) /*!< BK2INE (Bit 0) */ +#define ATIM_AF2_BK2INE_Msk (0x1UL) /*!< BK2INE (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define ATIM_ICR_TERRF_Pos (23UL) /*!< TERRF (Bit 23) */ +#define ATIM_ICR_TERRF_Msk (0x800000UL) /*!< TERRF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_IERRF_Pos (22UL) /*!< IERRF (Bit 22) */ +#define ATIM_ICR_IERRF_Msk (0x400000UL) /*!< IERRF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_DIRF_Pos (21UL) /*!< DIRF (Bit 21) */ +#define ATIM_ICR_DIRF_Msk (0x200000UL) /*!< DIRF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_IDXF_Pos (20UL) /*!< IDXF (Bit 20) */ +#define ATIM_ICR_IDXF_Msk (0x100000UL) /*!< IDXF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC6OF_Pos (19UL) /*!< CC6OF (Bit 19) */ +#define ATIM_ICR_CC6OF_Msk (0x80000UL) /*!< CC6OF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC5OF_Pos (18UL) /*!< CC5OF (Bit 18) */ +#define ATIM_ICR_CC5OF_Msk (0x40000UL) /*!< CC5OF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC6IF_Pos (17UL) /*!< CC6IF (Bit 17) */ +#define ATIM_ICR_CC6IF_Msk (0x20000UL) /*!< CC6IF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC5IF_Pos (16UL) /*!< CC5IF (Bit 16) */ +#define ATIM_ICR_CC5IF_Msk (0x10000UL) /*!< CC5IF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_SBIF_Pos (13UL) /*!< SBIF (Bit 13) */ +#define ATIM_ICR_SBIF_Msk (0x2000UL) /*!< SBIF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC4OF_Pos (12UL) /*!< CC4OF (Bit 12) */ +#define ATIM_ICR_CC4OF_Msk (0x1000UL) /*!< CC4OF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC3OF_Pos (11UL) /*!< CC3OF (Bit 11) */ +#define ATIM_ICR_CC3OF_Msk (0x800UL) /*!< CC3OF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC2OF_Pos (10UL) /*!< CC2OF (Bit 10) */ +#define ATIM_ICR_CC2OF_Msk (0x400UL) /*!< CC2OF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC1OF_Pos (9UL) /*!< CC1OF (Bit 9) */ +#define ATIM_ICR_CC1OF_Msk (0x200UL) /*!< CC1OF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_B2IF_Pos (8UL) /*!< B2IF (Bit 8) */ +#define ATIM_ICR_B2IF_Msk (0x100UL) /*!< B2IF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_BIF_Pos (7UL) /*!< BIF (Bit 7) */ +#define ATIM_ICR_BIF_Msk (0x80UL) /*!< BIF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_TIF_Pos (6UL) /*!< TIF (Bit 6) */ +#define ATIM_ICR_TIF_Msk (0x40UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_COMIF_Pos (5UL) /*!< COMIF (Bit 5) */ +#define ATIM_ICR_COMIF_Msk (0x20UL) /*!< COMIF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC4IF_Pos (4UL) /*!< CC4IF (Bit 4) */ +#define ATIM_ICR_CC4IF_Msk (0x10UL) /*!< CC4IF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC3IF_Pos (3UL) /*!< CC3IF (Bit 3) */ +#define ATIM_ICR_CC3IF_Msk (0x8UL) /*!< CC3IF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC2IF_Pos (2UL) /*!< CC2IF (Bit 2) */ +#define ATIM_ICR_CC2IF_Msk (0x4UL) /*!< CC2IF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_CC1IF_Pos (1UL) /*!< CC1IF (Bit 1) */ +#define ATIM_ICR_CC1IF_Msk (0x2UL) /*!< CC1IF (Bitfield-Mask: 0x01) */ +#define ATIM_ICR_UIF_Pos (0UL) /*!< UIF (Bit 0) */ +#define ATIM_ICR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ BGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define BGR_CR_TSEN_Pos (1UL) /*!< TSEN (Bit 1) */ +#define BGR_CR_TSEN_Msk (0x2UL) /*!< TSEN (Bitfield-Mask: 0x01) */ +#define BGR_CR_BGREN_Pos (0UL) /*!< BGREN (Bit 0) */ +#define BGR_CR_BGREN_Msk (0x1UL) /*!< BGREN (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ BTIM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define BTIMx_CR1_TOGEN_Pos (15UL) /*!< TOGEN (Bit 15) */ +#define BTIMx_CR1_TOGEN_Msk (0x8000UL) /*!< TOGEN (Bitfield-Mask: 0x01) */ +#define BTIMx_CR1_UIFREMAP_Pos (11UL) /*!< UIFREMAP (Bit 11) */ +#define BTIMx_CR1_UIFREMAP_Msk (0x800UL) /*!< UIFREMAP (Bitfield-Mask: 0x01) */ +#define BTIMx_CR1_ONESHOT_Pos (3UL) /*!< ONESHOT (Bit 3) */ +#define BTIMx_CR1_ONESHOT_Msk (0x8UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ +#define BTIMx_CR1_URS_Pos (2UL) /*!< URS (Bit 2) */ +#define BTIMx_CR1_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */ +#define BTIMx_CR1_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */ +#define BTIMx_CR1_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */ +#define BTIMx_CR1_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define BTIMx_CR1_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define BTIMx_CR2_MMS_Pos (4UL) /*!< MMS (Bit 4) */ +#define BTIMx_CR2_MMS_Msk (0x70UL) /*!< MMS (Bitfield-Mask: 0x07) */ +/* ========================================================= SMCR ========================================================== */ +#define BTIMx_SMCR_TRGIPOL_Pos (17UL) /*!< TRGIPOL (Bit 17) */ +#define BTIMx_SMCR_TRGIPOL_Msk (0x20000UL) /*!< TRGIPOL (Bitfield-Mask: 0x01) */ +#define BTIMx_SMCR_RSTIPOL_Pos (16UL) /*!< RSTIPOL (Bit 16) */ +#define BTIMx_SMCR_RSTIPOL_Msk (0x10000UL) /*!< RSTIPOL (Bitfield-Mask: 0x01) */ +#define BTIMx_SMCR_TRGIFLT_Pos (12UL) /*!< TRGIFLT (Bit 12) */ +#define BTIMx_SMCR_TRGIFLT_Msk (0x7000UL) /*!< TRGIFLT (Bitfield-Mask: 0x07) */ +#define BTIMx_SMCR_MSM_Pos (11UL) /*!< MSM (Bit 11) */ +#define BTIMx_SMCR_MSM_Msk (0x800UL) /*!< MSM (Bitfield-Mask: 0x01) */ +#define BTIMx_SMCR_TRGISRC_Pos (7UL) /*!< TRGISRC (Bit 7) */ +#define BTIMx_SMCR_TRGISRC_Msk (0x780UL) /*!< TRGISRC (Bitfield-Mask: 0x0f) */ +#define BTIMx_SMCR_RSTISRC_Pos (3UL) /*!< RSTISRC (Bit 3) */ +#define BTIMx_SMCR_RSTISRC_Msk (0x78UL) /*!< RSTISRC (Bitfield-Mask: 0x0f) */ +#define BTIMx_SMCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */ +#define BTIMx_SMCR_SMS_Msk (0x7UL) /*!< SMS (Bitfield-Mask: 0x07) */ +/* ========================================================= DIER ========================================================== */ +#define BTIMx_DIER_TDE_Pos (14UL) /*!< TDE (Bit 14) */ +#define BTIMx_DIER_TDE_Msk (0x4000UL) /*!< TDE (Bitfield-Mask: 0x01) */ +#define BTIMx_DIER_UDE_Pos (8UL) /*!< UDE (Bit 8) */ +#define BTIMx_DIER_UDE_Msk (0x100UL) /*!< UDE (Bitfield-Mask: 0x01) */ +#define BTIMx_DIER_TIE_Pos (6UL) /*!< TIE (Bit 6) */ +#define BTIMx_DIER_TIE_Msk (0x40UL) /*!< TIE (Bitfield-Mask: 0x01) */ +#define BTIMx_DIER_UIE_Pos (0UL) /*!< UIE (Bit 0) */ +#define BTIMx_DIER_UIE_Msk (0x1UL) /*!< UIE (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define BTIMx_ISR_TIF_Pos (6UL) /*!< TIF (Bit 6) */ +#define BTIMx_ISR_TIF_Msk (0x40UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define BTIMx_ISR_UIF_Pos (0UL) /*!< UIF (Bit 0) */ +#define BTIMx_ISR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define BTIMx_ICR_TIF_Pos (6UL) /*!< TIF (Bit 6) */ +#define BTIMx_ICR_TIF_Msk (0x40UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define BTIMx_ICR_UIF_Pos (0UL) /*!< UIF (Bit 0) */ +#define BTIMx_ICR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */ +/* ========================================================== EGR ========================================================== */ +#define BTIMx_EGR_TG_Pos (6UL) /*!< TG (Bit 6) */ +#define BTIMx_EGR_TG_Msk (0x40UL) /*!< TG (Bitfield-Mask: 0x01) */ +#define BTIMx_EGR_UG_Pos (0UL) /*!< UG (Bit 0) */ +#define BTIMx_EGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +#define BTIMx_CNT_UIFCPY_Pos (31UL) /*!< UIFCPY (Bit 31) */ +#define BTIMx_CNT_UIFCPY_Msk (0x80000000UL) /*!< UIFCPY (Bitfield-Mask: 0x01) */ +#define BTIMx_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define BTIMx_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== PSC ========================================================== */ +#define BTIMx_PSC_PSC_Pos (0UL) /*!< PSC (Bit 0) */ +#define BTIMx_PSC_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */ +/* ========================================================== ARR ========================================================== */ +#define BTIMx_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define BTIMx_ARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ CORDIC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CSR ========================================================== */ +#define CORDIC_CSR_BUSY_Pos (17UL) /*!< BUSY (Bit 17) */ +#define CORDIC_CSR_BUSY_Msk (0x20000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define CORDIC_CSR_EOC_Pos (16UL) /*!< EOC (Bit 16) */ +#define CORDIC_CSR_EOC_Msk (0x10000UL) /*!< EOC (Bitfield-Mask: 0x01) */ +#define CORDIC_CSR_DMAIDLE_Pos (15UL) /*!< DMAIDLE (Bit 15) */ +#define CORDIC_CSR_DMAIDLE_Msk (0x8000UL) /*!< DMAIDLE (Bitfield-Mask: 0x01) */ +#define CORDIC_CSR_DMAEOC_Pos (14UL) /*!< DMAEOC (Bit 14) */ +#define CORDIC_CSR_DMAEOC_Msk (0x4000UL) /*!< DMAEOC (Bitfield-Mask: 0x01) */ +#define CORDIC_CSR_IE_Pos (13UL) /*!< IE (Bit 13) */ +#define CORDIC_CSR_IE_Msk (0x2000UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define CORDIC_CSR_COMP_Pos (12UL) /*!< COMP (Bit 12) */ +#define CORDIC_CSR_COMP_Msk (0x1000UL) /*!< COMP (Bitfield-Mask: 0x01) */ +#define CORDIC_CSR_ITER_Pos (8UL) /*!< ITER (Bit 8) */ +#define CORDIC_CSR_ITER_Msk (0xf00UL) /*!< ITER (Bitfield-Mask: 0x0f) */ +#define CORDIC_CSR_FORMAT_Pos (7UL) /*!< SIZE (Bit 7) */ +#define CORDIC_CSR_FORMAT_Msk (0x80UL) /*!< SIZE (Bitfield-Mask: 0x01) */ +#define CORDIC_CSR_SCALE_Pos (4UL) /*!< SCALE (Bit 4) */ +#define CORDIC_CSR_SCALE_Msk (0x70UL) /*!< SCALE (Bitfield-Mask: 0x07) */ +#define CORDIC_CSR_FUNC_Pos (0UL) /*!< FUNC (Bit 0) */ +#define CORDIC_CSR_FUNC_Msk (0xfUL) /*!< FUNC (Bitfield-Mask: 0x0f) */ +/* ========================================================== DRX ========================================================== */ +#define CORDIC_X_X_Pos (0UL) /*!< DATA (Bit 0) */ +#define CORDIC_X_X_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== DRY ========================================================== */ +#define CORDIC_Y_Y_Pos (0UL) /*!< DATA (Bit 0) */ +#define CORDIC_Y_Y_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== DRZ ========================================================== */ +#define CORDIC_Z_Z_Pos (0UL) /*!< DATA (Bit 0) */ +#define CORDIC_Z_Z_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ CRC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define CRC_CR_MODE_Pos (0UL) /*!< MODE (Bit 0) */ +#define CRC_CR_MODE_Msk (0xfUL) /*!< MODE (Bitfield-Mask: 0x0f) */ +/* ========================================================== DR =========================================================== */ +#define CRC_DR_DR_Pos (0UL) /*!< DR (Bit 0) */ +#define CRC_DR_DR_Msk (0xffUL) /*!< DR (Bitfield-Mask: 0xff) */ +/* ======================================================== RESULT ========================================================= */ +#define CRC_RESULT_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */ +#define CRC_RESULT_RESULT_Msk (0xffffUL) /*!< RESULT (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define DAC_CR0_DMAUDRIE2_Pos (29UL) /*!< DMAUDRIE2 (Bit 29) */ +#define DAC_CR0_DMAUDRIE2_Msk (0x20000000UL) /*!< DMAUDRIE2 (Bitfield-Mask: 0x01) */ +#define DAC_CR0_DMAEN2_Pos (28UL) /*!< DMAEN2 (Bit 28) */ +#define DAC_CR0_DMAEN2_Msk (0x10000000UL) /*!< DMAEN2 (Bitfield-Mask: 0x01) */ +#define DAC_CR0_MAMP2_Pos (24UL) /*!< MAMP2 (Bit 24) */ +#define DAC_CR0_MAMP2_Msk (0xf000000UL) /*!< MAMP2 (Bitfield-Mask: 0x0f) */ +#define DAC_CR0_WAVE2_Pos (22UL) /*!< WAVE2 (Bit 22) */ +#define DAC_CR0_WAVE2_Msk (0xc00000UL) /*!< WAVE2 (Bitfield-Mask: 0x03) */ +#define DAC_CR0_TSEL2_Pos (18UL) /*!< TSEL2 (Bit 18) */ +#define DAC_CR0_TSEL2_Msk (0x3c0000UL) /*!< TSEL2 (Bitfield-Mask: 0x0f) */ +#define DAC_CR0_TEN2_Pos (17UL) /*!< TEN2 (Bit 17) */ +#define DAC_CR0_TEN2_Msk (0x20000UL) /*!< TEN2 (Bitfield-Mask: 0x01) */ +#define DAC_CR0_EN2_Pos (16UL) /*!< EN2 (Bit 16) */ +#define DAC_CR0_EN2_Msk (0x10000UL) /*!< EN2 (Bitfield-Mask: 0x01) */ +#define DAC_CR0_DMAUDRIE1_Pos (13UL) /*!< DMAUDRIE1 (Bit 13) */ +#define DAC_CR0_DMAUDRIE1_Msk (0x2000UL) /*!< DMAUDRIE1 (Bitfield-Mask: 0x01) */ +#define DAC_CR0_DMAEN1_Pos (12UL) /*!< DMAEN1 (Bit 12) */ +#define DAC_CR0_DMAEN1_Msk (0x1000UL) /*!< DMAEN1 (Bitfield-Mask: 0x01) */ +#define DAC_CR0_MAMP1_Pos (8UL) /*!< MAMP1 (Bit 8) */ +#define DAC_CR0_MAMP1_Msk (0xf00UL) /*!< MAMP1 (Bitfield-Mask: 0x0f) */ +#define DAC_CR0_WAVE1_Pos (6UL) /*!< WAVE1 (Bit 6) */ +#define DAC_CR0_WAVE1_Msk (0xc0UL) /*!< WAVE1 (Bitfield-Mask: 0x03) */ +#define DAC_CR0_TSEL1_Pos (2UL) /*!< TSEL1 (Bit 2) */ +#define DAC_CR0_TSEL1_Msk (0x3cUL) /*!< TSEL1 (Bitfield-Mask: 0x0f) */ +#define DAC_CR0_TEN1_Pos (1UL) /*!< TEN1 (Bit 1) */ +#define DAC_CR0_TEN1_Msk (0x2UL) /*!< TEN1 (Bitfield-Mask: 0x01) */ +#define DAC_CR0_EN1_Pos (0UL) /*!< EN1 (Bit 0) */ +#define DAC_CR0_EN1_Msk (0x1UL) /*!< EN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== SWTRGR ========================================================= */ +#define DAC_SWTRGR_SWTRIG2_Pos (1UL) /*!< SWTRIG2 (Bit 1) */ +#define DAC_SWTRGR_SWTRIG2_Msk (0x2UL) /*!< SWTRIG2 (Bitfield-Mask: 0x01) */ +#define DAC_SWTRGR_SWTRIG1_Pos (0UL) /*!< SWTRIG1 (Bit 0) */ +#define DAC_SWTRGR_SWTRIG1_Msk (0x1UL) /*!< SWTRIG1 (Bitfield-Mask: 0x01) */ +/* ======================================================== DHR12R1 ======================================================== */ +#define DAC_DHR12R1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define DAC_DHR12R1_DATA_Msk (0xfffUL) /*!< DATA (Bitfield-Mask: 0xfff) */ +/* ======================================================== DHR12L1 ======================================================== */ +#define DAC_DHR12L1_DATA_Pos (4UL) /*!< DATA (Bit 4) */ +#define DAC_DHR12L1_DATA_Msk (0xfff0UL) /*!< DATA (Bitfield-Mask: 0xfff) */ +/* ======================================================== DHR8R1 ========================================================= */ +#define DAC_DHR8R1_DATA_Pos (4UL) /*!< DATA (Bit 4) */ +#define DAC_DHR8R1_DATA_Msk (0xf0UL) /*!< DATA (Bitfield-Mask: 0x0f) */ +/* ======================================================== DHR12R2 ======================================================== */ +#define DAC_DHR12R2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define DAC_DHR12R2_DATA_Msk (0xfffUL) /*!< DATA (Bitfield-Mask: 0xfff) */ +/* ======================================================== DHR12L2 ======================================================== */ +#define DAC_DHR12L2_DATA_Pos (4UL) /*!< DATA (Bit 4) */ +#define DAC_DHR12L2_DATA_Msk (0xfff0UL) /*!< DATA (Bitfield-Mask: 0xfff) */ +/* ======================================================== DHR8R2 ========================================================= */ +#define DAC_DHR8R2_DATA_Pos (4UL) /*!< DATA (Bit 4) */ +#define DAC_DHR8R2_DATA_Msk (0xf0UL) /*!< DATA (Bitfield-Mask: 0x0f) */ +/* ======================================================== DHR12RD ======================================================== */ +#define DAC_DHR12RD_C2DATA_Pos (16UL) /*!< C2DATA (Bit 16) */ +#define DAC_DHR12RD_C2DATA_Msk (0xfff0000UL) /*!< C2DATA (Bitfield-Mask: 0xfff) */ +#define DAC_DHR12RD_C1DATA_Pos (0UL) /*!< C1DATA (Bit 0) */ +#define DAC_DHR12RD_C1DATA_Msk (0xfffUL) /*!< C1DATA (Bitfield-Mask: 0xfff) */ +/* ======================================================== DHR12LD ======================================================== */ +#define DAC_DHR12LD_C2DATA_Pos (20UL) /*!< C2DATA (Bit 20) */ +#define DAC_DHR12LD_C2DATA_Msk (0xfff00000UL) /*!< C2DATA (Bitfield-Mask: 0xfff) */ +#define DAC_DHR12LD_C1DATA_Pos (4UL) /*!< C1DATA (Bit 4) */ +#define DAC_DHR12LD_C1DATA_Msk (0xfff0UL) /*!< C1DATA (Bitfield-Mask: 0xfff) */ +/* ======================================================== DHR8RD ========================================================= */ +#define DAC_DHR8RD_C2DATA_Pos (8UL) /*!< C2DATA (Bit 8) */ +#define DAC_DHR8RD_C2DATA_Msk (0xff00UL) /*!< C2DATA (Bitfield-Mask: 0xff) */ +#define DAC_DHR8RD_C1DATA_Pos (0UL) /*!< C1DATA (Bit 0) */ +#define DAC_DHR8RD_C1DATA_Msk (0xffUL) /*!< C1DATA (Bitfield-Mask: 0xff) */ +/* ========================================================= DOR1 ========================================================== */ +#define DAC_DOR1_DMAUDR_Pos (15UL) /*!< DMAUDR (Bit 15) */ +#define DAC_DOR1_DMAUDR_Msk (0x8000UL) /*!< DMAUDR (Bitfield-Mask: 0x01) */ +#define DAC_DOR1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define DAC_DOR1_DATA_Msk (0xfffUL) /*!< DATA (Bitfield-Mask: 0xfff) */ +/* ========================================================= DOR2 ========================================================== */ +#define DAC_DOR2_DMAUDR_Pos (15UL) /*!< DMAUDR (Bit 15) */ +#define DAC_DOR2_DMAUDR_Msk (0x8000UL) /*!< DMAUDR (Bitfield-Mask: 0x01) */ +#define DAC_DOR2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define DAC_DOR2_DATA_Msk (0xfffUL) /*!< DATA (Bitfield-Mask: 0xfff) */ +/* ========================================================== CR1 ========================================================== */ +#define DAC_CR1_C2OUT_Pos (1UL) /*!< C2OUT (Bit 1) */ +#define DAC_CR1_C2OUT_Msk (0x2UL) /*!< C2OUT (Bitfield-Mask: 0x01) */ +#define DAC_CR1_C1OUT_Pos (0UL) /*!< C1OUT (Bit 0) */ +#define DAC_CR1_C1OUT_Msk (0x1UL) /*!< C1OUT (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ISR ========================================================== */ +#define DMA_ISR_TE4_Pos (13UL) /*!< TE4 (Bit 13) */ +#define DMA_ISR_TE4_Msk (0x2000UL) /*!< TE4 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC4_Pos (12UL) /*!< TC4 (Bit 12) */ +#define DMA_ISR_TC4_Msk (0x1000UL) /*!< TC4 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TE3_Pos (9UL) /*!< TE3 (Bit 9) */ +#define DMA_ISR_TE3_Msk (0x200UL) /*!< TE3 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC3_Pos (8UL) /*!< TC3 (Bit 8) */ +#define DMA_ISR_TC3_Msk (0x100UL) /*!< TC3 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TE2_Pos (5UL) /*!< TE2 (Bit 5) */ +#define DMA_ISR_TE2_Msk (0x20UL) /*!< TE2 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC2_Pos (4UL) /*!< TC2 (Bit 4) */ +#define DMA_ISR_TC2_Msk (0x10UL) /*!< TC2 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TE1_Pos (1UL) /*!< TE1 (Bit 1) */ +#define DMA_ISR_TE1_Msk (0x2UL) /*!< TE1 (Bitfield-Mask: 0x01) */ +#define DMA_ISR_TC1_Pos (0UL) /*!< TC1 (Bit 0) */ +#define DMA_ISR_TC1_Msk (0x1UL) /*!< TC1 (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define DMA_ICR_TE4_Pos (13UL) /*!< TE4 (Bit 13) */ +#define DMA_ICR_TE4_Msk (0x2000UL) /*!< TE4 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC4_Pos (12UL) /*!< TC4 (Bit 12) */ +#define DMA_ICR_TC4_Msk (0x1000UL) /*!< TC4 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TE3_Pos (9UL) /*!< TE3 (Bit 9) */ +#define DMA_ICR_TE3_Msk (0x200UL) /*!< TE3 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC3_Pos (8UL) /*!< TC3 (Bit 8) */ +#define DMA_ICR_TC3_Msk (0x100UL) /*!< TC3 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TE2_Pos (5UL) /*!< TE2 (Bit 5) */ +#define DMA_ICR_TE2_Msk (0x20UL) /*!< TE2 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC2_Pos (4UL) /*!< TC2 (Bit 4) */ +#define DMA_ICR_TC2_Msk (0x10UL) /*!< TC2 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TE1_Pos (1UL) /*!< TE1 (Bit 1) */ +#define DMA_ICR_TE1_Msk (0x2UL) /*!< TE1 (Bitfield-Mask: 0x01) */ +#define DMA_ICR_TC1_Pos (0UL) /*!< TC1 (Bit 0) */ +#define DMA_ICR_TC1_Msk (0x1UL) /*!< TC1 (Bitfield-Mask: 0x01) */ +/* ========================================================= CSR1 ========================================================== */ +#define DMA_CSR1_DSTLOAD_Pos (15UL) /*!< DSTLOAD (Bit 15) */ +#define DMA_CSR1_DSTLOAD_Msk (0x8000UL) /*!< DSTLOAD (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_SRCLOAD_Pos (14UL) /*!< SRCLOAD (Bit 14) */ +#define DMA_CSR1_SRCLOAD_Msk (0x4000UL) /*!< SRCLOAD (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_TE_Pos (13UL) /*!< TE (Bit 13) */ +#define DMA_CSR1_TE_Msk (0x2000UL) /*!< TE (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_TC_Pos (12UL) /*!< TC (Bit 12) */ +#define DMA_CSR1_TC_Msk (0x1000UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_RESTART_Pos (11UL) /*!< RESTART (Bit 11) */ +#define DMA_CSR1_RESTART_Msk (0x800UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR1_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR1_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR1_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR1_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR1_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR1_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR1_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR1_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR1_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR1_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR1_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= TRIG1 ========================================================= */ +#define DMA_TRIG1_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG1_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG1_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG1_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG1_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG1_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT1 ========================================================== */ +#define DMA_CNT1_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT1_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT1_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT1_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR1 ======================================================== */ +#define DMA_SRCADDR1_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR1_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR1 ======================================================== */ +#define DMA_DSTADDR1_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR1_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CCNT1 ========================================================= */ +#define DMA_CCNT1_CREPEAT_Pos (16UL) /*!< CREPEAT (Bit 16) */ +#define DMA_CCNT1_CREPEAT_Msk (0xf0000UL) /*!< CREPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CCNT1_CCNT_Pos (0UL) /*!< CCNT (Bit 0) */ +#define DMA_CCNT1_CCNT_Msk (0xffffUL) /*!< CCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CSRCADDR1 ======================================================= */ +#define DMA_CSRCADDR1_CSRCADDR_Pos (0UL) /*!< CSRCADDR (Bit 0) */ +#define DMA_CSRCADDR1_CSRCADDR_Msk (0xffffffffUL) /*!< CSRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDSTADDR1 ======================================================= */ +#define DMA_CDSTADDR1_CDSTADDR_Pos (0UL) /*!< CDSTADDR (Bit 0) */ +#define DMA_CDSTADDR1_CDSTADDR_Msk (0xffffffffUL) /*!< CDSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CSR2 ========================================================== */ +#define DMA_CSR2_DSTLOAD_Pos (15UL) /*!< DSTLOAD (Bit 15) */ +#define DMA_CSR2_DSTLOAD_Msk (0x8000UL) /*!< DSTLOAD (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_SRCLOAD_Pos (14UL) /*!< SRCLOAD (Bit 14) */ +#define DMA_CSR2_SRCLOAD_Msk (0x4000UL) /*!< SRCLOAD (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_TE_Pos (13UL) /*!< TE (Bit 13) */ +#define DMA_CSR2_TE_Msk (0x2000UL) /*!< TE (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_TC_Pos (12UL) /*!< TC (Bit 12) */ +#define DMA_CSR2_TC_Msk (0x1000UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_RESTART_Pos (11UL) /*!< RESTART (Bit 11) */ +#define DMA_CSR2_RESTART_Msk (0x800UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR2_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR2_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR2_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR2_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR2_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR2_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR2_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR2_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR2_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR2_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR2_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT2 ========================================================== */ +#define DMA_CNT2_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT2_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT2_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT2_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR2 ======================================================== */ +#define DMA_SRCADDR2_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR2_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR2 ======================================================== */ +#define DMA_DSTADDR2_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR2_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG2 ========================================================= */ +#define DMA_TRIG2_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG2_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG2_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG2_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG2_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG2_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCNT2 ========================================================= */ +#define DMA_CCNT2_CREPEAT_Pos (16UL) /*!< CREPEAT (Bit 16) */ +#define DMA_CCNT2_CREPEAT_Msk (0xf0000UL) /*!< CREPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CCNT2_CCNT_Pos (0UL) /*!< CCNT (Bit 0) */ +#define DMA_CCNT2_CCNT_Msk (0xffffUL) /*!< CCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CSRCADDR2 ======================================================= */ +#define DMA_CSRCADDR2_CSRCADDR_Pos (0UL) /*!< CSRCADDR (Bit 0) */ +#define DMA_CSRCADDR2_CSRCADDR_Msk (0xffffffffUL) /*!< CSRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDSTADDR2 ======================================================= */ +#define DMA_CDSTADDR2_CDSTADDR_Pos (0UL) /*!< CDSTADDR (Bit 0) */ +#define DMA_CDSTADDR2_CDSTADDR_Msk (0xffffffffUL) /*!< CDSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CSR3 ========================================================== */ +#define DMA_CSR3_DSTLOAD_Pos (15UL) /*!< DSTLOAD (Bit 15) */ +#define DMA_CSR3_DSTLOAD_Msk (0x8000UL) /*!< DSTLOAD (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_SRCLOAD_Pos (14UL) /*!< SRCLOAD (Bit 14) */ +#define DMA_CSR3_SRCLOAD_Msk (0x4000UL) /*!< SRCLOAD (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_TE_Pos (13UL) /*!< TE (Bit 13) */ +#define DMA_CSR3_TE_Msk (0x2000UL) /*!< TE (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_TC_Pos (12UL) /*!< TC (Bit 12) */ +#define DMA_CSR3_TC_Msk (0x1000UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_RESTART_Pos (11UL) /*!< RESTART (Bit 11) */ +#define DMA_CSR3_RESTART_Msk (0x800UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR3_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR3_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR3_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR3_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR3_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR3_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR3_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR3_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR3_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR3_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR3_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT3 ========================================================== */ +#define DMA_CNT3_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT3_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT3_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT3_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR3 ======================================================== */ +#define DMA_SRCADDR3_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR3_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR3 ======================================================== */ +#define DMA_DSTADDR3_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR3_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG3 ========================================================= */ +#define DMA_TRIG3_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG3_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG3_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG3_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG3_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG3_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCNT3 ========================================================= */ +#define DMA_CCNT3_CREPEAT_Pos (16UL) /*!< CREPEAT (Bit 16) */ +#define DMA_CCNT3_CREPEAT_Msk (0xf0000UL) /*!< CREPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CCNT3_CCNT_Pos (0UL) /*!< CCNT (Bit 0) */ +#define DMA_CCNT3_CCNT_Msk (0xffffUL) /*!< CCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CSRCADDR3 ======================================================= */ +#define DMA_CSRCADDR3_CSRCADDR_Pos (0UL) /*!< CSRCADDR (Bit 0) */ +#define DMA_CSRCADDR3_CSRCADDR_Msk (0xffffffffUL) /*!< CSRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDSTADDR3 ======================================================= */ +#define DMA_CDSTADDR3_CDSTADDR_Pos (0UL) /*!< CDSTADDR (Bit 0) */ +#define DMA_CDSTADDR3_CDSTADDR_Msk (0xffffffffUL) /*!< CDSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CSR4 ========================================================== */ +#define DMA_CSR4_DSTLOAD_Pos (15UL) /*!< DSTLOAD (Bit 15) */ +#define DMA_CSR4_DSTLOAD_Msk (0x8000UL) /*!< DSTLOAD (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_SRCLOAD_Pos (14UL) /*!< SRCLOAD (Bit 14) */ +#define DMA_CSR4_SRCLOAD_Msk (0x4000UL) /*!< SRCLOAD (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_TE_Pos (13UL) /*!< TE (Bit 13) */ +#define DMA_CSR4_TE_Msk (0x2000UL) /*!< TE (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_TC_Pos (12UL) /*!< TC (Bit 12) */ +#define DMA_CSR4_TC_Msk (0x1000UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_RESTART_Pos (11UL) /*!< RESTART (Bit 11) */ +#define DMA_CSR4_RESTART_Msk (0x800UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMA_CSR4_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMA_CSR4_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMA_CSR4_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CSR4_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMA_CSR4_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMA_CSR4_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMA_CSR4_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMA_CSR4_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMA_CSR4_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMA_CSR4_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMA_CSR4_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CNT4 ========================================================== */ +#define DMA_CNT4_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMA_CNT4_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CNT4_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA_CNT4_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= SRCADDR4 ======================================================== */ +#define DMA_SRCADDR4_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMA_SRCADDR4_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DSTADDR4 ======================================================== */ +#define DMA_DSTADDR4_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMA_DSTADDR4_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG4 ========================================================= */ +#define DMA_TRIG4_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMA_TRIG4_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMA_TRIG4_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMA_TRIG4_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMA_TRIG4_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMA_TRIG4_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCNT4 ========================================================= */ +#define DMA_CCNT4_CREPEAT_Pos (16UL) /*!< CREPEAT (Bit 16) */ +#define DMA_CCNT4_CREPEAT_Msk (0xf0000UL) /*!< CREPEAT (Bitfield-Mask: 0x0f) */ +#define DMA_CCNT4_CCNT_Pos (0UL) /*!< CCNT (Bit 0) */ +#define DMA_CCNT4_CCNT_Msk (0xffffUL) /*!< CCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CSRCADDR4 ======================================================= */ +#define DMA_CSRCADDR4_CSRCADDR_Pos (0UL) /*!< CSRCADDR (Bit 0) */ +#define DMA_CSRCADDR4_CSRCADDR_Msk (0xffffffffUL) /*!< CSRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDSTADDR4 ======================================================= */ +#define DMA_CDSTADDR4_CDSTADDR_Pos (0UL) /*!< CDSTADDR (Bit 0) */ +#define DMA_CDSTADDR4_CDSTADDR_Msk (0xffffffffUL) /*!< CDSTADDR (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ DMACHANNEL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CSR ========================================================== */ +#define DMACHx_CSR_DSTLOAD_Pos (15UL) /*!< DSTLOAD (Bit 15) */ +#define DMACHx_CSR_DSTLOAD_Msk (0x8000UL) /*!< DSTLOAD (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_SRCLOAD_Pos (14UL) /*!< SRCLOAD (Bit 14) */ +#define DMACHx_CSR_SRCLOAD_Msk (0x4000UL) /*!< SRCLOAD (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_TE_Pos (13UL) /*!< TE (Bit 13) */ +#define DMACHx_CSR_TE_Msk (0x2000UL) /*!< TE (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_TC_Pos (12UL) /*!< TC (Bit 12) */ +#define DMACHx_CSR_TC_Msk (0x1000UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_RESTART_Pos (11UL) /*!< RESTART (Bit 11) */ +#define DMACHx_CSR_RESTART_Msk (0x800UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_STATUS_Pos (8UL) /*!< STATUS (Bit 8) */ +#define DMACHx_CSR_STATUS_Msk (0x700UL) /*!< STATUS (Bitfield-Mask: 0x07) */ +#define DMACHx_CSR_SIZE_Pos (6UL) /*!< SIZE (Bit 6) */ +#define DMACHx_CSR_SIZE_Msk (0xc0UL) /*!< SIZE (Bitfield-Mask: 0x03) */ +#define DMACHx_CSR_DSTINC_Pos (5UL) /*!< DSTINC (Bit 5) */ +#define DMACHx_CSR_DSTINC_Msk (0x20UL) /*!< DSTINC (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_SRCINC_Pos (4UL) /*!< SRCINC (Bit 4) */ +#define DMACHx_CSR_SRCINC_Msk (0x10UL) /*!< SRCINC (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_TRANS_Pos (3UL) /*!< TRANS (Bit 3) */ +#define DMACHx_CSR_TRANS_Msk (0x8UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ +#define DMACHx_CSR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_TCIE_Pos (1UL) /*!< TCIE (Bit 1) */ +#define DMACHx_CSR_TCIE_Msk (0x2UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define DMACHx_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define DMACHx_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +#define DMACHx_CNT_REPEAT_Pos (16UL) /*!< REPEAT (Bit 16) */ +#define DMACHx_CNT_REPEAT_Msk (0xf0000UL) /*!< REPEAT (Bitfield-Mask: 0x0f) */ +#define DMACHx_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMACHx_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================== SRCADDR ======================================================== */ +#define DMACHx_SRCADDR_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define DMACHx_SRCADDR_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DSTADDR ======================================================== */ +#define DMACHx_DSTADDR_DSTADDR_Pos (0UL) /*!< DSTADDR (Bit 0) */ +#define DMACHx_DSTADDR_DSTADDR_Msk (0xffffffffUL) /*!< DSTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TRIG ========================================================== */ +#define DMACHx_TRIG_HARDSRC_Pos (2UL) /*!< HARDSRC (Bit 2) */ +#define DMACHx_TRIG_HARDSRC_Msk (0xfcUL) /*!< HARDSRC (Bitfield-Mask: 0x3f) */ +#define DMACHx_TRIG_SOFTSRC_Pos (1UL) /*!< SOFTSRC (Bit 1) */ +#define DMACHx_TRIG_SOFTSRC_Msk (0x2UL) /*!< SOFTSRC (Bitfield-Mask: 0x01) */ +#define DMACHx_TRIG_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ +#define DMACHx_TRIG_TYPE_Msk (0x1UL) /*!< TYPE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCNT ========================================================== */ +#define DMACHx_CCNT_CREPEAT_Pos (16UL) /*!< CREPEAT (Bit 16) */ +#define DMACHx_CCNT_CREPEAT_Msk (0xf0000UL) /*!< CREPEAT (Bitfield-Mask: 0x0f) */ +#define DMACHx_CCNT_CCNT_Pos (0UL) /*!< CCNT (Bit 0) */ +#define DMACHx_CCNT_CCNT_Msk (0xffffUL) /*!< CCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CSRCADDR ======================================================== */ +#define DMACHx_CSRCADDR_CSRCADDR_Pos (0UL) /*!< CSRCADDR (Bit 0) */ +#define DMACHx_CSRCADDR_CSRCADDR_Msk (0xffffffffUL) /*!< CSRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDSTADDR ======================================================== */ +#define DMACHx_CDSTADDR_CDSTADDR_Pos (0UL) /*!< CDSTADDR (Bit 0) */ +#define DMACHx_CDSTADDR_CDSTADDR_Msk (0xffffffffUL) /*!< CDSTADDR (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ EAU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CSR ========================================================== */ +#define EAU_CSR_BUSY_Pos (4UL) /*!< BUSY (Bit 4) */ +#define EAU_CSR_BUSY_Msk (0x10UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define EAU_CSR_ZERO_Pos (3UL) /*!< ZERO (Bit 3) */ +#define EAU_CSR_ZERO_Msk (0x8UL) /*!< ZERO (Bitfield-Mask: 0x01) */ +#define EAU_CSR_OVR_Pos (2UL) /*!< OVR (Bit 2) */ +#define EAU_CSR_OVR_Msk (0x4UL) /*!< OVR (Bitfield-Mask: 0x01) */ +#define EAU_CSR_MODE_Pos (0UL) /*!< MODE (Bit 0) */ +#define EAU_CSR_MODE_Msk (0x3UL) /*!< MODE (Bitfield-Mask: 0x03) */ +/* ======================================================= DIVIDEND ======================================================== */ +#define EAU_DIVIDEND_DIVIDEND_Pos (0UL) /*!< DIVIDEND (Bit 0) */ +#define EAU_DIVIDEND_DIVIDEND_Msk (0xffffffffUL) /*!< DIVIDEND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DIVISOR ======================================================== */ +#define EAU_DIVISOR_DIVISOR_Pos (0UL) /*!< DIVISOR (Bit 0) */ +#define EAU_DIVISOR_DIVISOR_Msk (0xffffffffUL) /*!< DIVISOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= QUOTIENT ======================================================== */ +#define EAU_QUOTIENT_QUOTIENT_Pos (0UL) /*!< QUOTIENT (Bit 0) */ +#define EAU_QUOTIENT_QUOTIENT_Msk (0xffffffffUL) /*!< QUOTIENT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= REMAINDER ======================================================= */ +#define EAU_REMAINDER_REMAINDER_Pos (0UL) /*!< REMAINDER (Bit 0) */ +#define EAU_REMAINDER_REMAINDER_Msk (0xffffffffUL) /*!< REMAINDER (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ FLASH ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define FLASH_CR1_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define FLASH_CR1_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define FLASH_CR1_SECURITY_Pos (5UL) /*!< SECURITY (Bit 5) */ +#define FLASH_CR1_SECURITY_Msk (0x60UL) /*!< SECURITY (Bitfield-Mask: 0x03) */ +#define FLASH_CR1_MODE_Pos (0UL) /*!< MODE (Bit 0) */ +#define FLASH_CR1_MODE_Msk (0x3UL) /*!< MODE (Bitfield-Mask: 0x03) */ +/* ========================================================== CR2 ========================================================== */ +#define FLASH_CR2_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define FLASH_CR2_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define FLASH_CR2_CACHEINVALID_Pos (5UL) /*!< CACHEINVALID (Bit 5) */ +#define FLASH_CR2_CACHEINVALID_Msk (0x20UL) /*!< CACHEINVALID (Bitfield-Mask: 0x01) */ +#define FLASH_CR2_CACHE_Pos (4UL) /*!< CACHE (Bit 4) */ +#define FLASH_CR2_CACHE_Msk (0x10UL) /*!< CACHE (Bitfield-Mask: 0x01) */ +#define FLASH_CR2_FETCH_Pos (3UL) /*!< FETCH (Bit 3) */ +#define FLASH_CR2_FETCH_Msk (0x8UL) /*!< FETCH (Bitfield-Mask: 0x01) */ +#define FLASH_CR2_WAIT_Pos (0UL) /*!< WAIT (Bit 0) */ +#define FLASH_CR2_WAIT_Msk (0x7UL) /*!< WAIT (Bitfield-Mask: 0x07) */ +/* ======================================================= PAGELOCK ======================================================== */ +#define FLASH_PAGELOCK_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define FLASH_PAGELOCK_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define FLASH_PAGELOCK_LOCK15_Pos (15UL) /*!< LOCK15 (Bit 15) */ +#define FLASH_PAGELOCK_LOCK15_Msk (0x8000UL) /*!< LOCK15 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK14_Pos (14UL) /*!< LOCK14 (Bit 14) */ +#define FLASH_PAGELOCK_LOCK14_Msk (0x4000UL) /*!< LOCK14 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK13_Pos (13UL) /*!< LOCK13 (Bit 13) */ +#define FLASH_PAGELOCK_LOCK13_Msk (0x2000UL) /*!< LOCK13 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK12_Pos (12UL) /*!< LOCK12 (Bit 12) */ +#define FLASH_PAGELOCK_LOCK12_Msk (0x1000UL) /*!< LOCK12 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK11_Pos (11UL) /*!< LOCK11 (Bit 11) */ +#define FLASH_PAGELOCK_LOCK11_Msk (0x800UL) /*!< LOCK11 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK10_Pos (10UL) /*!< LOCK10 (Bit 10) */ +#define FLASH_PAGELOCK_LOCK10_Msk (0x400UL) /*!< LOCK10 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK9_Pos (9UL) /*!< LOCK9 (Bit 9) */ +#define FLASH_PAGELOCK_LOCK9_Msk (0x200UL) /*!< LOCK9 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK8_Pos (8UL) /*!< LOCK8 (Bit 8) */ +#define FLASH_PAGELOCK_LOCK8_Msk (0x100UL) /*!< LOCK8 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK7_Pos (7UL) /*!< LOCK7 (Bit 7) */ +#define FLASH_PAGELOCK_LOCK7_Msk (0x80UL) /*!< LOCK7 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK6_Pos (6UL) /*!< LOCK6 (Bit 6) */ +#define FLASH_PAGELOCK_LOCK6_Msk (0x40UL) /*!< LOCK6 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK5_Pos (5UL) /*!< LOCK5 (Bit 5) */ +#define FLASH_PAGELOCK_LOCK5_Msk (0x20UL) /*!< LOCK5 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK4_Pos (4UL) /*!< LOCK4 (Bit 4) */ +#define FLASH_PAGELOCK_LOCK4_Msk (0x10UL) /*!< LOCK4 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK3_Pos (3UL) /*!< LOCK3 (Bit 3) */ +#define FLASH_PAGELOCK_LOCK3_Msk (0x8UL) /*!< LOCK3 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK2_Pos (2UL) /*!< LOCK2 (Bit 2) */ +#define FLASH_PAGELOCK_LOCK2_Msk (0x4UL) /*!< LOCK2 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK1_Pos (1UL) /*!< LOCK1 (Bit 1) */ +#define FLASH_PAGELOCK_LOCK1_Msk (0x2UL) /*!< LOCK1 (Bitfield-Mask: 0x01) */ +#define FLASH_PAGELOCK_LOCK0_Pos (0UL) /*!< LOCK0 (Bit 0) */ +#define FLASH_PAGELOCK_LOCK0_Msk (0x1UL) /*!< LOCK0 (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define FLASH_IER_PROG_Pos (4UL) /*!< PROG (Bit 4) */ +#define FLASH_IER_PROG_Msk (0x10UL) /*!< PROG (Bitfield-Mask: 0x01) */ +#define FLASH_IER_CACHEON_Pos (3UL) /*!< CACHEON (Bit 3) */ +#define FLASH_IER_CACHEON_Msk (0x8UL) /*!< CACHEON (Bitfield-Mask: 0x01) */ +#define FLASH_IER_SDKERR_Pos (2UL) /*!< SDKERR (Bit 2) */ +#define FLASH_IER_SDKERR_Msk (0x4UL) /*!< SDKERR (Bitfield-Mask: 0x01) */ +#define FLASH_IER_PAGELOCK_Pos (1UL) /*!< PAGELOCK (Bit 1) */ +#define FLASH_IER_PAGELOCK_Msk (0x2UL) /*!< PAGELOCK (Bitfield-Mask: 0x01) */ +#define FLASH_IER_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define FLASH_IER_PC_Msk (0x1UL) /*!< PC (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define FLASH_ISR_BUSY_Pos (5UL) /*!< BUSY (Bit 5) */ +#define FLASH_ISR_BUSY_Msk (0x20UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define FLASH_ISR_PROG_Pos (4UL) /*!< PROG (Bit 4) */ +#define FLASH_ISR_PROG_Msk (0x10UL) /*!< PROG (Bitfield-Mask: 0x01) */ +#define FLASH_ISR_CACHEON_Pos (3UL) /*!< CACHEON (Bit 3) */ +#define FLASH_ISR_CACHEON_Msk (0x8UL) /*!< CACHEON (Bitfield-Mask: 0x01) */ +#define FLASH_ISR_SDKERR_Pos (2UL) /*!< SDKERR (Bit 2) */ +#define FLASH_ISR_SDKERR_Msk (0x4UL) /*!< SDKERR (Bitfield-Mask: 0x01) */ +#define FLASH_ISR_PAGELOCK_Pos (1UL) /*!< PAGELOCK (Bit 1) */ +#define FLASH_ISR_PAGELOCK_Msk (0x2UL) /*!< PAGELOCK (Bitfield-Mask: 0x01) */ +#define FLASH_ISR_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define FLASH_ISR_PC_Msk (0x1UL) /*!< PC (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define FLASH_ICR_PROG_Pos (4UL) /*!< PROG (Bit 4) */ +#define FLASH_ICR_PROG_Msk (0x10UL) /*!< PROG (Bitfield-Mask: 0x01) */ +#define FLASH_ICR_CACHEON_Pos (3UL) /*!< CACHEON (Bit 3) */ +#define FLASH_ICR_CACHEON_Msk (0x8UL) /*!< CACHEON (Bitfield-Mask: 0x01) */ +#define FLASH_ICR_SDKERR_Pos (2UL) /*!< SDKERR (Bit 2) */ +#define FLASH_ICR_SDKERR_Msk (0x4UL) /*!< SDKERR (Bitfield-Mask: 0x01) */ +#define FLASH_ICR_PAGELOCK_Pos (1UL) /*!< PAGELOCK (Bit 1) */ +#define FLASH_ICR_PAGELOCK_Msk (0x2UL) /*!< PAGELOCK (Bitfield-Mask: 0x01) */ +#define FLASH_ICR_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define FLASH_ICR_PC_Msk (0x1UL) /*!< PC (Bitfield-Mask: 0x01) */ +/* ======================================================== SDKCFR ========================================================= */ +#define FLASH_SDKCFR_END_Pos (8UL) /*!< END (Bit 8) */ +#define FLASH_SDKCFR_END_Msk (0x7f00UL) /*!< END (Bitfield-Mask: 0x7f) */ +#define FLASH_SDKCFR_START_Pos (0UL) /*!< START (Bit 0) */ +#define FLASH_SDKCFR_START_Msk (0x7fUL) /*!< START (Bitfield-Mask: 0x7f) */ + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DIR ========================================================== */ +#define GPIOx_DIR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_DIR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_DIR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_DIR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_DIR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_DIR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_DIR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_DIR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_DIR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_DIR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_DIR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_DIR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_DIR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_DIR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_DIR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_DIR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_DIR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_DIR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================= OPENDRAIN ======================================================= */ +#define GPIOx_OPENDRAIN_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_OPENDRAIN_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_OPENDRAIN_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_OPENDRAIN_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_OPENDRAIN_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_OPENDRAIN_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_OPENDRAIN_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_OPENDRAIN_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_OPENDRAIN_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_OPENDRAIN_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_OPENDRAIN_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_OPENDRAIN_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_OPENDRAIN_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_OPENDRAIN_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_OPENDRAIN_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_OPENDRAIN_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_OPENDRAIN_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_OPENDRAIN_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== PUR ========================================================== */ +#define GPIOx_PUR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_PUR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_PUR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_PUR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_PUR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_PUR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_PUR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_PUR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_PUR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_PUR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_PUR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_PUR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_PUR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_PUR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_PUR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_PUR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_PUR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_PUR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= AFRH ========================================================== */ +#define GPIOx_AFRH_PIN15_Pos (28UL) /*!< PIN15 (Bit 28) */ +#define GPIOx_AFRH_PIN15_Msk (0xf0000000UL) /*!< PIN15 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_PIN14_Pos (24UL) /*!< PIN14 (Bit 24) */ +#define GPIOx_AFRH_PIN14_Msk (0xf000000UL) /*!< PIN14 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_PIN13_Pos (20UL) /*!< PIN13 (Bit 20) */ +#define GPIOx_AFRH_PIN13_Msk (0xf00000UL) /*!< PIN13 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_PIN12_Pos (16UL) /*!< PIN12 (Bit 16) */ +#define GPIOx_AFRH_PIN12_Msk (0xf0000UL) /*!< PIN12 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_PIN11_Pos (12UL) /*!< PIN11 (Bit 12) */ +#define GPIOx_AFRH_PIN11_Msk (0xf000UL) /*!< PIN11 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_PIN10_Pos (8UL) /*!< PIN10 (Bit 8) */ +#define GPIOx_AFRH_PIN10_Msk (0xf00UL) /*!< PIN10 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_PIN9_Pos (4UL) /*!< PIN9 (Bit 4) */ +#define GPIOx_AFRH_PIN9_Msk (0xf0UL) /*!< PIN9 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRH_PIN8_Pos (0UL) /*!< PIN8 (Bit 0) */ +#define GPIOx_AFRH_PIN8_Msk (0xfUL) /*!< PIN8 (Bitfield-Mask: 0x0f) */ +/* ========================================================= AFRL ========================================================== */ +#define GPIOx_AFRL_PIN7_Pos (28UL) /*!< PIN7 (Bit 28) */ +#define GPIOx_AFRL_PIN7_Msk (0xf0000000UL) /*!< PIN7 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_PIN6_Pos (24UL) /*!< PIN6 (Bit 24) */ +#define GPIOx_AFRL_PIN6_Msk (0xf000000UL) /*!< PIN6 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_PIN5_Pos (20UL) /*!< PIN5 (Bit 20) */ +#define GPIOx_AFRL_PIN5_Msk (0xf00000UL) /*!< PIN5 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_PIN4_Pos (16UL) /*!< PIN4 (Bit 16) */ +#define GPIOx_AFRL_PIN4_Msk (0xf0000UL) /*!< PIN4 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_PIN3_Pos (12UL) /*!< PIN3 (Bit 12) */ +#define GPIOx_AFRL_PIN3_Msk (0xf000UL) /*!< PIN3 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_PIN2_Pos (8UL) /*!< PIN2 (Bit 8) */ +#define GPIOx_AFRL_PIN2_Msk (0xf00UL) /*!< PIN2 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_PIN1_Pos (4UL) /*!< PIN1 (Bit 4) */ +#define GPIOx_AFRL_PIN1_Msk (0xf0UL) /*!< PIN1 (Bitfield-Mask: 0x0f) */ +#define GPIOx_AFRL_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_AFRL_PIN0_Msk (0xfUL) /*!< PIN0 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ANALOG ========================================================= */ +#define GPIOx_ANALOG_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_ANALOG_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_ANALOG_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_ANALOG_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_ANALOG_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_ANALOG_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_ANALOG_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_ANALOG_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_ANALOG_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_ANALOG_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_ANALOG_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_ANALOG_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_ANALOG_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_ANALOG_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_ANALOG_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_ANALOG_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_ANALOG_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_ANALOG_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== RISEIE ========================================================= */ +#define GPIOx_RISEIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_RISEIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_RISEIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_RISEIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_RISEIE_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_RISEIE_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_RISEIE_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_RISEIE_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_RISEIE_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_RISEIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_RISEIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_RISEIE_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_RISEIE_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_RISEIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_RISEIE_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_RISEIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_RISEIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_RISEIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FALLIE ========================================================= */ +#define GPIOx_FALLIE_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_FALLIE_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_FALLIE_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_FALLIE_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_FALLIE_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_FALLIE_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_FALLIE_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_FALLIE_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_FALLIE_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_FALLIE_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_FALLIE_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_FALLIE_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_FALLIE_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_FALLIE_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_FALLIE_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_FALLIE_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_FALLIE_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_FALLIE_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define GPIOx_ISR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_ISR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_ISR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_ISR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_ISR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_ISR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_ISR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_ISR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_ISR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_ISR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_ISR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_ISR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_ISR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_ISR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_ISR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_ISR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_ISR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_ISR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define GPIOx_ICR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_ICR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_ICR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_ICR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_ICR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_ICR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_ICR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_ICR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_ICR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_ICR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_ICR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_ICR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_ICR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_ICR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_ICR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_ICR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_ICR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_ICR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FILTER ========================================================= */ +#define GPIOx_FILTER_FLTCLK_Pos (16UL) /*!< FLTCLK (Bit 16) */ +#define GPIOx_FILTER_FLTCLK_Msk (0x70000UL) /*!< FLTCLK (Bitfield-Mask: 0x07) */ +#define GPIOx_FILTER_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_FILTER_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_FILTER_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_FILTER_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_FILTER_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_FILTER_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_FILTER_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_FILTER_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_FILTER_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_FILTER_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_FILTER_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_FILTER_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_FILTER_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_FILTER_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_FILTER_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_FILTER_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_FILTER_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_FILTER_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== IDR ========================================================== */ +#define GPIOx_IDR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_IDR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_IDR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_IDR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_IDR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_IDR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_IDR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_IDR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_IDR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_IDR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_IDR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_IDR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_IDR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_IDR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_IDR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_IDR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_IDR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_IDR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== ODR ========================================================== */ +#define GPIOx_ODR_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_ODR_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_ODR_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_ODR_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_ODR_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_ODR_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_ODR_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_ODR_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_ODR_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_ODR_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_ODR_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_ODR_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_ODR_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_ODR_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_ODR_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_ODR_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_ODR_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_ODR_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ +/* ========================================================== BRR ========================================================== */ +#define GPIOx_BRR_BRR15_Pos (15UL) /*!< BRR15 (Bit 15) */ +#define GPIOx_BRR_BRR15_Msk (0x8000UL) /*!< BRR15 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR14_Pos (14UL) /*!< BRR14 (Bit 14) */ +#define GPIOx_BRR_BRR14_Msk (0x4000UL) /*!< BRR14 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR13_Pos (13UL) /*!< BRR13 (Bit 13) */ +#define GPIOx_BRR_BRR13_Msk (0x2000UL) /*!< BRR13 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR12_Pos (12UL) /*!< BRR12 (Bit 12) */ +#define GPIOx_BRR_BRR12_Msk (0x1000UL) /*!< BRR12 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR11_Pos (11UL) /*!< BRR11 (Bit 11) */ +#define GPIOx_BRR_BRR11_Msk (0x800UL) /*!< BRR11 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR10_Pos (10UL) /*!< BRR10 (Bit 10) */ +#define GPIOx_BRR_BRR10_Msk (0x400UL) /*!< BRR10 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR9_Pos (9UL) /*!< BRR9 (Bit 9) */ +#define GPIOx_BRR_BRR9_Msk (0x200UL) /*!< BRR9 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR8_Pos (8UL) /*!< BRR8 (Bit 8) */ +#define GPIOx_BRR_BRR8_Msk (0x100UL) /*!< BRR8 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR7_Pos (7UL) /*!< BRR7 (Bit 7) */ +#define GPIOx_BRR_BRR7_Msk (0x80UL) /*!< BRR7 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR6_Pos (6UL) /*!< BRR6 (Bit 6) */ +#define GPIOx_BRR_BRR6_Msk (0x40UL) /*!< BRR6 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR5_Pos (5UL) /*!< BRR5 (Bit 5) */ +#define GPIOx_BRR_BRR5_Msk (0x20UL) /*!< BRR5 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR4_Pos (4UL) /*!< BRR4 (Bit 4) */ +#define GPIOx_BRR_BRR4_Msk (0x10UL) /*!< BRR4 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR3_Pos (3UL) /*!< BRR3 (Bit 3) */ +#define GPIOx_BRR_BRR3_Msk (0x8UL) /*!< BRR3 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR2_Pos (2UL) /*!< BRR2 (Bit 2) */ +#define GPIOx_BRR_BRR2_Msk (0x4UL) /*!< BRR2 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR1_Pos (1UL) /*!< BRR1 (Bit 1) */ +#define GPIOx_BRR_BRR1_Msk (0x2UL) /*!< BRR1 (Bitfield-Mask: 0x01) */ +#define GPIOx_BRR_BRR0_Pos (0UL) /*!< BRR0 (Bit 0) */ +#define GPIOx_BRR_BRR0_Msk (0x1UL) /*!< BRR0 (Bitfield-Mask: 0x01) */ +/* ========================================================= BSRR ========================================================== */ +#define GPIOx_BSRR_BRR15_Pos (31UL) /*!< BRR15 (Bit 31) */ +#define GPIOx_BSRR_BRR15_Msk (0x80000000UL) /*!< BRR15 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR14_Pos (30UL) /*!< BRR14 (Bit 30) */ +#define GPIOx_BSRR_BRR14_Msk (0x40000000UL) /*!< BRR14 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR13_Pos (29UL) /*!< BRR13 (Bit 29) */ +#define GPIOx_BSRR_BRR13_Msk (0x20000000UL) /*!< BRR13 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR12_Pos (28UL) /*!< BRR12 (Bit 28) */ +#define GPIOx_BSRR_BRR12_Msk (0x10000000UL) /*!< BRR12 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR11_Pos (27UL) /*!< BRR11 (Bit 27) */ +#define GPIOx_BSRR_BRR11_Msk (0x8000000UL) /*!< BRR11 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR10_Pos (26UL) /*!< BRR10 (Bit 26) */ +#define GPIOx_BSRR_BRR10_Msk (0x4000000UL) /*!< BRR10 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR9_Pos (25UL) /*!< BRR9 (Bit 25) */ +#define GPIOx_BSRR_BRR9_Msk (0x2000000UL) /*!< BRR9 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR8_Pos (24UL) /*!< BRR8 (Bit 24) */ +#define GPIOx_BSRR_BRR8_Msk (0x1000000UL) /*!< BRR8 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR7_Pos (23UL) /*!< BRR7 (Bit 23) */ +#define GPIOx_BSRR_BRR7_Msk (0x800000UL) /*!< BRR7 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR6_Pos (22UL) /*!< BRR6 (Bit 22) */ +#define GPIOx_BSRR_BRR6_Msk (0x400000UL) /*!< BRR6 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR5_Pos (21UL) /*!< BRR5 (Bit 21) */ +#define GPIOx_BSRR_BRR5_Msk (0x200000UL) /*!< BRR5 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR4_Pos (20UL) /*!< BRR4 (Bit 20) */ +#define GPIOx_BSRR_BRR4_Msk (0x100000UL) /*!< BRR4 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR3_Pos (19UL) /*!< BRR3 (Bit 19) */ +#define GPIOx_BSRR_BRR3_Msk (0x80000UL) /*!< BRR3 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR2_Pos (18UL) /*!< BRR2 (Bit 18) */ +#define GPIOx_BSRR_BRR2_Msk (0x40000UL) /*!< BRR2 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR1_Pos (17UL) /*!< BRR1 (Bit 17) */ +#define GPIOx_BSRR_BRR1_Msk (0x20000UL) /*!< BRR1 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BRR0_Pos (16UL) /*!< BRR0 (Bit 16) */ +#define GPIOx_BSRR_BRR0_Msk (0x10000UL) /*!< BRR0 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS15_Pos (15UL) /*!< BSS15 (Bit 15) */ +#define GPIOx_BSRR_BSS15_Msk (0x8000UL) /*!< BSS15 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS14_Pos (14UL) /*!< BSS14 (Bit 14) */ +#define GPIOx_BSRR_BSS14_Msk (0x4000UL) /*!< BSS14 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS13_Pos (13UL) /*!< BSS13 (Bit 13) */ +#define GPIOx_BSRR_BSS13_Msk (0x2000UL) /*!< BSS13 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS12_Pos (12UL) /*!< BSS12 (Bit 12) */ +#define GPIOx_BSRR_BSS12_Msk (0x1000UL) /*!< BSS12 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS11_Pos (11UL) /*!< BSS11 (Bit 11) */ +#define GPIOx_BSRR_BSS11_Msk (0x800UL) /*!< BSS11 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS10_Pos (10UL) /*!< BSS10 (Bit 10) */ +#define GPIOx_BSRR_BSS10_Msk (0x400UL) /*!< BSS10 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS9_Pos (9UL) /*!< BSS9 (Bit 9) */ +#define GPIOx_BSRR_BSS9_Msk (0x200UL) /*!< BSS9 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS8_Pos (8UL) /*!< BSS8 (Bit 8) */ +#define GPIOx_BSRR_BSS8_Msk (0x100UL) /*!< BSS8 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS7_Pos (7UL) /*!< BSS7 (Bit 7) */ +#define GPIOx_BSRR_BSS7_Msk (0x80UL) /*!< BSS7 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS6_Pos (6UL) /*!< BSS6 (Bit 6) */ +#define GPIOx_BSRR_BSS6_Msk (0x40UL) /*!< BSS6 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS5_Pos (5UL) /*!< BSS5 (Bit 5) */ +#define GPIOx_BSRR_BSS5_Msk (0x20UL) /*!< BSS5 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS4_Pos (4UL) /*!< BSS4 (Bit 4) */ +#define GPIOx_BSRR_BSS4_Msk (0x10UL) /*!< BSS4 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS3_Pos (3UL) /*!< BSS3 (Bit 3) */ +#define GPIOx_BSRR_BSS3_Msk (0x8UL) /*!< BSS3 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS2_Pos (2UL) /*!< BSS2 (Bit 2) */ +#define GPIOx_BSRR_BSS2_Msk (0x4UL) /*!< BSS2 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS1_Pos (1UL) /*!< BSS1 (Bit 1) */ +#define GPIOx_BSRR_BSS1_Msk (0x2UL) /*!< BSS1 (Bitfield-Mask: 0x01) */ +#define GPIOx_BSRR_BSS0_Pos (0UL) /*!< BSS0 (Bit 0) */ +#define GPIOx_BSRR_BSS0_Msk (0x1UL) /*!< BSS0 (Bitfield-Mask: 0x01) */ +/* ========================================================== TOG ========================================================== */ +#define GPIOx_TOG_PIN15_Pos (15UL) /*!< PIN15 (Bit 15) */ +#define GPIOx_TOG_PIN15_Msk (0x8000UL) /*!< PIN15 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN14_Pos (14UL) /*!< PIN14 (Bit 14) */ +#define GPIOx_TOG_PIN14_Msk (0x4000UL) /*!< PIN14 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN13_Pos (13UL) /*!< PIN13 (Bit 13) */ +#define GPIOx_TOG_PIN13_Msk (0x2000UL) /*!< PIN13 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN12_Pos (12UL) /*!< PIN12 (Bit 12) */ +#define GPIOx_TOG_PIN12_Msk (0x1000UL) /*!< PIN12 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN11_Pos (11UL) /*!< PIN11 (Bit 11) */ +#define GPIOx_TOG_PIN11_Msk (0x800UL) /*!< PIN11 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN10_Pos (10UL) /*!< PIN10 (Bit 10) */ +#define GPIOx_TOG_PIN10_Msk (0x400UL) /*!< PIN10 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN9_Pos (9UL) /*!< PIN9 (Bit 9) */ +#define GPIOx_TOG_PIN9_Msk (0x200UL) /*!< PIN9 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN8_Pos (8UL) /*!< PIN8 (Bit 8) */ +#define GPIOx_TOG_PIN8_Msk (0x100UL) /*!< PIN8 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ +#define GPIOx_TOG_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ +#define GPIOx_TOG_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ +#define GPIOx_TOG_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ +#define GPIOx_TOG_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ +#define GPIOx_TOG_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ +#define GPIOx_TOG_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ +#define GPIOx_TOG_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ +#define GPIOx_TOG_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ +#define GPIOx_TOG_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GTIM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define GTIMx_CR1_UIFREMAP_Pos (11UL) /*!< UIFREMAP (Bit 11) */ +#define GTIMx_CR1_UIFREMAP_Msk (0x800UL) /*!< UIFREMAP (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_CKD_Pos (8UL) /*!< CKD (Bit 8) */ +#define GTIMx_CR1_CKD_Msk (0x300UL) /*!< CKD (Bitfield-Mask: 0x03) */ +#define GTIMx_CR1_ARPE_Pos (7UL) /*!< ARPE (Bit 7) */ +#define GTIMx_CR1_ARPE_Msk (0x80UL) /*!< ARPE (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_CMS_Pos (5UL) /*!< CMS (Bit 5) */ +#define GTIMx_CR1_CMS_Msk (0x60UL) /*!< CMS (Bitfield-Mask: 0x03) */ +#define GTIMx_CR1_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define GTIMx_CR1_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_OPM_Pos (3UL) /*!< OPM (Bit 3) */ +#define GTIMx_CR1_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_URS_Pos (2UL) /*!< URS (Bit 2) */ +#define GTIMx_CR1_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */ +#define GTIMx_CR1_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */ +#define GTIMx_CR1_CEN_Pos (0UL) /*!< CEN (Bit 0) */ +#define GTIMx_CR1_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define GTIMx_CR2_MMSH_Pos (25UL) /*!< MMSH (Bit 25) */ +#define GTIMx_CR2_MMSH_Msk (0x6000000UL) /*!< MMSH (Bitfield-Mask: 0x03) */ +#define GTIMx_CR2_TI1S_Pos (7UL) /*!< TI1S (Bit 7) */ +#define GTIMx_CR2_TI1S_Msk (0x80UL) /*!< TI1S (Bitfield-Mask: 0x01) */ +#define GTIMx_CR2_MMS_Pos (4UL) /*!< MMS (Bit 4) */ +#define GTIMx_CR2_MMS_Msk (0x70UL) /*!< MMS (Bitfield-Mask: 0x07) */ +#define GTIMx_CR2_CCDS_Pos (3UL) /*!< CCDS (Bit 3) */ +#define GTIMx_CR2_CCDS_Msk (0x8UL) /*!< CCDS (Bitfield-Mask: 0x01) */ +/* ========================================================= SMCR ========================================================== */ +#define GTIMx_SMCR_SMSPS_Pos (25UL) /*!< SMSPS (Bit 25) */ +#define GTIMx_SMCR_SMSPS_Msk (0x2000000UL) /*!< SMSPS (Bitfield-Mask: 0x01) */ +#define GTIMx_SMCR_SMSPE_Pos (24UL) /*!< SMSPE (Bit 24) */ +#define GTIMx_SMCR_SMSPE_Msk (0x1000000UL) /*!< SMSPE (Bitfield-Mask: 0x01) */ +#define GTIMx_SMCR_TSH_Pos (20UL) /*!< TSH (Bit 20) */ +#define GTIMx_SMCR_TSH_Msk (0x300000UL) /*!< TSH (Bitfield-Mask: 0x03) */ +#define GTIMx_SMCR_SMSH_Pos (16UL) /*!< SMSH (Bit 16) */ +#define GTIMx_SMCR_SMSH_Msk (0x10000UL) /*!< SMSH (Bitfield-Mask: 0x01) */ +#define GTIMx_SMCR_ETP_Pos (15UL) /*!< ETP (Bit 15) */ +#define GTIMx_SMCR_ETP_Msk (0x8000UL) /*!< ETP (Bitfield-Mask: 0x01) */ +#define GTIMx_SMCR_ECE_Pos (14UL) /*!< ECE (Bit 14) */ +#define GTIMx_SMCR_ECE_Msk (0x4000UL) /*!< ECE (Bitfield-Mask: 0x01) */ +#define GTIMx_SMCR_ETPS_Pos (12UL) /*!< ETPS (Bit 12) */ +#define GTIMx_SMCR_ETPS_Msk (0x3000UL) /*!< ETPS (Bitfield-Mask: 0x03) */ +#define GTIMx_SMCR_ETF_Pos (8UL) /*!< ETF (Bit 8) */ +#define GTIMx_SMCR_ETF_Msk (0xf00UL) /*!< ETF (Bitfield-Mask: 0x0f) */ +#define GTIMx_SMCR_MSM_Pos (7UL) /*!< MSM (Bit 7) */ +#define GTIMx_SMCR_MSM_Msk (0x80UL) /*!< MSM (Bitfield-Mask: 0x01) */ +#define GTIMx_SMCR_TS_Pos (4UL) /*!< TS (Bit 4) */ +#define GTIMx_SMCR_TS_Msk (0x70UL) /*!< TS (Bitfield-Mask: 0x07) */ +#define GTIMx_SMCR_OCCS_Pos (3UL) /*!< OCCS (Bit 3) */ +#define GTIMx_SMCR_OCCS_Msk (0x8UL) /*!< OCCS (Bitfield-Mask: 0x01) */ +#define GTIMx_SMCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */ +#define GTIMx_SMCR_SMS_Msk (0x7UL) /*!< SMS (Bitfield-Mask: 0x07) */ +/* ========================================================== IER ========================================================== */ +#define GTIMx_IER_TERRIE_Pos (23UL) /*!< TERRIE (Bit 23) */ +#define GTIMx_IER_TERRIE_Msk (0x800000UL) /*!< TERRIE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_IERRIE_Pos (22UL) /*!< IERRIE (Bit 22) */ +#define GTIMx_IER_IERRIE_Msk (0x400000UL) /*!< IERRIE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_DIRIE_Pos (21UL) /*!< DIRIE (Bit 21) */ +#define GTIMx_IER_DIRIE_Msk (0x200000UL) /*!< DIRIE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_IDXIE_Pos (20UL) /*!< IDXIE (Bit 20) */ +#define GTIMx_IER_IDXIE_Msk (0x100000UL) /*!< IDXIE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_TDE_Pos (14UL) /*!< TDE (Bit 14) */ +#define GTIMx_IER_TDE_Msk (0x4000UL) /*!< TDE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC4DE_Pos (12UL) /*!< CC4DE (Bit 12) */ +#define GTIMx_IER_CC4DE_Msk (0x1000UL) /*!< CC4DE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC3DE_Pos (11UL) /*!< CC3DE (Bit 11) */ +#define GTIMx_IER_CC3DE_Msk (0x800UL) /*!< CC3DE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC2DE_Pos (10UL) /*!< CC2DE (Bit 10) */ +#define GTIMx_IER_CC2DE_Msk (0x400UL) /*!< CC2DE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC1DE_Pos (9UL) /*!< CC1DE (Bit 9) */ +#define GTIMx_IER_CC1DE_Msk (0x200UL) /*!< CC1DE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_UDE_Pos (8UL) /*!< UDE (Bit 8) */ +#define GTIMx_IER_UDE_Msk (0x100UL) /*!< UDE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_TIE_Pos (6UL) /*!< TIE (Bit 6) */ +#define GTIMx_IER_TIE_Msk (0x40UL) /*!< TIE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC4IE_Pos (4UL) /*!< CC4IE (Bit 4) */ +#define GTIMx_IER_CC4IE_Msk (0x10UL) /*!< CC4IE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC3IE_Pos (3UL) /*!< CC3IE (Bit 3) */ +#define GTIMx_IER_CC3IE_Msk (0x8UL) /*!< CC3IE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC2IE_Pos (2UL) /*!< CC2IE (Bit 2) */ +#define GTIMx_IER_CC2IE_Msk (0x4UL) /*!< CC2IE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_CC1IE_Pos (1UL) /*!< CC1IE (Bit 1) */ +#define GTIMx_IER_CC1IE_Msk (0x2UL) /*!< CC1IE (Bitfield-Mask: 0x01) */ +#define GTIMx_IER_UIE_Pos (0UL) /*!< UIE (Bit 0) */ +#define GTIMx_IER_UIE_Msk (0x1UL) /*!< UIE (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define GTIMx_ISR_TERRF_Pos (23UL) /*!< TERRF (Bit 23) */ +#define GTIMx_ISR_TERRF_Msk (0x800000UL) /*!< TERRF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_IERRF_Pos (22UL) /*!< IERRF (Bit 22) */ +#define GTIMx_ISR_IERRF_Msk (0x400000UL) /*!< IERRF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_DIRF_Pos (21UL) /*!< DIRF (Bit 21) */ +#define GTIMx_ISR_DIRF_Msk (0x200000UL) /*!< DIRF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_IDXF_Pos (20UL) /*!< IDXF (Bit 20) */ +#define GTIMx_ISR_IDXF_Msk (0x100000UL) /*!< IDXF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC4OF_Pos (12UL) /*!< CC4OF (Bit 12) */ +#define GTIMx_ISR_CC4OF_Msk (0x1000UL) /*!< CC4OF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC3OF_Pos (11UL) /*!< CC3OF (Bit 11) */ +#define GTIMx_ISR_CC3OF_Msk (0x800UL) /*!< CC3OF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC2OF_Pos (10UL) /*!< CC2OF (Bit 10) */ +#define GTIMx_ISR_CC2OF_Msk (0x400UL) /*!< CC2OF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC1OF_Pos (9UL) /*!< CC1OF (Bit 9) */ +#define GTIMx_ISR_CC1OF_Msk (0x200UL) /*!< CC1OF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_TIF_Pos (6UL) /*!< TIF (Bit 6) */ +#define GTIMx_ISR_TIF_Msk (0x40UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC4IF_Pos (4UL) /*!< CC4IF (Bit 4) */ +#define GTIMx_ISR_CC4IF_Msk (0x10UL) /*!< CC4IF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC3IF_Pos (3UL) /*!< CC3IF (Bit 3) */ +#define GTIMx_ISR_CC3IF_Msk (0x8UL) /*!< CC3IF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC2IF_Pos (2UL) /*!< CC2IF (Bit 2) */ +#define GTIMx_ISR_CC2IF_Msk (0x4UL) /*!< CC2IF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_CC1IF_Pos (1UL) /*!< CC1IF (Bit 1) */ +#define GTIMx_ISR_CC1IF_Msk (0x2UL) /*!< CC1IF (Bitfield-Mask: 0x01) */ +#define GTIMx_ISR_UIF_Pos (0UL) /*!< UIF (Bit 0) */ +#define GTIMx_ISR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define GTIMx_ICR_TERRF_Pos (23UL) /*!< TERRF (Bit 23) */ +#define GTIMx_ICR_TERRF_Msk (0x800000UL) /*!< TERRF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_IERRF_Pos (22UL) /*!< IERRF (Bit 22) */ +#define GTIMx_ICR_IERRF_Msk (0x400000UL) /*!< IERRF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_DIRF_Pos (21UL) /*!< DIRF (Bit 21) */ +#define GTIMx_ICR_DIRF_Msk (0x200000UL) /*!< DIRF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_IDXF_Pos (20UL) /*!< IDXF (Bit 20) */ +#define GTIMx_ICR_IDXF_Msk (0x100000UL) /*!< IDXF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC4OF_Pos (12UL) /*!< CC4OF (Bit 12) */ +#define GTIMx_ICR_CC4OF_Msk (0x1000UL) /*!< CC4OF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC3OF_Pos (11UL) /*!< CC3OF (Bit 11) */ +#define GTIMx_ICR_CC3OF_Msk (0x800UL) /*!< CC3OF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC2OF_Pos (10UL) /*!< CC2OF (Bit 10) */ +#define GTIMx_ICR_CC2OF_Msk (0x400UL) /*!< CC2OF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC1OF_Pos (9UL) /*!< CC1OF (Bit 9) */ +#define GTIMx_ICR_CC1OF_Msk (0x200UL) /*!< CC1OF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_TIF_Pos (6UL) /*!< TIF (Bit 6) */ +#define GTIMx_ICR_TIF_Msk (0x40UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC4IF_Pos (4UL) /*!< CC4IF (Bit 4) */ +#define GTIMx_ICR_CC4IF_Msk (0x10UL) /*!< CC4IF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC3IF_Pos (3UL) /*!< CC3IF (Bit 3) */ +#define GTIMx_ICR_CC3IF_Msk (0x8UL) /*!< CC3IF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC2IF_Pos (2UL) /*!< CC2IF (Bit 2) */ +#define GTIMx_ICR_CC2IF_Msk (0x4UL) /*!< CC2IF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_CC1IF_Pos (1UL) /*!< CC1IF (Bit 1) */ +#define GTIMx_ICR_CC1IF_Msk (0x2UL) /*!< CC1IF (Bitfield-Mask: 0x01) */ +#define GTIMx_ICR_UIF_Pos (0UL) /*!< UIF (Bit 0) */ +#define GTIMx_ICR_UIF_Msk (0x1UL) /*!< UIF (Bitfield-Mask: 0x01) */ +/* ========================================================== EGR ========================================================== */ +#define GTIMx_EGR_TG_Pos (6UL) /*!< TG (Bit 6) */ +#define GTIMx_EGR_TG_Msk (0x40UL) /*!< TG (Bitfield-Mask: 0x01) */ +#define GTIMx_EGR_CC4G_Pos (4UL) /*!< CC4G (Bit 4) */ +#define GTIMx_EGR_CC4G_Msk (0x10UL) /*!< CC4G (Bitfield-Mask: 0x01) */ +#define GTIMx_EGR_CC3G_Pos (3UL) /*!< CC3G (Bit 3) */ +#define GTIMx_EGR_CC3G_Msk (0x8UL) /*!< CC3G (Bitfield-Mask: 0x01) */ +#define GTIMx_EGR_CC2G_Pos (2UL) /*!< CC2G (Bit 2) */ +#define GTIMx_EGR_CC2G_Msk (0x4UL) /*!< CC2G (Bitfield-Mask: 0x01) */ +#define GTIMx_EGR_CC1G_Pos (1UL) /*!< CC1G (Bit 1) */ +#define GTIMx_EGR_CC1G_Msk (0x2UL) /*!< CC1G (Bitfield-Mask: 0x01) */ +#define GTIMx_EGR_UG_Pos (0UL) /*!< UG (Bit 0) */ +#define GTIMx_EGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */ +/* ======================================================= CCMR1CAP ======================================================== */ +#define GTIMx_CCMR1CAP_IC2F_Pos (12UL) /*!< IC2F (Bit 12) */ +#define GTIMx_CCMR1CAP_IC2F_Msk (0xf000UL) /*!< IC2F (Bitfield-Mask: 0x0f) */ +#define GTIMx_CCMR1CAP_IC2PSC_Pos (10UL) /*!< IC2PSC (Bit 10) */ +#define GTIMx_CCMR1CAP_IC2PSC_Msk (0xc00UL) /*!< IC2PSC (Bitfield-Mask: 0x03) */ +#define GTIMx_CCMR1CAP_CC2S_Pos (8UL) /*!< CC2S (Bit 8) */ +#define GTIMx_CCMR1CAP_CC2S_Msk (0x300UL) /*!< CC2S (Bitfield-Mask: 0x03) */ +#define GTIMx_CCMR1CAP_IC1F_Pos (4UL) /*!< IC1F (Bit 4) */ +#define GTIMx_CCMR1CAP_IC1F_Msk (0xf0UL) /*!< IC1F (Bitfield-Mask: 0x0f) */ +#define GTIMx_CCMR1CAP_IC1PSC_Pos (2UL) /*!< IC1PSC (Bit 2) */ +#define GTIMx_CCMR1CAP_IC1PSC_Msk (0xcUL) /*!< IC1PSC (Bitfield-Mask: 0x03) */ +#define GTIMx_CCMR1CAP_CC1S_Pos (0UL) /*!< CC1S (Bit 0) */ +#define GTIMx_CCMR1CAP_CC1S_Msk (0x3UL) /*!< CC1S (Bitfield-Mask: 0x03) */ +/* ======================================================= CCMR1CMP ======================================================== */ +#define GTIMx_CCMR1CMP_OC2MH_Pos (24UL) /*!< OC2MH (Bit 24) */ +#define GTIMx_CCMR1CMP_OC2MH_Msk (0x1000000UL) /*!< OC2MH (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR1CMP_OC1MH_Pos (16UL) /*!< OC1MH (Bit 16) */ +#define GTIMx_CCMR1CMP_OC1MH_Msk (0x10000UL) /*!< OC1MH (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR1CMP_OC2CE_Pos (15UL) /*!< OC2CE (Bit 15) */ +#define GTIMx_CCMR1CMP_OC2CE_Msk (0x8000UL) /*!< OC2CE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR1CMP_OC2M_Pos (12UL) /*!< OC2M (Bit 12) */ +#define GTIMx_CCMR1CMP_OC2M_Msk (0x7000UL) /*!< OC2M (Bitfield-Mask: 0x07) */ +#define GTIMx_CCMR1CMP_OC2PE_Pos (11UL) /*!< OC2PE (Bit 11) */ +#define GTIMx_CCMR1CMP_OC2PE_Msk (0x800UL) /*!< OC2PE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR1CMP_OC2FE_Pos (10UL) /*!< OC2FE (Bit 10) */ +#define GTIMx_CCMR1CMP_OC2FE_Msk (0x400UL) /*!< OC2FE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR1CMP_CC2S_Pos (8UL) /*!< CC2S (Bit 8) */ +#define GTIMx_CCMR1CMP_CC2S_Msk (0x300UL) /*!< CC2S (Bitfield-Mask: 0x03) */ +#define GTIMx_CCMR1CMP_OC1CE_Pos (7UL) /*!< OC1CE (Bit 7) */ +#define GTIMx_CCMR1CMP_OC1CE_Msk (0x80UL) /*!< OC1CE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR1CMP_OC1M_Pos (4UL) /*!< OC1M (Bit 4) */ +#define GTIMx_CCMR1CMP_OC1M_Msk (0x70UL) /*!< OC1M (Bitfield-Mask: 0x07) */ +#define GTIMx_CCMR1CMP_OC1PE_Pos (3UL) /*!< OC1PE (Bit 3) */ +#define GTIMx_CCMR1CMP_OC1PE_Msk (0x8UL) /*!< OC1PE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR1CMP_OC1FE_Pos (2UL) /*!< OC1FE (Bit 2) */ +#define GTIMx_CCMR1CMP_OC1FE_Msk (0x4UL) /*!< OC1FE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR1CMP_CC1S_Pos (0UL) /*!< CC1S (Bit 0) */ +#define GTIMx_CCMR1CMP_CC1S_Msk (0x3UL) /*!< CC1S (Bitfield-Mask: 0x03) */ +/* ======================================================= CCMR2CAP ======================================================== */ +#define GTIMx_CCMR2CAP_IC4F_Pos (12UL) /*!< IC4F (Bit 12) */ +#define GTIMx_CCMR2CAP_IC4F_Msk (0xf000UL) /*!< IC4F (Bitfield-Mask: 0x0f) */ +#define GTIMx_CCMR2CAP_IC4PSC_Pos (10UL) /*!< IC4PSC (Bit 10) */ +#define GTIMx_CCMR2CAP_IC4PSC_Msk (0xc00UL) /*!< IC4PSC (Bitfield-Mask: 0x03) */ +#define GTIMx_CCMR2CAP_CC4S_Pos (8UL) /*!< CC4S (Bit 8) */ +#define GTIMx_CCMR2CAP_CC4S_Msk (0x300UL) /*!< CC4S (Bitfield-Mask: 0x03) */ +#define GTIMx_CCMR2CAP_IC3F_Pos (4UL) /*!< IC3F (Bit 4) */ +#define GTIMx_CCMR2CAP_IC3F_Msk (0xf0UL) /*!< IC3F (Bitfield-Mask: 0x0f) */ +#define GTIMx_CCMR2CAP_IC3PSC_Pos (2UL) /*!< IC3PSC (Bit 2) */ +#define GTIMx_CCMR2CAP_IC3PSC_Msk (0xcUL) /*!< IC3PSC (Bitfield-Mask: 0x03) */ +#define GTIMx_CCMR2CAP_CC3S_Pos (0UL) /*!< CC3S (Bit 0) */ +#define GTIMx_CCMR2CAP_CC3S_Msk (0x3UL) /*!< CC3S (Bitfield-Mask: 0x03) */ +/* ======================================================= CCMR2CMP ======================================================== */ +#define GTIMx_CCMR2CMP_OC4MH_Pos (24UL) /*!< OC4MH (Bit 24) */ +#define GTIMx_CCMR2CMP_OC4MH_Msk (0x1000000UL) /*!< OC4MH (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR2CMP_OC3MH_Pos (16UL) /*!< OC3MH (Bit 16) */ +#define GTIMx_CCMR2CMP_OC3MH_Msk (0x10000UL) /*!< OC3MH (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR2CMP_OC4CE_Pos (15UL) /*!< OC4CE (Bit 15) */ +#define GTIMx_CCMR2CMP_OC4CE_Msk (0x8000UL) /*!< OC4CE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR2CMP_OC4M_Pos (12UL) /*!< OC4M (Bit 12) */ +#define GTIMx_CCMR2CMP_OC4M_Msk (0x7000UL) /*!< OC4M (Bitfield-Mask: 0x07) */ +#define GTIMx_CCMR2CMP_OC4PE_Pos (11UL) /*!< OC4PE (Bit 11) */ +#define GTIMx_CCMR2CMP_OC4PE_Msk (0x800UL) /*!< OC4PE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR2CMP_OC4FE_Pos (10UL) /*!< OC4FE (Bit 10) */ +#define GTIMx_CCMR2CMP_OC4FE_Msk (0x400UL) /*!< OC4FE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR2CMP_CC4S_Pos (8UL) /*!< CC4S (Bit 8) */ +#define GTIMx_CCMR2CMP_CC4S_Msk (0x300UL) /*!< CC4S (Bitfield-Mask: 0x03) */ +#define GTIMx_CCMR2CMP_OC3CE_Pos (7UL) /*!< OC3CE (Bit 7) */ +#define GTIMx_CCMR2CMP_OC3CE_Msk (0x80UL) /*!< OC3CE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR2CMP_OC3M_Pos (4UL) /*!< OC3M (Bit 4) */ +#define GTIMx_CCMR2CMP_OC3M_Msk (0x70UL) /*!< OC3M (Bitfield-Mask: 0x07) */ +#define GTIMx_CCMR2CMP_OC3PE_Pos (3UL) /*!< OC3PE (Bit 3) */ +#define GTIMx_CCMR2CMP_OC3PE_Msk (0x8UL) /*!< OC3PE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR2CMP_OC3FE_Pos (2UL) /*!< OC3FE (Bit 2) */ +#define GTIMx_CCMR2CMP_OC3FE_Msk (0x4UL) /*!< OC3FE (Bitfield-Mask: 0x01) */ +#define GTIMx_CCMR2CMP_CC3S_Pos (0UL) /*!< CC3S (Bit 0) */ +#define GTIMx_CCMR2CMP_CC3S_Msk (0x3UL) /*!< CC3S (Bitfield-Mask: 0x03) */ +/* ========================================================= CCER ========================================================== */ +#define GTIMx_CCER_CC4NP_Pos (15UL) /*!< CC4NP (Bit 15) */ +#define GTIMx_CCER_CC4NP_Msk (0x8000UL) /*!< CC4NP (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC4P_Pos (13UL) /*!< CC4P (Bit 13) */ +#define GTIMx_CCER_CC4P_Msk (0x2000UL) /*!< CC4P (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC4E_Pos (12UL) /*!< CC4E (Bit 12) */ +#define GTIMx_CCER_CC4E_Msk (0x1000UL) /*!< CC4E (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC3NP_Pos (11UL) /*!< CC3NP (Bit 11) */ +#define GTIMx_CCER_CC3NP_Msk (0x800UL) /*!< CC3NP (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC3P_Pos (9UL) /*!< CC3P (Bit 9) */ +#define GTIMx_CCER_CC3P_Msk (0x200UL) /*!< CC3P (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC3E_Pos (8UL) /*!< CC3E (Bit 8) */ +#define GTIMx_CCER_CC3E_Msk (0x100UL) /*!< CC3E (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC2NP_Pos (7UL) /*!< CC2NP (Bit 7) */ +#define GTIMx_CCER_CC2NP_Msk (0x80UL) /*!< CC2NP (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC2P_Pos (5UL) /*!< CC2P (Bit 5) */ +#define GTIMx_CCER_CC2P_Msk (0x20UL) /*!< CC2P (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC2E_Pos (4UL) /*!< CC2E (Bit 4) */ +#define GTIMx_CCER_CC2E_Msk (0x10UL) /*!< CC2E (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC1NP_Pos (3UL) /*!< CC1NP (Bit 3) */ +#define GTIMx_CCER_CC1NP_Msk (0x8UL) /*!< CC1NP (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC1P_Pos (1UL) /*!< CC1P (Bit 1) */ +#define GTIMx_CCER_CC1P_Msk (0x2UL) /*!< CC1P (Bitfield-Mask: 0x01) */ +#define GTIMx_CCER_CC1E_Pos (0UL) /*!< CC1E (Bit 0) */ +#define GTIMx_CCER_CC1E_Msk (0x1UL) /*!< CC1E (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +#define GTIMx_CNT_UIFCPY_Pos (31UL) /*!< UIFCPY (Bit 31) */ +#define GTIMx_CNT_UIFCPY_Msk (0x80000000UL) /*!< UIFCPY (Bitfield-Mask: 0x01) */ +#define GTIMx_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define GTIMx_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== PSC ========================================================== */ +#define GTIMx_PSC_PSC_Pos (0UL) /*!< PSC (Bit 0) */ +#define GTIMx_PSC_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */ +/* ========================================================== ARR ========================================================== */ +#define GTIMx_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define GTIMx_ARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR1 ========================================================== */ +#define GTIMx_CCR1_CCR1_Pos (0UL) /*!< CCR1 (Bit 0) */ +#define GTIMx_CCR1_CCR1_Msk (0xffffUL) /*!< CCR1 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR2 ========================================================== */ +#define GTIMx_CCR2_CCR2_Pos (0UL) /*!< CCR2 (Bit 0) */ +#define GTIMx_CCR2_CCR2_Msk (0xffffUL) /*!< CCR2 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR3 ========================================================== */ +#define GTIMx_CCR3_CCR3_Pos (0UL) /*!< CCR3 (Bit 0) */ +#define GTIMx_CCR3_CCR3_Msk (0xffffUL) /*!< CCR3 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCR4 ========================================================== */ +#define GTIMx_CCR4_CCR4_Pos (0UL) /*!< CCR4 (Bit 0) */ +#define GTIMx_CCR4_CCR4_Msk (0xffffUL) /*!< CCR4 (Bitfield-Mask: 0xffff) */ +/* ========================================================== ECR ========================================================== */ +#define GTIMx_ECR_IPOS_Pos (6UL) /*!< IPOS (Bit 6) */ +#define GTIMx_ECR_IPOS_Msk (0xc0UL) /*!< IPOS (Bitfield-Mask: 0x03) */ +#define GTIMx_ECR_FIDX_Pos (5UL) /*!< FIDX (Bit 5) */ +#define GTIMx_ECR_FIDX_Msk (0x20UL) /*!< FIDX (Bitfield-Mask: 0x01) */ +#define GTIMx_ECR_IDIR_Pos (1UL) /*!< IDIR (Bit 1) */ +#define GTIMx_ECR_IDIR_Msk (0x6UL) /*!< IDIR (Bitfield-Mask: 0x03) */ +#define GTIMx_ECR_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define GTIMx_ECR_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ========================================================= TISEL ========================================================= */ +#define GTIMx_TISEL_TI4SEL_Pos (24UL) /*!< TI4SEL (Bit 24) */ +#define GTIMx_TISEL_TI4SEL_Msk (0xf000000UL) /*!< TI4SEL (Bitfield-Mask: 0x0f) */ +#define GTIMx_TISEL_TI3SEL_Pos (16UL) /*!< TI3SEL (Bit 16) */ +#define GTIMx_TISEL_TI3SEL_Msk (0xf0000UL) /*!< TI3SEL (Bitfield-Mask: 0x0f) */ +#define GTIMx_TISEL_TI2SEL_Pos (8UL) /*!< TI2SEL (Bit 8) */ +#define GTIMx_TISEL_TI2SEL_Msk (0xf00UL) /*!< TI2SEL (Bitfield-Mask: 0x0f) */ +#define GTIMx_TISEL_TI1SEL_Pos (0UL) /*!< TI1SEL (Bit 0) */ +#define GTIMx_TISEL_TI1SEL_Msk (0xfUL) /*!< TI1SEL (Bitfield-Mask: 0x0f) */ +/* ========================================================== AF1 ========================================================== */ +#define GTIMx_AF1_ETRSEL_Pos (14UL) /*!< ETRSEL (Bit 14) */ +#define GTIMx_AF1_ETRSEL_Msk (0x3c000UL) /*!< ETRSEL (Bitfield-Mask: 0x0f) */ +/* ========================================================== AF2 ========================================================== */ +#define GTIMx_AF2_OCRSEL_Pos (16UL) /*!< OCRSEL (Bit 16) */ +#define GTIMx_AF2_OCRSEL_Msk (0x70000UL) /*!< OCRSEL (Bitfield-Mask: 0x07) */ + + +/* =========================================================================================================================== */ +/* ================ HALLTIM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define HALLTIM_CR_SOFTCAP_Pos (23UL) /*!< SOFTCAP (Bit 23) */ +#define HALLTIM_CR_SOFTCAP_Msk (0x800000UL) /*!< SOFTCAP (Bitfield-Mask: 0x01) */ +#define HALLTIM_CR_FLT2LEN_Pos (8UL) /*!< FLT2LEN (Bit 8) */ +#define HALLTIM_CR_FLT2LEN_Msk (0x7fff00UL) /*!< FLT2LEN (Bitfield-Mask: 0x7fff) */ +#define HALLTIM_CR_MMS_Pos (4UL) /*!< MMS (Bit 4) */ +#define HALLTIM_CR_MMS_Msk (0x70UL) /*!< MMS (Bitfield-Mask: 0x07) */ +#define HALLTIM_CR_DIV_Pos (2UL) /*!< DIV (Bit 2) */ +#define HALLTIM_CR_DIV_Msk (0xcUL) /*!< DIV (Bitfield-Mask: 0x03) */ +#define HALLTIM_CR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */ +#define HALLTIM_CR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */ +#define HALLTIM_CR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define HALLTIM_CR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= DIER ========================================================== */ +#define HALLTIM_DIER_SOFTDMA_Pos (7UL) /*!< SOFTDMA (Bit 7) */ +#define HALLTIM_DIER_SOFTDMA_Msk (0x80UL) /*!< SOFTDMA (Bitfield-Mask: 0x01) */ +#define HALLTIM_DIER_MATCHDMA_Pos (6UL) /*!< MATCHDMA (Bit 6) */ +#define HALLTIM_DIER_MATCHDMA_Msk (0x40UL) /*!< MATCHDMA (Bitfield-Mask: 0x01) */ +#define HALLTIM_DIER_OVDMA_Pos (5UL) /*!< OVDMA (Bit 5) */ +#define HALLTIM_DIER_OVDMA_Msk (0x20UL) /*!< OVDMA (Bitfield-Mask: 0x01) */ +#define HALLTIM_DIER_CAPDMA_Pos (4UL) /*!< CAPDMA (Bit 4) */ +#define HALLTIM_DIER_CAPDMA_Msk (0x10UL) /*!< CAPDMA (Bitfield-Mask: 0x01) */ +#define HALLTIM_DIER_MATCHIE_Pos (2UL) /*!< MATCHIE (Bit 2) */ +#define HALLTIM_DIER_MATCHIE_Msk (0x4UL) /*!< MATCHIE (Bitfield-Mask: 0x01) */ +#define HALLTIM_DIER_OVIE_Pos (1UL) /*!< OVIE (Bit 1) */ +#define HALLTIM_DIER_OVIE_Msk (0x2UL) /*!< OVIE (Bitfield-Mask: 0x01) */ +#define HALLTIM_DIER_CAPIE_Pos (0UL) /*!< CAPIE (Bit 0) */ +#define HALLTIM_DIER_CAPIE_Msk (0x1UL) /*!< CAPIE (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +#define HALLTIM_CNT_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define HALLTIM_CNT_DATA_Msk (0xffffffUL) /*!< DATA (Bitfield-Mask: 0xffffff) */ +/* ========================================================== ARR ========================================================== */ +#define HALLTIM_ARR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define HALLTIM_ARR_DATA_Msk (0xffffffUL) /*!< DATA (Bitfield-Mask: 0xffffff) */ +/* ========================================================= WIDTH ========================================================= */ +#define HALLTIM_WIDTH_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define HALLTIM_WIDTH_DATA_Msk (0xffffffUL) /*!< DATA (Bitfield-Mask: 0xffffff) */ +/* ========================================================== CCR ========================================================== */ +#define HALLTIM_CCR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define HALLTIM_CCR_DATA_Msk (0xffffffUL) /*!< DATA (Bitfield-Mask: 0xffffff) */ +/* ========================================================== ISR ========================================================== */ +#define HALLTIM_ISR_MATCH_Pos (2UL) /*!< MATCH (Bit 2) */ +#define HALLTIM_ISR_MATCH_Msk (0x4UL) /*!< MATCH (Bitfield-Mask: 0x01) */ +#define HALLTIM_ISR_OV_Pos (1UL) /*!< OV (Bit 1) */ +#define HALLTIM_ISR_OV_Msk (0x2UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define HALLTIM_ISR_CAPF_Pos (0UL) /*!< CAPF (Bit 0) */ +#define HALLTIM_ISR_CAPF_Msk (0x1UL) /*!< CAPF (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define HALLTIM_ICR_MATCHF_Pos (2UL) /*!< MATCHF (Bit 2) */ +#define HALLTIM_ICR_MATCHF_Msk (0x4UL) /*!< MATCHF (Bitfield-Mask: 0x01) */ +#define HALLTIM_ICR_OVF_Pos (1UL) /*!< OVF (Bit 1) */ +#define HALLTIM_ICR_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define HALLTIM_ICR_CAPF_Pos (0UL) /*!< CAPF (Bit 0) */ +#define HALLTIM_ICR_CAPF_Msk (0x1UL) /*!< CAPF (Bitfield-Mask: 0x01) */ +/* ========================================================= STATE ========================================================= */ +#define HALLTIM_STATE_CH3S_Pos (6UL) /*!< CH3S (Bit 6) */ +#define HALLTIM_STATE_CH3S_Msk (0x40UL) /*!< CH3S (Bitfield-Mask: 0x01) */ +#define HALLTIM_STATE_CH2S_Pos (5UL) /*!< CH2S (Bit 5) */ +#define HALLTIM_STATE_CH2S_Msk (0x20UL) /*!< CH2S (Bitfield-Mask: 0x01) */ +#define HALLTIM_STATE_CH1S_Pos (4UL) /*!< CH1S (Bit 4) */ +#define HALLTIM_STATE_CH1S_Msk (0x10UL) /*!< CH1S (Bitfield-Mask: 0x01) */ +#define HALLTIM_STATE_CH3F_Pos (2UL) /*!< CH3F (Bit 2) */ +#define HALLTIM_STATE_CH3F_Msk (0x4UL) /*!< CH3F (Bitfield-Mask: 0x01) */ +#define HALLTIM_STATE_CH2F_Pos (1UL) /*!< CH2F (Bit 1) */ +#define HALLTIM_STATE_CH2F_Msk (0x2UL) /*!< CH2F (Bitfield-Mask: 0x01) */ +#define HALLTIM_STATE_CH1F_Pos (0UL) /*!< CH1F (Bit 0) */ +#define HALLTIM_STATE_CH1F_Msk (0x1UL) /*!< CH1F (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ I2C ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= INSEL ========================================================= */ +#define I2Cx_INSEL_SDAINSEL_Pos (3UL) /*!< SDAINSEL (Bit 3) */ +#define I2Cx_INSEL_SDAINSEL_Msk (0x38UL) /*!< SDAINSEL (Bitfield-Mask: 0x07) */ +#define I2Cx_INSEL_SCLINSEL_Pos (0UL) /*!< SCLINSEL (Bit 0) */ +#define I2Cx_INSEL_SCLINSEL_Msk (0x7UL) /*!< SCLINSEL (Bitfield-Mask: 0x07) */ +/* ========================================================= MCR0 ========================================================== */ +#define I2Cx_MCR0_RXFIFORST_Pos (9UL) /*!< RXFIFORST (Bit 9) */ +#define I2Cx_MCR0_RXFIFORST_Msk (0x200UL) /*!< RXFIFORST (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR0_TXFIFORST_Pos (8UL) /*!< TXFIFORST (Bit 8) */ +#define I2Cx_MCR0_TXFIFORST_Msk (0x100UL) /*!< TXFIFORST (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR0_CLKSRC_Pos (6UL) /*!< CLKSRC (Bit 6) */ +#define I2Cx_MCR0_CLKSRC_Msk (0xc0UL) /*!< CLKSRC (Bitfield-Mask: 0x03) */ +#define I2Cx_MCR0_DBGEN_Pos (3UL) /*!< DBGEN (Bit 3) */ +#define I2Cx_MCR0_DBGEN_Msk (0x8UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR0_SLEEPEN_Pos (2UL) /*!< SLEEPEN (Bit 2) */ +#define I2Cx_MCR0_SLEEPEN_Msk (0x4UL) /*!< SLEEPEN (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR0_RESET_Pos (1UL) /*!< RESET (Bit 1) */ +#define I2Cx_MCR0_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR0_MEN_Pos (0UL) /*!< MEN (Bit 0) */ +#define I2Cx_MCR0_MEN_Msk (0x1UL) /*!< MEN (Bitfield-Mask: 0x01) */ +/* ========================================================= MCR1 ========================================================== */ +#define I2Cx_MCR1_RDMO_Pos (9UL) /*!< RDMO (Bit 9) */ +#define I2Cx_MCR1_RDMO_Msk (0x200UL) /*!< RDMO (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR1_CIRFIFO_Pos (8UL) /*!< CIRFIFO (Bit 8) */ +#define I2Cx_MCR1_CIRFIFO_Msk (0x100UL) /*!< CIRFIFO (Bitfield-Mask: 0x01) */ +/* ========================================================= MCR2 ========================================================== */ +#define I2Cx_MCR2_PINCFG_Pos (24UL) /*!< PINCFG (Bit 24) */ +#define I2Cx_MCR2_PINCFG_Msk (0x7000000UL) /*!< PINCFG (Bitfield-Mask: 0x07) */ +#define I2Cx_MCR2_MATCFG_Pos (16UL) /*!< MATCFG (Bit 16) */ +#define I2Cx_MCR2_MATCFG_Msk (0x70000UL) /*!< MATCFG (Bitfield-Mask: 0x07) */ +#define I2Cx_MCR2_TRGSEL_Pos (15UL) /*!< TRGSEL (Bit 15) */ +#define I2Cx_MCR2_TRGSEL_Msk (0x8000UL) /*!< TRGSEL (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR2_TIMECFG_Pos (10UL) /*!< TIMECFG (Bit 10) */ +#define I2Cx_MCR2_TIMECFG_Msk (0x400UL) /*!< TIMECFG (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR2_IGNACK_Pos (9UL) /*!< IGNACK (Bit 9) */ +#define I2Cx_MCR2_IGNACK_Msk (0x200UL) /*!< IGNACK (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR2_AUTOSTOP_Pos (8UL) /*!< AUTOSTOP (Bit 8) */ +#define I2Cx_MCR2_AUTOSTOP_Msk (0x100UL) /*!< AUTOSTOP (Bitfield-Mask: 0x01) */ +#define I2Cx_MCR2_PRESCALE_Pos (0UL) /*!< PRESCALE (Bit 0) */ +#define I2Cx_MCR2_PRESCALE_Msk (0x7UL) /*!< PRESCALE (Bitfield-Mask: 0x07) */ +/* ========================================================= MCR3 ========================================================== */ +#define I2Cx_MCR3_FLTSDA_Pos (24UL) /*!< FLTSDA (Bit 24) */ +#define I2Cx_MCR3_FLTSDA_Msk (0xf000000UL) /*!< FLTSDA (Bitfield-Mask: 0x0f) */ +#define I2Cx_MCR3_FLTSCL_Pos (16UL) /*!< FLTSCL (Bit 16) */ +#define I2Cx_MCR3_FLTSCL_Msk (0xf0000UL) /*!< FLTSCL (Bitfield-Mask: 0x0f) */ +#define I2Cx_MCR3_BUSIDLE_Pos (0UL) /*!< BUSIDLE (Bit 0) */ +#define I2Cx_MCR3_BUSIDLE_Msk (0xfffUL) /*!< BUSIDLE (Bitfield-Mask: 0xfff) */ +/* ========================================================= MCR4 ========================================================== */ +#define I2Cx_MCR4_PINLOW_Pos (8UL) /*!< PINLOW (Bit 8) */ +#define I2Cx_MCR4_PINLOW_Msk (0xfff00UL) /*!< PINLOW (Bitfield-Mask: 0xfff) */ +/* ========================================================= MCCR ========================================================= */ +#define I2Cx_MCCR_DATAVD_Pos (24UL) /*!< DATAVD (Bit 24) */ +#define I2Cx_MCCR_DATAVD_Msk (0x3f000000UL) /*!< DATAVD (Bitfield-Mask: 0x3f) */ +#define I2Cx_MCCR_SETHOLD_Pos (16UL) /*!< SETHOLD (Bit 16) */ +#define I2Cx_MCCR_SETHOLD_Msk (0x3f0000UL) /*!< SETHOLD (Bitfield-Mask: 0x3f) */ +#define I2Cx_MCCR_CLKHI_Pos (8UL) /*!< CLKHI (Bit 8) */ +#define I2Cx_MCCR_CLKHI_Msk (0x3f00UL) /*!< CLKHI (Bitfield-Mask: 0x3f) */ +#define I2Cx_MCCR_CLKLO_Pos (0UL) /*!< CLKLO (Bit 0) */ +#define I2Cx_MCCR_CLKLO_Msk (0x3fUL) /*!< CLKLO (Bitfield-Mask: 0x3f) */ +/* ======================================================== MMATCH ========================================================= */ +#define I2Cx_MMATCH_MATCH1_Pos (16UL) /*!< MATCH1 (Bit 16) */ +#define I2Cx_MMATCH_MATCH1_Msk (0xff0000UL) /*!< MATCH1 (Bitfield-Mask: 0xff) */ +#define I2Cx_MMATCH_MATCH0_Pos (0UL) /*!< MATCH0 (Bit 0) */ +#define I2Cx_MMATCH_MATCH0_Msk (0xffUL) /*!< MATCH0 (Bitfield-Mask: 0xff) */ +/* ======================================================== MFIFOCR ======================================================== */ +#define I2Cx_MFIFOCR_RXWATER_Pos (16UL) /*!< RXWATER (Bit 16) */ +#define I2Cx_MFIFOCR_RXWATER_Msk (0x10000UL) /*!< RXWATER (Bitfield-Mask: 0x01) */ +#define I2Cx_MFIFOCR_TXWATER_Pos (0UL) /*!< TXWATER (Bit 0) */ +#define I2Cx_MFIFOCR_TXWATER_Msk (0x1UL) /*!< TXWATER (Bitfield-Mask: 0x01) */ +/* ======================================================== MFIFOSR ======================================================== */ +#define I2Cx_MFIFOSR_RXCNT_Pos (16UL) /*!< RXCNT (Bit 16) */ +#define I2Cx_MFIFOSR_RXCNT_Msk (0x10000UL) /*!< RXCNT (Bitfield-Mask: 0x01) */ +#define I2Cx_MFIFOSR_TXCNT_Pos (0UL) /*!< TXCNT (Bit 0) */ +#define I2Cx_MFIFOSR_TXCNT_Msk (0x1UL) /*!< TXCNT (Bitfield-Mask: 0x01) */ +/* ========================================================= MTDR ========================================================== */ +#define I2Cx_MTDR_CMD_Pos (8UL) /*!< CMD (Bit 8) */ +#define I2Cx_MTDR_CMD_Msk (0x700UL) /*!< CMD (Bitfield-Mask: 0x07) */ +#define I2Cx_MTDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define I2Cx_MTDR_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================= MRDR ========================================================== */ +#define I2Cx_MRDR_EMPTY_Pos (14UL) /*!< EMPTY (Bit 14) */ +#define I2Cx_MRDR_EMPTY_Msk (0x4000UL) /*!< EMPTY (Bitfield-Mask: 0x01) */ +#define I2Cx_MRDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define I2Cx_MRDR_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================= MDER ========================================================== */ +#define I2Cx_MDER_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define I2Cx_MDER_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define I2Cx_MDER_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define I2Cx_MDER_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ +#define I2Cx_MIER_MATCH_Pos (14UL) /*!< MATCH (Bit 14) */ +#define I2Cx_MIER_MATCH_Msk (0x4000UL) /*!< MATCH (Bitfield-Mask: 0x01) */ +#define I2Cx_MIER_PINLOW_Pos (13UL) /*!< PINLOW (Bit 13) */ +#define I2Cx_MIER_PINLOW_Msk (0x2000UL) /*!< PINLOW (Bitfield-Mask: 0x01) */ +#define I2Cx_MIER_FIFO_Pos (12UL) /*!< FIFO (Bit 12) */ +#define I2Cx_MIER_FIFO_Msk (0x1000UL) /*!< FIFO (Bitfield-Mask: 0x01) */ +#define I2Cx_MIER_ARBI_Pos (11UL) /*!< ARBI (Bit 11) */ +#define I2Cx_MIER_ARBI_Msk (0x800UL) /*!< ARBI (Bitfield-Mask: 0x01) */ +#define I2Cx_MIER_NACK_Pos (10UL) /*!< NACK (Bit 10) */ +#define I2Cx_MIER_NACK_Msk (0x400UL) /*!< NACK (Bitfield-Mask: 0x01) */ +#define I2Cx_MIER_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define I2Cx_MIER_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define I2Cx_MIER_PACKET_Pos (8UL) /*!< PACKET (Bit 8) */ +#define I2Cx_MIER_PACKET_Msk (0x100UL) /*!< PACKET (Bitfield-Mask: 0x01) */ +#define I2Cx_MIER_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define I2Cx_MIER_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define I2Cx_MIER_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define I2Cx_MIER_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================= MISR ========================================================== */ +#define I2Cx_MISR_BUSBUSY_Pos (25UL) /*!< BUSBUSY (Bit 25) */ +#define I2Cx_MISR_BUSBUSY_Msk (0x2000000UL) /*!< BUSBUSY (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_MSTBUSY_Pos (24UL) /*!< MSTBUSY (Bit 24) */ +#define I2Cx_MISR_MSTBUSY_Msk (0x1000000UL) /*!< MSTBUSY (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_MATCH_Pos (14UL) /*!< MATCH (Bit 14) */ +#define I2Cx_MISR_MATCH_Msk (0x4000UL) /*!< MATCH (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_PINLOW_Pos (13UL) /*!< PINLOW (Bit 13) */ +#define I2Cx_MISR_PINLOW_Msk (0x2000UL) /*!< PINLOW (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_FIFO_Pos (12UL) /*!< FIFO (Bit 12) */ +#define I2Cx_MISR_FIFO_Msk (0x1000UL) /*!< FIFO (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_ARBI_Pos (11UL) /*!< ARBI (Bit 11) */ +#define I2Cx_MISR_ARBI_Msk (0x800UL) /*!< ARBI (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_NACK_Pos (10UL) /*!< NACK (Bit 10) */ +#define I2Cx_MISR_NACK_Msk (0x400UL) /*!< NACK (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define I2Cx_MISR_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_PACKET_Pos (8UL) /*!< PACKET (Bit 8) */ +#define I2Cx_MISR_PACKET_Msk (0x100UL) /*!< PACKET (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define I2Cx_MISR_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define I2Cx_MISR_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define I2Cx_MISR_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================= MICR ========================================================== */ +#define I2Cx_MICR_MATCH_Pos (14UL) /*!< MATCH (Bit 14) */ +#define I2Cx_MICR_MATCH_Msk (0x4000UL) /*!< MATCH (Bitfield-Mask: 0x01) */ +#define I2Cx_MICR_PINLOW_Pos (13UL) /*!< PINLOW (Bit 13) */ +#define I2Cx_MICR_PINLOW_Msk (0x2000UL) /*!< PINLOW (Bitfield-Mask: 0x01) */ +#define I2Cx_MICR_FIFO_Pos (12UL) /*!< FIFO (Bit 12) */ +#define I2Cx_MICR_FIFO_Msk (0x1000UL) /*!< FIFO (Bitfield-Mask: 0x01) */ +#define I2Cx_MICR_ARBI_Pos (11UL) /*!< ARBI (Bit 11) */ +#define I2Cx_MICR_ARBI_Msk (0x800UL) /*!< ARBI (Bitfield-Mask: 0x01) */ +#define I2Cx_MICR_NACK_Pos (10UL) /*!< NACK (Bit 10) */ +#define I2Cx_MICR_NACK_Msk (0x400UL) /*!< NACK (Bitfield-Mask: 0x01) */ +#define I2Cx_MICR_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define I2Cx_MICR_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define I2Cx_MICR_PACKET_Pos (8UL) /*!< PACKET (Bit 8) */ +#define I2Cx_MICR_PACKET_Msk (0x100UL) /*!< PACKET (Bitfield-Mask: 0x01) */ +/* ========================================================= SCR0 ========================================================== */ +#define I2Cx_SCR0_RXFIFORST_Pos (9UL) /*!< RXFIFORST (Bit 9) */ +#define I2Cx_SCR0_RXFIFORST_Msk (0x200UL) /*!< RXFIFORST (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR0_TXFIFORST_Pos (8UL) /*!< TXFIFORST (Bit 8) */ +#define I2Cx_SCR0_TXFIFORST_Msk (0x100UL) /*!< TXFIFORST (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR0_CLKSRC_Pos (6UL) /*!< CLKSRC (Bit 6) */ +#define I2Cx_SCR0_CLKSRC_Msk (0xc0UL) /*!< CLKSRC (Bitfield-Mask: 0x03) */ +#define I2Cx_SCR0_FLTEN_Pos (4UL) /*!< FLTEN (Bit 4) */ +#define I2Cx_SCR0_FLTEN_Msk (0x10UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR0_RESET_Pos (1UL) /*!< RESET (Bit 1) */ +#define I2Cx_SCR0_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR0_SEN_Pos (0UL) /*!< SEN (Bit 0) */ +#define I2Cx_SCR0_SEN_Msk (0x1UL) /*!< SEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SCR1 ========================================================== */ +#define I2Cx_SCR1_ADDRCFG_Pos (16UL) /*!< ADDRCFG (Bit 16) */ +#define I2Cx_SCR1_ADDRCFG_Msk (0x70000UL) /*!< ADDRCFG (Bitfield-Mask: 0x07) */ +#define I2Cx_SCR1_TRGSEL_Pos (15UL) /*!< TRGSEL (Bit 15) */ +#define I2Cx_SCR1_TRGSEL_Msk (0x8000UL) /*!< TRGSEL (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_IGNACK_Pos (12UL) /*!< IGNACK (Bit 12) */ +#define I2Cx_SCR1_IGNACK_Msk (0x1000UL) /*!< IGNACK (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_RXCFG_Pos (11UL) /*!< RXCFG (Bit 11) */ +#define I2Cx_SCR1_RXCFG_Msk (0x800UL) /*!< RXCFG (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_TXCFG_Pos (10UL) /*!< TXCFG (Bit 10) */ +#define I2Cx_SCR1_TXCFG_Msk (0x400UL) /*!< TXCFG (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_ALERTEN_Pos (9UL) /*!< ALERTEN (Bit 9) */ +#define I2Cx_SCR1_ALERTEN_Msk (0x200UL) /*!< ALERTEN (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_GCEN_Pos (8UL) /*!< GCEN (Bit 8) */ +#define I2Cx_SCR1_GCEN_Msk (0x100UL) /*!< GCEN (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_ACKSTALL_Pos (3UL) /*!< ACKSTALL (Bit 3) */ +#define I2Cx_SCR1_ACKSTALL_Msk (0x8UL) /*!< ACKSTALL (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_TXSTALL_Pos (2UL) /*!< TXSTALL (Bit 2) */ +#define I2Cx_SCR1_TXSTALL_Msk (0x4UL) /*!< TXSTALL (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_RXSTALL_Pos (1UL) /*!< RXSTALL (Bit 1) */ +#define I2Cx_SCR1_RXSTALL_Msk (0x2UL) /*!< RXSTALL (Bitfield-Mask: 0x01) */ +#define I2Cx_SCR1_ADRSTALL_Pos (0UL) /*!< ADRSTALL (Bit 0) */ +#define I2Cx_SCR1_ADRSTALL_Msk (0x1UL) /*!< ADRSTALL (Bitfield-Mask: 0x01) */ +/* ========================================================= SCR2 ========================================================== */ +#define I2Cx_SCR2_PINCFG_Pos (24UL) /*!< PINCFG (Bit 24) */ +#define I2Cx_SCR2_PINCFG_Msk (0x7000000UL) /*!< PINCFG (Bitfield-Mask: 0x07) */ +/* ========================================================= SCR3 ========================================================== */ +#define I2Cx_SCR3_FLTSDA_Pos (24UL) /*!< FLTSDA (Bit 24) */ +#define I2Cx_SCR3_FLTSDA_Msk (0xf000000UL) /*!< FLTSDA (Bitfield-Mask: 0x0f) */ +#define I2Cx_SCR3_FLTSCL_Pos (16UL) /*!< FLTSCL (Bit 16) */ +#define I2Cx_SCR3_FLTSCL_Msk (0xf0000UL) /*!< FLTSCL (Bitfield-Mask: 0x0f) */ +#define I2Cx_SCR3_DATAVD_Pos (8UL) /*!< DATAVD (Bit 8) */ +#define I2Cx_SCR3_DATAVD_Msk (0x3f00UL) /*!< DATAVD (Bitfield-Mask: 0x3f) */ +#define I2Cx_SCR3_CLKHOLD_Pos (0UL) /*!< CLKHOLD (Bit 0) */ +#define I2Cx_SCR3_CLKHOLD_Msk (0xfUL) /*!< CLKHOLD (Bitfield-Mask: 0x0f) */ +/* ========================================================= SAMR ========================================================== */ +#define I2Cx_SAMR_ADDR1_Pos (17UL) /*!< ADDR1 (Bit 17) */ +#define I2Cx_SAMR_ADDR1_Msk (0x7fe0000UL) /*!< ADDR1 (Bitfield-Mask: 0x3ff) */ +#define I2Cx_SAMR_ADDR0_Pos (1UL) /*!< ADDR0 (Bit 1) */ +#define I2Cx_SAMR_ADDR0_Msk (0x7feUL) /*!< ADDR0 (Bitfield-Mask: 0x3ff) */ +/* ========================================================= STAR ========================================================== */ +#define I2Cx_STAR_TXNACK_Pos (0UL) /*!< TXNACK (Bit 0) */ +#define I2Cx_STAR_TXNACK_Msk (0x1UL) /*!< TXNACK (Bitfield-Mask: 0x01) */ +/* ========================================================= STDR ========================================================== */ +#define I2Cx_STDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define I2Cx_STDR_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================= SRDR ========================================================== */ +#define I2Cx_SRDR_SOF_Pos (15UL) /*!< SOF (Bit 15) */ +#define I2Cx_SRDR_SOF_Msk (0x8000UL) /*!< SOF (Bitfield-Mask: 0x01) */ +#define I2Cx_SRDR_RXEMPTY_Pos (14UL) /*!< RXEMPTY (Bit 14) */ +#define I2Cx_SRDR_RXEMPTY_Msk (0x4000UL) /*!< RXEMPTY (Bitfield-Mask: 0x01) */ +#define I2Cx_SRDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define I2Cx_SRDR_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================= SASR ========================================================== */ +#define I2Cx_SASR_ANV_Pos (14UL) /*!< ANV (Bit 14) */ +#define I2Cx_SASR_ANV_Msk (0x4000UL) /*!< ANV (Bitfield-Mask: 0x01) */ +#define I2Cx_SASR_RADDR_Pos (0UL) /*!< RADDR (Bit 0) */ +#define I2Cx_SASR_RADDR_Msk (0x7ffUL) /*!< RADDR (Bitfield-Mask: 0x7ff) */ +/* ========================================================= SDER ========================================================== */ +#define I2Cx_SDER_ADDR_Pos (2UL) /*!< ADDR (Bit 2) */ +#define I2Cx_SDER_ADDR_Msk (0x4UL) /*!< ADDR (Bitfield-Mask: 0x01) */ +#define I2Cx_SDER_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define I2Cx_SDER_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define I2Cx_SDER_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define I2Cx_SDER_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================= SIER ========================================================== */ +#define I2Cx_SIER_ALERT_Pos (15UL) /*!< ALERT (Bit 15) */ +#define I2Cx_SIER_ALERT_Msk (0x8000UL) /*!< ALERT (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_GC_Pos (14UL) /*!< GC (Bit 14) */ +#define I2Cx_SIER_GC_Msk (0x4000UL) /*!< GC (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_AM1_Pos (13UL) /*!< AM1 (Bit 13) */ +#define I2Cx_SIER_AM1_Msk (0x2000UL) /*!< AM1 (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_AM0_Pos (12UL) /*!< AM0 (Bit 12) */ +#define I2Cx_SIER_AM0_Msk (0x1000UL) /*!< AM0 (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_FIFO_Pos (11UL) /*!< FIFO (Bit 11) */ +#define I2Cx_SIER_FIFO_Msk (0x800UL) /*!< FIFO (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_BIT_Pos (10UL) /*!< BIT (Bit 10) */ +#define I2Cx_SIER_BIT_Msk (0x400UL) /*!< BIT (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define I2Cx_SIER_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_RESTART_Pos (8UL) /*!< RESTART (Bit 8) */ +#define I2Cx_SIER_RESTART_Msk (0x100UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_TACK_Pos (3UL) /*!< TACK (Bit 3) */ +#define I2Cx_SIER_TACK_Msk (0x8UL) /*!< TACK (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_ADDR_Pos (2UL) /*!< ADDR (Bit 2) */ +#define I2Cx_SIER_ADDR_Msk (0x4UL) /*!< ADDR (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define I2Cx_SIER_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define I2Cx_SIER_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define I2Cx_SIER_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ +#define I2Cx_SISR_BUSBUSY_Pos (25UL) /*!< BUSBUSY (Bit 25) */ +#define I2Cx_SISR_BUSBUSY_Msk (0x2000000UL) /*!< BUSBUSY (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_SLVBUSY_Pos (24UL) /*!< SLVBUSY (Bit 24) */ +#define I2Cx_SISR_SLVBUSY_Msk (0x1000000UL) /*!< SLVBUSY (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_ALERT_Pos (15UL) /*!< ALERT (Bit 15) */ +#define I2Cx_SISR_ALERT_Msk (0x8000UL) /*!< ALERT (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_GC_Pos (14UL) /*!< GC (Bit 14) */ +#define I2Cx_SISR_GC_Msk (0x4000UL) /*!< GC (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_AM1_Pos (13UL) /*!< AM1 (Bit 13) */ +#define I2Cx_SISR_AM1_Msk (0x2000UL) /*!< AM1 (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_AM0_Pos (12UL) /*!< AM0 (Bit 12) */ +#define I2Cx_SISR_AM0_Msk (0x1000UL) /*!< AM0 (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_FIFO_Pos (11UL) /*!< FIFO (Bit 11) */ +#define I2Cx_SISR_FIFO_Msk (0x800UL) /*!< FIFO (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_BIT_Pos (10UL) /*!< BIT (Bit 10) */ +#define I2Cx_SISR_BIT_Msk (0x400UL) /*!< BIT (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define I2Cx_SISR_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_RESTART_Pos (8UL) /*!< RESTART (Bit 8) */ +#define I2Cx_SISR_RESTART_Msk (0x100UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_TACK_Pos (3UL) /*!< TACK (Bit 3) */ +#define I2Cx_SISR_TACK_Msk (0x8UL) /*!< TACK (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_ADDR_Pos (2UL) /*!< ADDR (Bit 2) */ +#define I2Cx_SISR_ADDR_Msk (0x4UL) /*!< ADDR (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define I2Cx_SISR_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define I2Cx_SISR_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define I2Cx_SISR_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================= SICR ========================================================== */ +#define I2Cx_SICR_FIFO_Pos (11UL) /*!< FIFO (Bit 11) */ +#define I2Cx_SICR_FIFO_Msk (0x800UL) /*!< FIFO (Bitfield-Mask: 0x01) */ +#define I2Cx_SICR_BIT_Pos (10UL) /*!< BIT (Bit 10) */ +#define I2Cx_SICR_BIT_Msk (0x400UL) /*!< BIT (Bitfield-Mask: 0x01) */ +#define I2Cx_SICR_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define I2Cx_SICR_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define I2Cx_SICR_RESTART_Pos (8UL) /*!< RESTART (Bit 8) */ +#define I2Cx_SICR_RESTART_Msk (0x100UL) /*!< RESTART (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ IRMOD ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define IRMOD_CR_INV_Pos (5UL) /*!< INV (Bit 5) */ +#define IRMOD_CR_INV_Msk (0x20UL) /*!< INV (Bitfield-Mask: 0x01) */ +#define IRMOD_CR_IRSW_Pos (4UL) /*!< IRSW (Bit 4) */ +#define IRMOD_CR_IRSW_Msk (0x10UL) /*!< IRSW (Bitfield-Mask: 0x01) */ +#define IRMOD_CR_MOD_Pos (0UL) /*!< MOD (Bit 0) */ +#define IRMOD_CR_MOD_Msk (0xfUL) /*!< MOD (Bitfield-Mask: 0x0f) */ + + +/* =========================================================================================================================== */ +/* ================ IWDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== KR =========================================================== */ +#define IWDT_KR_KR_Pos (0UL) /*!< KR (Bit 0) */ +#define IWDT_KR_KR_Msk (0xffffUL) /*!< KR (Bitfield-Mask: 0xffff) */ +/* ========================================================== CR =========================================================== */ +#define IWDT_CR_PAUSE_Pos (5UL) /*!< PAUSE (Bit 5) */ +#define IWDT_CR_PAUSE_Msk (0x20UL) /*!< PAUSE (Bitfield-Mask: 0x01) */ +#define IWDT_CR_IE_Pos (4UL) /*!< IE (Bit 4) */ +#define IWDT_CR_IE_Msk (0x10UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define IWDT_CR_ACTION_Pos (3UL) /*!< ACTION (Bit 3) */ +#define IWDT_CR_ACTION_Msk (0x8UL) /*!< ACTION (Bitfield-Mask: 0x01) */ +#define IWDT_CR_PRS_Pos (0UL) /*!< PRS (Bit 0) */ +#define IWDT_CR_PRS_Msk (0x7UL) /*!< PRS (Bitfield-Mask: 0x07) */ +/* ========================================================== ARR ========================================================== */ +#define IWDT_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define IWDT_ARR_ARR_Msk (0xfffUL) /*!< ARR (Bitfield-Mask: 0xfff) */ +/* ========================================================== CNT ========================================================== */ +#define IWDT_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define IWDT_CNT_CNT_Msk (0xfffUL) /*!< CNT (Bitfield-Mask: 0xfff) */ +/* ========================================================= WINR ========================================================== */ +#define IWDT_WINR_WINR_Pos (0UL) /*!< WINR (Bit 0) */ +#define IWDT_WINR_WINR_Msk (0xfffUL) /*!< WINR (Bitfield-Mask: 0xfff) */ +/* ========================================================== SR =========================================================== */ +#define IWDT_SR_RELOAD_Pos (5UL) /*!< RELOAD (Bit 5) */ +#define IWDT_SR_RELOAD_Msk (0x20UL) /*!< RELOAD (Bitfield-Mask: 0x01) */ +#define IWDT_SR_RUN_Pos (4UL) /*!< RUN (Bit 4) */ +#define IWDT_SR_RUN_Msk (0x10UL) /*!< RUN (Bitfield-Mask: 0x01) */ +#define IWDT_SR_OV_Pos (3UL) /*!< OV (Bit 3) */ +#define IWDT_SR_OV_Msk (0x8UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define IWDT_SR_WINRF_Pos (2UL) /*!< WINRF (Bit 2) */ +#define IWDT_SR_WINRF_Msk (0x4UL) /*!< WINRF (Bitfield-Mask: 0x01) */ +#define IWDT_SR_ARRF_Pos (1UL) /*!< ARRF (Bit 1) */ +#define IWDT_SR_ARRF_Msk (0x2UL) /*!< ARRF (Bitfield-Mask: 0x01) */ +#define IWDT_SR_CRF_Pos (0UL) /*!< CRF (Bit 0) */ +#define IWDT_SR_CRF_Msk (0x1UL) /*!< CRF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LPTIM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CFGR ========================================================== */ +#define LPTIM_CFGR_ICLKSRC_Pos (25UL) /*!< ICLKSRC (Bit 25) */ +#define LPTIM_CFGR_ICLKSRC_Msk (0x6000000UL) /*!< ICLKSRC (Bitfield-Mask: 0x03) */ +#define LPTIM_CFGR_ENC_Pos (24UL) /*!< ENC (Bit 24) */ +#define LPTIM_CFGR_ENC_Msk (0x1000000UL) /*!< ENC (Bitfield-Mask: 0x01) */ +#define LPTIM_CFGR_COUNTMD_Pos (23UL) /*!< COUNTMD (Bit 23) */ +#define LPTIM_CFGR_COUNTMD_Msk (0x800000UL) /*!< COUNTMD (Bitfield-Mask: 0x01) */ +#define LPTIM_CFGR_PRELOAD_Pos (22UL) /*!< PRELOAD (Bit 22) */ +#define LPTIM_CFGR_PRELOAD_Msk (0x400000UL) /*!< PRELOAD (Bitfield-Mask: 0x01) */ +#define LPTIM_CFGR_WAVPOL_Pos (21UL) /*!< WAVPOL (Bit 21) */ +#define LPTIM_CFGR_WAVPOL_Msk (0x200000UL) /*!< WAVPOL (Bitfield-Mask: 0x01) */ +#define LPTIM_CFGR_WAVE_Pos (20UL) /*!< WAVE (Bit 20) */ +#define LPTIM_CFGR_WAVE_Msk (0x100000UL) /*!< WAVE (Bitfield-Mask: 0x01) */ +#define LPTIM_CFGR_TIMOUT_Pos (19UL) /*!< TIMOUT (Bit 19) */ +#define LPTIM_CFGR_TIMOUT_Msk (0x80000UL) /*!< TIMOUT (Bitfield-Mask: 0x01) */ +#define LPTIM_CFGR_TRIGEN_Pos (17UL) /*!< TRIGEN (Bit 17) */ +#define LPTIM_CFGR_TRIGEN_Msk (0x60000UL) /*!< TRIGEN (Bitfield-Mask: 0x03) */ +#define LPTIM_CFGR_TRIGSEL_Pos (12UL) /*!< TRIGSEL (Bit 12) */ +#define LPTIM_CFGR_TRIGSEL_Msk (0xf000UL) /*!< TRIGSEL (Bitfield-Mask: 0x0f) */ +#define LPTIM_CFGR_PRS_Pos (9UL) /*!< PRS (Bit 9) */ +#define LPTIM_CFGR_PRS_Msk (0xe00UL) /*!< PRS (Bitfield-Mask: 0x07) */ +#define LPTIM_CFGR_TRIGFLT_Pos (6UL) /*!< TRIGFLT (Bit 6) */ +#define LPTIM_CFGR_TRIGFLT_Msk (0xc0UL) /*!< TRIGFLT (Bitfield-Mask: 0x03) */ +#define LPTIM_CFGR_CHFLT_Pos (3UL) /*!< CHFLT (Bit 3) */ +#define LPTIM_CFGR_CHFLT_Msk (0x18UL) /*!< CHFLT (Bitfield-Mask: 0x03) */ +#define LPTIM_CFGR_ENCMD_CKPOL_Pos (1UL) /*!< ENCMD_CKPOL (Bit 1) */ +#define LPTIM_CFGR_ENCMD_CKPOL_Msk (0x6UL) /*!< ENCMD_CKPOL (Bitfield-Mask: 0x03) */ +#define LPTIM_CFGR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ +#define LPTIM_CFGR_CKSEL_Msk (0x1UL) /*!< CKSEL (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ +#define LPTIM_CR0_ARST_Pos (4UL) /*!< ARST (Bit 4) */ +#define LPTIM_CR0_ARST_Msk (0x10UL) /*!< ARST (Bitfield-Mask: 0x01) */ +#define LPTIM_CR0_SRST_Pos (3UL) /*!< SRST (Bit 3) */ +#define LPTIM_CR0_SRST_Msk (0x8UL) /*!< SRST (Bitfield-Mask: 0x01) */ +#define LPTIM_CR0_CNTSTART_Pos (2UL) /*!< CNTSTART (Bit 2) */ +#define LPTIM_CR0_CNTSTART_Msk (0x4UL) /*!< CNTSTART (Bitfield-Mask: 0x01) */ +#define LPTIM_CR0_SNGSTART_Pos (1UL) /*!< SNGSTART (Bit 1) */ +#define LPTIM_CR0_SNGSTART_Msk (0x2UL) /*!< SNGSTART (Bitfield-Mask: 0x01) */ +#define LPTIM_CR0_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define LPTIM_CR0_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== ARR ========================================================== */ +#define LPTIM_ARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define LPTIM_ARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ========================================================== CNT ========================================================== */ +#define LPTIM_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define LPTIM_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== CMP ========================================================== */ +#define LPTIM_CMP_CMP_Pos (0UL) /*!< CMP (Bit 0) */ +#define LPTIM_CMP_CMP_Msk (0xffffUL) /*!< CMP (Bitfield-Mask: 0xffff) */ +/* ========================================================== IER ========================================================== */ +#define LPTIM_IER_DOWN_Pos (6UL) /*!< DOWN (Bit 6) */ +#define LPTIM_IER_DOWN_Msk (0x40UL) /*!< DOWN (Bitfield-Mask: 0x01) */ +#define LPTIM_IER_UP_Pos (5UL) /*!< UP (Bit 5) */ +#define LPTIM_IER_UP_Msk (0x20UL) /*!< UP (Bitfield-Mask: 0x01) */ +#define LPTIM_IER_ARROK_Pos (4UL) /*!< ARROK (Bit 4) */ +#define LPTIM_IER_ARROK_Msk (0x10UL) /*!< ARROK (Bitfield-Mask: 0x01) */ +#define LPTIM_IER_CMPOK_Pos (3UL) /*!< CMPOK (Bit 3) */ +#define LPTIM_IER_CMPOK_Msk (0x8UL) /*!< CMPOK (Bitfield-Mask: 0x01) */ +#define LPTIM_IER_EXTTRIG_Pos (2UL) /*!< EXTTRIG (Bit 2) */ +#define LPTIM_IER_EXTTRIG_Msk (0x4UL) /*!< EXTTRIG (Bitfield-Mask: 0x01) */ +#define LPTIM_IER_ARRM_Pos (1UL) /*!< ARRM (Bit 1) */ +#define LPTIM_IER_ARRM_Msk (0x2UL) /*!< ARRM (Bitfield-Mask: 0x01) */ +#define LPTIM_IER_CMPM_Pos (0UL) /*!< CMPM (Bit 0) */ +#define LPTIM_IER_CMPM_Msk (0x1UL) /*!< CMPM (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define LPTIM_ISR_DIR_Pos (7UL) /*!< DIR (Bit 7) */ +#define LPTIM_ISR_DIR_Msk (0x180UL) /*!< DIR (Bitfield-Mask: 0x03) */ +#define LPTIM_ISR_DOWN_Pos (6UL) /*!< DOWN (Bit 6) */ +#define LPTIM_ISR_DOWN_Msk (0x40UL) /*!< DOWN (Bitfield-Mask: 0x01) */ +#define LPTIM_ISR_UP_Pos (5UL) /*!< UP (Bit 5) */ +#define LPTIM_ISR_UP_Msk (0x20UL) /*!< UP (Bitfield-Mask: 0x01) */ +#define LPTIM_ISR_ARROK_Pos (4UL) /*!< ARROK (Bit 4) */ +#define LPTIM_ISR_ARROK_Msk (0x10UL) /*!< ARROK (Bitfield-Mask: 0x01) */ +#define LPTIM_ISR_CMPOK_Pos (3UL) /*!< CMPOK (Bit 3) */ +#define LPTIM_ISR_CMPOK_Msk (0x8UL) /*!< CMPOK (Bitfield-Mask: 0x01) */ +#define LPTIM_ISR_EXTTRIG_Pos (2UL) /*!< EXTTRIG (Bit 2) */ +#define LPTIM_ISR_EXTTRIG_Msk (0x4UL) /*!< EXTTRIG (Bitfield-Mask: 0x01) */ +#define LPTIM_ISR_ARRM_Pos (1UL) /*!< ARRM (Bit 1) */ +#define LPTIM_ISR_ARRM_Msk (0x2UL) /*!< ARRM (Bitfield-Mask: 0x01) */ +#define LPTIM_ISR_CMPM_Pos (0UL) /*!< CMPM (Bit 0) */ +#define LPTIM_ISR_CMPM_Msk (0x1UL) /*!< CMPM (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define LPTIM_ICR_DOWN_Pos (6UL) /*!< DOWN (Bit 6) */ +#define LPTIM_ICR_DOWN_Msk (0x40UL) /*!< DOWN (Bitfield-Mask: 0x01) */ +#define LPTIM_ICR_UP_Pos (5UL) /*!< UP (Bit 5) */ +#define LPTIM_ICR_UP_Msk (0x20UL) /*!< UP (Bitfield-Mask: 0x01) */ +#define LPTIM_ICR_ARROK_Pos (4UL) /*!< ARROK (Bit 4) */ +#define LPTIM_ICR_ARROK_Msk (0x10UL) /*!< ARROK (Bitfield-Mask: 0x01) */ +#define LPTIM_ICR_CMPOK_Pos (3UL) /*!< CMPOK (Bit 3) */ +#define LPTIM_ICR_CMPOK_Msk (0x8UL) /*!< CMPOK (Bitfield-Mask: 0x01) */ +#define LPTIM_ICR_EXTTRIG_Pos (2UL) /*!< EXTTRIG (Bit 2) */ +#define LPTIM_ICR_EXTTRIG_Msk (0x4UL) /*!< EXTTRIG (Bitfield-Mask: 0x01) */ +#define LPTIM_ICR_ARRM_Pos (1UL) /*!< ARRM (Bit 1) */ +#define LPTIM_ICR_ARRM_Msk (0x2UL) /*!< ARRM (Bitfield-Mask: 0x01) */ +#define LPTIM_ICR_CMPM_Pos (0UL) /*!< CMPM (Bit 0) */ +#define LPTIM_ICR_CMPM_Msk (0x1UL) /*!< CMPM (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ +#define LPTIM_CR1_CH2SRC_Pos (3UL) /*!< CH2SRC (Bit 3) */ +#define LPTIM_CR1_CH2SRC_Msk (0x38UL) /*!< CH2SRC (Bitfield-Mask: 0x07) */ +#define LPTIM_CR1_CH1SRC_Pos (0UL) /*!< CH1SRC (Bit 0) */ +#define LPTIM_CR1_CH1SRC_Msk (0x7UL) /*!< CH1SRC (Bitfield-Mask: 0x07) */ + + +/* =========================================================================================================================== */ +/* ================ UART ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define UARTx_CR1_SYNC_Pos (14UL) /*!< SYNC (Bit 14) */ +#define UARTx_CR1_SYNC_Msk (0x4000UL) /*!< SYNC (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_SOURCE_Pos (12UL) /*!< SOURCE (Bit 12) */ +#define UARTx_CR1_SOURCE_Msk (0x3000UL) /*!< SOURCE (Bitfield-Mask: 0x03) */ +#define UARTx_CR1_SIGNAL_Pos (11UL) /*!< SIGNAL (Bit 11) */ +#define UARTx_CR1_SIGNAL_Msk (0x800UL) /*!< SIGNAL (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_OVER_Pos (9UL) /*!< OVER (Bit 9) */ +#define UARTx_CR1_OVER_Msk (0x600UL) /*!< OVER (Bitfield-Mask: 0x03) */ +#define UARTx_CR1_START_Pos (8UL) /*!< START (Bit 8) */ +#define UARTx_CR1_START_Msk (0x100UL) /*!< START (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_MSBF_Pos (7UL) /*!< MSBF (Bit 7) */ +#define UARTx_CR1_MSBF_Msk (0x80UL) /*!< MSBF (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_CHLEN_Pos (6UL) /*!< CHLEN (Bit 6) */ +#define UARTx_CR1_CHLEN_Msk (0x40UL) /*!< CHLEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_STOP_Pos (4UL) /*!< STOP (Bit 4) */ +#define UARTx_CR1_STOP_Msk (0x30UL) /*!< STOP (Bitfield-Mask: 0x03) */ +#define UARTx_CR1_PARITYEN_Pos (3UL) /*!< PARITYEN (Bit 3) */ +#define UARTx_CR1_PARITYEN_Msk (0x8UL) /*!< PARITYEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_PARITY_Pos (2UL) /*!< PARITY (Bit 2) */ +#define UARTx_CR1_PARITY_Msk (0x4UL) /*!< PARITY (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_RXEN_Pos (1UL) /*!< RXEN (Bit 1) */ +#define UARTx_CR1_RXEN_Msk (0x2UL) /*!< RXEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR1_TXEN_Pos (0UL) /*!< TXEN (Bit 0) */ +#define UARTx_CR1_TXEN_Msk (0x1UL) /*!< TXEN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define UARTx_CR2_RXSRC_Pos (15UL) /*!< RXSRC (Bit 15) */ +#define UARTx_CR2_RXSRC_Msk (0x38000UL) /*!< RXSRC (Bitfield-Mask: 0x07) */ +#define UARTx_CR2_LOOP_Pos (14UL) /*!< LOOP (Bit 14) */ +#define UARTx_CR2_LOOP_Msk (0x4000UL) /*!< LOOP (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_ADCTX_Pos (13UL) /*!< ADCTX (Bit 13) */ +#define UARTx_CR2_ADCTX_Msk (0x2000UL) /*!< ADCTX (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_ADCRX_Pos (12UL) /*!< ADCRX (Bit 12) */ +#define UARTx_CR2_ADCRX_Msk (0x1000UL) /*!< ADCRX (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_SWAP_Pos (11UL) /*!< SWAP (Bit 11) */ +#define UARTx_CR2_SWAP_Msk (0x800UL) /*!< SWAP (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_TIMCR_Pos (8UL) /*!< TIMCR (Bit 8) */ +#define UARTx_CR2_TIMCR_Msk (0x700UL) /*!< TIMCR (Bitfield-Mask: 0x07) */ +#define UARTx_CR2_DMATX_Pos (7UL) /*!< DMATX (Bit 7) */ +#define UARTx_CR2_DMATX_Msk (0x80UL) /*!< DMATX (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_DMARX_Pos (6UL) /*!< DMARX (Bit 6) */ +#define UARTx_CR2_DMARX_Msk (0x40UL) /*!< DMARX (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_TXINV_Pos (5UL) /*!< TXINV (Bit 5) */ +#define UARTx_CR2_TXINV_Msk (0x20UL) /*!< TXINV (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_RXINV_Pos (4UL) /*!< RXINV (Bit 4) */ +#define UARTx_CR2_RXINV_Msk (0x10UL) /*!< RXINV (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_RTSEN_Pos (3UL) /*!< RTSEN (Bit 3) */ +#define UARTx_CR2_RTSEN_Msk (0x8UL) /*!< RTSEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_CTSEN_Pos (2UL) /*!< CTSEN (Bit 2) */ +#define UARTx_CR2_CTSEN_Msk (0x4UL) /*!< CTSEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_RXMATCHEN_Pos (1UL) /*!< RXMATCHEN (Bit 1) */ +#define UARTx_CR2_RXMATCHEN_Msk (0x2UL) /*!< RXMATCHEN (Bitfield-Mask: 0x01) */ +#define UARTx_CR2_ADDREN_Pos (0UL) /*!< ADDREN (Bit 0) */ +#define UARTx_CR2_ADDREN_Msk (0x1UL) /*!< ADDREN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR3 ========================================================== */ +#define UARTx_CR3_BRKL_Pos (8UL) /*!< BRKL (Bit 8) */ +#define UARTx_CR3_BRKL_Msk (0x100UL) /*!< BRKL (Bitfield-Mask: 0x01) */ +#define UARTx_CR3_LIN_Pos (7UL) /*!< LIN (Bit 7) */ +#define UARTx_CR3_LIN_Msk (0x80UL) /*!< LIN (Bitfield-Mask: 0x01) */ +#define UARTx_CR3_DETIME_Pos (2UL) /*!< DETIME (Bit 2) */ +#define UARTx_CR3_DETIME_Msk (0x7cUL) /*!< DETIME (Bitfield-Mask: 0x1f) */ +#define UARTx_CR3_DEP_Pos (1UL) /*!< DEP (Bit 1) */ +#define UARTx_CR3_DEP_Msk (0x2UL) /*!< DEP (Bitfield-Mask: 0x01) */ +#define UARTx_CR3_DEM_Pos (0UL) /*!< DEM (Bit 0) */ +#define UARTx_CR3_DEM_Msk (0x1UL) /*!< DEM (Bitfield-Mask: 0x01) */ +/* ========================================================= BRRI ========================================================== */ +#define UARTx_BRRI_BRRI_Pos (0UL) /*!< BRRI (Bit 0) */ +#define UARTx_BRRI_BRRI_Msk (0xffffUL) /*!< BRRI (Bitfield-Mask: 0xffff) */ +/* ========================================================= BRRF ========================================================== */ +#define UARTx_BRRF_BRRF_Pos (0UL) /*!< BRRF (Bit 0) */ +#define UARTx_BRRF_BRRF_Msk (0xfUL) /*!< BRRF (Bitfield-Mask: 0x0f) */ +/* ======================================================== TIMARR ========================================================= */ +#define UARTx_TIMARR_TIMARR_Pos (0UL) /*!< TIMARR (Bit 0) */ +#define UARTx_TIMARR_TIMARR_Msk (0xffffffUL) /*!< TIMARR (Bitfield-Mask: 0xffffff) */ +/* ======================================================== TIMCNT ========================================================= */ +#define UARTx_TIMCNT_TIMCNT_Pos (0UL) /*!< TIMCNT (Bit 0) */ +#define UARTx_TIMCNT_TIMCNT_Msk (0xffffffUL) /*!< TIMCNT (Bitfield-Mask: 0xffffff) */ +/* ========================================================== TDR ========================================================== */ +#define UARTx_TDR_BREAK_Pos (10UL) /*!< BREAK (Bit 10) */ +#define UARTx_TDR_BREAK_Msk (0x400UL) /*!< BREAK (Bitfield-Mask: 0x01) */ +#define UARTx_TDR_IDLE_Pos (9UL) /*!< IDLE (Bit 9) */ +#define UARTx_TDR_IDLE_Msk (0x200UL) /*!< IDLE (Bitfield-Mask: 0x01) */ +#define UARTx_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ +#define UARTx_TDR_TDR_Msk (0x1ffUL) /*!< TDR (Bitfield-Mask: 0x1ff) */ +/* ========================================================== RDR ========================================================== */ +#define UARTx_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ +#define UARTx_RDR_RDR_Msk (0x1ffUL) /*!< RDR (Bitfield-Mask: 0x1ff) */ +/* ========================================================== IER ========================================================== */ +#define UARTx_IER_RXMATCH_Pos (12UL) /*!< RXMATCH (Bit 12) */ +#define UARTx_IER_RXMATCH_Msk (0x1000UL) /*!< RXMATCH (Bitfield-Mask: 0x01) */ +#define UARTx_IER_ORE_Pos (11UL) /*!< ORE (Bit 11) */ +#define UARTx_IER_ORE_Msk (0x800UL) /*!< ORE (Bitfield-Mask: 0x01) */ +#define UARTx_IER_NE_Pos (10UL) /*!< NE (Bit 10) */ +#define UARTx_IER_NE_Msk (0x400UL) /*!< NE (Bitfield-Mask: 0x01) */ +#define UARTx_IER_PE_Pos (9UL) /*!< PE (Bit 9) */ +#define UARTx_IER_PE_Msk (0x200UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UARTx_IER_FE_Pos (8UL) /*!< FE (Bit 8) */ +#define UARTx_IER_FE_Msk (0x100UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UARTx_IER_CTS_Pos (7UL) /*!< CTS (Bit 7) */ +#define UARTx_IER_CTS_Msk (0x80UL) /*!< CTS (Bitfield-Mask: 0x01) */ +#define UARTx_IER_TIMOV_Pos (6UL) /*!< TIMOV (Bit 6) */ +#define UARTx_IER_TIMOV_Msk (0x40UL) /*!< TIMOV (Bitfield-Mask: 0x01) */ +#define UARTx_IER_BAUD_Pos (5UL) /*!< BAUD (Bit 5) */ +#define UARTx_IER_BAUD_Msk (0x20UL) /*!< BAUD (Bitfield-Mask: 0x01) */ +#define UARTx_IER_RXBRK_Pos (4UL) /*!< RXBRK (Bit 4) */ +#define UARTx_IER_RXBRK_Msk (0x10UL) /*!< RXBRK (Bitfield-Mask: 0x01) */ +#define UARTx_IER_RXIDLE_Pos (3UL) /*!< RXIDLE (Bit 3) */ +#define UARTx_IER_RXIDLE_Msk (0x8UL) /*!< RXIDLE (Bitfield-Mask: 0x01) */ +#define UARTx_IER_RC_Pos (2UL) /*!< RC (Bit 2) */ +#define UARTx_IER_RC_Msk (0x4UL) /*!< RC (Bitfield-Mask: 0x01) */ +#define UARTx_IER_TC_Pos (1UL) /*!< TC (Bit 1) */ +#define UARTx_IER_TC_Msk (0x2UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define UARTx_IER_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define UARTx_IER_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define UARTx_ISR_CTSLV_Pos (15UL) /*!< CTSLV (Bit 15) */ +#define UARTx_ISR_CTSLV_Msk (0x8000UL) /*!< CTSLV (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_TXBUSY_Pos (14UL) /*!< TXBUSY (Bit 14) */ +#define UARTx_ISR_TXBUSY_Msk (0x4000UL) /*!< TXBUSY (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_SLVMATCH_Pos (13UL) /*!< SLVMATCH (Bit 13) */ +#define UARTx_ISR_SLVMATCH_Msk (0x2000UL) /*!< SLVMATCH (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_RXMATCH_Pos (12UL) /*!< RXMATCH (Bit 12) */ +#define UARTx_ISR_RXMATCH_Msk (0x1000UL) /*!< RXMATCH (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_ORE_Pos (11UL) /*!< ORE (Bit 11) */ +#define UARTx_ISR_ORE_Msk (0x800UL) /*!< ORE (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_NE_Pos (10UL) /*!< NE (Bit 10) */ +#define UARTx_ISR_NE_Msk (0x400UL) /*!< NE (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_PE_Pos (9UL) /*!< PE (Bit 9) */ +#define UARTx_ISR_PE_Msk (0x200UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_FE_Pos (8UL) /*!< FE (Bit 8) */ +#define UARTx_ISR_FE_Msk (0x100UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_CTS_Pos (7UL) /*!< CTS (Bit 7) */ +#define UARTx_ISR_CTS_Msk (0x80UL) /*!< CTS (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_TIMOV_Pos (6UL) /*!< TIMOV (Bit 6) */ +#define UARTx_ISR_TIMOV_Msk (0x40UL) /*!< TIMOV (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_BAUD_Pos (5UL) /*!< BAUD (Bit 5) */ +#define UARTx_ISR_BAUD_Msk (0x20UL) /*!< BAUD (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_RXBRK_Pos (4UL) /*!< RXBRK (Bit 4) */ +#define UARTx_ISR_RXBRK_Msk (0x10UL) /*!< RXBRK (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_RXIDLE_Pos (3UL) /*!< RXIDLE (Bit 3) */ +#define UARTx_ISR_RXIDLE_Msk (0x8UL) /*!< RXIDLE (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_RC_Pos (2UL) /*!< RC (Bit 2) */ +#define UARTx_ISR_RC_Msk (0x4UL) /*!< RC (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_TC_Pos (1UL) /*!< TC (Bit 1) */ +#define UARTx_ISR_TC_Msk (0x2UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define UARTx_ISR_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define UARTx_ISR_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define UARTx_ICR_RXMATCH_Pos (12UL) /*!< RXMATCH (Bit 12) */ +#define UARTx_ICR_RXMATCH_Msk (0x1000UL) /*!< RXMATCH (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_ORE_Pos (11UL) /*!< ORE (Bit 11) */ +#define UARTx_ICR_ORE_Msk (0x800UL) /*!< ORE (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_NE_Pos (10UL) /*!< NE (Bit 10) */ +#define UARTx_ICR_NE_Msk (0x400UL) /*!< NE (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_PE_Pos (9UL) /*!< PE (Bit 9) */ +#define UARTx_ICR_PE_Msk (0x200UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_FE_Pos (8UL) /*!< FE (Bit 8) */ +#define UARTx_ICR_FE_Msk (0x100UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_CTS_Pos (7UL) /*!< CTS (Bit 7) */ +#define UARTx_ICR_CTS_Msk (0x80UL) /*!< CTS (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_TIMOV_Pos (6UL) /*!< TIMOV (Bit 6) */ +#define UARTx_ICR_TIMOV_Msk (0x40UL) /*!< TIMOV (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_BAUD_Pos (5UL) /*!< BAUD (Bit 5) */ +#define UARTx_ICR_BAUD_Msk (0x20UL) /*!< BAUD (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_RXBRK_Pos (4UL) /*!< RXBRK (Bit 4) */ +#define UARTx_ICR_RXBRK_Msk (0x10UL) /*!< RXBRK (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_RXIDLE_Pos (3UL) /*!< RXIDLE (Bit 3) */ +#define UARTx_ICR_RXIDLE_Msk (0x8UL) /*!< RXIDLE (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_RC_Pos (2UL) /*!< RC (Bit 2) */ +#define UARTx_ICR_RC_Msk (0x4UL) /*!< RC (Bitfield-Mask: 0x01) */ +#define UARTx_ICR_TC_Pos (1UL) /*!< TC (Bit 1) */ +#define UARTx_ICR_TC_Msk (0x2UL) /*!< TC (Bitfield-Mask: 0x01) */ +/* ========================================================= ADDR ========================================================== */ +#define UARTx_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define UARTx_ADDR_ADDR_Msk (0xffUL) /*!< ADDR (Bitfield-Mask: 0xff) */ +/* ========================================================= MASK ========================================================== */ +#define UARTx_MASK_MASK_Pos (0UL) /*!< MASK (Bit 0) */ +#define UARTx_MASK_MASK_Msk (0xffUL) /*!< MASK (Bitfield-Mask: 0xff) */ +/* ======================================================== RXMATCH ======================================================== */ +#define UARTx_RXMATCH_RXMATCH_Pos (0UL) /*!< RXMATCH (Bit 0) */ +#define UARTx_RXMATCH_RXMATCH_Msk (0x1ffUL) /*!< RXMATCH (Bitfield-Mask: 0x1ff) */ + + +/* =========================================================================================================================== */ +/* ================ LVD ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define LVD_CR0_FLTCLK_Pos (8UL) /*!< FLTCLK (Bit 8) */ +#define LVD_CR0_FLTCLK_Msk (0x100UL) /*!< FLTCLK (Bitfield-Mask: 0x01) */ +#define LVD_CR0_VTH_Pos (4UL) /*!< VTH (Bit 4) */ +#define LVD_CR0_VTH_Msk (0x70UL) /*!< VTH (Bitfield-Mask: 0x07) */ +#define LVD_CR0_SOURCE_Pos (2UL) /*!< SOURCE (Bit 2) */ +#define LVD_CR0_SOURCE_Msk (0x4UL) /*!< SOURCE (Bitfield-Mask: 0x01) */ +#define LVD_CR0_ACTION_Pos (1UL) /*!< ACTION (Bit 1) */ +#define LVD_CR0_ACTION_Msk (0x2UL) /*!< ACTION (Bitfield-Mask: 0x01) */ +#define LVD_CR0_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define LVD_CR0_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ +#define LVD_CR1_FLTTIME_Pos (4UL) /*!< FLTTIME (Bit 4) */ +#define LVD_CR1_FLTTIME_Msk (0xf0UL) /*!< FLTTIME (Bitfield-Mask: 0x0f) */ +#define LVD_CR1_FALL_Pos (3UL) /*!< FALL (Bit 3) */ +#define LVD_CR1_FALL_Msk (0x8UL) /*!< FALL (Bitfield-Mask: 0x01) */ +#define LVD_CR1_RISE_Pos (2UL) /*!< RISE (Bit 2) */ +#define LVD_CR1_RISE_Msk (0x4UL) /*!< RISE (Bitfield-Mask: 0x01) */ +#define LVD_CR1_LEVEL_Pos (1UL) /*!< LEVEL (Bit 1) */ +#define LVD_CR1_LEVEL_Msk (0x2UL) /*!< LEVEL (Bitfield-Mask: 0x01) */ +#define LVD_CR1_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define LVD_CR1_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ========================================================== SR =========================================================== */ +#define LVD_SR_FLTV_Pos (1UL) /*!< FLTV (Bit 1) */ +#define LVD_SR_FLTV_Msk (0x2UL) /*!< FLTV (Bitfield-Mask: 0x01) */ +#define LVD_SR_INTF_Pos (0UL) /*!< INTF (Bit 0) */ +#define LVD_SR_INTF_Msk (0x1UL) /*!< INTF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ OPA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define OPAx_CR_BIAS_Pos (13UL) /*!< BIAS (Bit 13) */ +#define OPAx_CR_BIAS_Msk (0xe000UL) /*!< BIAS (Bitfield-Mask: 0x07) */ +#define OPAx_CR_AMP_Pos (10UL) /*!< AMP (Bit 10) */ +#define OPAx_CR_AMP_Msk (0x1c00UL) /*!< AMP (Bitfield-Mask: 0x07) */ +#define OPAx_CR_INN2EN_Pos (9UL) /*!< INN2EN (Bit 9) */ +#define OPAx_CR_INN2EN_Msk (0x200UL) /*!< INN2EN (Bitfield-Mask: 0x01) */ +#define OPAx_CR_INN1EN_Pos (8UL) /*!< INN1EN (Bit 8) */ +#define OPAx_CR_INN1EN_Msk (0x100UL) /*!< INN1EN (Bitfield-Mask: 0x01) */ +#define OPAx_CR_INP4EN_Pos (7UL) /*!< INP4EN (Bit 7) */ +#define OPAx_CR_INP4EN_Msk (0x80UL) /*!< INP4EN (Bitfield-Mask: 0x01) */ +#define OPAx_CR_INP3EN_Pos (6UL) /*!< INP3EN (Bit 6) */ +#define OPAx_CR_INP3EN_Msk (0x40UL) /*!< INP3EN (Bitfield-Mask: 0x01) */ +#define OPAx_CR_INP2EN_Pos (5UL) /*!< INP2EN (Bit 5) */ +#define OPAx_CR_INP2EN_Msk (0x20UL) /*!< INP2EN (Bitfield-Mask: 0x01) */ +#define OPAx_CR_INP1EN_Pos (4UL) /*!< INP1EN (Bit 4) */ +#define OPAx_CR_INP1EN_Msk (0x10UL) /*!< INP1EN (Bitfield-Mask: 0x01) */ +#define OPAx_CR_MODE_Pos (1UL) /*!< MODE (Bit 1) */ +#define OPAx_CR_MODE_Msk (0x6UL) /*!< MODE (Bitfield-Mask: 0x03) */ +#define OPAx_CR_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define OPAx_CR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CAL ========================================================== */ +#define OPAx_CAL_GTIM4OC2_Pos (31UL) /*!< GTIM4OC2 (Bit 31) */ +#define OPAx_CAL_GTIM4OC2_Msk (0x80000000UL) /*!< GTIM4OC2 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM4OC1_Pos (30UL) /*!< GTIM4OC1 (Bit 30) */ +#define OPAx_CAL_GTIM4OC1_Msk (0x40000000UL) /*!< GTIM4OC1 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM4TRGO_Pos (29UL) /*!< GTIM4TRGO (Bit 29) */ +#define OPAx_CAL_GTIM4TRGO_Msk (0x20000000UL) /*!< GTIM4TRGO (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM3OC2_Pos (28UL) /*!< GTIM3OC2 (Bit 28) */ +#define OPAx_CAL_GTIM3OC2_Msk (0x10000000UL) /*!< GTIM3OC2 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM3OC1_Pos (27UL) /*!< GTIM3OC1 (Bit 27) */ +#define OPAx_CAL_GTIM3OC1_Msk (0x8000000UL) /*!< GTIM3OC1 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM3TRGO_Pos (26UL) /*!< GTIM3TRGO (Bit 26) */ +#define OPAx_CAL_GTIM3TRGO_Msk (0x4000000UL) /*!< GTIM3TRGO (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM2OC2_Pos (25UL) /*!< GTIM2OC2 (Bit 25) */ +#define OPAx_CAL_GTIM2OC2_Msk (0x2000000UL) /*!< GTIM2OC2 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM2OC1_Pos (24UL) /*!< GTIM2OC1 (Bit 24) */ +#define OPAx_CAL_GTIM2OC1_Msk (0x1000000UL) /*!< GTIM2OC1 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM2TRGO_Pos (23UL) /*!< GTIM2TRGO (Bit 23) */ +#define OPAx_CAL_GTIM2TRGO_Msk (0x800000UL) /*!< GTIM2TRGO (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM1OC2_Pos (22UL) /*!< GTIM1OC2 (Bit 22) */ +#define OPAx_CAL_GTIM1OC2_Msk (0x400000UL) /*!< GTIM1OC2 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM1OC1_Pos (21UL) /*!< GTIM1OC1 (Bit 21) */ +#define OPAx_CAL_GTIM1OC1_Msk (0x200000UL) /*!< GTIM1OC1 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_GTIM1TRGO_Pos (20UL) /*!< GTIM1TRGO (Bit 20) */ +#define OPAx_CAL_GTIM1TRGO_Msk (0x100000UL) /*!< GTIM1TRGO (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_ATIM1OC6_Pos (19UL) /*!< ATIM1OC6 (Bit 19) */ +#define OPAx_CAL_ATIM1OC6_Msk (0x80000UL) /*!< ATIM1OC6 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_ATIM1OC5_Pos (18UL) /*!< ATIM1OC5 (Bit 18) */ +#define OPAx_CAL_ATIM1OC5_Msk (0x40000UL) /*!< ATIM1OC5 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_ATIM1OC4_Pos (17UL) /*!< ATIM1OC4 (Bit 17) */ +#define OPAx_CAL_ATIM1OC4_Msk (0x20000UL) /*!< ATIM1OC4 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_ATIM1TRGO_Pos (16UL) /*!< ATIM1TRGO (Bit 16) */ +#define OPAx_CAL_ATIM1TRGO_Msk (0x10000UL) /*!< ATIM1TRGO (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_ADC2START1_Pos (15UL) /*!< ADC2START1 (Bit 15) */ +#define OPAx_CAL_ADC2START1_Msk (0x8000UL) /*!< ADC2START1 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_ADC1START1_Pos (14UL) /*!< ADC1START1 (Bit 14) */ +#define OPAx_CAL_ADC1START1_Msk (0x4000UL) /*!< ADC1START1 (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_CLKDIV_Pos (11UL) /*!< CLKDIV (Bit 11) */ +#define OPAx_CAL_CLKDIV_Msk (0x3800UL) /*!< CLKDIV (Bitfield-Mask: 0x07) */ +#define OPAx_CAL_AZRUN_Pos (10UL) /*!< AZRUN (Bit 10) */ +#define OPAx_CAL_AZRUN_Msk (0x400UL) /*!< AZRUN (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_ADCSTART_Pos (8UL) /*!< ADCSTART (Bit 8) */ +#define OPAx_CAL_ADCSTART_Msk (0x100UL) /*!< ADCSTART (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_CALPERIOD_Pos (4UL) /*!< CALPERIOD (Bit 4) */ +#define OPAx_CAL_CALPERIOD_Msk (0xf0UL) /*!< CALPERIOD (Bitfield-Mask: 0x0f) */ +#define OPAx_CAL_SOFTTRIG_Pos (3UL) /*!< SOFTTRIG (Bit 3) */ +#define OPAx_CAL_SOFTTRIG_Msk (0x8UL) /*!< SOFTTRIG (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_START_Pos (2UL) /*!< START (Bit 2) */ +#define OPAx_CAL_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_CALMODE_Pos (1UL) /*!< CALMODE (Bit 1) */ +#define OPAx_CAL_CALMODE_Msk (0x2UL) /*!< CALMODE (Bitfield-Mask: 0x01) */ +#define OPAx_CAL_CALEN_Pos (0UL) /*!< CALEN (Bit 0) */ +#define OPAx_CAL_CALEN_Msk (0x1UL) /*!< CALEN (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ RAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== IER ========================================================== */ +#define RAM_IER_PARITY_Pos (0UL) /*!< PARITY (Bit 0) */ +#define RAM_IER_PARITY_Msk (0x1UL) /*!< PARITY (Bitfield-Mask: 0x01) */ +/* ========================================================= ADDR ========================================================== */ +#define RAM_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define RAM_ADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== ISR ========================================================== */ +#define RAM_ISR_PARITY_Pos (0UL) /*!< PARITY (Bit 0) */ +#define RAM_ISR_PARITY_Msk (0x1UL) /*!< PARITY (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define RAM_ICR_PARITY_Pos (0UL) /*!< PARITY (Bit 0) */ +#define RAM_ICR_PARITY_Msk (0x1UL) /*!< PARITY (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== KEY ========================================================== */ +#define RTC_KEY_KEY_Pos (0UL) /*!< KEY (Bit 0) */ +#define RTC_KEY_KEY_Msk (0xffUL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================== CR0 ========================================================== */ +#define RTC_CR0_START_Pos (7UL) /*!< START (Bit 7) */ +#define RTC_CR0_START_Msk (0x80UL) /*!< START (Bitfield-Mask: 0x01) */ +#define RTC_CR0_RTC1HZ_Pos (5UL) /*!< RTC1HZ (Bit 5) */ +#define RTC_CR0_RTC1HZ_Msk (0x60UL) /*!< RTC1HZ (Bitfield-Mask: 0x03) */ +#define RTC_CR0_H24_Pos (3UL) /*!< H24 (Bit 3) */ +#define RTC_CR0_H24_Msk (0x8UL) /*!< H24 (Bitfield-Mask: 0x01) */ +#define RTC_CR0_INTERVAL_Pos (0UL) /*!< INTERVAL (Bit 0) */ +#define RTC_CR0_INTERVAL_Msk (0x7UL) /*!< INTERVAL (Bitfield-Mask: 0x07) */ +/* ========================================================== CR1 ========================================================== */ +#define RTC_CR1_SOURCE_Pos (8UL) /*!< SOURCE (Bit 8) */ +#define RTC_CR1_SOURCE_Msk (0x700UL) /*!< SOURCE (Bitfield-Mask: 0x07) */ +#define RTC_CR1_WAIT_Pos (2UL) /*!< WAIT (Bit 2) */ +#define RTC_CR1_WAIT_Msk (0x4UL) /*!< WAIT (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define RTC_CR2_ALARMBEN_Pos (10UL) /*!< ALARMBEN (Bit 10) */ +#define RTC_CR2_ALARMBEN_Msk (0x400UL) /*!< ALARMBEN (Bitfield-Mask: 0x01) */ +#define RTC_CR2_ALARMAEN_Pos (9UL) /*!< ALARMAEN (Bit 9) */ +#define RTC_CR2_ALARMAEN_Msk (0x200UL) /*!< ALARMAEN (Bitfield-Mask: 0x01) */ +#define RTC_CR2_AWTEN_Pos (7UL) /*!< AWTEN (Bit 7) */ +#define RTC_CR2_AWTEN_Msk (0x80UL) /*!< AWTEN (Bitfield-Mask: 0x01) */ +#define RTC_CR2_TAMPEN_Pos (6UL) /*!< TAMPEN (Bit 6) */ +#define RTC_CR2_TAMPEN_Msk (0x40UL) /*!< TAMPEN (Bitfield-Mask: 0x01) */ +#define RTC_CR2_RTCOUT_Pos (4UL) /*!< RTCOUT (Bit 4) */ +#define RTC_CR2_RTCOUT_Msk (0x30UL) /*!< RTCOUT (Bitfield-Mask: 0x03) */ +#define RTC_CR2_TAMPEDGE_Pos (3UL) /*!< TAMPEDGE (Bit 3) */ +#define RTC_CR2_TAMPEDGE_Msk (0x8UL) /*!< TAMPEDGE (Bitfield-Mask: 0x01) */ +#define RTC_CR2_AWTSRC_Pos (2UL) /*!< AWTSRC (Bit 2) */ +#define RTC_CR2_AWTSRC_Msk (0x4UL) /*!< AWTSRC (Bitfield-Mask: 0x01) */ +#define RTC_CR2_AWTPRS_Pos (0UL) /*!< AWTPRS (Bit 0) */ +#define RTC_CR2_AWTPRS_Msk (0x3UL) /*!< AWTPRS (Bitfield-Mask: 0x03) */ +/* ========================================================== PSC ========================================================== */ +#define RTC_PSC_PSC1_Pos (20UL) /*!< PSC1 (Bit 20) */ +#define RTC_PSC_PSC1_Msk (0xff00000UL) /*!< PSC1 (Bitfield-Mask: 0xff) */ +#define RTC_PSC_PSC2_Pos (0UL) /*!< PSC2 (Bit 0) */ +#define RTC_PSC_PSC2_Msk (0xfffffUL) /*!< PSC2 (Bitfield-Mask: 0xfffff) */ +/* ========================================================= DATE ========================================================== */ +#define RTC_DATE_WEEK_Pos (24UL) /*!< WEEK (Bit 24) */ +#define RTC_DATE_WEEK_Msk (0x7000000UL) /*!< WEEK (Bitfield-Mask: 0x07) */ +#define RTC_DATE_YEAR_Pos (16UL) /*!< YEAR (Bit 16) */ +#define RTC_DATE_YEAR_Msk (0xff0000UL) /*!< YEAR (Bitfield-Mask: 0xff) */ +#define RTC_DATE_MONTH_Pos (8UL) /*!< MONTH (Bit 8) */ +#define RTC_DATE_MONTH_Msk (0x1f00UL) /*!< MONTH (Bitfield-Mask: 0x1f) */ +#define RTC_DATE_DAY_Pos (0UL) /*!< DAY (Bit 0) */ +#define RTC_DATE_DAY_Msk (0x3fUL) /*!< DAY (Bitfield-Mask: 0x3f) */ +/* ========================================================= TIME ========================================================== */ +#define RTC_TIME_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */ +#define RTC_TIME_HOUR_Msk (0x3f0000UL) /*!< HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_TIME_MINUTE_Pos (8UL) /*!< MINUTE (Bit 8) */ +#define RTC_TIME_MINUTE_Msk (0x7f00UL) /*!< MINUTE (Bitfield-Mask: 0x7f) */ +#define RTC_TIME_SECOND_Pos (0UL) /*!< SECOND (Bit 0) */ +#define RTC_TIME_SECOND_Msk (0x7fUL) /*!< SECOND (Bitfield-Mask: 0x7f) */ +/* ========================================================= SSCNT ========================================================= */ +#define RTC_SSCNT_SSCNT1_Pos (20UL) /*!< SSCNT1 (Bit 20) */ +#define RTC_SSCNT_SSCNT1_Msk (0x100000UL) /*!< SSCNT1 (Bitfield-Mask: 0x01) */ +#define RTC_SSCNT_SSCNT0_Pos (0UL) /*!< SSCNT0 (Bit 0) */ +#define RTC_SSCNT_SSCNT0_Msk (0xfffffUL) /*!< SSCNT0 (Bitfield-Mask: 0xfffff) */ +/* ======================================================== ALARMA ========================================================= */ +#define RTC_ALARMA_WEEKMASK_Pos (24UL) /*!< WEEKMASK (Bit 24) */ +#define RTC_ALARMA_WEEKMASK_Msk (0x7f000000UL) /*!< WEEKMASK (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMA_HOUREN_Pos (23UL) /*!< HOUREN (Bit 23) */ +#define RTC_ALARMA_HOUREN_Msk (0x800000UL) /*!< HOUREN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMA_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */ +#define RTC_ALARMA_HOUR_Msk (0x3f0000UL) /*!< HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_ALARMA_MINUTEEN_Pos (15UL) /*!< MINUTEEN (Bit 15) */ +#define RTC_ALARMA_MINUTEEN_Msk (0x8000UL) /*!< MINUTEEN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMA_MINUTE_Pos (8UL) /*!< MINUTE (Bit 8) */ +#define RTC_ALARMA_MINUTE_Msk (0x7f00UL) /*!< MINUTE (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMA_SECONDEN_Pos (7UL) /*!< SECONDEN (Bit 7) */ +#define RTC_ALARMA_SECONDEN_Msk (0x80UL) /*!< SECONDEN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMA_SECOND_Pos (0UL) /*!< SECOND (Bit 0) */ +#define RTC_ALARMA_SECOND_Msk (0x7fUL) /*!< SECOND (Bitfield-Mask: 0x7f) */ +/* ======================================================== ALARMB ========================================================= */ +#define RTC_ALARMB_WEEKMASK_Pos (24UL) /*!< WEEKMASK (Bit 24) */ +#define RTC_ALARMB_WEEKMASK_Msk (0x7f000000UL) /*!< WEEKMASK (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMB_HOUREN_Pos (23UL) /*!< HOUREN (Bit 23) */ +#define RTC_ALARMB_HOUREN_Msk (0x800000UL) /*!< HOUREN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMB_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */ +#define RTC_ALARMB_HOUR_Msk (0x3f0000UL) /*!< HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_ALARMB_MINUTEEN_Pos (15UL) /*!< MINUTEEN (Bit 15) */ +#define RTC_ALARMB_MINUTEEN_Msk (0x8000UL) /*!< MINUTEEN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMB_MINUTE_Pos (8UL) /*!< MINUTE (Bit 8) */ +#define RTC_ALARMB_MINUTE_Msk (0x7f00UL) /*!< MINUTE (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMB_SECONDEN_Pos (7UL) /*!< SECONDEN (Bit 7) */ +#define RTC_ALARMB_SECONDEN_Msk (0x80UL) /*!< SECONDEN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMB_SECOND_Pos (0UL) /*!< SECOND (Bit 0) */ +#define RTC_ALARMB_SECOND_Msk (0x7fUL) /*!< SECOND (Bitfield-Mask: 0x7f) */ +/* ======================================================= TAMPDATE ======================================================== */ +#define RTC_TAMPDATE_WEEK_Pos (13UL) /*!< WEEK (Bit 13) */ +#define RTC_TAMPDATE_WEEK_Msk (0xe000UL) /*!< WEEK (Bitfield-Mask: 0x07) */ +#define RTC_TAMPDATE_MONTH_Pos (8UL) /*!< MONTH (Bit 8) */ +#define RTC_TAMPDATE_MONTH_Msk (0x1f00UL) /*!< MONTH (Bitfield-Mask: 0x1f) */ +#define RTC_TAMPDATE_DAY_Pos (0UL) /*!< DAY (Bit 0) */ +#define RTC_TAMPDATE_DAY_Msk (0x3fUL) /*!< DAY (Bitfield-Mask: 0x3f) */ +/* ======================================================= TAMPTIME ======================================================== */ +#define RTC_TAMPTIME_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */ +#define RTC_TAMPTIME_HOUR_Msk (0x3f0000UL) /*!< HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_TAMPTIME_MINUTE_Pos (8UL) /*!< MINUTE (Bit 8) */ +#define RTC_TAMPTIME_MINUTE_Msk (0x7f00UL) /*!< MINUTE (Bitfield-Mask: 0x7f) */ +#define RTC_TAMPTIME_SECOND_Pos (0UL) /*!< SECOND (Bit 0) */ +#define RTC_TAMPTIME_SECOND_Msk (0x7fUL) /*!< SECOND (Bitfield-Mask: 0x7f) */ +/* ========================================================== IER ========================================================== */ +#define RTC_IER_INTERVAL_Pos (6UL) /*!< INTERVAL (Bit 6) */ +#define RTC_IER_INTERVAL_Msk (0x40UL) /*!< INTERVAL (Bitfield-Mask: 0x01) */ +#define RTC_IER_TAMPOV_Pos (4UL) /*!< TAMPOV (Bit 4) */ +#define RTC_IER_TAMPOV_Msk (0x10UL) /*!< TAMPOV (Bitfield-Mask: 0x01) */ +#define RTC_IER_TAMP_Pos (3UL) /*!< TAMP (Bit 3) */ +#define RTC_IER_TAMP_Msk (0x8UL) /*!< TAMP (Bitfield-Mask: 0x01) */ +#define RTC_IER_AWTIMER_Pos (2UL) /*!< AWTIMER (Bit 2) */ +#define RTC_IER_AWTIMER_Msk (0x4UL) /*!< AWTIMER (Bitfield-Mask: 0x01) */ +#define RTC_IER_ALARMB_Pos (1UL) /*!< ALARMB (Bit 1) */ +#define RTC_IER_ALARMB_Msk (0x2UL) /*!< ALARMB (Bitfield-Mask: 0x01) */ +#define RTC_IER_ALARMA_Pos (0UL) /*!< ALARMA (Bit 0) */ +#define RTC_IER_ALARMA_Msk (0x1UL) /*!< ALARMA (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define RTC_ISR_INTERVAL_Pos (6UL) /*!< INTERVAL (Bit 6) */ +#define RTC_ISR_INTERVAL_Msk (0x40UL) /*!< INTERVAL (Bitfield-Mask: 0x01) */ +#define RTC_ISR_TAMPOV_Pos (4UL) /*!< TAMPOV (Bit 4) */ +#define RTC_ISR_TAMPOV_Msk (0x10UL) /*!< TAMPOV (Bitfield-Mask: 0x01) */ +#define RTC_ISR_TAMP_Pos (3UL) /*!< TAMP (Bit 3) */ +#define RTC_ISR_TAMP_Msk (0x8UL) /*!< TAMP (Bitfield-Mask: 0x01) */ +#define RTC_ISR_AWTIMER_Pos (2UL) /*!< AWTIMER (Bit 2) */ +#define RTC_ISR_AWTIMER_Msk (0x4UL) /*!< AWTIMER (Bitfield-Mask: 0x01) */ +#define RTC_ISR_ALARMB_Pos (1UL) /*!< ALARMB (Bit 1) */ +#define RTC_ISR_ALARMB_Msk (0x2UL) /*!< ALARMB (Bitfield-Mask: 0x01) */ +#define RTC_ISR_ALARMA_Pos (0UL) /*!< ALARMA (Bit 0) */ +#define RTC_ISR_ALARMA_Msk (0x1UL) /*!< ALARMA (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define RTC_ICR_INTERVAL_Pos (6UL) /*!< INTERVAL (Bit 6) */ +#define RTC_ICR_INTERVAL_Msk (0x40UL) /*!< INTERVAL (Bitfield-Mask: 0x01) */ +#define RTC_ICR_TAMPOV_Pos (4UL) /*!< TAMPOV (Bit 4) */ +#define RTC_ICR_TAMPOV_Msk (0x10UL) /*!< TAMPOV (Bitfield-Mask: 0x01) */ +#define RTC_ICR_TAMP_Pos (3UL) /*!< TAMP (Bit 3) */ +#define RTC_ICR_TAMP_Msk (0x8UL) /*!< TAMP (Bitfield-Mask: 0x01) */ +#define RTC_ICR_AWTIMER_Pos (2UL) /*!< AWTIMER (Bit 2) */ +#define RTC_ICR_AWTIMER_Msk (0x4UL) /*!< AWTIMER (Bitfield-Mask: 0x01) */ +#define RTC_ICR_ALARMB_Pos (1UL) /*!< ALARMB (Bit 1) */ +#define RTC_ICR_ALARMB_Msk (0x2UL) /*!< ALARMB (Bitfield-Mask: 0x01) */ +#define RTC_ICR_ALARMA_Pos (0UL) /*!< ALARMA (Bit 0) */ +#define RTC_ICR_ALARMA_Msk (0x1UL) /*!< ALARMA (Bitfield-Mask: 0x01) */ +/* ======================================================== AWTARR ========================================================= */ +#define RTC_AWTARR_ARR_Pos (0UL) /*!< ARR (Bit 0) */ +#define RTC_AWTARR_ARR_Msk (0xffffUL) /*!< ARR (Bitfield-Mask: 0xffff) */ +/* ======================================================== AWTCNT ========================================================= */ +#define RTC_AWTCNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define RTC_AWTCNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= COMPCFR1 ======================================================== */ +#define RTC_COMPCFR1_EN_Pos (15UL) /*!< EN (Bit 15) */ +#define RTC_COMPCFR1_EN_Msk (0x8000UL) /*!< EN (Bitfield-Mask: 0x01) */ +#define RTC_COMPCFR1_SIGN_Pos (14UL) /*!< SIGN (Bit 14) */ +#define RTC_COMPCFR1_SIGN_Msk (0x4000UL) /*!< SIGN (Bitfield-Mask: 0x01) */ +#define RTC_COMPCFR1_PERIOD_Pos (12UL) /*!< PERIOD (Bit 12) */ +#define RTC_COMPCFR1_PERIOD_Msk (0x3000UL) /*!< PERIOD (Bitfield-Mask: 0x03) */ +#define RTC_COMPCFR1_COMP_Pos (0UL) /*!< COMP (Bit 0) */ +#define RTC_COMPCFR1_COMP_Msk (0xfffUL) /*!< COMP (Bitfield-Mask: 0xfff) */ + + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR1 ========================================================== */ +#define SPIx_CR1_BR_Pos (24UL) /*!< BR (Bit 24) */ +#define SPIx_CR1_BR_Msk (0x7f000000UL) /*!< BR (Bitfield-Mask: 0x7f) */ +#define SPIx_CR1_SMP_Pos (20UL) /*!< SMP (Bit 20) */ +#define SPIx_CR1_SMP_Msk (0x100000UL) /*!< SMP (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_MISOHD_Pos (19UL) /*!< MISOHD (Bit 19) */ +#define SPIx_CR1_MISOHD_Msk (0x80000UL) /*!< MISOHD (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_FLTEN_Pos (18UL) /*!< FLTEN (Bit 18) */ +#define SPIx_CR1_FLTEN_Msk (0x40000UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_MODE_Pos (16UL) /*!< MODE (Bit 16) */ +#define SPIx_CR1_MODE_Msk (0x30000UL) /*!< MODE (Bitfield-Mask: 0x03) */ +#define SPIx_CR1_GAP_Pos (12UL) /*!< GAP (Bit 12) */ +#define SPIx_CR1_GAP_Msk (0xf000UL) /*!< GAP (Bitfield-Mask: 0x0f) */ +#define SPIx_CR1_WIDTH_Pos (8UL) /*!< WIDTH (Bit 8) */ +#define SPIx_CR1_WIDTH_Msk (0xf00UL) /*!< WIDTH (Bitfield-Mask: 0x0f) */ +#define SPIx_CR1_LSBF_Pos (7UL) /*!< LSBF (Bit 7) */ +#define SPIx_CR1_LSBF_Msk (0x80UL) /*!< LSBF (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_CPOL_Pos (3UL) /*!< CPOL (Bit 3) */ +#define SPIx_CR1_CPOL_Msk (0x8UL) /*!< CPOL (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_CPHA_Pos (2UL) /*!< CPHA (Bit 2) */ +#define SPIx_CR1_CPHA_Msk (0x4UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_SSM_Pos (1UL) /*!< SSM (Bit 1) */ +#define SPIx_CR1_SSM_Msk (0x2UL) /*!< SSM (Bitfield-Mask: 0x01) */ +#define SPIx_CR1_MSTR_Pos (0UL) /*!< MSTR (Bit 0) */ +#define SPIx_CR1_MSTR_Msk (0x1UL) /*!< MSTR (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define SPIx_CR2_DMATX_Pos (2UL) /*!< DMATX (Bit 2) */ +#define SPIx_CR2_DMATX_Msk (0x4UL) /*!< DMATX (Bitfield-Mask: 0x01) */ +#define SPIx_CR2_DMARX_Pos (1UL) /*!< DMARX (Bit 1) */ +#define SPIx_CR2_DMARX_Msk (0x2UL) /*!< DMARX (Bitfield-Mask: 0x01) */ +#define SPIx_CR2_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define SPIx_CR2_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR3 ========================================================== */ +#define SPIx_CR3_HDOE_Pos (0UL) /*!< HDOE (Bit 0) */ +#define SPIx_CR3_HDOE_Msk (0x1UL) /*!< HDOE (Bitfield-Mask: 0x01) */ +/* ========================================================== SSI ========================================================== */ +#define SPIx_SSI_SSI_Pos (0UL) /*!< SSI (Bit 0) */ +#define SPIx_SSI_SSI_Msk (0x1UL) /*!< SSI (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define SPIx_IER_MODF_Pos (7UL) /*!< MODF (Bit 7) */ +#define SPIx_IER_MODF_Msk (0x80UL) /*!< MODF (Bitfield-Mask: 0x01) */ +#define SPIx_IER_SSERR_Pos (6UL) /*!< SSERR (Bit 6) */ +#define SPIx_IER_SSERR_Msk (0x40UL) /*!< SSERR (Bitfield-Mask: 0x01) */ +#define SPIx_IER_OV_Pos (5UL) /*!< OV (Bit 5) */ +#define SPIx_IER_OV_Msk (0x20UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define SPIx_IER_UD_Pos (4UL) /*!< UD (Bit 4) */ +#define SPIx_IER_UD_Msk (0x10UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define SPIx_IER_SSR_Pos (3UL) /*!< SSR (Bit 3) */ +#define SPIx_IER_SSR_Msk (0x8UL) /*!< SSR (Bitfield-Mask: 0x01) */ +#define SPIx_IER_SSF_Pos (2UL) /*!< SSF (Bit 2) */ +#define SPIx_IER_SSF_Msk (0x4UL) /*!< SSF (Bitfield-Mask: 0x01) */ +#define SPIx_IER_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define SPIx_IER_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define SPIx_IER_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define SPIx_IER_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define SPIx_ISR_SSLVL_Pos (9UL) /*!< SSLVL (Bit 9) */ +#define SPIx_ISR_SSLVL_Msk (0x200UL) /*!< SSLVL (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_BUSY_Pos (8UL) /*!< BUSY (Bit 8) */ +#define SPIx_ISR_BUSY_Msk (0x100UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_MODF_Pos (7UL) /*!< MODF (Bit 7) */ +#define SPIx_ISR_MODF_Msk (0x80UL) /*!< MODF (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_SSERR_Pos (6UL) /*!< SSERR (Bit 6) */ +#define SPIx_ISR_SSERR_Msk (0x40UL) /*!< SSERR (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_OV_Pos (5UL) /*!< OV (Bit 5) */ +#define SPIx_ISR_OV_Msk (0x20UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_UD_Pos (4UL) /*!< UD (Bit 4) */ +#define SPIx_ISR_UD_Msk (0x10UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_SSR_Pos (3UL) /*!< SSR (Bit 3) */ +#define SPIx_ISR_SSR_Msk (0x8UL) /*!< SSR (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_SSF_Pos (2UL) /*!< SSF (Bit 2) */ +#define SPIx_ISR_SSF_Msk (0x4UL) /*!< SSF (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define SPIx_ISR_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define SPIx_ISR_TXE_Pos (0UL) /*!< TXE (Bit 0) */ +#define SPIx_ISR_TXE_Msk (0x1UL) /*!< TXE (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define SPIx_ICR_MODF_Pos (7UL) /*!< MODF (Bit 7) */ +#define SPIx_ICR_MODF_Msk (0x80UL) /*!< MODF (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_SSERR_Pos (6UL) /*!< SSERR (Bit 6) */ +#define SPIx_ICR_SSERR_Msk (0x40UL) /*!< SSERR (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_OV_Pos (5UL) /*!< OV (Bit 5) */ +#define SPIx_ICR_OV_Msk (0x20UL) /*!< OV (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_UD_Pos (4UL) /*!< UD (Bit 4) */ +#define SPIx_ICR_UD_Msk (0x10UL) /*!< UD (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_SSR_Pos (3UL) /*!< SSR (Bit 3) */ +#define SPIx_ICR_SSR_Msk (0x8UL) /*!< SSR (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_SSF_Pos (2UL) /*!< SSF (Bit 2) */ +#define SPIx_ICR_SSF_Msk (0x4UL) /*!< SSF (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_RXNE_Pos (1UL) /*!< RXNE (Bit 1) */ +#define SPIx_ICR_RXNE_Msk (0x2UL) /*!< RXNE (Bitfield-Mask: 0x01) */ +#define SPIx_ICR_FLUSH_Pos (0UL) /*!< FLUSH (Bit 0) */ +#define SPIx_ICR_FLUSH_Msk (0x1UL) /*!< FLUSH (Bitfield-Mask: 0x01) */ +/* ========================================================== DR =========================================================== */ +#define SPIx_DR_DR_Pos (0UL) /*!< DR (Bit 0) */ +#define SPIx_DR_DR_Msk (0xffffUL) /*!< DR (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ SYSCTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define SYSCTRL_CR0_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_CR0_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_CR0_HCLKPRS_Pos (5UL) /*!< HCLKPRS (Bit 5) */ +#define SYSCTRL_CR0_HCLKPRS_Msk (0xe0UL) /*!< HCLKPRS (Bitfield-Mask: 0x07) */ +#define SYSCTRL_CR0_PCLKPRS_Pos (3UL) /*!< PCLKPRS (Bit 3) */ +#define SYSCTRL_CR0_PCLKPRS_Msk (0x18UL) /*!< PCLKPRS (Bitfield-Mask: 0x03) */ +#define SYSCTRL_CR0_SYSCLK_Pos (0UL) /*!< SYSCLK (Bit 0) */ +#define SYSCTRL_CR0_SYSCLK_Msk (0x7UL) /*!< SYSCLK (Bitfield-Mask: 0x07) */ +/* ========================================================== CR1 ========================================================== */ +#define SYSCTRL_CR1_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_CR1_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_CR1_CLKCCS_Pos (8UL) /*!< CLKCCS (Bit 8) */ +#define SYSCTRL_CR1_CLKCCS_Msk (0x100UL) /*!< CLKCCS (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_HSECCS_Pos (7UL) /*!< HSECCS (Bit 7) */ +#define SYSCTRL_CR1_HSECCS_Msk (0x80UL) /*!< HSECCS (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_LSECCS_Pos (6UL) /*!< LSECCS (Bit 6) */ +#define SYSCTRL_CR1_LSECCS_Msk (0x40UL) /*!< LSECCS (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_LSELOCK_Pos (5UL) /*!< LSELOCK (Bit 5) */ +#define SYSCTRL_CR1_LSELOCK_Msk (0x20UL) /*!< LSELOCK (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_LSEEN_Pos (4UL) /*!< LSEEN (Bit 4) */ +#define SYSCTRL_CR1_LSEEN_Msk (0x10UL) /*!< LSEEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_LSIEN_Pos (3UL) /*!< LSIEN (Bit 3) */ +#define SYSCTRL_CR1_LSIEN_Msk (0x8UL) /*!< LSIEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_PLLEN_Pos (2UL) /*!< PLLEN (Bit 2) */ +#define SYSCTRL_CR1_PLLEN_Msk (0x4UL) /*!< PLLEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_HSEEN_Pos (1UL) /*!< HSEEN (Bit 1) */ +#define SYSCTRL_CR1_HSEEN_Msk (0x2UL) /*!< HSEEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR1_HSIEN_Pos (0UL) /*!< HSIEN (Bit 0) */ +#define SYSCTRL_CR1_HSIEN_Msk (0x1UL) /*!< HSIEN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR2 ========================================================== */ +#define SYSCTRL_CR2_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_CR2_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_CR2_RAMBRKEN_Pos (15UL) /*!< RAMBRKEN (Bit 15) */ +#define SYSCTRL_CR2_RAMBRKEN_Msk (0x8000UL) /*!< RAMBRKEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_LVDBRKEN_Pos (14UL) /*!< LVDBRKEN (Bit 14) */ +#define SYSCTRL_CR2_LVDBRKEN_Msk (0x4000UL) /*!< LVDBRKEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_DSBRKEN_Pos (13UL) /*!< DSBRKEN (Bit 13) */ +#define SYSCTRL_CR2_DSBRKEN_Msk (0x2000UL) /*!< DSBRKEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_CLLBRKEN_Pos (12UL) /*!< CLLBRKEN (Bit 12) */ +#define SYSCTRL_CR2_CLLBRKEN_Msk (0x1000UL) /*!< CLLBRKEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_LSEBRKEN_Pos (11UL) /*!< LSEBRKEN (Bit 11) */ +#define SYSCTRL_CR2_LSEBRKEN_Msk (0x800UL) /*!< LSEBRKEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_HSEBRKEN_Pos (10UL) /*!< HSEBRKEN (Bit 10) */ +#define SYSCTRL_CR2_HSEBRKEN_Msk (0x400UL) /*!< HSEBRKEN (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_FLASHWAIT_Pos (4UL) /*!< FLASHWAIT (Bit 4) */ +#define SYSCTRL_CR2_FLASHWAIT_Msk (0x70UL) /*!< FLASHWAIT (Bitfield-Mask: 0x07) */ +#define SYSCTRL_CR2_WAKEUPCLK_Pos (3UL) /*!< WAKEUPCLK (Bit 3) */ +#define SYSCTRL_CR2_WAKEUPCLK_Msk (0x8UL) /*!< WAKEUPCLK (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_LOCKUP_Pos (2UL) /*!< LOCKUP (Bit 2) */ +#define SYSCTRL_CR2_LOCKUP_Msk (0x4UL) /*!< LOCKUP (Bitfield-Mask: 0x01) */ +#define SYSCTRL_CR2_SWDIO_Pos (1UL) /*!< SWDIO (Bit 1) */ +#define SYSCTRL_CR2_SWDIO_Msk (0x2UL) /*!< SWDIO (Bitfield-Mask: 0x01) */ +/* ========================================================== HSI ========================================================== */ +#define SYSCTRL_HSI_STABLE_Pos (15UL) /*!< STABLE (Bit 15) */ +#define SYSCTRL_HSI_STABLE_Msk (0x8000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSI_DIV_Pos (11UL) /*!< DIV (Bit 11) */ +#define SYSCTRL_HSI_DIV_Msk (0x7800UL) /*!< DIV (Bitfield-Mask: 0x0f) */ +#define SYSCTRL_HSI_TRIM_Pos (0UL) /*!< TRIM (Bit 0) */ +#define SYSCTRL_HSI_TRIM_Msk (0x7ffUL) /*!< TRIM (Bitfield-Mask: 0x7ff) */ +/* ========================================================== LSI ========================================================== */ +#define SYSCTRL_LSI_STABLE_Pos (15UL) /*!< STABLE (Bit 15) */ +#define SYSCTRL_LSI_STABLE_Msk (0x8000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_LSI_WAITCYCLE_Pos (10UL) /*!< WAITCYCLE (Bit 10) */ +#define SYSCTRL_LSI_WAITCYCLE_Msk (0xc00UL) /*!< WAITCYCLE (Bitfield-Mask: 0x03) */ +#define SYSCTRL_LSI_TRIM_Pos (0UL) /*!< TRIM (Bit 0) */ +#define SYSCTRL_LSI_TRIM_Msk (0x1ffUL) /*!< TRIM (Bitfield-Mask: 0x1ff) */ +/* ========================================================== HSE ========================================================== */ +#define SYSCTRL_HSE_DIGFLT_Pos (24UL) /*!< DIGFLT (Bit 24) */ +#define SYSCTRL_HSE_DIGFLT_Msk (0x1000000UL) /*!< DIGFLT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSE_PDRIVER_Pos (20UL) /*!< PDRIVER (Bit 20) */ +#define SYSCTRL_HSE_PDRIVER_Msk (0xf00000UL) /*!< PDRIVER (Bitfield-Mask: 0x0f) */ +#define SYSCTRL_HSE_STABLE_Pos (19UL) /*!< STABLE (Bit 19) */ +#define SYSCTRL_HSE_STABLE_Msk (0x80000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSE_DETCNT_Pos (8UL) /*!< DETCNT (Bit 8) */ +#define SYSCTRL_HSE_DETCNT_Msk (0x7ff00UL) /*!< DETCNT (Bitfield-Mask: 0x7ff) */ +#define SYSCTRL_HSE_HEXENPOL_Pos (7UL) /*!< HEXENPOL (Bit 7) */ +#define SYSCTRL_HSE_HEXENPOL_Msk (0x80UL) /*!< HEXENPOL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSE_MODE_Pos (6UL) /*!< MODE (Bit 6) */ +#define SYSCTRL_HSE_MODE_Msk (0x40UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_HSE_WAITCYCLE_Pos (4UL) /*!< WAITCYCLE (Bit 4) */ +#define SYSCTRL_HSE_WAITCYCLE_Msk (0x30UL) /*!< WAITCYCLE (Bitfield-Mask: 0x03) */ +#define SYSCTRL_HSE_DRIVER_Pos (0UL) /*!< DRIVER (Bit 0) */ +#define SYSCTRL_HSE_DRIVER_Msk (0xfUL) /*!< DRIVER (Bitfield-Mask: 0x0f) */ +/* ========================================================== LSE ========================================================== */ +#define SYSCTRL_LSE_STABLE_Pos (18UL) /*!< STABLE (Bit 18) */ +#define SYSCTRL_LSE_STABLE_Msk (0x40000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_LSE_PINLOCK_Pos (17UL) /*!< PINLOCK (Bit 17) */ +#define SYSCTRL_LSE_PINLOCK_Msk (0x20000UL) /*!< PINLOCK (Bitfield-Mask: 0x01) */ +#define SYSCTRL_LSE_PDRIVER_Pos (8UL) /*!< PDRIVER (Bit 8) */ +#define SYSCTRL_LSE_PDRIVER_Msk (0xf00UL) /*!< PDRIVER (Bitfield-Mask: 0x0f) */ +#define SYSCTRL_LSE_MODE_Pos (6UL) /*!< MODE (Bit 6) */ +#define SYSCTRL_LSE_MODE_Msk (0x40UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_LSE_WAITCYCLE_Pos (4UL) /*!< WAITCYCLE (Bit 4) */ +#define SYSCTRL_LSE_WAITCYCLE_Msk (0x30UL) /*!< WAITCYCLE (Bitfield-Mask: 0x03) */ +#define SYSCTRL_LSE_DRIVER_Pos (0UL) /*!< DRIVER (Bit 0) */ +#define SYSCTRL_LSE_DRIVER_Msk (0xfUL) /*!< DRIVER (Bitfield-Mask: 0x0f) */ +/* ========================================================== IER ========================================================== */ +#define SYSCTRL_IER_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_IER_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_IER_HSEFAULT_Pos (8UL) /*!< HSEFAULT (Bit 8) */ +#define SYSCTRL_IER_HSEFAULT_Msk (0x100UL) /*!< HSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_LSEFAULT_Pos (7UL) /*!< LSEFAULT (Bit 7) */ +#define SYSCTRL_IER_LSEFAULT_Msk (0x80UL) /*!< LSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_HSEFAIL_Pos (6UL) /*!< HSEFAIL (Bit 6) */ +#define SYSCTRL_IER_HSEFAIL_Msk (0x40UL) /*!< HSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_LSEFAIL_Pos (5UL) /*!< LSEFAIL (Bit 5) */ +#define SYSCTRL_IER_LSEFAIL_Msk (0x20UL) /*!< LSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_LSERDY_Pos (4UL) /*!< LSERDY (Bit 4) */ +#define SYSCTRL_IER_LSERDY_Msk (0x10UL) /*!< LSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_LSIRDY_Pos (3UL) /*!< LSIRDY (Bit 3) */ +#define SYSCTRL_IER_LSIRDY_Msk (0x8UL) /*!< LSIRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_PLLRDY_Pos (2UL) /*!< PLLRDY (Bit 2) */ +#define SYSCTRL_IER_PLLRDY_Msk (0x4UL) /*!< PLLRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_HSERDY_Pos (1UL) /*!< HSERDY (Bit 1) */ +#define SYSCTRL_IER_HSERDY_Msk (0x2UL) /*!< HSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_IER_HSIRDY_Pos (0UL) /*!< HSIRDY (Bit 0) */ +#define SYSCTRL_IER_HSIRDY_Msk (0x1UL) /*!< HSIRDY (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ +#define SYSCTRL_ISR_LSESTABLE_Pos (15UL) /*!< LSESTABLE (Bit 15) */ +#define SYSCTRL_ISR_LSESTABLE_Msk (0x8000UL) /*!< LSESTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSISTABLE_Pos (14UL) /*!< LSISTABLE (Bit 14) */ +#define SYSCTRL_ISR_LSISTABLE_Msk (0x4000UL) /*!< LSISTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_PLLSTABLE_Pos (13UL) /*!< PLLSTABLE (Bit 13) */ +#define SYSCTRL_ISR_PLLSTABLE_Msk (0x2000UL) /*!< PLLSTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSESTABLE_Pos (12UL) /*!< HSESTABLE (Bit 12) */ +#define SYSCTRL_ISR_HSESTABLE_Msk (0x1000UL) /*!< HSESTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSISTABLE_Pos (11UL) /*!< HSISTABLE (Bit 11) */ +#define SYSCTRL_ISR_HSISTABLE_Msk (0x800UL) /*!< HSISTABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSEFAULT_Pos (8UL) /*!< HSEFAULT (Bit 8) */ +#define SYSCTRL_ISR_HSEFAULT_Msk (0x100UL) /*!< HSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSEFAULT_Pos (7UL) /*!< LSEFAULT (Bit 7) */ +#define SYSCTRL_ISR_LSEFAULT_Msk (0x80UL) /*!< LSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSEFAIL_Pos (6UL) /*!< HSEFAIL (Bit 6) */ +#define SYSCTRL_ISR_HSEFAIL_Msk (0x40UL) /*!< HSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSEFAIL_Pos (5UL) /*!< LSEFAIL (Bit 5) */ +#define SYSCTRL_ISR_LSEFAIL_Msk (0x20UL) /*!< LSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSERDY_Pos (4UL) /*!< LSERDY (Bit 4) */ +#define SYSCTRL_ISR_LSERDY_Msk (0x10UL) /*!< LSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_LSIRDY_Pos (3UL) /*!< LSIRDY (Bit 3) */ +#define SYSCTRL_ISR_LSIRDY_Msk (0x8UL) /*!< LSIRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_PLLRDY_Pos (2UL) /*!< PLLRDY (Bit 2) */ +#define SYSCTRL_ISR_PLLRDY_Msk (0x4UL) /*!< PLLRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSERDY_Pos (1UL) /*!< HSERDY (Bit 1) */ +#define SYSCTRL_ISR_HSERDY_Msk (0x2UL) /*!< HSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ISR_HSIRDY_Pos (0UL) /*!< HSIRDY (Bit 0) */ +#define SYSCTRL_ISR_HSIRDY_Msk (0x1UL) /*!< HSIRDY (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define SYSCTRL_ICR_HSEFAULT_Pos (8UL) /*!< HSEFAULT (Bit 8) */ +#define SYSCTRL_ICR_HSEFAULT_Msk (0x100UL) /*!< HSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_LSEFAULT_Pos (7UL) /*!< LSEFAULT (Bit 7) */ +#define SYSCTRL_ICR_LSEFAULT_Msk (0x80UL) /*!< LSEFAULT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_HSEFAIL_Pos (6UL) /*!< HSEFAIL (Bit 6) */ +#define SYSCTRL_ICR_HSEFAIL_Msk (0x40UL) /*!< HSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_LSEFAIL_Pos (5UL) /*!< LSEFAIL (Bit 5) */ +#define SYSCTRL_ICR_LSEFAIL_Msk (0x20UL) /*!< LSEFAIL (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_LSERDY_Pos (4UL) /*!< LSERDY (Bit 4) */ +#define SYSCTRL_ICR_LSERDY_Msk (0x10UL) /*!< LSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_LSIRDY_Pos (3UL) /*!< LSIRDY (Bit 3) */ +#define SYSCTRL_ICR_LSIRDY_Msk (0x8UL) /*!< LSIRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_PLLRDY_Pos (2UL) /*!< PLLRDY (Bit 2) */ +#define SYSCTRL_ICR_PLLRDY_Msk (0x4UL) /*!< PLLRDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_HSERDY_Pos (1UL) /*!< HSERDY (Bit 1) */ +#define SYSCTRL_ICR_HSERDY_Msk (0x2UL) /*!< HSERDY (Bitfield-Mask: 0x01) */ +#define SYSCTRL_ICR_HSIRDY_Pos (0UL) /*!< HSIRDY (Bit 0) */ +#define SYSCTRL_ICR_HSIRDY_Msk (0x1UL) /*!< HSIRDY (Bitfield-Mask: 0x01) */ +/* ========================================================= AHBEN ========================================================= */ +#define SYSCTRL_AHBEN_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_AHBEN_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_AHBEN_CORDIC_Pos (8UL) /*!< CORDIC (Bit 8) */ +#define SYSCTRL_AHBEN_CORDIC_Msk (0x100UL) /*!< CORDIC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_GPIOF_Pos (7UL) /*!< GPIOF (Bit 7) */ +#define SYSCTRL_AHBEN_GPIOF_Msk (0x80UL) /*!< GPIOF (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_GPIOC_Pos (6UL) /*!< GPIOC (Bit 6) */ +#define SYSCTRL_AHBEN_GPIOC_Msk (0x40UL) /*!< GPIOC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_GPIOB_Pos (5UL) /*!< GPIOB (Bit 5) */ +#define SYSCTRL_AHBEN_GPIOB_Msk (0x20UL) /*!< GPIOB (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_GPIOA_Pos (4UL) /*!< GPIOA (Bit 4) */ +#define SYSCTRL_AHBEN_GPIOA_Msk (0x10UL) /*!< GPIOA (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_EAU_Pos (3UL) /*!< EAU (Bit 3) */ +#define SYSCTRL_AHBEN_EAU_Msk (0x8UL) /*!< EAU (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_CRC_Pos (2UL) /*!< CRC (Bit 2) */ +#define SYSCTRL_AHBEN_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_FLASH_Pos (1UL) /*!< FLASH (Bit 1) */ +#define SYSCTRL_AHBEN_FLASH_Msk (0x2UL) /*!< FLASH (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBEN_DMA_Pos (0UL) /*!< DMA (Bit 0) */ +#define SYSCTRL_AHBEN_DMA_Msk (0x1UL) /*!< DMA (Bitfield-Mask: 0x01) */ +/* ======================================================== APBEN1 ========================================================= */ +#define SYSCTRL_APBEN1_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_APBEN1_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_APBEN1_SPI3_Pos (14UL) /*!< SPI3 (Bit 14) */ +#define SYSCTRL_APBEN1_SPI3_Msk (0x4000UL) /*!< SPI3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_SPI2_Pos (13UL) /*!< SPI2 (Bit 13) */ +#define SYSCTRL_APBEN1_SPI2_Msk (0x2000UL) /*!< SPI2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_GTIM4_Pos (12UL) /*!< GTIM4 (Bit 12) */ +#define SYSCTRL_APBEN1_GTIM4_Msk (0x1000UL) /*!< GTIM4 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_GTIM3_Pos (11UL) /*!< GTIM3 (Bit 11) */ +#define SYSCTRL_APBEN1_GTIM3_Msk (0x800UL) /*!< GTIM3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_UART3_Pos (8UL) /*!< UART3 (Bit 8) */ +#define SYSCTRL_APBEN1_UART3_Msk (0x100UL) /*!< UART3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_GTIM2_Pos (7UL) /*!< GTIM2 (Bit 7) */ +#define SYSCTRL_APBEN1_GTIM2_Msk (0x80UL) /*!< GTIM2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_GTIM1_Pos (6UL) /*!< GTIM1 (Bit 6) */ +#define SYSCTRL_APBEN1_GTIM1_Msk (0x40UL) /*!< GTIM1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_ATIM_Pos (5UL) /*!< ATIM (Bit 5) */ +#define SYSCTRL_APBEN1_ATIM_Msk (0x20UL) /*!< ATIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_UART2_Pos (4UL) /*!< UART2 (Bit 4) */ +#define SYSCTRL_APBEN1_UART2_Msk (0x10UL) /*!< UART2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_UART1_Pos (3UL) /*!< UART1 (Bit 3) */ +#define SYSCTRL_APBEN1_UART1_Msk (0x8UL) /*!< UART1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_SPI1_Pos (2UL) /*!< SPI1 (Bit 2) */ +#define SYSCTRL_APBEN1_SPI1_Msk (0x4UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_VC_Pos (1UL) /*!< VC (Bit 1) */ +#define SYSCTRL_APBEN1_VC_Msk (0x2UL) /*!< VC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN1_ADC_Pos (0UL) /*!< ADC (Bit 0) */ +#define SYSCTRL_APBEN1_ADC_Msk (0x1UL) /*!< ADC (Bitfield-Mask: 0x01) */ +/* ======================================================== APBEN2 ========================================================= */ +#define SYSCTRL_APBEN2_KEY_Pos (16UL) /*!< KEY (Bit 16) */ +#define SYSCTRL_APBEN2_KEY_Msk (0xffff0000UL) /*!< KEY (Bitfield-Mask: 0xffff) */ +#define SYSCTRL_APBEN2_HALLTIM_Pos (12UL) /*!< HALLTIM (Bit 12) */ +#define SYSCTRL_APBEN2_HALLTIM_Msk (0x1000UL) /*!< HALLTIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_I2C2_Pos (11UL) /*!< I2C2 (Bit 11) */ +#define SYSCTRL_APBEN2_I2C2_Msk (0x800UL) /*!< I2C2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_DAC_Pos (10UL) /*!< DAC (Bit 10) */ +#define SYSCTRL_APBEN2_DAC_Msk (0x400UL) /*!< DAC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_OPA_Pos (9UL) /*!< OPA (Bit 9) */ +#define SYSCTRL_APBEN2_OPA_Msk (0x200UL) /*!< OPA (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_LPTIM_Pos (7UL) /*!< LPTIM (Bit 7) */ +#define SYSCTRL_APBEN2_LPTIM_Msk (0x80UL) /*!< LPTIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_I2C1_Pos (6UL) /*!< I2C1 (Bit 6) */ +#define SYSCTRL_APBEN2_I2C1_Msk (0x40UL) /*!< I2C1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_WWDT_Pos (5UL) /*!< WWDT (Bit 5) */ +#define SYSCTRL_APBEN2_WWDT_Msk (0x20UL) /*!< WWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_IWDT_Pos (4UL) /*!< IWDT (Bit 4) */ +#define SYSCTRL_APBEN2_IWDT_Msk (0x10UL) /*!< IWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_BTIM123_Pos (2UL) /*!< BTIM123 (Bit 2) */ +#define SYSCTRL_APBEN2_BTIM123_Msk (0x4UL) /*!< BTIM123 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBEN2_RTC_Pos (1UL) /*!< RTC (Bit 1) */ +#define SYSCTRL_APBEN2_RTC_Msk (0x2UL) /*!< RTC (Bitfield-Mask: 0x01) */ +/* ======================================================== AHBRST ========================================================= */ +#define SYSCTRL_AHBRST_CORDIC_Pos (8UL) /*!< CORDIC (Bit 8) */ +#define SYSCTRL_AHBRST_CORDIC_Msk (0x100UL) /*!< CORDIC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_GPIOF_Pos (7UL) /*!< GPIOF (Bit 7) */ +#define SYSCTRL_AHBRST_GPIOF_Msk (0x80UL) /*!< GPIOF (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_GPIOC_Pos (6UL) /*!< GPIOC (Bit 6) */ +#define SYSCTRL_AHBRST_GPIOC_Msk (0x40UL) /*!< GPIOC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_GPIOB_Pos (5UL) /*!< GPIOB (Bit 5) */ +#define SYSCTRL_AHBRST_GPIOB_Msk (0x20UL) /*!< GPIOB (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_GPIOA_Pos (4UL) /*!< GPIOA (Bit 4) */ +#define SYSCTRL_AHBRST_GPIOA_Msk (0x10UL) /*!< GPIOA (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_EAU_Pos (3UL) /*!< EAU (Bit 3) */ +#define SYSCTRL_AHBRST_EAU_Msk (0x8UL) /*!< EAU (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_CRC_Pos (2UL) /*!< CRC (Bit 2) */ +#define SYSCTRL_AHBRST_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_FLASH_Pos (1UL) /*!< FLASH (Bit 1) */ +#define SYSCTRL_AHBRST_FLASH_Msk (0x2UL) /*!< FLASH (Bitfield-Mask: 0x01) */ +#define SYSCTRL_AHBRST_DMA_Pos (0UL) /*!< DMA (Bit 0) */ +#define SYSCTRL_AHBRST_DMA_Msk (0x1UL) /*!< DMA (Bitfield-Mask: 0x01) */ +/* ======================================================== APBRST1 ======================================================== */ +#define SYSCTRL_APBRST1_SPI3_Pos (14UL) /*!< SPI3 (Bit 14) */ +#define SYSCTRL_APBRST1_SPI3_Msk (0x4000UL) /*!< SPI3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_SPI2_Pos (13UL) /*!< SPI2 (Bit 13) */ +#define SYSCTRL_APBRST1_SPI2_Msk (0x2000UL) /*!< SPI2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_GTIM4_Pos (12UL) /*!< GTIM4 (Bit 12) */ +#define SYSCTRL_APBRST1_GTIM4_Msk (0x1000UL) /*!< GTIM4 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_GTIM3_Pos (11UL) /*!< GTIM3 (Bit 11) */ +#define SYSCTRL_APBRST1_GTIM3_Msk (0x800UL) /*!< GTIM3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_UART3_Pos (8UL) /*!< UART3 (Bit 8) */ +#define SYSCTRL_APBRST1_UART3_Msk (0x100UL) /*!< UART3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_GTIM2_Pos (7UL) /*!< GTIM2 (Bit 7) */ +#define SYSCTRL_APBRST1_GTIM2_Msk (0x80UL) /*!< GTIM2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_GTIM1_Pos (6UL) /*!< GTIM1 (Bit 6) */ +#define SYSCTRL_APBRST1_GTIM1_Msk (0x40UL) /*!< GTIM1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_ATIM_Pos (5UL) /*!< ATIM (Bit 5) */ +#define SYSCTRL_APBRST1_ATIM_Msk (0x20UL) /*!< ATIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_UART2_Pos (4UL) /*!< UART2 (Bit 4) */ +#define SYSCTRL_APBRST1_UART2_Msk (0x10UL) /*!< UART2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_UART1_Pos (3UL) /*!< UART1 (Bit 3) */ +#define SYSCTRL_APBRST1_UART1_Msk (0x8UL) /*!< UART1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_SPI1_Pos (2UL) /*!< SPI1 (Bit 2) */ +#define SYSCTRL_APBRST1_SPI1_Msk (0x4UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_VC_Pos (1UL) /*!< VC (Bit 1) */ +#define SYSCTRL_APBRST1_VC_Msk (0x2UL) /*!< VC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST1_ADC_Pos (0UL) /*!< ADC (Bit 0) */ +#define SYSCTRL_APBRST1_ADC_Msk (0x1UL) /*!< ADC (Bitfield-Mask: 0x01) */ +/* ======================================================== APBRST2 ======================================================== */ +#define SYSCTRL_APBRST2_HALLTIM_Pos (12UL) /*!< HALLTIM (Bit 12) */ +#define SYSCTRL_APBRST2_HALLTIM_Msk (0x1000UL) /*!< HALLTIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_I2C2_Pos (11UL) /*!< I2C2 (Bit 11) */ +#define SYSCTRL_APBRST2_I2C2_Msk (0x800UL) /*!< I2C2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_DAC_Pos (10UL) /*!< DAC (Bit 10) */ +#define SYSCTRL_APBRST2_DAC_Msk (0x400UL) /*!< DAC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_OPA_Pos (9UL) /*!< OPA (Bit 9) */ +#define SYSCTRL_APBRST2_OPA_Msk (0x200UL) /*!< OPA (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_LPTIM_Pos (7UL) /*!< LPTIM (Bit 7) */ +#define SYSCTRL_APBRST2_LPTIM_Msk (0x80UL) /*!< LPTIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_I2C1_Pos (6UL) /*!< I2C1 (Bit 6) */ +#define SYSCTRL_APBRST2_I2C1_Msk (0x40UL) /*!< I2C1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_WWDT_Pos (5UL) /*!< WWDT (Bit 5) */ +#define SYSCTRL_APBRST2_WWDT_Msk (0x20UL) /*!< WWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_IWDT_Pos (4UL) /*!< IWDT (Bit 4) */ +#define SYSCTRL_APBRST2_IWDT_Msk (0x10UL) /*!< IWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_BTIM123_Pos (2UL) /*!< BTIM123 (Bit 2) */ +#define SYSCTRL_APBRST2_BTIM123_Msk (0x4UL) /*!< BTIM123 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_APBRST2_RTC_Pos (1UL) /*!< RTC (Bit 1) */ +#define SYSCTRL_APBRST2_RTC_Msk (0x2UL) /*!< RTC (Bitfield-Mask: 0x01) */ +/* ======================================================= RESETFLAG ======================================================= */ +#define SYSCTRL_RESETFLAG_SYSRESETREQ_Pos (9UL) /*!< SYSRESETREQ (Bit 9) */ +#define SYSCTRL_RESETFLAG_SYSRESETREQ_Msk (0x200UL) /*!< SYSRESETREQ (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_LOCKUP_Pos (8UL) /*!< LOCKUP (Bit 8) */ +#define SYSCTRL_RESETFLAG_LOCKUP_Msk (0x100UL) /*!< LOCKUP (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_RSTB_Pos (6UL) /*!< RSTB (Bit 6) */ +#define SYSCTRL_RESETFLAG_RSTB_Msk (0x40UL) /*!< RSTB (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_WWDT_Pos (5UL) /*!< WWDT (Bit 5) */ +#define SYSCTRL_RESETFLAG_WWDT_Msk (0x20UL) /*!< WWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_IWDT_Pos (4UL) /*!< IWDT (Bit 4) */ +#define SYSCTRL_RESETFLAG_IWDT_Msk (0x10UL) /*!< IWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_LVD_Pos (3UL) /*!< LVD (Bit 3) */ +#define SYSCTRL_RESETFLAG_LVD_Msk (0x8UL) /*!< LVD (Bitfield-Mask: 0x01) */ +#define SYSCTRL_RESETFLAG_POR_Pos (0UL) /*!< POR (Bit 0) */ +#define SYSCTRL_RESETFLAG_POR_Msk (0x1UL) /*!< POR (Bitfield-Mask: 0x01) */ +/* ========================================================= DEBUG ========================================================= */ +#define SYSCTRL_DEBUG_HALLTIM_Pos (11UL) /*!< HALLTIM (Bit 11) */ +#define SYSCTRL_DEBUG_HALLTIM_Msk (0x800UL) /*!< HALLTIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_WWDT_Pos (10UL) /*!< WWDT (Bit 10) */ +#define SYSCTRL_DEBUG_WWDT_Msk (0x400UL) /*!< WWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_IWDT_Pos (9UL) /*!< IWDT (Bit 9) */ +#define SYSCTRL_DEBUG_IWDT_Msk (0x200UL) /*!< IWDT (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_RTC_Pos (8UL) /*!< RTC (Bit 8) */ +#define SYSCTRL_DEBUG_RTC_Msk (0x100UL) /*!< RTC (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_LPTIM_Pos (6UL) /*!< LPTIM (Bit 6) */ +#define SYSCTRL_DEBUG_LPTIM_Msk (0x40UL) /*!< LPTIM (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_BTIM123_Pos (5UL) /*!< BTIM123 (Bit 5) */ +#define SYSCTRL_DEBUG_BTIM123_Msk (0x20UL) /*!< BTIM123 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_GTIM4_Pos (4UL) /*!< GTIM4 (Bit 4) */ +#define SYSCTRL_DEBUG_GTIM4_Msk (0x10UL) /*!< GTIM4 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_GTIM3_Pos (3UL) /*!< GTIM3 (Bit 3) */ +#define SYSCTRL_DEBUG_GTIM3_Msk (0x8UL) /*!< GTIM3 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_GTIM2_Pos (2UL) /*!< GTIM2 (Bit 2) */ +#define SYSCTRL_DEBUG_GTIM2_Msk (0x4UL) /*!< GTIM2 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_GTIM1_Pos (1UL) /*!< GTIM1 (Bit 1) */ +#define SYSCTRL_DEBUG_GTIM1_Msk (0x2UL) /*!< GTIM1 (Bitfield-Mask: 0x01) */ +#define SYSCTRL_DEBUG_ATIM_Pos (0UL) /*!< ATIM (Bit 0) */ +#define SYSCTRL_DEBUG_ATIM_Msk (0x1UL) /*!< ATIM (Bitfield-Mask: 0x01) */ +/* ========================================================== MCO ========================================================== */ +#define SYSCTRL_MCO_DIV_Pos (4UL) /*!< DIV (Bit 4) */ +#define SYSCTRL_MCO_DIV_Msk (0xf0UL) /*!< DIV (Bitfield-Mask: 0x0f) */ +#define SYSCTRL_MCO_SOURCE_Pos (0UL) /*!< SOURCE (Bit 0) */ +#define SYSCTRL_MCO_SOURCE_Msk (0xfUL) /*!< SOURCE (Bitfield-Mask: 0x0f) */ +/* ========================================================== PLL ========================================================== */ +#define SYSCTRL_PLL_STABLE_Pos (16UL) /*!< STABLE (Bit 16) */ +#define SYSCTRL_PLL_STABLE_Msk (0x10000UL) /*!< STABLE (Bitfield-Mask: 0x01) */ +#define SYSCTRL_PLL_MUL_Pos (8UL) /*!< MUL (Bit 8) */ +#define SYSCTRL_PLL_MUL_Msk (0xff00UL) /*!< MUL (Bitfield-Mask: 0xff) */ +#define SYSCTRL_PLL_WAITCYCLE_Pos (5UL) /*!< WAITCYCLE (Bit 5) */ +#define SYSCTRL_PLL_WAITCYCLE_Msk (0xe0UL) /*!< WAITCYCLE (Bitfield-Mask: 0x07) */ +#define SYSCTRL_PLL_DIV_Pos (1UL) /*!< DIV (Bit 1) */ +#define SYSCTRL_PLL_DIV_Msk (0x1eUL) /*!< DIV (Bitfield-Mask: 0x0f) */ +#define SYSCTRL_PLL_SOURCE_Pos (0UL) /*!< SOURCE (Bit 0) */ +#define SYSCTRL_PLL_SOURCE_Msk (0x1UL) /*!< SOURCE (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ VC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define VCx_CR0_INP_Pos (12UL) /*!< INP (Bit 12) */ +#define VCx_CR0_INP_Msk (0x3000UL) /*!< INP (Bitfield-Mask: 0x03) */ +#define VCx_CR0_INN_Pos (8UL) /*!< INN (Bit 8) */ +#define VCx_CR0_INN_Msk (0x300UL) /*!< INN (Bitfield-Mask: 0x03) */ +#define VCx_CR0_WINDOW_Pos (7UL) /*!< WINDOW (Bit 7) */ +#define VCx_CR0_WINDOW_Msk (0x80UL) /*!< WINDOW (Bitfield-Mask: 0x01) */ +#define VCx_CR0_POL_Pos (6UL) /*!< POL (Bit 6) */ +#define VCx_CR0_POL_Msk (0x40UL) /*!< POL (Bitfield-Mask: 0x01) */ +#define VCx_CR0_IE_Pos (5UL) /*!< IE (Bit 5) */ +#define VCx_CR0_IE_Msk (0x20UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define VCx_CR0_HYS_Pos (3UL) /*!< HYS (Bit 3) */ +#define VCx_CR0_HYS_Msk (0x8UL) /*!< HYS (Bitfield-Mask: 0x01) */ +#define VCx_CR0_RESP_Pos (1UL) /*!< RESP (Bit 1) */ +#define VCx_CR0_RESP_Msk (0x2UL) /*!< RESP (Bitfield-Mask: 0x01) */ +#define VCx_CR0_EN_Pos (0UL) /*!< EN (Bit 0) */ +#define VCx_CR0_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ +#define VCx_CR1_BLANKLVL_Pos (11UL) /*!< BLANKLVL (Bit 11) */ +#define VCx_CR1_BLANKLVL_Msk (0x800UL) /*!< BLANKLVL (Bitfield-Mask: 0x01) */ +#define VCx_CR1_BLANKTIME_Pos (8UL) /*!< BLANKTIME (Bit 8) */ +#define VCx_CR1_BLANKTIME_Msk (0x700UL) /*!< BLANKTIME (Bitfield-Mask: 0x07) */ +#define VCx_CR1_HIGHIE_Pos (7UL) /*!< HIGHIE (Bit 7) */ +#define VCx_CR1_HIGHIE_Msk (0x80UL) /*!< HIGHIE (Bitfield-Mask: 0x01) */ +#define VCx_CR1_RISEIE_Pos (6UL) /*!< RISEIE (Bit 6) */ +#define VCx_CR1_RISEIE_Msk (0x40UL) /*!< RISEIE (Bitfield-Mask: 0x01) */ +#define VCx_CR1_FALLIE_Pos (5UL) /*!< FALLIE (Bit 5) */ +#define VCx_CR1_FALLIE_Msk (0x20UL) /*!< FALLIE (Bitfield-Mask: 0x01) */ +#define VCx_CR1_FLTCLK_Pos (4UL) /*!< FLTCLK (Bit 4) */ +#define VCx_CR1_FLTCLK_Msk (0x10UL) /*!< FLTCLK (Bitfield-Mask: 0x01) */ +#define VCx_CR1_FLTTIME_Pos (0UL) /*!< FLTTIME (Bit 0) */ +#define VCx_CR1_FLTTIME_Msk (0xfUL) /*!< FLTTIME (Bitfield-Mask: 0x0f) */ +/* ========================================================== CR2 ========================================================== */ +#define VCx_CR2_HALLTIM1TRGO_Pos (31UL) /*!< HALLTIM1TRGO (Bit 31) */ +#define VCx_CR2_HALLTIM1TRGO_Msk (0x80000000UL) /*!< HALLTIM1TRGO (Bitfield-Mask: 0x01) */ +#define VCx_CR2_BTIM3TRGO_Pos (30UL) /*!< BTIM3TRGO (Bit 30) */ +#define VCx_CR2_BTIM3TRGO_Msk (0x40000000UL) /*!< BTIM3TRGO (Bitfield-Mask: 0x01) */ +#define VCx_CR2_BTIM2TRGO_Pos (29UL) /*!< BTIM2TRGO (Bit 29) */ +#define VCx_CR2_BTIM2TRGO_Msk (0x20000000UL) /*!< BTIM2TRGO (Bitfield-Mask: 0x01) */ +#define VCx_CR2_BTIM1TRGO_Pos (28UL) /*!< BTIM1TRGO (Bit 28) */ +#define VCx_CR2_BTIM1TRGO_Msk (0x10000000UL) /*!< BTIM1TRGO (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM4OC4REFC_Pos (27UL) /*!< GTIM4OC4REFC (Bit 27) */ +#define VCx_CR2_GTIM4OC4REFC_Msk (0x8000000UL) /*!< GTIM4OC4REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM4OC3REFC_Pos (26UL) /*!< GTIM4OC3REFC (Bit 26) */ +#define VCx_CR2_GTIM4OC3REFC_Msk (0x4000000UL) /*!< GTIM4OC3REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM4OC2REFC_Pos (25UL) /*!< GTIM4OC2REFC (Bit 25) */ +#define VCx_CR2_GTIM4OC2REFC_Msk (0x2000000UL) /*!< GTIM4OC2REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM4OC1REFC_Pos (24UL) /*!< GTIM4OC1REFC (Bit 24) */ +#define VCx_CR2_GTIM4OC1REFC_Msk (0x1000000UL) /*!< GTIM4OC1REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM4TRGO_Pos (23UL) /*!< GTIM4TRGO (Bit 23) */ +#define VCx_CR2_GTIM4TRGO_Msk (0x800000UL) /*!< GTIM4TRGO (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM3OC4REFC_Pos (22UL) /*!< GTIM3OC4REFC (Bit 22) */ +#define VCx_CR2_GTIM3OC4REFC_Msk (0x400000UL) /*!< GTIM3OC4REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM3OC3REFC_Pos (21UL) /*!< GTIM3OC3REFC (Bit 21) */ +#define VCx_CR2_GTIM3OC3REFC_Msk (0x200000UL) /*!< GTIM3OC3REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM3OC2REFC_Pos (20UL) /*!< GTIM3OC2REFC (Bit 20) */ +#define VCx_CR2_GTIM3OC2REFC_Msk (0x100000UL) /*!< GTIM3OC2REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM3OC1REFC_Pos (19UL) /*!< GTIM3OC1REFC (Bit 19) */ +#define VCx_CR2_GTIM3OC1REFC_Msk (0x80000UL) /*!< GTIM3OC1REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM3TRGO_Pos (18UL) /*!< GTIM3TRGO (Bit 18) */ +#define VCx_CR2_GTIM3TRGO_Msk (0x40000UL) /*!< GTIM3TRGO (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM2OC4REFC_Pos (17UL) /*!< GTIM2OC4REFC (Bit 17) */ +#define VCx_CR2_GTIM2OC4REFC_Msk (0x20000UL) /*!< GTIM2OC4REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM2OC3REFC_Pos (16UL) /*!< GTIM2OC3REFC (Bit 16) */ +#define VCx_CR2_GTIM2OC3REFC_Msk (0x10000UL) /*!< GTIM2OC3REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM2OC2REFC_Pos (15UL) /*!< GTIM2OC2REFC (Bit 15) */ +#define VCx_CR2_GTIM2OC2REFC_Msk (0x8000UL) /*!< GTIM2OC2REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM2OC1REFC_Pos (14UL) /*!< GTIM2OC1REFC (Bit 14) */ +#define VCx_CR2_GTIM2OC1REFC_Msk (0x4000UL) /*!< GTIM2OC1REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM2TRGO_Pos (13UL) /*!< GTIM2TRGO (Bit 13) */ +#define VCx_CR2_GTIM2TRGO_Msk (0x2000UL) /*!< GTIM2TRGO (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM1OC4REFC_Pos (12UL) /*!< GTIM1OC4REFC (Bit 12) */ +#define VCx_CR2_GTIM1OC4REFC_Msk (0x1000UL) /*!< GTIM1OC4REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM1OC3REFC_Pos (11UL) /*!< GTIM1OC3REFC (Bit 11) */ +#define VCx_CR2_GTIM1OC3REFC_Msk (0x800UL) /*!< GTIM1OC3REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM1OC2REFC_Pos (10UL) /*!< GTIM1OC2REFC (Bit 10) */ +#define VCx_CR2_GTIM1OC2REFC_Msk (0x400UL) /*!< GTIM1OC2REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM1OC1REFC_Pos (9UL) /*!< GTIM1OC1REFC (Bit 9) */ +#define VCx_CR2_GTIM1OC1REFC_Msk (0x200UL) /*!< GTIM1OC1REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_GTIM1TRGO_Pos (8UL) /*!< GTIM1TRGO (Bit 8) */ +#define VCx_CR2_GTIM1TRGO_Msk (0x100UL) /*!< GTIM1TRGO (Bitfield-Mask: 0x01) */ +#define VCx_CR2_ATIMOC6REFC_Pos (7UL) /*!< ATIM1OC6REFC (Bit 7) */ +#define VCx_CR2_ATIMOC6REFC_Msk (0x80UL) /*!< ATIM1OC6REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_ATIMOC5REFC_Pos (6UL) /*!< ATIM1OC5REFC (Bit 6) */ +#define VCx_CR2_ATIMOC5REFC_Msk (0x40UL) /*!< ATIM1OC5REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_ATIMOC4REFC_Pos (5UL) /*!< ATIM1OC4REFC (Bit 5) */ +#define VCx_CR2_ATIMOC4REFC_Msk (0x20UL) /*!< ATIM1OC4REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_ATIMOC3REFC_Pos (4UL) /*!< ATIM1OC3REFC (Bit 4) */ +#define VCx_CR2_ATIMOC3REFC_Msk (0x10UL) /*!< ATIM1OC3REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_ATIMOC2REFC_Pos (3UL) /*!< ATIM1OC2REFC (Bit 3) */ +#define VCx_CR2_ATIMOC2REFC_Msk (0x8UL) /*!< ATIM1OC2REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_ATIMOC1REFC_Pos (2UL) /*!< ATIM1OC1REFC (Bit 2) */ +#define VCx_CR2_ATIMOC1REFC_Msk (0x4UL) /*!< ATIM1OC1REFC (Bitfield-Mask: 0x01) */ +#define VCx_CR2_ATIMTRGO2_Pos (1UL) /*!< ATIM1TRGO2 (Bit 1) */ +#define VCx_CR2_ATIMTRGO2_Msk (0x2UL) /*!< ATIM1TRGO2 (Bitfield-Mask: 0x01) */ +#define VCx_CR2_ATIMTRGO_Pos (0UL) /*!< ATIM1TRGO (Bit 0) */ +#define VCx_CR2_ATIMTRGO_Msk (0x1UL) /*!< ATIM1TRGO (Bitfield-Mask: 0x01) */ +/* ========================================================== SR =========================================================== */ +#define VCx_SR_FLTV_Pos (1UL) /*!< FLTV (Bit 1) */ +#define VCx_SR_FLTV_Msk (0x2UL) /*!< FLTV (Bitfield-Mask: 0x01) */ +#define VCx_SR_INTF_Pos (0UL) /*!< INTF (Bit 0) */ +#define VCx_SR_INTF_Msk (0x1UL) /*!< INTF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ VCREF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DIV ========================================================== */ +#define VC12REF_DIV_VIN_Pos (5UL) /*!< VIN (Bit 5) */ +#define VC12REF_DIV_VIN_Msk (0x20UL) /*!< VIN (Bitfield-Mask: 0x01) */ +#define VC12REF_DIV_EN_Pos (4UL) /*!< EN (Bit 4) */ +#define VC12REF_DIV_EN_Msk (0x10UL) /*!< EN (Bitfield-Mask: 0x01) */ +#define VC12REF_DIV_DIV_Pos (0UL) /*!< DIV (Bit 0) */ +#define VC12REF_DIV_DIV_Msk (0x7UL) /*!< DIV (Bitfield-Mask: 0x07) */ + + +/* =========================================================================================================================== */ +/* ================ WWDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define WWDT_CR0_EN_Pos (7UL) /*!< EN (Bit 7) */ +#define WWDT_CR0_EN_Msk (0x80UL) /*!< EN (Bitfield-Mask: 0x01) */ +#define WWDT_CR0_WCNT_Pos (0UL) /*!< WCNT (Bit 0) */ +#define WWDT_CR0_WCNT_Msk (0x7fUL) /*!< WCNT (Bitfield-Mask: 0x7f) */ +/* ========================================================== CR1 ========================================================== */ +#define WWDT_CR1_IE_Pos (10UL) /*!< IE (Bit 10) */ +#define WWDT_CR1_IE_Msk (0x400UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define WWDT_CR1_PRS_Pos (7UL) /*!< PRS (Bit 7) */ +#define WWDT_CR1_PRS_Msk (0x380UL) /*!< PRS (Bitfield-Mask: 0x07) */ +#define WWDT_CR1_WINR_Pos (0UL) /*!< WINR (Bit 0) */ +#define WWDT_CR1_WINR_Msk (0x7fUL) /*!< WINR (Bitfield-Mask: 0x7f) */ +/* ========================================================== SR =========================================================== */ +#define WWDT_SR_POV_Pos (0UL) /*!< POV (Bit 0) */ +#define WWDT_SR_POV_Msk (0x1UL) /*!< POV (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CW32L012_H */ + + +/** @} */ /* End of group cw32l012 */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_adc.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_adc.h new file mode 100644 index 0000000..cbfef31 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_adc.h @@ -0,0 +1,494 @@ +/** +* @file cw32l012_adc.h +* @author WHXY +* @brief +* @version 0.1 +* @date 2024-08-07 +* +* @copyright Copyright (c) 2021 +* +*/ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +#ifndef __CW32L012_ADC_H +#define __CW32L012_ADC_H + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "system_cw32l012.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup AdcGroup AD Converter (ADC) + ** + ******************************************************************************/ + + +/****************************************************************************** + * Extern type definitions ('typedef') * + ******************************************************************************/ + +/** + ****************************************************************************** + ** @brief ADC配置 + *****************************************************************************/ +typedef struct +{ + uint32_t ADC_SampTime; /*单通道ADC采样保持时间*/ + uint32_t ADC_InputChannel; /*通道选择 */ +} ADC_ChannelTypeDef; + +typedef struct +{ + uint32_t ADC_ClkDiv; /*ADC时钟分频选择*/ + + uint32_t ADC_ConvertMode; /*ADC转换模式选择*/ + + uint32_t ADC_SlaveMod; /*ADC主从选择 */ + + uint32_t ADC_SQREns; /*ADC转换通道配置*/ + + ADC_ChannelTypeDef ADC_IN0; /*ADC 通道0配置*/ + + ADC_ChannelTypeDef ADC_IN1; /*ADC 通道1配置*/ + + ADC_ChannelTypeDef ADC_IN2; /*ADC 通道2配置*/ + + ADC_ChannelTypeDef ADC_IN3; /*ADC 通道3配置*/ + + ADC_ChannelTypeDef ADC_IN4; /*ADC 通道4配置*/ + + ADC_ChannelTypeDef ADC_IN5; /*ADC 通道5配置*/ + + ADC_ChannelTypeDef ADC_IN6; /*ADC 通道6配置*/ + + ADC_ChannelTypeDef ADC_IN7; /*ADC 通道7配置*/ + +} ADC_InitTypeDef; + +/** + ****************************************************************************** + ** @brief ADC模拟看门狗配置 + *****************************************************************************/ +typedef struct +{ + ADC_InitTypeDef ADC_InitStruct; /*ADC通用初始化配置*/ + + uint32_t ADC_WatchdogCHx; /*ADC模拟看门狗通道*/ + + uint32_t ADC_WatchdogVth; /*ADC模拟看门狗上超出门限*/ + + uint32_t ADC_WatchdogVtl; /*ADC模拟看门狗下超出门限*/ + + uint32_t ADC_WatchdogOverHighIrq; /*ADC模拟看门狗上超出门限中断使能*/ + + uint32_t ADC_WatchdogUnderLowIrq; /*ADC模拟看门狗下超出门限中断使能*/ +} ADC_WatchdogTypeDef; + + +/** + ****************************************************************************** + ** @brief ADC中断配置 + *****************************************************************************/ +typedef struct +{ + boolean_t ADC_WdthIrq; /*ADC模拟看门狗上阈值中断*/ + + boolean_t ADC_WdtlIrq; /*ADC模拟看门狗下阈值中断*/ + + boolean_t ADC_EosIrq; /*ADC序列转换完成中断*/ + + boolean_t ADC_EocIrq; /*ADC单次转换完成中断*/ +} ADC_IrqTypeDef; + +// 定义ADC DMA触发配置结构体 +typedef struct { + boolean_t dma_eoc_enable; // 每次转换完成DMA触发使能 + boolean_t dma_eos_enable; // 序列转换完成DMA触发使能 +} ADC_DMA_TriggerTypeDef; +//@{ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#ifndef ADC_WAIT_TIMEOUT +#define ADC_WAIT_TIMEOUT 5000U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +#define ADC_INT_PRIORITY ((uint32_t)3) /*ADC interrupt priority (lowest by default) */ + +#define COEFF_TS (0.095765f) +#define ADC_BGR_VOL_ADDRESS (0x001007D2) +#define ADC_TS_T0_ADDRESS (0x001007CD) +#define ADC_TS_TRIM_ADDRESS (0x001007CE) + +/** + * @} + */ + +/** @defgroup ADC_ConvertMode + * @{ + */ +#define ADC_ConvertMode_Once (0UL << ADCx_CR_CONT_Pos) +#define ADC_ConvertMode_Continuous (1UL << ADCx_CR_CONT_Pos) + +#define IS_ADC_CONV_MODE(MODE) (((MODE) == ADC_ConvertMode_Single) || \ + ((MODE) == ADC_ConvertMode_Continuous)) + +/** @defgroup ADC_SlaveMod + * @{ + */ +#define ADC_SlaveMode_Enable (1UL << ADCx_CR_SLAVE_Pos) +#define ADC_SlaveMode_Disable (0UL << ADCx_CR_SLAVE_Pos) + +#define IS_ADC_CONV_MODE(MODE) (((MODE) == ADC_ConvertMode_Single) || \ + ((MODE) == ADC_ConvertMode_Continuous)) + + +/** @defgroup ADC_ClkDiv + * @{ + */ +#define ADC_Clk_Div1 ((uint32_t)0) +#define ADC_Clk_Div2 ((uint32_t)(1U<= 1)) + + +/* BTIM_Mode */ +#define BTIM_MODE_TIMER ((uint16_t)0x0000) +#define BTIM_MODE_COUNTER ((uint16_t)0x0003) +#define BTIM_MODE_TRIGGER ((uint16_t)0x0001) +#define BTIM_MODE_GATE ((uint16_t)0x0002) +#define IS_BTIM_MODE(MODE) (((MODE) == BTIM_MODE_TIMER) || \ + ((MODE) == BTIM_MODE_COUNTER) || \ + ((MODE) == BTIM_MODE_TRIGGER) || \ + ((MODE) == BTIM_MODE_GATE)) +/* BTIM TOG */ +#define BTIM_TOGGLE_ENABLE (0x8000) +#define BTIM_TOGGLE_DISABLE (0x0000) + +/* BTIM UPDATE REMAP */ +#define BTIM_UPDATE_REMAP_ENABLE (0x0800) +#define BTIM_UPDATE_REMAP_DISABLE (0x0000) + +/* BTIM ETR 滤波时钟分频系数 */ +#define BTIM_ETR_FLITER_PCLK_DIV1 (0x0000) +#define BTIM_ETR_FLITER_PCLK_DIV2 (0x0100) +#define BTIM_ETR_FLITER_PCLK_DIV4 (0x0200) +#define IS_BTIM_ETR_FILTER_DIV(DIV) (((DIV) == BTIM_ETR_FLITER_PCLK_DIV1) || \ + ((DIV) == BTIM_ETR_FLITER_PCLK_DIV2) || \ + ((DIV) == BTIM_ETR_FLITER_PCLK_DIV4)) + +/* BTIM_External_Trigger_Filter */ +#define BTIM_ETR_FILTER_NONE (0U) +#define BTIM_ETR_FILTER_DIV1_N2 (1U<<12) +#define BTIM_ETR_FILTER_DIV1_N4 (2U<<12) +#define BTIM_ETR_FILTER_DIV1_N6 (3U<<12) +#define BTIM_ETR_FILTER_DIV4_N4 (4U<<12) +#define BTIM_ETR_FILTER_DIV4_N6 (5U<<12) +#define BTIM_ETR_FILTER_DIV16_N4 (6U<<12) +#define BTIM_ETR_FILTER_DIV16_N6 (7U<<12) +#define IS_BTIM_ETR_FILTER(EXTFILTER) (((EXTFILTER) == BTIM_ETR_FILTER_NONE) || \ + ((EXTFILTER) == BTIM_ETR_FILTER_DIV1_N2) || \ + ((EXTFILTER) == BTIM_ETR_FILTER_DIV1_N4) || \ + ((EXTFILTER) == BTIM_ETR_FILTER_DIV1_N6) || \ + ((EXTFILTER) == BTIM_ETR_FILTER_DIV4_N4) || \ + ((EXTFILTER) == BTIM_ETR_FILTER_DIV4_N6) || \ + ((EXTFILTER) == BTIM_ETR_FILTER_DIV16_N4) || \ + ((EXTFILTER) == BTIM_ETR_FILTER_DIV16_N6)) + +/* BTIM ARR 缓存 */ +#define BTIM_ARR_PRELOAD_ENABLE (0x0080) +#define BTIM_ARR_PRELOAD_DISABLE (0x0000) +#define IS_BTIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == BTIM_ARR_PRELOAD_ENABLE) || ((PRELOAD) == BTIM_ARR_PRELOAD_DISABLE)) + +/* BTIM 更新源 */ +#define BTIM_UPDATE_REQUEST_SOURCE_OVERFLOW (0x0004) +#define BTIM_UPDATE_REQUEST_SOURCE_FLEXIBLE (0x0000) +#define IS_BTIM_UPDATE_REQUEST(SOURCE) (((SOURCE) == BTIM_UPDATE_REQUEST_SOURCE_OVERFLOW) || ((SOURCE) == BTIM_UPDATE_REQUEST_SOURCE_FLEXIBLE)) + +/* BTIM_interrupt_sources */ +#define BTIM_IT_UPDATE ((uint16_t)0x0001) +#define BTIM_IT_TI ((uint16_t)0x0040) +#define IS_BTIM_IT(IT) (((IT) == BTIM_IT_UPDATE) || ((IT) == BTIM_IT_TI)) + +#define IS_BTIM_GET_IT(IT) (((IT) == BTIM_IT_UPDATE) || ((IT) == BTIM_IT_TI)) + +/* BTIM event source */ +#define BTIM_EVENTSOURCE_TRIG (0x00000040) +#define BTIM_EVENTSOURCE_UPDATE (0x00000001) +#define IS_BTIM_EVENTSOURCE(SOURCE) (((SOURCE) == BTIM_EVENTSOURCE_TRIG) || ((SOURCE) == BTIM_EVENTSOURCE_UPDATE)) + +/* BTIM Trigger source */ +#define BTIM_TS_AWT_OV (0U<<7) +#define BTIM_TS_LVD_OUT (1U<<7) +#define BTIM_TS_VCx_OUT (2U<<7) +#define BTIM_TS_SPI_NCS (3U<<7) +#define BTIM_TS_I2C_SCL (4U<<7) +#define BTIM_TS_UARTx_RXD (5U<<7) +#define BTIM_TS_RTC_OUT (6U<<7) +#define BTIM_TS_ATIM1_TRGO (7U<<7) +#define BTIM_TS_BTIM1_TRGO (8U<<7) +#define BTIM_TS_BTIM2_TRGO (9U<<7) +#define BTIM_TS_BTIM3_TRGO (10U<<7) +#define BTIM_TS_GTIM1_TRGO (11U<<7) +#define BTIM_TS_GTIM2_TRGO (12U<<7) +#define BTIM_TS_BTIMx_ETR (15U<<7) +#define IS_BTIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == BTIM_TS_AWT_OV) || \ + ((SELECTION) == BTIM_TS_LVD_OUT) || \ + ((SELECTION) == BTIM_TS_VCx_OUT) || \ + ((SELECTION) == BTIM_TS_SPI_NCS) || \ + ((SELECTION) == BTIM_TS_I2C_SCL) || \ + ((SELECTION) == BTIM_TS_UARTx_RXD) || \ + ((SELECTION) == BTIM_TS_RTC_OUT) || \ + ((SELECTION) == BTIM_TS_ATIM1_TRGO) || \ + ((SELECTION) == BTIM_TS_BTIM1_TRGO) || \ + ((SELECTION) == BTIM_TS_BTIM2_TRGO) || \ + ((SELECTION) == BTIM_TS_BTIM3_TRGO) || \ + ((SELECTION) == BTIM_TS_GTIM1_TRGO) || \ + ((SELECTION) == BTIM_TS_GTIM2_TRGO) || \ + ((SELECTION) == BTIM_TS_BTIMx_ETR)) + +/* BTIM Trigger input polarity */ +#define BTIM_TRIGGER_POLARITY_POSITIVE (0x00000000) +#define BTIM_TRIGGER_POLARITY_NEGATIVE (1U << 17) +#define IS_BTIM_TRIGGER_POLARITY(POLARITY) (((POLARITY) == BTIM_TRIGGER_POLARITY_POSITIVE) || ((POLARITY) == BTIM_TRIGGER_POLARITY_NEGATIVE)) + +/* BTIM Reset source */ +#define BTIM_RESET_AWT_OV (0U<<3) +#define BTIM_RESET_LVD_OUT (1U<<3) +#define BTIM_RESET_VCx_OUT (2U<<3) +#define BTIM_RESET_SPI_NCS (3U<<3) +#define BTIM_RESET_I2C_SCL (4U<<3) +#define BTIM_RESET_UARTx_RXD (5U<<3) +#define BTIM_RESET_RTC_OUT (6U<<3) +#define BTIM_RESET_ATIM1_TRGO (7U<<3) +#define BTIM_RESET_BTIM1_TRGO (8U<<3) +#define BTIM_RESET_BTIM2_TRGO (9U<<3) +#define BTIM_RESET_BTIM3_TRGO (10U<<3) +#define BTIM_RESET_GTIM1_TRGO (11U<<3) +#define BTIM_RESET_GTIM2_TRGO (12U<<3) +#define BTIM_RESET_BTIMx_ETR (15U<<3) +#define IS_BTIM_RESET_SELECTION(SELECTION) (((SELECTION) == BTIM_RESET_AWT_OV) || \ + ((SELECTION) == BTIM_RESET_LVD_OUT) || \ + ((SELECTION) == BTIM_RESET_VCx_OUT) || \ + ((SELECTION) == BTIM_RESET_SPI_NCS) || \ + ((SELECTION) == BTIM_RESET_I2C_SCL) || \ + ((SELECTION) == BTIM_RESET_UARTx_RXD) || \ + ((SELECTION) == BTIM_RESET_RTC_OUT) || \ + ((SELECTION) == BTIM_RESET_ATIM1_TRGO) || \ + ((SELECTION) == BTIM_RESET_BTIM1_TRGO) || \ + ((SELECTION) == BTIM_RESET_BTIM2_TRGO) || \ + ((SELECTION) == BTIM_RESET_BTIM3_TRGO) || \ + ((SELECTION) == BTIM_RESET_GTIM1_TRGO) || \ + ((SELECTION) == BTIM_RESET_GTIM2_TRGO) || \ + ((SELECTION) == BTIM_RESET_BTIMx_ETR)) + +/* BTIM Trigger input polarity */ +#define BTIM_RESET_POLARITY_POSITIVE (0x00000000) +#define BTIM_RESET_POLARITY_NEGATIVE (1U << 16) +#define IS_BTIM_RESET_POLARITY(POLARITY) (((POLARITY) == BTIM_RESET_POLARITY_POSITIVE) || ((POLARITY) == BTIM_RESET_POLARITY_NEGATIVE)) + +/* BTIM_DMA_sources */ +#define BTIM_DMA_TRIGGER (1U<<14) +#define BTIM_DMA_UPDATE (1U<<8) +#define IS_BTIM_DMA_SOURCE(SOURCE) (((SOURCE) == BTIM_DMA_TRIGGER) ||\ + ((SOURCE) == BTIM_DMA_UPDATE)) +/* BTIM Master output trigger */ +#define BTIM_MASTER_OUTPUT_TRIGGER_RESET (0U) +#define BTIM_MASTER_OUTPUT_TRIGGER_EN (1U << 4) +#define BTIM_MASTER_OUTPUT_TRIGGER_UPDATE (2U << 4) +#define BTIM_MASTER_OUTPUT_TRIGGER_OVERFLOW (3U << 4) +#define IS_BTIM_MASTER_OUTPUT_TRIGGER(SOURCE) (((SOURCE) == BTIM_MASTER_OUTPUT_TRIGGER_RESET) ||\ + ((SOURCE) == BTIM_MASTER_OUTPUT_TRIGGER_EN) ||\ + ((SOURCE) == BTIM_MASTER_OUTPUT_TRIGGER_UPDATE) ||\ + ((SOURCE) == BTIM_MASTER_OUTPUT_TRIGGER_OVERFLOW)) + +/* BTIM_Exported_Functions */ +/******************************************************************************* +// 说明：去初始化 +// 参数：BTIMx x为1~3 +// 返回值：无 +*******************************************************************************/ +void BTIM_DeInit(BTIM_TypeDef* BTIMx); + +/******************************************************************************* +// 说明：BTIM基本定时器初始化 +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_TimeBaseInitStruct 指向BTIM_TimeBaseInitTypeDef类型结构体的指针 +// 返回值：无 +*******************************************************************************/ +void BTIM_TimeBaseInit(BTIM_TypeDef* BTIMx, BTIM_TimeBaseInitTypeDef* BTIM_TimeBaseInitStruct); + +/******************************************************************************* +// 说明：使能BTIMx定时器 +// 参数：BTIM_TimeBaseInitStruct +// 返回值：无 +*******************************************************************************/ +void BTIM_Cmd(BTIM_TypeDef* BTIMx, FunctionalState NewState); + +/******************************************************************************* +// 说明：配置BTIMx的中断 +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_IT 中断事件类型 +// 参数：NewState 中断事件类型的状态，ENABLE 或 DISABLE +// 返回值：无 +*******************************************************************************/ +void BTIM_ITConfig(BTIM_TypeDef* BTIMx, uint16_t BTIM_IT, FunctionalState NewState); + +/******************************************************************************* +// 说明： 检查BTIM的中断状态寄存器的各状态位是否置位 +// 参数： BTIMx CW_BTIM1~3 +// 参数： BTIM_FLAG 指定的状态位 ，参数范围： BTIM_IT_UPDATE +// BTIM_IT_TI +// +// 返回值： 无 +*******************************************************************************/ +FlagStatus BTIM_GetITStatus(BTIM_TypeDef* BTIMx, uint16_t BTIM_FLAG); + +/******************************************************************************* +// 说明： 清除BTIM的状态寄存器的各状态位 +// 参数： BTIMx CW_BTIM1~3 +// 参数： BTIM_FLAG 指定的状态位 ，参数范围： BTIM_IT_UPDATE +// BTIM_IT_TI +// +// 返回值： 无 +*******************************************************************************/ +void BTIM_ClearITPendingBit(BTIM_TypeDef* BTIMx, uint16_t BTIM_FLAG); + +/******************************************************************************* +// 说明： 软件产生事件 +// 参数： BTIMx CW_BTIM1~3 +// 参数： EventSource 事件源 BTIM_EVENTSOURCE_TRIG +// BTIM_EVENTSOURCE_UPDATE +// +// 返回值： 无 +*******************************************************************************/ +void BTIM_GenerateEvent(BTIM_TypeDef* BTIMx, uint16_t EventSource); + +/******************************************************************************* +// 说明：配置BTIMx的工作模式 +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_Mode 模式类型 +// BTIM_MODE_TIMER 定时器模式 +// BTIM_MODE_COUNTER 计数器模式 +// BTIM_MODE_TRIGGER 触发启动模式 +// BTIM_MODE_GATE 门控模式 +// 返回值：无 +*******************************************************************************/ +void BTIM_ModeConfig(BTIM_TypeDef* BTIMx, uint16_t BTIM_Mode); + +/******************************************************************************* +// 说明：配置BTIMx的计数模式 +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_CountMode 运行类型 +// BTIM_COUNT_MODE_SINGLE 单次运行 +// BTIM_COUNT_MODE_REPETITIVE 连续运行 +// 返回值：无 +*******************************************************************************/ +void BTIM_SelectOnePulseMode(BTIM_TypeDef* BTIMx, uint16_t BTIM_CountMode); + +/******************************************************************************* +// 说明：配置BTIMx的翻转输出功能 +// 参数：BTIMx CW_BTIM1~3 +// 参数：NewState ENABLE 或 DISABLE +// 返回值：无 +*******************************************************************************/ +void BTIM_OutputToggleCmd(BTIM_TypeDef* BTIMx, FunctionalState NewState); + +/******************************************************************************* +// 说明：设置BTIM的计数初值 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Counter 范围0x0000~0xFFFF +// 返回值：无 +*******************************************************************************/ +void BTIM_SetCounter(BTIM_TypeDef* BTIMx, uint16_t Counter); + +/******************************************************************************* +// 说明：获取BTIM的当前计数值 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：CNT寄存器的值 +*******************************************************************************/ +uint16_t BTIM_GetCounter(BTIM_TypeDef* BTIMx); + +/******************************************************************************* +// 说明：设置BTIM的自动重载值 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Autoreload 范围0x0000~0xFFFF +// 返回值：无 +*******************************************************************************/ +void BTIM_SetAutoreload(BTIM_TypeDef* BTIMx, uint16_t Autoreload); + +/******************************************************************************* +// 说明：获取BTIM的当前自动重载值 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：ARR寄存器的值 +*******************************************************************************/ +uint16_t BTIM_GetAutoreload(BTIM_TypeDef* BTIMx); + +/******************************************************************************* +// 说明：配置BTIMx的预分配系数 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Prescaler 预分配系数 +// 返回值：无 +*******************************************************************************/ +void BTIM_SetPrescaler(BTIM_TypeDef* BTIMx, uint16_t Prescaler); + +/******************************************************************************* +// 说明：获取BTIM的当前预分配系数 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：预分频器当前正在使用的分频系数,实际的分配值为预分配系数PSC+1 +*******************************************************************************/ +uint16_t BTIM_GetPrescaler(BTIM_TypeDef* BTIMx); + +/******************************************************************************* +// 说明：UPDATE位重映射配置 +// 参数：BTIMx CW_BTIM1~3 +// 参数：State ENABLE 或 DISABLE +// 返回值： 无 +*******************************************************************************/ +void BTIM_ConfigUpdateRemap(BTIM_TypeDef* BTIMx, FunctionalState State); + +/******************************************************************************* +// 说明：配置BTIMx的外部输入ETR +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_ETRConfigStruct ETR滤波器参数 +// 返回值：无 +*******************************************************************************/ +void BTIM_ETRConfig(BTIM_TypeDef* BTIMx, BTIM_ETRConfigTypeDef *BTIM_ETRConfigStruct); + +/******************************************************************************* +// 说明：配置BTIMx的ARR预装载功能 +// 参数：BTIMx CW_BTIM1~3 +// 参数：NewState Enable or Disable +// 返回值：无 +*******************************************************************************/ +void BTIM_AutoReloadPreloadConfig(BTIM_TypeDef* BTIMx, FunctionalState NewState); + +/******************************************************************************* +// 说明：配置BTIMx的更新请求 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Source BTIM_UPDATE_REQUEST_SOURCE_OVERFLOW BTIM_UPDATE_REQUEST_SOURCE_FLEXIBLE +// 返回值：无 +*******************************************************************************/ +void BTIM_UpdateRequestSourceConfig(BTIM_TypeDef* BTIMx, uint16_t Source); + +/******************************************************************************* +// 说明：使能BTIMx的事件更新请求 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：无 +*******************************************************************************/ +void BTIM_EnableUpdateEvent(BTIM_TypeDef* BTIMx); + +/******************************************************************************* +// 说明：禁止BTIMx的事件更新请求 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：无 +*******************************************************************************/ +void BTIM_DisableUpdateEvent(BTIM_TypeDef* BTIMx); + +/******************************************************************************* +// 说明：配置BTIMx的触发输入信号来源 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Source 触发源 +// 参数：Polarity 极性 BTIM_TRIGGER_POLARITY_POSITIVE， BTIM_TRIGGER_POLARITY_NEGATIVE +// 返回值：无 +*******************************************************************************/ +void BTIM_TriggerInputConfig(BTIM_TypeDef* BTIMx, uint16_t Source, uint32_t Polarity); + +/******************************************************************************* +// 说明：配置BTIMx的复位输入信号来源 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Source 复位源 +// 参数：Polarity 极性 BTIM_RESET_POLARITY_POSITIVE， BTIM_RESET_POLARITY_NEGATIVE +// 返回值：无 +*******************************************************************************/ +void BTIM_ResetInputConfig(BTIM_TypeDef* BTIMx, uint16_t Source, uint32_t Polarity); + + +/******************************************************************************* +// 说明：配置BTIMx在主模式下的输出 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Source TRGO信号生成的来源 +// 返回值：无 +*******************************************************************************/ +void BTIM_MasterOutputTriggerConfig(BTIM_TypeDef* BTIMx, uint16_t source); + +/******************************************************************************* +// 说明：配置BTIMx在从模式下同步使能 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：无 +*******************************************************************************/ +void BTIM_SlaveSynchronEnable(BTIM_TypeDef* BTIMx); + +/******************************************************************************* +// 说明：配置BTIMx在从模式下同步使能 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：无 +*******************************************************************************/ +void BTIM_SlaveSynchronDisable(BTIM_TypeDef* BTIMx); + +/* +// 说明：配置BTIMx的DMA +// 参数：BTIMx CW_BTIM1~3 +// 参数：Source DMA源 +// 参数：NewState ENABLE 或 DISABLE +// 返回值：无 +*******************************************************************************/ +void BTIM_DMACmd(BTIM_TypeDef* BTIMx, uint16_t Source, FunctionalState NewState); + + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_cordic.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_cordic.h new file mode 100644 index 0000000..757cd9c --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_cordic.h @@ -0,0 +1,124 @@ +/** + * @file cw32l012_cordic.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_CORDIC_H__ +#define __CW32L012_CORDIC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "cw32l012.h" +#include + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +// CORDIC函数配置 +typedef enum { + CORDIC_FUNC_COS = 0x0, // 余弦cos + CORDIC_FUNC_SIN = 0x1, // 正弦sin + CORDIC_FUNC_ATAN2 = 0x2, // 相位角atan2 + CORDIC_FUNC_HYPOT = 0x3, // 模hypot + CORDIC_FUNC_ATAN = 0x4, // 反正切atan + CORDIC_FUNC_COSH = 0x5, // 双曲余弦cosh + CORDIC_FUNC_SINH = 0x6, // 双曲正弦sinh + CORDIC_FUNC_ATANH = 0x7, // 双曲反正切atanh + CORDIC_FUNC_LN = 0x8, // 自然对数ln + CORDIC_FUNC_SQRT = 0x9 // 平方根sqrt +} cordic_func_t; + +// 数据格式配置 +typedef enum { + CORDIC_FORMAT_Q1_15 = 0x0, // q1.15格式 + CORDIC_FORMAT_Q1_31 = 0x1 // q1.31格式 +} cordic_format_t; + +// 迭代次数配置 +typedef enum { + CORDIC_ITER_2 = 0x0, + CORDIC_ITER_4, + CORDIC_ITER_6, + CORDIC_ITER_8, + CORDIC_ITER_10, + CORDIC_ITER_12, + CORDIC_ITER_14, + CORDIC_ITER_16, + CORDIC_ITER_18, + CORDIC_ITER_20, + CORDIC_ITER_22, + CORDIC_ITER_24, + CORDIC_ITER_26, + CORDIC_ITER_28, + CORDIC_ITER_30, + CORDIC_ITER_32, +} cordic_iter_t; + +// CORDIC初始化结构体 +typedef struct { + cordic_func_t func; // 运算函数 + uint8_t scale; // 扩展范围 + cordic_format_t format; // 数据格式 + cordic_iter_t iter; // 迭代次数 + uint8_t comp; // 伸缩因子补偿 + uint8_t ie; // 中断使能 + uint8_t dmaeoc; // DMA使能（运算完成） + uint8_t dmaidle; // DMA使能（空闲状态） +} cordic_init_t; + +// CORDIC状态结构体 +typedef struct { + uint8_t busy; // 工作状态 + uint8_t eoc; // 运算完成 +} cordic_status_t; + +// 函数声明 +void CORDIC_Init(cordic_init_t *init); +cordic_status_t CORDIC_GetStatus(void); +void CORDIC_SetFunction(cordic_func_t func); +void CORDIC_SetScale(uint8_t scale); +void CORDIC_SetFormat(cordic_format_t format); +void CORDIC_SetIter(uint8_t iter); +void CORDIC_SetComp(uint8_t comp); +void CORDIC_SetIE(uint8_t ie); +void CORDIC_SetDMAEoc(uint8_t dmaeoc); +void CORDIC_SetDMAIdle(uint8_t dmaidle); +int32_t float_to_q1_31(float value); +float q1_31_to_float(int32_t value); +int32_t float_to_q1_15(float value); +float q1_15_to_float(int32_t value); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_crc.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_crc.h new file mode 100644 index 0000000..eda7c58 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_crc.h @@ -0,0 +1,79 @@ +/** + * @file cw32l012_crc.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_CRC_H__ +#define __CW32L012_CRC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#include "base_types.h" +#include "cw32l012.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +//============================================================ + + +uint16_t CRC16_Calc_8bit( uint8_t CrcMode, uint8_t *pByteBuf, uint16_t ByteCnt ); + +//============================================================ + +#define CRC16_IBM 0x00UL +#define CRC16_MAXIM 0x01UL +#define CRC16_USB 0x02UL +#define CRC16_MODBUS 0x03UL +#define CRC16_CCITT 0x04UL +#define CRC16_CCITTFALSE 0x05UL +#define CRC16_X25 0x06UL +#define CRC16_XMODEM 0x07UL + + +#define IS_CRC_CRC16_MODE(MODE) (((MODE) == CRC16_IBM) || \ + ((MODE) == CRC16_MAXIM) || \ + ((MODE) == CRC16_USB) || \ + ((MODE) == CRC16_MODBUS) || \ + ((MODE) == CRC16_CCITT) || \ + ((MODE) == CRC16_CCITTFALSE) || \ + ((MODE) == CRC16_X25) || \ + ((MODE) == CRC16_XMODEM)) + +//============================================================ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_dac.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_dac.h new file mode 100644 index 0000000..2600e76 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_dac.h @@ -0,0 +1,179 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_DAC_H__ +#define __CW32L012_DAC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* 头文件包含部分 */ +#include "system_cw32l012.h" + +/* 宏定义部分 */ + +// DAC输出管脚 +#define AFx_DACOUT1_PB00() (CW_GPIOB->ANALOG_f.PIN0 = 1U) +#define AFx_DACOUT2_PB01() (CW_GPIOB->ANALOG_f.PIN1 = 1U) +// DAC通道选择 +#define DAC_CHANNEL_1 (0x00) +#define DAC_CHANNEL_2 (0x01) + +// DAC输出使能 +#define DAC_OUT_DISABLE (0x00) +#define DAC_OUT_ENABLE (0x01) + +// DAC数据对齐方式 +#define DAC_ALIGN_12B_R (0x00) +#define DAC_ALIGN_12B_L (0x01) +#define DAC_ALIGN_8B_R (0x02) + +// DAC中断 +#define DAC_IT_DMA_UNDER (0x8000) + +/* 类型定义部分 */ +// DAC触发源枚举类型 +typedef enum { + DAC_TRIG_SOFTWARE = 0x0000, // 软件触发 + DAC_TRIG_BTIM1_Trgo = 0x0001, // 基本定时器1 TRGO + DAC_TRIG_BTIM2_Trgo = 0x0002, // 基本定时器2 TRGO + DAC_TRIG_BTIM3_Trgo = 0x0003, // 基本定时器3 TRGO + DAC_TRIG_GTIM1_Trgo = 0x0004, // 通用定时器1 TRGO + DAC_TRIG_GTIM2_Trgo = 0x0005, // 通用定时器2 TRGO + DAC_TRIG_GTIM3_Trgo = 0x0006, // 通用定时器3 TRGO + DAC_TRIG_GTIM4_Trgo = 0x0007, // 通用定时器4 TRGO + DAC_TRIG_ATIM_Trgo = 0x0008, // 高级定时器 TRGO + DAC_TRIG_LPTIM_OV = 0x0009, // 低功耗定时器溢出 + DAC_TRIG_BTIM1_ETR = 0x000A, // 基本定时器1 ETR + DAC_TRIG_BTIM2_ETR = 0x000B, // 基本定时器2 ETR + DAC_TRIG_BTIM3_ETR = 0x000C, // 基本定时器3 ETR + DAC_TRIG_GTIM1_ETR = 0x000D, // 通用定时器1 ETR + DAC_TRIG_GTIM2_ETR = 0x000E, // 通用定时器2 ETR + DAC_TRIG_GTIM3_ETR = 0x000F // 通用定时器3 ETR +} DAC_TriggerSourceTypeDef; + +// DAC通道1和通道2使能状态 +typedef enum { + DAC_CHANNEL_DISABLE = 0, + DAC_CHANNEL_ENABLE = 1 +} DAC_ChannelStateTypeDef; + +// DAC通道1和通道2触发使能状态 +typedef enum { + DAC_TRIGGER_DISABLE = 0, + DAC_TRIGGER_ENABLE = 1 +} DAC_TriggerStateTypeDef; + +// DAC通道1和通道2波形生成模式 +typedef enum { + DAC_WAVE_DISABLE = 0, // 禁止生成波 + DAC_WAVE_NOISE = 1, // 生成噪声波 + DAC_WAVE_TRIANGLE = 2 // 生成三角波 +} DAC_WaveformModeTypeDef; + +// DAC通道1和通道2DMA使能状态 +typedef enum { + DAC_DMA_DISABLE = 0, + DAC_DMA_ENABLE = 1 +} DAC_DMAStateTypeDef; + +// DAC通道1和通道2DMA下溢中断使能状态 +typedef enum { + DAC_DMA_UNDERFLOW_DISABLE = 0, + DAC_DMA_UNDERFLOW_ENABLE = 1 +} DAC_DMAUnderflowStateTypeDef; + +// DAC通道1和通道2振幅选择器 +typedef enum { + DAC_TriangleAmplitude_1 = 0x0, // 振幅等于 1 + DAC_TriangleAmplitude_3 = 0x1, // 振幅等于 3 + DAC_TriangleAmplitude_7 = 0x2, // 振幅等于 7 + DAC_TriangleAmplitude_15 = 0x3, // 振幅等于 15 + DAC_TriangleAmplitude_31 = 0x4, // 振幅等于 31 + DAC_TriangleAmplitude_63 = 0x5, // 振幅等于 63 + DAC_TriangleAmplitude_127 = 0x6, // 振幅等于 127 + DAC_TriangleAmplitude_255 = 0x7, // 振幅等于 255 + DAC_TriangleAmplitude_511 = 0x8, // 振幅等于 511 + DAC_TriangleAmplitude_1023 = 0x9, // 振幅等于 1023 + DAC_TriangleAmplitude_2047 = 0xA, // 振幅等于 2047 + DAC_TriangleAmplitude_4095 = 0xB // 振幅等于 4095 +} DAC_TriangleAmplitudeTypeDef; + +// DAC通道1和通道2噪声选择器 +typedef enum { + DAC_LFSRUnmask_Bit0 = 0x0, // 不屏蔽 LFSR 的位 0 + DAC_LFSRUnmask_Bits1_0 = 0x1, // 不屏蔽 LFSR 的位 [1:0] + DAC_LFSRUnmask_Bits2_0 = 0x2, // 不屏蔽 LFSR 的位 [2:0] + DAC_LFSRUnmask_Bits3_0 = 0x3, // 不屏蔽 LFSR 的位 [3:0] + DAC_LFSRUnmask_Bits4_0 = 0x4, // 不屏蔽 LFSR 的位 [4:0] + DAC_LFSRUnmask_Bits5_0 = 0x5, // 不屏蔽 LFSR 的位 [5:0] + DAC_LFSRUnmask_Bits6_0 = 0x6, // 不屏蔽 LFSR 的位 [6:0] + DAC_LFSRUnmask_Bits7_0 = 0x7, // 不屏蔽 LFSR 的位 [7:0] + DAC_LFSRUnmask_Bits8_0 = 0x8, // 不屏蔽 LFSR 的位 [8:0] + DAC_LFSRUnmask_Bits9_0 = 0x9, // 不屏蔽 LFSR 的位 [9:0] + DAC_LFSRUnmask_Bits10_0 = 0xA, // 不屏蔽 LFSR 的位 [10:0] + DAC_LFSRUnmask_Bits11_0 = 0xB // 不屏蔽 LFSR 的位 [11:0] +} DAC_NoiseLFSRUnmaskBitsTypeDef; + +typedef struct +{ + DAC_TriggerSourceTypeDef DAC_TriggerSource; + DAC_ChannelStateTypeDef DAC_ChannelState; + DAC_TriggerStateTypeDef DAC_TriggerState; + DAC_WaveformModeTypeDef DAC_WaveformMode; + DAC_DMAStateTypeDef DAC_DMAState; + DAC_DMAUnderflowStateTypeDef DAC_DMAUnderflowState; + DAC_TriangleAmplitudeTypeDef DAC_TriangleAmplitude; + DAC_NoiseLFSRUnmaskBitsTypeDef DAC_NoiseLFSRUnmaskBits; +}DAC_InitTypeDef; + +/* 全局变量声明部分 */ + + +/* 函数声明部分 */ +/** @defgroup DAC驱动函数原型 + * @{ + */ +void DAC_DeInit(void); +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_ChannelOutCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTrigger(uint32_t DAC_Channel); +void DAC_DualSoftwareTrigger(void); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, DAC_WaveformModeTypeDef DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data1, uint16_t Data2); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); + +/* DMA management functions ***************************************************/ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_debug.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_debug.h new file mode 100644 index 0000000..3f286ed --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_debug.h @@ -0,0 +1,64 @@ +/** + * @file cw32l012_debug.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_DEBUG_H__ +#define __CW32L012_DEBUG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#include "base_types.h" +#include "cw32l012.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +#define DBGMCU_ATIM_STOP ((uint32_t)0x00000001) +#define DBGMCU_GTIM1_STOP ((uint32_t)0x00000002) +#define DBGMCU_GTIM2_STOP ((uint32_t)0x00000004) +#define DBGMCU_BTIM123_STOP ((uint32_t)0x00000020) +#define DBGMCU_AWT_STOP ((uint32_t)0x00000040) +#define DBGMCU_RTC_STOP ((uint32_t)0x00000100) +#define DBGMCU_IWDT_STOP ((uint32_t)0x00000200) +#define DBGMCU_WWDT_STOP ((uint32_t)0x00000400) +#define DBGMCU_LPTIM_STOP ((uint32_t)0x00000800) +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFF080) == 0x00) && ((PERIPH) != 0x00)) + +//============================================================ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_digitalsign.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_digitalsign.h new file mode 100644 index 0000000..419a3aa --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_digitalsign.h @@ -0,0 +1,77 @@ +/** + * @file cw32l012_digitalsign.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_DIGITALSIGN_H__ +#define __CW32L012_DIGITALSIGN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "base_types.h" +#include "cw32l012.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +//============================================================ + +//#define DIGITALSIGN_BASE 0x00012610UL + +#define CHIP_TYPE_BASE 0x001007E0UL +#define PIN_COUNT_BASE 0x001007D5UL +#define FLASH_SIZE_BASE 0x001007D8UL +#define RAM_SIZE_BASE 0x001007D6UL + +#define CHIP_UID_BASE 0x001007B0UL + +#define CHIP_TYPE_LENGTH 16 +#define CHIP_UID_LENGTH 10 +//============================================================ + +//获取芯片型号// +void DIGITALSIGN_GetChipType(uint8_t* pChipType); +//获取管脚数量// +uint8_t DIGITALSIGN_GetPinCount(void); +//获取FLASH容量// +uint32_t DIGITALSIGN_GetFlashSize(void); +//获取RAM容量// +uint16_t DIGITALSIGN_GetRamSize(void); +//获取芯片UID// +void DIGITALSIGN_GetChipUid(uint8_t* pChipUid); + +//============================================================ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_dma.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_dma.h new file mode 100644 index 0000000..d1bada3 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_dma.h @@ -0,0 +1,213 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_DMA_H__ +#define __CW32L012_DMA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* 头文件包含部分 */ +#include "system_cw32l012.h" + +/* 宏定义部分 */ + +#define DMA_BASE_ADDRESS 0x40020000 + +// 定义寄存器地址 +#define DMA_ISR (volatile uint32_t *)(DMA_BASE_ADDRESS + 0x00) +#define DMA_ICR (volatile uint32_t *)(DMA_BASE_ADDRESS + 0x04) +#define DMA_CSRy(y) (volatile uint32_t *)(DMA_BASE_ADDRESS + 0x00 + 32 * (y+1)) +#define DMA_CNTy(y) (volatile uint32_t *)(DMA_BASE_ADDRESS + 0x04 + 32 * (y+1)) +#define DMA_SRCADDRy(y) (volatile uint32_t *)(DMA_BASE_ADDRESS + 0x08 + 32 * (y+1)) +#define DMA_DSTADDRy(y) (volatile uint32_t *)(DMA_BASE_ADDRESS + 0x0C + 32 * (y+1)) +#define DMA_TRIGy(y) (volatile uint32_t *)(DMA_BASE_ADDRESS + 0x10 + 32 * (y+1)) +#define DMA_CCNTy(y) (volatile uint32_t *)(DMA_BASE_ADDRESS + 0x14 + 32 * (y+1)) + +#define DMA_INTERRUPT_TE DMA_CSR1_TEIE_Msk +#define DMA_INTERRUPT_TC DMA_CSR1_TCIE_Msk + +/* 类型定义部分 */ +// DMA通道编号 +typedef enum { + DMA_CHANNEL_1 = 0, + DMA_CHANNEL_2, + DMA_CHANNEL_3, + DMA_CHANNEL_4 +} DMA_ChannelTypeDef; + +// DMA数据宽度 +typedef enum { + DMA_DATA_SIZE_8BITS = 0, // 8-bit 数据大小 + DMA_DATA_SIZE_16BITS, // 16-bit 数据大小 + DMA_DATA_SIZE_32BITS // 32-bit 数据大小 +} DMA_DataSizeTypeDef; + +// DMA传输模式 +typedef enum { + DMA_MODE_BULK = 0, // 批量传输模式 + DMA_MODE_BLOCK // 块传输模式 +} DMA_ModeTypeDef; + +// DMA触发类型 +typedef enum { + DMA_TRIGGER_SOFTWARE = 0, // 软件触发 + DMA_TRIGGER_HARDWARE // 硬件触发 +} DMA_TriggerTypeDef; + +typedef enum { + DMA_STATUS_IDLE = 0, // 初始状态 + DMA_STATUS_ERROR_ADDR, // 地址超出范围 + DMA_STATUS_ERROR_STOP, // 停止请求引起中止 + DMA_STATUS_ERROR_SRC, // 源地址访问错误 + DMA_STATUS_ERROR_DST, // 目的地址访问错误 + DMA_STATUS_COMPLETE // 传输完成 +} DMA_StatusTypeDef; + +// DMA硬件触发源 +typedef enum { + DMA_TRIGGER_SRC_UART1_RX = 0, // UART1 接收 Buf 非空事件 + DMA_TRIGGER_SRC_UART1_TX, // UART1 发送 Buf 空事件 + DMA_TRIGGER_SRC_UART2_RX, // UART2 接收 Buf 非空事件 + DMA_TRIGGER_SRC_UART2_TX, // UART2 发送 Buf 空事件 + DMA_TRIGGER_SRC_UART3_RX, // UART3 接收 Buf 非空事件 + DMA_TRIGGER_SRC_UART3_TX, // UART3 发送 Buf 空事件 + DMA_TRIGGER_SRC_SPI1_RX, // SPI1 接收 Buf 非空事件 + DMA_TRIGGER_SRC_SPI1_TX, // SPI1 发送 Buf 空事件 + DMA_TRIGGER_SRC_SPI2_RX, // SPI2 接收 Buf 非空事件 + DMA_TRIGGER_SRC_SPI2_TX, // SPI2 发送 Buf 空事件 + DMA_TRIGGER_SRC_SPI3_RX, // SPI3 接收 Buf 非空事件 + DMA_TRIGGER_SRC_SPI3_TX, // SPI3 发送 Buf 空事件 + DMA_TRIGGER_SRC_ADC1_SEQ, // ADC1 序列转换完成事件 + DMA_TRIGGER_SRC_ADC1_SINGLE, // ADC1 单次转换完成事件 + DMA_TRIGGER_SRC_ADC2_SEQ, // ADC2 序列转换完成事件 + DMA_TRIGGER_SRC_ADC2_SINGLE, // ADC2 单次转换完成事件 + DMA_TRIGGER_SRC_DAC1_DHR_OVF, // DAC1 DHR下溢出事件 + DMA_TRIGGER_SRC_DAC2_DHR_OVF, // DAC2 DHR下溢出事件 + DMA_TRIGGER_SRC_HALLTIM, // HALLTIM事件 + DMA_TRIGGER_SRC_BTIM1_UPD, // BTIM1 更新事件 + DMA_TRIGGER_SRC_BTIM1_TRIG, // BTIM1 触发事件 + DMA_TRIGGER_SRC_BTIM2_UPD, // BTIM2 更新事件 + DMA_TRIGGER_SRC_BTIM2_TRIG, // BTIM2 触发事件 + DMA_TRIGGER_SRC_BTIM3_UPD, // BTIM3 更新事件 + DMA_TRIGGER_SRC_BTIM3_TRIG, // BTIM3 触发事件 + DMA_TRIGGER_SRC_GTIM1_TRIG, // GTIM1 触发事件 + DMA_TRIGGER_SRC_GTIM1_UPD, // GTIM1 更新事件 + DMA_TRIGGER_SRC_GTIM1_CC1, // GTIM1 捕获/比较1事件 + DMA_TRIGGER_SRC_GTIM1_CC2, // GTIM1 捕获/比较2事件 + DMA_TRIGGER_SRC_GTIM1_CC3, // GTIM1 捕获/比较3事件 + DMA_TRIGGER_SRC_GTIM1_CC4, // GTIM1 捕获/比较4事件 + DMA_TRIGGER_SRC_GTIM2_TRIG, // GTIM2 触发事件 + DMA_TRIGGER_SRC_GTIM2_UPD, // GTIM2 更新事件 + DMA_TRIGGER_SRC_GTIM2_CC1, // GTIM2 捕获/比较1事件 + DMA_TRIGGER_SRC_GTIM2_CC2, // GTIM2 捕获/比较2事件 + DMA_TRIGGER_SRC_GTIM2_CC3, // GTIM2 捕获/比较3事件 + DMA_TRIGGER_SRC_GTIM2_CC4, // GTIM2 捕获/比较4事件 + DMA_TRIGGER_SRC_GTIM3_TRIG, // GTIM3 触发事件 + DMA_TRIGGER_SRC_GTIM3_UPD, // GTIM3 更新事件 + DMA_TRIGGER_SRC_GTIM3_CC1, // GTIM3 捕获/比较1事件 + DMA_TRIGGER_SRC_GTIM3_CC2, // GTIM3 捕获/比较2事件 + DMA_TRIGGER_SRC_GTIM3_CC3, // GTIM3 捕获/比较3事件 + DMA_TRIGGER_SRC_GTIM3_CC4, // GTIM3 捕获/比较4事件 + DMA_TRIGGER_SRC_GTIM4_TRIG, // GTIM4 触发事件 + DMA_TRIGGER_SRC_GTIM4_UPD, // GTIM4 更新事件 + DMA_TRIGGER_SRC_GTIM4_CC1, // GTIM4 捕获/比较1事件 + DMA_TRIGGER_SRC_GTIM4_CC2, // GTIM4 捕获/比较2事件 + DMA_TRIGGER_SRC_GTIM4_CC3, // GTIM4 捕获/比较3事件 + DMA_TRIGGER_SRC_GTIM4_CC4, // GTIM4 捕获/比较4事件 + DMA_TRIGGER_SRC_ATIM_UPD, // ATIM 更新事件 + DMA_TRIGGER_SRC_ATIM_CC1, // ATIM 捕获/比较1事件 + DMA_TRIGGER_SRC_ATIM_CC2, // ATIM 捕获/比较2事件 + DMA_TRIGGER_SRC_ATIM_CC3, // ATIM 捕获/比较3事件 + DMA_TRIGGER_SRC_ATIM_CC4, // ATIM 捕获/比较4事件 + DMA_TRIGGER_SRC_ATIM_CC5, // ATIM 捕获/比较5事件 + DMA_TRIGGER_SRC_ATIM_CC6, // ATIM 捕获/比较6事件 + DMA_TRIGGER_SRC_ATIM_COM, // ATIM COM事件 + DMA_TRIGGER_SRC_ATIM_TRIG, // ATIM 触发事件 + DMA_TRIGGER_SRC_CORDIC_IDLE, // cordic_IDLE事件 + DMA_TRIGGER_SRC_CORDIC_EOC, // cordic_EOC事件 + DMA_TRIGGER_SRC_LPI2C1_TX, // LPI2C1 发送事件 + DMA_TRIGGER_SRC_LPI2C1_RX, // LPI2C1 接收事件 + DMA_TRIGGER_SRC_LPI2C2_TX, // LPI2C2 发送事件 + DMA_TRIGGER_SRC_LPI2C2_RX // LPI2C2 接收事件 +} DMA_TriggerSourceTypeDef; + +// DMA传输状态标志 +typedef enum { + DMA_STATUS_TC = 0x01, // 传输完成标志 + DMA_STATUS_TE = 0x02 // 传输错误标志 +} DMA_TransferStatusTypeDef; + +// DMA地址增量模式 +typedef enum { + DMA_ADDRESS_FIXED = 0, // 地址固定 + DMA_ADDRESS_INCREMENT // 地址自增 +} DMA_AddressModeTypeDef; + +// +typedef struct { + // DMA_CSRy寄存器相关配置 + boolean_t RestartEnable; // 自动重传使能（0：禁用，1：启用） + DMA_DataSizeTypeDef DataSize; // 数据位宽 + DMA_AddressModeTypeDef SrcIncrement; // 源地址增量方式 + DMA_AddressModeTypeDef DstIncrement; // 目的地址增量方式 + DMA_ModeTypeDef TransferMode; // 传输模式（批量或块传输） +// boolean_t TransferErrorInterruptEnable; // 传输错误中断使能（0：禁用，1：启用） +// boolean_t TransferCompleteInterruptEnable; // 传输完成中断使能（0：禁用，1：启用） + + // DMA_CNTy寄存器相关配置 + uint16_t TransferCount; // 待传输的任务数量 + uint8_t BlockCount; // 每个传输任务的数据块数量 + + // DMA_SRCADDRy和DMA_DSTADDRy寄存器相关配置 + uint32_t SrcAddress; // 源地址 + uint32_t DstAddress; // 目的地址 + + // DMA_TRIGy寄存器相关配置 + DMA_TriggerTypeDef TriggerType; // 触发类型（软件或硬件触发） + DMA_TriggerSourceTypeDef TriggerSource; // 硬件触发源 +} DMA_InitTypeDef; +/* 全局变量声明部分 */ + + +/* 函数声明部分 */ +void DMA_DeInit(DMA_ChannelTypeDef Channel); +// DMA初始化 +void DMA_Init(DMA_ChannelTypeDef Channel, DMA_InitTypeDef *DMAInitStruct); +// 启用DMA通道 +void DMA_Cmd(DMA_ChannelTypeDef channel, FunctionalState state); +// 启动DMA传输 +void DMA_StartTransfer(DMA_ChannelTypeDef channel); +// 检查DMA传输状态 +DMA_StatusTypeDef DMA_CheckStatus(DMA_ChannelTypeDef channel); +// 配置DMA触发源 +void DMA_ConfigTriggerSource(DMA_ChannelTypeDef channel, DMA_TriggerTypeDef trigger_type, DMA_TriggerSourceTypeDef trigger_source); +// +void DMA_ITConfig(DMA_ChannelTypeDef channel, uint32_t interrupt_type, FunctionalState state); + +void DMA_ClearInterruptFlag(DMA_ChannelTypeDef channel, uint32_t interrupt_type); + +// 配置DMA通道 +void DMA_ConfigChannel(DMA_ChannelTypeDef channel, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size, uint32_t data_size); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_eau.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_eau.h new file mode 100644 index 0000000..960d430 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_eau.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_EAU_H__ +#define __CW32L012_EAU_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* 头文件包含部分 */ +#include "system_cw32l012.h" + +/* 宏定义部分 */ + + +/* 类型定义部分 */ +// EAU运算模式枚举 +typedef enum { + EAU_MODE_UNSIGNED_DIV = 0x00, // 无符号除法 + EAU_MODE_SIGNED_DIV = 0x01, // 有符号除法 + EAU_MODE_SQRT = 0x02, // 开方 + EAU_MODE_RESERVED = 0x03 // 保留 +} EAU_Mode; + +// EAU状态标志枚举 +typedef enum { + EAU_STATUS_IDLE = 0x00, // 空闲状态 + EAU_STATUS_BUSY = 0x01, // 忙碌状态 + EAU_STATUS_DIV_ZERO = 0x02, // 除数为零 + EAU_STATUS_OVERFLOW = 0x04 // 有符号除法溢出 +} EAU_Status; + +/* 全局变量声明部分 */ + + +/* 函数声明部分 */ + +// EAU驱动库函数声明 +void EAU_Init(void); +void EAU_SetMode(EAU_Mode mode); +void EAU_StartOperation(uint32_t dividend, uint32_t divisor); +uint32_t EAU_GetQuotient(void); +uint32_t EAU_GetRemainder(void); +EAU_Status EAU_GetStatus(void); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_flash.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_flash.h new file mode 100644 index 0000000..f195e01 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_flash.h @@ -0,0 +1,179 @@ +/** + * @file cw32l012_flash.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_FLASH_H__ +#define __CW32L012_FLASH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "system_cw32l012.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +// 密钥值（高16位） +#define FLASH_KEY 0x5A5A + +#define FLASH_PAGES_SIZE 128 +#define FLASH_BYTES_SIZE 0x10000 +#define FLASH_START_ADDRESS 0x00000000 +#define FLASH_END_ADDRESS 0x0000FFFF + +#define OTP_BYTES_SIZE 22 +#define OTP_START_ADDRESS 0x00100760 +#define OTP_END_ADDRESS 0x00100775 +//============================================================ + +/** @defgroup FLASH状态 + * @{ + */ +#define FLASH_FLAG_OK (0UL) +#define FLASH_FLAG_BSY (bv5) /*!< FLASH Busy flag */ +#define FLASH_FLAG_PGERR (bv4) /*!< FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR (bv1) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PCERR (bv0) /*!< FLASH PC error flag */ +#define FLASH_ERROR_ADDR 0x80 + +/** @defgroup 读访问周期延时 + * @{ + */ +#define FLASH_Latency_1 ((uint32_t)0x00000000) /*!< FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000001) /*!< FLASH Two Latency cycles */ +#define FLASH_Latency_3 ((uint32_t)0x00000002) /*!< FLASH Three Latency cycles */ +#define FLASH_Latency_4 ((uint32_t)0x00000003) /*!< FLASH Four Latency cycles */ + + +#define IS_FLASH_LATENCY(LATENCY) ((LATENCY) < 4) + +/** @defgroup 读保护等级 + * @{ + */ +#define FLASH_RDLEVEL0 ((uint16_t)0x00) +#define FLASH_RDLEVEL1 ((uint16_t)0x01) +#define FLASH_RDLEVEL2 ((uint16_t)0x02) +#define FLASH_RDLEVEL3 ((uint16_t)0x03) +#define IS_FLASH_RDLEVEL(LEVEL) (((LEVEL) == FLASH_RDLEVEL0) || \ + ((LEVEL) == FLASH_RDLEVEL1) || \ + ((LEVEL) == FLASH_RDLEVEL2) || \ + ((LEVEL) == FLASH_RDLEVEL3)) +/** @defgroup 预取指 + * @{ + */ +#define FLASH_PREFETCH_ENABLE FLASH_CR2_FETCH_Msk +#define FLASH_PREFETCH_DISABLE 0 + +/** @defgroup 缓存 + * @{ + */ +#define FLASH_CACHE_ENABLE FLASH_CR2_CACHE_Msk +#define FLASH_CACHE_DISABLE 0 + + +/** @defgroup 中断标志位 + * @{ + */ +#define FLASH_IT_PROG (bv4) +#define FLASH_IT_PAGELOCK (bv1) +#define FLASH_IT_PC (bv0) +#define IS_FLASH_IT(IT) ((((IT) & 0xFFFFFFEC) == 0x0UL) && ((IT) != 0x0UL)) +#define IS_FLASH_GET_IT(IT) (((IT) == FLASH_IT_PROG) || \ + ((IT) == FLASH_IT_PAGELOCK) || \ + ((IT) == FLASH_IT_PC)) + +/** @defgroup FLASH页 + * @{ + */ +#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Pages */ +#define IS_FLASH_PAGE_Number(PAGENUMBER) ((PAGENUMBER) < FLASH_PAGES_SIZE) +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_START_ADDRESS) && ((ADDRESS) <= FLASH_END_ADDRESS)) + +//============================================================ +void FLASH_Init(uint32_t hclk_freq); +//设置FLASH读访问周期 +void FLASH_SetLatency(uint32_t FLASH_Latency); +//设置预取使能 +void FLASH_PrefetchCmd(FunctionalState NewState); +//设置BUFFER使能 +void FLASH_CacheCmd(FunctionalState NewState); +//获取FLASH的Fetch状态 +FlagStatus FLASH_GetPrefetchStatus(void); +//获取FLASH的Cache状态 +FlagStatus FLASH_GetCacheStatus(void); +//获取FLASH的读保护等级 +uint8_t FLASH_GetReadOutLevel(void); +//设置FLASH的读保护等级 +void FLASH_SetReadOutLevel(uint16_t RdLevel); +//解锁FLASH所有页面 +void FLASH_UnlockAllPages(void); +//锁定FLASH所有页面 +void FLASH_LockAllPages(void); +//解锁FLASH指定页面：按照页面号解锁，0~FLASH_PAGES_SIZE-1 +uint8_t FLASH_UnlockPage(uint16_t Page_Number); +//解锁FLASH指定页面：按照起始和终止地址解锁 +uint8_t FLASH_UnlockPages(uint32_t StartAddr, uint32_t EndAddr); +//擦除FLASH指定页面：按照页面号擦除，0~FLASH_PAGES_SIZE-1 +uint8_t FLASH_ErasePage(uint16_t Page_Number); +//擦除FLASH指定页面：按照起始和终止地址擦除 +uint8_t FLASH_ErasePages(uint32_t StartAddr, uint32_t EndAddr); +//指定地址开始写一定长度的数据，按照字节写 +uint8_t FLASH_WriteBytes(uint32_t WriteAddr, uint8_t* pWrBuf, uint16_t WrByteCnt); +//指定地址开始写一定长度的数据，按照半字写 +uint8_t FLASH_WriteHalfWords(uint32_t WriteAddr, uint16_t* pWrBuf, uint16_t WrByteCnt); +//指定地址开始写一定长度的数据，按照字写 +uint8_t FLASH_WriteWords(uint32_t WriteAddr, uint32_t* pWrBuf, uint16_t WrByteCnt); + +//锁定FLASH指定页面：按照页面号锁定，0~FLASH_PAGES_SIZE-1 +uint8_t FLASH_LockPage(uint16_t Page_Number); +//锁定FLASH指定页面：按照起始和终止地址锁定 +uint8_t FLASH_LockPages(uint32_t StartAddr, uint32_t EndAddr); +//FLASH指定中断使能配置 +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +//获取指定FLASH中断标志位 +ITStatus FLASH_GetITStatus(uint32_t FLASH_IT); +//清除指定FLASH中断标志位 +void FLASH_ClearITPendingBit(uint32_t FLASH_IT); +//获取FLASH模块当前状态// +uint32_t FLASH_GetStatus(void); + +//向OTP的指定地址写入数据 +uint8_t OTP_WriteBytes(uint32_t WriteAddr, uint8_t* pWrBuf, uint16_t WrByteCnt); +// FLASH的安全运行库区功能使能 +uint8_t FLASH_SafetyLibraryEnable(uint8_t *Passwords, uint8_t StartPage, uint8_t EndPage); +//============================================================ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_gpio.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_gpio.h new file mode 100644 index 0000000..4b79998 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_gpio.h @@ -0,0 +1,1046 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_GPIO_H__ +#define __CW32L012_GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "system_cw32l012.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +typedef struct +{ + uint32_t Pins; + uint32_t Mode; + uint32_t IT; +} GPIO_InitTypeDef; + +typedef enum +{ + GPIO_Pin_RESET = 0, + GPIO_Pin_SET +} GPIO_PinState; + + +//============================================================ + +#define GPIO_MODE_ANALOG (0X00) +#define GPIO_MODE_INPUT (0x10) +#define GPIO_MODE_INPUT_PULLUP (0x11) + +#define GPIO_MODE_OUTPUT_PP (0x20) +#define GPIO_MODE_OUTPUT_OD (0x21) + +#define GPIO_IT_NONE (0x80) +#define GPIO_IT_RISING (0x81) +#define GPIO_IT_FALLING (0x82) + + +//============================================================ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +//============================================================ +//端口滤波定义 +#define GPIO_FLTCLK_HCLK2 (((uint32_t)0) << 16) +#define GPIO_FLTCLK_HCLK4 (((uint32_t)1) << 16) +#define GPIO_FLTCLK_HCLK8 (((uint32_t)2) << 16) +#define GPIO_FLTCLK_BTIM1OV (((uint32_t)3) << 16) +#define GPIO_FLTCLK_LSI (((uint32_t)5) << 16) +#define GPIO_FLTCLK_LPTIMOV (((uint32_t)7) << 16) + +//============================================================ +//清除CW_GPIO中断标志 +#define GPIOA_INTFLAG_CLR(Mask) ((CW_GPIOA->ICR) = (~((uint32_t)(Mask)))) +#define GPIOB_INTFLAG_CLR(Mask) ((CW_GPIOB->ICR) = (~((uint32_t)(Mask)))) +#define GPIOC_INTFLAG_CLR(Mask) ((CW_GPIOC->ICR) = (~((uint32_t)(Mask)))) +#define GPIOF_INTFLAG_CLR(Mask) ((CW_GPIOF->ICR) = (~((uint32_t)(Mask)))) + + +//============================================================ +//ANALOG OR DIGTAL +#define PA00_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN0 = 0) +#define PA00_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN0 = 1) +#define PA01_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN1 = 0) +#define PA01_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN1 = 1) +#define PA02_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN2 = 0) +#define PA02_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN2 = 1) +#define PA03_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN3 = 0) +#define PA03_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN3 = 1) +#define PA04_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN4 = 0) +#define PA04_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN4 = 1) +#define PA05_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN5 = 0) +#define PA05_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN5 = 1) +#define PA06_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN6 = 0) +#define PA06_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN6 = 1) +#define PA07_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN7 = 0) +#define PA07_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN7 = 1) +#define PA08_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN8 = 0) +#define PA08_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN8 = 1) +#define PA09_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN9 = 0) +#define PA09_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN9 = 1) +#define PA10_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN10 = 0) +#define PA10_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN10 = 1) +#define PA11_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN11 = 0) +#define PA11_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN11 = 1) +#define PA12_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN12 = 0) +#define PA12_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN12 = 1) +#define PA13_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN13 = 0) +#define PA13_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN13 = 1) +#define PA14_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN14 = 0) +#define PA14_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN14 = 1) +#define PA15_DIGTAL_ENABLE() (CW_GPIOA->ANALOG_f.PIN15 = 0) +#define PA15_ANALOG_ENABLE() (CW_GPIOA->ANALOG_f.PIN15 = 1) + +#define PB00_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN0 = 0) +#define PB00_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN0 = 1) +#define PB01_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN1 = 0) +#define PB01_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN1 = 1) +#define PB02_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN2 = 0) +#define PB02_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN2 = 1) +#define PB03_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN3 = 0) +#define PB03_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN3 = 1) +#define PB04_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN4 = 0) +#define PB04_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN4 = 1) +#define PB05_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN5 = 0) +#define PB05_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN5 = 1) +#define PB06_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN6 = 0) +#define PB06_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN6 = 1) +#define PB07_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN7 = 0) +#define PB07_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN7 = 1) +#define PB08_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN8 = 0) +#define PB08_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN8 = 1) +#define PB09_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN9 = 0) +#define PB09_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN9 = 1) +#define PB10_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN10 = 0) +#define PB10_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN10 = 1) +#define PB11_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN11 = 0) +#define PB11_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN11 = 1) +#define PB12_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN12 = 0) +#define PB12_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN12 = 1) +#define PB13_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN13 = 0) +#define PB13_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN13 = 1) +#define PB14_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN14 = 0) +#define PB14_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN14 = 1) +#define PB15_DIGTAL_ENABLE() (CW_GPIOB->ANALOG_f.PIN15 = 0) +#define PB15_ANALOG_ENABLE() (CW_GPIOB->ANALOG_f.PIN15 = 1) + +#define PC13_DIGTAL_ENABLE() (CW_GPIOC->ANALOG_f.PIN13 = 0) +#define PC13_ANALOG_ENABLE() (CW_GPIOC->ANALOG_f.PIN13 = 1) +#define PC14_DIGTAL_ENABLE() (CW_GPIOC->ANALOG_f.PIN14 = 0) +#define PC14_ANALOG_ENABLE() (CW_GPIOC->ANALOG_f.PIN14 = 1) +#define PC15_DIGTAL_ENABLE() (CW_GPIOC->ANALOG_f.PIN15 = 0) +#define PC15_ANALOG_ENABLE() (CW_GPIOC->ANALOG_f.PIN15 = 1) + +#define PF00_DIGTAL_ENABLE() (CW_GPIOF->ANALOG_f.PIN0 = 0) +#define PF00_ANALOG_ENABLE() (CW_GPIOF->ANALOG_f.PIN0 = 1) +#define PF01_DIGTAL_ENABLE() (CW_GPIOF->ANALOG_f.PIN1 = 0) +#define PF01_ANALOG_ENABLE() (CW_GPIOF->ANALOG_f.PIN1 = 1) +#define PF03_DIGTAL_ENABLE() (CW_GPIOF->ANALOG_f.PIN3 = 0) +#define PF03_ANALOG_ENABLE() (CW_GPIOF->ANALOG_f.PIN3 = 1) +#define PF06_DIGTAL_ENABLE() (CW_GPIOF->ANALOG_f.PIN6 = 0) +#define PF06_ANALOG_ENABLE() (CW_GPIOF->ANALOG_f.PIN6 = 1) +#define PF07_DIGTAL_ENABLE() (CW_GPIOF->ANALOG_f.PIN7 = 0) +#define PF07_ANALOG_ENABLE() (CW_GPIOF->ANALOG_f.PIN7 = 1) + +//============================================================ +// INPUTAND OUTPUT +#define PA00_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN0 = 0) +#define PA00_DIR_INPUT() (CW_GPIOA->DIR_f.PIN0 = 1) +#define PA01_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN1 = 0) +#define PA01_DIR_INPUT() (CW_GPIOA->DIR_f.PIN1 = 1) +#define PA02_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN2 = 0) +#define PA02_DIR_INPUT() (CW_GPIOA->DIR_f.PIN2 = 1) +#define PA03_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN3 = 0) +#define PA03_DIR_INPUT() (CW_GPIOA->DIR_f.PIN3 = 1) +#define PA04_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN4 = 0) +#define PA04_DIR_INPUT() (CW_GPIOA->DIR_f.PIN4 = 1) +#define PA05_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN5 = 0) +#define PA05_DIR_INPUT() (CW_GPIOA->DIR_f.PIN5 = 1) +#define PA06_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN6 = 0) +#define PA06_DIR_INPUT() (CW_GPIOA->DIR_f.PIN6 = 1) +#define PA07_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN7 = 0) +#define PA07_DIR_INPUT() (CW_GPIOA->DIR_f.PIN7 = 1) +#define PA08_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN8 = 0) +#define PA08_DIR_INPUT() (CW_GPIOA->DIR_f.PIN8 = 1) +#define PA09_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN9 = 0) +#define PA09_DIR_INPUT() (CW_GPIOA->DIR_f.PIN9 = 1) +#define PA10_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN10 = 0) +#define PA10_DIR_INPUT() (CW_GPIOA->DIR_f.PIN10 = 1) +#define PA11_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN11 = 0) +#define PA11_DIR_INPUT() (CW_GPIOA->DIR_f.PIN11 = 1) +#define PA12_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN12 = 0) +#define PA12_DIR_INPUT() (CW_GPIOA->DIR_f.PIN12 = 1) +#define PA13_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN13 = 0) +#define PA13_DIR_INPUT() (CW_GPIOA->DIR_f.PIN13 = 1) +#define PA14_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN14 = 0) +#define PA14_DIR_INPUT() (CW_GPIOA->DIR_f.PIN14 = 1) +#define PA15_DIR_OUTPUT() (CW_GPIOA->DIR_f.PIN15 = 0) +#define PA15_DIR_INPUT() (CW_GPIOA->DIR_f.PIN15 = 1) + +#define PB00_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN0 = 0) +#define PB00_DIR_INPUT() (CW_GPIOB->DIR_f.PIN0 = 1) +#define PB01_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN1 = 0) +#define PB01_DIR_INPUT() (CW_GPIOB->DIR_f.PIN1 = 1) +#define PB02_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN2 = 0) +#define PB02_DIR_INPUT() (CW_GPIOB->DIR_f.PIN2 = 1) +#define PB03_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN3 = 0) +#define PB03_DIR_INPUT() (CW_GPIOB->DIR_f.PIN3 = 1) +#define PB04_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN4 = 0) +#define PB04_DIR_INPUT() (CW_GPIOB->DIR_f.PIN4 = 1) +#define PB05_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN5 = 0) +#define PB05_DIR_INPUT() (CW_GPIOB->DIR_f.PIN5 = 1) +#define PB06_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN6 = 0) +#define PB06_DIR_INPUT() (CW_GPIOB->DIR_f.PIN6 = 1) +#define PB07_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN7 = 0) +#define PB07_DIR_INPUT() (CW_GPIOB->DIR_f.PIN7 = 1) +#define PB08_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN8 = 0) +#define PB08_DIR_INPUT() (CW_GPIOB->DIR_f.PIN8 = 1) +#define PB09_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN9 = 0) +#define PB09_DIR_INPUT() (CW_GPIOB->DIR_f.PIN9 = 1) +#define PB10_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN10 = 0) +#define PB10_DIR_INPUT() (CW_GPIOB->DIR_f.PIN10 = 1) +#define PB11_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN11 = 0) +#define PB11_DIR_INPUT() (CW_GPIOB->DIR_f.PIN11 = 1) +#define PB12_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN12 = 0) +#define PB12_DIR_INPUT() (CW_GPIOB->DIR_f.PIN12 = 1) +#define PB13_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN13 = 0) +#define PB13_DIR_INPUT() (CW_GPIOB->DIR_f.PIN13 = 1) +#define PB14_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN14 = 0) +#define PB14_DIR_INPUT() (CW_GPIOB->DIR_f.PIN14 = 1) +#define PB15_DIR_OUTPUT() (CW_GPIOB->DIR_f.PIN15 = 0) +#define PB15_DIR_INPUT() (CW_GPIOB->DIR_f.PIN15 = 1) + +#define PC13_DIR_OUTPUT() (CW_GPIOC->DIR_f.PIN13 = 0) +#define PC13_DIR_INPUT() (CW_GPIOC->DIR_f.PIN13 = 1) +#define PC14_DIR_OUTPUT() (CW_GPIOC->DIR_f.PIN14 = 0) +#define PC14_DIR_INPUT() (CW_GPIOC->DIR_f.PIN14 = 1) +#define PC15_DIR_OUTPUT() (CW_GPIOC->DIR_f.PIN15 = 0) +#define PC15_DIR_INPUT() (CW_GPIOC->DIR_f.PIN15 = 1) + +#define PF00_DIR_OUTPUT() (CW_GPIOF->DIR_f.PIN0 = 0) +#define PF00_DIR_INPUT() (CW_GPIOF->DIR_f.PIN0 = 1) +#define PF01_DIR_OUTPUT() (CW_GPIOF->DIR_f.PIN1 = 0) +#define PF01_DIR_INPUT() (CW_GPIOF->DIR_f.PIN1 = 1) +#define PF03_DIR_OUTPUT() (CW_GPIOF->DIR_f.PIN3 = 0) +#define PF03_DIR_INPUT() (CW_GPIOF->DIR_f.PIN3 = 1) +#define PF06_DIR_OUTPUT() (CW_GPIOF->DIR_f.PIN6 = 0) +#define PF06_DIR_INPUT() (CW_GPIOF->DIR_f.PIN6 = 1) +#define PF07_DIR_OUTPUT() (CW_GPIOF->DIR_f.PIN7 = 0) +#define PF07_DIR_INPUT() (CW_GPIOF->DIR_f.PIN7 = 1) + +//============================================================ +//push-pull or opendrain +#define PA00_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN0 = 0) +#define PA00_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN0 = 1) +#define PA01_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN1 = 0) +#define PA01_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN1 = 1) +#define PA02_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN2 = 0) +#define PA02_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN2 = 1) +#define PA03_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN3 = 0) +#define PA03_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN3 = 1) +#define PA04_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN4 = 0) +#define PA04_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN4 = 1) +#define PA05_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN5 = 0) +#define PA05_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN5 = 1) +#define PA06_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN6 = 0) +#define PA06_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN6 = 1) +#define PA07_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN7 = 0) +#define PA07_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN7 = 1) +#define PA08_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN8 = 0) +#define PA08_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN8 = 1) +#define PA09_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN9 = 0) +#define PA09_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN9 = 1) +#define PA10_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN10 = 0) +#define PA10_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN10 = 1) +#define PA11_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN11 = 0) +#define PA11_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN11 = 1) +#define PA12_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN12 = 0) +#define PA12_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN12 = 1) +#define PA13_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN13 = 0) +#define PA13_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN13 = 1) +#define PA14_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN14 = 0) +#define PA14_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN14 = 1) +#define PA15_PUSHPULL_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN15 = 0) +#define PA15_OPENDRAIN_ENABLE() (CW_GPIOA->OPENDRAIN_f.PIN15 = 1) + +#define PB00_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN0 = 0) +#define PB00_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN0 = 1) +#define PB01_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN1 = 0) +#define PB01_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN1 = 1) +#define PB02_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN2 = 0) +#define PB02_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN2 = 1) +#define PB03_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN3 = 0) +#define PB03_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN3 = 1) +#define PB04_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN4 = 0) +#define PB04_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN4 = 1) +#define PB05_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN5 = 0) +#define PB05_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN5 = 1) +#define PB06_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN6 = 0) +#define PB06_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN6 = 1) +#define PB07_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN7 = 0) +#define PB07_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN7 = 1) +#define PB08_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN8 = 0) +#define PB08_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN8 = 1) +#define PB09_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN9 = 0) +#define PB09_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN9 = 1) +#define PB10_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN10 = 0) +#define PB10_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN10 = 1) +#define PB11_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN11 = 0) +#define PB11_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN11 = 1) +#define PB12_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN12 = 0) +#define PB12_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN12 = 1) +#define PB13_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN13 = 0) +#define PB13_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN13 = 1) +#define PB14_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN14 = 0) +#define PB14_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN14 = 1) +#define PB15_PUSHPULL_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN15 = 0) +#define PB15_OPENDRAIN_ENABLE() (CW_GPIOB->OPENDRAIN_f.PIN15 = 1) + +#define PC13_PUSHPULL_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN13 = 0) +#define PC13_OPENDRAIN_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN13 = 1) +#define PC14_PUSHPULL_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN14 = 0) +#define PC14_OPENDRAIN_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN14 = 1) +#define PC15_PUSHPULL_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN15 = 0) +#define PC15_OPENDRAIN_ENABLE() (CW_GPIOC->OPENDRAIN_f.PIN15 = 1) + +#define PF00_PUSHPULL_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN0 = 0) +#define PF00_OPENDRAIN_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN0 = 1) +#define PF01_PUSHPULL_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN1 = 0) +#define PF01_OPENDRAIN_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN1 = 1) +#define PF03_PUSHPULL_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN3 = 0) +#define PF03_OPENDRAIN_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN3 = 1) +#define PF06_PUSHPULL_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN6 = 0) +#define PF06_OPENDRAIN_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN6 = 1) +#define PF07_PUSHPULL_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN7 = 0) +#define PF07_OPENDRAIN_ENABLE() (CW_GPIOF->OPENDRAIN_f.PIN7 = 1) + +//============================================================ +//PUR +#define PA00_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN0 = 1) +#define PA00_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN0 = 0) +#define PA01_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN1 = 1) +#define PA01_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN1 = 0) +#define PA02_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN2 = 1) +#define PA02_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN2 = 0) +#define PA03_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN3 = 1) +#define PA03_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN3 = 0) +#define PA04_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN4 = 1) +#define PA04_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN4 = 0) +#define PA05_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN5 = 1) +#define PA05_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN5 = 0) +#define PA06_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN6 = 1) +#define PA06_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN6 = 0) +#define PA07_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN7 = 1) +#define PA07_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN7 = 0) +#define PA08_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN8 = 1) +#define PA08_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN8 = 0) +#define PA09_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN9 = 1) +#define PA09_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN9 = 0) +#define PA10_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN10 = 1) +#define PA10_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN10 = 0) +#define PA11_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN11 = 1) +#define PA11_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN11 = 0) +#define PA12_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN12 = 1) +#define PA12_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN12 = 0) +#define PA13_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN13 = 1) +#define PA13_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN13 = 0) +#define PA14_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN14 = 1) +#define PA14_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN14 = 0) +#define PA15_PUR_ENABLE() (CW_GPIOA->PUR_f.PIN15 = 1) +#define PA15_PUR_DISABLE() (CW_GPIOA->PUR_f.PIN15 = 0) + +#define PB00_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN0 = 1) +#define PB00_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN0 = 0) +#define PB01_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN1 = 1) +#define PB01_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN1 = 0) +#define PB02_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN2 = 1) +#define PB02_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN2 = 0) +#define PB03_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN3 = 1) +#define PB03_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN3 = 0) +#define PB04_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN4 = 1) +#define PB04_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN4 = 0) +#define PB05_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN5 = 1) +#define PB05_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN5 = 0) +#define PB06_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN6 = 1) +#define PB06_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN6 = 0) +#define PB07_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN7 = 1) +#define PB07_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN7 = 0) +#define PB08_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN8 = 1) +#define PB08_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN8 = 0) +#define PB09_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN9 = 1) +#define PB09_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN9 = 0) +#define PB10_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN10 = 1) +#define PB10_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN10 = 0) +#define PB11_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN11 = 1) +#define PB11_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN11 = 0) +#define PB12_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN12 = 1) +#define PB12_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN12 = 0) +#define PB13_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN13 = 1) +#define PB13_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN13 = 0) +#define PB14_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN14 = 1) +#define PB14_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN14 = 0) +#define PB15_PUR_ENABLE() (CW_GPIOB->PUR_f.PIN15 = 1) +#define PB15_PUR_DISABLE() (CW_GPIOB->PUR_f.PIN15 = 0) + +#define PC13_PUR_ENABLE() (CW_GPIOC->PUR_f.PIN13 = 1) +#define PC13_PUR_DISABLE() (CW_GPIOC->PUR_f.PIN13 = 0) +#define PC14_PUR_ENABLE() (CW_GPIOC->PUR_f.PIN14 = 1) +#define PC14_PUR_DISABLE() (CW_GPIOC->PUR_f.PIN14 = 0) +#define PC15_PUR_ENABLE() (CW_GPIOC->PUR_f.PIN15 = 1) +#define PC15_PUR_DISABLE() (CW_GPIOC->PUR_f.PIN15 = 0) + +#define PF00_PUR_ENABLE() (CW_GPIOF->PUR_f.PIN0 = 1) +#define PF00_PUR_DISABLE() (CW_GPIOF->PUR_f.PIN0 = 0) +#define PF01_PUR_ENABLE() (CW_GPIOF->PUR_f.PIN1 = 1) +#define PF01_PUR_DISABLE() (CW_GPIOF->PUR_f.PIN1 = 0) +#define PF03_PUR_ENABLE() (CW_GPIOF->PUR_f.PIN3 = 1) +#define PF03_PUR_DISABLE() (CW_GPIOF->PUR_f.PIN3 = 0) +#define PF06_PUR_ENABLE() (CW_GPIOF->PUR_f.PIN6 = 1) +#define PF06_PUR_DISABLE() (CW_GPIOF->PUR_f.PIN6 = 0) +#define PF07_PUR_ENABLE() (CW_GPIOF->PUR_f.PIN7 = 1) +#define PF07_PUR_DISABLE() (CW_GPIOF->PUR_f.PIN7 = 0) + +//============================================================ +//PDR +#define PF03_PDR_ENABLE() (CW_GPIOF->PDR_f.PIN3 = 1) +#define PF03_PDR_DISABLE() (CW_GPIOF->PDR_f.PIN3 = 0) + +//============================================================ +// GETVALUE +#define PA00_GETVALUE() !!(CW_GPIOA->IDR & bv0) +#define PA01_GETVALUE() !!(CW_GPIOA->IDR & bv1) +#define PA02_GETVALUE() !!(CW_GPIOA->IDR & bv2) +#define PA03_GETVALUE() !!(CW_GPIOA->IDR & bv3) +#define PA04_GETVALUE() !!(CW_GPIOA->IDR & bv4) +#define PA05_GETVALUE() !!(CW_GPIOA->IDR & bv5) +#define PA06_GETVALUE() !!(CW_GPIOA->IDR & bv6) +#define PA07_GETVALUE() !!(CW_GPIOA->IDR & bv7) +#define PA08_GETVALUE() !!(CW_GPIOA->IDR & bv8) +#define PA09_GETVALUE() !!(CW_GPIOA->IDR & bv9) +#define PA10_GETVALUE() !!(CW_GPIOA->IDR & bv10) +#define PA11_GETVALUE() !!(CW_GPIOA->IDR & bv11) +#define PA12_GETVALUE() !!(CW_GPIOA->IDR & bv12) +#define PA13_GETVALUE() !!(CW_GPIOA->IDR & bv13) +#define PA14_GETVALUE() !!(CW_GPIOA->IDR & bv14) +#define PA15_GETVALUE() !!(CW_GPIOA->IDR & bv15) + +#define PB00_GETVALUE() !!(CW_GPIOB->IDR & bv0) +#define PB01_GETVALUE() !!(CW_GPIOB->IDR & bv1) +#define PB02_GETVALUE() !!(CW_GPIOB->IDR & bv2) +#define PB03_GETVALUE() !!(CW_GPIOB->IDR & bv3) +#define PB04_GETVALUE() !!(CW_GPIOB->IDR & bv4) +#define PB05_GETVALUE() !!(CW_GPIOB->IDR & bv5) +#define PB06_GETVALUE() !!(CW_GPIOB->IDR & bv6) +#define PB07_GETVALUE() !!(CW_GPIOB->IDR & bv7) +#define PB08_GETVALUE() !!(CW_GPIOB->IDR & bv8) +#define PB09_GETVALUE() !!(CW_GPIOB->IDR & bv9) +#define PB10_GETVALUE() !!(CW_GPIOB->IDR & bv10) +#define PB11_GETVALUE() !!(CW_GPIOB->IDR & bv11) +#define PB12_GETVALUE() !!(CW_GPIOB->IDR & bv12) +#define PB13_GETVALUE() !!(CW_GPIOB->IDR & bv13) +#define PB14_GETVALUE() !!(CW_GPIOB->IDR & bv14) +#define PB15_GETVALUE() !!(CW_GPIOB->IDR & bv15) + +#define PC13_GETVALUE() !!(CW_GPIOC->IDR & bv13) +#define PC14_GETVALUE() !!(CW_GPIOC->IDR & bv14) +#define PC15_GETVALUE() !!(CW_GPIOC->IDR & bv15) + +#define PF00_GETVALUE() !!(CW_GPIOF->IDR & bv0) +#define PF01_GETVALUE() !!(CW_GPIOF->IDR & bv1) +#define PF03_GETVALUE() !!(CW_GPIOF->IDR & bv3) +#define PF06_GETVALUE() !!(CW_GPIOF->IDR & bv6) +#define PF07_GETVALUE() !!(CW_GPIOF->IDR & bv7) + +//============================================================ +// SET HIGH AND LOW +#define PA00_SETHIGH() (CW_GPIOA->BSRR = bv0) +#define PA00_SETLOW() (CW_GPIOA->BRR = bv0) +#define PA01_SETHIGH() (CW_GPIOA->BSRR = bv1) +#define PA01_SETLOW() (CW_GPIOA->BRR = bv1) +#define PA02_SETHIGH() (CW_GPIOA->BSRR = bv2) +#define PA02_SETLOW() (CW_GPIOA->BRR = bv2) +#define PA03_SETHIGH() (CW_GPIOA->BSRR = bv3) +#define PA03_SETLOW() (CW_GPIOA->BRR = bv3) +#define PA04_SETHIGH() (CW_GPIOA->BSRR = bv4) +#define PA04_SETLOW() (CW_GPIOA->BRR = bv4) +#define PA05_SETHIGH() (CW_GPIOA->BSRR = bv5) +#define PA05_SETLOW() (CW_GPIOA->BRR = bv5) +#define PA06_SETHIGH() (CW_GPIOA->BSRR = bv6) +#define PA06_SETLOW() (CW_GPIOA->BRR = bv6) +#define PA07_SETHIGH() (CW_GPIOA->BSRR = bv7) +#define PA07_SETLOW() (CW_GPIOA->BRR = bv7) +#define PA08_SETHIGH() (CW_GPIOA->BSRR = bv8) +#define PA08_SETLOW() (CW_GPIOA->BRR = bv8) +#define PA09_SETHIGH() (CW_GPIOA->BSRR = bv9) +#define PA09_SETLOW() (CW_GPIOA->BRR = bv9) +#define PA10_SETHIGH() (CW_GPIOA->BSRR = bv10) +#define PA10_SETLOW() (CW_GPIOA->BRR = bv10) +#define PA11_SETHIGH() (CW_GPIOA->BSRR = bv11) +#define PA11_SETLOW() (CW_GPIOA->BRR = bv11) +#define PA12_SETHIGH() (CW_GPIOA->BSRR = bv12) +#define PA12_SETLOW() (CW_GPIOA->BRR = bv12) +#define PA13_SETHIGH() (CW_GPIOA->BSRR = bv13) +#define PA13_SETLOW() (CW_GPIOA->BRR = bv13) +#define PA14_SETHIGH() (CW_GPIOA->BSRR = bv14) +#define PA14_SETLOW() (CW_GPIOA->BRR = bv14) +#define PA15_SETHIGH() (CW_GPIOA->BSRR = bv15) +#define PA15_SETLOW() (CW_GPIOA->BRR = bv15) + +#define PB00_SETHIGH() (CW_GPIOB->BSRR = bv0) +#define PB00_SETLOW() (CW_GPIOB->BRR = bv0) +#define PB01_SETHIGH() (CW_GPIOB->BSRR = bv1) +#define PB01_SETLOW() (CW_GPIOB->BRR = bv1) +#define PB02_SETHIGH() (CW_GPIOB->BSRR = bv2) +#define PB02_SETLOW() (CW_GPIOB->BRR = bv2) +#define PB03_SETHIGH() (CW_GPIOB->BSRR = bv3) +#define PB03_SETLOW() (CW_GPIOB->BRR = bv3) +#define PB04_SETHIGH() (CW_GPIOB->BSRR = bv4) +#define PB04_SETLOW() (CW_GPIOB->BRR = bv4) +#define PB05_SETHIGH() (CW_GPIOB->BSRR = bv5) +#define PB05_SETLOW() (CW_GPIOB->BRR = bv5) +#define PB06_SETHIGH() (CW_GPIOB->BSRR = bv6) +#define PB06_SETLOW() (CW_GPIOB->BRR = bv6) +#define PB07_SETHIGH() (CW_GPIOB->BSRR = bv7) +#define PB07_SETLOW() (CW_GPIOB->BRR = bv7) +#define PB08_SETHIGH() (CW_GPIOB->BSRR = bv8) +#define PB08_SETLOW() (CW_GPIOB->BRR = bv8) +#define PB09_SETHIGH() (CW_GPIOB->BSRR = bv9) +#define PB09_SETLOW() (CW_GPIOB->BRR = bv9) +#define PB10_SETHIGH() (CW_GPIOB->BSRR = bv10) +#define PB10_SETLOW() (CW_GPIOB->BRR = bv10) +#define PB11_SETHIGH() (CW_GPIOB->BSRR = bv11) +#define PB11_SETLOW() (CW_GPIOB->BRR = bv11) +#define PB12_SETHIGH() (CW_GPIOB->BSRR = bv12) +#define PB12_SETLOW() (CW_GPIOB->BRR = bv12) +#define PB13_SETHIGH() (CW_GPIOB->BSRR = bv13) +#define PB13_SETLOW() (CW_GPIOB->BRR = bv13) +#define PB14_SETHIGH() (CW_GPIOB->BSRR = bv14) +#define PB14_SETLOW() (CW_GPIOB->BRR = bv14) +#define PB15_SETHIGH() (CW_GPIOB->BSRR = bv15) +#define PB15_SETLOW() (CW_GPIOB->BRR = bv15) + +#define PC13_SETHIGH() (CW_GPIOC->BSRR = bv13) +#define PC13_SETLOW() (CW_GPIOC->BRR = bv13) +#define PC14_SETHIGH() (CW_GPIOC->BSRR = bv14) +#define PC14_SETLOW() (CW_GPIOC->BRR = bv14) +#define PC15_SETHIGH() (CW_GPIOC->BSRR = bv15) +#define PC15_SETLOW() (CW_GPIOC->BRR = bv15) + +#define PF00_SETHIGH() (CW_GPIOF->BSRR = bv0) +#define PF00_SETLOW() (CW_GPIOF->BRR = bv0) +#define PF01_SETHIGH() (CW_GPIOF->BSRR = bv1) +#define PF01_SETLOW() (CW_GPIOF->BRR = bv1) +#define PF03_SETHIGH() (CW_GPIOF->BSRR = bv3) +#define PF03_SETLOW() (CW_GPIOF->BRR = bv3) +#define PF06_SETHIGH() (CW_GPIOF->BSRR = bv6) +#define PF06_SETLOW() (CW_GPIOF->BRR = bv6) +#define PF07_SETHIGH() (CW_GPIOF->BSRR = bv7) +#define PF07_SETLOW() (CW_GPIOF->BRR = bv7) + + +//============================================================ +// TOG +#define PA00_TOG() (CW_GPIOA->TOG = bv0) +#define PA01_TOG() (CW_GPIOA->TOG = bv1) +#define PA02_TOG() (CW_GPIOA->TOG = bv2) +#define PA03_TOG() (CW_GPIOA->TOG = bv3) +#define PA04_TOG() (CW_GPIOA->TOG = bv4) +#define PA05_TOG() (CW_GPIOA->TOG = bv5) +#define PA06_TOG() (CW_GPIOA->TOG = bv6) +#define PA07_TOG() (CW_GPIOA->TOG = bv7) +#define PA08_TOG() (CW_GPIOA->TOG = bv8) +#define PA09_TOG() (CW_GPIOA->TOG = bv9) +#define PA10_TOG() (CW_GPIOA->TOG = bv10) +#define PA11_TOG() (CW_GPIOA->TOG = bv11) +#define PA12_TOG() (CW_GPIOA->TOG = bv12) +#define PA13_TOG() (CW_GPIOA->TOG = bv13) +#define PA14_TOG() (CW_GPIOA->TOG = bv14) +#define PA15_TOG() (CW_GPIOA->TOG = bv15) + +#define PB00_TOG() (CW_GPIOB->TOG = bv0) +#define PB01_TOG() (CW_GPIOB->TOG = bv1) +#define PB02_TOG() (CW_GPIOB->TOG = bv2) +#define PB03_TOG() (CW_GPIOB->TOG = bv3) +#define PB04_TOG() (CW_GPIOB->TOG = bv4) +#define PB05_TOG() (CW_GPIOB->TOG = bv5) +#define PB06_TOG() (CW_GPIOB->TOG = bv6) +#define PB07_TOG() (CW_GPIOB->TOG = bv7) +#define PB08_TOG() (CW_GPIOB->TOG = bv8) +#define PB09_TOG() (CW_GPIOB->TOG = bv9) +#define PB10_TOG() (CW_GPIOB->TOG = bv10) +#define PB11_TOG() (CW_GPIOB->TOG = bv11) +#define PB12_TOG() (CW_GPIOB->TOG = bv12) +#define PB13_TOG() (CW_GPIOB->TOG = bv13) +#define PB14_TOG() (CW_GPIOB->TOG = bv14) +#define PB15_TOG() (CW_GPIOB->TOG = bv15) + +#define PC13_TOG() (CW_GPIOC->TOG = bv13) +#define PC14_TOG() (CW_GPIOC->TOG = bv14) +#define PC15_TOG() (CW_GPIOC->TOG = bv15) + +#define PF00_TOG() (CW_GPIOF->TOG = bv0) +#define PF01_TOG() (CW_GPIOF->TOG = bv1) +#define PF03_TOG() (CW_GPIOF->TOG = bv3) +#define PF06_TOG() (CW_GPIOF->TOG = bv6) +#define PF07_TOG() (CW_GPIOF->TOG = bv7) + +//============================================================ +// GPIOA +#define PA00_AFx_GPIO() (CW_GPIOA->AFRL_f.PIN0 = 0) +#define PA00_AFx_UART1CTS() (CW_GPIOA->AFRL_f.PIN0 = 1) +#define PA00_AFx_UART3RXD() (CW_GPIOA->AFRL_f.PIN0 = 2) +#define PA00_AFx_RTCTAMP() (CW_GPIOA->AFRL_f.PIN0 = 3) +#define PA00_AFx_VC1OUT() (CW_GPIOA->AFRL_f.PIN0 = 4) +#define PA00_AFx_BTIM3TOGN() (CW_GPIOA->AFRL_f.PIN0 = 5) +#define PA00_AFx_GTIM2CH1() (CW_GPIOA->AFRL_f.PIN0 = 6) +#define PA00_AFx_ATIMBKIN() (CW_GPIOA->AFRL_f.PIN0 = 7) +#define PA00_AFx_SPI2MISO() (CW_GPIOA->AFRL_f.PIN0 = 8) +#define PA00_AFx_VC3OUT() (CW_GPIOA->AFRL_f.PIN0 = 9) +#define PA01_AFx_GPIO() (CW_GPIOA->AFRL_f.PIN1 = 0) +#define PA01_AFx_UART1RTS() (CW_GPIOA->AFRL_f.PIN1 = 1) +#define PA01_AFx_UART3TXD() (CW_GPIOA->AFRL_f.PIN1 = 2) +#define PA01_AFx_RTCOUT() (CW_GPIOA->AFRL_f.PIN1 = 3) +#define PA01_AFx_HEXEN() (CW_GPIOA->AFRL_f.PIN1 = 4) +#define PA01_AFx_BTIM3TOGP() (CW_GPIOA->AFRL_f.PIN1 = 5) +#define PA01_AFx_GTIM2CH2() (CW_GPIOA->AFRL_f.PIN1 = 6) +#define PA01_AFx_ATIMETR() (CW_GPIOA->AFRL_f.PIN1 = 7) +#define PA01_AFx_SPI2MOSI() (CW_GPIOA->AFRL_f.PIN1 = 8) +#define PA02_AFx_GPIO() (CW_GPIOA->AFRL_f.PIN2 = 0) +#define PA02_AFx_UART1TXD() (CW_GPIOA->AFRL_f.PIN2 = 1) +#define PA02_AFx_UART2TXD() (CW_GPIOA->AFRL_f.PIN2 = 2) +#define PA02_AFx_BTIM2ETR() (CW_GPIOA->AFRL_f.PIN2 = 3) +#define PA02_AFx_VC2OUT() (CW_GPIOA->AFRL_f.PIN2 = 4) +#define PA02_AFx_LPTIMCH1() (CW_GPIOA->AFRL_f.PIN2 = 5) +#define PA02_AFx_GTIM2CH3() (CW_GPIOA->AFRL_f.PIN2 = 6) +#define PA02_AFx_ATIMCH4N() (CW_GPIOA->AFRL_f.PIN2 = 7) +#define PA02_AFx_SPI2SCK() (CW_GPIOA->AFRL_f.PIN2 = 8) +#define PA03_AFx_GPIO() (CW_GPIOA->AFRL_f.PIN3 = 0) +#define PA03_AFx_UART1RXD() (CW_GPIOA->AFRL_f.PIN3 = 1) +#define PA03_AFx_UART2RXD() (CW_GPIOA->AFRL_f.PIN3 = 2) +#define PA03_AFx_RTCOUT() (CW_GPIOA->AFRL_f.PIN3 = 3) +#define PA03_AFx_PCLKOUT() (CW_GPIOA->AFRL_f.PIN3 = 4) +#define PA03_AFx_LPTIMCH2() (CW_GPIOA->AFRL_f.PIN3 = 5) +#define PA03_AFx_GTIM2CH4() (CW_GPIOA->AFRL_f.PIN3 = 6) +#define PA03_AFx_ATIMCH4() (CW_GPIOA->AFRL_f.PIN3 = 7) +#define PA03_AFx_SPI2NCS() (CW_GPIOA->AFRL_f.PIN3 = 8) +#define PA03_AFx_HALLTIMCH1() (CW_GPIOA->AFRL_f.PIN3 = 9) +#define PA04_AFx_GPIO() (CW_GPIOA->AFRL_f.PIN4 = 0) +#define PA04_AFx_UART3TXD() (CW_GPIOA->AFRL_f.PIN4 = 1) +#define PA04_AFx_I2C1SCL() (CW_GPIOA->AFRL_f.PIN4 = 2) +#define PA04_AFx_SPI1NCS() (CW_GPIOA->AFRL_f.PIN4 = 3) +#define PA04_AFx_MCOOUT() (CW_GPIOA->AFRL_f.PIN4 = 4) +#define PA04_AFx_LPTIMOUT() (CW_GPIOA->AFRL_f.PIN4 = 5) +#define PA04_AFx_ADC2SAM() (CW_GPIOA->AFRL_f.PIN4 = 6) +#define PA04_AFx_ATIMCH2N() (CW_GPIOA->AFRL_f.PIN4 = 7) +#define PA04_AFx_GTIM3CH1() (CW_GPIOA->AFRL_f.PIN4 = 8) +#define PA04_AFx_HALLTIMCH2() (CW_GPIOA->AFRL_f.PIN4 = 9) +#define PA05_AFx_GPIO() (CW_GPIOA->AFRL_f.PIN5 = 0) +#define PA05_AFx_UART3RXD() (CW_GPIOA->AFRL_f.PIN5 = 1) +#define PA05_AFx_I2C1SDA() (CW_GPIOA->AFRL_f.PIN5 = 2) +#define PA05_AFx_SPI1SCK() (CW_GPIOA->AFRL_f.PIN5 = 3) +#define PA05_AFx_BTIM2TOGN() (CW_GPIOA->AFRL_f.PIN5 = 4) +#define PA05_AFx_LPTIMETR() (CW_GPIOA->AFRL_f.PIN5 = 5) +#define PA05_AFx_GTIM1CH3() (CW_GPIOA->AFRL_f.PIN5 = 6) +#define PA05_AFx_ATIMCH1() (CW_GPIOA->AFRL_f.PIN5 = 7) +#define PA05_AFx_GTIM3CH2() (CW_GPIOA->AFRL_f.PIN5 = 8) +#define PA05_AFx_HALLTIMCH3() (CW_GPIOA->AFRL_f.PIN5 = 9) +#define PA06_AFx_GPIO() (CW_GPIOA->AFRL_f.PIN6 = 0) +#define PA06_AFx_UART2RXD() (CW_GPIOA->AFRL_f.PIN6 = 1) +#define PA06_AFx_BTIM1ETR() (CW_GPIOA->AFRL_f.PIN6 = 2) +#define PA06_AFx_SPI1MISO() (CW_GPIOA->AFRL_f.PIN6 = 3) +#define PA06_AFx_BTIM2TOGP() (CW_GPIOA->AFRL_f.PIN6 = 4) +#define PA06_AFx_LPTIMCH1() (CW_GPIOA->AFRL_f.PIN6 = 5) +#define PA06_AFx_GTIM1CH1() (CW_GPIOA->AFRL_f.PIN6 = 6) +#define PA06_AFx_ATIMBKIN() (CW_GPIOA->AFRL_f.PIN6 = 7) +#define PA06_AFx_GTIM3CH3() (CW_GPIOA->AFRL_f.PIN6 = 8) +#define PA07_AFx_GPIO() (CW_GPIOA->AFRL_f.PIN7 = 0) +#define PA07_AFx_UART2TXD() (CW_GPIOA->AFRL_f.PIN7 = 1) +#define PA07_AFx_GTIM2ETR() (CW_GPIOA->AFRL_f.PIN7 = 2) +#define PA07_AFx_SPI1MOSI() (CW_GPIOA->AFRL_f.PIN7 = 3) +#define PA07_AFx_BTIM1TOGN() (CW_GPIOA->AFRL_f.PIN7 = 4) +#define PA07_AFx_LPTIMCH2() (CW_GPIOA->AFRL_f.PIN7 = 5) +#define PA07_AFx_GTIM1CH2() (CW_GPIOA->AFRL_f.PIN7 = 6) +#define PA07_AFx_ATIMCH1N() (CW_GPIOA->AFRL_f.PIN7 = 7) +#define PA07_AFx_GTIM3CH4() (CW_GPIOA->AFRL_f.PIN7 = 8) +#define PA08_AFx_GPIO() (CW_GPIOA->AFRH_f.PIN8 = 0) +#define PA08_AFx_UART3TXD() (CW_GPIOA->AFRH_f.PIN8 = 1) +#define PA08_AFx_VC4OUT() (CW_GPIOA->AFRH_f.PIN8 = 2) +#define PA08_AFx_IROUT() (CW_GPIOA->AFRH_f.PIN8 = 3) +#define PA08_AFx_MCOOUT() (CW_GPIOA->AFRH_f.PIN8 = 4) +#define PA08_AFx_BTIM2TOGP() (CW_GPIOA->AFRH_f.PIN8 = 5) +#define PA08_AFx_LVDOUT() (CW_GPIOA->AFRH_f.PIN8 = 6) +#define PA08_AFx_ATIMCH1() (CW_GPIOA->AFRH_f.PIN8 = 7) +#define PA08_AFx_SPI3NCS() (CW_GPIOA->AFRH_f.PIN8 = 8) +#define PA08_AFx_GTIM4ETR() (CW_GPIOA->AFRH_f.PIN8 = 9) +#define PA09_AFx_GPIO() (CW_GPIOA->AFRH_f.PIN9 = 0) +#define PA09_AFx_UART1TXD() (CW_GPIOA->AFRH_f.PIN9 = 1) +#define PA09_AFx_UART3RXD() (CW_GPIOA->AFRH_f.PIN9 = 2) +#define PA09_AFx_SPI1NCS() (CW_GPIOA->AFRH_f.PIN9 = 3) +#define PA09_AFx_I2C1SCL() (CW_GPIOA->AFRH_f.PIN9 = 4) +#define PA09_AFx_LPTIMETR() (CW_GPIOA->AFRH_f.PIN9 = 5) +#define PA09_AFx_BTIM1TOGN() (CW_GPIOA->AFRH_f.PIN9 = 6) +#define PA09_AFx_ATIMCH2() (CW_GPIOA->AFRH_f.PIN9 = 7) +#define PA09_AFx_SPI3SCK() (CW_GPIOA->AFRH_f.PIN9 = 8) +#define PA09_AFx_GTIM4CH1() (CW_GPIOA->AFRH_f.PIN9 = 9) +#define PA10_AFx_GPIO() (CW_GPIOA->AFRH_f.PIN10 = 0) +#define PA10_AFx_UART1RXD() (CW_GPIOA->AFRH_f.PIN10 = 1) +#define PA10_AFx_BTIM3ETR() (CW_GPIOA->AFRH_f.PIN10 = 2) +#define PA10_AFx_SPI1SCK() (CW_GPIOA->AFRH_f.PIN10 = 3) +#define PA10_AFx_I2C1SDA() (CW_GPIOA->AFRH_f.PIN10 = 4) +#define PA10_AFx_LPTIMOUT() (CW_GPIOA->AFRH_f.PIN10 = 5) +#define PA10_AFx_BTIM1TOGP() (CW_GPIOA->AFRH_f.PIN10 = 6) +#define PA10_AFx_ATIMCH3() (CW_GPIOA->AFRH_f.PIN10 = 7) +#define PA10_AFx_SPI3MISO() (CW_GPIOA->AFRH_f.PIN10 = 8) +#define PA10_AFx_GTIM4CH2() (CW_GPIOA->AFRH_f.PIN10 = 9) +#define PA11_AFx_GPIO() (CW_GPIOA->AFRH_f.PIN11 = 0) +#define PA11_AFx_UART1CTS() (CW_GPIOA->AFRH_f.PIN11 = 1) +#define PA11_AFx_VC1OUT() (CW_GPIOA->AFRH_f.PIN11 = 2) +#define PA11_AFx_SPI1MISO() (CW_GPIOA->AFRH_f.PIN11 = 3) +#define PA11_AFx_HEXEN() (CW_GPIOA->AFRH_f.PIN11 = 4) +#define PA11_AFx_ATIMBK2IN() (CW_GPIOA->AFRH_f.PIN11 = 5) +#define PA11_AFx_GTIM2CH2() (CW_GPIOA->AFRH_f.PIN11 = 6) +#define PA11_AFx_ATIMCH4() (CW_GPIOA->AFRH_f.PIN11 = 7) +#define PA11_AFx_SPI3MOSI() (CW_GPIOA->AFRH_f.PIN11 = 8) +#define PA11_AFx_GTIM4CH3() (CW_GPIOA->AFRH_f.PIN11 = 9) +#define PA12_AFx_GPIO() (CW_GPIOA->AFRH_f.PIN12 = 0) +#define PA12_AFx_UART1RTS() (CW_GPIOA->AFRH_f.PIN12 = 1) +#define PA12_AFx_VC2OUT() (CW_GPIOA->AFRH_f.PIN12 = 2) +#define PA12_AFx_SPI1MOSI() (CW_GPIOA->AFRH_f.PIN12 = 3) +#define PA12_AFx_BTIM3ETR() (CW_GPIOA->AFRH_f.PIN12 = 4) +#define PA12_AFx_ATIMBKIN() (CW_GPIOA->AFRH_f.PIN12 = 5) +#define PA12_AFx_GTIM2CH3() (CW_GPIOA->AFRH_f.PIN12 = 6) +#define PA12_AFx_ATIMETR() (CW_GPIOA->AFRH_f.PIN12 = 7) +#define PA12_AFx_GTIM3ETR() (CW_GPIOA->AFRH_f.PIN12 = 8) +#define PA12_AFx_GTIM4CH4() (CW_GPIOA->AFRH_f.PIN12 = 9) +#define PA13_AFx_GPIO() (CW_GPIOA->AFRH_f.PIN13 = 0) +#define PA13_AFx_UART1RXD() (CW_GPIOA->AFRH_f.PIN13 = 1) +#define PA13_AFx_UART3TXD() (CW_GPIOA->AFRH_f.PIN13 = 2) +#define PA13_AFx_UART2RTS() (CW_GPIOA->AFRH_f.PIN13 = 3) +#define PA13_AFx_I2C1SDA() (CW_GPIOA->AFRH_f.PIN13 = 4) +#define PA13_AFx_ATIMBKIN() (CW_GPIOA->AFRH_f.PIN13 = 5) +#define PA13_AFx_IROUT() (CW_GPIOA->AFRH_f.PIN13 = 6) +#define PA13_AFx_ATIMCH6() (CW_GPIOA->AFRH_f.PIN13 = 7) +#define PA13_AFx_ATIMCH5N() (CW_GPIOA->AFRH_f.PIN13 = 8) +#define PA14_AFx_GPIO() (CW_GPIOA->AFRH_f.PIN14 = 0) +#define PA14_AFx_UART1TXD() (CW_GPIOA->AFRH_f.PIN14 = 1) +#define PA14_AFx_UART3RXD() (CW_GPIOA->AFRH_f.PIN14 = 2) +#define PA14_AFx_UART2CTS() (CW_GPIOA->AFRH_f.PIN14 = 3) +#define PA14_AFx_I2C1SCL() (CW_GPIOA->AFRH_f.PIN14 = 4) +#define PA14_AFx_ATIMBK2IN() (CW_GPIOA->AFRH_f.PIN14 = 5) +#define PA14_AFx_GTIM1ETR() (CW_GPIOA->AFRH_f.PIN14 = 6) +#define PA14_AFx_ATIMCH6N() (CW_GPIOA->AFRH_f.PIN14 = 7) +#define PA14_AFx_ATIMCH5() (CW_GPIOA->AFRH_f.PIN14 = 8) +#define PA15_AFx_GPIO() (CW_GPIOA->AFRH_f.PIN15 = 0) +#define PA15_AFx_UART1RXD() (CW_GPIOA->AFRH_f.PIN15 = 1) +#define PA15_AFx_UART2RXD() (CW_GPIOA->AFRH_f.PIN15 = 2) +#define PA15_AFx_SPI1NCS() (CW_GPIOA->AFRH_f.PIN15 = 3) +#define PA15_AFx_ATIMBKOUT() (CW_GPIOA->AFRH_f.PIN15 = 4) +#define PA15_AFx_GTIM2CH1() (CW_GPIOA->AFRH_f.PIN15 = 5) +#define PA15_AFx_GTIM2ETR() (CW_GPIOA->AFRH_f.PIN15 = 6) +#define PA15_AFx_ATIMCH1N() (CW_GPIOA->AFRH_f.PIN15 = 7) +#define PA15_AFx_GTIM3CH1() (CW_GPIOA->AFRH_f.PIN15 = 8) +#define PA15_AFx_SPI2SCK() (CW_GPIOA->AFRH_f.PIN15 = 9) + +//============================================================ +// GPIOB +#define PB00_AFx_GPIO() (CW_GPIOB->AFRL_f.PIN0 = 0) +#define PB00_AFx_UART1RXD() (CW_GPIOB->AFRL_f.PIN0 = 1) +#define PB00_AFx_UART2TXD() (CW_GPIOB->AFRL_f.PIN0 = 2) +#define PB00_AFx_HSIOSCOUT() (CW_GPIOB->AFRL_f.PIN0 = 3) +#define PB00_AFx_BTIM1TOGP() (CW_GPIOB->AFRL_f.PIN0 = 4) +#define PB00_AFx_ATIMETR() (CW_GPIOB->AFRL_f.PIN0 = 5) +#define PB00_AFx_GTIM1CH3() (CW_GPIOB->AFRL_f.PIN0 = 6) +#define PB00_AFx_ATIMCH2N() (CW_GPIOB->AFRL_f.PIN0 = 7) +#define PB00_AFx_I2C2SCL() (CW_GPIOB->AFRL_f.PIN0 = 8) +#define PB00_AFx_HALLTIMOUT() (CW_GPIOB->AFRL_f.PIN0 = 9) +#define PB01_AFx_GPIO() (CW_GPIOB->AFRL_f.PIN1 = 0) +#define PB01_AFx_UART1TXD() (CW_GPIOB->AFRL_f.PIN1 = 1) +#define PB01_AFx_UART2RXD() (CW_GPIOB->AFRL_f.PIN1 = 2) +#define PB01_AFx_RTCTAMP() (CW_GPIOB->AFRL_f.PIN1 = 3) +#define PB01_AFx_IROUT() (CW_GPIOB->AFRL_f.PIN1 = 4) +#define PB01_AFx_BTIM3TOGN() (CW_GPIOB->AFRL_f.PIN1 = 5) +#define PB01_AFx_GTIM1CH4() (CW_GPIOB->AFRL_f.PIN1 = 6) +#define PB01_AFx_ATIMCH3N() (CW_GPIOB->AFRL_f.PIN1 = 7) +#define PB01_AFx_I2C2SDA() (CW_GPIOB->AFRL_f.PIN1 = 8) +#define PB01_AFx_HALLTIMTRGO() (CW_GPIOB->AFRL_f.PIN1 = 9) +#define PB02_AFx_GPIO() (CW_GPIOB->AFRL_f.PIN2 = 0) +#define PB02_AFx_UART3TXD() (CW_GPIOB->AFRL_f.PIN2 = 1) +#define PB02_AFx_UART2CTS() (CW_GPIOB->AFRL_f.PIN2 = 2) +#define PB02_AFx_ATIMBKOUT() (CW_GPIOB->AFRL_f.PIN2 = 3) +#define PB02_AFx_HSEOUT() (CW_GPIOB->AFRL_f.PIN2 = 4) +#define PB02_AFx_BTIM3TOGP() (CW_GPIOB->AFRL_f.PIN2 = 5) +#define PB02_AFx_GTIM1ETR() (CW_GPIOB->AFRL_f.PIN2 = 6) +#define PB02_AFx_ATIMCH1() (CW_GPIOB->AFRL_f.PIN2 = 7) +#define PB02_AFx_GTIM3TRGO() (CW_GPIOB->AFRL_f.PIN2 = 8) +#define PB02_AFx_HALLTIMCH1() (CW_GPIOB->AFRL_f.PIN2 = 9) +#define PB03_AFx_GPIO() (CW_GPIOB->AFRL_f.PIN3 = 0) +#define PB03_AFx_UART1TXD() (CW_GPIOB->AFRL_f.PIN3 = 1) +#define PB03_AFx_UART2TXD() (CW_GPIOB->AFRL_f.PIN3 = 2) +#define PB03_AFx_SPI1SCK() (CW_GPIOB->AFRL_f.PIN3 = 3) +#define PB03_AFx_UART3CTS() (CW_GPIOB->AFRL_f.PIN3 = 4) +#define PB03_AFx_GTIM2CH2() (CW_GPIOB->AFRL_f.PIN3 = 5) +#define PB03_AFx_GTIM1ETR() (CW_GPIOB->AFRL_f.PIN3 = 6) +#define PB03_AFx_ATIMCH2N() (CW_GPIOB->AFRL_f.PIN3 = 7) +#define PB03_AFx_GTIM3CH2() (CW_GPIOB->AFRL_f.PIN3 = 8) +#define PB03_AFx_SPI2MISO() (CW_GPIOB->AFRL_f.PIN3 = 9) +#define PB04_AFx_GPIO() (CW_GPIOB->AFRL_f.PIN4 = 0) +#define PB04_AFx_UART3TXD() (CW_GPIOB->AFRL_f.PIN4 = 1) +#define PB04_AFx_UART2CTS() (CW_GPIOB->AFRL_f.PIN4 = 2) +#define PB04_AFx_SPI1MISO() (CW_GPIOB->AFRL_f.PIN4 = 3) +#define PB04_AFx_UART3RTS() (CW_GPIOB->AFRL_f.PIN4 = 4) +#define PB04_AFx_ATIMETR() (CW_GPIOB->AFRL_f.PIN4 = 5) +#define PB04_AFx_GTIM1CH1() (CW_GPIOB->AFRL_f.PIN4 = 6) +#define PB04_AFx_ATIMCH3N() (CW_GPIOB->AFRL_f.PIN4 = 7) +#define PB04_AFx_GTIM3CH3() (CW_GPIOB->AFRL_f.PIN4 = 8) +#define PB04_AFx_SPI2MOSI() (CW_GPIOB->AFRL_f.PIN4 = 9) +#define PB05_AFx_GPIO() (CW_GPIOB->AFRL_f.PIN5 = 0) +#define PB05_AFx_UART3RXD() (CW_GPIOB->AFRL_f.PIN5 = 1) +#define PB05_AFx_UART2RTS() (CW_GPIOB->AFRL_f.PIN5 = 2) +#define PB05_AFx_SPI1MOSI() (CW_GPIOB->AFRL_f.PIN5 = 3) +#define PB05_AFx_ADC1SAM() (CW_GPIOB->AFRL_f.PIN5 = 4) +#define PB05_AFx_ATIMBKIN() (CW_GPIOB->AFRL_f.PIN5 = 5) +#define PB05_AFx_GTIM1CH2() (CW_GPIOB->AFRL_f.PIN5 = 6) +#define PB05_AFx_ATIMCH1() (CW_GPIOB->AFRL_f.PIN5 = 7) +#define PB05_AFx_GTIM3CH4() (CW_GPIOB->AFRL_f.PIN5 = 8) +#define PB05_AFx_HALLTIMCH1() (CW_GPIOB->AFRL_f.PIN5 = 9) +#define PB06_AFx_GPIO() (CW_GPIOB->AFRL_f.PIN6 = 0) +#define PB06_AFx_UART1TXD() (CW_GPIOB->AFRL_f.PIN6 = 1) +#define PB06_AFx_UART2RXD() (CW_GPIOB->AFRL_f.PIN6 = 2) +#define PB06_AFx_I2C1SCL() (CW_GPIOB->AFRL_f.PIN6 = 3) +#define PB06_AFx_BTIM3TOGN() (CW_GPIOB->AFRL_f.PIN6 = 4) +#define PB06_AFx_GTIM2CH3() (CW_GPIOB->AFRL_f.PIN6 = 5) +#define PB06_AFx_GTIM1CH3() (CW_GPIOB->AFRL_f.PIN6 = 6) +#define PB06_AFx_ATIMCH2() (CW_GPIOB->AFRL_f.PIN6 = 7) +#define PB06_AFx_SPI3MOSI() (CW_GPIOB->AFRL_f.PIN6 = 8) +#define PB06_AFx_HALLTIMCH2() (CW_GPIOB->AFRL_f.PIN6 = 9) +#define PB07_AFx_GPIO() (CW_GPIOB->AFRL_f.PIN7 = 0) +#define PB07_AFx_UART1RXD() (CW_GPIOB->AFRL_f.PIN7 = 1) +#define PB07_AFx_UART2TXD() (CW_GPIOB->AFRL_f.PIN7 = 2) +#define PB07_AFx_I2C1SDA() (CW_GPIOB->AFRL_f.PIN7 = 3) +#define PB07_AFx_BTIM3TOGP() (CW_GPIOB->AFRL_f.PIN7 = 4) +#define PB07_AFx_GTIM2CH4() (CW_GPIOB->AFRL_f.PIN7 = 5) +#define PB07_AFx_GTIM1CH4() (CW_GPIOB->AFRL_f.PIN7 = 6) +#define PB07_AFx_ATIMCH3() (CW_GPIOB->AFRL_f.PIN7 = 7) +#define PB07_AFx_SPI3MISO() (CW_GPIOB->AFRL_f.PIN7 = 8) +#define PB07_AFx_HALLTIMCH3() (CW_GPIOB->AFRL_f.PIN7 = 9) +#define PB08_AFx_GPIO() (CW_GPIOB->AFRH_f.PIN8 = 0) +#define PB08_AFx_UART2RXD() (CW_GPIOB->AFRH_f.PIN8 = 1) +#define PB08_AFx_UART3TXD() (CW_GPIOB->AFRH_f.PIN8 = 2) +#define PB08_AFx_I2C1SCL() (CW_GPIOB->AFRH_f.PIN8 = 3) +#define PB08_AFx_ADC2SAM() (CW_GPIOB->AFRH_f.PIN8 = 4) +#define PB08_AFx_ATIMCH4N() (CW_GPIOB->AFRH_f.PIN8 = 5) +#define PB08_AFx_GTIM1CH3() (CW_GPIOB->AFRH_f.PIN8 = 6) +#define PB08_AFx_ATIMETR() (CW_GPIOB->AFRH_f.PIN8 = 7) +#define PB08_AFx_SPI3SCK() (CW_GPIOB->AFRH_f.PIN8 = 8) +#define PB09_AFx_GPIO() (CW_GPIOB->AFRH_f.PIN9 = 0) +#define PB09_AFx_UART2TXD() (CW_GPIOB->AFRH_f.PIN9 = 1) +#define PB09_AFx_UART3RXD() (CW_GPIOB->AFRH_f.PIN9 = 2) +#define PB09_AFx_I2C1SDA() (CW_GPIOB->AFRH_f.PIN9 = 3) +#define PB09_AFx_IROUT() (CW_GPIOB->AFRH_f.PIN9 = 4) +#define PB09_AFx_ATIMCH4() (CW_GPIOB->AFRH_f.PIN9 = 5) +#define PB09_AFx_GTIM1CH4() (CW_GPIOB->AFRH_f.PIN9 = 6) +#define PB09_AFx_ATIMBKIN() (CW_GPIOB->AFRH_f.PIN9 = 7) +#define PB09_AFx_SPI3NCS() (CW_GPIOB->AFRH_f.PIN9 = 8) +#define PB10_AFx_GPIO() (CW_GPIOB->AFRH_f.PIN10 = 0) +#define PB10_AFx_UART3RXD() (CW_GPIOB->AFRH_f.PIN10 = 1) +#define PB10_AFx_UART2RTS() (CW_GPIOB->AFRH_f.PIN10 = 2) +#define PB10_AFx_I2C1SCL() (CW_GPIOB->AFRH_f.PIN10 = 3) +#define PB10_AFx_ATIMBK2IN() (CW_GPIOB->AFRH_f.PIN10 = 4) +#define PB10_AFx_VC4OUT() (CW_GPIOB->AFRH_f.PIN10 = 5) +#define PB10_AFx_GTIM2CH3() (CW_GPIOB->AFRH_f.PIN10 = 6) +#define PB10_AFx_ATIMCH2() (CW_GPIOB->AFRH_f.PIN10 = 7) +#define PB10_AFx_I2C2SCL() (CW_GPIOB->AFRH_f.PIN10 = 8) +#define PB10_AFx_HALLTIMCH2() (CW_GPIOB->AFRH_f.PIN10 = 9) +#define PB11_AFx_GPIO() (CW_GPIOB->AFRH_f.PIN11 = 0) +#define PB11_AFx_UART1RXD() (CW_GPIOB->AFRH_f.PIN11 = 1) +#define PB11_AFx_ATIMBK2OUT() (CW_GPIOB->AFRH_f.PIN11 = 2) +#define PB11_AFx_I2C1SDA() (CW_GPIOB->AFRH_f.PIN11 = 3) +#define PB11_AFx_LSIOUT() (CW_GPIOB->AFRH_f.PIN11 = 4) +#define PB11_AFx_BTIM1ETR() (CW_GPIOB->AFRH_f.PIN11 = 5) +#define PB11_AFx_GTIM2CH4() (CW_GPIOB->AFRH_f.PIN11 = 6) +#define PB11_AFx_ATIMCH3() (CW_GPIOB->AFRH_f.PIN11 = 7) +#define PB11_AFx_I2C2SDA() (CW_GPIOB->AFRH_f.PIN11 = 8) +#define PB11_AFx_HALLTIMCH3() (CW_GPIOB->AFRH_f.PIN11 = 9) +#define PB12_AFx_GPIO() (CW_GPIOB->AFRH_f.PIN12 = 0) +#define PB12_AFx_UART1TXD() (CW_GPIOB->AFRH_f.PIN12 = 1) +#define PB12_AFx_LPTIMOUT() (CW_GPIOB->AFRH_f.PIN12 = 2) +#define PB12_AFx_SPI1NCS() (CW_GPIOB->AFRH_f.PIN12 = 3) +#define PB12_AFx_LSEOUT() (CW_GPIOB->AFRH_f.PIN12 = 4) +#define PB12_AFx_VC1OUT() (CW_GPIOB->AFRH_f.PIN12 = 5) +#define PB12_AFx_ATIMTRGO() (CW_GPIOB->AFRH_f.PIN12 = 6) +#define PB12_AFx_ATIMBKIN() (CW_GPIOB->AFRH_f.PIN12 = 7) +#define PB12_AFx_SPI2NCS() (CW_GPIOB->AFRH_f.PIN12 = 8) +#define PB12_AFx_HALLTIMOUT() (CW_GPIOB->AFRH_f.PIN12 = 9) +#define PB13_AFx_GPIO() (CW_GPIOB->AFRH_f.PIN13 = 0) +#define PB13_AFx_UART2RXD() (CW_GPIOB->AFRH_f.PIN13 = 1) +#define PB13_AFx_LPTIMETR() (CW_GPIOB->AFRH_f.PIN13 = 2) +#define PB13_AFx_SPI1SCK() (CW_GPIOB->AFRH_f.PIN13 = 3) +#define PB13_AFx_ATIMBK2IN() (CW_GPIOB->AFRH_f.PIN13 = 4) +#define PB13_AFx_VC2OUT() (CW_GPIOB->AFRH_f.PIN13 = 5) +#define PB13_AFx_ATIMTRGO2() (CW_GPIOB->AFRH_f.PIN13 = 6) +#define PB13_AFx_ATIMCH1N() (CW_GPIOB->AFRH_f.PIN13 = 7) +#define PB13_AFx_SPI2SCK() (CW_GPIOB->AFRH_f.PIN13 = 8) +#define PB13_AFx_HALLTIMCH1() (CW_GPIOB->AFRH_f.PIN13 = 9) +#define PB14_AFx_GPIO() (CW_GPIOB->AFRH_f.PIN14 = 0) +#define PB14_AFx_UART2TXD() (CW_GPIOB->AFRH_f.PIN14 = 1) +#define PB14_AFx_LPTIMCH2() (CW_GPIOB->AFRH_f.PIN14 = 2) +#define PB14_AFx_SPI1MISO() (CW_GPIOB->AFRH_f.PIN14 = 3) +#define PB14_AFx_RTCOUT() (CW_GPIOB->AFRH_f.PIN14 = 4) +#define PB14_AFx_VC3OUT() (CW_GPIOB->AFRH_f.PIN14 = 5) +#define PB14_AFx_GTIM2CH1() (CW_GPIOB->AFRH_f.PIN14 = 6) +#define PB14_AFx_ATIMCH2N() (CW_GPIOB->AFRH_f.PIN14 = 7) +#define PB14_AFx_SPI2MISO() (CW_GPIOB->AFRH_f.PIN14 = 8) +#define PB14_AFx_HALLTIMCH2() (CW_GPIOB->AFRH_f.PIN14 = 9) +#define PB15_AFx_GPIO() (CW_GPIOB->AFRH_f.PIN15 = 0) +#define PB15_AFx_UART3RXD() (CW_GPIOB->AFRH_f.PIN15 = 1) +#define PB15_AFx_LPTIMCH1() (CW_GPIOB->AFRH_f.PIN15 = 2) +#define PB15_AFx_SPI1MOSI() (CW_GPIOB->AFRH_f.PIN15 = 3) +#define PB15_AFx_RTCOUT() (CW_GPIOB->AFRH_f.PIN15 = 4) +#define PB15_AFx_BTIM2TOGN() (CW_GPIOB->AFRH_f.PIN15 = 5) +#define PB15_AFx_GTIM2CH2() (CW_GPIOB->AFRH_f.PIN15 = 6) +#define PB15_AFx_ATIMCH3N() (CW_GPIOB->AFRH_f.PIN15 = 7) +#define PB15_AFx_SPI2MOSI() (CW_GPIOB->AFRH_f.PIN15 = 8) +#define PB15_AFx_HALLTIMCH3() (CW_GPIOB->AFRH_f.PIN15 = 9) + +//============================================================ +// GPIOC +#define PC13_AFx_GPIO() (CW_GPIOC->AFRH_f.PIN13 = 0) +#define PC13_AFx_MCOOUT() (CW_GPIOC->AFRH_f.PIN13 = 1) +#define PC13_AFx_RTCTAMP() (CW_GPIOC->AFRH_f.PIN13 = 3) +#define PC13_AFx_RTCOUT() (CW_GPIOC->AFRH_f.PIN13 = 4) +#define PC13_AFx_BTIM2ETR() (CW_GPIOC->AFRH_f.PIN13 = 5) +#define PC13_AFx_ATIMBKIN() (CW_GPIOC->AFRH_f.PIN13 = 6) +#define PC13_AFx_ATIMETR() (CW_GPIOC->AFRH_f.PIN13 = 7) +#define PC13_AFx_GTIM3ETR() (CW_GPIOC->AFRH_f.PIN13 = 8) +#define PC13_AFx_GTIM4ETR() (CW_GPIOC->AFRH_f.PIN13 = 9) +#define PC14_AFx_GPIO() (CW_GPIOC->AFRH_f.PIN14 = 0) +#define PC14_AFx_UART1RXD() (CW_GPIOC->AFRH_f.PIN14 = 1) +#define PC14_AFx_UART2RXD() (CW_GPIOC->AFRH_f.PIN14 = 2) +#define PC14_AFx_UART3CTS() (CW_GPIOC->AFRH_f.PIN14 = 3) +#define PC14_AFx_I2C1SDA() (CW_GPIOC->AFRH_f.PIN14 = 4) +#define PC14_AFx_BTIM2TOGN() (CW_GPIOC->AFRH_f.PIN14 = 5) +#define PC14_AFx_ATIMCH6() (CW_GPIOC->AFRH_f.PIN14 = 6) +#define PC14_AFx_ATIMCH5N() (CW_GPIOC->AFRH_f.PIN14 = 7) +#define PC14_AFx_SPI3MISO() (CW_GPIOC->AFRH_f.PIN14 = 8) +#define PC14_AFx_GTIM4CH1() (CW_GPIOC->AFRH_f.PIN14 = 9) +#define PC15_AFx_GPIO() (CW_GPIOC->AFRH_f.PIN15 = 0) +#define PC15_AFx_UART1TXD() (CW_GPIOC->AFRH_f.PIN15 = 1) +#define PC15_AFx_UART2TXD() (CW_GPIOC->AFRH_f.PIN15 = 2) +#define PC15_AFx_UART3RTS() (CW_GPIOC->AFRH_f.PIN15 = 3) +#define PC15_AFx_I2C1SCL() (CW_GPIOC->AFRH_f.PIN15 = 4) +#define PC15_AFx_BTIM2TOGP() (CW_GPIOC->AFRH_f.PIN15 = 5) +#define PC15_AFx_ATIMCH6N() (CW_GPIOC->AFRH_f.PIN15 = 6) +#define PC15_AFx_ATIMCH5() (CW_GPIOC->AFRH_f.PIN15 = 7) +#define PC15_AFx_SPI3MOSI() (CW_GPIOC->AFRH_f.PIN15 = 8) +#define PC15_AFx_GTIM4CH2() (CW_GPIOC->AFRH_f.PIN15 = 9) + +//============================================================ +// GPIOF +#define PF00_AFx_GPIO() (CW_GPIOF->AFRL_f.PIN0 = 0) +#define PF00_AFx_UART1RXD() (CW_GPIOF->AFRL_f.PIN0 = 1) +#define PF00_AFx_I2C1SDA() (CW_GPIOF->AFRL_f.PIN0 = 4) +#define PF00_AFx_BTIM1TOGN() (CW_GPIOF->AFRL_f.PIN0 = 5) +#define PF00_AFx_GTIM1TRGO() (CW_GPIOF->AFRL_f.PIN0 = 6) +#define PF00_AFx_ATIMCH6N() (CW_GPIOF->AFRL_f.PIN0 = 7) +#define PF00_AFx_SPI3SCK() (CW_GPIOF->AFRL_f.PIN0 = 8) +#define PF00_AFx_GTIM4CH3() (CW_GPIOF->AFRL_f.PIN0 = 9) +#define PF01_AFx_GPIO() (CW_GPIOF->AFRL_f.PIN1 = 0) +#define PF01_AFx_UART1TXD() (CW_GPIOF->AFRL_f.PIN1 = 1) +#define PF01_AFx_HEXEN() (CW_GPIOF->AFRL_f.PIN1 = 2) +#define PF01_AFx_LSEOUT() (CW_GPIOF->AFRL_f.PIN1 = 3) +#define PF01_AFx_I2C1SCL() (CW_GPIOF->AFRL_f.PIN1 = 4) +#define PF01_AFx_BTIM1TOGP() (CW_GPIOF->AFRL_f.PIN1 = 5) +#define PF01_AFx_GTIM2TRGO() (CW_GPIOF->AFRL_f.PIN1 = 6) +#define PF01_AFx_ATIMCH6() (CW_GPIOF->AFRL_f.PIN1 = 7) +#define PF01_AFx_SPI3NCS() (CW_GPIOF->AFRL_f.PIN1 = 8) +#define PF01_AFx_GTIM4CH4() (CW_GPIOF->AFRL_f.PIN1 = 9) +#define PF03_AFx_GPIO() (CW_GPIOF->AFRL_f.PIN3 = 0) +#define PF03_AFx_LSEOUT() (CW_GPIOF->AFRL_f.PIN3 = 1) +#define PF03_AFx_LSIOUT() (CW_GPIOF->AFRL_f.PIN3 = 2) +#define PF03_AFx_ADC1SAM() (CW_GPIOF->AFRL_f.PIN3 = 3) +#define PF03_AFx_LVDOUT() (CW_GPIOF->AFRL_f.PIN3 = 4) +#define PF03_AFx_HCLKOUT() (CW_GPIOF->AFRL_f.PIN3 = 5) +#define PF03_AFx_ATIMTRGO() (CW_GPIOF->AFRL_f.PIN3 = 6) +#define PF03_AFx_IROUT() (CW_GPIOF->AFRL_f.PIN3 = 7) +#define PF03_AFx_GTIM3TRGO() (CW_GPIOF->AFRL_f.PIN3 = 8) +#define PF03_AFx_GTIM4TRGO() (CW_GPIOF->AFRL_f.PIN3 = 9) +#define PF06_AFx_GPIO() (CW_GPIOF->AFRL_f.PIN6 = 0) +#define PF06_AFx_UART1CTS() (CW_GPIOF->AFRL_f.PIN6 = 1) +#define PF06_AFx_UART3RXD() (CW_GPIOF->AFRL_f.PIN6 = 2) +#define PF06_AFx_UART2CTS() (CW_GPIOF->AFRL_f.PIN6 = 3) +#define PF06_AFx_I2C1SCL() (CW_GPIOF->AFRL_f.PIN6 = 4) +#define PF06_AFx_BTIM3TOGN() (CW_GPIOF->AFRL_f.PIN6 = 5) +#define PF06_AFx_GTIM2TRGO() (CW_GPIOF->AFRL_f.PIN6 = 6) +#define PF06_AFx_ATIMCH5() (CW_GPIOF->AFRL_f.PIN6 = 7) +#define PF06_AFx_I2C2SCL() (CW_GPIOF->AFRL_f.PIN6 = 8) +#define PF06_AFx_GTIM4TRGO() (CW_GPIOF->AFRL_f.PIN6 = 9) +#define PF07_AFx_GPIO() (CW_GPIOF->AFRL_f.PIN7 = 0) +#define PF07_AFx_UART1RTS() (CW_GPIOF->AFRL_f.PIN7 = 1) +#define PF07_AFx_UART3TXD() (CW_GPIOF->AFRL_f.PIN7 = 2) +#define PF07_AFx_UART2RTS() (CW_GPIOF->AFRL_f.PIN7 = 3) +#define PF07_AFx_I2C1SDA() (CW_GPIOF->AFRL_f.PIN7 = 4) +#define PF07_AFx_BTIM3TOGP() (CW_GPIOF->AFRL_f.PIN7 = 5) +#define PF07_AFx_GTIM1TRGO() (CW_GPIOF->AFRL_f.PIN7 = 6) +#define PF07_AFx_ATIMCH5N() (CW_GPIOF->AFRL_f.PIN7 = 7) +#define PF07_AFx_I2C2SDA() (CW_GPIOF->AFRL_f.PIN7 = 8) +#define PF07_AFx_SPI2NCS() (CW_GPIOF->AFRL_f.PIN7 = 9) + + +//============================================================ + +void GPIO_SWD2GPIO(void); +void GPIO_GPIO2SWD(void); +void GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pins); +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void GPIO_ConfigFilter(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pins, uint32_t FltClk); +void GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pins, GPIO_PinState PinState); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t Value); +void GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pins); +GPIO_PinState GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_SetAlternateFunction(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint16_t GPIO_AFx); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_gtim.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_gtim.h new file mode 100644 index 0000000..242bcfa --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_gtim.h @@ -0,0 +1,367 @@ +/** + * @file cw32l012_gtim.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_GTIM_H +#define __CW32L012_GTIM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "system_cw32l012.h" + + +/****************************************************************************** + * type definitions ('typedef') + ******************************************************************************/ + +/** + * @brief GTIM 基础初始化参数 + */ +typedef struct +{ + uint32_t ARRBuffState; /*!< GTIM ARR 缓存是能控制 */ + uint32_t AlignMode; /*!< GTIM的模式选择。 */ + uint32_t Direction; /*!< GTIM的计数方向，中心对其模式下无效 */ + uint32_t PulseMode; /*!< GTIM的单次/连续计数模式选择。 */ + uint32_t EventOption; /*!< GTIM的事件源选择 */ + uint32_t UpdateOption; /*!< GTIM更新使能选择 */ + uint32_t Prescaler; /*!< GTIM的预分频系数。 */ + uint32_t ReloadValue; /*!< GTIM的重载值。 */ +} GTIM_InitTypeDef; + + +typedef struct +{ + uint32_t SlaverMode; /*!< 从模式选择 */ + uint32_t TrigInput; /*!< 触发信号源选择 */ + uint32_t PreloadSource; /*!< 预加载源选择 */ + uint32_t PreloadState; /*!< 预加载使能 */ +}GTIM_SlaverCfgTypeDef; + +typedef struct +{ + FunctionalState FastMode; /* 输出比较快速模式使能 */ + FunctionalState PreloadState; /* 输出比较预装载使能 */ + uint32_t OCMode; /* 输出比较模式 */ + uint32_t OCPolarity; /* 比较输出极性 */ +}GTIM_OCModeCfgTypeDef; + + +typedef struct +{ + uint32_t ICMap; /* IC映射 */ + + uint32_t ICPrescaler; /* 输入捕获预分配 */ + + uint32_t ICFilter; /*!< 输入滤波配置 */ + + uint32_t ICPolarity; /*!< 输入捕获极性：上升、下降、双沿 */ +}GTIM_ICModeCfgTypeDef; + +/****************************************************************************** + * pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_GTIM_DEFINE(GTIMx) ((GTIMx) == CW_GTIM1 || (GTIMx) == CW_GTIM2 || \ + (GTIMx) == CW_GTIM3 || (GTIMx) == CW_GTIM4) + +#define GTIM_ARR_BUFF_EN (1UL << GTIMx_CR1_ARPE_Pos) +#define GTIM_ARR_BUFF_DIS (0UL) +#define IS_GTIM_ARR_BUFF(STATE) (((STATE) == GTIM_ARR_BUFF_EN) ||\ + ((STATE) == GTIM_ARR_BUFF_DIS)) + +#define GTIM_ALIGN_MODE_EDGE (0UL) +#define GTIM_ALIGN_MODE_CENTER_DOWN (1UL << GTIMx_CR1_CMS_Pos) +#define GTIM_ALIGN_MODE_CENTER_UP (2UL << GTIMx_CR1_CMS_Pos) +#define GTIM_ALIGN_MODE_CENTER_BOTH (3UL << GTIMx_CR1_CMS_Pos) +#define IS_GTIM_ALIGN_MODE(MODE) (((MODE) == GTIM_ALIGN_MODE_EDGE) ||\ + ((MODE) == GTIM_ALIGN_MODE_CENTER_DOWN) ||\ + ((MODE) == GTIM_ALIGN_MODE_CENTER_UP) ||\ + ((MODE) == GTIM_ALIGN_MODE_CENTER_BOTH)) + +#define GTIM_DIRECTION_UP (0U) +#define GTIM_DIRECTION_DOWN (1UL << GTIMx_CR1_DIR_Pos) +#define IS_GTIM_DIRECTION(DIR) (((DIR) == GTIM_DIRECTION_UP) ||\ + ((DIR) == GTIM_DIRECTION_DOWN)) + +#define GTIM_PULSE_MODE_EN (1UL << GTIMx_CR1_OPM_Pos) +#define GTIM_PULSE_MODE_DIS (0UL) +#define IS_GTIM_PULSE_MODE(MODE) (((MODE) == GTIM_PULSE_MODE_EN) ||\ + ((MODE) == GTIM_PULSE_MODE_DIS)) + +#define GTIM_EVENT_EXTENSION (0U) +#define GTIM_EVENT_NORMAL (1UL << GTIMx_CR1_URS_Pos) +#define IS_GTIM_EVENT_OPT(OPT) (((OPT) == GTIM_EVENT_NORMAL) ||\ + ((OPT) == GTIM_EVENT_EXTENSION)) + +#define GTIM_UPDATE_EN (0U) +#define GTIM_UPDATE_DIS (1UL << GTIMx_CR1_UDIS_Pos) +#define IS_GTIM_UPDATE_OPT(OPT) (((OPT) == GTIM_UPDATE_EN) ||\ + ((OPT) == GTIM_UPDATE_DIS)) + +#define GTIM_MASTER_TRGO_RESET (0UL) +#define GTIM_MASTER_TRGO_EN (1UL) +#define GTIM_MASTER_TRGO_UPDATE (2UL) +#define GTIM_MASTER_TRGO_CCH1 (3UL) +#define GTIM_MASTER_TRGO_CCH2 (4UL) +#define GTIM_MASTER_TRGO_CCH3 (5UL) +#define GTIM_MASTER_TRGO_CCH4 (6UL) +#define GTIM_MASTER_TRGO_OC1REF (7UL) +#define GTIM_MASTER_TRGO_OC2REF (8UL) +#define GTIM_MASTER_TRGO_OC3REF (9UL) +#define GTIM_MASTER_TRGO_OC4REF (10UL) +#define GTIM_MASTER_TRGO_OC1REFC (11UL) +#define GTIM_MASTER_TRGO_OC2REFC (12UL) +#define GTIM_MASTER_TRGO_OC3REFC (13UL) +#define GTIM_MASTER_TRGO_OC4REFC (14UL) +#define GTIM_MASTER_TRGO_ENCODE (15UL) + +#define GTIM_SLAVER_MODE_RESET (4UL) +#define GTIM_SLAVER_MODE_GATE (5UL) +#define GTIM_SLAVER_MODE_TRIGGER (6UL) +#define GTIM_SLAVER_MODE_EXTENAL (7UL) +#define GTIM_SLAVER_MODE_GROUP_RST_TRIG (8UL) +#define GTIM_SLAVER_MODE_GROUP_GATE_RST (9UL) +#define IS_GTIM_SLAVER_MODE(MODE) (((MODE) == GTIM_SLAVER_MODE_RESET) ||\ + ((MODE) == GTIM_SLAVER_MODE_GATE) ||\ + ((MODE) == GTIM_SLAVER_MODE_TRIGGER) ||\ + ((MODE) == GTIM_SLAVER_MODE_EXTENAL) ||\ + ((MODE) == GTIM_SLAVER_MODE_GROUP_RST_TRIG) ||\ + ((MODE) == GTIM_SLAVER_MODE_GROUP_GATE_RST)) + +#define GTIM_TRIG_INPUT_ITR0 (0U) +#define GTIM_TRIG_INPUT_ITR1 (1U) +#define GTIM_TRIG_INPUT_ITR2 (2U) +#define GTIM_TRIG_INPUT_ITR3 (3U) +#define GTIM_TRIG_INPUT_TI1F_ED (4U) +#define GTIM_TRIG_INPUT_TI1FP1 (5U) +#define GTIM_TRIG_INPUT_TI1FP2 (6U) +#define GTIM_TRIG_INPUT_ETRF (7U) +#define GTIM_TRIG_INPUT_ITR4 (8U) +#define GTIM_TRIG_INPUT_ITR5 (9U) +#define GTIM_TRIG_INPUT_ITR6 (10U) +#define GTIM_TRIG_INPUT_ITR7 (11U) +#define GTIM_TRIG_INPUT_ITR8 (12U) +#define GTIM_TRIG_INPUT_ITR9 (13U) +#define GTIM_TRIG_INPUT_ITR10 (14U) +#define GTIM_TRIG_INPUT_ITR11 (15U) +#define GTIM_TRIG_INPUT_ITR12 (16U) +#define IS_GTIM_TRIG_INPUT(INPUT) (INPUT <= 16) + + +#define GTIM_PRELOAD_SOURCE_EVENT 0 +#define GTIM_PRELOAD_SOURCE_INDEX 1 +#define IS_GTIM_PRELOAD_SOURCE(SOURCE) (((SOURCE) == GTIM_PRELOAD_SOURCE_EVENT) ||\ + ((SOURCE) == GTIM_PRELOAD_SOURCE_INDEX)) + +#define GTIM_PRELOAD_EN 1 +#define GTIM_PRELOAD_DIS 0 + + +#define GTIM_OC_MODE_FROZEN 0u +#define GTIM_OC_MODE_ACTIVE 1u +#define GTIM_OC_MODE_INACTIVE 2u +#define GTIM_OC_MODE_TOGGLE 3u +#define GTIM_OC_MODE_FORCE_LOW 4u +#define GTIM_OC_MODE_FORCE_HIGH 5u +#define GTIM_OC_MODE_PWM1 6u +#define GTIM_OC_MODE_PWM2 7u +#define GTIM_OC_MODE_OPM1 8u +#define GTIM_OC_MODE_OPM2 9u +#define GTIM_OC_MODE_DIRECTION 11u +#define GTIM_OC_MODE_GROUP_PWM1_OCREF 12u +#define GTIM_OC_MODE_GROUP_PWM2_OCREF 13u +#define GTIM_OC_MODE_PWM_ASYM1 14u +#define GTIM_OC_MODE_PWM_ASYM2 15u +#define IS_GTIM_OC_MODE(MODE) (((MODE) <= 15) && ((MODE) != 10)) + +#define GTIM_OC_POLAR_INVERT 1 +#define GTIM_OC_POLAR_NONINVERT 0 +#define IS_GTIM_OC_POLAR(POLAR) (((POLAR) == GTIM_OC_POLAR_INVERT) ||\ + ((POLAR) == GTIM_OC_POLAR_NONINVERT)) + +#define GTIM_IC1_MAP_TI1 (0x01U) +#define GTIM_IC1_MAP_TI2 (0x02U) +#define GTIM_IC2_MAP_TI2 (0x01U) +#define GTIM_IC2_MAP_TI1 (0x02U) +#define GTIM_IC_MAP_TRC (0x03U) + +#define GTIM_IC3_MAP_TI3 (0x01U) +#define GTIM_IC3_MAP_TI4 (0x02U) +#define GTIM_IC4_MAP_TI4 (0x01U) +#define GTIM_IC4_MAP_TI3 (0x02U) +#define GTIM_IC_MAP_TRC (0x03U) +#define IS_GTIM_IC_MAP(INSTANCE) (((INSTANCE) <= 3) && ((INSTANCE) != 0)) + +#define GTIM_IC_PRESCALER_DIV1 0u +#define GTIM_IC_PRESCALER_DIV2 1u +#define GTIM_IC_PRESCALER_DIV4 2u +#define GTIM_IC_PRESCALER_DIV8 3u +#define IS_GTIM_IC_PRESCALER(SCALER) ((SCALER) < 4) + +#define GTIM_IC_FILTER_PCLK_NONE (0u) +#define GTIM_IC_FILTER_PCLK_N2 (1u) +#define GTIM_IC_FILTER_PCLK_N4 (2u) +#define GTIM_IC_FILTER_PCLK_N8 (3u) +#define GTIM_IC_FILTER_FDTS_DIV2_N6 (4u) +#define GTIM_IC_FILTER_FDTS_DIV2_N8 (5u) +#define GTIM_IC_FILTER_FDTS_DIV4_N6 (6u) +#define GTIM_IC_FILTER_FDTS_DIV4_N8 (7u) +#define GTIM_IC_FILTER_FDTS_DIV8_N6 (8u) +#define GTIM_IC_FILTER_FDTS_DIV8_N8 (9u) +#define GTIM_IC_FILTER_FDTS_DIV16_N5 (10u) +#define GTIM_IC_FILTER_FDTS_DIV16_N6 (11u) +#define GTIM_IC_FILTER_FDTS_DIV16_N8 (12u) +#define GTIM_IC_FILTER_FDTS_DIV32_N5 (13u) +#define GTIM_IC_FILTER_FDTS_DIV32_N6 (14u) +#define GTIM_IC_FILTER_FDTS_DIV32_N8 (15u) +#define IS_GTIM_IC_FILTER(FILTER) (FILTER <=15) + +#define GTIM_ICPolarity_Rising (1UL) +#define GTIM_ICPolarity_Falling (2UL) +#define GTIM_ICPolarity_BothEdge (3UL) +#define IS_GTIM_ICPolarity(MODE) (((MODE) == GTIM_ICPolarity_Rising) || \ + ((MODE) == GTIM_ICPolarity_Falling) || \ + ((MODE) == GTIM_ICPolarity_BothEdge)) + + + + + +#define GTIM_PRESCALER_DIV1 (0UL) +#define GTIM_PRESCALER_DIV2 (1UL) +#define GTIM_PRESCALER_DIV4 (3UL) +#define GTIM_PRESCALER_DIV8 (7UL) +#define GTIM_PRESCALER_DIV16 (15UL) +#define GTIM_PRESCALER_DIV32 (31UL) +#define GTIM_PRESCALER_DIV64 (63UL) +#define GTIM_PRESCALER_DIV128 (127UL) +#define GTIM_PRESCALER_DIV256 (255UL) +#define GTIM_PRESCALER_DIV512 (511UL) +#define GTIM_PRESCALER_DIV1024 (1023UL) +#define GTIM_PRESCALER_DIV2048 (2047UL) +#define GTIM_PRESCALER_DIV4096 (4095UL) +#define GTIM_PRESCALER_DIV8192 (8191UL) +#define GTIM_PRESCALER_DIV16384 (16383UL) +#define GTIM_PRESCALER_DIV32768 (32767UL) + +#define IS_GTIM_PRESCALER(DIV) ((DIV) <= 0xFFFF) + +#define GTIM_IT_UPDATA (1UL << GTIMx_IER_UIE_Pos) +#define GTIM_IT_CC1 (1UL << GTIMx_IER_CC1IE_Pos) +#define GTIM_IT_CC2 (1UL << GTIMx_IER_CC2IE_Pos) +#define GTIM_IT_CC3 (1UL << GTIMx_IER_CC3IE_Pos) +#define GTIM_IT_CC4 (1UL << GTIMx_IER_CC4IE_Pos) +#define GTIM_IT_TI (1UL << GTIMx_IER_TIE_Pos) +#define GTIM_IT_IDX (1UL << GTIMx_IER_IDXIE_Pos) +#define GTIM_IT_DIR (1UL << GTIMx_IER_DIRIE_Pos) +#define GTIM_IT_IERR (1UL << GTIMx_IER_IERRIE_Pos) +#define GTIM_IT_TERR (1UL << GTIMx_IER_TERRIE_Pos) +#define IS_GTIM_IT(IT) ((((IT) & 0xFF0FFFA0) == 0x0UL) && ((IT) != 0x0UL)) +#define IS_GTIM_GET_IT(IT) (((IT) == GTIM_IT_UPDATA) ||\ + ((IT) == GTIM_IT_CC1) ||\ + ((IT) == GTIM_IT_CC2) ||\ + ((IT) == GTIM_IT_CC3) ||\ + ((IT) == GTIM_IT_CC4) ||\ + ((IT) == GTIM_IT_TI) ||\ + ((IT) == GTIM_IT_IDX) ||\ + ((IT) == GTIM_IT_DIR) ||\ + ((IT) == GTIM_IT_IERR) ||\ + ((IT) == GTIM_IT_TERR)) + +/****************************************************************************** +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ + + +/****************************************************************************** +* Global function prototypes +******************************************************************************/ +void GTIM1_DeInit(void); +void GTIM2_DeInit(void); +void GTIM3_DeInit(void); +void GTIM4_DeInit(void); +void GTIM_TimeBaseInit(GTIM_TypeDef* GTIMx, GTIM_InitTypeDef *GTIM_InitStruct); + +void GTIM_MasterTRGOCfg(GTIM_TypeDef *GTIMx,uint32_t MasterTRGO); +void GTIM_SlaverModeCfg(GTIM_TypeDef *GTIMx, GTIM_SlaverCfgTypeDef *GTIM_SlaverCfgStruct); + +void GTIM_OC1ModeCfg(GTIM_TypeDef *GTIMx, GTIM_OCModeCfgTypeDef *GTIM_OCModeCfgStruct); +void GTIM_OC2ModeCfg(GTIM_TypeDef *GTIMx, GTIM_OCModeCfgTypeDef *GTIM_OCModeCfgStruct); +void GTIM_OC3ModeCfg(GTIM_TypeDef *GTIMx, GTIM_OCModeCfgTypeDef *GTIM_OCModeCfgStruct); +void GTIM_OC4ModeCfg(GTIM_TypeDef *GTIMx, GTIM_OCModeCfgTypeDef *GTIM_OCModeCfgStruct); + +void GTIM_OC1Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState); +void GTIM_OC2Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState); +void GTIM_OC3Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState); +void GTIM_OC4Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState); + +void GTIM_IC1ModeCfg(GTIM_TypeDef* GTIMx, GTIM_ICModeCfgTypeDef *GTIM_ICInitStruct); +void GTIM_IC2ModeCfg(GTIM_TypeDef* GTIMx, GTIM_ICModeCfgTypeDef *GTIM_ICInitStruct); +void GTIM_IC3ModeCfg(GTIM_TypeDef* GTIMx, GTIM_ICModeCfgTypeDef *GTIM_ICInitStruct); +void GTIM_IC4ModeCfg(GTIM_TypeDef* GTIMx, GTIM_ICModeCfgTypeDef *GTIM_ICInitStruct); + +void GTIM_IC1Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState); +void GTIM_IC2Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState); +void GTIM_IC3Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState); +void GTIM_IC4Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState); + +void GTIM_Cmd(GTIM_TypeDef* GTIMx, FunctionalState NewState); + +void GTIM_RemapUpdateFlag(GTIM_TypeDef *GTIMx,FunctionalState NewState); +void GTIM_SetPrescaler(GTIM_TypeDef* GTIMx, uint16_t GTIMPrescaler); +void GTIM_SetReloadValue(GTIM_TypeDef* GTIMx, uint16_t ReloadValue); +void GTIM_SetCounterValue(GTIM_TypeDef* GTIMx, uint16_t Value); + +void GTIM_SetCompare1(GTIM_TypeDef* GTIMx, uint16_t Value); +void GTIM_SetCompare2(GTIM_TypeDef* GTIMx, uint16_t Value); +void GTIM_SetCompare3(GTIM_TypeDef* GTIMx, uint16_t Value); +void GTIM_SetCompare4(GTIM_TypeDef* GTIMx, uint16_t Value); +uint16_t GTIM_GetCapture1(GTIM_TypeDef* GTIMx); +uint16_t GTIM_GetCapture2(GTIM_TypeDef* GTIMx); +uint16_t GTIM_GetCapture3(GTIM_TypeDef* GTIMx); +uint16_t GTIM_GetCapture4(GTIM_TypeDef* GTIMx); + +void GTIM_ITConfig(GTIM_TypeDef* GTIMx, uint32_t GTIM_IT, FunctionalState NewState); +ITStatus GTIM_GetITStatus(GTIM_TypeDef* GTIMx, uint32_t GTIM_IT); +void GTIM_ClearITPendingBit(GTIM_TypeDef* GTIMx, uint32_t GTIM_IT); + + + +void GTIM_ETRConfig(GTIM_TypeDef* GTIMx, uint32_t ETRPolarity, uint32_t ETRFilter); +void GTIM_ICChannelConfig(GTIM_TypeDef* GTIMx, uint32_t CHx, uint32_t CHxFilter,uint32_t CHxInvert); + + +void GTIM1_ITRConfig(uint32_t ITRSouce); + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32L012_GTIM_H */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_halltim.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_halltim.h new file mode 100644 index 0000000..bfea14e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_halltim.h @@ -0,0 +1,133 @@ +/** + * @file cw32l012_halltim.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_HALLTIM_H__ +#define __CW32L012_HALLTIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "cw32l012.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +// HALLTIM_CR 控制寄存器位域定义 +typedef enum { + HALLTIM_CR_SOFTTRIG = 0x00800000, // 软件触发信号生成控制 + HALLTIM_CR_FLT2LEN = 0x00FF0000, // 滤波宽度配置掩码 + HALLTIM_CR_MMS = 0x00000700, // 触发输出选择掩码 + HALLTIM_CR_DIV = 0x000000C0, // HALL模块计数时钟来源分频配置掩码 + HALLTIM_CR_FLT1EN = 0x00000004, // 7/5滤波器使能控制 + HALLTIM_CR_EN = 0x00000001 // HALL模块使能控制 +} HALLTIM_CR_BitField; + +// HALLTIM_DIER DMA、中断使能控制寄存器位域定义 +typedef enum { + HALLTIM_DIER_SOFTDMA = 0x00000080, // 软件触发DMA使能控制 + HALLTIM_DIER_MATCHDMA = 0x00000040, // 计数器匹配DMA使能控制 + HALLTIM_DIER_OVDMA = 0x00000020, // 计数器溢出DMA使能控制 + HALLTIM_DIER_CHGDMA = 0x00000010, // HALL信号DMA中断使能控制 + HALLTIM_DIER_MATCH = 0x00000004, // 计数器匹配中断使能控制 + HALLTIM_DIER_OV = 0x00000002, // 计数器溢出中断使能控制 + HALLTIM_DIER_CHG = 0x00000001 // HALL信号变化中断使能控制 +} HALLTIM_DIER_BitField; + +// HALLTIM_ISR 中断标志寄存器位域定义 +typedef enum { + HALLTIM_ISR_MATCH = 0x00000004, // 匹配标志 + HALLTIM_ISR_OV = 0x00000002, // 溢出标志 + HALLTIM_ISR_CHG = 0x00000001 // HALL信号变化标志 +} HALLTIM_ISR_BitField; + +// HALLTIM_ICR 中断标志清除寄存器位域定义 +typedef enum { + HALLTIM_ICR_MATCH = 0x00000004, // 匹配标志清除 + HALLTIM_ICR_OV = 0x00000002, // 溢出标志清除 + HALLTIM_ICR_CHG = 0x00000001 // HALL信号变化标志清除 +} HALLTIM_ICR_BitField; + +// HALLTIM_MMS 触发输出选择枚举 +typedef enum { + HALLTIM_MMS_OV = 0x00000000, // OV，溢出脉冲 + HALLTIM_MMS_PWM = 0x0000010, // PWM，PWM信号 + HALLTIM_MMS_MATCH = 0x0000020, // MATCH，CCR匹配脉冲 + HALLTIM_MMS_CHANGE = 0x0000030, // CHANGE，HALL信号变化脉冲 + HALLTIM_MMS_CH3FLT = 0x0000040, // CH3FLT，滤波后的CH3波形 + HALLTIM_MMS_CH2FLT = 0x0000050, // CH2FLT，滤波后的CH2波形 + HALLTIM_MMS_CH1FLT = 0x0000060, // CH1FLT，滤波后的CH1波形 + HALLTIM_MMS_CHXOR = 0x0000070 // CHXOR，3通道滤波后的信号异或 +} HALLTIM_MMS; + +// HALLTIM_DIV HALL模块计数时钟来源分频配置枚举 +typedef enum { + HALLTIM_DIV_PCLK = 0x00000000, // PCLK + HALLTIM_DIV_PCLK_DIV2 = 0x0000004, // PCLK/2 + HALLTIM_DIV_PCLK_DIV4 = 0x0000008, // PCLK/4 + HALLTIM_DIV_PCLK_DIV8 = 0x000000C // PCLK/8 +} HALLTIM_DIV; + +// 初始化配置结构体 +typedef struct { + boolean_t filter_enable; // 是否启用7/5滤波器 + uint8_t filter_length; // 滤波器长度（0-0x7FFF） + HALLTIM_DIV clock_division; // 时钟分频（0: PCLK, 0x4: PCLK/2, 0x8: PCLK/4, 0xc: PCLK/8） + HALLTIM_MMS trigger_output; // 触发输出模式（0: OV, 0x10: PWM, 0x20: MATCH, 0x30: CHANGE, + // 0x40: CH3FLT, 0x50: CH2FLT, 0x60: CH1FLT, 0x70: CHXOR） + uint32_t auto_reload_value; // 自动重装载值 +} HALLTIM_InitTypeDef; + +// 驱动库函数声明 +void HALLTIM_Init(HALLTIM_InitTypeDef *HALLTIM_InitStruct); +void HALLTIM_Cmd(FunctionalState state); +void HALLTIM_SetFilterLength(uint32_t length); +void HALLTIM_SetMode(HALLTIM_MMS mode); +void HALLTIM_SetClockDivider(HALLTIM_DIV div); +void HALLTIM_GenerateSoftTrigger(void); +void HALLTIM_SetAutoReloadValue(uint32_t value); +uint32_t HALLTIM_GetCounterValue(void); +uint32_t HALLTIM_GetPulseWidth(void); +void HALLTIM_SetCompareValue(uint32_t value); +uint32_t HALLTIM_GetStatus(void); +void HALLTIM_ClearStatus(uint32_t flags); +uint32_t HALLTIM_GetRawStateCH1(void); +uint32_t HALLTIM_GetRawStateCH2(void); +uint32_t HALLTIM_GetRawStateCH3(void); +uint32_t HALLTIM_GetFilteredStateCH1(void); +uint32_t HALLTIM_GetFilteredStateCH2(void); +uint32_t HALLTIM_GetFilteredStateCH3(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_irmod.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_irmod.h new file mode 100644 index 0000000..957e882 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_irmod.h @@ -0,0 +1,162 @@ +/** + * @file cw32l012_irmod.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + ****************************************************************************** + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_IRMOD_H +#define __CW32L012_IRMOD_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "cw32l012.h" + +/** @addtogroup IRMOD + * @{ + */ + + +/******************************************************************************/ +/* Global enum type definitions */ +/******************************************************************************/ +/** @defgroup IRMOD枚举类型定义 + * @{ + */ + +/** + * @brief 红外调制方式配置 + */ +typedef enum +{ + IRMOD_IRSW_AND_GTIM1_CH1 = 0x0, // IRSW & GTIM1_CH1 + IRMOD_IRSW_OR_GTIM2_CH1 = 0x1, // IRSW | GTIM2_CH1 + IRMOD_GTIM1_CH1_AND_GTIM3_CH1 = 0x2, // GTIM1_CH1 & GTIM3_CH1 + IRMOD_GTIM2_CH1_OR_GTIM4_CH1 = 0x3, // GTIM2_CH1 | GTIM4_CH1 + IRMOD_UART1_TXD_AND_GTIM1_CH2 = 0x4, // UART1_TXD & GTIM1_CH2 + IRMOD_UART1_TXD_OR_GTIM2_CH2 = 0x5, // UART1_TXD | GTIM2_CH2 + IRMOD_UART1_TXD_AND_GTIM3_CH2 = 0x6, // UART1_TXD & GTIM3_CH2 + IRMOD_UART1_TXD_OR_GTIM4_CH2 = 0x7, // UART1_TXD | GTIM4_CH2 + IRMOD_UART2_TXD_AND_GTIM1_CH3 = 0x8, // UART2_TXD & GTIM1_CH3 + IRMOD_UART2_TXD_OR_GTIM2_CH3 = 0x9, // UART2_TXD | GTIM2_CH3 + IRMOD_UART2_TXD_AND_GTIM3_CH3 = 0xA, // UART2_TXD & GTIM3_CH3 + IRMOD_UART2_TXD_OR_GTIM4_CH3 = 0xB, // UART2_TXD | GTIM4_CH3 + IRMOD_UART3_TXD_AND_GTIM1_CH4 = 0xC, // UART3_TXD & GTIM1_CH4 + IRMOD_UART3_TXD_OR_GTIM2_CH4 = 0xD, // UART3_TXD | GTIM2_CH4 + IRMOD_UART3_TXD_AND_GTIM3_CH4 = 0xE, // UART3_TXD & GTIM3_CH4 + IRMOD_UART3_TXD_OR_GTIM4_CH4 = 0xF // UART3_TXD | GTIM4_CH4 +}IRMOD_ModulateModTypeDef; + +/** + * @brief IR输出极性配置 + */ +typedef enum +{ + IRMOD_POLARITY_POSITIVE = (0x0UL << IRMOD_CR_INV_Pos),/*!< 正向输出 */ + IRMOD_POLARITY_NEGATIVE = (0x1UL << IRMOD_CR_INV_Pos) /*!< 反向输入 */ +} IRMOD_PolarityTypeDef; + +/** + * @} + */ + + +/******************************************************************************/ +/* Global struct type definitions */ +/******************************************************************************/ + + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + + +/******************************************************************************/ +/* Global macro function */ +/******************************************************************************/ +/** @defgroup IRMOD宏函数定义 + * @{ + */ + +/** + * @brief 置位 IRMOD_CR 寄存器的红外调制软件控制(IRSW)位 + * @param None + * @retval None + */ +#define IRMOD_IRSW_SETHIGH() (CW_IRMOD->CR |= IRMOD_CR_IRSW_Msk) + +/** + * @brief 重置 IRMOD_CR 寄存器的红外调制软件控制(IRSW)位 + * @param None + * @retval None + */ +#define IRMOD_IRSW_SETLOW() (CW_IRMOD->CR &= ~(IRMOD_CR_IRSW_Msk)) + +/** + * @} + */ + + +/******************************************************************************/ +/* Exported variables ('extern', definition in C source) */ +/******************************************************************************/ + + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ +/** @defgroup IRMOD驱动函数原型 + * @{ + */ + +void IRMOD_Config(IRMOD_ModulateModTypeDef ModulateMod, IRMOD_PolarityTypeDef Polarity); +void IRMOD_IRSW_SetHigh(void); +void IRMOD_IRSW_SetLow(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __SYM32L010_HAL_IRMOD_H */ + + +/************************ (C) COPYRIGHT SIYIMicro *****END OF FILE*************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_iwdt.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_iwdt.h new file mode 100644 index 0000000..337badf --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_iwdt.h @@ -0,0 +1,137 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_IWDT_H +#define __CW32L012_IWDT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012.h" +#include "system_cw32l012.h" +/****************************************************************************** + * type definitions ('typedef') + ******************************************************************************/ +typedef struct +{ + uint32_t IWDT_Prescaler; /* 预分配系数，取值范围2的n次幂，n=2,3..9 */ + + uint32_t IWDT_OverFlowAction; /* 溢出后的动作 */ + + FunctionalState IWDT_ITState; /* 看门狗中断状态，取值范围ENABLE或DISABLE */ + + uint32_t IWDT_Pause; /* Deepsleep模式下IWDT暂停控制 */ + + uint32_t IWDT_ReloadValue; /* 看门狗重载值，取值范围小于等于0x0FFF */ + + uint32_t IWDT_WindowValue; /* 窗口比较器比较值,取值范围小于等于0x0FFF */ +} IWDT_InitTypeDef; +/****************************************************************************** + * pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IWDT_FREQ 10000UL + +#define IWDT_Prescaler_DIV4 ((uint32_t)0x00000000) +#define IWDT_Prescaler_DIV8 ((uint32_t)0x00000001) +#define IWDT_Prescaler_DIV16 ((uint32_t)0x00000002) +#define IWDT_Prescaler_DIV32 ((uint32_t)0x00000003) +#define IWDT_Prescaler_DIV64 ((uint32_t)0x00000004) +#define IWDT_Prescaler_DIV128 ((uint32_t)0x00000005) +#define IWDT_Prescaler_DIV256 ((uint32_t)0x00000006) +#define IWDT_Prescaler_DIV512 ((uint32_t)0x00000007) +#define IS_IWDT_PRESCALER(PRESCALER) (((PRESCALER) == IWDT_Prescaler_DIV4) ||\ + ((PRESCALER) == IWDT_Prescaler_DIV8) ||\ + ((PRESCALER) == IWDT_Prescaler_DIV16) ||\ + ((PRESCALER) == IWDT_Prescaler_DIV32) ||\ + ((PRESCALER) == IWDT_Prescaler_DIV64) ||\ + ((PRESCALER) == IWDT_Prescaler_DIV128) ||\ + ((PRESCALER) == IWDT_Prescaler_DIV512)) +#define IS_IWDT_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF) +#define IS_IWDT_RELOAD(COUNTER) ((COUNTER) <= 0xFFF) + +#define IWDT_5_SECS (IWDT_4_SECS+IWDT_1_SECS+1) +#define IWDT_4_SECS 79 +#define IWDT_2_SECS 39 +#define IWDT_1_SECS 19 +#define IWDT_0_5_SECS 9 +#define IWDT_0_25_SECS 4 +#define IS_IWDT_PERIOD(PERIOD) ((PERIOD) == IWDT_2_SECS || (PERIOD) == IWDT_1_SECS ||\ + (PERIOD) == IWDT_0_5_SECS || (PERIOD) == IWDT_0_25_SECS) + +#define IWDT_UNLOCK_KEY 0x5555 +#define IWDT_LOCK_KEY 0x6666 +#define IWDT_RUN_KEY 0xCCCC +#define IWDT_REFRESH_KEY 0xAAAA +#define IWDT_STOP_KEY1 0x5A5A +#define IWDT_STOP_KEY2 0xA5A5 + +#define IWDT_OVERFLOW_ACTION_RESET 0 +#define IWDT_OVERFLOW_ACTION_INT IWDT_CR_ACTION_Msk +#define IS_IWDT_ACTION(ACTION) ((ACTION) == IWDT_OVERFLOW_ACTION_RESET || \ + (ACTION) == IWDT_OVERFLOW_ACTION_INT) +#define IWDT_SLEEP_PAUSE IWDT_CR_PAUSE_Msk +#define IWDT_SLEEP_CONTINUE 0 +#define IS_IWDT_SLEEP_MODE(MODE) ((MODE) == IWDT_SLEEP_PAUSE || \ + (MODE) == IWDT_SLEEP_CONTINUE) + +#define __IWDT_RUN() (CW_IWDT->KR = IWDT_RUN_KEY) +#define __IWDT_REFRESH() (CW_IWDT->KR = IWDT_REFRESH_KEY) +#define __IWDT_STOP() do{ \ + CW_IWDT->KR = IWDT_STOP_KEY1;\ + CW_IWDT->KR = IWDT_STOP_KEY2;\ + } while(0) +#define __IWDT_UNLOCK() (CW_IWDT->KR = IWDT_UNLOCK_KEY) +#define __IWDT_LOCK() (CW_IWDT->KR = IWDT_LOCK_KEY) + + +/****************************************************************************** +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ + + +/****************************************************************************** +* Global function prototypes +******************************************************************************/ +void IWDT_DeInit(void); +int IWDT_Init(IWDT_InitTypeDef *IWDT_InitStruct); + +void IWDT_Cmd(void); +void IWDT_Refresh(void); + +void IWDT_Unlock(void); +void IWDT_Lock(void); +void IWDT_Stop(void); + +int IWDT_SetPrescaler(uint32_t WWDT_Prescaler); +int IWDT_SetWindowValue(uint32_t WindowValue); +int IWDT_SetReloadValue(uint32_t ReloadValue); +int IWDT_ITConfig(FunctionalState NewState); +FlagStatus IWDT_GetFlagStatus(uint32_t StatusBit); +void IWDT_ClearOVFlag(void); +uint32_t IWDT_GetCounterValue(void); +void IWDT_SetPeriod(uint32_t period); + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32L012_IWDT_H */ +/** + * @} + */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_lpi2c.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_lpi2c.h new file mode 100644 index 0000000..255ed08 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_lpi2c.h @@ -0,0 +1,1230 @@ +/** + * @file cw32l012_lpi2c.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2022-7-12 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* + * + * 代码许可和免责信息 + * 武汉力源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉力源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉力源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + * + *******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012X_I2C_H +#define __CW32L012X_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012.h" + + +/* Private_TypesDefinitions --------------------------------------------------*/ +typedef int32_t status_t; + +/******************************************************************************/ +/* Global enum type definitions */ +/******************************************************************************/ +/** @defgroup I2C枚举类型定义 + * @{ + */ + +/** + * @brief I2C 主从模式 + */ +typedef enum +{ + I2C_ROLE_MASTER = 0, /*!< 主机模式 */ + I2C_ROLE_SLAVE /*!< 从机模式 */ +} I2C_RoleTypeDef; + +/** +* @brief I2C 从机地址模式 + */ +typedef enum +{ + I2C_ADDRESS_7BIT = 0, /*!< 7bit slaveAddr mode */ + I2C_ADDRESS_10BIT /*!< 10bit slaveAddr mode */ +} I2C_AddressTypeDef; + +/** + * @brief I2C 从机寄存器地址模式 + */ +typedef enum +{ + I2C_REG_ADDR_8BIT = 0, /*!< 8bit slave Register Address */ + I2C_REG_ADDR_16BIT, /*!< 16bit slave Register Address */ + I2C_REG_ADDR_24BIT, /*!< 24bit slave Register Address */ + I2C_REG_ADDR_32BIT /*!< 32bit slave Register Address */ +} I2C_SlaveRegAddrTypeDef; + +/** + * @brief I2C 读/写模式 + */ +typedef enum +{ + I2C_MODE_WRITE = 0, /*!< Master Write mode */ + I2C_MODE_READ /*!< Master Read mode */ +} I2C_ModeTypeDef; + +/** + * @brief I2C 时钟来源 + */ +typedef enum +{ + I2C_CLK_SRC_PCLK = (0x0UL << I2Cx_MCR0_CLKSRC_Pos), /*!< PCLK */ + I2C_CLK_SRC_LSE = (0x2UL << I2Cx_MCR0_CLKSRC_Pos), /*!< LSE */ + I2C_CLK_SRC_LSI = (0x3UL << I2Cx_MCR0_CLKSRC_Pos), /*!< LSI */ +} I2C_MasterClkSrcTypeDef; + +/** + * @brief I2C 主机时钟分频系数 + */ +typedef enum +{ + I2C_TCLK_Prescaler_Div1 = 0, + I2C_TCLK_Prescaler_Div2, + I2C_TCLK_Prescaler_Div4, + I2C_TCLK_Prescaler_Div8, + I2C_TCLK_Prescaler_Div16, + I2C_TCLK_Prescaler_Div32, + I2C_TCLK_Prescaler_Div64, + I2C_TCLK_Prescaler_Div128, +} I2C_TclkPrecaleTypeDef; + +/** + * @brief I2C slave 时钟延展和滤波时钟来源 + */ +typedef enum +{ + I2C_CLK_SRC_PCLK_SLV = (0x0UL << I2Cx_SCR0_CLKSRC_Pos), /*!< PCLK */ + I2C_CLK_SRC_LSE_SLV = (0x2UL << I2Cx_SCR0_CLKSRC_Pos), /*!< LSE */ + I2C_CLK_SRC_LSI_SLV = (0x3UL << I2Cx_SCR0_CLKSRC_Pos), /*!< LSI */ +} I2C_SlaveClkSrcTypeDef; + +/** + * @brief I2C SDA 输入信号来源 + */ +typedef enum +{ + I2C_SDA_INSRC_GPIO = (0x0UL << I2Cx_INSEL_SDAINSEL_Pos), /*!< I2Cx_SDA管脚 */ + I2C_SDA_INSRC_VC1_OUT = (0x1UL << I2Cx_INSEL_SDAINSEL_Pos), /*!< VC1_OUT */ + I2C_SDA_INSRC_VC2_OUT = (0x2UL << I2Cx_INSEL_SDAINSEL_Pos), /*!< VC2_OUT */ + I2C_SDA_INSRC_VC3_OUT = (0x3UL << I2Cx_INSEL_SDAINSEL_Pos), /*!< VC3_OUT */ + I2C_SDA_INSRC_VC4_OUT = (0x4UL << I2Cx_INSEL_SDAINSEL_Pos), /*!< VC4_OUT */ +} I2C_SdaInSrcTypeDef; + +/** + * @brief I2C SCL 输入信号来源 + */ +typedef enum +{ + I2C_SCL_INSRC_GPIO = (0x0UL << I2Cx_INSEL_SCLINSEL_Pos), /*!< I2Cx_SCL管脚 */ + I2C_SCL_INSRC_VC1_OUT = (0x1UL << I2Cx_INSEL_SCLINSEL_Pos), /*!< VC1_OUT */ + I2C_SCL_INSRC_VC2_OUT = (0x2UL << I2Cx_INSEL_SCLINSEL_Pos), /*!< VC2_OUT */ + I2C_SCL_INSRC_VC3_OUT = (0x3UL << I2Cx_INSEL_SCLINSEL_Pos), /*!< VC3_OUT */ + I2C_SCL_INSRC_VC4_OUT = (0x4UL << I2Cx_INSEL_SCLINSEL_Pos), /*!< VC4_OUT */ +} I2C_SclInSrcTypeDef; + +/** + * @brief I2C 主机数据匹配方式 + */ +typedef enum +{ + I2C_ByteMatch_Prohibit = (0x0UL), /*!< 禁止数据匹配 */ + I2C_ByteMatch_1st_M0_Or_M1 = (0x2UL), /*!< 第一个字节匹配 MATCH0 或 MATCH1 */ + I2C_ByteMatch_Any_M0_Or_M1 = (0x3UL), /*!< 任意字节匹配 MATCH0 或 MATCH1 */ + I2C_ByteMatch_1stM0_And_2ndM1 = (0x4UL), /*!< 第一个字节匹配 MATCH0 且第二个字节匹配 MATCH1 */ + I2C_ByteMatch_AnyM0_And_NextM1 = (0x5UL), /*!< 任意字节匹配 MATCH0 且下一字节匹配 MATCH1 */ + I2C_ByteMatch_1stAndM1_MAT_M0AndM1 = (0x6UL), /*!< 第一个字节与 MATCH1 相与后的值匹配 MATCH0 与MATCH1 相与后的值 */ + I2C_ByteMatch_AnyAndM1_MAT_M0AndM1 = (0x7UL), /*!< 任 意 字 节 与 MATCH1 相 与 后 的 值 匹 配 MATCH0 与MATCH1 相与后的值 */ +} I2C_DataMatchTypeDef; + +/** + * @brief I2C 从机地址比较方式 + */ +typedef enum +{ + I2C_Addr0_7bit = 0x0UL, /*!< 比较 ADDR0(7bit) */ + I2C_Addr0_10bit, /*!< 比较 ADDR0(10bit) */ + I2C_Addr0_Or_Addr1_7bit, /*!< 比较 ADDR0(7bit) / 比较 ADDR1(7bit) */ + I2C_Addr0_Or_Addr1_10bit, /*!< 比较 ADDR0(10bit) / 比较 ADDR1(10bit) */ + I2C_Addr0_7bit_Or_Addr1_10bit, /*!< 比较 ADDR0(7bit) / 比较 ADDR1(10bit) */ + I2C_Addr0_10bit_Or_Addr1_7bit, /*!< 比较 ADDR0(10bit) / 比较 ADDR1(7bit) */ + I2C_Addr0_To_Addr1_7bit, /*!< 比较地址空间 ADDR0 ~ ADDR1，7bit 模式 */ + I2C_Addr0_To_Addr1_10bit, /*!< 比较地址空间 ADDR0 ~ ADDR1，10bit 模式 */ +} I2C_SlaveAddrCfgTypeDef; + +/** + * @brief I2C 主机待执行的指令 + */ +enum I2C_MASTER_CMD +{ + I2C_Cmd_Tx_Data = (0x0UL << I2Cx_MTDR_CMD_Pos), /*!< 向总线发送一个字节数据 MTDR[7:0] */ + I2C_Cmd_Rx_DataToMRDR = (0x1UL << I2Cx_MTDR_CMD_Pos), /*!< 从总线接收（MTDR[7:0]+1）个字节数据，存入MRDR寄存器 */ + I2C_Cmd_Tx_STOP = (0x2UL << I2Cx_MTDR_CMD_Pos), /*!< 在总线上产生 STOP 信号 */ + I2C_Cmd_Rx_Data_BypassMRDR = (0x3UL << I2Cx_MTDR_CMD_Pos), /*!< 从总线接收（MTDR[7:0]+1）个字节数据， 不存入MRDR 寄存器 */ + I2C_Cmd_Tx_RepSTART_Data_Rx_ACK = (0x4UL << I2Cx_MTDR_CMD_Pos), /*!< 在总线上生成（Repeated）START 信号，并向总线发送一个字节数据 MTDR[7:0]，期待从总线收到 ACK */ + I2C_Cmd_Tx_RepSTART_Data_Rx_NACK = (0x5UL << I2Cx_MTDR_CMD_Pos), /*!< 在总线上生成（Repeated）START 信号，并向总线发送一个字节数据 MTDR[7:0]，期待从总线收到 NACK */ + I2C_Cmd_Tx_RepSTART_Data_Rx_ACK_HS = (0x6UL << I2Cx_MTDR_CMD_Pos), /*!< 在高速模式下生成（Repeated）START 信号，并向总线发送一个字节数据 MTDR[7:0]，期待从总线收到 ACK */ + I2C_Cmd_Tx_RepSTART_Data_Rx_NACK_HS = (0x7UL << I2Cx_MTDR_CMD_Pos), /*!< 在高速模式下生成（Repeated）START 信号，并向总线发送一个字节数据 MTDR[7:0]，期待从总线收到 NACK */ +} ; + +/** + * @brief I2C 总线状态字 + */ +enum I2C_STATUS +{ + I2C_Status_Success = 0, + I2C_Status_Busy, /*!< The master is already performing a transfer. */ + I2C_Status_Idle, /*!< The slave driver is idle. */ + I2C_Status_Nak, /*!< The slave device sent a NAK in response to a byte. */ + I2C_Status_FifoError, /*!< FIFO under run or overrun. */ + I2C_Status_BitError, /*!< Transferred bit was not seen on the bus. */ + I2C_Status_ArbitrationLost, /*!< Arbitration lost error. */ + I2C_Status_PinLowTimeout, /*!< SCL or SDA were held low longer than the timeout. */ + I2C_Status_NoTransferInProgress, /*!< Attempt to abort a transfer when one is not in progress. */ + I2C_Status_DmaRequestFail, /*!< DMA request failed. */ + I2C_Status_Timeout, /*!< Timeout poling status flags. */ + I2C_Status_Error, +}; + +/* Private_Defines -----------------------------------------------------------*/ +//I2C从设备地址，按照7/10 BIT设置 +#define I2C_SLAVEADDRESS_EEPROM (0xA0 >> 1) //读EEPROM时设置为(0xA0>>1) + +#ifndef I2C_WAIT_TIMEOUT +#define I2C_WAIT_TIMEOUT 0x100U //Best to adjust this value according to MCU's HCLK frequency. +#endif + +/*! @brief Retry times for waiting flag. */ +#ifndef I2C_RETRY_TIMES +#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +#define MAX_SLAVE_ADDR_7B (0x7F) +#define MAX_SLAVE_ADDR_10B (0x3FF) +#define I2C_SLAVE_ADDR10B_MSB_MASK (0x300) +#define I2C_SLAVE_ADDR10B_LSB_MASK (0x0FF) +#define I2C_SLAVE_ADDR10B_MSB (0xF0) //b11110XXY +#define MAX_DATA_LEN_RX (1024UL) +#define MAX_DATA_LEN_EEPROM (256UL) +#define MAX_SIZE_SUBADDRESS (4UL) + +#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == CW_I2C1) || ((PERIPH) == CW_I2C2)) + +#define I2C_CMD_TX_DATA (0U) +#define I2C_CMD_RX_DATA (1UL << I2Cx_MTDR_CMD_Pos) +#define I2C_CMD_STOP (2UL << I2Cx_MTDR_CMD_Pos) +#define I2C_CMD_START (4UL << I2Cx_MTDR_CMD_Pos) + +/** + * @defgroup I2C_Interrupts & Flags of I2C Master + */ +#define ENABLE_IT_MASK (0xFFFF80FC) // 定义清除I2C_MISR特定位的掩码 +#define CLEAR_IT_MASK (0xFFFF80FF) // 定义清除I2C_MICR特定位的掩码 +#define POLLING_IT_MASK (0xFCFF80FC) // 定义查询I2C_MISR特定位的掩码 +// 中断标志位定义 +#define I2C_IT_BUSBUSY (I2Cx_MISR_BUSBUSY_Msk) +#define I2C_IT_MSTBUSY (I2Cx_MISR_MSTBUSY_Msk) +#define I2C_IT_MATCH (I2Cx_MISR_MATCH_Msk) +#define I2C_IT_PINLOW (I2Cx_MISR_PINLOW_Msk) +#define I2C_IT_FIFO (I2Cx_MISR_FIFO_Msk) +#define I2C_IT_ARBI (I2Cx_MISR_ARBI_Msk) +#define I2C_IT_NACK (I2Cx_MISR_NACK_Msk) +#define I2C_IT_STOP (I2Cx_MISR_STOP_Msk) +#define I2C_IT_PACKET (I2Cx_MISR_PACKET_Msk) +#define I2C_IT_FRAME (I2Cx_MISR_FRAME_Msk) +#define I2C_IT_RXNE (I2Cx_MISR_RXNE_Msk) +#define I2C_IT_TXE (I2Cx_MISR_TXE_Msk) + +// 检查中断标志位 +#define IS_I2C_IT(IT) ((((IT) & POLLING_IT_MASK) == 0UL) && ((IT) != 0UL)) +// 检查清除中断标志位 +#define IS_I2C_CLEAR_IT(IT) ((((IT) & CLEAR_IT_MASK) == 0UL) && ((IT) != 0UL)) +// 检查使能中断标志位 +#define IS_I2C_ENABLE_IT(IT) ((((IT) & ENABLE_IT_MASK) == 0UL) && ((IT) != 0UL)) +// 检查标志位 +#define IS_I2C_FLAG(FLAG) ((((FLAG) & POLLING_IT_MASK) == 0UL) && ((FLAG) != 0UL)) +// 检查清除标志位 +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & CLEAR_IT_MASK) == 0UL) && ((FLAG) != 0UL)) + +/** + * @defgroup I2C_Interrupts & Flags of I2C Slave + */ +#define ENABLE_IT_MASK_SLV (0xFFFF00F0) // 定义清除I2C_SISR特定位的掩码 +#define CLEAR_IT_MASK_SLV (0xFFFFF0FF) // 定义清除I2C_SICR特定位的掩码 +#define POLLING_IT_MASK_SLV (0xFCFF00F0) // 定义查询I2C_SISR特定位的掩码 +// 中断标志位定义 +#define I2C_IT_BUSBUSY_SLV (I2Cx_SISR_BUSBUSY_Msk) +#define I2C_IT_SLVBUSY_SLV (I2Cx_SISR_SLVBUSY_Msk) +#define I2C_IT_ALERT_SLV (I2Cx_SISR_ALERT_Msk) +#define I2C_IT_GC_SLV (I2Cx_SISR_GC_Msk) +#define I2C_IT_AM1_SLV (I2Cx_SISR_AM1_Msk) +#define I2C_IT_AM0_SLV (I2Cx_SISR_AM0_Msk) +#define I2C_IT_FIFO_SLV (I2Cx_SISR_FIFO_Msk) +#define I2C_IT_BIT_SLV (I2Cx_SISR_BIT_Msk) +#define I2C_IT_STOP_SLV (I2Cx_SISR_STOP_Msk) +#define I2C_IT_RESTART_SLV (I2Cx_SISR_RESTART_Msk) +#define I2C_IT_TACK_SLV (I2Cx_SISR_TACK_Msk) +#define I2C_IT_ADDR_SLV (I2Cx_SISR_ADDR_Msk) +#define I2C_IT_RXNE_SLV (I2Cx_SISR_RXNE_Msk) +#define I2C_IT_TXE_SLV (I2Cx_SISR_TXE_Msk) + +// 检查中断标志位 +#define IS_I2C_IT_SLV(IT) ((((IT) & POLLING_IT_MASK_SLV) == 0UL) && ((IT) != 0UL)) +// 检查清除中断标志 +#define IS_I2C_CLEAR_IT_SLV(IT) ((((IT) & CLEAR_IT_MASK_SLV) == 0UL) && ((IT) != 0UL)) +// 检查使能中断标志 +#define IS_I2C_ENABLE_IT_SLV(IT) ((((IT) & ENABLE_IT_MASK_SLV) == 0UL) && ((IT) != 0UL)) +// 检查标志 +#define IS_I2C_FLAG_SLV(FLAG) ((((FLAG) & POLLING_IT_MASK_SLV) == 0UL) && ((FLAG) != 0UL)) +// 检查清除标志 +#define IS_I2C_CLEAR_FLAG_SLV(FLAG) ((((FLAG) & CLEAR_IT_MASK_SLV) == 0UL) && ((FLAG) != 0UL)) + +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { 0u, I2C1_BASE, I2C2_BASE,} +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { (I2C_TypeDef *)0u, CW_I2C1, CW_I2C2} +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { Reset_IRQn, I2C1_IRQn, I2C2_IRQn} +#define FSL_FEATURE_I2C_FIFO_SIZEn(x) (1) + +//I2C Master +#define I2C_MCR1_RDMO(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MCR1_RDMO_Pos)) & I2Cx_MCR1_RDMO_Msk) + +#define I2C_MCR2_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MCR2_MATCFG_Pos)) & I2Cx_MCR2_MATCFG_Msk) +#define I2C_MCR2_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MCR2_PINCFG_Pos)) & I2Cx_MCR2_PINCFG_Msk) +#define I2C_MCR2_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MCR2_IGNACK_Pos)) & I2Cx_MCR2_IGNACK_Msk) +#define I2C_MCR2_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MCR2_PRESCALE_Pos)) & I2Cx_MCR2_PRESCALE_Msk) + +#define I2C_MCR3_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MCR3_BUSIDLE_Pos)) & I2Cx_MCR3_BUSIDLE_Msk) +#define I2C_MCR3_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MCR3_FLTSCL_Pos)) & I2Cx_MCR3_FLTSCL_Msk) +#define I2C_MCR3_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MCR3_FLTSDA_Pos)) & I2Cx_MCR3_FLTSDA_Msk) + +#define I2C_MCR4_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MCR4_PINLOW_Pos)) & I2Cx_MCR4_PINLOW_Msk) + +#define I2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MCCR_CLKLO_Pos)) & I2Cx_MCCR_CLKLO_Msk) +#define I2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MCCR_CLKHI_Pos)) & I2Cx_MCCR_CLKHI_Msk) +#define I2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MCCR_SETHOLD_Pos)) & I2Cx_MCCR_SETHOLD_Msk) +#define I2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MCCR_DATAVD_Pos)) & I2Cx_MCCR_DATAVD_Msk) + +#define I2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MTDR_CMD_Pos)) & I2Cx_MTDR_CMD_Msk) +#define I2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MTDR_DATA_Pos)) & I2Cx_MTDR_DATA_Msk) + +#define I2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MCR0_MEN_Pos)) & I2Cx_MCR0_MEN_Msk) + +#define I2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MDER_TXE_Pos)) & I2Cx_MDER_TXE_Msk) +#define I2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MDER_RXNE_Pos)) & I2Cx_MDER_RXNE_Msk) + +#define I2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MFIFOCR_TXWATER_Pos)) & I2Cx_MFIFOCR_TXWATER_Msk) +#define I2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MFIFOCR_RXWATER_Pos)) & I2Cx_MFIFOCR_RXWATER_Msk) + +#define I2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MMATCH_MATCH0_Pos)) & I2Cx_MMATCH_MATCH0_Msk) +#define I2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_MMATCH_MATCH1_Pos)) & I2Cx_MMATCH_MATCH1_Msk) +/*! @} */ + +//I2C Slave +#define I2C_SCR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SCR1_ADRSTALL_Pos)) & I2Cx_SCR1_ADRSTALL_Msk) +#define I2C_SCR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SCR1_RXSTALL_Pos)) & I2Cx_SCR1_RXSTALL_Msk) +#define I2C_SCR1_TXSTALL(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SCR1_TXSTALL_Pos)) & I2Cx_SCR1_TXSTALL_Msk) +#define I2C_SCR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SCR1_ACKSTALL_Pos)) & I2Cx_SCR1_ACKSTALL_Msk) +#define I2C_SCR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SCR1_GCEN_Pos)) & I2Cx_SCR1_GCEN_Msk) +#define I2C_SCR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SCR1_ALERTEN_Pos)) & I2Cx_SCR1_ALERTEN_Msk) +#define I2C_SCR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SCR1_TXCFG_Pos)) & I2Cx_SCR1_TXCFG_Msk) +#define I2C_SCR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SCR1_RXCFG_Pos)) & I2Cx_SCR1_RXCFG_Msk) +#define I2C_SCR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SCR1_IGNACK_Pos)) & I2Cx_SCR1_IGNACK_Msk) +#define I2C_SCR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SCR1_HSMEN_Pos)) & I2Cx_SCR1_HSMEN_Msk) +#define I2C_SCR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SCR1_ADDRCFG_Pos)) & I2Cx_SCR1_ADDRCFG_Msk) + +#define I2C_SCR3_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SCR3_CLKHOLD_Pos)) & I2Cx_SCR3_CLKHOLD_Msk) +#define I2C_SCR3_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SCR3_DATAVD_Pos)) & I2Cx_SCR3_DATAVD_Msk) +#define I2C_SCR3_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SCR3_FLTSCL_Pos)) & I2Cx_SCR3_FLTSCL_Msk) +#define I2C_SCR3_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SCR3_FLTSDA_Pos)) & I2Cx_SCR3_FLTSDA_Msk) + +#define I2C_SCR0_SEN(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SCR0_SEN_Pos)) & I2Cx_SCR0_SEN_Msk) + +#define I2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SDER_ADDR_Pos)) & I2Cx_SDER_ADDR_Msk) +#define I2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SDER_RXNE_Pos)) & I2Cx_SDER_RXNE_Msk) +#define I2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_SDER_TXE_Pos)) & I2Cx_SDER_TXE_Msk) + +#define I2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << I2Cx_STAR_TXNACK_Pos)) & I2Cx_STAR_TXNACK_Msk) +/*! @} */ + +/*! + * @addtogroup lpi2c + * @{ + */ + +/* ! @brief LPI2C master fifo commands. */ +enum +{ + kTxDataCmd = I2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ + kRxDataCmd = I2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ + kStopCmd = I2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ + kStartCmd = I2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ +}; + +/*! + * @brief Default watermark values. + * + * The default watermarks are set to zero. + */ +enum +{ + kDefaultTxWatermark = 0, + kDefaultRxWatermark = 0, +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum +{ + kIdleState = 0, + kSendCommandState, + kIssueReadCommandState, + kTransferDataState, + kStopState, + kWaitForCompletionState, +}; + + +/*! \public + * @brief Generic status return codes. + */ +enum +{ + kStatus_Success = 0, /*!< Generic status for Success. */ + kStatus_Fail = 1, /*!< Generic status for Fail. */ + kStatus_ReadOnly = 2, /*!< Generic status for read only failure. */ + kStatus_OutOfRange = 3, /*!< Generic status for out of range access. */ + kStatus_InvalidArgument = 4, /*!< Generic status for invalid argument check. */ + kStatus_Timeout = 5, /*!< Generic status for timeout. */ + kStatus_NoTransferInProgress = 6, /*!< Generic status for no transfer in progress. */ + kStatus_Busy = 7, /*!< Generic status for module is busy. */ + kStatus_NoData = 8, /*!< Generic status for no data is found for the operation. */ +}; + +/*! @brief LPI2C status return codes. */ +enum +{ + kStatus_LPI2C_Busy = 100, /*!< The master is already performing a transfer. */ + kStatus_LPI2C_Idle = 101, /*!< The slave driver is idle. */ + kStatus_LPI2C_Nak = 102, /*!< The slave device sent a NAK in response to a byte. */ + kStatus_LPI2C_FifoError = 103, /*!< FIFO under run or overrun. */ + kStatus_LPI2C_BitError = 104, /*!< Transferred bit was not seen on the bus. */ + kStatus_LPI2C_ArbitrationLost = 105, /*!< Arbitration lost error. */ + kStatus_LPI2C_PinLowTimeout = 106, /*!< SCL or SDA were held low longer than the timeout. */ + kStatus_LPI2C_NoTransferInProgress = 107, /*!< Attempt to abort a transfer when one is not in progress. */ + kStatus_LPI2C_DmaRequestFail = 108, /*!< DMA request failed. */ + kStatus_LPI2C_Timeout = 109, /*!< Timeout polling status flags. */ +}; + +/*! @} */ + +/*! + * @addtogroup lpi2c_master_driver + * @{ + */ + +/*! + * @brief LPI2C master peripheral flags. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _lpi2c_master_flags +{ + kLPI2C_MasterTxReadyFlag = I2Cx_MISR_TXE_Msk, /*!< Transmit data flag */ + kLPI2C_MasterRxReadyFlag = I2Cx_MISR_RXNE_Msk, /*!< Receive data flag */ + kLPI2C_MasterEndOfPacketFlag = I2Cx_MISR_PACKET_Msk, /*!< End Packet flag */ + kLPI2C_MasterStopDetectFlag = I2Cx_MISR_STOP_Msk, /*!< Stop detect flag */ + kLPI2C_MasterNackDetectFlag = I2Cx_MISR_NACK_Msk, /*!< NACK detect flag */ + kLPI2C_MasterArbitrationLostFlag = I2Cx_MISR_ARBI_Msk, /*!< Arbitration lost flag */ + kLPI2C_MasterFifoErrFlag = I2Cx_MISR_FIFO_Msk, /*!< FIFO error flag */ + kLPI2C_MasterPinLowTimeoutFlag = I2Cx_MISR_PINLOW_Msk, /*!< Pin low timeout flag */ + kLPI2C_MasterDataMatchFlag = I2Cx_MISR_MATCH_Msk, /*!< Data match flag */ + kLPI2C_MasterBusyFlag = I2Cx_MISR_MSTBUSY_Msk, /*!< Master busy flag */ + kLPI2C_MasterBusBusyFlag = I2Cx_MISR_BUSBUSY_Msk, /*!< Bus busy flag */ + + /*! All flags which are cleared by the driver upon starting a transfer. */ + kLPI2C_MasterClearFlags = I2Cx_MISR_MATCH_Msk | I2Cx_MISR_PINLOW_Msk | + I2Cx_MISR_FIFO_Msk | I2Cx_MISR_ARBI_Msk | + I2Cx_MISR_NACK_Msk | I2Cx_MISR_STOP_Msk | + I2Cx_MISR_PACKET_Msk, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kLPI2C_MasterIrqFlags = I2Cx_MIER_MATCH_Msk | I2Cx_MIER_PINLOW_Msk | + I2Cx_MIER_FIFO_Msk | I2Cx_MIER_ARBI_Msk | + I2Cx_MIER_NACK_Msk | I2Cx_MIER_STOP_Msk | + I2Cx_MIER_PACKET_Msk | I2Cx_MIER_RXNE_Msk | + I2Cx_MIER_TXE_Msk, + /*! Errors to check for. */ + kLPI2C_MasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag | + kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag, +}; + +/*! @brief LPI2C pin configuration. */ +typedef enum _lpi2c_master_pin_config +{ + kLPI2C_2PinOpenDrain = 0x0U, /*!< LPI2C Configured for 2-pin open drain mode */ + kLPI2C_2PinOutputOnly = 0x1U, /*!< LPI2C Configured for 2-pin output only mode (ultra-fast mode) */ + kLPI2C_2PinPushPull = 0x2U, /*!< LPI2C Configured for 2-pin push-pull mode */ + kLPI2C_4PinPushPull = 0x3U, /*!< LPI2C Configured for 4-pin push-pull mode */ + kLPI2C_2PinOpenDrainWithSeparateSlave = 0x4U, /*!< LPI2C Configured for 2-pin open drain mode with separate LPI2C slave */ + kLPI2C_2PinOutputOnlyWithSeparateSlave = 0x5U, /*!< LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave */ + kLPI2C_2PinPushPullWithSeparateSlave = 0x6U, /*!< LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave */ + kLPI2C_4PinPushPullWithInvertedOutput = 0x7U, /*!< LPI2C Configured for 4-pin push-pull mode(inverted outputs) */ +} lpi2c_master_pin_config_t; + +/*! @brief LPI2C master host request selection. */ +typedef enum _lpi2c_host_request_source +{ + kLPI2C_HostRequestExternalPin = 0x0U, /*!< Select the LPI2C_HREQ pin as the host request input */ + kLPI2C_HostRequestInputTrigger = 0x1U, /*!< Select the input trigger as the host request input */ +} lpi2c_host_request_source_t; + +/*! @brief LPI2C master host request pin polarity configuration. */ +typedef enum _lpi2c_host_request_polarity +{ + kLPI2C_HostRequestPinActiveLow = 0x0U, /*!< Configure the LPI2C_HREQ pin active low */ + kLPI2C_HostRequestPinActiveHigh = 0x1U, /*!< Configure the LPI2C_HREQ pin active high */ +} lpi2c_host_request_polarity_t; + +/** + * \brief I2C主机初始化结构体 + */ +typedef struct +{ + uint32_t I2C_BaudRate_Hz; + uint32_t busIdleTimeout_ns; /*!< Bus idle timeout in nanoseconds. Set to 0 to disable. */ + uint32_t pinLowTimeout_ns; /*!< Pin low timeout in nanoseconds. Set to 0 to disable. */ + I2C_DataMatchTypeDef I2C_DataMatchMode; + I2C_MasterClkSrcTypeDef I2C_ClockSouce; + I2C_SdaInSrcTypeDef I2C_SDA_Source; + I2C_SclInSrcTypeDef I2C_SCL_Source; + boolean_t I2C_InDebugState; + boolean_t I2C_InDeepSleepState; + boolean_t I2C_RxDataMatch; + boolean_t I2C_TxFIFO_Autoload; + boolean_t ignoreAck; /*!< Whether to ignore ACK/NACK. */ + uint8_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable. */ + uint8_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable. */ + uint8_t I2C_PinsConfig; + struct + { + boolean_t enable; /*!< Enable host request. */ + lpi2c_host_request_source_t source; /*!< Host request source. */ + lpi2c_host_request_polarity_t polarity; /*!< Host request pin polarity. */ + } hostRequest; +} I2C_MasterConfigTypeDef; + +/*! @brief LPI2C master data match configuration structure. */ +typedef struct _lpi2c_match_config +{ + I2C_DataMatchTypeDef matchMode; /*!< Data match configuration setting. */ + boolean_t rxDataMatchOnly; /*!< When set to TRUE, received data is ignored until a successful match. */ + uint32_t match0; /*!< Match value 0. */ + uint32_t match1; /*!< Match value 1. */ +} lpi2c_data_match_config_t; + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t; +typedef struct _lpi2c_master_handle lpi2c_master_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to LPI2C_MasterTransferCreateHandle(). + * + * @param I2Cx The LPI2C peripheral base address. + * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_master_transfer_callback_t)(I2C_TypeDef *I2Cx, + lpi2c_master_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Transfer option flags. + * + * @note These enumerations are intended to be OR'd together to form a bit mask of options for + * the #_lpi2c_master_transfer::flags field. + */ +enum _lpi2c_master_transfer_flags +{ + kLPI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kLPI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kLPI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ + kLPI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ +}; + +/*! + * @brief Non-blocking transfer descriptor structure. + * + * This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API. + */ +struct _lpi2c_master_transfer +{ + uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_lpi2c_master_transfer_flags for + available options. Set to 0 or #kLPI2C_TransferDefaultFlag for normal transfers. */ + uint16_t slaveAddress; /*!< The 7-bit slave address. */ + I2C_ModeTypeDef direction; /*!< Either #I2C_MODE_READ or #I2C_MODE_WRITE. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ + void *data; /*!< Pointer to data to transfer. */ + size_t dataSize; /*!< Number of bytes to transfer. */ +}; + +/*! + * @brief Driver handle for master non-blocking APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_master_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint16_t remainingBytes; /*!< Remaining byte count in current state. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint16_t commandBuffer[6]; /*!< LPI2C command sequence. When all 6 command words are used: + Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word] */ + lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + lpi2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ +}; + +/*! @brief Typedef for master interrupt handler, used internally for LPI2C master interrupt APIs. + */ +typedef void (*lpi2c_master_isr_t)(I2C_TypeDef *I2Cx, void *handle); + +/*! @} */ + +/*! + * @addtogroup lpi2c_slave_driver + * @{ + */ + +/*! + * @brief LPI2C slave peripheral flags. + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + */ +enum _lpi2c_slave_flags +{ + kLPI2C_SlaveTxReadyFlag = I2Cx_SISR_TXE_Msk, /*!< Transmit data flag */ + kLPI2C_SlaveRxReadyFlag = I2Cx_SISR_RXNE_Msk, /*!< Receive data flag */ + kLPI2C_SlaveAddressValidFlag = I2Cx_SISR_ADDR_Msk, /*!< Address valid flag */ + kLPI2C_SlaveTransmitAckFlag = I2Cx_SISR_TACK_Msk, /*!< Transmit ACK flag */ + kLPI2C_SlaveRepeatedStartDetectFlag = I2Cx_SISR_RESTART_Msk, /*!< Repeated start detect flag */ + kLPI2C_SlaveStopDetectFlag = I2Cx_SISR_STOP_Msk, /*!< Stop detect flag */ + kLPI2C_SlaveBitErrFlag = I2Cx_SISR_BIT_Msk, /*!< Bit error flag */ + kLPI2C_SlaveFifoErrFlag = I2Cx_SISR_FIFO_Msk, /*!< FIFO error flag */ + kLPI2C_SlaveAddressMatch0Flag = I2Cx_SISR_AM0_Msk, /*!< Address match 0 flag */ + kLPI2C_SlaveAddressMatch1Flag = I2Cx_SISR_AM1_Msk, /*!< Address match 1 flag */ + kLPI2C_SlaveGeneralCallFlag = I2Cx_SISR_GC_Msk, /*!< General call flag */ + kLPI2C_SlaveBusyFlag = I2Cx_SISR_SLVBUSY_Msk, /*!< Master busy flag */ + kLPI2C_SlaveBusBusyFlag = I2Cx_SISR_BUSBUSY_Msk, /*!< Bus busy flag */ + /*! All flags which are cleared by the driver upon starting a transfer. */ + kLPI2C_SlaveClearFlags = I2Cx_SISR_RESTART_Msk | I2Cx_SISR_STOP_Msk | + I2Cx_SISR_BIT_Msk | I2Cx_SISR_FIFO_Msk, + /*! IRQ sources enabled by the non-blocking transactional API. */ + kLPI2C_SlaveIrqFlags = I2Cx_SIER_ALERT_Msk | I2Cx_SIER_GC_Msk | + I2Cx_SIER_AM1_Msk | I2Cx_SIER_AM0_Msk | + I2Cx_SIER_FIFO_Msk | I2Cx_SIER_BIT_Msk | + I2Cx_SIER_STOP_Msk | I2Cx_SIER_RESTART_Msk | + I2Cx_SIER_TACK_Msk | I2Cx_SIER_ADDR_Msk | + I2Cx_SIER_RXNE_Msk | I2Cx_SIER_TXE_Msk, + + /*! Errors to check for. */ + kLPI2C_SlaveErrorFlags = I2Cx_SISR_FIFO_Msk | I2Cx_SISR_BIT_Msk, +}; + +/** + * \brief I2C从机初始化结构体 + */ +typedef struct +{ + uint32_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SDA signal. Set to 0 to disable. */ + uint32_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SCL signal. Set to 0 to disable. */ + uint32_t dataValidDelay_ns; /*!< Width in nanoseconds of the data valid delay. */ + uint32_t clockHoldTime_ns; /*!< Width in nanoseconds of the clock hold time. */ + I2C_SlaveClkSrcTypeDef I2C_ClockSouce; + uint16_t I2C_Addr0; + uint16_t I2C_Addr1; + I2C_SlaveAddrCfgTypeDef addressMatchMode; + I2C_SlaveRegAddrTypeDef I2C_RegAddr; + boolean_t filterEnable; /*!< Enable digital glitch filter. */ + boolean_t enableGeneralCall; /*!< Enable general call address matching. */ + struct + { + boolean_t enableAck; /*!< Enables SCL clock stretching during slave-transmit address byte(s) + and slave-receiver address and data byte(s) to allow software to + write the Transmit ACK Register before the ACK or NACK is transmitted. + Clock stretching occurs when transmitting the 9th bit. When + enableAckSCLStall is enabled, there is no need to set either + enableRxDataSCLStall or enableAddressSCLStall. */ + boolean_t enableTx; /*!< Enables SCL clock stretching when the transmit data flag is set + during a slave-transmit transfer. */ + boolean_t enableRx; /*!< Enables SCL clock stretching when receive data flag is set during + a slave-receive transfer. */ + boolean_t enableAddress; /*!< Enables SCL clock stretching when the address valid flag is asserted. */ + } sclStall; + + boolean_t ignoreAck; /*!< Continue transfers after a NACK is detected. */ + boolean_t enableReceivedAddressRead; /*!< Enable reading the address received address as the first byte of data. */ +} I2C_SlaveConfigTypeDef; + +/*! + * @brief Set of events sent to the callback for non blocking slave transfers. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _lpi2c_slave_transfer_event +{ + kLPI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kLPI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + (slave-transmitter role). */ + kLPI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kLPI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. */ + kLPI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */ + kLPI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected, completing the transfer. */ + + /*! Bit mask of all available events. */ + kLPI2C_SlaveAllEvents = kLPI2C_SlaveAddressMatchEvent | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent | + kLPI2C_SlaveTransmitAckEvent | kLPI2C_SlaveRepeatedStartEvent | kLPI2C_SlaveCompletionEvent, +} lpi2c_slave_transfer_event_t; + +/*! @brief LPI2C slave transfer structure */ +typedef struct _lpi2c_slave_transfer +{ + lpi2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ + uint8_t receivedAddress; /*!< Matching address send by master. */ + uint8_t *data; /*!< Transfer buffer */ + size_t dataSize; /*!< Transfer size */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kLPI2C_SlaveCompletionEvent. */ + size_t transferredCount; /*!< Number of bytes actually transferred since start or last repeated start. */ +} lpi2c_slave_transfer_t; + +/* Forward declaration. */ +typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t; + +/*! + * @brief Slave event callback function pointer type. + * + * @param I2Cx Base address for the LPI2C instance on which the event occurred. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_slave_transfer_callback_t)(I2C_TypeDef *I2Cx, lpi2c_slave_transfer_t *transfer, void *userData); + +/*! + * @brief LPI2C slave handle structure. + */ +struct _lpi2c_slave_handle +{ + lpi2c_slave_transfer_t transfer; /*!< LPI2C slave transfer copy. */ + boolean_t isBusy; /*!< Whether transfer is busy. */ + boolean_t wasTransmit; /*!< Whether the last transfer was a transmit. */ + uint32_t eventMask; /*!< Mask of enabled events. */ + uint32_t transferredCount; /*!< Count of bytes transferred. */ + lpi2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*lpi2c_slave_isr_t)(I2C_TypeDef *I2Cx, lpi2c_slave_handle_t *handle); +/*! @} */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +// I2C Master使能或禁能 +void I2C_MasterCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +// I2C Slave使能或禁能 +void I2C_SlaveCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +// I2C Master初始化 +ErrorStatus I2C_MasterInit(I2C_TypeDef *I2Cx, I2C_MasterConfigTypeDef *I2C_MasterConfig, uint32_t sourceClock_Hz); +// I2C Slave初始化 +ErrorStatus I2C_SlaveInit(I2C_TypeDef *I2Cx, I2C_SlaveConfigTypeDef *I2C_SlaveConfig, uint32_t sourceClock_Hz); +// I2C 去初始化 +void I2C_DeInit(I2C_TypeDef *I2Cx); +void I2C_MasterDeinit(I2C_TypeDef *I2Cx); +void I2C_SlaveDeinit(I2C_TypeDef *I2Cx); +// I2C Master设置波特率 +void I2C_MasterSetBaudRate(I2C_TypeDef *I2Cx, uint32_t sourceClock_Hz, uint32_t baudRate_Hz); +// 发送START/ReSTART信号 +uint8_t I2C_MasterSTART_Addr7b(I2C_TypeDef *I2Cx, uint8_t slaveAddr, I2C_ModeTypeDef dataMode); +uint8_t I2C_MasterReSTART_Addr7b(I2C_TypeDef *I2Cx, uint8_t slaveAddr, I2C_ModeTypeDef dataMode); +uint8_t I2C_MasterSTART_Addr10b(I2C_TypeDef *I2Cx, uint16_t slaveAddr, I2C_ModeTypeDef dataMode); +uint8_t I2C_MasterReSTART_Addr10b(I2C_TypeDef *I2Cx, uint16_t slaveAddr, I2C_ModeTypeDef dataMode); +// 发送STOP信号 +uint8_t I2C_MasterSTOP(I2C_TypeDef *I2Cx); +// I2C 主机接收 +uint8_t I2C_MasterReceive(I2C_TypeDef *I2Cx, uint8_t *rxBuff, uint16_t rxSize); +// I2C 主机发送 +uint8_t I2C_MasterSend(I2C_TypeDef *I2Cx, uint8_t *txBuff, uint16_t txSize); +// I2C 从机接收 +uint8_t I2C_SlaveReceive(I2C_TypeDef *I2Cx, uint8_t *rxBuff, uint16_t *rxSize); +// I2C 从机发送 +uint8_t I2C_SlaveSend(I2C_TypeDef *I2Cx, uint8_t *txBuff, uint16_t txSize); + +void I2C_MasterSoftReset(I2C_TypeDef *I2Cx); +void I2C_SlaveSoftReset(I2C_TypeDef *I2Cx); +void I2C_MasterTxFIFOReset(I2C_TypeDef *I2Cx); +void I2C_MasterRxFIFOReset(I2C_TypeDef *I2Cx); +void I2C_SlaveTxFIFOReset(I2C_TypeDef *I2Cx); +void I2C_SlaveRxFIFOReset(I2C_TypeDef *I2Cx); +void I2C_MasterBusFilter(I2C_TypeDef *I2Cx, uint8_t SDAFilter, uint8_t SCLFilter); +void I2C_SlaveBusFilter(I2C_TypeDef *I2Cx, uint8_t SDAFilter, uint8_t SCLFilter); + +void I2C_MasterClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); +uint8_t I2C_MasterPollingFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); +uint8_t I2C_MasterPollingFlagReverse(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); +static uint8_t I2C_MasterPollingFlagCommon(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG, boolean_t reverse); +uint32_t I2C_MasterGetFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); + +void I2C_SlaveClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); +uint8_t I2C_SlavePollingFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); +uint8_t I2C_SlavePollingFlagReverse(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); +static uint8_t I2C_SlavePollingFlagCommon(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG, boolean_t reverse); +uint32_t I2C_SlaveGetFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); + +void I2C_MasterInitDefault(I2C_MasterConfigTypeDef *masterConfig); +void I2C_SlaveInitDefault(I2C_SlaveConfigTypeDef *slaveConfig); + +// 主写EEPROM函数 +uint8_t I2C_MasterWriteEepromData(I2C_TypeDef *I2Cx, uint32_t regAddr, I2C_SlaveRegAddrTypeDef regAddrType, uint8_t *pu8Data, uint16_t u16Len); +// 主读EEPROM函数 +uint8_t I2C_MasterReadEepromData(I2C_TypeDef *I2Cx, uint32_t regAddr, I2C_SlaveRegAddrTypeDef regAddrType, uint8_t *pu8Data, uint16_t u16Len); + +// 主机发送X字节数据 +uint8_t I2C_MasterSendDataToSlave(I2C_TypeDef *I2Cx, uint16_t slaveAddr, uint8_t *pu8Data, uint16_t u16Len); +// 主机读取X字节数据 +uint8_t I2C_MasterReceiveDataFromSlave(I2C_TypeDef *I2Cx, uint16_t slaveAddr, uint8_t *pu8RegAddr, I2C_SlaveRegAddrTypeDef regAddrType, uint8_t *pu8Data, uint16_t u16Len); + +void I2C_SlaveTxNAck(I2C_TypeDef *I2Cx, FunctionalState stateNAck); + +static uint32_t I2C_GetCyclesForWidth(uint32_t sourceClock_Hz, uint32_t width_ns, uint32_t minCycles, uint32_t maxCycles, uint32_t prescaler); + +uint32_t LPI2C_GetInstance(I2C_TypeDef *I2Cx); + +/*! + * @addtogroup lpi2c_master_driver + * @{ + */ + +void LPI2C_MasterConfigureDataMatch(I2C_TypeDef *I2Cx, const lpi2c_data_match_config_t *matchConfig); + +status_t LPI2C_MasterCheckAndClearError(I2C_TypeDef *I2Cx, uint32_t status); + +status_t LPI2C_CheckForBusyBus(I2C_TypeDef *I2Cx); + +/*@}*/ + +/*! @name Status */ +/*@{*/ + +/** + * @brief 获取LPI2C主模式状态标志 + * + * 该函数用于获取指定LPI2C接口的主模式状态标志。 + * + * @param I2Cx LPI2C接口指针，指向一个I2C_TypeDef结构体 + * + * @return 返回LPI2C主模式状态标志，通过读取MSR寄存器获取 + */ +static inline uint32_t LPI2C_MasterGetStatusFlags(I2C_TypeDef *I2Cx) +{ + return I2Cx->MISR; +} + +/*@}*/ + +/*! @name Interrupts */ +/*@{*/ + +/** + * @brief 使能指定的I2C主模式中断 + * + * 该函数用于使能I2C主模式下指定的中断。 + * + * @param I2Cx 指向I2C外设的指针 + * @param interruptMask 要使能的中断掩码，可以是多个中断的组合 + */ +static inline void LPI2C_MasterEnableInterrupts(I2C_TypeDef *I2Cx, uint32_t interruptMask) +{ + I2Cx->MIER |= interruptMask; +} + +/** + * @brief 禁用LPI2C主机中断 + * + * 禁用指定LPI2C主机接口上的指定中断。 + * + * @param I2Cx LPI2C主机接口指针，指向I2C_TypeDef类型的结构体。 + * @param interruptMask 要禁用的中断掩码，可以通过按位或运算组合多个中断标志。 + */ +static inline void LPI2C_MasterDisableInterrupts(I2C_TypeDef *I2Cx, uint32_t interruptMask) +{ + I2Cx->MIER &= ~interruptMask; +} + +/** + * @brief 获取LPI2C主模式已启用的中断 + * + * 获取指定LPI2C接口在主模式下已启用的中断。 + * + * @param I2Cx LPI2C接口指针 + * @return 已启用的中断标志，具体值参考LPI2C模块的MIER寄存器 + */ +static inline uint32_t LPI2C_MasterGetEnabledInterrupts(I2C_TypeDef *I2Cx) +{ + return I2Cx->MIER; +} + +/*@}*/ + +/*! @name DMA control */ +/*@{*/ + +/** + * @brief 使能或禁用LPI2C主机模式下的DMA传输 + * + * 使能或禁用指定LPI2C接口在主机模式下的DMA传输功能。 + * + * @param I2Cx 指向LPI2C接口的指针 + * @param enableTx 是否使能TX DMA传输，TRUE表示使能，FALSE表示禁用 + * @param enableRx 是否使能RX DMA传输，TRUE表示使能，FALSE表示禁用 + */ +static inline void LPI2C_MasterEnableDMA(I2C_TypeDef *I2Cx, boolean_t enableTx, boolean_t enableRx) +{ + I2Cx->MDER = I2C_MDER_TDDE(enableTx) | I2C_MDER_RDDE(enableRx); +} + +/** + * @brief 获取LPI2C主模式发送FIFO的数据 + * + * 获取指定LPI2C接口的发送FIFO（MTDR）的数据。 + * + * @param I2Cx LPI2C接口指针 + * @return 返回一个uint32_t类型的值，表示LPI2C主模式发送FIFO的数据 + */ +static inline uint32_t LPI2C_MasterGetTxFifoAddress(I2C_TypeDef *I2Cx) +{ + return (uint32_t)&I2Cx->MTDR; +} + +/** + * @brief 获取LPI2C主设备接收FIFO的数据 + * + * 获取LPI2C主设备接收FIFO的数据。 + * + * @param I2Cx LPI2C模块指针 + * + * @return 返回接收FIFO的数据 + */ +static inline uint32_t LPI2C_MasterGetRxFifoAddress(I2C_TypeDef *I2Cx) +{ + return (uint32_t)&I2Cx->MRDR; +} + +/*@}*/ + +/*! @name FIFO control */ +/*@{*/ + +/** + * @brief 设置LPI2C主模式传输和接收的水位标记 + * + * 该函数用于设置LPI2C主模式下的传输和接收水位标记。 + * + * @param I2Cx 指向I2C类型定义的指针，表示要配置的LPI2C实例 + * @param txWords 要设置的传输水位标记，单位为字（word） + * @param rxWords 要设置的接收水位标记，单位为字（word） + */ +static inline void LPI2C_MasterSetWatermarks(I2C_TypeDef *I2Cx, size_t txWords, size_t rxWords) +{ + I2Cx->MFIFOCR = I2C_MFCR_TXWATER(txWords) | I2C_MFCR_RXWATER(rxWords); +} + +/** + * @brief I2C主机获取FIFO中TX和RX的计数值 + * + * 该函数用于获取I2C主模式FIFO中TX和RX的计数值。 + * + * @param I2Cx I2C模块指针 + * @param rxCount 指向存储RX计数值的变量的指针 + * @param txCount 指向存储TX计数值的变量的指针 + * + * @return 无 + */ +static inline void LPI2C_MasterGetFifoCounts(I2C_TypeDef *I2Cx, size_t *rxCount, size_t *txCount) +{ + if (NULL != txCount) + { + *txCount = (I2Cx->MFIFOSR & I2Cx_MFIFOSR_TXCNT_Msk) >> I2Cx_MFIFOSR_TXCNT_Pos; + } + + if (NULL != rxCount) + { + *rxCount = (I2Cx->MFIFOSR & I2Cx_MFIFOSR_RXCNT_Msk) >> I2Cx_MFIFOSR_RXCNT_Pos; + } +} + +/*@}*/ + +/*! @name Bus operations */ +/*@{*/ + +/** + * @brief 主机获取I2C总线的空闲状态 + * + * 获取指定I2C总线的空闲状态。如果总线处于忙碌状态，则返回FALSE；否则返回TRUE。 + * + * @param I2Cx 指向I2C模块的指针 + * + * @return 如果I2C总线空闲，则返回TRUE；否则返回FALSE + */ +static inline boolean_t LPI2C_MasterGetBusIdleState(I2C_TypeDef *I2Cx) +{ + return ((I2Cx->MISR & I2Cx_MISR_BUSBUSY_Msk) >> I2Cx_MISR_BUSBUSY_Pos) == 1U ? TRUE : FALSE; +} + +status_t LPI2C_MasterSend(I2C_TypeDef *I2Cx, void *txBuff, size_t txSize); + +status_t LPI2C_MasterReceive(I2C_TypeDef *I2Cx, void *rxBuff, size_t rxSize); + +status_t LPI2C_MasterStop(I2C_TypeDef *I2Cx); + +status_t LPI2C_MasterTransferBlocking(I2C_TypeDef *I2Cx, lpi2c_master_transfer_t *transfer); + +/*@}*/ + +/*! @name Non-blocking */ +/*@{*/ +void LPI2C_MasterTransferCreateHandle(I2C_TypeDef *I2Cx, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_callback_t callback, + void *userData); + +status_t LPI2C_MasterTransferNonBlocking(I2C_TypeDef *I2Cx, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_t *transfer); + +status_t LPI2C_MasterTransferGetCount(I2C_TypeDef *I2Cx, lpi2c_master_handle_t *handle, size_t *count); + +void LPI2C_MasterTransferAbort(I2C_TypeDef *I2Cx, lpi2c_master_handle_t *handle); + +/*@}*/ + +/*! @name IRQ handler */ +/*@{*/ +void LPI2C_MasterTransferHandleIRQ(I2C_TypeDef *I2Cx, void *lpi2cMasterHandle); + +/*@}*/ + +/*! @} */ + +/*! + * @addtogroup lpi2c_slave_driver + * @{ + */ + +/** + * @brief 获取LPI2C从设备状态标志 + * + * 该函数用于获取指定的LPI2C从设备状态标志。 + * + * @param I2Cx 指向I2C类型的指针，指向要操作的LPI2C从设备 + * + * @return 返回从设备的状态标志，类型为uint32_t + */ +static inline uint32_t LPI2C_SlaveGetStatusFlags(I2C_TypeDef *I2Cx) +{ + return I2Cx->SISR; +} + +/*@}*/ + +/*! @name Slave interrupts */ +/*@{*/ + +/** + * @brief 使能指定I2C从设备的中断 + * + * 该函数用于使能指定I2C从设备的中断。通过向I2C从设备的SIER寄存器写入指定的中断掩码， + * 来使能相应的中断。 + * + * @param I2Cx 指向I2C设备的指针 + * @param interruptMask 需要使能的中断掩码，可以通过按位或操作组合多个中断标志 + */ +static inline void LPI2C_SlaveEnableInterrupts(I2C_TypeDef *I2Cx, uint32_t interruptMask) +{ + I2Cx->SIER |= interruptMask; +} + +/** + * @brief 禁用I2C从设备的中断 + * + * 该函数用于禁用指定I2C从设备的中断。 + * + * @param I2Cx I2C设备指针 + * @param interruptMask 需要禁用的中断掩码 + */ +static inline void LPI2C_SlaveDisableInterrupts(I2C_TypeDef *I2Cx, uint32_t interruptMask) +{ + I2Cx->SIER &= ~interruptMask; +} + +/** + * @brief 获取LPI2C从机使能的中断 + * + * 获取指定I2C从机使能的中断状态。 + * + * @param I2Cx 指向I2C模块的指针 + * + * @return 返回I2Cx->SIER寄存器的值，即当前使能的中断状态 + */ +static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(I2C_TypeDef *I2Cx) +{ + return I2Cx->SIER; +} + +/*@}*/ + +/*! @name Slave DMA control */ +/*@{*/ + +/** + * @brief 使能LPI2C从设备的DMA功能 + * + * 该函数用于配置LPI2C从设备的DMA相关功能，包括地址有效性、接收和发送使能。 + * + * @param I2Cx LPI2C设备指针，指向需要配置的LPI2C外设实例。 + * @param enableAddressValid 是否使能地址有效性检查。 + * TRUE: 使能地址有效性检查； + * FALSE: 不使能地址有效性检查。 + * @param enableRx 是否使能DMA接收功能。 + * TRUE: 使能DMA接收功能； + * FALSE: 不使能DMA接收功能。 + * @param enableTx 是否使能DMA发送功能。 + * TRUE: 使能DMA发送功能； + * FALSE: 不使能DMA发送功能。 + */ +static inline void LPI2C_SlaveEnableDMA(I2C_TypeDef *I2Cx, boolean_t enableAddressValid, boolean_t enableRx, boolean_t enableTx) +{ + I2Cx->SDER = (I2Cx->SDER & ~(I2Cx_SDER_ADDR_Msk | I2Cx_SDER_RXNE_Msk | I2Cx_SDER_TXE_Msk)) | + I2C_SDER_AVDE(enableAddressValid) | I2C_SDER_RDDE(enableRx) | I2C_SDER_TDDE(enableTx); +} + +/*@}*/ + +/*! @name Slave bus operations */ +/*@{*/ + +/** + * @brief 从设备获取LPI2C的总线空闲状态 + * + * 该函数用于从设备获取指定LPI2C的总线空闲状态。 + * + * @param I2Cx LPI2C设备实例指针 + * + * @return 返回一个布尔值，表示总线是否空闲： + * - TRUE：总线空闲 + * - FALSE：总线忙碌 + */ +static inline boolean_t LPI2C_SlaveGetBusIdleState(I2C_TypeDef *I2Cx) +{ + return ((I2Cx->SISR & I2Cx_SISR_BUSBUSY_Msk) >> I2Cx_SISR_BUSBUSY_Pos) == 1U ? TRUE : FALSE; +} + +/** + * @brief 从设备发送应答或非应答信号 + * + * 该函数用于在I2C通信过程中，从设备发送应答（ACK）或非应答（NACK）信号。 + * + * @param I2Cx I2C设备指针，指向需要操作的I2C设备。 + * @param ackOrNack 应答信号标志，传入TRUE表示发送应答信号，传入FALSE表示发送非应答信号。 + */ +static inline void LPI2C_SlaveTransmitAck(I2C_TypeDef *I2Cx, boolean_t ackOrNack) +{ + I2Cx->STAR = I2C_STAR_TXNACK(!ackOrNack); +} + +/** + * @brief LPI2C从设备获取接收到的地址 + * + * 该函数从指定的LPI2C设备的状态和控制寄存器中获取从设备接收到的地址。 + * + * @param I2Cx 指向I2C设备类型的指针 + * + * @return 返回接收到的地址 + */ +static inline uint32_t LPI2C_SlaveGetReceivedAddress(I2C_TypeDef *I2Cx) +{ + return I2Cx->SASR & I2Cx_SASR_RADDR_Msk; +} + +status_t LPI2C_SlaveSend(I2C_TypeDef *I2Cx, void *txBuff, size_t txSize, size_t *actualTxSize); + +status_t LPI2C_SlaveReceive(I2C_TypeDef *I2Cx, void *rxBuff, size_t rxSize, size_t *actualRxSize); + +/*@}*/ + +/*! @name Slave non-blocking */ +/*@{*/ + +void LPI2C_SlaveTransferCreateHandle(I2C_TypeDef *I2Cx, + lpi2c_slave_handle_t *handle, + lpi2c_slave_transfer_callback_t callback, + void *userData); + +status_t LPI2C_SlaveTransferNonBlocking(I2C_TypeDef *I2Cx, lpi2c_slave_handle_t *handle, uint32_t eventMask); + +status_t LPI2C_SlaveTransferGetCount(I2C_TypeDef *I2Cx, lpi2c_slave_handle_t *handle, size_t *count); + +void LPI2C_SlaveTransferAbort(I2C_TypeDef *I2Cx, lpi2c_slave_handle_t *handle); + +/*@}*/ + +/*! @name Slave IRQ handler */ +/*@{*/ +void LPI2C_SlaveTransferHandleIRQ(I2C_TypeDef *I2Cx, lpi2c_slave_handle_t *handle); + +void LPI2C_CommonIRQHandler(I2C_TypeDef *I2Cx, uint32_t instance); + +#ifdef __cplusplus +} + +#endif + +#endif /*__CW32L012_LPI2C_H */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_lptim.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_lptim.h new file mode 100644 index 0000000..5425824 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_lptim.h @@ -0,0 +1,172 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_LPTIM_H +#define __CW32L012_LPTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012.h" +#include "base_types.h" + + +/* Exported types ------------------------------------------------------------*/ + +typedef enum {DOWN_STOP = 0, UP_STOP, DOWN_RUN, UP_RUN} ENCStatus; + + + +/** + * @brief LPTIM Init structure definition + */ + +typedef struct +{ + uint32_t LPTIM_ClockSource; + uint32_t LPTIM_CounterMode; + uint32_t LPTIM_Period; + uint32_t LPTIM_Prescaler; +} LPTIM_InitTypeDef; + + +/* Exported constants --------------------------------------------------------*/ +#define LPTIM_CLOCK_SOURCE_MCLK ((uint32_t)0x00000000) +#define LPTIM_CLOCK_SOURCE_CH1 ((uint32_t)0x00000001) +#define IS_LPTIM_CLOCK_SOURCE(SOURCE) (((SOURCE) == LPTIM_CLOCK_SOURCE_MCLK) ||\ + ((SOURCE) == LPTIM_CLOCK_SOURCE_CH1)) + +#define LPTIM_COUNTER_MODE_TIME ((uint32_t)0x00000000) +#define LPTIM_COUNTER_MODE_COUNT (((uint32_t)0x00000001) << 23) +#define IS_LPTIM_COUNTER_MODE(MODE) (((MODE) == LPTIM_COUNTER_MODE_TIME) ||\ + ((MODE) == LPTIM_COUNTER_MODE_COUNT)) + +#define LPTIM_PRS_DIV1 (((uint32_t)0x00000000)) +#define LPTIM_PRS_DIV2 (((uint32_t)0x00000001) << 9) +#define LPTIM_PRS_DIV4 (((uint32_t)0x00000002) << 9) +#define LPTIM_PRS_DIV8 (((uint32_t)0x00000003) << 9) +#define LPTIM_PRS_DIV16 (((uint32_t)0x00000004) << 9) +#define LPTIM_PRS_DIV32 (((uint32_t)0x00000005) << 9) +#define LPTIM_PRS_DIV64 (((uint32_t)0x00000006) << 9) +#define LPTIM_PRS_DIV128 (((uint32_t)0x00000007) << 9) +#define IS_LPTIM_PRS(PRS) (((PRS) == LPTIM_PRS_DIV1) || \ + ((PRS) == LPTIM_PRS_DIV2) || \ + ((PRS) == LPTIM_PRS_DIV4) || \ + ((PRS) == LPTIM_PRS_DIV8) || \ + ((PRS) == LPTIM_PRS_DIV16) || \ + ((PRS) == LPTIM_PRS_DIV32) || \ + ((PRS) == LPTIM_PRS_DIV64) || \ + ((PRS) == LPTIM_PRS_DIV128)) + +#define LPTIM_OPERATION_SINGLE ((uint32_t)0x00000002) +#define LPTIM_OPERATION_REPETITIVE ((uint32_t)0x00000004) +#define IS_LPTIM_OPERATION_MODE(MODE) (((MODE) == LPTIM_OPERATION_SINGLE) ||\ + ((MODE) == LPTIM_OPERATION_REPETITIVE)) + +#define LPTIM_RELOAD_MODE_UPDATE (((uint32_t)0x00000001) << 22) +#define LPTIM_RELOAD_MODE_IMMEDIATE (((uint32_t)0x00000000)) +#define IS_LPTIM_RELOAD_MODE(RELOAD) (((RELOAD) == LPTIM_RELOAD_MODE_UPDATE) ||\ + ((RELOAD) == LPTIM_RELOAD_MODE_IMMEDIATE)) + + + +#define LPTIM_FLAG_CMPM (((uint32_t)0x00000001)) +#define LPTIM_FLAG_ARRM (((uint32_t)0x00000001) << 1) +#define LPTIM_FLAG_EXTTRIG (((uint32_t)0x00000001) << 2) +#define LPTIM_FLAG_CMPOK (((uint32_t)0x00000001) << 3) +#define LPTIM_FLAG_ARROK (((uint32_t)0x00000001) << 4) +#define LPTIM_FLAG_UP (((uint32_t)0x00000001) << 5) +#define LPTIM_FLAG_DOWN (((uint32_t)0x00000001) << 6) +//#define LPTIM_FLAG_DIR (((uint32_t)0x00000003) << 7) +#define IS_LPTIM_GET_FLAG(FLAG) (((FLAG) == LPTIM_FLAG_CMPM) || \ + ((FLAG) == LPTIM_FLAG_ARRM) || \ + ((FLAG) == LPTIM_FLAG_EXTTRIG) || \ + ((FLAG) == LPTIM_FLAG_CMPOK) || \ + ((FLAG) == LPTIM_FLAG_ARROK) || \ + ((FLAG) == LPTIM_FLAG_UP) || \ + ((FLAG) == LPTIM_FLAG_DOWN)) +// ((FLAG) == LPTIM_FLAG_DIR)) + +#define IS_LPTIM_CLEAR_FLAG(FLAG) ((((FLAG) & 0xFFFFFE00) == 0x00000000) && ((FLAG) != 0x00000000)) + +#define LPTIM_IT_CMPM (((uint32_t)0x00000000)) +#define LPTIM_IT_ARRM (((uint32_t)0x00000001) << 1) +#define LPTIM_IT_EXTTRIG (((uint32_t)0x00000001) << 2) +#define LPTIM_IT_CMPOK (((uint32_t)0x00000001) << 3) +#define LPTIM_IT_ARROK (((uint32_t)0x00000001) << 4) +#define LPTIM_IT_UP (((uint32_t)0x00000001) << 5) +#define LPTIM_IT_DOWN (((uint32_t)0x00000001) << 6) + +#define IS_LPTIM_IT(IT) (((IT) == LPTIM_IT_CMPM) || \ + ((IT) == LPTIM_IT_ARRM) || \ + ((IT) == LPTIM_IT_EXTTRIG) || \ + ((IT) == LPTIM_IT_CMPOK) || \ + ((IT) == LPTIM_IT_ARROK) || \ + ((IT) == LPTIM_IT_UP) || \ + ((IT) == LPTIM_IT_DOWN)) + +#define IS_LPTIM_CLEAR_IT(IT) ((((IT) & 0xFFFFFF80) == 0x00000000) && ((IT) != 0x00000000)) + +#define LPTIM_ICLK_PCLK ((uint32_t)0x00000000) +#define LPTIM_ICLK_LSE (((uint32_t)0x00000002) << 25) +#define LPTIM_ICLK_LSI (((uint32_t)0x00000003) << 25) +#define IS_LPTIM_ICLK(SRC) (((SRC) == LPTIM_ICLK_PCLK) ||\ + ((SRC) == LPTIM_ICLK_LSE) ||\ + ((SRC) == LPTIM_ICLK_LSI)) + +#define LPTIM_PWM_POL_POS (((uint32_t)0x00000000)) +#define LPTIM_PWM_POL_NEG (((uint32_t)0x00000001) << 21) +#define IS_LPTIM_PWM_POL(POL) (((POL) == LPTIM_PWM_POL_POS) || ((POL) == LPTIM_PWM_POL_NEG)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void LPTIM_DeInit(void); +void LPTIM_Init(LPTIM_InitTypeDef* LPTIM_InitStruct); +void LPTIM_PrescalerConfig(uint32_t Prescaler); +void LPTIM_CounterModeConfig(uint32_t LPTIM_CounterMode); +void LPTIM_SetAutoreload(uint16_t Autoreload, uint32_t ReloadMode); +uint32_t LPTIM_GetCounter(void); +uint8_t LPTIM_GetPrescaler(void); +void LPTIM_SelectOnePulseMode(uint16_t LPTIM_OPMode); +void LPTIM_Cmd(FunctionalState NewState); + +void LPTIM_InternalClockConfig(uint32_t LPTIM_ICLK_Source); +void LPTIM_PWMStart(uint32_t Period, uint32_t Pulse, uint32_t Polarity); + + + +void LPTIM_ITConfig(uint32_t LPTIM_IT, FunctionalState NewState); +FlagStatus LPTIM_GetFlagStatus(uint32_t LPTIM_FLAG); +void LPTIM_ClearFlag(uint32_t LPTIM_FLAG); +ITStatus LPTIM_GetITStatus(uint32_t LPTIM_IT); +void LPTIM_ClearITPendingBit(uint32_t LPTIM_IT); + +ENCStatus LPTIM_GetENCStatus(void); + + + + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32L012_LPTIM_H */ +/** + * @} + */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_lvd.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_lvd.h new file mode 100644 index 0000000..992dd1b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_lvd.h @@ -0,0 +1,245 @@ +/** + * @file cw32l012_lvd.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +#ifndef __CW32L012_LVD_H +#define __CW32L012_LVD_H + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "base_types.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup LvdGroup Low Voltage Detector (LVD) + ** + ******************************************************************************/ +//@{ +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define LVD_INT_PRIORITY ((uint32_t)3) /*VC interrupt priority (lowest by default) */ + +/** + * @} + */ +/** @defgroup LVD_interrupts_definition + * @{ + */ +#define LVD_TRIG_LEVEL ((uint16_t)0x0002) +#define LVD_TRIG_RISE ((uint16_t)0x0004) +#define LVD_TRIG_FALL ((uint16_t)0x0008) + + +#define IS_LVD_TRIG(TRIG) ((((TRIG) & (uint16_t)0xFF00) == 0x00) && ((TRIG) != 0x00)) +#define IS_LVD_GET_TRIG(TRIG) (((TRIG) == LVD_TRIG_LEVEL) || \ + ((TRIG) == LVD_TRIG_FALL) || \ + ((TRIG) == LVD_TRIG_RISE)) + +/** @defgroup LVD_flags_definition + * @{ + */ +#define LVD_FLAG_FLTV ((uint16_t)0x0002) +#define LVD_FLAG_INTF ((uint16_t)0x0001) + +#define IS_LVD_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFF00) == 0x00) && ((FLAG) != 0x00)) +#define IS_LVD_GET_FLAG(FLAG) (((FLAG) == LVD_FLAG_FLTV) || \ + ((FLAG) == LVD_FLAG_INTF)) + + +/** @defgroup LVD_Action + * @{ + */ +#define LVD_Action_Irq ((uint32_t)0x00000000) +#define LVD_Action_Reset ((uint32_t)0x00000002) + +#define IS_LVD_ACTION(ACTION) (((ACTION) == LVD_Action_Irq) || \ + ((ACTION) == LVD_Action_Reset)) + +/** @defgroup LVD_Source + * @{ + */ +#define LVD_Source_VDDA ((uint32_t)0x00000000) +#define LVD_Source_PA00 ((uint32_t)0x00000004) + + +#define IS_LVD_SOURCE(SOURCE) (((SOURCE) == LVD_Source_VDDA) || \ + ((SOURCE) == LVD_Source_PA00)) + +/** @defgroup LVD_Threshold + * @{ + */ +#define LVD_Threshold_1p8V ((uint32_t)0x00000000) +#define LVD_Threshold_2p2V ((uint32_t)0x00000010) +#define LVD_Threshold_2p6V ((uint32_t)0x00000020) +#define LVD_Threshold_3p0V ((uint32_t)0x00000030) +#define LVD_Threshold_3p4V ((uint32_t)0x00000040) +#define LVD_Threshold_3p8V ((uint32_t)0x00000050) +#define LVD_Threshold_4p2V ((uint32_t)0x00000060) +#define LVD_Threshold_4p6V ((uint32_t)0x00000070) + + +#define IS_LVD_THRESHOLD(THRESHOLD) (((THRESHOLD) == LVD_Threshold_1p8V) || \ + ((THRESHOLD) == LVD_Threshold_2p2V) || \ + ((THRESHOLD) == LVD_Threshold_2p6V) || \ + ((THRESHOLD) == LVD_Threshold_3p0V) || \ + ((THRESHOLD) == LVD_Threshold_3p4V) || \ + ((THRESHOLD) == LVD_Threshold_3p8V) || \ + ((THRESHOLD) == LVD_Threshold_4p2V) || \ + ((THRESHOLD) == LVD_Threshold_4p6V)) + +/** @defgroup LVD_Filter + * @{ + */ +#define LVD_Filter_Disable ((uint32_t)0x00000000) +#define LVD_Filter_Enable ((uint32_t)0x00000001) + +#define IS_LVD_FILTER(FILTER) (((FILTER) == LVD_Filter_Disable) || \ + ((FILTER) == LVD_Filter_Enable)) + +/** @defgroup LVD_FilterClk + * @{ + */ +#define LVD_FilterClk_LSI ((uint32_t)0x00000000) +#define LVD_FilterClk_SYSCLK ((uint32_t)0x00000100) + +#define IS_LVD_FILTER_CLK(FILTER_CLK) (((FILTER_CLK) == LVD_FilterClk_LSI) || \ + ((FILTER_CLK) == LVD_FilterClk_SYSCLK)) + +/** @defgroup LVD_FilterTime + * @{ + */ +#define LVD_FilterTime_None ((uint32_t)0x00000000) +#define LVD_FilterTime_1N2 ((uint32_t)0x00000010) +#define LVD_FilterTime_1N4 ((uint32_t)0x00000020) +#define LVD_FilterTime_1N8 ((uint32_t)0x00000030) +#define LVD_FilterTime_2N6 ((uint32_t)0x00000040) +#define LVD_FilterTime_2N8 ((uint32_t)0x00000050) +#define LVD_FilterTime_4N6 ((uint32_t)0x00000060) +#define LVD_FilterTime_4N8 ((uint32_t)0x00000070) +#define LVD_FilterTime_8N6 ((uint32_t)0x00000080) +#define LVD_FilterTime_8N8 ((uint32_t)0x00000090) +#define LVD_FilterTime_16N5 ((uint32_t)0x000000A0) +#define LVD_FilterTime_16N6 ((uint32_t)0x000000B0) +#define LVD_FilterTime_16N8 ((uint32_t)0x000000C0) +#define LVD_FilterTime_32N5 ((uint32_t)0x000000D0) +#define LVD_FilterTime_32N6 ((uint32_t)0x000000E0) +#define LVD_FilterTime_32N8 ((uint32_t)0x000000F0) + +#define IS_LVD_FILTER_TIME(FILTER_TIME) (((FILTER_TIME) == LVD_FilterTime_None) || \ + ((FILTER_TIME) == LVD_FilterTime_1N2) || \ + ((FILTER_TIME) == LVD_FilterTime_1N4) || \ + ((FILTER_TIME) == LVD_FilterTime_1N8) || \ + ((FILTER_TIME) == LVD_FilterTime_2N6) || \ + ((FILTER_TIME) == LVD_FilterTime_2N8) || \ + ((FILTER_TIME) == LVD_FilterTime_4N6) || \ + ((FILTER_TIME) == LVD_FilterTime_4N8) || \ + ((FILTER_TIME) == LVD_FilterTime_8N6) || \ + ((FILTER_TIME) == LVD_FilterTime_8N8) || \ + ((FILTER_TIME) == LVD_FilterTime_16N5)|| \ + ((FILTER_TIME) == LVD_FilterTime_16N6)|| \ + ((FILTER_TIME) == LVD_FilterTime_16N8)|| \ + ((FILTER_TIME) == LVD_FilterTime_32N5)|| \ + ((FILTER_TIME) == LVD_FilterTime_32N6)|| \ + ((FILTER_TIME) == LVD_FilterTime_32N8)) + +/** + ****************************************************************************** + ** @brief LVD配置 + ** \note + ******************************************************************************/ +typedef struct +{ + uint32_t LVD_Action; // LVD触发动作 + uint32_t LVD_Source; // LVD输入电压源 + uint32_t LVD_Threshold; // LVD阈值电压 + uint32_t LVD_FilterClk; // 滤波时钟源 + uint32_t LVD_FilterTime; // 输出滤波时间 +} LVD_InitTypeDef; + +/****************************************************************************** + * Global definitions + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions ('extern') + ******************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + ******************************************************************************/ +//使能NVIC中LVD中断 +void LVD_EnableNvic(uint8_t intPriority); +//禁止NVIC中LVD中断 +void LVD_DisableNvic(void); +//配置LVD中断/系统复位触发方式 +void LVD_TrigConfig(uint16_t LVD_TRIG, FunctionalState NewState); +//使能LVD中断 +void LVD_EnableIrq(uint8_t intPriority); +//禁止LVD中断 +void LVD_DisableIrq(void); + +//清除LVD中断标志 +void LVD_ClearIrq(void); +//获取LVD中断标志 +boolean_t LVD_GetIrqStatus(void); +//获取LVD指定的状态位 +FlagStatus LVD_GetFlagStatus(uint16_t LVD_FLAG); +//获取Filter结果 +boolean_t LVD_GetFilterResult(void); + +//LVD初始化 +void LVD_Init(LVD_InitTypeDef* LVD_InitStruct); +//LVD去初始化 +void LVD_DeInit(void); + +//使能LVD +void LVD_Enable(void); +//停止LVD +void LVD_Disable(void); + +//@} // LvdGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __CW32L012_LVD_H */ +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_opa.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_opa.h new file mode 100644 index 0000000..45caa28 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_opa.h @@ -0,0 +1,267 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_OPA_H__ +#define __CW32L012_OPA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "system_cw32l012.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +/** @defgroup OPA枚举类型定义 + * @{ + */ + +/** + * @brief OPA偏置电流 + */ +typedef enum +{ + OPA_BIAS_1UA_36US = (0x00UL << OPAx_CR_BIAS_Pos), /*!< OPA 偏置电流为 1uA*/ + OPA_BIAS_2UA_20US = (0x01UL << OPAx_CR_BIAS_Pos), /*!< OPA 偏置电流为 2uA*/ + OPA_BIAS_3UA_11US = (0x02UL << OPAx_CR_BIAS_Pos), /*!< OPA 偏置电流为 3uA*/ + OPA_BIAS_4UA_10US = (0x03UL << OPAx_CR_BIAS_Pos), /*!< OPA 偏置电流为 4uA*/ + OPA_BIAS_5UA_8US = (0x04UL << OPAx_CR_BIAS_Pos), /*!< OPA 偏置电流为 5uA*/ + OPA_BIAS_6UA_7US = (0x05UL << OPAx_CR_BIAS_Pos), /*!< OPA 偏置电流为 6uA*/ + OPA_BIAS_7UA_6US = (0x06UL << OPAx_CR_BIAS_Pos), /*!< OPA 偏置电流为 7uA*/ + OPA_BIAS_8UA_4US = (0x07UL << OPAx_CR_BIAS_Pos) /*!< OPA 偏置电流为 8uA*/ +} OPA_BiasTypeDef; + +/** + * @brief OPA PGA同向放大倍数 + */ +typedef enum +{ + OPA_PGA_GAIN2 = (0x00UL << OPAx_CR_AMP_Pos), /*!< OPA PGA同向放大2倍 */ + OPA_PGA_GAIN4 = (0x01UL << OPAx_CR_AMP_Pos), /*!< OPA PGA同向放大4倍 */ + OPA_PGA_GAIN8 = (0x02UL << OPAx_CR_AMP_Pos), /*!< OPA PGA同向放大8倍 */ + OPA_PGA_GAIN16 = (0x03UL << OPAx_CR_AMP_Pos), /*!< OPA PGA同向放大16倍 */ + OPA_PGA_GAIN32 = (0x04UL << OPAx_CR_AMP_Pos) /*!< OPA PGA同向放大32倍 */ +} OPA_PgaGainTypeDef; + +/** + * @brief OPA工作模式 + */ +typedef enum +{ + OPA_WORKMODE_STANDALONE = (0x00UL << OPAx_CR_MODE_Pos), /*!< 独立运放模式，与外接电路联合工作 */ + OPA_WORKMODE_PGA = (0x02UL << OPAx_CR_MODE_Pos), /*!< PGA模式，放大系数由GAIN控制 */ + OPA_WORKMODE_FOLLOWER = (0x03UL << OPAx_CR_MODE_Pos) /*!< 内置跟随模式，输出电压等于输入电压 */ +} OPA_WorkModeTypeDef; + +/** + * @brief OPA校正时钟源 + */ +typedef enum +{ + OPA_AZCLOCK_PCLK_DIV1 = (0x00UL << OPAx_CAL_CLKDIV_Pos), /*!< Auto Zero Clk = PCLK/1 */ + OPA_AZCLOCK_PCLK_DIV2 = (0x01UL << OPAx_CAL_CLKDIV_Pos), /*!< Auto Zero Clk = PCLK/2 */ + OPA_AZCLOCK_PCLK_DIV4 = (0x02UL << OPAx_CAL_CLKDIV_Pos), /*!< Auto Zero Clk = PCLK/4 */ + OPA_AZCLOCK_PCLK_DIV8 = (0x03UL << OPAx_CAL_CLKDIV_Pos), /*!< Auto Zero Clk = PCLK/8 */ + OPA_AZCLOCK_PCLK_DIV16 = (0x04UL << OPAx_CAL_CLKDIV_Pos), /*!< Auto Zero Clk = PCLK/16 */ + OPA_AZCLOCK_PCLK_DIV32 = (0x05UL << OPAx_CAL_CLKDIV_Pos), /*!< Auto Zero Clk = PCLK/32 */ + OPA_AZCLOCK_PCLK_DIV64 = (0x06UL << OPAx_CAL_CLKDIV_Pos), /*!< Auto Zero Clk = PCLK/64 */ + OPA_AZCLOCK_PCLK_DIV128 = (0x07UL << OPAx_CAL_CLKDIV_Pos) /*!< Auto Zero Clk = PCLK/128 */ +} OPA_AutoZeroClockTypeDef; + +/** + * @brief OPA触发校正时长 + */ +typedef enum +{ + OPA_AZPERIOD_AZCLK16 = (0x00UL << OPAx_CAL_CALPERIOD_Pos), /*!< OPA 触发校正过程持续 16 个tAZCLK */ + OPA_AZPERIOD_AZCLK32 = (0x01UL << OPAx_CAL_CALPERIOD_Pos), /*!< OPA 触发校正过程持续 32 个tAZCLK */ + OPA_AZPERIOD_AZCLK64 = (0x02UL << OPAx_CAL_CALPERIOD_Pos), /*!< OPA 触发校正过程持续 64 个tAZCLK */ + OPA_AZPERIOD_AZCLK128 = (0x03UL << OPAx_CAL_CALPERIOD_Pos), /*!< OPA 触发校正过程持续 128 个tAZCLK */ + OPA_AZPERIOD_AZCLK256 = (0x04UL << OPAx_CAL_CALPERIOD_Pos), /*!< OPA 触发校正过程持续 256 个tAZCLK */ + OPA_AZPERIOD_AZCLK512 = (0x05UL << OPAx_CAL_CALPERIOD_Pos), /*!< OPA 触发校正过程持续 512 个tAZCLK */ + OPA_AZPERIOD_AZCLK1024 = (0x06UL << OPAx_CAL_CALPERIOD_Pos), /*!< OPA 触发校正过程持续 1024 个tAZCLK */ + OPA_AZPERIOD_AZCLK2048 = (0x07UL << OPAx_CAL_CALPERIOD_Pos), /*!< OPA 触发校正过程持续 2048 个tAZCLK */ + OPA_AZPERIOD_AZCLK4096 = (0x08UL << OPAx_CAL_CALPERIOD_Pos), /*!< OPA 触发校正过程持续 4096 个tAZCLK */ + OPA_AZPERIOD_AZCLK8192 = (0x09UL << OPAx_CAL_CALPERIOD_Pos), /*!< OPA 触发校正过程持续 8192 个tAZCLK */ + OPA_AZPERIOD_AZCLK16384 = (0x0AUL << OPAx_CAL_CALPERIOD_Pos), /*!< OPA 触发校正过程持续 16384 个tAZCLK */ + OPA_AZPERIOD_AZCLK32768 = (0x0BUL << OPAx_CAL_CALPERIOD_Pos), /*!< OPA 触发校正过程持续 32768 个tAZCLK */ + OPA_AZPERIOD_AZCLK65536 = (0x0CUL << OPAx_CAL_CALPERIOD_Pos), /*!< OPA 触发校正过程持续 65536 个tAZCLK */ + OPA_AZPERIOD_AZCLK131072 = (0x0DUL << OPAx_CAL_CALPERIOD_Pos), /*!< OPA 触发校正过程持续 131072个tAZCLK */ + OPA_AZPERIOD_AZCLK262144 = (0x0EUL << OPAx_CAL_CALPERIOD_Pos), /*!< OPA 触发校正过程持续 262144个tAZCLK */ + OPA_AZPERIOD_AZCLK524288 = (0x0FUL << OPAx_CAL_CALPERIOD_Pos) /*!< OPA 触发校正过程持续 524288个tAZCLK */ +} OPA_AutoZeroPeriodTypeDef; + +/** @defgroup OPA结构体类型定义 + * @{ + */ + +/** + * @brief OPA基本功能初始化结构体 + */ +typedef struct +{ + uint32_t InputP; /*!< OPA正端输入信号，可将部分参数或在一起使用，该参数可为下列之一: + @arg OPA_INPUT_NONE 正端输入信号不连接到IO + @arg OPA_INPUT_INP1 正端输入信号1连接到IO： OPA1_INP1 = PA03, OPA2_INP1 = PA04 + @arg OPA_INPUT_INP2 正端输入信号2连接到IO： OPA1_INP2 = PA06, OPA2_INP2 = PA06 + @arg OPA_INPUT_INP3 正端输入信号3连接到IO： OPA1_INP3 = PB01, OPA2_INP3 = PB00 + @arg OPA_INPUT_DAC_OUT 正端输入信号连接到DACOUT: OPA1_INP4 = DAC1_OUTICT, OPA2_INP4 = DAC2_OUTICT */ + uint32_t InputN; /*!< OPA负端输入信号，可将部分参数或在一起使用，该参数可为下列之一: + @arg OPA_INPUT_NONE 负端输入信号不连接到IO + @arg OPA_INPUT_INN1 负端输入信号1连接到IO： OPA1_INN1 = PA04, OPA2_INN1 = PA05 + @arg OPA_INPUT_INN2 负端输入信号2连接到IO： OPA1_INN2 = PA07, OPA2_INN2 = PA07 */ + OPA_BiasTypeDef Bias; /*!< 偏置电流配置 */ + OPA_PgaGainTypeDef PgaGain; /*!< PGA同相放大倍数 */ + OPA_WorkModeTypeDef WorkMode; /*!< OPA工作模式，独立运放模式/内置PGA模式/内置跟随器模式 */ +} OPA_InitTypeDef; +//============================================================ +/** @addtogroup OPA1输入输出管脚 + * @{ + */ +#define AFx_OPA1INP1_PA03() (CW_GPIOA->ANALOG_f.PIN3 = 1U) +#define AFx_OPA1INP2_PA06() (CW_GPIOA->ANALOG_f.PIN6 = 1U) +#define AFx_OPA1INP3_PB01() (CW_GPIOB->ANALOG_f.PIN1 = 1U) +#define AFx_OPA1INN1_PA04() (CW_GPIOA->ANALOG_f.PIN4 = 1U) +#define AFx_OPA1INN2_PA07() (CW_GPIOA->ANALOG_f.PIN7 = 1U) +#define AFx_OPA1OUT_PB00() (CW_GPIOB->ANALOG_f.PIN0 = 1U) +/** @} */ + +/** @addtogroup OPA2输入输出管脚 + * @{ + */ +#define AFx_OPA2INP1_PA04() (CW_GPIOA->ANALOG_f.PIN4 = 1U) +#define AFx_OPA2INP2_PA06() (CW_GPIOA->ANALOG_f.PIN6 = 1U) +#define AFx_OPA2INP3_PB00() (CW_GPIOB->ANALOG_f.PIN0 = 1U) +#define AFx_OPA2INN1_PA05() (CW_GPIOA->ANALOG_f.PIN5 = 1U) +#define AFx_OPA2INN2_PA07() (CW_GPIOA->ANALOG_f.PIN7 = 1U) +#define AFx_OPA2OUT_PB01() (CW_GPIOB->ANALOG_f.PIN1 = 1U) +/** @} */ + +/** @addtogroup OPA端口输入信号使能控制 + * @{ + */ +#define OPA_INPUT_NONE 0 +#define OPA_INPUT_INP1 OPAx_CR_INP1EN_Msk /*!< 正端输入信号1连接到IO使能控制 */ + /*!< - OPA1_INPUT_INP1 = PA03 */ + /*!< - OPA2_INPUT_INP1 = PA04 */ +#define OPA_INPUT_INP2 OPAx_CR_INP2EN_Msk /*!< 正端输入信号2连接到IO使能控制 */ + /*!< - OPA1_INPUT_INP2 = PA06 */ + /*!< - OPA2_INPUT_INP2 = PA06 */ +#define OPA_INPUT_INP3 OPAx_CR_INP3EN_Msk /*!< 正端输入信号3连接到IO使能控制 */ + /*!< - OPA1_INPUT_INP3 = PB01 */ + /*!< - OPA2_INPUT_INP3 = PB00 */ +#define OPA_INPUT_DAC_OUT OPAx_CR_INP4EN_Msk /*!< 正端输入信号4连接到内部DAC使能控制 */ + /*!< - OPA1_INPUT_INP4 = DAC1_OUTICT */ + /*!< - OPA2_INPUT_INP4 = DAC2_OUTICT */ + +#define OPA_INPUT_INN1 OPAx_CR_INN1EN_Msk /*!< 负端输入信号1连接到IO使能控制 */ + /*!< - OPA1_INN1 = PA04 */ + /*!< - OPA2_INN1 = PA05 */ +#define OPA_INPUT_INN2 OPAx_CR_INN2EN_Msk /*!< 负端输入信号2连接到IO使能控制 */ + /*!< - OPA1_INN2 = PA07 */ + /*!< - OPA2_INN2 = PA07 */ +/** @} */ + +#define OPA_CR0_RESET_VALUE 0x0000E000 +#define OPA_INP_MASK (OPA_INPUT_INP1 | OPA_INPUT_INP2 | OPA_INPUT_INP3 | OPA_INPUT_DAC_OUT) +#define OPA_INN_MASK (OPA_INPUT_INN1 | OPA_INPUT_INN2) + +/** @addtogroup OPA软件触发校正的触发源 + */ +#define OPA_AZTRIGSRC_NONE (0x00000000UL) /*!< 无校正触发源 */ +#define OPA_AZTRIGSRC_SOFT OPAx_CAL_SOFTTRIG_Msk /*!< 使用软件触发校正 */ +#define OPA_AZTRIGSRC_ADC1START OPAx_CAL_ADC1START1_Msk /*!< 使用ADC1START信号触发校正 */ +#define OPA_AZTRIGSRC_ADC2START OPAx_CAL_ADC2START1_Msk /*!< 使用ADC2START信号触发校正 */ +#define OPA_AZTRIGSRC_ATIMTRGO OPAx_CAL_ATIMTRGO_Msk /*!< 使用ATIMTRGO信号触发校正 */ +#define OPA_AZTRIGSRC_ATIMOC4REFC OPAx_CAL_ATIMOC4REFC_Msk /*!< 使用ATIMOC4REFC信号触发校正 */ +#define OPA_AZTRIGSRC_ATIMOC5REFC OPAx_CAL_ATIMOC5REFC_Msk /*!< 使用ATIMOC5REFC信号触发校正 */ +#define OPA_AZTRIGSRC_ATIMOC6REFC OPAx_CAL_ATIMOC6REFC_Msk /*!< 使用ATIMOC6REFC信号触发校正 */ +#define OPA_AZTRIGSRC_GTIM1TRGO OPAx_CAL_GTIM1TRGO_Msk /*!< 使用GTIM1TRGO信号触发校正 */ +#define OPA_AZTRIGSRC_GTIM1OC1REFC OPAx_CAL_GTIM1OC1REFC_Msk /*!< 使用GTIM1OC1REFC信号触发校正 */ +#define OPA_AZTRIGSRC_GTIM1OC2REFC OPAx_CAL_GTIM1OC2REFC_Msk /*!< 使用GTIM1OC2REFC信号触发校正 */ +#define OPA_AZTRIGSRC_GTIM2TRGO OPAx_CAL_GTIM2TRGO_Msk /*!< 使用GTIM2TRGO信号触发校正 */ +#define OPA_AZTRIGSRC_GTIM2OC1REFC OPAx_CAL_GTIM2OC1REFC_Msk /*!< 使用GTIM2OC1REFC信号触发校正 */ +#define OPA_AZTRIGSRC_GTIM2OC2REFC OPAx_CAL_GTIM2OC2REFC_Msk /*!< 使用GTIM2OC2REFC信号触发校正 */ +#define OPA_AZTRIGSRC_GTIM3TRGO OPAx_CAL_GTIM3TRGO_Msk /*!< 使用GTIM3TRGO信号触发校正 */ +#define OPA_AZTRIGSRC_GTIM3OC1REFC OPAx_CAL_GTIM3OC1REFC_Msk /*!< 使用GTIM3OC1REFC信号触发校正 */ +#define OPA_AZTRIGSRC_GTIM3OC2REFC OPAx_CAL_GTIM3OC2REFC_Msk /*!< 使用GTIM3OC2REFC信号触发校正 */ +#define OPA_AZTRIGSRC_GTIM4TRGO OPAx_CAL_GTIM4TRGO_Msk /*!< 使用GTIM4TRGO信号触发校正 */ +#define OPA_AZTRIGSRC_GTIM4OC1REFC OPAx_CAL_GTIM4OC1REFC_Msk /*!< 使用GTIM4OC1REFC信号触发校正 */ +#define OPA_AZTRIGSRC_GTIM4OC2REFC OPAx_CAL_GTIM4OC2REFC_Msk /*!< 使用GTIM4OC2REFC信号触发校正 */ +#define OPA_AZTRIGSRC_ALLHARD 0xFFFFC000; /*!< 使用所有硬件触发源校正 */ + +//============================================================ + +/******************************************************************************/ +/* Global macro function */ +/******************************************************************************/ +/** @defgroup OPA宏函数定义 + * @{ + */ + +/** + * @brief 等待OPA校正完成 + * @param __INSTANCE__ OPA实体 + * @retval None + */ +#define OPA_WAIT_BUSY(__INSTANCE__) while (((__INSTANCE__)->CAL & OPAx_CAL_AZRUN_Msk) != 0) + +/** + * @brief 创建OPA软件触发校正事件 + * @param __INSTANCE__ OPA实体 + * @retval None + */ +#define OPA_AUTOZEROTRIG_SOFTEVENT(__INSTANCE__) \ +do { \ + REGBITS_SET((__INSTANCE__)->CAL, OPAx_CAL_SOFTTRIG_Msk); \ + OPA_WAIT_BUSY(__INSTANCE__); \ +} while (0) +/** @} */ + + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ +/** @defgroup OPA驱动函数原型 + * @{ + */ + +void OPA_Init(OPA_TypeDef *OPAx, OPA_InitTypeDef *OPA_InitStruct); +void OPA_DeInit(OPA_TypeDef *OPAx); +void OPA_Start(OPA_TypeDef *OPAx); +void OPA_Stop(OPA_TypeDef *OPAx); + +void OPA_AutoZeroSoft_Start(OPA_TypeDef *OPAx); +void OPA_AutoZeroSoft_Stop(OPA_TypeDef *OPAx); + +void OPA_AutoZeroTrig_Config(OPA_TypeDef *OPAx, + OPA_AutoZeroClockTypeDef AutoZeroClk, + OPA_AutoZeroPeriodTypeDef AutoZeroPeriod, + uint32_t AutoZeroTrigSrc); +void OPA_AutoZeroTrig_SoftEvent(OPA_TypeDef *OPAx); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_pwr.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_pwr.h new file mode 100644 index 0000000..4de27ba --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_pwr.h @@ -0,0 +1,120 @@ +/** + * @file cw32l012_pwr.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +#ifndef __CW32L012_PWR_H +#define __CW32L012_PWR_H + +/***************************************************************************** + * Include files + *****************************************************************************/ +#include "base_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup LpmGroup Low Power Management (LPM) + ** + ** + ******************************************************************************/ +//@{ + +/****************************************************************************** + ** Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** @defgroup PWR_Sevonpend + * @{ + */ +#define PWR_Sevonpend_Disable ((uint32_t)0x00000000) +#define PWR_Sevonpend_Enable ((uint32_t)0x00000010) + +#define IS_PWR_SEVONPEND(SEVONPEND) (((SEVONPEND) == PWR_Sevonpend_Disable) || \ + ((SEVONPEND) == PWR_Sevonpend_Enable)) + +/** @defgroup PWR_SleepDeep + * @{ + */ +#define PWR_SleepDeep_Disable ((uint32_t)0x00000000) +#define PWR_SleepDeep_Enable ((uint32_t)0x00000004) + +#define IS_PWR_SLEEPDEEP(SLEEPDEEP) (((SLEEPDEEP) == PWR_SleepDeep_Disable) || \ + ((SLEEPDEEP) == PWR_SleepDeep_Enable)) + +/** @defgroup PWR_SleepOnExit + * @{ + */ +#define PWR_SleepOnExit_Disable ((uint32_t)0x00000000) +#define PWR_SleepOnExit_Enable ((uint32_t)0x00000002) + +#define IS_PWR_SLEEPONEXIT(SLEEPONEXIT) (((SLEEPONEXIT) == PWR_SleepOnExit_Disable) || \ + ((SLEEPONEXIT) == PWR_SleepOnExit_Enable)) + +/** + ****************************************************************************** + ** @brief Low Power Mode 配置结构体定义 + *****************************************************************************/ +typedef struct +{ + uint32_t PWR_Sevonpend; // 使能:每次新中断会产生一个事件,如果使用WFE休眠,则可用于唤醒处理器. + uint32_t PWR_SleepDeep; // 使能:执行WFI进入深度休眠;不使能:执行WFI进入休眠. + uint32_t PWR_SleepOnExit; // 使能:退出异常处理并返回时,处理器自动进入休眠模式;不使能:该特性禁止. +} PWR_InitTypeDef; + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + *****************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + *****************************************************************************/ +//功能配置及操作函数 +//低功耗模式配置 +void PWR_Config(PWR_InitTypeDef* PWR_InitStruct); +//进入低功耗模式 +void PWR_GotoLpmMode(void); + +//@} // PWRGroup + +#ifdef __cplusplus +} +#endif + + +#endif /* __CW32L012_PWR_H */ +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_ram.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_ram.h new file mode 100644 index 0000000..86abc0e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_ram.h @@ -0,0 +1,71 @@ +/** + * @file cw32l012_ram.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_RAM_H__ +#define __CW32L012_RAM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "system_cw32l012.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +//============================================================ + +/** @defgroup 中断标志位 + * @{ + */ +#define RAM_IT_PARITY (bv0) +#define IS_RAM_IT(IT) ((IT)==RAM_IT_PARITY) +#define IS_RAM_GET_IT(IT) ((IT) == RAM_IT_PARITY) + +//============================================================ + +//RAM PARITY中断使能配置 +void RAM_ITConfig(uint32_t RAM_IT, FunctionalState NewState); +//获取RAM PARITY中断标志位 +ITStatus RAM_GetITStatus(uint32_t RAM_IT); +//清除RAM PARITY断标志位 +void RAM_ClearITPendingBit(uint32_t RAM_IT); +//获取发生奇偶校验错的RAM地址// +uint32_t RAM_GetErrorAddress(void); + +//============================================================ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_rtc.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_rtc.h new file mode 100644 index 0000000..66871dd --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_rtc.h @@ -0,0 +1,490 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_RTC_H +#define __CW32L012_RTC_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32l012.h" + + +typedef struct +{ + uint8_t Day; + uint8_t Month; + uint8_t Year; + uint8_t Week; +} RTC_DateTypeDef; + +typedef struct +{ + uint8_t Second; + uint8_t Minute; + uint8_t Hour; + uint8_t AMPM; // RTC_AM (0), RTC_PM(1) + uint8_t H24; //RTC_HOUR24(1),RTC_HOUR12(0) +} RTC_TimeTypeDef; + +typedef struct +{ + uint32_t RTC_ClockSource; + RTC_TimeTypeDef TimeStruct; + RTC_DateTypeDef DateStruct; + +} RTC_InitTypeDef; + + +typedef struct +{ + RTC_TimeTypeDef RTC_AlarmTime; + uint32_t RTC_AlarmMask; /*!< @ref RTC_AlarmMask_Definitions */ +} RTC_AlarmTypeDef; + +typedef struct +{ + uint8_t AWT_ClockSource; + uint16_t AWT_ARRValue; +} RTC_AWTTypeDef; + +typedef struct +{ + uint32_t Freq; + uint32_t Sign; + uint32_t Step; + uint32_t CompensationValue; +} RTC_CalibTypeDef; + +#define RTC_Alarm_A ((uint32_t)0x00000200) +#define RTC_Alarm_B ((uint32_t)0x00000400) +#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) +#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) + +/** @defgroup RTC_ACCESS_TIMEOUT +* @{ +* RTC寄存器访问最大次数，RTC_CR1->WINDOW位未检测到1，判定访问RTC寄存器失败 +*/ +#define RTC_ACCESS_MAXTIMES ((uint32_t)200U) + +/** @defgroup RTC_RTC1HZ_source +* @{ +*/ +#define RTC_RTC1HZ_NONE (0UL) +#define RTC_RTC1HZ_FROM_LSE (1UL << 5) +#define RTC_RTC1HZ_FROM_PCLK (3UL << 5) + +#define IS_RTC_RTC1HZ_SOURCE(src) (((src) == RTC_RTC1HZ_NONE) || \ + ((src) == RTC_RTC1HZ_FROM_PCLK) || \ + ((src) == RTC_RTC1HZ_FROM_LSE)) + +#define RTC_HOUR24 (1UL) +#define RTC_HOUR12 (0UL) +#define IS_RTC_HOUR_FORMAT(fmt) (((fmt) == RTC_HOUR24) || ((fmt) == RTC_HOUR12)) +#define IS_RTC_HOUR12_FORMAT(fmt) ((fmt) == RTC_HOUR12) + + +/** @defgroup RTC_Interval_Value + * @{ + */ + +#define RTC_INTERVAL_NONE (0X00) +#define RTC_INTERVAL_EVERY_0_5S (0x01) +#define RTC_INTERVAL_EVERY_1S (0x02) +#define RTC_INTERVAL_EVERY_1M (0x03) +#define RTC_INTERVAL_EVERY_1H (0x04) +#define RTC_INTERVAL_EVERY_1D (0x05) +#define RTC_INTERVAL_EVERY_1MO (0x06) + +#define IS_RTC_INTERVAL_PERIOD(per) (per < 7) + +/** @defgroup RTC_Clock_source + * 000：外部晶体时钟LSE + * 010：内置低频时钟LSI + * 001：外部晶体时钟HSE + * 011：内部高速时钟HSIOSC + * @{ + */ + +#define RTC_RTCCLK_FROM_LSE (0UL) +#define RTC_RTCCLK_FROM_HSE (1UL << 8) +#define RTC_RTCCLK_FROM_LSI (2UL << 8) +#define RTC_RTCCLK_FROM_HSIOSC (3UL << 8) + + +#define IS_RTC_RTCCLK_SOURCE(src) (((src) == RTC_RTCCLK_FROM_LSE) || \ + ((src) == RTC_RTCCLK_FROM_HSE) || \ + ((src) == RTC_RTCCLK_FROM_LSI) || \ + ((src) == RTC_RTCCLK_FROM_HSIOSC)) + +#define RTC_IT_INTERVAL (1UL << 6) +#define RTC_IT_TAMPOV (1UL << 4) +#define RTC_IT_TAMP (1UL << 3) +#define RTC_IT_AWTIMER (1UL << 2) +#define RTC_IT_ALARMB (1UL << 1) +#define RTC_IT_ALARMA (1UL) +#define RTC_IT_ALL (RTC_IT_ALARMA|RTC_IT_ALARMB|RTC_IT_AWTIMER|RTC_IT_TAMP|RTC_IT_TAMPOV|RTC_IT_INTERVAL) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_INTERVAL) || \ + ((IT) == RTC_IT_TAMPOV) || \ + ((IT) == RTC_IT_TAMP) || \ + ((IT) == RTC_IT_AWTIMER) || \ + ((IT) == RTC_IT_ALARMB) || \ + ((IT) == RTC_IT_ALARMA) || \ + ((IT) == RTC_IT_ALL )) +#define IS_RTC_CONFIG_IT(IT) ((((uint8_t)(IT) & 0x20) == 0) && \ + ((uint8_t)(IT) < 0x40)) +#define IS_RTC_CLAER_IT(IT) ((((uint8_t)(IT) & 0x20) == 0) && \ + ((uint8_t)(IT) < 0x40)) + +/** @defgroup RTC_AlarmMask_Definitions + * @{ + */ +#define RTC_AlarmMask_None ((uint32_t)0x00000000) +#define RTC_AlarmMask_WeekSAT ((uint32_t)0x40000000) +#define RTC_AlarmMask_WeekFRI ((uint32_t)0x20000000) +#define RTC_AlarmMask_WeekTHU ((uint32_t)0x10000000) +#define RTC_AlarmMask_WeekWED ((uint32_t)0x08000000) +#define RTC_AlarmMask_WeekTUE ((uint32_t)0x04000000) +#define RTC_AlarmMask_WeekMON ((uint32_t)0x02000000) +#define RTC_AlarmMask_WeekSun ((uint32_t)0x01000000) +#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) +#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) +#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) +#define RTC_AlarmMask_All ((uint32_t)0x7F808080) +#define IS_ALARM_MASK(MASK) (((MASK) & 0x807F7F7F) == (uint32_t)RESET) + + +#define RTC_TamperTrigger_RisingEdge (0UL) +#define RTC_TamperTrigger_FallingEdge (1UL) +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_FallingEdge)) + + +/** @defgroup RTC_Compen_step + * @{ + */ +#define RTC_RTCOUT_AS_LOW (0x0) +#define RTC_RTCOUT_AS_ALARM_A (0x1) +#define RTC_RTCOUT_AS_ALARM_B (0x2) +#define RTC_RTCOUT_AS_AWT (0x3) + +#define IS_RTC_RTCOUT_SOURCE(src) (src < 4) + +/** @defgroup RTC_TimerSrc_Value +* @{ +*/ + +#define RTC_AWTSOURCE_FROM_RTCCLK_2 (0x0) +#define RTC_AWTSOURCE_FROM_RTCCLK_4 (0x1) +#define RTC_AWTSOURCE_FROM_RTCCLK_8 (0x2) +#define RTC_AWTSOURCE_FROM_RTCCLK_16 (0x3) +#define RTC_AWTSOURCE_FROM_RTC1HZ_1 (0x4) +#define RTC_AWTSOURCE_FROM_RTC1HZ_2 (0x5) +#define RTC_AWTSOURCE_FROM_RTC1HZ_4 (0x6) +#define RTC_AWTSOURCE_FROM_RTC1HZ_8 (0x7) + +#define IS_RTC_AWTTIMER_SOURCE(clk) (clk < 8) + +/** @defgroup RTC_Compen_Freq + * @{ + */ +#define RTC_COMPENFREQ_AS_4MHZ (0x0UL) +#define RTC_COMPENFREQ_AS_6MHZ (0x1UL) +#define RTC_COMPENFREQ_AS_8MHZ (0x2UL) +#define RTC_COMPENFREQ_AS_12MHZ (0x3UL) +#define RTC_COMPENFREQ_AS_16MHZ (0x4UL) +#define RTC_COMPENFREQ_AS_20MHZ (0x5UL) +#define RTC_COMPENFREQ_AS_24MHZ (0x6UL) +#define RTC_COMPENFREQ_AS_30MHZ (0x7UL) +#define RTC_COMPENFREQ_AS_48MHZ (0x8UL) + +#define IS_RTC_COMPEN_FREQ(clk) (clk < 9) + +/** @defgroup RTC_Compen_step + * @{ + */ +#define RTC_COMPENSTEP_0_950PPM (0x0UL) +#define RTC_COMPENSTEP_0_238PPM (0x1UL) +#define RTC_COMPENSTEP_0_119PPM (0x2UL) + +#define IS_RTC_COMPEN_STEP(stp) ((stp) < 3) + +#define RTC_COMPEN_SIGN_UP (0UL) +#define RTC_COMPEN_SIGN_DOWN (1UL) +#define IS_RTC_COMPEN_SIGN(SIGN) ((SIGN) < 2) + +#define IS_RTC_COMPEN_VALUE(VAL) (((VAL) & 0xFFFFF000) == RESET) + +/** @defgroup RTC_Month_Day_Definitions + * @{ + */ +#define RTC_Month_January ((uint8_t)0x01) +#define RTC_Month_February ((uint8_t)0x02) +#define RTC_Month_March ((uint8_t)0x03) +#define RTC_Month_April ((uint8_t)0x04) +#define RTC_Month_May ((uint8_t)0x05) +#define RTC_Month_June ((uint8_t)0x06) +#define RTC_Month_July ((uint8_t)0x07) +#define RTC_Month_August ((uint8_t)0x08) +#define RTC_Month_September ((uint8_t)0x09) +#define RTC_Month_October ((uint8_t)0x10) +#define RTC_Month_November ((uint8_t)0x11) +#define RTC_Month_December ((uint8_t)0x12) +#define IS_RTC_MONTH(MON) (((MON) >= 1) && ((MON) <= 12)) +#define IS_RTC_DAY(DAY) (((DAY) >= 1) && ((DAY) <= 31)) + +/** @defgroup RTC_WeekDay_Definitions +* @{ +*/ + +#define RTC_Weekday_Sunday ((uint8_t)0x00) +#define RTC_Weekday_Monday ((uint8_t)0x01) +#define RTC_Weekday_Tuesday ((uint8_t)0x02) +#define RTC_Weekday_Wednesday ((uint8_t)0x03) +#define RTC_Weekday_Thursday ((uint8_t)0x04) +#define RTC_Weekday_Friday ((uint8_t)0x05) +#define RTC_Weekday_Saturday ((uint8_t)0x06) + +#define IS_RTC_WEEKDAY(wek) (wek < 7) + +/** @defgroup RTC_Alarm_Definitions + * @{ + */ +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(dat) (((dat) > 0) && ((dat) <= 31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(wek) (((wek) == RTC_Weekday_Monday) || \ + ((wek) == RTC_Weekday_Tuesday) || \ + ((wek) == RTC_Weekday_Wednesday) || \ + ((wek) == RTC_Weekday_Thursday) || \ + ((wek) == RTC_Weekday_Friday) || \ + ((wek) == RTC_Weekday_Saturday) || \ + ((wek) == RTC_Weekday_Sunday)) + +/** @defgroup RTC_Time_Definitions + * @{ + */ +#define IS_RTC_HOUR12(hor) (((hor) >= 1) && ((hor) <= 12)) +#define IS_RTC_HOUR24(hor) ((hor) <= 23) +#define IS_RTC_MINUTES(min) ((min) <= 59) +#define IS_RTC_SECONDS(sec) ((sec) <= 59) + +/** @defgroup RTC_AM_PM_Definitions + * @{ + */ +#define RTC_H12_AM (0UL) +#define RTC_H12_PM (1UL) +#define IS_RTC_H12_AMPM(apm) (((apm) == RTC_H12_AM) || ((apm) == RTC_H12_PM)) + +/** @defgroup RTC_Year_Date_Definitions + * @{ + */ +#define IS_RTC_YEAR(yer) ((yer) <= 99) + +/** @defgroup RTC_KEY_WORD + * @{ + */ +#define RTC_KEY_WORD1 ((uint8_t)0xCA) +#define RTC_KEY_WORD2 ((uint8_t)0x53) + +#define RTC_KEY_LOCKW ((uint8_t)0x55) + +#define IS_RTC_KEYWORD(kwd) (((kwd) == RTC_KEY_WORD1) || ((kwd) == RTC_KEY_WORD2)) + +#define RTC_UNLOCK() do{ CW_RTC->KEY_f.KEY = RTC_KEY_WORD1;\ + CW_RTC->KEY_f.KEY = RTC_KEY_WORD2; }while (0) +#define RTC_LOCK() do{ CW_RTC->KEY_f.KEY = RTC_KEY_LOCKW; \ + CW_RTC->KEY_f.KEY = RTC_KEY_LOCKW;}while (0) + + +/** + * @} + */ +#define RTC_DATE_RESET_VALUE ((uint32_t) 0x00000000) +#define RTC_TIME_RESET_VALUE ((uint32_t) 0x12000000) +#define RTC_ALARMA_RESET_VALUE ((uint32_t) 0x12000000) +#define RTC_ALARMB_RESET_VALUE ((uint32_t) 0x12000000) +#define RTC_TAMPDATA_RESET_VALUE ((uint32_t) 0x00000000) +#define RTC_TAMPTIME_RESET_VALUE ((uint32_t) 0x00000000) +#define RTC_AWTARR_RESET_VALUE ((uint32_t) 0x0000FFFF) +#define RTC_IER_RESET_VALUE ((uint32_t) 0x00000000) + + +//============================================================ + +//RTC CONTROLLER REGSITER0 +#define RTC_START_ENABLE() (CW_RTC->CR0_f.START = 1) +#define RTC_START_DISABLE() (CW_RTC->CR0_f.START = 0) + +#define RTC_RTC1HZ_PCLK() (CW_RTC->CR0_f.RTC1HZ = RTC_RTC1HZ_FROM_PCLK) +#define RTC_RTC1HZ_LSE() (CW_RTC->CR0_f.RTC1HZ = RTC_RTC1HZ_FROM_LSE) + +#define RTC_AMPM_12HOUR() (CW_RTC->CR0_f.AMPM = 0) +#define RTC_AMPM_24HOUR() (CW_RTC->CR0_f.AMPM = 1) + +#define RTC_INTERVAL_0_5S() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_0_5S) +#define RTC_INTERVAL_1S() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_1S) +#define RTC_INTERVAL_1M() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_1M) +#define RTC_INTERVAL_1H() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_1H) +#define RTC_INTERVAL_1D() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_1D) +#define RTC_INTERVAL_1MO() (CW_RTC->CR0_f.INTERVAL = RTC_INTERVAL_EVERY_1MO) + +#define IS_RTC_START() (CW_RTC->CR0 & bv7) + +//============================================================ +//RTC CONTROLLER REGSITER1 +#define RTC_RTCCLK_LSE() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_LSE) +#define RTC_RTCCLK_LSI() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_LIE) +#define RTC_RTCCLK_HEX128() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_HEX_128) +#define RTC_RTCCLK_HEX256() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_HEX_256) +#define RTC_RTCCLK_HEX512() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_HEX_512) +#define RTC_RTCCLK_HEX1024() (CW_RTC->CR1_f.SOURCE = RTC_RTCCLK_FROM_HEX_1024) + +#define RTC_WINDOW_GETVALUE() (CW_RTC->CR1_f.WINDOW) +#define RTC_ACCESS_GETVALUE() (CW_RTC->CR1_f.ACCESS) +#define RTC_ACCESS_SET() (CW_RTC->CR1_f.ACCESS = 1) +#define RTC_ACCESS_RESET() (CW_RTC->CR1_f.ACCESS = 0) + +//============================================================ +//RTC CONTROLLER REGSITER2 +#define RTC_ALARM_A_ENABLE() (CW_RTC->CR2_f.ALARMAEN = 1) +#define RTC_ALARM_A_DISABLE() (CW_RTC->CR2_f.ALARMAEN = 0) + +#define RTC_ALARM_B_ENABLE() (CW_RTC->CR2_f.ALARMBEN = 1) +#define RTC_ALARM_B_DISABLE() (CW_RTC->CR2_f.ALARMBEN = 0) + +#define RTC_AWT_ENABLE() (CW_RTC->CR2_f.AWTEN = 1) +#define RTC_AWT_DISABLE() (CW_RTC->CR2_f.AWTEN = 0) + +#define RTC_TAMP_ENABLE() (CW_RTC->CR2_f.TAMPEN = 1) +#define RTC_TAMP_DISABLE() (CW_RTC->CR2_f.TAMPEN = 0) + +#define RTC_RTCOUT_LOW() (CW_RTC->CR2_f.RTCOUT = RTC_RTCOUT_AS_LOW) +#define RTC_RTCOUT_ALARM_A() (CW_RTC->CR2_f.RTCOUT = RTC_RTCOUT_AS_ALARM_A) +#define RTC_RTCOUT_ALARM_B() (CW_RTC->CR2_f.RTCOUT = RTC_RTCOUT_AS_ALARM_B) +#define RTC_RTCOUT_AWT() (CW_RTC->CR2_f.RTCOUT = RTC_RTCOUT_AS_AWT) + +#define RTC_TAMPEDGE_FALL() (CW_RTC->CR2_f.TAMPEDGE = 1) +#define RTC_TAMPEDGE_RISE() (CW_RTC->CR2_f.TAMPEDGE = 0) + +#define RTC_AWTSOURCE_RTCLK_2() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTCCLK_2) +#define RTC_AWTSOURCE_RTCLK_4() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTCCLK_4) +#define RTC_AWTSOURCE_RTCLK_8() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTCCLK_8) +#define RTC_AWTSOURCE_RTCLK_16() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTCCLK_16) +#define RTC_AWTSOURCE_RTC1HZ_1() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTC1HZ_1) +#define RTC_AWTSOURCE_RTC1HZ_2() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTC1HZ_2) +#define RTC_AWTSOURCE_RTC1HZ_4() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTC1HZ_4) +#define RTC_AWTSOURCE_RTC1HZ_8() (CW_RTC->CR2_f.TIMERSRC = RTC_AWTSOURCE_FROM_RTC1HZ_8) + +//============================================================ +//RTC COMPEN REGSITER +#define RTC_COMPEN_ENABLE() (CW_RTC->COMPEN_f.EN = 1) +#define RTC_COMPEN_DISABLE() (CW_RTC->COMPEN_f.EN = 0) + +#define RTC_COMPEN_STEP_0_950PPM() (CW_RTC->COMPEN_f.STEP = RTC_COMPENSTEP_0_950PPM) +#define RTC_COMPEN_STEP_0_238PPM() (CW_RTC->COMPEN_f.STEP = RTC_COMPENSTEP_0_238PPM) +#define RTC_COMPEN_STEP_0_119PPM() (CW_RTC->COMPEN_f.STEP = RTC_COMPENSTEP_0_119PPM) + +//============================================================ +//RTC ALARM A CONTROLLER REGSITER +#define RTC_ALARMA_HOURMASK_ENABLE() (CW_RTC->ALARMA_f.HOURMASK = 1) +#define RTC_ALARMA_HOURMASK_DISABLE() (CW_RTC->ALARMA_f.HOURMASK = 0) + +#define RTC_ALARMA_MINUTEMASK_ENABLE() (CW_RTC->ALARMA_f.MINUTEMASK = 1) +#define RTC_ALARMA_MINUTEMASK_DISABLE() (CW_RTC->ALARMA_f.MINUTEMASK = 0) + +#define RTC_ALARMA_SECONDMASK_ENABLE() (CW_RTC->ALARMA_f.SECONDMASK = 1) +#define RTC_ALARMA_SECONDMASK_DISABLE() (CW_RTC->ALARMA_f.SECONDMASK = 0) + +//============================================================ +//RTC ALARM B CONTROLLER REGSITER +#define RTC_ALARMB_HOURMASK_ENABLE() (CW_RTC->ALARMB_f.HOURMASK = 1) +#define RTC_ALARMB_HOURMASK_DISABLE() (CW_RTC->ALARMB_f.HOURMASK = 0) + +#define RTC_ALARMB_MINUTEMASK_ENABLE() (CW_RTC->ALARMB_f.MINUTEMASK = 1) +#define RTC_ALARMB_MINUTEMASK_DISABLE() (CW_RTC->ALARMB_f.MINUTEMASK = 0) + +#define RTC_ALARMB_SECONDMASK_ENABLE() (CW_RTC->ALARMB_f.SECONDMASK = 1) +#define RTC_ALARMB_SECONDMASK_DISABLE() (CW_RTC->ALARMB_f.SECONDMASK = 0) + +//============================================================ +//RTC INTERRUPT ENABLE REGSITER +#define RTC_IE_INTERVAL_ENABLE() (CW_RTC->IER_f.INTERVAL = 1) +#define RTC_IE_INTERVAL_DISABLE() (CW_RTC->IER_f.INTERVAL = 0) + +#define RTC_IE_TAMPOV_ENABLE() (CW_RTC->IER_f.TAMPOV = 1) +#define RTC_IE_TAMPOV_DISABLE() (CW_RTC->IER_f.TAMPOV = 0) + +#define RTC_IE_TAMP_ENABLE() (CW_RTC->IER_f.TAMP = 1) +#define RTC_IE_TAMP_DISABLE() (CW_RTC->IER_f.TAMP = 0) + +#define RTC_IE_AWTIMER_ENABLE() (CW_RTC->IER_f.AWTIMER = 1) +#define RTC_IE_AWTIMER_DISABLE() (CW_RTC->IER_f.AWTIMER = 0) + +#define RTC_IE_ALARMA_ENABLE() (CW_RTC->IER_f.ALARMA = 1) +#define RTC_IE_ALARMA_DISABLE() (CW_RTC->IER_f.ALARMA = 0) + +#define RTC_IE_ALARMB_ENABLE() (CW_RTC->IER_f.ALARMB = 1) +#define RTC_IE_ALARMB_DISABLE() (CW_RTC->IER_f.ALARMB = 0) + +//============================================================ +//RTC INTERRUPT CLEAR REGSITER +#define RTC_IE_INTERVAL_CLEAR() (CW_RTC->ICR_f.INTERVAL = 0) +#define RTC_IE_TAMPOV_CLEAR() (CW_RTC->ICR_f.TAMPOV = 0) +#define RTC_IE_TAMP_CLEAR() (CW_RTC->ICR_f.TAMP = 0) +#define RTC_IE_AWTIMER_CLEAR() (CW_RTC->ICR_f.AWTIMER = 0) +#define RTC_IE_ALARMA_CLEAR() (CW_RTC->ICR_f.ALARMA = 0) +#define RTC_IE_ALARMB_CLEAR() (CW_RTC->ICR_f.ALARMB = 0) + +//============================================================ +// cw32l012 RTC HAL API Function（Total： 14），及所有位域的宏命令 +//============================================================ +void RTC_DeInit(void); +ErrorStatus RTC_Init(RTC_InitTypeDef *RTC_InitStruct); +void RTC_Cmd(FunctionalState NewState); +ITStatus RTC_GetITState(uint32_t RTC_ITState); +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); +void RTC_ClearITPendingBit(uint32_t RTC_IT); +void RTC_SetTime(RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_SetDate(RTC_DateTypeDef *RTC_Date); +void RTC_GetTime(RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_GetDate(RTC_DateTypeDef *RTC_Date); +void RTC_SetAlarm(uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_GetAlarm(uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); +void RTC_TamperTriggerConfig(uint32_t RTC_TamperTrigger); +void RTC_TamperCmd(FunctionalState NewState); +void RTC_GetTamperDate(RTC_DateTypeDef *RTC_Date); +void RTC_GetTamperTime(RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_OutputConfig(uint8_t RTC_Output); +void RTC_AWTConfig(RTC_AWTTypeDef *RCT_AWTStruct); +void RTC_AWTCmd(FunctionalState NewState); +void RTC_SetInterval(uint8_t Period); +void RTC_SetClockSource(uint32_t RTC_ClockSource); +void RTC_CalibrationConfig(RTC_CalibTypeDef *RTC_CalibStruct); +void RTC_CalibrationCmd(FunctionalState NewState); +void RTC_AWT_PSC_set(uint8_t PSC1A,uint32_t PSC2A);//RTC的自动唤醒定时器PSC1 PSC2设置 +uint8_t RTC_BinToBCD(uint8_t Value); +uint8_t RTC_BCDToBin(uint8_t Value); + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32L012_RTC_H */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_spi.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_spi.h new file mode 100644 index 0000000..358346d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_spi.h @@ -0,0 +1,296 @@ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_SPI_H +#define __CW32L012_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "system_cw32l012.h" + +/****************************************************************************** + * type definitions ('typedef') + ******************************************************************************/ +typedef struct +{ + uint32_t SPI_Direction; /*!< 数据通信模式：全双工，单工单发，单工单收，单线半双工 + 参数取值 @ref SPI_Data_Direction */ + + uint32_t SPI_Mode; /*!< SPI主从模式 + 参数取值 @ref SPI_Mode */ + + uint32_t SPI_DataSize; /*!< 单帧数据宽度 + 参数取值 @ref SPI_Data_Size */ + + uint32_t SPI_CPOL; /*!< 串行时钟待机极性 + 参数取值 @ref SPI_Clock_Polarity */ + + uint32_t SPI_CPHA; /*!< 串行时钟相位配置 + 参数取值 @ref SPI_Clock_Phase */ + + uint32_t SPI_NSS; /*!< CS管脚配置 + 参数取值 @ref SPI_Slave_Select_Management */ + + uint32_t SPI_BaudRatePrescaler; /*!< 主机模式下SCK波特率配置 + 参数取值 @ref SPI_BaudRate_Prescaler */ + + uint32_t SPI_FirstBit; /*!< 数据帧高低位顺序选择 + 参数取值 @ref SPI_MSB_LSB_Transmission */ + + uint32_t SPI_Speed; /*!< 设置SPI的采样是否延后，高速下延后，慢速下不用延后 + 参数取值 @ref SPI_Speed */ +} SPI_InitTypeDef; + +/****************************************************************************** + * pre-processor symbols/macros ('#define') + ******************************************************************************/ +// 定义波特率值宏 +#define SPI_BAUDRATE_PCLK_DIV2 0x000 // PCLK/2 +#define SPI_BAUDRATE_PCLK_DIV4 0x001 // PCLK/4 +#define SPI_BAUDRATE_PCLK_DIV8 0x003 // PCLK/8 +#define SPI_BAUDRATE_PCLK_DIV16 0x007 // PCLK/16 +#define SPI_BAUDRATE_PCLK_DIV32 0x00F // PCLK/32 +#define SPI_BAUDRATE_PCLK_DIV64 0x01F // PCLK/64 +#define SPI_BAUDRATE_PCLK_DIV128 0x03F // PCLK/128 +#define SPI_BAUDRATE_PCLK_DIV256 0x07F // PCLK/256 +#define SPI_BAUDRATE_EXT_PCLK_DIV(n) (((n) >> 1) -1) + +/** @defgroup SPI_Data_Direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex (0x00000000) //双向全双工 +#define SPI_Direction_1Line_TxOnly (0x00010000) //单工单发 +#define SPI_Direction_1Line_RxOnly (0x00020000) //单工单收 +#define SPI_Direction_1Lines_HalfDuplex (0x00030000) //单线半双工 +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_1Lines_HalfDuplex) || \ + ((MODE) == SPI_Direction_1Line_TxOnly) || \ + ((MODE) == SPI_Direction_1Line_RxOnly)) + +/** @defgroup SPI_Mode + * @{ + */ + +#define SPI_Mode_Master (0x0001) +#define SPI_Mode_Slave (0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) + +/** @defgroup SPI_Data_Size + * @{ + */ + +#define SPI_DataSize_4b (0x0300) +#define SPI_DataSize_5b (0x0400) +#define SPI_DataSize_6b (0x0500) +#define SPI_DataSize_7b (0x0600) +#define SPI_DataSize_8b (0x0700) +#define SPI_DataSize_9b (0x0800) +#define SPI_DataSize_10b (0x0900) +#define SPI_DataSize_11b (0x0A00) +#define SPI_DataSize_12b (0x0B00) +#define SPI_DataSize_13b (0x0C00) +#define SPI_DataSize_14b (0x0D00) +#define SPI_DataSize_15b (0x0E00) +#define SPI_DataSize_16b (0x0F00) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_4b) || \ + ((DATASIZE) == SPI_DataSize_5b) || \ + ((DATASIZE) == SPI_DataSize_6b) || \ + ((DATASIZE) == SPI_DataSize_7b) || \ + ((DATASIZE) == SPI_DataSize_8b) || \ + ((DATASIZE) == SPI_DataSize_9b) || \ + ((DATASIZE) == SPI_DataSize_10b) || \ + ((DATASIZE) == SPI_DataSize_11b) || \ + ((DATASIZE) == SPI_DataSize_12b) || \ + ((DATASIZE) == SPI_DataSize_13b) || \ + ((DATASIZE) == SPI_DataSize_14b) || \ + ((DATASIZE) == SPI_DataSize_15b) ||\ + ((DATASIZE) == SPI_DataSize_16b)) + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low (0x0000) +#define SPI_CPOL_High (0x0008) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge (0x0000) +#define SPI_CPHA_2Edge (0x0004) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) + +/** @defgroup SPI_Slave_Select_Management + * @{ + */ + +#define SPI_NSS_Soft (0x0002) +#define SPI_NSS_Hard (0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) + + +/** @defgroup SPI_MSB_LSB_Transmission + * @{ + */ + +#define SPI_FirstBit_MSB (0x0000) +#define SPI_FirstBit_LSB (0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) + +/** @defgroup SPI_Speed + * @{ + */ + +#define SPI_Speed_Low (0x00000000) +#define SPI_Speed_High (0x00100000) +#define IS_SPI_SPEED(SPEED) (((SPEED) == SPI_Speed_Low) || \ + ((SPEED) == SPI_Speed_High)) + +/** @defgroup SPI_Direction_Transmit_Receive + * @{ + */ + +#define SPI_Direction_Tx (0x01) +#define SPI_Direction_Rx (0x00) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Tx) || \ + ((DIRECTION) == SPI_Direction_Rx)) + +/** @defgroup SPI_DMA_Requests + * @{ + */ + +#define SPI_DMAReq_Tx (0x00000004) +#define SPI_DMAReq_Rx (0x00000002) +#define IS_SPI_DMAREQ(DMAREQ) (((DMAREQ) == SPI_DMAReq_Tx) || \ + ((DMAREQ) == SPI_DMAReq_Rx) || \ + ((DMAREQ) == (SPI_DMAReq_Tx | SPI_DMAReq_Rx))) + +/** @defgroup SPI_NSS_Internal_Software_Management + * @{ + */ + +#define SPI_NSSInternalSoft_Set ((uint8_t)0x01) +#define SPI_NSSInternalSoft_Reset ((uint8_t)0x00) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) + +/** @defgroup SPI_MISO_Output_config + * @{ + */ + +#define SPI_MISOOutput_HD ((uint8_t)0x01) +#define SPI_MISOOutput_CMOS ((uint8_t)0x00) +#define IS_SPI_MISOOUTPUT(MISOOUTPUT) (((MISOOUTPUT) == SPI_MISOOutput_HD) || \ + ((MISOOUTPUT) == SPI_MISOOutput_CMOS)) + +/** @defgroup SPI_Interrupts + * @{ + */ + +#define SPI_IT_MODF ((uint8_t)0x80) +#define SPI_IT_SSERR ((uint8_t)0x40) +#define SPI_IT_OV ((uint8_t)0x20) +#define SPI_IT_UD ((uint8_t)0x10) +#define SPI_IT_SSR ((uint8_t)0x08) +#define SPI_IT_SSF ((uint8_t)0x04) +#define SPI_IT_RXNE ((uint8_t)0x02) +#define SPI_IT_TXE ((uint8_t)0x01) +#define IS_SPI_IT(IT) ((IT) <= 0xFF && ((IT) != (uint8_t)0x00)) +#define IS_SPI_CLEAR_IT(IT) ((((IT) & (uint8_t)0x01) == 0x00) && ((IT) != (uint8_t)0x00)) + +/** @defgroup SPI_Flags + * @{ + */ + +#define SPI_FLAG_SSLVL (0x0200) +#define SPI_FLAG_BUSY (0x0100) +#define SPI_FLAG_MODF (0x0080) +#define SPI_FLAG_SSERR (0x0040) +#define SPI_FLAG_OV (0x0020) +#define SPI_FLAG_UD (0x0010) +#define SPI_FLAG_SSR (0x0008) +#define SPI_FLAG_SSF (0x0004) +#define SPI_FLAG_RXNE (0x0002) +#define SPI_FLAG_TXE (0x0001) +#define IS_SPI_FLAG(FLAG) ((((FLAG) & 0xFC00) == 0x00) && ((FLAG) != 0x00)) +#define IS_SPI_CLEAR_FLAG(FLAG) ((((FLAG) & 0xFF01) == 0x00) && ((FLAG) != 0x00)) + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == CW_SPI1) || ((PERIPH) == CW_SPI2) ||((PERIPH) == CW_SPI3)) + +/****************************************************************************** +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ + + +/****************************************************************************** +* Global function prototypes +******************************************************************************/ + +/* 数据收发 */ +void SPI_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_ReceiveData(SPI_TypeDef* SPIx); +uint16_t SPI_TransmitReceive(SPI_TypeDef* SPIx, uint16_t Data); +/* 初始化 */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void SPI1_DeInit(void); + +/* 使能或禁止SPIx */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); + +/* 中断及标志 */ +void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState); +ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT); +void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT); +FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG); +void SPI_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_FLAG); + +/* 单线半双工数据传输方向配置 */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint8_t SPI_Direction); + +/* DMA */ +void SPI_DMACmd(SPI_TypeDef* SPIx, uint32_t SPI_DMAReq, FunctionalState NewState); + +/* 软件内部配置NSS */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint8_t SPI_NSSInternalSoft); + +/* 设置数据帧的位宽 */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); + +/* 从模式MISO输出配置*/ +void SPI_MISOOutputConfig(SPI_TypeDef* SPIx, uint8_t SPI_MISOOutput); + +/* 清空发送缓冲区和移位寄存器 */ +void SPI_FlushSendBuff(SPI_TypeDef* SPIx); + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32L012_SPI_H */ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_sysctrl.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_sysctrl.h new file mode 100644 index 0000000..89039d9 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_sysctrl.h @@ -0,0 +1,725 @@ +/** + * @file cw32l012_sysctrl.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2022 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_SYSCTRL_H +#define __CW32L012_SYSCTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "system_cw32l012.h" +#include "cw32l012_gpio.h" + +typedef struct { + uint32_t SourceFreq; + uint32_t PLL_OutFreq; + uint16_t ClockSource; + uint16_t WaitCycle; +}PLL_InitTypeDef; +//================================================================================== +#define HSIOSC_VALUE ((uint32_t)96000000) /*!< Value of the Internal oscillator in Hz*/ +#define HSE_VALUE ((uint32_t)16000000) /*!< Value of the External oscillator in Hz */ + +#define LSI_VALUE ((uint32_t)32800) /*!< Value of the External oscillator in Hz */ +#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz */ + +#define LSE_PIN_PORT CW_GPIOC +#define LSE_PIN_IN GPIO_PIN_14 +#define LSE_PIN_OUT GPIO_PIN_15 + +#define HSE_PIN_PORT CW_GPIOF +#define HSE_PIN_IN GPIO_PIN_0 +#define HSE_PIN_OUT GPIO_PIN_1 + +#define PCLK_OUT_PIN_PORT CW_GPIOA +#define PCLK_OUT_PIN GPIO_PIN_3 +#define PCLK_OUT_PIN_AF 4 + +#define MCO_PIN_PORT CW_GPIOA +#define MCO_PIN GPIO_PIN_4 +#define MCO_PIN_AF 4 +/* SYSCTRL CR0 --------------------------------------------------------*/ +#define SYSCTRL_KEY (0x5A5A0000U) +#define SYSCTRL_KEY_MASK (0xFFFF0000U) +#define SYSCTRL_KEY_MASK_INV (0x0000FFFFU) + +#define SYSCTRL_HCLK_DIV1 (0x0UL << SYSCTRL_CR0_HCLKPRS_Pos) /*!< SYSCLK not divided */ +#define SYSCTRL_HCLK_DIV2 (0x1UL << SYSCTRL_CR0_HCLKPRS_Pos) /*!< SYSCLK divided by 2 */ +#define SYSCTRL_HCLK_DIV4 (0x2UL << SYSCTRL_CR0_HCLKPRS_Pos) /*!< SYSCLK divided by 4 */ +#define SYSCTRL_HCLK_DIV8 (0x3UL << SYSCTRL_CR0_HCLKPRS_Pos) /*!< SYSCLK divided by 8 */ +#define SYSCTRL_HCLK_DIV16 (0x4UL << SYSCTRL_CR0_HCLKPRS_Pos) /*!< SYSCLK divided by 16 */ +#define SYSCTRL_HCLK_DIV32 (0x5UL << SYSCTRL_CR0_HCLKPRS_Pos) /*!< SYSCLK divided by 32 */ +#define SYSCTRL_HCLK_DIV64 (0x6UL << SYSCTRL_CR0_HCLKPRS_Pos) /*!< SYSCLK divided by 64 */ +#define SYSCTRL_HCLK_DIV128 (0x7ul << SYSCTRL_CR0_HCLKPRS_Pos) /*!< SYSCLK divided by 128 */ +#define IS_SYSCTRL_HCLKPRS(INSTANCE) (((INSTANCE) == SYSCTRL_HCLK_DIV1) ||\ + ((INSTANCE) == SYSCTRL_HCLK_DIV2) ||\ + ((INSTANCE) == SYSCTRL_HCLK_DIV4) ||\ + ((INSTANCE) == SYSCTRL_HCLK_DIV8) ||\ + ((INSTANCE) == SYSCTRL_HCLK_DIV16) ||\ + ((INSTANCE) == SYSCTRL_HCLK_DIV32) ||\ + ((INSTANCE) == SYSCTRL_HCLK_DIV64) ||\ + ((INSTANCE) == SYSCTRL_HCLK_DIV128)) + +#define SYSCTRL_PCLK_DIV1 (0x0UL << SYSCTRL_CR0_PCLKPRS_Pos) /*!< HCLK not divided */ +#define SYSCTRL_PCLK_DIV2 (0x1UL << SYSCTRL_CR0_PCLKPRS_Pos) /*!< HCLK divided by 2 */ +#define SYSCTRL_PCLK_DIV4 (0x2UL << SYSCTRL_CR0_PCLKPRS_Pos) /*!< HCLK divided by 4 */ +#define SYSCTRL_PCLK_DIV8 (0x3UL << SYSCTRL_CR0_PCLKPRS_Pos) /*!< HCLK divided by 8 */ +#define IS_SYSCTRL_PCLKPRS(INSTANCE) (((INSTANCE) == SYSCTRL_PCLK_DIV1) ||\ + ((INSTANCE) == SYSCTRL_PCLK_DIV2) ||\ + ((INSTANCE) == SYSCTRL_PCLK_DIV4) ||\ + ((INSTANCE) == SYSCTRL_PCLK_DIV8)) + +#define SYSCTRL_SYSCLKSRC_HSI (0x00000000U) /*!< HSI selected as system clock */ +#define SYSCTRL_SYSCLKSRC_HSE (0x00000001U) /*!< HSE selected as system clock */ +#define SYSCTRL_SYSCLKSRC_PLL (0x00000002U) /*!< LSI selected as system clock */ +#define SYSCTRL_SYSCLKSRC_LSI (0x00000003U) /*!< LSI selected as system clock */ +#define SYSCTRL_SYSCLKSRC_LSE (0x00000004U) /*!< LSE selected as system clock */ + +#define IS_SYSCTRL_SYSCLKSRC(INSTANCE) (((INSTANCE) == SYSCTRL_SYSCLKSRC_HSI) ||\ + ((INSTANCE) == SYSCTRL_SYSCLKSRC_HSE) ||\ + ((INSTANCE) == SYSCTRL_SYSCLKSRC_LSI) ||\ + ((INSTANCE) == SYSCTRL_SYSCLKSRC_LSE)) + +/* SYSCTRL CR1 --------------------------------------------------------*/ +#define SYSCTRL_HSIEN bv0 +#define SYSCTRL_HSEEN bv1 +#define SYSCTRL_PLLEN bv2 +#define SYSCTRL_LSIEN bv3 +#define SYSCTRL_LSEEN bv4 +#define SYSCTRL_LSELOCKEN bv5 +#define SYSCTRL_LSELOCKDIS 0x00UL +#define IS_SYSCTRL_LSELOCK_STATUS(INSTANCE) (((INSTANCE) == SYSCTRL_LSELOCKEN) ||\ + ((INSTANCE) == SYSCTRL_LSELOCKDIS)) + +#define SYSCTRL_LSECCSEN bv6 +#define SYSCTRL_HSECCSEN bv7 +#define SYSCTRL_CLKCCSEN bv8 +#define IS_SYSCTRL_CCS_STATUS(INSTANCE) (((INSTANCE) == SYSCTRL_LSECCSEN) ||\ + ((INSTANCE) == SYSCTRL_HSECCSEN) ||\ + ((INSTANCE) == SYSCTRL_CLKCCSEN)) + +/* SYSCTRL CR2 --------------------------------------------------------*/ +#define SYSCTRL_RAMBRKEN bv15 +#define SYSCTRL_LVDBRKEN bv14 +#define SYSCTRL_DSBRKEN bv13 +#define SYSCTRL_LOCKUPBRKEN bv12 +#define SYSCTRL_LSEBRKEN bv11 +#define SYSCTRL_HSEBRKEN bv10 +//#define SYSCTRL_RTC_LOWPOWEREN bv7 +#define SYSCTRL_FLASHWAIT_24M (0x00UL) +#define SYSCTRL_FLASHWAIT_48M (0x01UL << SYSCTRL_CR2_FLASHWAIT_Pos) +#define SYSCTRL_FLASHWAIT_72M (0x02UL << SYSCTRL_CR2_FLASHWAIT_Pos) +#define SYSCTRL_FLASHWAIT_96M (0x03UL << SYSCTRL_CR2_FLASHWAIT_Pos) +#define IS_SYSCTRL_FLASHWAIT_VALUE(VAL) (((VAL) == SYSCTRL_FLASHWAIT_24M) ||\ + ((VAL) == SYSCTRL_FLASHWAIT_48M) ||\ + ((VAL) == SYSCTRL_FLASHWAIT_72M) ||\ + ((VAL) == SYSCTRL_FLASHWAIT_96M)) + +#define SYSCTRL_WAKEUPCLKEN bv3 +#define SYSCTRL_WAKEUPCLKDIS 0x00UL +#define IS_SYSCTRL_WAKEUPCLK_STATUS(INSTANCE) (((INSTANCE) == SYSCTRL_WAKEUPCLKEN) ||\ + ((INSTANCE) == SYSCTRL_WAKEUPCLKDIS)) + +#define SYSCTRL_LOCKUPEN bv2 +#define SYSCTRL_LOCKUPDIS 0x00UL +#define IS_SYSCTRL_LOCKUP_STATUS(INSTANCE) (((INSTANCE) == SYSCTRL_LOCKUPEN) ||\ + ((INSTANCE) == SYSCTRL_LOCKUPDIS)) + +#define SYSCTRL_SWDIOEN 0x00UL +#define SYSCTRL_SWDIODIS bv1 +#define IS_SYSCTRL_SWDIO_STATUS(INSTANCE) (((INSTANCE) == SYSCTRL_SWDIOEN) ||\ + ((INSTANCE) == SYSCTRL_SWDIODIS)) + +//#define SYSCTRL_RSTIOEN 0x00UL +//#define SYSCTRL_RSTIODIS bv0 + +/* SYSCTRL HSI --------------------------------------------------------*/ +#define SYSCTRL_HSI_TRIMCODEADDR (0x001007C0U) // + + +#define SYSCTRL_HSIOSC_DIV1 ((uint32_t)(1UL << SYSCTRL_HSI_DIV_Pos)) +#define SYSCTRL_HSIOSC_DIV2 ((uint32_t)(2UL << SYSCTRL_HSI_DIV_Pos)) +#define SYSCTRL_HSIOSC_DIV3 ((uint32_t)(3UL << SYSCTRL_HSI_DIV_Pos)) +#define SYSCTRL_HSIOSC_DIV4 ((uint32_t)(4UL << SYSCTRL_HSI_DIV_Pos)) +#define SYSCTRL_HSIOSC_DIV5 ((uint32_t)(5UL << SYSCTRL_HSI_DIV_Pos)) +#define SYSCTRL_HSIOSC_DIV6 ((uint32_t)(6UL << SYSCTRL_HSI_DIV_Pos)) +#define SYSCTRL_HSIOSC_DIV7 ((uint32_t)(7UL << SYSCTRL_HSI_DIV_Pos)) +#define SYSCTRL_HSIOSC_DIV8 ((uint32_t)(8UL << SYSCTRL_HSI_DIV_Pos)) +#define SYSCTRL_HSIOSC_DIV9 ((uint32_t)(9UL << SYSCTRL_HSI_DIV_Pos)) +#define SYSCTRL_HSIOSC_DIV10 ((uint32_t)(10UL << SYSCTRL_HSI_DIV_Pos)) +#define SYSCTRL_HSIOSC_DIV12 ((uint32_t)(11UL << SYSCTRL_HSI_DIV_Pos)) +#define SYSCTRL_HSIOSC_DIV16 ((uint32_t)(12UL << SYSCTRL_HSI_DIV_Pos)) +#define SYSCTRL_HSIOSC_DIV20 ((uint32_t)(13UL << SYSCTRL_HSI_DIV_Pos)) +#define SYSCTRL_HSIOSC_DIV24 ((uint32_t)(14UL << SYSCTRL_HSI_DIV_Pos)) +#define SYSCTRL_HSIOSC_DIV28 ((uint32_t)(15UL << SYSCTRL_HSI_DIV_Pos)) +#define SYSCTRL_HSIOSC_DIV32 ((uint32_t)(0UL)) +#define HSIOSC_TO_HSI96MHZ SYSCTRL_HSIOSC_DIV1 +#define HSIOSC_TO_HSI48MHZ SYSCTRL_HSIOSC_DIV2 +#define HSIOSC_TO_HSI32MHZ SYSCTRL_HSIOSC_DIV3 +#define HSIOSC_TO_HSI24MHZ SYSCTRL_HSIOSC_DIV4 +#define HSIOSC_TO_HSI19P2MHZ SYSCTRL_HSIOSC_DIV5 +#define HSIOSC_TO_HSI16MHZ SYSCTRL_HSIOSC_DIV6 +#define HSIOSC_TO_HSI13P7MHZ SYSCTRL_HSIOSC_DIV7 +#define HSIOSC_TO_HSI12MHZ SYSCTRL_HSIOSC_DIV8 +#define HSIOSC_TO_HSI10P6MHZ SYSCTRL_HSIOSC_DIV9 +#define HSIOSC_TO_HSI9P6MHZ SYSCTRL_HSIOSC_DIV10 +#define HSIOSC_TO_HSI8MHZ SYSCTRL_HSIOSC_DIV12 +#define HSIOSC_TO_HSI6MHZ SYSCTRL_HSIOSC_DIV16 +#define HSIOSC_TO_HSI4P8MHZ SYSCTRL_HSIOSC_DIV20 +#define HSIOSC_TO_HSI4MHZ SYSCTRL_HSIOSC_DIV24 +#define HSIOSC_TO_HSI3P4MHZ SYSCTRL_HSIOSC_DIV28 +#define HSIOSC_TO_HSI3MHZ SYSCTRL_HSIOSC_DIV32 + +#define IS_SYSCTRL_HSIOSC_DIV(INSTANCE) (((INSTANCE) == SYSCTRL_HSIOSC_DIV1) ||\ + ((INSTANCE) == SYSCTRL_HSIOSC_DIV2) ||\ + ((INSTANCE) == SYSCTRL_HSIOSC_DIV3) ||\ + ((INSTANCE) == SYSCTRL_HSIOSC_DIV4) ||\ + ((INSTANCE) == SYSCTRL_HSIOSC_DIV5) ||\ + ((INSTANCE) == SYSCTRL_HSIOSC_DIV6) ||\ + ((INSTANCE) == SYSCTRL_HSIOSC_DIV7) ||\ + ((INSTANCE) == SYSCTRL_HSIOSC_DIV8) ||\ + ((INSTANCE) == SYSCTRL_HSIOSC_DIV9) ||\ + ((INSTANCE) == SYSCTRL_HSIOSC_DIV10) ||\ + ((INSTANCE) == SYSCTRL_HSIOSC_DIV12) ||\ + ((INSTANCE) == SYSCTRL_HSIOSC_DIV16) ||\ + ((INSTANCE) == SYSCTRL_HSIOSC_DIV20) ||\ + ((INSTANCE) == SYSCTRL_HSIOSC_DIV24) ||\ + ((INSTANCE) == SYSCTRL_HSIOSC_DIV28) ||\ + ((INSTANCE) == SYSCTRL_HSIOSC_DIV32)) + +/* SYSCTRL LSI --------------------------------------------------------*/ +#define SYSCTRL_LSI_TRIMCODEADDR (0x001007C2U) // + +#define SYSCTRL_LSI_WAITCYCLE_6 ((uint32_t)(0x0UL << SYSCTRL_LSI_WAITCYCLE_Pos)) +#define SYSCTRL_LSI_WAITCYCLE_18 ((uint32_t)(0x1UL << SYSCTRL_LSI_W13ITCYCLE_Pos)) +#define SYSCTRL_LSI_WAITCYCLE_66 ((uint32_t)(0x2UL << SYSCTRL_LSI_WAITCYCLE_Pos)) +#define SYSCTRL_LSI_WAITCYCLE_258 ((uint32_t)(0x3UL << SYSCTRL_LSI_WAITCYCLE_Pos)) + + +/* SYSCTRL HSE --------------------------------------------------------*/ +#define SYSCTRL_HSE_FLT_CLOSE (0U) +#define SYSCTRL_HSE_FLT_OPEN (1U << SYSCTRL_HSE_DIGFLT_Pos) + +#define SYSCTRL_HSE_PDRIVER_LEVEL0 ((uint32_t)(0x0UL << SYSCTRL_HSE_PDRIVER_Pos)) +#define SYSCTRL_HSE_PDRIVER_LEVEL1 ((uint32_t)(0x1UL << SYSCTRL_HSE_PDRIVER_Pos)) +#define SYSCTRL_HSE_PDRIVER_LEVEL2 ((uint32_t)(0x2UL << SYSCTRL_HSE_PDRIVER_Pos)) +#define SYSCTRL_HSE_PDRIVER_LEVEL3 ((uint32_t)(0x3UL << SYSCTRL_HSE_PDRIVER_Pos)) +#define SYSCTRL_HSE_PDRIVER_LEVEL4 ((uint32_t)(0x4UL << SYSCTRL_HSE_PDRIVER_Pos)) +#define SYSCTRL_HSE_PDRIVER_LEVEL5 ((uint32_t)(0x5UL << SYSCTRL_HSE_PDRIVER_Pos)) +#define SYSCTRL_HSE_PDRIVER_LEVEL6 ((uint32_t)(0x6UL << SYSCTRL_HSE_PDRIVER_Pos)) +#define SYSCTRL_HSE_PDRIVER_LEVEL7 ((uint32_t)(0x7UL << SYSCTRL_HSE_PDRIVER_Pos)) +#define SYSCTRL_HSE_PDRIVER_LEVEL8 ((uint32_t)(0x8UL << SYSCTRL_HSE_PDRIVER_Pos)) +#define SYSCTRL_HSE_PDRIVER_LEVEL9 ((uint32_t)(0x9UL << SYSCTRL_HSE_PDRIVER_Pos)) +#define SYSCTRL_HSE_PDRIVER_LEVEL10 ((uint32_t)(0xAUL << SYSCTRL_HSE_PDRIVER_Pos)) +#define SYSCTRL_HSE_PDRIVER_LEVEL11 ((uint32_t)(0xBUL << SYSCTRL_HSE_PDRIVER_Pos)) +#define SYSCTRL_HSE_PDRIVER_LEVEL12 ((uint32_t)(0xCUL << SYSCTRL_HSE_PDRIVER_Pos)) +#define SYSCTRL_HSE_PDRIVER_LEVEL13 ((uint32_t)(0xDUL << SYSCTRL_HSE_PDRIVER_Pos)) +#define SYSCTRL_HSE_PDRIVER_LEVEL14 ((uint32_t)(0xEUL << SYSCTRL_HSE_PDRIVER_Pos)) +#define SYSCTRL_HSE_PDRIVER_LEVEL15 ((uint32_t)(0xFUL << SYSCTRL_HSE_PDRIVER_Pos)) + + +#define SYSCTRL_HSE_DETCNT_4M ((uint32_t)(2000UL << SYSCTRL_HSE_DETCNT_Pos)) +#define SYSCTRL_HSE_DETCNT_8M ((uint32_t)(1000UL << SYSCTRL_HSE_DETCNT_Pos)) +#define SYSCTRL_HSE_DETCNT_12M ((uint32_t)(666UL << SYSCTRL_HSE_DETCNT_Pos)) +#define SYSCTRL_HSE_DETCNT_16M ((uint32_t)(500UL << SYSCTRL_HSE_DETCNT_Pos)) +#define SYSCTRL_HSE_DETCNT_24M ((uint32_t)(333UL << SYSCTRL_HSE_DETCNT_Pos)) +#define SYSCTRL_HSE_DETCNT_32M ((uint32_t)(250UL << SYSCTRL_HSE_DETCNT_Pos)) +#define SYSCTRL_HSE_DETCNT_48M ((uint32_t)(167UL << SYSCTRL_HSE_DETCNT_Pos)) +#define SYSCTRL_HSE_DETCNT_(X)M ((uint32_t)(8000/X) << SYSCTRL_HSE_DETCNT_Pos) + +#define SYSCTRL_HEX_ENPOL_HIGH (0x00000000U) +#define SYSCTRL_HEX_ENPOL_LOW (bv7) + +#define SYSCTRL_HSE_MODE_OSC (0x00000000U) +#define SYSCTRL_HSE_MODE_CLK bv6 +#define IS_SYSCTRL_HSE_MODE(INSTANCE) (((INSTANCE) == SYSCTRL_HSE_MODE_OSC) ||\ + ((INSTANCE) == SYSCTRL_HSE_MODE_CLK)) + + +#define SYSCTRL_HSE_WAITCYCLE_8192 (0x00000000U) +#define SYSCTRL_HSE_WAITCYCLE_32768 ((uint32_t)(0x1UL << SYSCTRL_HSE_WAITCYCLE_Pos)) +#define SYSCTRL_HSE_WAITCYCLE_131072 ((uint32_t)(0x2UL << SYSCTRL_HSE_WAITCYCLE_Pos)) +#define SYSCTRL_HSE_WAITCYCLE_262144 ((uint32_t)(0x3UL << SYSCTRL_HSE_WAITCYCLE_Pos)) + +#define SYSCTRL_HSE_DRIVER_LEVEL0 ((uint32_t)(0x0UL << SYSCTRL_HSE_DRIVER_Pos)) +#define SYSCTRL_HSE_DRIVER_LEVEL1 ((uint32_t)(0x1UL << SYSCTRL_HSE_DRIVER_Pos)) +#define SYSCTRL_HSE_DRIVER_LEVEL2 ((uint32_t)(0x2UL << SYSCTRL_HSE_DRIVER_Pos)) +#define SYSCTRL_HSE_DRIVER_LEVEL3 ((uint32_t)(0x3UL << SYSCTRL_HSE_DRIVER_Pos)) +#define SYSCTRL_HSE_DRIVER_LEVEL4 ((uint32_t)(0x4UL << SYSCTRL_HSE_DRIVER_Pos)) +#define SYSCTRL_HSE_DRIVER_LEVEL5 ((uint32_t)(0x5UL << SYSCTRL_HSE_DRIVER_Pos)) +#define SYSCTRL_HSE_DRIVER_LEVEL6 ((uint32_t)(0x6UL << SYSCTRL_HSE_DRIVER_Pos)) +#define SYSCTRL_HSE_DRIVER_LEVEL7 ((uint32_t)(0x7UL << SYSCTRL_HSE_DRIVER_Pos)) +#define SYSCTRL_HSE_DRIVER_LEVEL8 ((uint32_t)(0x8UL << SYSCTRL_HSE_DRIVER_Pos)) +#define SYSCTRL_HSE_DRIVER_LEVEL9 ((uint32_t)(0x9UL << SYSCTRL_HSE_DRIVER_Pos)) +#define SYSCTRL_HSE_DRIVER_LEVEL10 ((uint32_t)(0xAUL << SYSCTRL_HSE_DRIVER_Pos)) +#define SYSCTRL_HSE_DRIVER_LEVEL11 ((uint32_t)(0xBUL << SYSCTRL_HSE_DRIVER_Pos)) +#define SYSCTRL_HSE_DRIVER_LEVEL12 ((uint32_t)(0xCUL << SYSCTRL_HSE_DRIVER_Pos)) +#define SYSCTRL_HSE_DRIVER_LEVEL13 ((uint32_t)(0xDUL << SYSCTRL_HSE_DRIVER_Pos)) +#define SYSCTRL_HSE_DRIVER_LEVEL14 ((uint32_t)(0xEUL << SYSCTRL_HSE_DRIVER_Pos)) +#define SYSCTRL_HSE_DRIVER_LEVEL15 ((uint32_t)(0xFUL << SYSCTRL_HSE_DRIVER_Pos)) + + +/* SYSCTRL LSE --------------------------------------------------------*/ +#define SYSCTRL_LSE_PINLOCKEN (bv17) +#define SYSCTRL_LSE_PINLOCKDIS (0UL) + +//#define SYSCTRL_LSE_RESTRIM_35M 0UL +//#define SYSCTRL_LSE_RESTRIM_25M (1UL << SYSCTRL_LSE_RESTRIM_Pos) +//#define SYSCTRL_LSE_RESTRIM_20M (1UL << SYSCTRL_LSE_RESTRIM_Pos) +//#define SYSCTRL_LSE_RESTRIM_10M (1UL << SYSCTRL_LSE_RESTRIM_Pos) + +//#define SYSCTRL_LSE_CAP_ENHANCE 0UL +//#define SYSCTRL_LSE_CAP_NORMAL (1UL << SYSCTRL_LSE_CPEN_Pos) + +//#define SYSCTRL_LSE_COMP_40nA 0UL +//#define SYSCTRL_LSE_COMP_80nA bv12 + +#define SYSCTRL_LSE_PDRIVER_LEVEL0 ((uint32_t)(0x0UL << SYSCTRL_LSE_PDRIVER_Pos)) +#define SYSCTRL_LSE_PDRIVER_LEVEL1 ((uint32_t)(0x1UL << SYSCTRL_LSE_PDRIVER_Pos)) +#define SYSCTRL_LSE_PDRIVER_LEVEL2 ((uint32_t)(0x2UL << SYSCTRL_LSE_PDRIVER_Pos)) +#define SYSCTRL_LSE_PDRIVER_LEVEL3 ((uint32_t)(0x3UL << SYSCTRL_LSE_PDRIVER_Pos)) +#define SYSCTRL_LSE_PDRIVER_LEVEL4 ((uint32_t)(0x4UL << SYSCTRL_LSE_PDRIVER_Pos)) +#define SYSCTRL_LSE_PDRIVER_LEVEL5 ((uint32_t)(0x5UL << SYSCTRL_LSE_PDRIVER_Pos)) +#define SYSCTRL_LSE_PDRIVER_LEVEL6 ((uint32_t)(0x6UL << SYSCTRL_LSE_PDRIVER_Pos)) +#define SYSCTRL_LSE_PDRIVER_LEVEL7 ((uint32_t)(0x7UL << SYSCTRL_LSE_PDRIVER_Pos)) +#define SYSCTRL_LSE_PDRIVER_LEVEL8 ((uint32_t)(0x8UL << SYSCTRL_LSE_PDRIVER_Pos)) +#define SYSCTRL_LSE_PDRIVER_LEVEL9 ((uint32_t)(0x9UL << SYSCTRL_LSE_PDRIVER_Pos)) +#define SYSCTRL_LSE_PDRIVER_LEVEL10 ((uint32_t)(0xAUL << SYSCTRL_LSE_PDRIVER_Pos)) +#define SYSCTRL_LSE_PDRIVER_LEVEL11 ((uint32_t)(0xBUL << SYSCTRL_LSE_PDRIVER_Pos)) +#define SYSCTRL_LSE_PDRIVER_LEVEL12 ((uint32_t)(0xCUL << SYSCTRL_LSE_PDRIVER_Pos)) +#define SYSCTRL_LSE_PDRIVER_LEVEL13 ((uint32_t)(0xDUL << SYSCTRL_LSE_PDRIVER_Pos)) +#define SYSCTRL_LSE_PDRIVER_LEVEL14 ((uint32_t)(0xEUL << SYSCTRL_LSE_PDRIVER_Pos)) +#define SYSCTRL_LSE_PDRIVER_LEVEL15 ((uint32_t)(0xFUL << SYSCTRL_LSE_PDRIVER_Pos)) + +//#define SYSCTRL_LSE_ANAFLT_DIS bv7 + +#define SYSCTRL_LSE_MODE_OSC (0x00000000U) +#define SYSCTRL_LSE_MODE_CLK (bv6) +#define IS_SYSCTRL_LSE_MODE(INSTANCE) (((INSTANCE) == SYSCTRL_LSE_MODE_OSC) ||\ + ((INSTANCE) == SYSCTRL_LSE_MODE_CLK)) + +#define SYSCTRL_LSE_WAITCYCLE_256 (0x00000000U) +#define SYSCTRL_LSE_WAITCYCLE_1024 ((uint32_t)(1UL << SYSCTRL_LSE_WAITCYCLE_Pos)) +#define SYSCTRL_LSE_WAITCYCLE_4096 ((uint32_t)(2UL << SYSCTRL_LSE_WAITCYCLE_Pos)) +#define SYSCTRL_LSE_WAITCYCLE_16384 ((uint32_t)(3UL << SYSCTRL_LSE_WAITCYCLE_Pos)) + + +#define SYSCTRL_LSE_DRIVER_LEVEL0 (0x00000000U) +#define SYSCTRL_LSE_DRIVER_LEVEL1 (0x00000001U) +#define SYSCTRL_LSE_DRIVER_LEVEL2 (0x00000002U) +#define SYSCTRL_LSE_DRIVER_LEVEL3 (0x00000003U) +#define SYSCTRL_LSE_DRIVER_LEVEL4 (0x00000004U) +#define SYSCTRL_LSE_DRIVER_LEVEL5 (0x00000005U) +#define SYSCTRL_LSE_DRIVER_LEVEL6 (0x00000006U) +#define SYSCTRL_LSE_DRIVER_LEVEL7 (0x00000007U) +#define SYSCTRL_LSE_DRIVER_LEVEL8 (0x00000008U) +#define SYSCTRL_LSE_DRIVER_LEVEL9 (0x00000009U) +#define SYSCTRL_LSE_DRIVER_LEVEL10 (0x0000000aU) +#define SYSCTRL_LSE_DRIVER_LEVEL11 (0x0000000bU) +#define SYSCTRL_LSE_DRIVER_LEVEL12 (0x0000000cU) +#define SYSCTRL_LSE_DRIVER_LEVEL13 (0x0000000dU) +#define SYSCTRL_LSE_DRIVER_LEVEL14 (0x0000000eU) +#define SYSCTRL_LSE_DRIVER_LEVEL15 (0x0000000fU) + +#define IS_SYSCTRL_LSE_DRIVER(DRIVER) ((DRIVER) < 0x10) + +/* SYSCTRL PLL --------------------------------------------------------*/ +#define SYSCTRL_PLL_WAIT_CYCLE_128 (0U << SYSCTRL_PLL_WAITCYCLE_Pos) +#define SYSCTRL_PLL_WAIT_CYCLE_256 (1U << SYSCTRL_PLL_WAITCYCLE_Pos) +#define SYSCTRL_PLL_WAIT_CYCLE_512 (2U << SYSCTRL_PLL_WAITCYCLE_Pos) +#define SYSCTRL_PLL_WAIT_CYCLE_1024 (3U << SYSCTRL_PLL_WAITCYCLE_Pos) +#define SYSCTRL_PLL_WAIT_CYCLE_2048 (4U << SYSCTRL_PLL_WAITCYCLE_Pos) +#define SYSCTRL_PLL_WAIT_CYCLE_4096 (5U << SYSCTRL_PLL_WAITCYCLE_Pos) +#define SYSCTRL_PLL_WAIT_CYCLE_8192 (6U << SYSCTRL_PLL_WAITCYCLE_Pos) +#define SYSCTRL_PLL_WAIT_CYCLE_16384 (7U << SYSCTRL_PLL_WAITCYCLE_Pos) + +#define SYSCTRL_PLL_DIV1 (0U << SYSCTRL_PLL_DIV_Pos) +#define SYSCTRL_PLL_DIV2 (1U << SYSCTRL_PLL_DIV_Pos) +#define SYSCTRL_PLL_DIV3 (2U << SYSCTRL_PLL_DIV_Pos) +#define SYSCTRL_PLL_DIV4 (3U << SYSCTRL_PLL_DIV_Pos) +#define SYSCTRL_PLL_DIV5 (4U << SYSCTRL_PLL_DIV_Pos) +#define SYSCTRL_PLL_DIV6 (5U << SYSCTRL_PLL_DIV_Pos) +#define SYSCTRL_PLL_DIV7 (6U << SYSCTRL_PLL_DIV_Pos) +#define SYSCTRL_PLL_DIV8 (7U << SYSCTRL_PLL_DIV_Pos) +#define SYSCTRL_PLL_DIV9 (8U << SYSCTRL_PLL_DIV_Pos) +#define SYSCTRL_PLL_DIV10 (9U << SYSCTRL_PLL_DIV_Pos) +#define SYSCTRL_PLL_DIV11 (10U << SYSCTRL_PLL_DIV_Pos) +#define SYSCTRL_PLL_DIV12 (11U << SYSCTRL_PLL_DIV_Pos) +#define SYSCTRL_PLL_DIV13 (12U << SYSCTRL_PLL_DIV_Pos) +#define SYSCTRL_PLL_DIV14 (13U << SYSCTRL_PLL_DIV_Pos) +#define SYSCTRL_PLL_DIV15 (14U << SYSCTRL_PLL_DIV_Pos) +#define SYSCTRL_PLL_DIV16 (15U << SYSCTRL_PLL_DIV_Pos) + +#define SYSCTRL_PLL_SOURCE_HSI_48M (0U << SYSCTRL_PLL_SOURCE_Pos) +#define SYSCTRL_PLL_SOURCE_HSE (1U << SYSCTRL_PLL_SOURCE_Pos) + +/* SYSCTRL ISR --------------------------------------------------------*/ +#define SYSCTRL_FLAG_LSESTABLE bv15 +#define SYSCTRL_FLAG_LSISTABLE bv14 +#define SYSCTRL_FLAG_PLLSTABLE bv13 +#define SYSCTRL_FLAG_HSESTABLE bv12 +#define SYSCTRL_FLAG_HSISTABLE bv11 +#define IS_SYSCTRL_STABLEFLAG(FLAG) ((FLAG) == SYSCTRL_FLAG_HSISTABLE || \ + (FLAG) == SYSCTRL_FLAG_HSESTABLE || \ + (FLAG) == SYSCTRL_FLAG_LSESTABLE || \ + (FLAG) == SYSCTRL_FLAG_LSISTABLE || \ + (FLAG) == SYSCTRL_FLAG_PLLSTABLE) + +#define SYSCTRL_FLAG_HSEFAULT bv8 +#define SYSCTRL_FLAG_LSEFAULT bv7 +#define SYSCTRL_FLAG_HSEFAIL bv6 +#define SYSCTRL_FLAG_LSEFAIL bv5 +#define SYSCTRL_FLAG_LSERDY bv4 +#define SYSCTRL_FLAG_LSIRDY bv3 +#define SYSCTRL_FLAG_PLLRDY bv2 +#define SYSCTRL_FLAG_HSERDY bv1 +#define SYSCTRL_FLAG_HSIRDY bv0 + +/* SYSCTRL IER ICR --------------------------------------------------------*/ +#define SYSCTRL_IT_HSEFAULT (bv8) +#define SYSCTRL_IT_LSEFAULT (bv7) +#define SYSCTRL_IT_HSEFAIL (bv6) +#define SYSCTRL_IT_LSEFAIL (bv5) +#define SYSCTRL_IT_LSERDY (bv4) +#define SYSCTRL_IT_LSIRDY (bv3) +#define SYSCTRL_IT_PLLRDY (bv2) +#define SYSCTRL_IT_HSERDY (bv1) +#define SYSCTRL_IT_HSIRDY (bv0) +#define IS_SYSCTRL_IT(IT) ((((IT) & 0xFFFFFFE0) == 0x0UL) && ((IT) != 0x0UL)) +#define IS_SYSCTRL_GET_IT(IT) (((IT) == SYSCTRL_IT_HSEFAULT) || \ + ((IT) == SYSCTRL_IT_LSEFAULT) || \ + ((IT) == SYSCTRL_IT_HSEFAIL) || \ + ((IT) == SYSCTRL_IT_LSEFAIL) || \ + ((IT) == SYSCTRL_IT_LSERDY) ||\ + ((IT) == SYSCTRL_IT_LSIRDY) ||\ + ((IT) == SYSCTRL_IT_PLLRDY) ||\ + ((IT) == SYSCTRL_IT_HSERDY) ||\ + ((IT) == SYSCTRL_IT_HSIRDY)) + +/* SYSCTRL RESETFLAG --------------------------------------------------------*/ +#define SYSCTRL_RESETFLAG_POR bv0 +#define SYSCTRL_RESETFLAG_LVD bv3 +#define SYSCTRL_RESETFLAG_IWDT bv4 +#define SYSCTRL_RESETFLAG_WWDT bv5 +#define SYSCTRL_RESETFLAG_PIN bv6 +#define SYSCTRL_RESETFLAG_LOCKUP bv8 +#define SYSCTRL_RESETFLAG_SYSRESETREQ bv9 +#define SYSCTRL_RESETFLAG_ALL (bv9|bv8|bv6|bv5|bv4|bv3|bv0) +#define IS_SYSCTRL_RSTFLAG(FLAG) ((FLAG) == SYSCTRL_RESETFLAG_POR || \ + (FLAG) == SYSCTRL_RESETFLAG_LVD || \ + (FLAG) == SYSCTRL_RESETFLAG_IWDT || \ + (FLAG) == SYSCTRL_RESETFLAG_WWDT || \ + (FLAG) == SYSCTRL_RESETFLAG_PIN || \ + (FLAG) == SYSCTRL_RESETFLAG_LOCKUP || \ + (FLAG) == SYSCTRL_RESETFLAG_SYSRESETREQ || \ + (FLAG) == SYSCTRL_RESETFLAG_ALL) + +/* SYSCTRL AHB --------------------------------------------------------*/ +#define SYSCTRL_AHB_PERIPH_CORDIC bv8 +#define SYSCTRL_AHB_PERIPH_GPIOF bv7 +#define SYSCTRL_AHB_PERIPH_GPIOC bv6 +#define SYSCTRL_AHB_PERIPH_GPIOB bv5 +#define SYSCTRL_AHB_PERIPH_GPIOA bv4 +#define SYSCTRL_AHB_PERIPH_EAU bv3 +#define SYSCTRL_AHB_PERIPH_CRC bv2 +#define SYSCTRL_AHB_PERIPH_FLASH bv1 +#define SYSCTRL_AHB_PERIPH_DMA bv0 +#define IS_SYSCTRL_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFE00 ) == 0x00) && ((PERIPH) != 0x00)) + + +#define __SYSCTRL_CORDIC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, (SYSCTRL_KEY | SYSCTRL_AHB_PERIPH_CORDIC)) +#define __SYSCTRL_GPIOF_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, (SYSCTRL_KEY | SYSCTRL_AHB_PERIPH_GPIOF)) +#define __SYSCTRL_GPIOC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, (SYSCTRL_KEY | SYSCTRL_AHB_PERIPH_GPIOC)) +#define __SYSCTRL_GPIOB_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, (SYSCTRL_KEY | SYSCTRL_AHB_PERIPH_GPIOB)) +#define __SYSCTRL_GPIOA_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, (SYSCTRL_KEY | SYSCTRL_AHB_PERIPH_GPIOA)) +#define __SYSCTRL_EAU_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, (SYSCTRL_KEY | SYSCTRL_AHB_PERIPH_EAU)) +#define __SYSCTRL_CRC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, (SYSCTRL_KEY | SYSCTRL_AHB_PERIPH_CRC)) +#define __SYSCTRL_FLASH_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, (SYSCTRL_KEY | SYSCTRL_AHB_PERIPH_FLASH)) +#define __SYSCTRL_DMA_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->AHBEN, (SYSCTRL_KEY | SYSCTRL_AHB_PERIPH_DMA)) + +#define __SYSCTRL_CORDIC_CLK_DISABLE() (CW_SYSCTRL->AHBEN = (SYSCTRL_KEY | (CW_SYSCTRL->AHBEN & (~SYSCTRL_AHB_PERIPH_CORDIC)))) +#define __SYSCTRL_GPIOF_CLK_DISABLE() (CW_SYSCTRL->AHBEN = (SYSCTRL_KEY | (CW_SYSCTRL->AHBEN & (~SYSCTRL_AHB_PERIPH_GPIOF)))) +#define __SYSCTRL_GPIOC_CLK_DISABLE() (CW_SYSCTRL->AHBEN = (SYSCTRL_KEY | (CW_SYSCTRL->AHBEN & (~SYSCTRL_AHB_PERIPH_GPIOC)))) +#define __SYSCTRL_GPIOB_CLK_DISABLE() (CW_SYSCTRL->AHBEN = (SYSCTRL_KEY | (CW_SYSCTRL->AHBEN & (~SYSCTRL_AHB_PERIPH_GPIOB)))) +#define __SYSCTRL_GPIOA_CLK_DISABLE() (CW_SYSCTRL->AHBEN = (SYSCTRL_KEY | (CW_SYSCTRL->AHBEN & (~SYSCTRL_AHB_PERIPH_GPIOA)))) +#define __SYSCTRL_EAU_CLK_DISABLE() (CW_SYSCTRL->AHBEN = (SYSCTRL_KEY | (CW_SYSCTRL->AHBEN & (~SYSCTRL_AHB_PERIPH_EAU)))) +#define __SYSCTRL_CRC_CLK_DISABLE() (CW_SYSCTRL->AHBEN = (SYSCTRL_KEY | (CW_SYSCTRL->AHBEN & (~SYSCTRL_AHB_PERIPH_CRC)))) +#define __SYSCTRL_FLASH_CLK_DISABLE() (CW_SYSCTRL->AHBEN = (SYSCTRL_KEY | (CW_SYSCTRL->AHBEN & (~SYSCTRL_AHB_PERIPH_FLASH)))) +#define __SYSCTRL_DMA_CLK_DISABLE() (CW_SYSCTRL->AHBEN = (SYSCTRL_KEY | (CW_SYSCTRL->AHBEN & (~SYSCTRL_AHB_PERIPH_DMA)))) + +/* SYSCTRL APB1 --------------------------------------------------------*/ +#define SYSCTRL_APB1_PERIPH_SPI3 bv14 +#define SYSCTRL_APB1_PERIPH_SPI2 bv13 +#define SYSCTRL_APB1_PERIPH_GTIM4 bv12 +#define SYSCTRL_APB1_PERIPH_GTIM3 bv11 +#define SYSCTRL_APB1_PERIPH_UART3 bv8 +#define SYSCTRL_APB1_PERIPH_GTIM2 bv7 +#define SYSCTRL_APB1_PERIPH_GTIM1 bv6 +#define SYSCTRL_APB1_PERIPH_ATIM bv5 +#define SYSCTRL_APB1_PERIPH_UART2 bv4 +#define SYSCTRL_APB1_PERIPH_UART1 bv3 +#define SYSCTRL_APB1_PERIPH_SPI1 bv2 +#define SYSCTRL_APB1_PERIPH_VC bv1 +#define SYSCTRL_APB1_PERIPH_ADC bv0 +#define IS_SYSCTRL_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF8600) == 0x00) && ((PERIPH) != 0x00)) + +#define __SYSCTRL_SPI3_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, (SYSCTRL_KEY | SYSCTRL_APB1_PERIPH_SPI3)) +#define __SYSCTRL_SPI2_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, (SYSCTRL_KEY | SYSCTRL_APB1_PERIPH_SPI2)) +#define __SYSCTRL_GTIM4_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, (SYSCTRL_KEY | SYSCTRL_APB1_PERIPH_GTIM4)) +#define __SYSCTRL_GTIM3_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, (SYSCTRL_KEY | SYSCTRL_APB1_PERIPH_GTIM3)) +#define __SYSCTRL_UART3_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, (SYSCTRL_KEY | SYSCTRL_APB1_PERIPH_UART3)) +#define __SYSCTRL_GTIM2_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, (SYSCTRL_KEY | SYSCTRL_APB1_PERIPH_GTIM2)) +#define __SYSCTRL_GTIM1_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, (SYSCTRL_KEY | SYSCTRL_APB1_PERIPH_GTIM1)) +#define __SYSCTRL_ATIM_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, (SYSCTRL_KEY | SYSCTRL_APB1_PERIPH_ATIM)) +#define __SYSCTRL_UART2_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, (SYSCTRL_KEY | SYSCTRL_APB1_PERIPH_UART2)) +#define __SYSCTRL_UART1_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, (SYSCTRL_KEY | SYSCTRL_APB1_PERIPH_UART1)) +#define __SYSCTRL_SPI1_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, (SYSCTRL_KEY | SYSCTRL_APB1_PERIPH_SPI1)) +#define __SYSCTRL_VC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, (SYSCTRL_KEY | SYSCTRL_APB1_PERIPH_VC)) +#define __SYSCTRL_ADC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN1, (SYSCTRL_KEY | SYSCTRL_APB1_PERIPH_ADC)) + +#define __SYSCTRL_SPI3_CLK_DISABLE() (CW_SYSCTRL->APBEN1 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN1 & (~SYSCTRL_APB1_PERIPH_SPI3)))) +#define __SYSCTRL_SPI2_CLK_DISABLE() (CW_SYSCTRL->APBEN1 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN1 & (~SYSCTRL_APB1_PERIPH_SPI2)))) +#define __SYSCTRL_GTIM4_CLK_DISABLE() (CW_SYSCTRL->APBEN1 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN1 & (~SYSCTRL_APB1_PERIPH_GTIM4)))) +#define __SYSCTRL_GTIM3_CLK_DISABLE() (CW_SYSCTRL->APBEN1 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN1 & (~SYSCTRL_APB1_PERIPH_GTIM3)))) +#define __SYSCTRL_UART3_CLK_DISABLE() (CW_SYSCTRL->APBEN1 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN1 & (~SYSCTRL_APB1_PERIPH_UART3)))) +#define __SYSCTRL_GTIM2_CLK_DISABLE() (CW_SYSCTRL->APBEN1 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN1 & (~SYSCTRL_APB1_PERIPH_GTIM2)))) +#define __SYSCTRL_GTIM1_CLK_DISABLE() (CW_SYSCTRL->APBEN1 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN1 & (~SYSCTRL_APB1_PERIPH_GTIM1)))) +#define __SYSCTRL_ATIM_CLK_DISABLE() (CW_SYSCTRL->APBEN1 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN1 & (~SYSCTRL_APB1_PERIPH_ATIM)))) +#define __SYSCTRL_UART2_CLK_DISABLE() (CW_SYSCTRL->APBEN1 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN1 & (~SYSCTRL_APB1_PERIPH_UART2)))) +#define __SYSCTRL_UART1_CLK_DISABLE() (CW_SYSCTRL->APBEN1 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN1 & (~SYSCTRL_APB1_PERIPH_UART1)))) +#define __SYSCTRL_SPI1_CLK_DISABLE() (CW_SYSCTRL->APBEN1 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN1 & (~SYSCTRL_APB1_PERIPH_SPI1)))) +#define __SYSCTRL_VC_CLK_DISABLE() (CW_SYSCTRL->APBEN1 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN1 & (~SYSCTRL_APB1_PERIPH_VC)))) +#define __SYSCTRL_ADC_CLK_DISABLE() (CW_SYSCTRL->APBEN1 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN1 & (~SYSCTRL_APB1_PERIPH_ADC)))) + + +/* SYSCTRL APB2 --------------------------------------------------------*/ +#define SYSCTRL_APB2_PERIPH_HALLTIM bv12 +#define SYSCTRL_APB2_PERIPH_I2C2 bv11 +#define SYSCTRL_APB2_PERIPH_DAC bv10 +#define SYSCTRL_APB2_PERIPH_OPA bv9 +#define SYSCTRL_APB2_PERIPH_LPTIM bv7 +#define SYSCTRL_APB2_PERIPH_I2C1 bv6 +#define SYSCTRL_APB2_PERIPH_WWDT bv5 +#define SYSCTRL_APB2_PERIPH_IWDT bv4 +#define SYSCTRL_APB2_PERIPH_BTIM123 bv2 +#define SYSCTRL_APB2_PERIPH_RTC bv1 +#define IS_SYSCTRL_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFC109) == 0x00) && ((PERIPH) != 0x00)) + +#define __SYSCTRL_HALLTIM_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, (SYSCTRL_KEY | SYSCTRL_APB2_PERIPH_HALLTIM)) +#define __SYSCTRL_I2C2_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, (SYSCTRL_KEY | SYSCTRL_APB2_PERIPH_I2C2)) +#define __SYSCTRL_DAC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, (SYSCTRL_KEY | SYSCTRL_APB2_PERIPH_DAC)) +#define __SYSCTRL_OPA_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, (SYSCTRL_KEY | SYSCTRL_APB2_PERIPH_OPA)) +#define __SYSCTRL_LPTIM_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, (SYSCTRL_KEY | SYSCTRL_APB2_PERIPH_LPTIM)) +#define __SYSCTRL_I2C1_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, (SYSCTRL_KEY | SYSCTRL_APB2_PERIPH_I2C1)) +#define __SYSCTRL_WWDT_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, (SYSCTRL_KEY | SYSCTRL_APB2_PERIPH_WWDT)) +#define __SYSCTRL_IWDT_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, (SYSCTRL_KEY | SYSCTRL_APB2_PERIPH_IWDT)) +#define __SYSCTRL_BTIM123_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, (SYSCTRL_KEY | SYSCTRL_APB2_PERIPH_BTIM123)) +#define __SYSCTRL_RTC_CLK_ENABLE() REGBITS_SET(CW_SYSCTRL->APBEN2, (SYSCTRL_KEY | SYSCTRL_APB2_PERIPH_RTC)) + +#define __SYSCTRL_HALLTIM_CLK_DISABLE() (CW_SYSCTRL->APBEN2 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN2 & (~SYSCTRL_APB2_PERIPH_HALLTIM)))) +#define __SYSCTRL_I2C2_CLK_DISABLE() (CW_SYSCTRL->APBEN2 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN2 & (~SYSCTRL_APB2_PERIPH_I2C2)))) +#define __SYSCTRL_DAC_CLK_DISABLE() (CW_SYSCTRL->APBEN2 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN2 & (~SYSCTRL_APB2_PERIPH_DAC)))) +#define __SYSCTRL_OPA_CLK_DISABLE() (CW_SYSCTRL->APBEN2 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN2 & (~SYSCTRL_APB2_PERIPH_OPA)))) +#define __SYSCTRL_LPTIM_CLK_DISABLE() (CW_SYSCTRL->APBEN2 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN2 & (~SYSCTRL_APB2_PERIPH_LPTIM)))) +#define __SYSCTRL_I2C1_CLK_DISABLE() (CW_SYSCTRL->APBEN2 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN2 & (~SYSCTRL_APB2_PERIPH_I2C1)))) +#define __SYSCTRL_WWDT_CLK_DISABLE() (CW_SYSCTRL->APBEN2 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN2 & (~SYSCTRL_APB2_PERIPH_WWDT)))) +#define __SYSCTRL_IWDT_CLK_DISABLE() (CW_SYSCTRL->APBEN2 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN2 & (~SYSCTRL_APB2_PERIPH_IWDT)))) +#define __SYSCTRL_BTIM123_CLK_DISABLE() (CW_SYSCTRL->APBEN2 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN2 & (~SYSCTRL_APB2_PERIPH_BTIM123)))) +#define __SYSCTRL_RTC_CLK_DISABLE() (CW_SYSCTRL->APBEN2 = (SYSCTRL_KEY | (CW_SYSCTRL->APBEN2 & (~SYSCTRL_APB2_PERIPH_RTC)))) + +/* SYSCTRL AHB RST --------------------------------------------------------*/ +#define __SYSCTRL_CORDIC_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_CORDIC)) +#define __SYSCTRL_GPIOF_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_GPIOF)) +#define __SYSCTRL_GPIOC_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_GPIOC)) +#define __SYSCTRL_GPIOB_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_GPIOB)) +#define __SYSCTRL_GPIOA_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_GPIOA)) +#define __SYSCTRL_EAU_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_EAU)) +#define __SYSCTRL_CRC_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_CRC)) +#define __SYSCTRL_FLASH_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_FLASH)) +#define __SYSCTRL_DMA_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_DMA)) + +#define __SYSCTRL_CORDIC_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_CORDIC)) +#define __SYSCTRL_GPIOF_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_GPIOF)) +#define __SYSCTRL_GPIOC_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_GPIOC)) +#define __SYSCTRL_GPIOB_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_GPIOB)) +#define __SYSCTRL_GPIOA_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_GPIOA)) +#define __SYSCTRL_EAU_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_EAU)) +#define __SYSCTRL_CRC_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_CRC)) +#define __SYSCTRL_FLASH_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_FLASH)) +#define __SYSCTRL_DMA_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->AHBRST, (SYSCTRL_AHB_PERIPH_DMA)) + +/* SYSCTRL APB1 RST --------------------------------------------------------*/ +#define __SYSCTRL_SPI3_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_SPI3)) +#define __SYSCTRL_SPI2_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_SPI2)) +#define __SYSCTRL_GTIM4_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_GTIM4)) +#define __SYSCTRL_GTIM3_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_GTIM3)) +#define __SYSCTRL_UART3_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_UART3)) +#define __SYSCTRL_GTIM2_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_GTIM2)) +#define __SYSCTRL_GTIM1_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_GTIM1)) +#define __SYSCTRL_ATIM_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_ATIM)) +#define __SYSCTRL_UART2_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_UART2)) +#define __SYSCTRL_UART1_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_UART1)) +#define __SYSCTRL_SPI1_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_SPI1)) +#define __SYSCTRL_VC_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_VC)) +#define __SYSCTRL_ADC_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_ADC)) + +#define __SYSCTRL_SPI3_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_SPI3)) +#define __SYSCTRL_SPI2_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_SPI2)) +#define __SYSCTRL_GTIM4_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_GTIM4)) +#define __SYSCTRL_GTIM3_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_GTIM3)) +#define __SYSCTRL_UART3_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_UART3)) +#define __SYSCTRL_GTIM2_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_GTIM2)) +#define __SYSCTRL_GTIM1_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_GTIM1)) +#define __SYSCTRL_ATIM_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_ATIM)) +#define __SYSCTRL_UART2_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_UART2)) +#define __SYSCTRL_UART1_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_UART1)) +#define __SYSCTRL_SPI1_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_SPI1)) +#define __SYSCTRL_VC_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_VC)) +#define __SYSCTRL_ADC_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST1, (SYSCTRL_APB1_PERIPH_ADC)) + +/* SYSCTRL APB2 RST --------------------------------------------------------*/ +#define __SYSCTRL_HALLTIM_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_HALLTIM)) +#define __SYSCTRL_I2C2_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_I2C2)) +#define __SYSCTRL_DAC_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_DAC)) +#define __SYSCTRL_OPA_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_OPA)) +#define __SYSCTRL_LPTIM_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_LPTIM)) +#define __SYSCTRL_I2C1_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_I2C1)) +#define __SYSCTRL_WWDT_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_WWDT)) +#define __SYSCTRL_IWDT_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_IWDT)) +#define __SYSCTRL_BTIM123_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_BTIM123)) +#define __SYSCTRL_RTC_RST_ENABLE() REGBITS_CLR(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_RTC)) + +#define __SYSCTRL_HALLTIM_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_HALLTIM)) +#define __SYSCTRL_I2C2_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_I2C2)) +#define __SYSCTRL_DAC_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_DAC)) +#define __SYSCTRL_OPA_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_OPA)) +#define __SYSCTRL_LPTIM_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_LPTIM)) +#define __SYSCTRL_I2C1_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_I2C1)) +#define __SYSCTRL_WWDT_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_WWDT)) +#define __SYSCTRL_IWDT_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_IWDT)) +#define __SYSCTRL_BTIM123_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_BTIM123)) +#define __SYSCTRL_RTC_RST_DISABLE() REGBITS_SET(CW_SYSCTRL->APBRST2, (SYSCTRL_APB2_PERIPH_RTC)) + + + + +#define SYSCTRL_MCO_DIV1 (0x00U) +#define SYSCTRL_MCO_DIV2 ((uint8_t)(0x01U << SYSCTRL_MCO_DIV_Pos)) +#define SYSCTRL_MCO_DIV4 ((uint8_t)(0x02U << SYSCTRL_MCO_DIV_Pos)) +#define SYSCTRL_MCO_DIV8 ((uint8_t)(0x03U << SYSCTRL_MCO_DIV_Pos)) +#define SYSCTRL_MCO_DIV16 ((uint8_t)(0x04U << SYSCTRL_MCO_DIV_Pos)) +#define SYSCTRL_MCO_DIV32 ((uint8_t)(0x05U << SYSCTRL_MCO_DIV_Pos)) +#define SYSCTRL_MCO_DIV64 ((uint8_t)(0x06U << SYSCTRL_MCO_DIV_Pos)) +#define SYSCTRL_MCO_DIV128 ((uint8_t)(0x07U << SYSCTRL_MCO_DIV_Pos)) +#define SYSCTRL_MCO_DIV256 ((uint8_t)(0x08U << SYSCTRL_MCO_DIV_Pos)) +#define SYSCTRL_MCO_DIV512 ((uint8_t)(0x09U << SYSCTRL_MCO_DIV_Pos)) +#define SYSCTRL_MCO_DIV1024 ((uint8_t)(0x0AU << SYSCTRL_MCO_DIV_Pos)) +#define SYSCTRL_MCO_DIV2048 ((uint8_t)(0x0BU << SYSCTRL_MCO_DIV_Pos)) +#define SYSCTRL_MCO_DIV4096 ((uint8_t)(0x0CU << SYSCTRL_MCO_DIV_Pos)) +#define SYSCTRL_MCO_DIV8192 ((uint8_t)(0x0DU << SYSCTRL_MCO_DIV_Pos)) +#define IS_SYSCTRL_MCO_DIV(INSTANCE) ((INSTANCE) <= 0x0DU) + +#define SYSCTRL_MCO_SRC_NONE (0x00U) +#define SYSCTRL_MCO_SRC_HCLK (0x01U) +#define SYSCTRL_MCO_SRC_PCLK (0x02U) +#define SYSCTRL_MCO_SRC_HSI (0x03U) +#define SYSCTRL_MCO_SRC_LSI (0x04U) +#define SYSCTRL_MCO_SRC_HSE (0x05U) +#define SYSCTRL_MCO_SRC_LSE (0x06U) +#define SYSCTRL_MCO_SRC_PLL (0x07U) +#define SYSCTRL_MCO_SRC_RC8K (0x09U) + +#define IS_SYSCTRL_MCO_SRC(INSTANCE) (((INSTANCE) == SYSCTRL_MCO_SRC_NONE) || \ + ((INSTANCE) == SYSCTRL_MCO_SRC_HCLK) || \ + ((INSTANCE) == SYSCTRL_MCO_SRC_PCLK) || \ + ((INSTANCE) == SYSCTRL_MCO_SRC_HSI) || \ + ((INSTANCE) == SYSCTRL_MCO_SRC_LSI) || \ + ((INSTANCE) == SYSCTRL_MCO_SRC_HSE) || \ + ((INSTANCE) == SYSCTRL_MCO_SRC_LSE) || \ + ((INSTANCE) == SYSCTRL_MCO_SRC_PLL) || \ + ((INSTANCE) == SYSCTRL_MCO_SRC_RC8K)) + +// #define RCC_HSE_FLT_CLOSE (0x00000000U) +// #define RCC_HSE_FLT_OPEN (0x01000000U) +//================================================================================== +extern void SYSCTRL_HCLKPRS_Config(uint32_t HCLKPRS); +extern void SYSCTRL_PCLKPRS_Config(uint32_t PCLKPRS); +extern void SYSCTRL_SYSCLKSRC_Config(uint32_t SYSCLKSRC); +extern void SYSCTRL_CCS_Config(uint32_t CCS, FunctionalState NewState); +extern void SYSCTRL_LSELOCK_Config(uint32_t LSELOCK); +extern void SYSCTRL_WAKEUPCLK_Config(uint32_t WAKEUPCLK); +extern void SYSCTRL_LOCKUP_Config(uint32_t LOCKUP); +extern void SYSCTRL_SWDIO_Config(uint32_t SWDIO); +extern void SYSCTRL_BrakeConfig(uint32_t BrakeType, FunctionalState NewState); +extern int SYSCTRL_DeInit(void); +extern void SYSCTRL_SystemCoreClockUpdate(uint32_t NewFreq); +extern int SYSCTRL_HSI_Enable(uint32_t HSIDiv); +extern void SYSCTRL_HSI_Disable(void); +extern int SYSCTRL_LSI_Enable(void); +extern void SYSCTRL_LSI_Disable(void); +extern void SYSCTRL_HSEWaitClockSet(uint32_t WaitClock); +extern void SYSCTRL_HSEEnablePinPolSet(uint32_t Polarity); +int SYSCTRL_HSE_Enable(uint32_t Mode, uint32_t FreqIn, uint8_t Driver, uint32_t Flt); +void SYSCTRL_HSE_Disable(void); +extern int SYSCTRL_LSE_Enable(uint32_t Mode, uint8_t Driver); +extern void SYSCTRL_LSE_Disable(void); +extern int SYSCTRL_PLL_Enable(PLL_InitTypeDef *PLL_InitStruct); +void SYSCTRL_PLL_Disable(void); +extern int SYSCTRL_SysClk_Switch(uint32_t NewClk); +extern void SYSCTRL_ITConfig(uint32_t SYSCTRL_IT, FunctionalState NewState); +extern ITStatus SYSCTRL_GetITStatus(uint32_t SYSCTRL_IT); +extern void SYSCTRL_ClearITPendingBit(uint32_t SYSCTRL_IT); +extern FlagStatus SYSCTRL_GetStableFlag(uint32_t SYSCTRL_STABLEFLAG); +extern uint32_t SYSCTRL_GetAllStableFlag(void); +extern void SYSCTRL_AHBPeriphClk_Enable(uint32_t Periph, FunctionalState NewState); +extern void SYSCTRL_APBPeriphClk_Enable1(uint32_t Periph, FunctionalState NewState); +extern void SYSCTRL_APBPeriphClk_Enable2(uint32_t Periph, FunctionalState NewState); +extern void SYSCTRL_AHBPeriphReset(uint32_t Periph, FunctionalState NewState); +extern void SYSCTRL_APBPeriphReset1(uint32_t Periph, FunctionalState NewState); +extern void SYSCTRL_APBPeriphReset2(uint32_t Periph, FunctionalState NewState); +extern FlagStatus SYSCTRL_GetRstFlag(uint32_t SYSCTRL_RSTFLAG); +extern uint32_t SYSCTRL_GetAllRstFlag(void); +extern void SYSCTRL_ClearRstFlag(uint32_t SYSCTRL_RSTFLAG); + +extern void SYSCTRL_PCLK_OUT(void); +extern void SYSCTRL_MCO_OUT(uint8_t Source, uint8_t Div); + +extern uint32_t SYSCTRL_GetHClkFreq(void); +extern uint32_t SYSCTRL_GetPClkFreq(void); + +void SYSCTRL_GotoSleep(void); +void SYSCTRL_GotoDeepSleep(void); +void SYSCTRL_ConfigSleepOnExit(FunctionalState state); + +#ifdef __cplusplus +} +#endif + +#endif /* __CW32L012_SYSCTRL_H */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_systick.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_systick.h new file mode 100644 index 0000000..d06c6cb --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_systick.h @@ -0,0 +1,77 @@ +/** + * @file cw32l012_systick.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_HAL_H +#define __CW32L012_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "base_types.h" +#include "cw32l012.h" + +/* Exported types ------------------------------------------------------------*/ + +typedef enum +{ + TICK_FREQ_10HZ = 100U, + TICK_FREQ_100HZ = 10U, + TICK_FREQ_1KHZ = 1U, + TICK_FREQ_DEFAULT = TICK_FREQ_1KHZ +} TickFreqTypeDef; + +#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */ +#define MAX_SYSTICK_DELAY 0xFFFFFFFFU +#define IS_TICKFREQ(FREQ) (((FREQ) == TICK_FREQ_10HZ) || \ + ((FREQ) == TICK_FREQ_100HZ) || \ + ((FREQ) == TICK_FREQ_1KHZ)) + +/* Exported functions --------------------------------------------------------*/ +void InitTick(uint32_t HclkFreq); +void SysTickDelay(uint32_t Delay); +uint32_t GetTick(void); +void SuspendTick(void); +void ResumeTick(void); + +/* Exported variables ---------------------------------------------------------*/ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern TickFreqTypeDef uwTickFreq; + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CW32L012_HAL_H */ + +/************************ (C) COPYRIGHT CW *****END OF FILE****/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_uart.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_uart.h new file mode 100644 index 0000000..c4e5027 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_uart.h @@ -0,0 +1,439 @@ +/******************************************************************************* + * @file cw32l012_uart.h + * @brief CW32L012 UART驱动头文件 + * @version 1.0 + * @date + * @copyright Copyright (c) 2025 + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + ********************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_UART_H +#define __CW32L012_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "system_cw32l012.h" +#include "cw32l012_dma.h" + +/****************************************************************************** + * type definitions ('typedef') + ******************************************************************************/ + +/** + * @brief UART Init Structure definition + */ + +typedef struct +{ + uint32_t UART_BaudRate; /*!< 波特率 + 计算公式: + - UART_Over = 00， BaudRate = UCLK / (16 * BRRI + BRRF) + - UART_Over = 01， BaudRate = UCLK / (8 * BRRI) + - UART_Over = 10， BaudRate = UCLK / (4 * BRRI) + - UART_Over = 11， BaudRate = (256 * UCLK) / BRRI */ + + uint16_t UART_Over; /*!< 采样方式 + 参数取值 @ref UART_Over */ + + uint16_t UART_Source; /*!< 传输时钟源UCLK + 参数取值 @ref UART_Source */ + + uint32_t UART_UclkFreq; /*!< 传输时钟UCLK频率 Hz */ + + uint16_t UART_StartBit; /*!< 起始位判定方式 + 参数取值 @ref UART_Start_Bit */ + + uint16_t UART_StopBits; /*!< 停止位长度 + 参数取值 @ref UART_Stop_Bits */ + + uint16_t UART_Parity; /*!< 校验方式 + 参数取值 @ref UART_Parity + @note 当设置为无校验时，数据字长为8位； + 当设置为有校验时，数据字长自动设置为9位 */ + + uint16_t UART_Mode; /*!< 发送/接收使能 + 参数取值 @ref UART_Mode */ + + uint16_t UART_HardwareFlowControl; /*!< 硬件流控 + 参数取值 @ref UART_Hardware_Flow_Control */ +} UART_InitTypeDef; + +/** + * @brief UART Clock Init Structure definition + */ + +typedef struct +{ + uint16_t UART_Clock; /*!< UART同步模式使能/失能 + 参数取值 @ref UART_Clock */ + + uint16_t UART_Source; /*!< 传输时钟源UCLK + 参数取值 @ref UART_Source */ +} UART_ClockInitTypeDef; + +typedef struct +{ + uint32_t UART_ClockSource; /*!< 时钟源选择 */ + uint32_t UART_ClockFreq; /*!< 时钟频率 Hz */ + uint32_t UART_BaudRate; /*!< 波特率 */ + uint32_t UART_TransmitOrder; /*!< 发送顺序 (0: LSB first, 1: MSB first) + 参数取值 @ref UART_Transmit_Order */ +} UART_SyncModeInitTypeDef; + +/** + * @brief UART 状态枚举定义 + */ +typedef enum +{ + UART_STATUS_OK = 0x00, /*!< UART 操作成功 */ + UART_STATUS_ERROR = 0x01, /*!< UART 操作出错 */ + UART_STATUS_BUSY = 0x02, /*!< UART 忙碌 */ + UART_STATUS_TIMEOUT = 0x03, /*!< UART 操作超时 */ + UART_STATUS_PE = 0x04, /*!< UART 奇偶校验错误 */ + UART_STATUS_FE = 0x05, /*!< UART 帧错误 */ + UART_STATUS_NE = 0x06, /*!< UART 噪声错误 */ + UART_STATUS_ORE = 0x07 /*!< UART 过载错误 */ +} UART_StatusTypeDef; + +// TIMCR位域定义 +typedef enum { + UART_TIMER_STOP_IMMEDIATELY = 0x0, // 立即停止定时器 + UART_TIMER_WAIT_FOR_TIMEOUT = 0x2, // 等待超时检测模式 + UART_TIMER_RECEIVE_IDLE = 0x3, // 接收空闲检测模式 + UART_TIMER_AUTO_BAUD_RATE_1 = 0x4, // 自动波特率检测模式1 + UART_TIMER_AUTO_BAUD_RATE_2 = 0x5, // 自动波特率检测模式2 + UART_TIMER_GENERAL_PURPOSE = 0x7 // 通用定时模式 +} UART_TimerModeTypeDef; + +/** + * @brief UART 自动波特率检测模式 + * + */ +typedef enum { + UART_AUTO_BAUD_RATE_MODE_1 = 0x0, // 自动波特率检测模式1 + UART_AUTO_BAUD_RATE_MODE_2 = 0x1 // 自动波特率检测模式2 +} UART_AutoBaudRateModeTypeDef; + +/** + * @brief UART LIN 模式间隔段检测长度 + */ +typedef enum { + UART_LIN_BREAK_DETECT_LENGTH_10B = 0x0, // 10位 + UART_LIN_BREAK_DETECT_LENGTH_11B = 0x1 // 11位 +} UART_LINBreakDetectLengthTypeDef; + + +/** + * @brief UART LIN 模式间隔段发送长度 + */ +typedef enum { + UART_LIN_BREAK_SEND_LENGTH_13B = 0x040D, // 13位 + UART_LIN_BREAK_SEND_LENGTH_14B = 0x040E, // 14位 + UART_LIN_BREAK_SEND_LENGTH_15B = 0x040F, // 15位 + UART_LIN_BREAK_SEND_LENGTH_16B = 0x0410, // 16位 + UART_LIN_BREAK_SEND_LENGTH_17B = 0x0411 // 17位 +} UART_LINBreakSendLengthTypeDef; + +/****************************************************************************** + * pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** @defgroup UART_Over + * @{ + */ + +#define UART_Over_16 (0u << UARTx_CR1_OVER_Pos) +#define UART_Over_8 (1u << UARTx_CR1_OVER_Pos) +#define UART_Over_4 (2u << UARTx_CR1_OVER_Pos) +#define UART_Over_sp (3u << UARTx_CR1_OVER_Pos) +#define IS_UART_Over(Over) (((Over) == UART_Over_16) || \ + ((Over) == UART_Over_8) || \ + ((Over) == UART_Over_4) || \ + ((Over) == UART_Over_sp)) + +/** @defgroup UART_Source + * @{ + */ + +#define UART_Source_PCLK (1u << UARTx_CR1_SOURCE_Pos) +#define UART_Source_LSE (2u << UARTx_CR1_SOURCE_Pos) +#define UART_Source_LSI (3u << UARTx_CR1_SOURCE_Pos) +#define IS_UART_Source(Source) (((Source) == UART_Source_PCLK) || \ + ((Source) == UART_Source_LSE) || \ + ((Source) == UART_Source_LSI)) + +/** @defgroup UART_Start_Bit + * @{ + */ + +#define UART_StartBit_FE (0u) //RXD下降沿 +#define UART_StartBit_LL (1u << UARTx_CR1_START_Pos) //RXD低电平 +#define IS_UART_StartBit(StartBit) (((StartBit) == UART_StartBit_FE) || \ + ((StartBit) == UART_StartBit_LL)) + +/** @defgroup UART_Stop_Bits + * @{ + */ + +#define UART_StopBits_1 (0u) +#define UART_StopBits_2 (1u << UARTx_CR1_STOP_Pos) +#define UART_StopBits_1_5 (2u << UARTx_CR1_STOP_Pos) +#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \ + ((STOPBITS) == UART_StopBits_2) || \ + ((STOPBITS) == UART_StopBits_1_5)) + +/** @defgroup UART_Parity + * @{ + */ + +#define UART_Parity_No (0u) +#define UART_Parity_Even (2u << UARTx_CR1_PARITY_Pos) +#define UART_Parity_Odd (3u << UARTx_CR1_PARITY_Pos) +#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \ + ((PARITY) == UART_Parity_Even) || \ + ((PARITY) == UART_Parity_Odd)) + +/** @defgroup UART_Transmit_Order + * + * @brief 发送顺序 + */ +#define UART_Transmit_Order_MSB (1u << UARTx_CR1_MSBF_Pos) +#define UART_Transmit_Order_LSB (0u) + +/** @defgroup UART_Mode + * @{ + */ + +#define UART_Mode_Tx ((uint16_t)0x0001) +#define UART_Mode_Rx ((uint16_t)0x0002) +#define IS_UART_MODE(MODE) ((((MODE) & (uint16_t)0xFFFC) == 0x00) && ((MODE) != (uint16_t)0x00)) + +/** @defgroup UART_Hardware_Flow_Control + * @{ + */ + +#define UART_HardwareFlowControl_None ((uint16_t)0x0000) +#define UART_HardwareFlowControl_RTS ((uint16_t)0x0008) +#define UART_HardwareFlowControl_CTS ((uint16_t)0x0004) +#define UART_HardwareFlowControl_RTS_CTS ((uint16_t)0x000C) +#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == UART_HardwareFlowControl_None) || \ + ((CONTROL) == UART_HardwareFlowControl_RTS) || \ + ((CONTROL) == UART_HardwareFlowControl_CTS) || \ + ((CONTROL) == UART_HardwareFlowControl_RTS_CTS)) + +/** @defgroup UART_Clock + * @{ + */ + +#define UART_Clock_Disable ((uint16_t)0x0000) +#define UART_Clock_Enable ((uint16_t)0x0040) +#define IS_UART_CLOCK(CLOCK) (((CLOCK) == UART_Clock_Disable) || \ + ((CLOCK) == UART_Clock_Enable)) + +/** @defgroup UART_Inversion_Pins + * @{ + */ + +#define UART_InvPin_Tx ((uint16_t)0x0020) +#define UART_InvPin_Rx ((uint16_t)0x0010) +#define IS_UART_INVERSTION_PIN(INVPIN) ((((INVPIN) & (uint16_t)0xFFCF) == 0x00) && ((INVPIN) != (uint16_t)0x00)) + +/** @defgroup UART_DMA_Requests + * @{ + */ + +#define UART_DMAReq_Tx ((uint16_t)0x0080) +#define UART_DMAReq_Rx ((uint16_t)0x0040) +#define IS_UART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + + +/** @defgroup UART_Timer_Mode + * @{ + */ + +#define UART_TimerMode_Stop (0U) +#define UART_TimerMode_TimeOut (2U << UARTx_CR2_TIMCR_Pos) +#define UART_TimerMode_Idle (3U << UARTx_CR2_TIMCR_Pos) +#define UART_TimerMode_AutoBaudRate1 (5U << UARTx_CR2_TIMCR_Pos) +#define UART_TimerMode_AutoBaudRate2 (6U << UARTx_CR2_TIMCR_Pos) +#define UART_TimerMode_GeneralTimer (7U << UARTx_CR2_TIMCR_Pos) +#define IS_UART_TIMER_MODE(MODE) (((MODE) == UART_TimerMode_Stop) || \ + ((MODE) == UART_TimerMode_TimeOut) ||\ + ((MODE) == UART_TimerMode_Idle) || \ + ((MODE) == UART_TimerMode_AutoBaudRate1) ||\ + ((MODE) == UART_TimerMode_AutoBaudRate2) || \ + ((MODE) == UART_TimerMode_GeneralTimer)) + +/** @defgroup UART_Interrupt + * @{ + */ +#define UART_IT_RXMATCH ((uint16_t)0x1000) +#define UART_IT_ORE ((uint16_t)0x0800) +#define UART_IT_NE ((uint16_t)0x0400) +#define UART_IT_PE ((uint16_t)0x0200) +#define UART_IT_FE ((uint16_t)0x0100) +#define UART_IT_CTS ((uint16_t)0x0080) +#define UART_IT_TIMOV ((uint16_t)0x0040) +#define UART_IT_BAUD ((uint16_t)0x0020) +#define UART_IT_RXBRK ((uint16_t)0x0010) +#define UART_IT_RXIDLE ((uint16_t)0x0008) +#define UART_IT_RC ((uint16_t)0x0004) +#define UART_IT_TC ((uint16_t)0x0002) +#define UART_IT_TXE ((uint16_t)0x0001) +#define UART_IT_ALL (0x1FFF) +#define IS_UART_IT(IT) ((((IT) & (uint16_t)0xE000) == 0x00) && ((IT) != (uint16_t)0x00)) +#define IS_UART_CLEAR_IT(IT) ((((IT) & (uint16_t)0xE000) == 0x00) && ((IT) != (uint16_t)0x00)) + +/** @defgroup UART_Flags + * @{ + */ + +#define UART_FLAG_CTSLV ((uint16_t)0x8000) +#define UART_FLAG_TXBUSY ((uint16_t)0x4000) +#define UART_FLAG_SLVMATCH ((uint16_t)0x2000) +#define UART_FLAG_RXMATCH ((uint16_t)0x1000) +#define UART_FLAG_ORE ((uint16_t)0x0800) +#define UART_FLAG_NE ((uint16_t)0x0400) +#define UART_FLAG_PE ((uint16_t)0x0200) +#define UART_FLAG_FE ((uint16_t)0x0100) +#define UART_FLAG_CTS ((uint16_t)0x0080) +#define UART_FLAG_TIMOV ((uint16_t)0x0040) +#define UART_FLAG_BAUD ((uint16_t)0x0020) +#define UART_FLAG_RXBRK ((uint16_t)0x0010) +#define UART_FLAG_RXIDLE ((uint16_t)0x0008) +#define UART_FLAG_RC ((uint16_t)0x0004) +#define UART_FLAG_TC ((uint16_t)0x0002) +#define UART_FLAG_TXE ((uint16_t)0x0001) +#define IS_UART_FLAG(FLAG) ((((FLAG) & (uint16_t)0xF000) == 0x00) && ((FLAG) != (uint16_t)0x00)) +#define IS_UART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xF1A1) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_UART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) <= 0x00B71B00)) +#define IS_UART_UCLKFREQ(UCLKFREQ) (((UCLKFREQ) > 0) && ((UCLKFREQ) <= 0x05B8D800)) +#define IS_UART_DATA_16BIT(DATA) ((DATA) <= 0x1FF) +#define IS_UART_DATA_8BIT(DATA) ((DATA) <= 0xFF) +#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xFF) +#define IS_UART_ADDRESSMSK(ADDRESSMSK) ((ADDRESSMSK) <= 0xFF) +#define IS_UART_AUTORELOAD(AUTORELOAD) ((AUTORELOAD) <= 0xFFFFFF) +#define IS_UART_ALL_PERIPH(PERIPH) (((PERIPH) == CW_UART1) || \ + ((PERIPH) == CW_UART2) || \ + ((PERIPH) == CW_UART3)) + + +/****************************************************************************** +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ +extern volatile boolean_t txComplete; +extern volatile boolean_t rxComplete; +extern volatile uint8_t *rxDataPtr; +extern volatile uint8_t *txDataPtr; +extern volatile uint32_t rxDataLen; +extern volatile uint32_t txDataLen; +extern volatile uint32_t rxDataCount; +extern volatile uint32_t txDataCount; +/****************************************************************************** +* Global function prototypes +******************************************************************************/ + +/* 数据收发 */ +void UART_SendData(UART_TypeDef* UARTx, uint16_t Data); +uint16_t UART_ReceiveData(UART_TypeDef* UARTx); +void UART_SendString(UART_TypeDef* UARTx, char* String); +UART_StatusTypeDef UART_TransmitPolling(UART_TypeDef* UARTx, uint8_t *Data, uint32_t length); +UART_StatusTypeDef UART_ReceivePolling(UART_TypeDef* UARTx, uint8_t *Data, uint32_t length); +UART_StatusTypeDef UART_TransmitInterrupt(UART_TypeDef* UARTx, uint8_t *Data, uint32_t length); +UART_StatusTypeDef UART_ReceiveInterrupt(UART_TypeDef* UARTx, uint8_t *Data, uint32_t length); +UART_StatusTypeDef UART_TransmitDMA(UART_TypeDef* UARTx, DMA_ChannelTypeDef DMACHx, uint8_t *Data, uint32_t length); +UART_StatusTypeDef UART_ReceiveDMA(UART_TypeDef* UARTx, DMA_ChannelTypeDef DMACHx, uint8_t *Data, uint32_t length); + + +void UART_SyncMode_SendDataPolling(UART_TypeDef* UARTx, uint8_t *Data, uint32_t length); +void UART_SyncMode_ReceiveDataPolling(UART_TypeDef* UARTx, uint8_t *Data, uint32_t length); + +/* 初始化及配置*/ +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct); +void UART_StructInit(UART_InitTypeDef* UART_InitStruct); +void UART_SyncMode_Init(UART_TypeDef* UARTx, UART_SyncModeInitTypeDef *UART_SyncModeInitStruct); +void UART_ClockInit(UART_TypeDef* UARTx, UART_ClockInitTypeDef* UART_ClockInitStruct); +void UART_ClockStructInit(UART_ClockInitTypeDef* UART_ClockInitStruct); +void UART1_DeInit(void); +void UART2_DeInit(void); +void UART3_DeInit(void); + +/* 中断及标志 */ +void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState); +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT); +void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT); +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG); +void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG); + +/* 发送和接收控制 */ +void UART_DirectionModeCmd(UART_TypeDef* UARTx, uint16_t UART_DirectionMode, FunctionalState NewState); +void UART_InvPinCmd(UART_TypeDef* UARTx, uint16_t UART_InvPin, FunctionalState NewState); +void UART_PinSwapCmd(UART_TypeDef* UARTx, FunctionalState NewState); + +/* 半双工通信 */ +void UART_HalfDuplexCmd(UART_TypeDef* UARTx, FunctionalState NewState); + +/* DMA */ +void UART_DMACmd(UART_TypeDef* UARTx, uint16_t UART_DMAReq, FunctionalState NewState); + +/* 多机通信 */ +void UART_SetMultiMode(UART_TypeDef* UARTx, uint8_t UART_Address, uint8_t UART_AddressMsK); + +/* LIN通信 */ +void UART_LINCmd(UART_TypeDef* UARTx, FunctionalState NewState); +void UART_LINSendBreak(UART_TypeDef* UARTx, UART_LINBreakSendLengthTypeDef BreakLength); +void UART_LINBreakDetectLengthConfig(UART_TypeDef* UARTx, UART_LINBreakDetectLengthTypeDef UART_LINBreakDetectLength); + +/* 定时器工作模式 */ +void UART_TimerModeConfig(UART_TypeDef* UARTx, uint16_t UART_TimerMode); +void UART_SetAutoReload(UART_TypeDef* UARTx, uint32_t AutoReload); +uint32_t UART_GetCounter(UART_TypeDef* UARTx); + +/* 自动波特率检测 */ +void UART_EnableAutoBaudRateDetection(UART_TypeDef* UARTx,UART_AutoBaudRateModeTypeDef AutoBaudRateMode); +void UART_DisableAutoBaudRateDetection(UART_TypeDef* UARTx); +boolean_t UART_AutoBaudRateDetectionComplete(UART_TypeDef* UARTx); +uint32_t UART_GetDetectedBaudRate(UART_TypeDef* UARTx); + +/* 数据匹配功能 */ +void UART_EnableDataMatch(UART_TypeDef* UARTx); +void UART_DisableDataMatch(UART_TypeDef* UARTx); +void UART_SetDataMatch(UART_TypeDef* UARTx, uint16_t DataMatch); +boolean_t UART_GetDataMatchFlag(UART_TypeDef* UARTx); + + +#ifdef __cplusplus +} +#endif + +#endif /*__CW32L012_UART_H */ +/** + * @} + */ + + + + + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_vc.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_vc.h new file mode 100644 index 0000000..b44947b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_vc.h @@ -0,0 +1,247 @@ +/** + * @file cw32l012_vc.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/******************************************************************************* +* VC1: VC2: VC3 VC4 +* INP0 PA00 PA01 PA06 PA09 +* INP1 PA02 PA03 PA07 PA10 +* INP2 PA04 PA05 PB00 PB10 +* INP3 PB00 PB01 PB02 PB01 +* +* INN0 PA00 PA01 PA06 PA09 +* INN1 PA02 PA03 PA07 PA10 +*/ + +#ifndef __CW32L012_VC_H +#define __CW32L012_VC_H + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "system_cw32l012.h" +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup VcGroup Voltage Comparator (VC) + ** + ******************************************************************************/ +//@{ + + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +// 定义参考电压源 +typedef enum { + VC_REF_EXT = 0, // 选择外部输入，则关闭内部的分压 + VC_REF_AVCC = 1, + VC_REF_VCORE = 3, + +} VC_RefVoltage; + +// 定义电阻分压系数 +typedef enum { + VC_DIV_0 = 0, // 输出电压 = 输入电压 * (1 + 0) / 8 + VC_DIV_1 = 1, // 输出电压 = 输入电压 * (1 + 1) / 8 + VC_DIV_2 = 2, // 输出电压 = 输入电压 * (1 + 2) / 8 + VC_DIV_3 = 3, // 输出电压 = 输入电压 * (1 + 3) / 8 + VC_DIV_4 = 4, // 输出电压 = 输入电压 * (1 + 4) / 8 + VC_DIV_5 = 5, // 输出电压 = 输入电压 * (1 + 5) / 8 + VC_DIV_6 = 6, // 输出电压 = 输入电压 * (1 + 6) / 8 + VC_DIV_7 = 7 // 输出电压 = 输入电压 * (1 + 7) / 8 +} VC_Divider; + +// 定义通用输入信号选择 +typedef enum { + VC_INPUT_IN0 = 0, + VC_INPUT_IN1 = 1, + VC_INPUT_IN2 = 2, + VC_INPUT_IN3 = 3 +} VC_InputSignal; + +// 定义正端输入信号选择 +typedef enum { + VC_INP_IN0 = 0, + VC_INP_IN1 = 1, + VC_INP_IN2 = 2, + VC_INP_IN3 = 3 +} VC_PosInputSignal; + +// 定义负端输入信号选择 +typedef enum { + VC_INN_IN0 = 0, + VC_INN_IN1 = 1, + VC_INN_DAC = 2, + VC_INN_REF = 3 +} VC_NegInputSignal; + +// 定义中断触发方式 +typedef enum { + VC_INT_DISABLE = 0, + VC_INT_FALLING = 1, + VC_INT_RISING = 2, + VC_INT_HIGH = 4 +} VC_InterruptMode; + +// 定义滤波器时钟源 +typedef enum { + VC_FILTER_CLOCK_LSI = 0, + VC_FILTER_CLOCK_PCLK +}VC_FilterClock; + +// 定义滤波器时间 +typedef enum { + VC_FILTER_DISABLE = 0, + VC_FILTER_1X_2SAMPLES = 1, + VC_FILTER_1X_4SAMPLES = 2, + VC_FILTER_1X_8SAMPLES = 3, + VC_FILTER_2X_6SAMPLES = 4, + VC_FILTER_2X_8SAMPLES = 5, + VC_FILTER_4X_6SAMPLES = 6, + VC_FILTER_4X_8SAMPLES = 7, + VC_FILTER_8X_6SAMPLES = 8, + VC_FILTER_8X_8SAMPLES = 9, + VC_FILTER_16X_5SAMPLES = 10, + VC_FILTER_16X_6SAMPLES = 11, + VC_FILTER_16X_8SAMPLES = 12, + VC_FILTER_32X_5SAMPLES = 13, + VC_FILTER_32X_6SAMPLES = 14, + VC_FILTER_32X_8SAMPLES = 15 +} VC_FilterTime; + +// 定义滤波器配置 +typedef struct { + VC_FilterClock FilterClock; + VC_FilterTime FilterTime; +}VC_FilterConfig; + + +// 定义VC相应速度 +typedef enum { + VC_RESPONSE_SLOW = 0, + VC_RESPONSE_FAST +}VC_ResponseSpeed; + +// 定义VC模块配置结构体 +typedef struct { + VC_RefVoltage RefVoltage; // 参考输入电压源 + VC_Divider div; // 分压系数 + VC_PosInputSignal inputPositive; // 正端输入信号 + VC_NegInputSignal inputNegative; // 负端输入信号 + boolean_t polarityInvert; // 输出极性 + boolean_t hysteresisEnable; // 迟滞窗口 + VC_ResponseSpeed responseSpeed; // 响应速度 + VC_InterruptMode interruptMode; // 中断触发方式 + VC_FilterConfig filterConfig; // 滤波器配置 +} VC_InitTypeDef; + +typedef enum { + VC_BLANK_OUTPUT_LOW = 0, + VC_BLANK_OUTPUT_HIGH +}VC_BlankOutput; + +// 定义 BLANKTIME 枚举 +typedef enum { + VC_BLANKTIME_6PCLK = 0, // BLANK窗口持续时间为 2 ^ (0+2) + N PCLK周期，N = 0~2, 最多6个PCLK + VC_BLANKTIME_10PCLK, // BLANK窗口持续时间为 2 ^ (1+2) + N PCLK周期，N = 0~2, 最多10个PCLK + VC_BLANKTIME_18PCLK, // BLANK窗口持续时间为 2 ^ (2+2) + N PCLK周期，N = 0~2, 最多18个PCLK + VC_BLANKTIME_34PCLK, // BLANK窗口持续时间为 2 ^ (3+2) + N PCLK周期，N = 0~2, 最多34个PCLK + VC_BLANKTIME_66PCLK, // BLANK窗口持续时间为 2 ^ (4+2) + N PCLK周期，N = 0~2, 最多66个PCLK + VC_BLANKTIME_130PCLK, // BLANK窗口持续时间为 2 ^ (5+2) + N PCLK周期，N = 0~2, 最多130个PCLK + VC_BLANKTIME_258PCLK, // BLANK窗口持续时间为 2 ^ (6+2) + N PCLK周期，N = 0~2, 最多258个PCLK + VC_BLANKTIME_514PCLK, // BLANK窗口持续时间为 2 ^ (7+2) + N PCLK周期，N = 0~2, 最多514个PCLK +} VC_BlankTime; + +// 定义 BLANK窗口使能控制 +typedef enum{ + VC_CR2_HALLTIM1TRGO = (int32_t) (1 << 31), // HALLTIM1TRGO信号触发 BLANK窗口使能控制 + VC_CR2_BTIM3TRGO = (1 << 30), // BTIM3TRGO信号触发 BLANK窗口使能控制 + VC_CR2_BTIM2TRGO = (1 << 29), // BTIM2TRGO信号触发 BLANK窗口使能控制 + VC_CR2_BTIM1TRGO = (1 << 28), // BTIM1TRGO信号触发 BLANK窗口使能控制 + VC_CR2_GTIM4OC4REFC = (1 << 27), // GTIM4OC4REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_GTIM4OC3REFC = (1 << 26), // GTIM4OC3REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_GTIM4OC2REFC = (1 << 25), // GTIM4OC2REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_GTIM4OC1REFC = (1 << 24), // GTIM4OC1REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_GTIM4TRGO = (1 << 23), // GTIM4TRGO信号触发 BLANK窗口使能控制 + VC_CR2_GTIM3OC4REFC = (1 << 22), // GTIM3OC4REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_GTIM3OC3REFC = (1 << 21), // GTIM3OC3REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_GTIM3OC2REFC = (1 << 20), // GTIM3OC2REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_GTIM3OC1REFC = (1 << 19), // GTIM3OC1REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_GTIM3TRGO = (1 << 18), // GTIM3TRGO信号触发 BLANK窗口使能控制 + VC_CR2_GTIM2OC4REFC = (1 << 17), // GTIM2OC4REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_GTIM2OC3REFC = (1 << 16), // GTIM2OC3REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_GTIM2OC2REFC = (1 << 15), // GTIM2OC2REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_GTIM2OC1REFC = (1 << 14), // GTIM2OC1REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_GTIM2TRGO = (1 << 13), // GTIM2TRGO信号触发 BLANK窗口使能控制 + VC_CR2_GTIM1OC4REFC = (1 << 12), // GTIM1OC4REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_GTIM1OC3REFC = (1 << 11), // GTIM1OC3REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_GTIM1OC2REFC = (1 << 10), // GTIM1OC2REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_GTIM1OC1REFC = (1 << 9), // GTIM1OC1REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_GTIM1TRGO = (1 << 8), // GTIM1TRGO信号触发 BLANK窗口使能控制 + VC_CR2_ATIM1OC6REFC = (1 << 7), // ATIM1 OC6REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_ATIM1OC5REFC = (1 << 6), // ATIM1 OC5REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_ATIM1OC4REFC = (1 << 5), // ATIM1 OC4REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_ATIM1OC3REFC = (1 << 4), // ATIM1 OC3REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_ATIM1OC2REFC = (1 << 3), // ATIM1 OC2REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_ATIM1OC1REFC = (1 << 2), // ATIM1 OC1REFC上升沿信号触发 BLANK窗口使能控制 + VC_CR2_ATIM1TRGO2 = (1 << 1), // ATIM1 TRGO2信号触发 BLANK窗口使能控制 + VC_CR2_ATIM1TRGO = (1 << 0) // ATIM1 TRGO信号触发 BLANK窗口使能控制 +} VC_BlankTrigSource; + +typedef struct { + VC_BlankOutput BlankOutput; + VC_BlankTime BlankTime; + VC_BlankTrigSource BlankTrigSource; +}VC_BlankWindowCfg; + + +// 函数声明 +void VC_Init(VC_TypeDef *VCx, VC_InitTypeDef* VC_InitStruct); +void VC_Cmd(VC_TypeDef *VCx, FunctionalState state); +void VC_SetRefVoltage(VC_TypeDef *VCx, VC_RefVoltage RefVoltage, VC_Divider div); +void VC_SetInputSignals(VC_TypeDef *VCx, VC_PosInputSignal inputPositive, VC_NegInputSignal inputNegative); +void VC_SetInterruptMode(VC_TypeDef *VCx, VC_InterruptMode mode); +void VC_SetFilterConfig(VC_TypeDef *VCx, VC_FilterConfig *config); +uint8_t VC_GetInterruptFlag(VC_TypeDef *VCx); +void VC_ClearInterruptFlag(VC_TypeDef *VCx); +uint8_t VC_GetFilterOutput(VC_TypeDef *VCx); +void VC_SetBlankWindow(VC_TypeDef *VCx, VC_BlankWindowCfg *config); + + +#ifdef __cplusplus +} +#endif + +#endif /* __CW32L012_VC_H */ +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_wwdt.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_wwdt.h new file mode 100644 index 0000000..a483f21 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/cw32l012_wwdt.h @@ -0,0 +1,48 @@ +/** + * @file cw32l012_wwdt.h + * @brief 此文件包含 CW32L012 窗口看门狗 (WWDT) 外设的标准外设库头文件声明。 + * @version 0.1 + * @date {%当前日期%} + * + * @copyright Copyright (c) {%当前年份%} + */ +#ifndef CW32L012_WWDT_H +#define CW32L012_WWDT_H + +#include "cw32l012.h" +#include "cw32l012_sysctrl.h" + +#define WWDT_ClearPOVFlag() {CW_WWDT->SR = 0;} +/** + * @brief WWDT Prescaler divider + */ +typedef enum +{ + WWDT_PRESCALER_DIV4096 = 0x0, /*!< PCLK/4096 */ + WWDT_PRESCALER_DIV8192 = 0x1, /*!< PCLK/8192 */ + WWDT_PRESCALER_DIV16384 = 0x2, /*!< PCLK/16384 */ + WWDT_PRESCALER_DIV32768 = 0x3, /*!< PCLK/32768 */ + WWDT_PRESCALER_DIV65536 = 0x4, /*!< PCLK/65536 */ + WWDT_PRESCALER_DIV131072 = 0x5, /*!< PCLK/131072 */ + WWDT_PRESCALER_DIV262144 = 0x6, /*!< PCLK/262144 */ + WWDT_PRESCALER_DIV524288 = 0x7 /*!< PCLK/524288 */ +} WWDT_PrescalerTypeDef; + +/** + * @brief WWDT Init structure definition + */ +typedef struct +{ + WWDT_PrescalerTypeDef Prescaler; /*!< 预分频值 */ + uint8_t WindowValue; /*!< 窗口值，范围0-127 */ + uint8_t CounterValue; /*!< 计数器初始值，范围0-127 */ + FunctionalState PreOvInt; /*!< 提前唤醒中断使能 */ +} WWDT_InitTypeDef; + +// 修改初始化函数声明 +void WWDT_Init(const WWDT_InitTypeDef *WWDT_InitStruct); + +// 喂狗操作 +void WWDT_Feed(uint8_t ReloadCnt); + +#endif diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/system_cw32l012.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/system_cw32l012.h new file mode 100644 index 0000000..bec303e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/inc/system_cw32l012.h @@ -0,0 +1,84 @@ +/** + ****************************************************************************** + * @file system_cw32l012.h + * @author WHXY Application Team + * @brief + ****************************************************************************** + */ + +#ifndef __SYSTEM_CW32l012_H +#define __SYSTEM_CW32l012_H + +#define SYSCTRL_HSI_TRIMCODEADDR (0x001007C0U) // +#define SYSCTRL_LSI_TRIMCODEADDR (0x001007C2U) // + +#ifdef __cplusplus +extern "C" { +#endif +/** @addtogroup Includes + * @{ + */ + +#include "cw32l012.h" +#include "base_types.h" +/** + * @} + */ + +/** @addtogroup Exported_Variables + * @{ + */ +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) + +/** + * @} + */ + +/** @addtogroup Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup Exported_Macros + * @{ + */ +#define HWWD_DISABLE (1) +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u +/** + * @} + */ + +/** @addtogroup Exported_Functions + * @{ + */ + +extern void SystemInit (void); // Initialize the system +extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable +extern void FirmwareDelay(uint32_t DlyCnt); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_CW32l010_H__ */ + + + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_adc.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_adc.c new file mode 100644 index 0000000..3ac3f08 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_adc.c @@ -0,0 +1,560 @@ +/** + * @file cw32l012_adc.c + * @author WHXY + * @brief + * @version 0.1 + * @file cw32l012_adc.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* + * + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + * + *******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "cw32l012.h" +#include "cw32l012_adc.h" +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" + +/** + ****************************************************************************** + ** \addtogroup AdcGroup + ******************************************************************************/ +//@{ +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + + +/** + * @brief + * ADC去初始化 + */ +void ADC_DeInit(void) +{ + // Enable ADC reset state + REGBITS_CLR(CW_SYSCTRL->APBRST1, SYSCTRL_APBRST1_ADC_Msk); + // Release ADC from reset state + REGBITS_SET(CW_SYSCTRL->APBRST1, SYSCTRL_APBRST1_ADC_Msk); +} + + +/** + * @brief + * ADC初始化 + * + * @param ADC_InitStruct + */ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) +{ + ASSERT(NULL != ADC_InitStruct) + + assert_param(IS_ADC_CLK_DIV(ADC_InitStruct->ADC_ClkDiv )); + + __SYSCTRL_ADC_CLK_ENABLE(); //打开ADC时钟 + + REGBITS_MODIFY(ADCx->CR, + ADCx_CR_ENS_Msk | ADCx_CR_CLK_Msk | ADCx_CR_CONT_Msk | ADCx_CR_SLAVE_Msk, + ADC_InitStruct->ADC_SQREns | \ + ADC_InitStruct->ADC_ClkDiv | \ + ADC_InitStruct->ADC_ConvertMode | \ + ADC_InitStruct->ADC_SlaveMod); + + + ADCx->SQRCFR_f.SQRCH0 = ADC_InitStruct->ADC_IN0.ADC_InputChannel; + ADCx->SQRCFR_f.SQRCH1 = ADC_InitStruct->ADC_IN1.ADC_InputChannel; + ADCx->SQRCFR_f.SQRCH2 = ADC_InitStruct->ADC_IN2.ADC_InputChannel; + ADCx->SQRCFR_f.SQRCH3 = ADC_InitStruct->ADC_IN3.ADC_InputChannel; + ADCx->SQRCFR_f.SQRCH4 = ADC_InitStruct->ADC_IN4.ADC_InputChannel; + ADCx->SQRCFR_f.SQRCH5 = ADC_InitStruct->ADC_IN5.ADC_InputChannel; + ADCx->SQRCFR_f.SQRCH6 = ADC_InitStruct->ADC_IN6.ADC_InputChannel; + ADCx->SQRCFR_f.SQRCH7 = ADC_InitStruct->ADC_IN7.ADC_InputChannel; + + ADCx->SAMPLE_f.SQRCH0 = ADC_InitStruct->ADC_IN0.ADC_SampTime; + ADCx->SAMPLE_f.SQRCH1 = ADC_InitStruct->ADC_IN1.ADC_SampTime; + ADCx->SAMPLE_f.SQRCH2 = ADC_InitStruct->ADC_IN2.ADC_SampTime; + ADCx->SAMPLE_f.SQRCH3 = ADC_InitStruct->ADC_IN3.ADC_SampTime; + ADCx->SAMPLE_f.SQRCH4 = ADC_InitStruct->ADC_IN4.ADC_SampTime; + ADCx->SAMPLE_f.SQRCH5 = ADC_InitStruct->ADC_IN5.ADC_SampTime; + ADCx->SAMPLE_f.SQRCH6 = ADC_InitStruct->ADC_IN6.ADC_SampTime; + ADCx->SAMPLE_f.SQRCH7 = ADC_InitStruct->ADC_IN7.ADC_SampTime; +} + +/** + * @brief + * ADC使能 + */ +ErrorStatus ADC_Enable(ADC_TypeDef *ADCx) +{ + REGBITS_SET(ADCx->CR, ADCx_CR_EN_Msk); + + return SUCCESS; +} + +/** + * @brief + * ADC禁用 + */ +void ADC_Disable(ADC_TypeDef *ADCx) +{ + REGBITS_CLR(ADCx->CR, ADCx_CR_EN_Msk); +} + + +/** + * @brief + * ADC模拟看门狗初始化 + */ +void ADC_WatchdogInit(ADC_TypeDef *ADCx, ADC_WatchdogTypeDef* ADC_WatchdogStruct) +{ + assert_param(IS_ADC_WATCHDOG_VTH(ADC_WatchdogStruct->ADC_WatchdogVth)); + assert_param(IS_ADC_WATCHDOG_VTL(ADC_WatchdogStruct->ADC_WatchdogVtl)); + assert_param(IS_FUNCTIONAL_STATE(ADC_WatchdogStruct->ADC_WatchdogOverHighIrq)); + assert_param(IS_FUNCTIONAL_STATE(ADC_WatchdogStruct->ADC_WatchdogUnderLowIrq)); + + ADC_Init(ADCx, &ADC_WatchdogStruct->ADC_InitStruct); + + REGBITS_MODIFY(ADCx->AWDTR, ADCx_AWDTR_VTH_Msk | ADCx_AWDTR_VTL_Msk, \ + (ADC_WatchdogStruct->ADC_WatchdogVth << 16) | ADC_WatchdogStruct->ADC_WatchdogVtl); + ADCx->AWDCR = ADC_WatchdogStruct->ADC_WatchdogCHx; + + (ADC_WatchdogStruct->ADC_WatchdogOverHighIrq == ENABLE) ? (ADCx->IER_f.AWDH = 1) : (ADCx->IER_f.AWDH = 0); + (ADC_WatchdogStruct->ADC_WatchdogUnderLowIrq == ENABLE) ? (ADCx->IER_f.AWDL = 1) : (ADCx->IER_f.AWDL = 0); +} + + + +/** + * @brief + * 获取ADC所有中断状态 + * + * @param pFlagAdcIrq + */ +void ADC_GetITStatusAll(ADC_TypeDef *ADCx, volatile uint8_t* pFlagAdcIrq) +{ + *pFlagAdcIrq = (uint8_t) (ADCx->ISR); +} + +/** + * @brief + * 获取ADC指定的中断状态 + * + * @param ADC_IT: + + * @arg ADC_IT_AWDH + * @arg ADC_IT_AWDL + * @arg ADC_IT_EOS + * @arg ADC_IT_EOC + * + * @return ITStatus: SET or RESET + */ +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + assert_param(IS_ADC_GET_IT(ADC_IT)); + return (REGBITS_GET(ADCx->ISR, ADC_IT) ? SET : RESET); +} + +/** + * @brief + * 清除ADC所有中断状态 + */ +void ADC_ClearITPendingAll(ADC_TypeDef *ADCx) +{ + ADCx->ICR = 0x0000; +} + +/** + * @brief + * 清除ADC指定的中断状态 + * + * @param ADC_IT + * @arg ADC_IT_AWDH + * @arg ADC_IT_AWDL + * @arg ADC_IT_EOS + * @arg ADC_IT_EOC + */ +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + assert_param(IS_ADC_GET_IT(ADC_IT)); + REGBITS_CLR(ADCx->ICR, ADC_IT); +} + +/** + * @brief + * ADC中断配置 + * + * @param ADC_IT: + * @arg ADC_IT_AWDH + * @arg ADC_IT_AWDL + * @arg ADC_IT_EOS + * @arg ADC_IT_EOC + * @param NewState: + * @arg DISABLE + * @arg ENABLE + */ +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->IER |= ADC_IT; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->IER &= (~(uint32_t) ADC_IT); + } +} + + +/** + * @brief + * ADC转换软件启动命令1 + * + * @param NewState + * @arg DISABLE + * @arg ENABLE + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + REGBITS_SET(ADCx->START, ADCx_START_START_Msk); + } + else + { + REGBITS_CLR(ADCx->START, ADCx_START_START_Msk); + } +} + + +/** + * @brief + * ADC外部触发源配置 + * + * @param ADC_TRIG: + + * @arg ADC_TRIG_UART2 + * @arg ADC_TRIG_UART1 + * @arg ADC_TRIG_SPI1 + * @arg ADC_TRIG_BTIM3TRGO + * @arg ADC_TRIG_BTIM2TRGO + * @arg ADC_TRIG_BTIM1TRGO + * @arg ADC_TRIG_GTIM1CC4 + * @arg ADC_TRIG_GTIM1CC3 + * @arg ADC_TRIG_GTIM1CC2 + * @arg ADC_TRIG_GTIM1CC1 + * @arg ADC_TRIG_GTIM1TRGO + * @arg ADC_TRIG_ATIMCC6 + * @arg ADC_TRIG_ATIMCC5 + * @arg ADC_TRIG_ATIMCC4 + * @arg ADC_TRIG_ATIMCC3 + * @arg ADC_TRIG_ATIMCC2 + * @arg ADC_TRIG_ATIMCC1 + * @arg ADC_TRIG_ATIMTRGO2 + * @arg ADC_TRIG_ATIMTRGO + * @param NewState: + * @arg DISABLE + * @arg ENABLE + */ +void ADC_ExtTrigCfg(ADC_TypeDef *ADCx, uint32_t ADC_TRIG, FunctionalState NewState) +{ + uint32_t trigMask = 0; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_TRIG(ADC_TRIG)); + /* Get the ADC TRIG index */ + trigMask = ADC_TRIG; + + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->TRIGGER |= trigMask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->TRIGGER &= (~(uint32_t) trigMask); + } +} + +/** + * @brief + * 获取采样结果值 + * + * @param Result 范围0~7 + */ + +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx, uint32_t ResultX) +{ + assert_param(IS_ADC_RESULT_X(ResultX)); + + uint32_t *pAdcResult = (uint32_t *)&ADCx->RESULT0; + + return *(pAdcResult + ResultX); + +} + +/** + * @brief + * 获取SQR0通道采样值 + * + * @param pAdcResult + */ +void ADC_GetSqr0Result(ADC_TypeDef *ADCx, uint16_t* pAdcResult) +{ + if (NULL == pAdcResult) + { + return; + } + + *pAdcResult = (uint16_t)(ADCx->RESULT0); +} + +/** + * @brief + * 获取SQR1通道采样值 + * + * @param pAdcResult + */ +void ADC_GetSqr1Result(ADC_TypeDef *ADCx, uint16_t* pAdcResult) +{ + if (NULL == pAdcResult) + { + return; + } + + *pAdcResult = (uint16_t)(ADCx->RESULT1); +} + +/** + * @brief + * 获取SQR2通道采样值 + * + * @param pAdcResult + */ +void ADC_GetSqr2Result(ADC_TypeDef *ADCx, uint16_t* pAdcResult) +{ + if (NULL == pAdcResult) + { + return; + } + + *pAdcResult = (uint16_t)(ADCx->RESULT2); +} + +/** + * @brief + * 获取SQR3通道采样值 + * + * @param pAdcResult + */ +void ADC_GetSqr3Result(ADC_TypeDef *ADCx, uint16_t* pAdcResult) +{ + if (NULL == pAdcResult) + { + return; + } + + *pAdcResult = (uint16_t)(ADCx->RESULT3); +} + +/** + * @brief + * 获取SQR4通道采样值 + * + * @param pAdcResult + */ +void ADC_GetSqr4Result(ADC_TypeDef *ADCx, uint16_t* pAdcResult) +{ + if (NULL == pAdcResult) + { + return; + } + + *pAdcResult = (uint16_t)(ADCx->RESULT4); +} + +/** + * @brief + * 获取SQR5通道采样值 + * + * @param pAdcResult + */ +void ADC_GetSqr5Result(ADC_TypeDef *ADCx, uint16_t* pAdcResult) +{ + if (NULL == pAdcResult) + { + return; + } + + *pAdcResult = (uint16_t)(ADCx->RESULT5); +} + +/** + * @brief + * 获取SQR6通道采样值 + * + * @param pAdcResult + */ +void ADC_GetSqr6Result(ADC_TypeDef *ADCx, uint16_t* pAdcResult) +{ + if (NULL == pAdcResult) + { + return; + } + + *pAdcResult = (uint16_t)(ADCx->RESULT6); +} + +/** + * @brief + * 获取SQR7通道采样值 + * + * @param pAdcResult + */ +void ADC_GetSqr7Result(ADC_TypeDef *ADCx, uint16_t* pAdcResult) +{ + if (NULL == pAdcResult) + { + return; + } + + *pAdcResult = (uint16_t)(ADCx->RESULT7); +} + + +/** + * @brief + * 设置内置温度传感器使能控制 + * + * @param enTs: + * @arg ADC_TsDisable + * @arg ADC_TsEnable + */ +void ADC_SetTs(uint32_t enTs) +{ + assert_param(IS_ADC_TS_ENABLE(enTs)); + + CW_BGR->CR_f.TSEN = !!enTs; + + +} + +/** + * @brief + * 获取内置温度传感器的值， + * + * @param RefVoltage: 参考电压值 如3.3 表示3.3V + * @param AdcValue: ADC的采样结果 + * @return 返回摄氏度 + */ +float ADC_GetTs(float RefVoltage, uint32_t AdcValue) +{ + return (*((uint8_t *)(ADC_TS_T0_ADDRESS)) >> 1) + \ + COEFF_TS* (RefVoltage *AdcValue - *(uint16_t *)(ADC_TS_TRIM_ADDRESS)*4.095); + +} + +/** + * @brief + * 通过BGR的采样转换值反推AVCC的电压 + * + * @param BgrValue: BGR在当前AVCC下的转换结果 + * @return 返回AVCC的精确值，单位V + */ +float ADC_BgrResult2Avcc(uint16_t BgrValue) +{ + return *(uint16_t *)(ADC_BGR_VOL_ADDRESS) * 4.095f/BgrValue; +} + +/** + * @brief + * 通过BGR的采样转换值反推其它转换通道的电压 + * + * @param BgrValue: BGR在当前AVCC下的转换结果 + * @param AdcValue: ADC通道的转换结果 + * @return 返回ADC通道的输入电压值，单位V + */ + +float ADC_ResultByBgr(uint16_t AdcValue, uint16_t BgrValue) +{ + return (*(uint16_t *)(ADC_BGR_VOL_ADDRESS) / 1000.0f) * ((float)AdcValue/(float)BgrValue); +} + +void ADC_DMACmd(ADC_TypeDef *ADCx, ADC_DMA_TriggerTypeDef* ADC_DmaTriggerStruct) +{ + if (ADC_DmaTriggerStruct->dma_eoc_enable) + { + ADCx->IER |= ADCx_IER_DMAEOC_Msk; + } + else + { + ADCx->IER &= ~ADCx_IER_DMAEOC_Msk; + } + + if (ADC_DmaTriggerStruct->dma_eos_enable) + { + ADCx->IER |= ADCx_IER_DMAEOS_Msk; + } + else + { + ADCx->IER &= ~ADCx_IER_DMAEOS_Msk; + } +} + +//@} // AdcGroup + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_atim.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_atim.c new file mode 100644 index 0000000..7a6ca90 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_atim.c @@ -0,0 +1,699 @@ +/** + * @file cw32l012_atim.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_atim.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ +/** + * @brief ATIM复位，寄存器恢复为默认值 + */ +void ATIM_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.ATIM = 0; + CW_SYSCTRL->APBRST1_f.ATIM = 1; +} + +/** + * @brief ATIM 初始化 + * @param ATIM_InitStruct 详见ATIM_InitTypeDef的定义 + */ +void ATIM_Init(ATIM_InitTypeDef *ATIM_InitStruct) +{ + assert_param(IS_ATIM_COUNTING_DIRECTION(ATIM_InitStruct->CounterDirection)); + assert_param(IS_ATIM_OP_MODE(ATIM_InitStruct->CounterOPMode)); + assert_param(IS_ATIM_COUNT_MODE(ATIM_InitStruct->CounterAlignedMode)); + assert_param(IS_ATIM_PRESCALER(ATIM_InitStruct->Prescaler)); + + CW_SYSCTRL->APBEN1 |= SYSCTRL_APBEN1_ATIM_Msk; + + REGBITS_MODIFY(CW_ATIM->CR1, ATIM_CR1_DIR_Msk | ATIM_CR1_OPM_Msk | \ + ATIM_CR1_ARPE_Msk | ATIM_CR1_CMS_Msk, + ATIM_InitStruct->CounterDirection | ATIM_InitStruct->CounterOPMode | \ + (ATIM_InitStruct->BufferState ? ATIM_BUFFER_ENABLE : ATIM_BUFFER_DISABLE) | \ + ATIM_InitStruct->CounterAlignedMode); + + CW_ATIM->PSC = ATIM_InitStruct->Prescaler; + + CW_ATIM->ARR = ATIM_InitStruct->ReloadValue; + + CW_ATIM->RCR = ATIM_InitStruct->RepetitionCounter; +} + +/** + * @brief ATIM 启动 + * + * @param NewState ENABLE or DISABLE + */ +void ATIM_Cmd(FunctionalState NewState) +{ + CW_ATIM->CR1_f.CEN = NewState; +} + +/** + * @brief ATIM中断设置 + * @param ATIM_IT 中断源 + * @param NewState ENABLE 或 DISABLE + */ +void ATIM_ITConfig(uint32_t ATIM_IT, FunctionalState NewState) +{ + assert_param(IS_ATIM_IT(ATIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + CW_ATIM->IER |= ATIM_IT; + } + else + { + CW_ATIM->IER &= ~ATIM_IT; + } +} + +/** + * @brief 获取ATIM中断标志位 + * @param ATIM_IT 中断源 + * @return ITStatus + */ +ITStatus ATIM_GetITStatus(uint32_t ATIM_STATE) +{ + assert_param(IS_ATIM_STATE(ATIM_STATE)); + return (CW_ATIM->ISR & ATIM_STATE) ? SET : RESET; +} + +/** + * @brief 清除ATIM中断标志位 + */ +void ATIM_ClearITPendingBit(uint32_t ATIM_STATE) +{ + assert_param(IS_ATIM_IT(ATIM_STATE)); + CW_ATIM->ICR = ~ATIM_STATE; +} + +/** + * @brief 设置ATIM重载值 + * @param Value + */ +void ATIM_SetReloadValue(uint32_t Value) +{ + CW_ATIM->ARR = Value; +} + +/** + * @brief 设置ATIM的计数器值 + * @param Value + */ +void ATIM_SetCounterValue(uint32_t value) +{ + CW_ATIM->CNT = value; +} + +/** + * @brief 设置ATIM主模式下，TRGO1的输出配置 + * @param Value + */ + +void ATIM_MasterModeTrgo1Config(uint8_t ATIM_MasterOutput) +{ + assert_param(IS_ATIM_MASTER_OUTPUT(ATIM_MasterOutput)); + + CW_ATIM->CR2_f.MMS = (ATIM_MasterOutput & 0x07); + CW_ATIM->CR2_f.MMSH = (ATIM_MasterOutput >> 3); +} + +void ATIM_MasterModeTrgo2Config(uint8_t ATIM_MasterOutput) +{ + assert_param(IS_ATIM_MASTER_OUTPUT(ATIM_MasterOutput)); + + CW_ATIM->CR2_f.MMS2 = ATIM_MasterOutput; +} + + +void ATIM_SlaverModeConfig(uint8_t ATIM_SlaverType) +{ + assert_param(IS_ATIM_SLAVER_TYPE(ATIM_SlaverType)); + + CW_ATIM->SMCR_f.SMS = ATIM_SlaverType & 0x07; + CW_ATIM->SMCR_f.SMSH = ATIM_SlaverType >> 3; +} + +void ATIM_SetTriggerInput(uint32_t TriggerInput) +{ + assert_param(IS_ATIM_TRIGGER_INPUT(TriggerInput)); + REGBITS_MODIFY(CW_ATIM->SMCR, ATIM_SMCR_TSH_Msk | ATIM_SMCR_TS_Msk, TriggerInput); +} + +void ATIM_IC1Init(ATIM_ICInitTypeDef *ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + assert_param(IS_ATIMC_IC_PRESCALER(ATIM_ICInitStruct->ICPrescaler)); + + CW_ATIM->CCMR1CAP_f.CC1S = ATIM_ICInitStruct->ICMap; + CW_ATIM->CCMR1CAP_f.IC1PSC = ATIM_ICInitStruct->ICPrescaler; + CW_ATIM->CCMR1CAP_f.IC1F = ATIM_ICInitStruct->ICFilter; + + CW_ATIM->CCER_f.CC1P = ATIM_ICInitStruct->ICPolarity & 0x01; + CW_ATIM->CCER_f.CC1NP = (ATIM_ICInitStruct->ICPolarity & 0x02) >> 1; + CW_ATIM->CCER_f.CC1E = 1; +} + +void ATIM_IC2Init(ATIM_ICInitTypeDef *ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + + CW_ATIM->CCMR1CAP_f.CC2S = ATIM_ICInitStruct->ICMap; + CW_ATIM->CCMR1CAP_f.IC2PSC = ATIM_ICInitStruct->ICPrescaler; + CW_ATIM->CCMR1CAP_f.IC2F = ATIM_ICInitStruct->ICFilter; + + CW_ATIM->CCER_f.CC2P = ATIM_ICInitStruct->ICPolarity & 0x01; + CW_ATIM->CCER_f.CC2NP = (ATIM_ICInitStruct->ICPolarity & 0x02) >> 1; + CW_ATIM->CCER_f.CC2E = 1; +} + +void ATIM_IC3Init(ATIM_ICInitTypeDef *ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + + CW_ATIM->CCMR2CAP_f.CC3S = ATIM_ICInitStruct->ICMap; + CW_ATIM->CCMR2CAP_f.IC3PSC = ATIM_ICInitStruct->ICPrescaler; + CW_ATIM->CCMR2CAP_f.IC3F = ATIM_ICInitStruct->ICFilter; + + CW_ATIM->CCER_f.CC3P = ATIM_ICInitStruct->ICPolarity & 0x01; + CW_ATIM->CCER_f.CC3NP = (ATIM_ICInitStruct->ICPolarity & 0x02) >> 1; + CW_ATIM->CCER_f.CC3E = 1; +} + +void ATIM_IC4Init(ATIM_ICInitTypeDef *ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + + CW_ATIM->CCMR2CAP_f.CC4S = ATIM_ICInitStruct->ICMap; + CW_ATIM->CCMR2CAP_f.IC4PSC = ATIM_ICInitStruct->ICPrescaler; + CW_ATIM->CCMR2CAP_f.IC4F = ATIM_ICInitStruct->ICFilter; + + CW_ATIM->CCER_f.CC4P = ATIM_ICInitStruct->ICPolarity & 0x01; + CW_ATIM->CCER_f.CC4NP = (ATIM_ICInitStruct->ICPolarity & 0x02) >> 1; + CW_ATIM->CCER_f.CC4E = 1; +} + +void ATIM_IC5Init(ATIM_ICInitTypeDef *ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + + CW_ATIM->CCMR3CAP_f.CC5S = ATIM_ICInitStruct->ICMap; + CW_ATIM->CCMR3CAP_f.IC5PSC = ATIM_ICInitStruct->ICPrescaler; + CW_ATIM->CCMR3CAP_f.IC5F = ATIM_ICInitStruct->ICFilter; + + CW_ATIM->CCER_f.CC5P = ATIM_ICInitStruct->ICPolarity & 0x01; + CW_ATIM->CCER_f.CC5NP = (ATIM_ICInitStruct->ICPolarity & 0x02) >> 1; + CW_ATIM->CCER_f.CC5E = 1; +} + +void ATIM_IC6Init(ATIM_ICInitTypeDef *ATIM_ICInitStruct) +{ + assert_param(IS_ATIM_IC_POLARITY(ATIM_ICInitStruct->ICPolarity)); + assert_param(IS_ATIM_IC_FILTER(ATIM_ICInitStruct->ICFilter)); + + CW_ATIM->CCMR3CAP_f.CC6S = ATIM_ICInitStruct->ICMap; + CW_ATIM->CCMR3CAP_f.IC6PSC = ATIM_ICInitStruct->ICPrescaler; + CW_ATIM->CCMR3CAP_f.IC6F = ATIM_ICInitStruct->ICFilter; + + CW_ATIM->CCER_f.CC6P = ATIM_ICInitStruct->ICPolarity & 0x01; + CW_ATIM->CCER_f.CC6NP = (ATIM_ICInitStruct->ICPolarity & 0x02) >> 1; + CW_ATIM->CCER_f.CC6E = 1; +} + +void ATIM_OC1Init(ATIM_OCInitTypeDef *TIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_POLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_ATIM_OC_MODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_FAST_MODE(TIM_OCInitStruct->OCFastMode)); + assert_param(IS_FUNCTIONAL_STATE(TIM_OCInitStruct->BufferState)); + + CW_ATIM->CCMR1CMP_f.CC1S = 0; + CW_ATIM->CCMR1CMP_f.OC1FE = TIM_OCInitStruct->OCFastMode; + CW_ATIM->CCMR1CMP_f.OC1PE = TIM_OCInitStruct->BufferState; + CW_ATIM->CCMR1CMP_f.OC1M = TIM_OCInitStruct->OCMode & 0x07; + CW_ATIM->CCMR1CMP_f.OC1MH = TIM_OCInitStruct->OCMode >> 3; + + CW_ATIM->CCER_f.CC1P = TIM_OCInitStruct->OCPolarity; + + CW_ATIM->CCER_f.CC1NE = TIM_OCInitStruct->OCComplement; + +} + +void ATIM_OC2Init(ATIM_OCInitTypeDef *TIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_POLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_ATIM_OC_MODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_FAST_MODE(TIM_OCInitStruct->OCFastMode)); + assert_param(IS_FUNCTIONAL_STATE(TIM_OCInitStruct->BufferState)); + + CW_ATIM->CCMR1CMP_f.CC2S = 0; + CW_ATIM->CCMR1CMP_f.OC2FE = TIM_OCInitStruct->OCFastMode; + CW_ATIM->CCMR1CMP_f.OC2PE = TIM_OCInitStruct->BufferState; + CW_ATIM->CCMR1CMP_f.OC2M = TIM_OCInitStruct->OCMode & 0x07; + CW_ATIM->CCMR1CMP_f.OC2MH = TIM_OCInitStruct->OCMode >> 3; + + CW_ATIM->CCER_f.CC2P = TIM_OCInitStruct->OCPolarity; + + CW_ATIM->CCER_f.CC2NE = TIM_OCInitStruct->OCComplement; +} + +void ATIM_OC3Init(ATIM_OCInitTypeDef *TIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_POLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_ATIM_OC_MODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_FAST_MODE(TIM_OCInitStruct->OCFastMode)); + assert_param(IS_FUNCTIONAL_STATE(TIM_OCInitStruct->BufferState)); + + CW_ATIM->CCMR2CMP_f.CC3S = 0; + CW_ATIM->CCMR2CMP_f.OC3FE = TIM_OCInitStruct->OCFastMode; + CW_ATIM->CCMR2CMP_f.OC3PE = TIM_OCInitStruct->BufferState; + CW_ATIM->CCMR2CMP_f.OC3M = TIM_OCInitStruct->OCMode & 0x07; + CW_ATIM->CCMR2CMP_f.OC3MH = TIM_OCInitStruct->OCMode >> 3; + + CW_ATIM->CCER_f.CC3P = TIM_OCInitStruct->OCPolarity; + + CW_ATIM->CCER_f.CC3NE = TIM_OCInitStruct->OCComplement; +} + +void ATIM_OC4Init(ATIM_OCInitTypeDef *TIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_POLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_ATIM_OC_MODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_FAST_MODE(TIM_OCInitStruct->OCFastMode)); + assert_param(IS_FUNCTIONAL_STATE(TIM_OCInitStruct->BufferState)); + + CW_ATIM->CCMR2CMP_f.CC4S = 0; + CW_ATIM->CCMR2CMP_f.OC4FE = TIM_OCInitStruct->OCFastMode; + CW_ATIM->CCMR2CMP_f.OC4PE = TIM_OCInitStruct->BufferState; + CW_ATIM->CCMR2CMP_f.OC4M = TIM_OCInitStruct->OCMode & 0x07; + CW_ATIM->CCMR2CMP_f.OC4MH = TIM_OCInitStruct->OCMode >> 3; + + CW_ATIM->CCER_f.CC4P = TIM_OCInitStruct->OCPolarity; + + CW_ATIM->CCER_f.CC4NE = TIM_OCInitStruct->OCComplement; +} + +void ATIM_OC5Init(ATIM_OCInitTypeDef *TIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_POLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_ATIM_OC_MODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_FAST_MODE(TIM_OCInitStruct->OCFastMode)); + assert_param(IS_FUNCTIONAL_STATE(TIM_OCInitStruct->BufferState)); + + CW_ATIM->CCMR3CMP_f.CC5S = 0; + CW_ATIM->CCMR3CMP_f.OC5FE = TIM_OCInitStruct->OCFastMode; + CW_ATIM->CCMR3CMP_f.OC5PE = TIM_OCInitStruct->BufferState; + CW_ATIM->CCMR3CMP_f.OC5M = TIM_OCInitStruct->OCMode & 0x07; + CW_ATIM->CCMR3CMP_f.OC5MH = TIM_OCInitStruct->OCMode >> 3; + + CW_ATIM->CCER_f.CC5P = TIM_OCInitStruct->OCPolarity; + + CW_ATIM->CCER_f.CC5NE = TIM_OCInitStruct->OCComplement; +} + +void ATIM_OC6Init(ATIM_OCInitTypeDef *TIM_OCInitStruct) +{ + assert_param(IS_ATIM_OC_POLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_ATIM_OC_MODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_ATIM_OC_FAST_MODE(TIM_OCInitStruct->OCFastMode)); + assert_param(IS_FUNCTIONAL_STATE(TIM_OCInitStruct->BufferState)); + + CW_ATIM->CCMR3CMP_f.CC6S = 0; + CW_ATIM->CCMR3CMP_f.OC6FE = TIM_OCInitStruct->OCFastMode; + CW_ATIM->CCMR3CMP_f.OC6PE = TIM_OCInitStruct->BufferState; + CW_ATIM->CCMR3CMP_f.OC6M = TIM_OCInitStruct->OCMode & 0x07; + CW_ATIM->CCMR3CMP_f.OC6MH = TIM_OCInitStruct->OCMode >> 3; + + CW_ATIM->CCER_f.CC6P = TIM_OCInitStruct->OCPolarity; + + CW_ATIM->CCER_f.CC6NE = TIM_OCInitStruct->OCComplement; +} + +/** + * @brief 设置通道1的功能 + * + * @param NewState ENABLE 或 DISABLE + */ +void ATIM_CH1Config(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + CW_ATIM->CCER_f.CC1E = NewState; +} + +/** + * @brief 设置通道2的功能 + * + * @param NewState ENABLE 或 DISABLE + */ +void ATIM_CH2Config(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + CW_ATIM->CCER_f.CC2E = NewState; +} + +/** + * @brief 设置通道3的功能 + * + * @param NewState ENABLE 或 DISABLE + */ +void ATIM_CH3Config(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + CW_ATIM->CCER_f.CC3E = NewState; +} + +/** + * @brief 设置通道4的功能 + * + * @param NewState ENABLE 或 DISABLE + */ +void ATIM_CH4Config(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + CW_ATIM->CCER_f.CC4E = NewState; +} + +/** + * @brief 设置通道5的功能 + * + * @param NewState ENABLE 或 DISABLE + */ +void ATIM_CH5Config(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + CW_ATIM->CCER_f.CC5E = NewState; +} + +/** + * @brief 设置通道6的功能 + * + * @param NewState ENABLE 或 DISABLE + */ +void ATIM_CH6Config(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + CW_ATIM->CCER_f.CC6E = NewState; +} + +uint16_t ATIM_GetCapture1(void) +{ + return CW_ATIM->CCR1; +} + +uint16_t ATIM_GetCapture2(void) +{ + return CW_ATIM->CCR2; +} + +uint16_t ATIM_GetCapture3(void) +{ + return CW_ATIM->CCR3; +} + +uint16_t ATIM_GetCapture4(void) +{ + return CW_ATIM->CCR4; +} + +uint16_t ATIM_GetCapture5(void) +{ + return CW_ATIM->CCR5; +} + +uint16_t ATIM_GetCapture6(void) +{ + return CW_ATIM->CCR6; +} + +void ATIM_SetCompare1(uint16_t Compare) +{ + CW_ATIM->CCR1 = Compare; +} + +void ATIM_SetCompare2(uint16_t Compare) +{ + CW_ATIM->CCR2 = Compare; +} +void ATIM_SetCompare3(uint16_t Compare) +{ + CW_ATIM->CCR3 = Compare; +} +void ATIM_SetCompare4(uint16_t Compare) +{ + CW_ATIM->CCR4 = Compare; +} +void ATIM_SetCompare5(uint16_t Compare) +{ + CW_ATIM->CCR5 = Compare; +} +void ATIM_SetCompare6(uint16_t Compare) +{ + CW_ATIM->CCR6 = Compare; +} + +void ATIM_CtrlPWMOutputs(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + CW_ATIM->BDTR_f.MOE = NewState; +} + +/** + * @brief 设置PWM输出的死区 + * + * @param RiseDeadtime 上升沿死区 死区时间，单位为定时器的计数时隙，范围：0~0xFF + * @param FallDeadtime 上升沿死区 死区时间，单位为定时器的计数时隙，范围：0~0xFF + * @param BuffState 死区缓存使能 + * + */ +void ATIM_SetPWMDeadtime(int16_t RiseDeadtime, int16_t FallDeadtime, FunctionalState BuffState) +{ + if (RiseDeadtime == FallDeadtime) + { + CW_ATIM->DTR2_f.DTAE = 0; + CW_ATIM->BDTR_f.DTG = RiseDeadtime; + } + else + { + CW_ATIM->DTR2_f.DTAE = 1; + CW_ATIM->BDTR_f.DTG = RiseDeadtime; + CW_ATIM->DTR2_f.DTGF = FallDeadtime; + } + + CW_ATIM->DTR2_f.DTPE = BuffState; +} + +/** + * @brief 设置Brake输入信号的参数 + * @param ATIM_BrakePolarity 信号极性，参数为下列参数之一： + * @arg ATIM_BRAKE_POLARITY_LOW + * @arg ATIM_BRAKE_POLARITY_HIGH + * @param ATIM_BrakeFilter + */ +void ATIM_Brake1Config(uint32_t ATIM_BrakePolarity, uint32_t ATIM_BrakeFilter) +{ + assert_param(IS_ATIM_BRAKE_POLARITY(ATIM_BrakePolarity)); + assert_param(IS_ATIM_BRAKE_FILTER(ATIM_BrakeFilter)); + + CW_ATIM->BDTR_f.BKP = ATIM_BrakePolarity; + CW_ATIM->BDTR_f.BKF = ATIM_BrakeFilter; + + CW_ATIM->BDTR_f.BKE = 1; +} + +void ATIM_Brake2Config(uint32_t ATIM_BrakePolarity, uint32_t ATIM_BrakeFilter) +{ + assert_param(IS_ATIM_BRAKE_POLARITY(ATIM_BrakePolarity)); + assert_param(IS_ATIM_BRAKE_FILTER(ATIM_BrakeFilter)); + + CW_ATIM->BDTR_f.BK2P = ATIM_BrakePolarity; + CW_ATIM->BDTR_f.BK2F = ATIM_BrakeFilter; + + CW_ATIM->BDTR_f.BK2E = 1; +} + +/** + * @brief 设置ATIM更新事件类型 + * + * @param ATIM_UpdateEvent + * @arg ATIM_UPDATE_EVENT_NORMAL 上溢出/下溢出 + * @arg ATIM_UPDATE_EVENT_EXTENSION 上溢出/下溢出/软件更新/从模式复位 + * + */ + +void ATIM_UpdateEventSelect(uint8_t ATIM_UpdateEvent) +{ + assert_param(IS_ATIM_UPDATE_EVENT(ATIM_UpdateEvent)); + + CW_ATIM->CR1_f.URS = ATIM_UpdateEvent; +} + +void ATIM_RemapTimerInput(uint32_t ChannelX, uint32_t Remap) +{ + switch (ChannelX) + { + case ATIM_CH1: + CW_ATIM->TISEL1_f.TI1SEL = Remap; + break; + + case ATIM_CH2: + CW_ATIM->TISEL1_f.TI2SEL = Remap; + break; + + case ATIM_CH3: + CW_ATIM->TISEL1_f.TI3SEL = Remap; + break; + + case ATIM_CH4: + CW_ATIM->TISEL1_f.TI4SEL = Remap; + break; + + case ATIM_CH5: + CW_ATIM->TISEL2_f.TI5SEL = Remap; + break; + + case ATIM_CH6: + CW_ATIM->TISEL2_f.TI6SEL = Remap; + break; + + default: + break; + } +} + +/** + * @brief 配置ATIM外部触发信号ETR + * + * @param ATIM_ETRInitStuctor 见ATIM_ETRInitTypeDef定义 + * + * + */ +void ATIM_ETRInit(ATIM_ETRInitTypeDef *ATIM_ETRInitStuctor) +{ + CW_ATIM->AF1_f.ETRSEL = ATIM_ETRInitStuctor->Source; + + CW_ATIM->SMCR = (CW_ATIM->SMCR & (~(ATIM_SMCR_ETF_Msk | ATIM_SMCR_ETPS_Msk | \ + ATIM_SMCR_ETP_Msk))) | ATIM_ETRInitStuctor->Filter | \ + ATIM_ETRInitStuctor->Prescaler | ATIM_ETRInitStuctor->Polarity; +} + +/** + * @brief 设置ATIM外部触发信号ETR的来源 + * + * @param ETRSource 见ATIM_ETRTypeDef定义 + * + * + */ +void ATIM_SetETRSource(ATIM_ETRSourceTypeDef ETRSource) +{ + CW_ATIM->AF1_f.ETRSEL = ETRSource; + +} + + +/** + * @brief 配置ATIM外部触发信号ETR的极性 + * + * @param ETR_Polarity + * @arg ATIM_ETR_POLARITY_POSITIVE + * @arg ATIM_ETR_POLARITY_NEGATIVE + * + */ +void ATIM_SetETRPolarity(uint32_t ETR_Polarity) +{ + CW_ATIM->SMCR = (CW_ATIM->SMCR & (~ATIM_SMCR_ETP_Pos)) | ETR_Polarity; +} + +/** + * @brief 配置ATIM外部触发信号ETR的分配器 + * + * @param ETR_Prescale + * @arg ATIM_ETR_PRESCALE_NONE + * @arg ATIM_ETR_PRESCALE_DIV2 + * @arg ATIM_ETR_PRESCALE_DIV4 + * @arg ATIM_ETR_PRESCALE_DIV8 + * + */ +void ATIM_SetETRPrescaler(uint32_t ETR_Prescale) +{ + CW_ATIM->SMCR = (CW_ATIM->SMCR & (~ATIM_SMCR_ETPS_Msk)) | ETR_Prescale; +} + +/** + * @brief 配置ATIM外部触发信号ETR的滤波器 + * + * @param ETR_Filter + * @arg ATIM_ETR_FILTER_NONE + * @arg ATIM_ETR_FILTER_DIV1_N2 ATIM_ETR_FILTER_DIV1_N4 ATIM_ETR_FILTER_DIV1_N8 + * @arg ATIM_ETR_FILTER_DIV2_N6 ATIM_ETR_FILTER_DIV2_N8 ATIM_ETR_FILTER_DIV4_N6 + * @arg ATIM_ETR_FILTER_DIV4_N8 ATIM_ETR_FILTER_DIV8_N6 ATIM_ETR_FILTER_DIV8_N8 + * @arg ATIM_ETR_FILTER_DIV16_N5 ATIM_ETR_FILTER_DIV16_N6 ATIM_ETR_FILTER_DIV16_N8 + * @arg ATIM_ETR_FILTER_DIV32_N5 ATIM_ETR_FILTER_DIV32_N6 ATIM_ETR_FILTER_DIV32_N8 + */ +void ATIM_SetETRFilter(uint32_t ETR_Filter) +{ + CW_ATIM->SMCR = (CW_ATIM->SMCR & (~ATIM_SMCR_ETF_Msk)) | ETR_Filter; +} + +/** + * @brief 配置ATIM外部时钟模式 + * + * @param _bool + * @arg TRUE or FALSE + * + */ +void ATIM_EnableExternalClock(boolean_t _bool) +{ + if (_bool) + { + CW_ATIM->SMCR_f.ECE = 1; + } + else + { + CW_ATIM->SMCR_f.ECE = 0; + } +} + +/** + * @brief 配置ATIM数字滤波时钟分频系数 + * + * @param Div + * @arg FILTER_CLOCK_DIV1 + * @arg FILTER_CLOCK_DIV2 + * @arg FILTER_CLOCK_DIV4 + */ +void ATIM_SetFilterClockDiv(ATIM_FilterClockDivTypeDef Div) +{ + CW_ATIM->CR1_f.CKD = Div; +} diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_btim.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_btim.c new file mode 100644 index 0000000..158c95e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_btim.c @@ -0,0 +1,462 @@ +/** + * @file cw32l012_btim.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_btim.h" +#include "cw32l012_sysctrl.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/******************************************************************************* +// 说明：去初始化 +// 参数：BTIMx x为1~3 +// 返回值：无 +*******************************************************************************/ + +void BTIM_DeInit(BTIM_TypeDef* BTIMx) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + + BTIMx->CR1 = 0UL; + BTIMx->CR2 = 0UL; + BTIMx->SMCR = 0UL; + BTIMx->DIER = 0UL; + BTIMx->ICR = 0UL; + BTIMx->CNT = 0UL; + BTIMx->PSC = 0UL; + BTIMx->ARR = 0x0000FFFF; +} + +/******************************************************************************* +// 说明：BTIM基本定时器初始化 +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_TimeBaseInitStruct 指向BTIM_TimeBaseInitTypeDef类型结构体的指针 +// 返回值：无 +*******************************************************************************/ +void BTIM_TimeBaseInit(BTIM_TypeDef* BTIMx, BTIM_TimeBaseInitTypeDef* BTIM_TimeBaseInitStruct) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_MODE(BTIM_TimeBaseInitStruct->BTIM_Mode)); + assert_param(IS_BTIM_PRS_DIV(BTIM_TimeBaseInitStruct->BTIM_Prescaler)); + assert_param(IS_BTIM_COUNT_MODE(BTIM_TimeBaseInitStruct->BTIM_CountMode)); + + + /* 使能BTIM的APB时钟 */ + CW_SYSCTRL->APBEN2 |= SYSCTRL_KEY | SYSCTRL_APBEN2_BTIM123_Msk; + + /* 配置BTIM的工作模式 */ + BTIMx->ARR = BTIM_TimeBaseInitStruct->BTIM_Period; + BTIMx->PSC = BTIM_TimeBaseInitStruct->BTIM_Prescaler; + REGBITS_MODIFY(BTIMx->CR1, BTIMx_CR1_ONESHOT_Msk, + BTIM_TimeBaseInitStruct->BTIM_CountMode); + REGBITS_MODIFY(BTIMx->SMCR, BTIMx_SMCR_SMS_Msk, BTIM_TimeBaseInitStruct->BTIM_Mode); +} + + + +/******************************************************************************* +// 说明：使能BTIMx定时器 +// 参数：BTIM_TimeBaseInitStruct +// 返回值：无 +*******************************************************************************/ +void BTIM_Cmd(BTIM_TypeDef* BTIMx, FunctionalState NewState) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + NewState ? (BTIMx->CR1 |= BTIMx_CR1_EN_Msk) : (BTIMx->CR1 &= ~BTIMx_CR1_EN_Msk); +} + + +/******************************************************************************* +// 说明：配置BTIMx的中断 +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_IT 中断事件类型 +// 参数：NewState 中断事件类型的状态，ENABLE 或 DISABLE +// 返回值：无 +*******************************************************************************/ +void BTIM_ITConfig(BTIM_TypeDef* BTIMx, uint16_t BTIM_IT, FunctionalState NewState) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_BTIM_IT(BTIM_IT)); + + NewState ? ( BTIMx->DIER |= BTIM_IT) : (BTIMx->DIER &= ~BTIM_IT); +} +/******************************************************************************* +// 说明： 检查BTIM的中断状态寄存器的各状态位是否置位 +// 参数： BTIMx CW_BTIM1~3 +// 参数： BTIM_FLAG 指定的状态位 ，参数范围： BTIM_IT_UPDATE +// BTIM_IT_TI +// +// 返回值： 无 +*******************************************************************************/ +FlagStatus BTIM_GetITStatus(BTIM_TypeDef* BTIMx, uint16_t BTIM_FLAG) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_IT(BTIM_FLAG)); + + return (REGBITS_GET(BTIMx->ISR, BTIM_FLAG) ? SET : RESET); +} + +/******************************************************************************* +// 说明： 清除BTIM的状态寄存器的各状态位 +// 参数： BTIMx CW_BTIM1~3 +// 参数： BTIM_FLAG 指定的状态位 ，参数范围： BTIM_IT_UPDATE +// BTIM_IT_TI +// +// 返回值： 无 +*******************************************************************************/ +void BTIM_ClearITPendingBit(BTIM_TypeDef* BTIMx, uint16_t BTIM_FLAG) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_IT(BTIM_FLAG)); + + REGBITS_CLR(BTIMx->ICR, BTIM_FLAG); +} + +/******************************************************************************* +// 说明： 软件产生事件 +// 参数： BTIMx CW_BTIM1~3 +// 参数： EventSource 事件源 BTIM_EVENTSOURCE_TRIG +// BTIM_EVENTSOURCE_UPDATE +// +// 返回值： 无 +*******************************************************************************/ +void BTIM_GenerateEvent(BTIM_TypeDef* BTIMx, uint16_t EventSource) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_EVENTSOURCE(EventSource)); + + BTIMx->EGR |= EventSource; +} + +/******************************************************************************* +// 说明：配置BTIMx的工作模式 +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_Mode 模式类型 +// BTIM_MODE_TIMER 定时器模式 +// BTIM_MODE_COUNTER 计数器模式 +// BTIM_MODE_TRIGGER 触发启动模式 +// BTIM_MODE_GATE 门控模式 +// 返回值：无 +*******************************************************************************/ +void BTIM_ModeConfig(BTIM_TypeDef* BTIMx, uint16_t BTIM_Mode) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_MODE(BTIM_Mode)); + + REGBITS_MODIFY(BTIMx->SMCR , BTIMx_SMCR_SMS_Msk, BTIM_Mode); +} + + +/******************************************************************************* +// 说明：配置BTIMx的计数模式 +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_CountMode 运行类型 +// BTIM_COUNT_MODE_SINGLE 单次运行 +// BTIM_COUNT_MODE_REPETITIVE 连续运行 +// 返回值：无 +*******************************************************************************/ +void BTIM_SelectOnePulseMode(BTIM_TypeDef* BTIMx, uint16_t BTIM_CountMode) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_COUNT_MODE(BTIM_CountMode)); + + REGBITS_MODIFY(BTIMx->CR1, BTIMx_CR1_ONESHOT_Msk, BTIM_CountMode); +} + +/******************************************************************************* +// 说明：配置BTIMx的翻转输出功能 +// 参数：BTIMx CW_BTIM1~3 +// 参数：NewState ENABLE 或 DISABLE +// 返回值：无 +*******************************************************************************/ +void BTIM_OutputToggleCmd(BTIM_TypeDef* BTIMx, FunctionalState NewState) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + NewState ? (BTIMx->CR1 |= BTIMx_CR1_TOGEN_Msk) : (BTIMx->CR1 &= ~BTIMx_CR1_TOGEN_Msk); +} + +/******************************************************************************* +// 说明：设置BTIM的计数初值 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Counter 范围0x0000~0xFFFF +// 返回值：无 +*******************************************************************************/ +void BTIM_SetCounter(BTIM_TypeDef* BTIMx, uint16_t Counter) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + + BTIMx->CNT = Counter; +} + +/******************************************************************************* +// 说明：获取BTIM的当前计数值 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：CNT寄存器的值 +*******************************************************************************/ +uint16_t BTIM_GetCounter(BTIM_TypeDef* BTIMx) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + + return BTIMx->CNT; +} + +/******************************************************************************* +// 说明：设置BTIM的自动重载值 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Autoreload 范围0x0000~0xFFFF +// 返回值：无 +*******************************************************************************/ +void BTIM_SetAutoreload(BTIM_TypeDef* BTIMx, uint16_t Autoreload) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + + BTIMx->ARR = Autoreload; +} + +/******************************************************************************* +// 说明：获取BTIM的当前自动重载值 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：ARR寄存器的值 +*******************************************************************************/ +uint16_t BTIM_GetAutoreload(BTIM_TypeDef* BTIMx) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + + return BTIMx->ARR; +} + +/******************************************************************************* +// 说明：配置BTIMx的预分配系数 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Prescaler 预分配系数 +// 返回值：无 +*******************************************************************************/ +void BTIM_SetPrescaler(BTIM_TypeDef* BTIMx, uint16_t Prescaler) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_PRS_DIV(Prescaler)); + + BTIMx->PSC = Prescaler - 1; +} + +/******************************************************************************* +// 说明：获取BTIM的当前预分配系数 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：预分频器当前正在使用的分频系数,实际的分配值为预分配系数PSC+1 +*******************************************************************************/ +uint16_t BTIM_GetPrescaler(BTIM_TypeDef* BTIMx) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + + return BTIMx->PSC; +} + +/******************************************************************************* +// 说明：UPDATE位重映射配置 +// 参数：BTIMx CW_BTIM1~3 +// 参数：State ENABLE 或 DISABLE +// 返回值： 无 +*******************************************************************************/ +void BTIM_ConfigUpdateRemap(BTIM_TypeDef* BTIMx, FunctionalState State) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + State ? (BTIMx->CR1 |= BTIM_UPDATE_REMAP_ENABLE) : (BTIMx->CR1 &= ~BTIM_UPDATE_REMAP_ENABLE); +} + +/******************************************************************************* +// 说明：配置BTIMx的外部输入ETR +// 参数：BTIMx CW_BTIM1~3 +// 参数：BTIM_ETRConfigStruct ETR滤波器参数 +// 返回值：无 +*******************************************************************************/ +void BTIM_ETRConfig(BTIM_TypeDef* BTIMx, BTIM_ETRConfigTypeDef *BTIM_ETRConfigStruct) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_ETR_FILTER(BTIM_ETRConfigStruct->BTIM_ETR_Fliter)); + + + + REGBITS_MODIFY(BTIMx->SMCR, BTIMx_SMCR_TRGIFLT_Msk, BTIM_ETRConfigStruct->BTIM_ETR_Fliter); +} + + +/******************************************************************************* +// 说明：配置BTIMx的ARR预装载功能 +// 参数：BTIMx CW_BTIM1~3 +// 参数：NewState Enable or Disable +// 返回值：无 +*******************************************************************************/ +void BTIM_AutoReloadPreloadConfig(BTIM_TypeDef* BTIMx, FunctionalState NewState) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + (NewState) ? (BTIMx->CR1 |= BTIM_ARR_PRELOAD_ENABLE) : (BTIMx->CR1 &= ~BTIM_ARR_PRELOAD_ENABLE); +} + +/******************************************************************************* +// 说明：配置BTIMx的更新请求 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Source BTIM_UPDATE_REQUEST_SOURCE_OVERFLOW BTIM_UPDATE_REQUEST_SOURCE_FLEXIBLE +// 返回值：无 +*******************************************************************************/ +void BTIM_UpdateRequestSourceConfig(BTIM_TypeDef* BTIMx, uint16_t Source) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_UPDATE_REQUEST(Source)); + REGBITS_MODIFY(BTIMx->CR1, BTIMx_CR1_URS_Msk, Source); +} + +/******************************************************************************* +// 说明：使能BTIMx的事件更新请求 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：无 +*******************************************************************************/ +void BTIM_EnableUpdateEvent(BTIM_TypeDef* BTIMx) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + + REGBITS_CLR(BTIMx->CR1, BTIMx_CR1_UDIS_Msk); +} + +/******************************************************************************* +// 说明：禁止BTIMx的事件更新请求 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：无 +*******************************************************************************/ +void BTIM_DisableUpdateEvent(BTIM_TypeDef* BTIMx) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + + REGBITS_SET(BTIMx->CR1, BTIMx_CR1_UDIS_Msk); +} + +/******************************************************************************* +// 说明：配置BTIMx的触发输入信号来源 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Source 触发源 +// 参数：Polarity 极性 BTIM_TRIGGER_POLARITY_POSITIVE， BTIM_TRIGGER_POLARITY_NEGATIVE +// 返回值：无 +*******************************************************************************/ +void BTIM_TriggerInputConfig(BTIM_TypeDef* BTIMx, uint16_t Source, uint32_t Polarity) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_TRIGGER_SELECTION(Source)); + assert_param(IS_BTIM_TRIGGER_POLARITY(Polarity)); + + REGBITS_MODIFY(BTIMx->SMCR, BTIMx_SMCR_TRGIPOL_Msk |BTIMx_SMCR_TRGISRC_Msk, (Source) |(Polarity)); +} + +/******************************************************************************* +// 说明：配置BTIMx的复位输入信号来源 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Source 复位源 +// 参数：Polarity 极性 BTIM_RESET_POLARITY_POSITIVE， BTIM_RESET_POLARITY_NEGATIVE +// 返回值：无 +*******************************************************************************/ +void BTIM_ResetInputConfig(BTIM_TypeDef* BTIMx, uint16_t Source, uint32_t Polarity) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_RESET_SELECTION(Source)); + assert_param(IS_BTIM_RESET_POLARITY(Polarity)); + + REGBITS_MODIFY(BTIMx->SMCR, BTIMx_SMCR_RSTIPOL_Msk |BTIMx_SMCR_RSTISRC_Msk, (Source) |(Polarity)); +} + +/******************************************************************************* +// 说明：配置BTIMx在主模式下的输出 +// 参数：BTIMx CW_BTIM1~3 +// 参数：Source TRGO信号生成的来源 +// 返回值：无 +*******************************************************************************/ +void BTIM_MasterOutputTriggerConfig(BTIM_TypeDef* BTIMx, uint16_t source) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_MASTER_OUTPUT_TRIGGER(source)); + + BTIMx->CR2 = source; +} + +/******************************************************************************* +// 说明：配置BTIMx在从模式下同步使能 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：无 +*******************************************************************************/ +void BTIM_SlaveSynchronEnable(BTIM_TypeDef* BTIMx) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + REGBITS_SET(BTIMx->SMCR, BTIMx_SMCR_MSM_Msk); +} + +/******************************************************************************* +// 说明：配置BTIMx在从模式下同步使能 +// 参数：BTIMx CW_BTIM1~3 +// 返回值：无 +*******************************************************************************/ +void BTIM_SlaveSynchronDisable(BTIM_TypeDef* BTIMx) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + REGBITS_CLR(BTIMx->SMCR, BTIMx_SMCR_MSM_Msk); +} + +/* + + +*/ +void BTIM_DMACmd(BTIM_TypeDef* BTIMx, uint16_t Source, FunctionalState NewState) +{ + assert_param(IS_BTIM_ALL_PERIPH(BTIMx)); + assert_param(IS_BTIM_DMA_SOURCE(Source)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState) + { + BTIMx->DIER |= Source; + } + else + { + BTIMx->DIER &= ~Source; + } +} + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_cordic.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_cordic.c new file mode 100644 index 0000000..59e84b4 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_cordic.c @@ -0,0 +1,181 @@ +/** + * @file cw32l012_cordic.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_sysctrl.h" +#include "cw32l012_cordic.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +// 初始化CORDIC模块 +void CORDIC_Init(cordic_init_t *init) { + uint32_t csr_value = 0; + + __SYSCTRL_CORDIC_CLK_ENABLE(); + // 配置运算函数 + csr_value |= init->func << CORDIC_CSR_FUNC_Pos; + + // 配置扩展范围 + csr_value |= init->scale << CORDIC_CSR_SCALE_Pos; + + // 配置数据格式 + csr_value |= init->format << CORDIC_CSR_FORMAT_Pos; + + // 配置迭代次数 + csr_value |= init->iter << CORDIC_CSR_ITER_Pos; + + // 配置伸缩因子补偿 + csr_value |= init->comp << CORDIC_CSR_COMP_Pos; + + // 配置中断使能 + csr_value |= init->ie << CORDIC_CSR_IE_Pos; + + // 配置DMA使能（运算完成） + csr_value |= init->dmaeoc << CORDIC_CSR_DMAEOC_Pos; + + // 配置DMA使能（空闲状态） + csr_value |= init->dmaidle << CORDIC_CSR_DMAIDLE_Pos; + + // 写入控制及状态寄存器 + CW_CORDIC->CSR = csr_value; +} + +// 获取CORDIC模块状态 +cordic_status_t CORDIC_GetStatus(void) { + cordic_status_t status; + uint32_t csr_value = CW_CORDIC->CSR; + + status.busy = (csr_value & CORDIC_CSR_BUSY_Msk) ? 1 : 0; + status.eoc = (csr_value & CORDIC_CSR_EOC_Msk) ? 1 : 0; + + return status; +} + +// 设置运算函数 +void CORDIC_SetFunction(cordic_func_t func) { + uint32_t csr_value = CW_CORDIC->CSR; + csr_value &= ~CORDIC_CSR_FUNC_Msk; // 清除旧的函数配置 + csr_value |= (func & CORDIC_CSR_FUNC_Msk) << CORDIC_CSR_FUNC_Pos; // 设置新的函数配置 + CW_CORDIC->CSR = csr_value; +} + +// 设置扩展范围 +void CORDIC_SetScale(uint8_t scale) { + uint32_t csr_value = CW_CORDIC->CSR; + csr_value &= ~CORDIC_CSR_SCALE_Msk; // 清除旧的扩展范围配置 + csr_value |= (scale << CORDIC_CSR_SCALE_Pos) & CORDIC_CSR_SCALE_Msk; // 设置新的扩展范围配置 + CW_CORDIC->CSR = csr_value; +} + +// 设置数据格式 +void CORDIC_SetFormat(cordic_format_t format) { + uint32_t csr_value = CW_CORDIC->CSR; + csr_value &= ~CORDIC_CSR_FORMAT_Pos; // 清除旧的数据格式配置 + csr_value |= (format << CORDIC_CSR_FORMAT_Pos) & CORDIC_CSR_FORMAT_Msk; // 设置新的数据格式配置 + CW_CORDIC->CSR = csr_value; +} + +// 设置迭代次数 +void CORDIC_SetIter(uint8_t iter) { + uint32_t csr_value = CW_CORDIC->CSR; + csr_value &= ~CORDIC_CSR_ITER_Msk; // 清除旧的迭代次数配置 + csr_value |= (iter << CORDIC_CSR_ITER_Pos) & CORDIC_CSR_ITER_Msk; // 设置新的迭代次数配置 + CW_CORDIC->CSR = csr_value; +} + +// 设置伸缩因子补偿 +void CORDIC_SetComp(uint8_t comp) { + uint32_t csr_value = CW_CORDIC->CSR; + csr_value &= ~CORDIC_CSR_COMP_Msk; // 清除旧的伸缩因子补偿配置 + csr_value |= (comp << CORDIC_CSR_COMP_Pos) & CORDIC_CSR_COMP_Msk; // 设置新的伸缩因子补偿配置 + CW_CORDIC->CSR = csr_value; +} + +// 设置中断使能 +void CORDIC_SetIE(uint8_t ie) { + uint32_t csr_value = CW_CORDIC->CSR; + csr_value &= ~CORDIC_CSR_IE_Msk; // 清除旧的中断使能配置 + csr_value |= (ie << CORDIC_CSR_IE_Pos) & CORDIC_CSR_IE_Msk; // 设置新的中断使能配置 + CW_CORDIC->CSR = csr_value; +} + +// 设置DMA使能（运算完成） +void CORDIC_SetDMAEoc(uint8_t dmaeoc) { + uint32_t csr_value = CW_CORDIC->CSR; + csr_value &= ~CORDIC_CSR_DMAEOC_Msk; // 清除旧的DMA使能配置 + csr_value |= (dmaeoc << CORDIC_CSR_DMAEOC_Pos) & CORDIC_CSR_DMAEOC_Msk; // 设置新的DMA使能配置 + CW_CORDIC->CSR = csr_value; +} + +// 设置DMA使能（空闲状态） +void CORDIC_SetDMAIdle(uint8_t dmaidle) { + uint32_t csr_value = CW_CORDIC->CSR; + csr_value &= ~CORDIC_CSR_DMAIDLE_Msk; // 清除旧的DMA使能配置 + csr_value |= (dmaidle << CORDIC_CSR_DMAIDLE_Pos) & CORDIC_CSR_DMAIDLE_Msk; // 设置新的DMA使能配置 + CW_CORDIC->CSR = csr_value; +} + +// 启动运算 +void CORDIC_StartComputation(void) { + // 根据文档，启动运算的方式取决于输入数据的写入 + // 这里不直接操作CSR寄存器，而是通过写入输入寄存器启动运算 +} + +// 将浮点数转换为Q1.31格式 +int32_t float_to_q1_31(float value) { + return (int32_t)round(value * 2147483648.0); // 2^31 +} + +// 将Q1.31格式转换为浮点数 +float q1_31_to_float(int32_t value) { + return (float)value / 2147483648.0; // 2^31 +} + +// 浮点数转换为Q1.15格式的定点数 +int32_t float_to_q1_15(float value) +{ + return (int32_t)round(value * 32768.0f); +} + +// Q1.15格式的定点数转换为浮点数 +float q1_15_to_float(int32_t value) +{ + return (float)value / 32768.0f; +} + + +//============================================================================= + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_crc.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_crc.c new file mode 100644 index 0000000..a4bc7b3 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_crc.c @@ -0,0 +1,69 @@ +/** + * @file cw32l012_crc.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_crc.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief 采用8bit方式，计数CRC16 + * + * @param CrcMode : CRC16_IBM CRC16_MAXIM + * CRC16_USB CRC16_MODBUS + * CRC16_CCITT CRC16_CCITTFALSE + * CRC16_X25 CRC16_XMODEM + * @param pByteBuf : uint8_t型Buffer指针 + * @param ByteCnt ：0x01 - 0xFFFF + * @return uint16_t ：0x00 - 0xFFFF + */ +uint16_t CRC16_Calc_8bit( uint8_t CrcMode, uint8_t *pByteBuf, uint16_t ByteCnt ) +{ + /* Check the parameters */ + assert_param(IS_CRC_CRC16_MODE(CrcMode)); + CW_CRC->CR = CrcMode; + while ( ByteCnt ) + { + CW_CRC->DR = *pByteBuf; + pByteBuf++; + ByteCnt--; + } + return( CW_CRC->RESULT ); +} + + +//============================================================================= + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_dac.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_dac.c new file mode 100644 index 0000000..3010ab9 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_dac.c @@ -0,0 +1,429 @@ +/** + * @file cw32l012_dac.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* + DAC_CHANNEL1 PB00 + DAC_CHANNEL2 PB01 +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32L012_sysctrl.h" +#include "cw32l012_dac.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ +/** + * @brief DAC 反初始化 + * @param + * @retval + */ +void DAC_DeInit(void) +{ + __SYSCTRL_DAC_CLK_ENABLE(); + CW_DAC->CR0 = 0; + CW_DAC->CR1 = 0; + CW_DAC->DOR1 = 0; + CW_DAC->DOR2 = 0; +} + +/** + * @brief DAC 初始化 + * @param DAC_Channel : DAC_CHANNEL_1 or DAC_CHANNEL_2 + * DAC_InitStruct + * @retval + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +{ + uint32_t ChannelShift = 0, RegTmp =0, RegMAMP = 0; + + __SYSCTRL_DAC_CLK_ENABLE(); + + if (DAC_Channel == DAC_CHANNEL_1) + { + ChannelShift = 0; + CW_DAC->CR0_f.EN1 = 0; // 需关闭EN，才能设置 + } + else + { + ChannelShift = 16; + CW_DAC->CR0_f.EN2 = 0; + } + + + + if (DAC_InitStruct->DAC_WaveformMode == DAC_WAVE_NOISE) + { + RegMAMP = (uint32_t) DAC_InitStruct->DAC_NoiseLFSRUnmaskBits; + } + else if (DAC_InitStruct->DAC_WaveformMode == DAC_WAVE_TRIANGLE) + { + RegMAMP = (uint32_t) DAC_InitStruct->DAC_TriangleAmplitude; + } + else + { + RegMAMP = 0; + } + + RegTmp = DAC_InitStruct->DAC_DMAUnderflowState << DAC_CR0_DMAUDRIE1_Pos | + DAC_InitStruct->DAC_DMAState << DAC_CR0_DMAEN1_Pos | + RegMAMP << DAC_CR0_MAMP1_Pos | + DAC_InitStruct->DAC_WaveformMode << DAC_CR0_WAVE1_Pos | + DAC_InitStruct->DAC_TriggerSource << DAC_CR0_TSEL1_Pos | + DAC_InitStruct->DAC_TriggerState << DAC_CR0_TEN1_Pos | + DAC_InitStruct->DAC_ChannelState << DAC_CR0_EN1_Pos; + CW_DAC->CR0 = (CW_DAC->CR0 & (~(0x0000FFFFUL <CR0 |= (DAC_CR0_EN1_Msk << ChannelShift); + } + else + { + CW_DAC->CR0 &= ~(DAC_CR0_EN1_Msk << ChannelShift); + } +} + +/** + * @brief DAC输出控制 + * @param DAC_Channel : DAC_CHANNEL_1 or DAC_CHANNEL_2 + * NewState : ENABLE, DISABLE + * @retval + */ +void DAC_ChannelOutCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + if (DAC_Channel == DAC_CHANNEL_1) + { + NewState ? (CW_DAC->CR1 |= DAC_CR1_C1OUT_Msk) : (CW_DAC->CR1 &= ~DAC_CR1_C1OUT_Msk); + } + else + { + NewState ? (CW_DAC->CR1 |= DAC_CR1_C2OUT_Msk) : (CW_DAC->CR1 &= ~DAC_CR1_C2OUT_Msk); + } +} + +/** + * @brief DAC软件触发 + * @param DAC_Channel : DAC_CHANNEL_1 or DAC_CHANNEL_2 + * + * @retval + */ +void DAC_SoftwareTrigger(uint32_t DAC_Channel) +{ + if (DAC_Channel == DAC_CHANNEL_1) + { + CW_DAC->SWTRGR_f.SWTRIG1 = 1; + } + else + { + CW_DAC->SWTRGR_f.SWTRIG2 = 1; + } +} + +/** + * @brief DAC双通道软件触发控制 + * @param + * + * @retval + */ +void DAC_DualSoftwareTrigger(void) +{ + CW_DAC->SWTRGR = 0x03; +} + +/** + * @brief DAC输出波形类型控制 + * @param DAC_Channel : DAC_CHANNEL_1 or DAC_CHANNEL_2 + * Amplitude : + * @retval + */ +void DAC_TriangleWaveGenerate(uint32_t DAC_Channel, DAC_TriangleAmplitudeTypeDef Amplitude) +{ + uint32_t RegBackup = CW_DAC->CR0; + + if (DAC_Channel == DAC_CHANNEL_1) + { + CW_DAC->CR0_f.TEN1 = 0; // 禁止时，才能配置 + CW_DAC->CR0_f.EN1 = 0; + RegBackup = (RegBackup & (~(DAC_CR0_MAMP1_Msk|DAC_CR0_WAVE1_Msk))) | (Amplitude<CR0_f.TEN2 = 0; // 禁止时，才能配置 + CW_DAC->CR0_f.EN2 = 0; + RegBackup = (RegBackup & (~(DAC_CR0_MAMP2_Msk|DAC_CR0_WAVE1_Msk))) | (Amplitude<DHR12R1 = Data; + break; + case DAC_ALIGN_12B_L: + CW_DAC->DHR12L1 = Data; + break; + case DAC_ALIGN_8B_R: + CW_DAC->DHR8R1 = Data; + break; + default: + break; + } +} + +/** + * @brief DAC通道2输出幅值控制 + * @param DAC_Align : DAC_ALIGN_12B_R or DAC_ALIGN_12B_L or DAC_ALIGN_8B_R + * Data : + * @retval + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + switch (DAC_Align) + { + case DAC_ALIGN_12B_R: + CW_DAC->DHR12R2 = Data; + break; + case DAC_ALIGN_12B_L: + CW_DAC->DHR12L2 = Data; + break; + case DAC_ALIGN_8B_R: + CW_DAC->DHR8R2 = Data; + break; + default: + break; + } +} + +/** + * @brief DAC双通道输出幅值控制 + * @param DAC_Align : DAC_ALIGN_12B_R or DAC_ALIGN_12B_L or DAC_ALIGN_8B_R + * Data1 : 通道1 + * Data1 : 通道2 + * @retval + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data1, uint16_t Data2) +{ + uint32_t data; + + switch (DAC_Align) + { + case DAC_ALIGN_12B_R: + data = ((uint32_t)Data2 << 16U) | Data1; + CW_DAC->DHR12RD = data; + break; + case DAC_ALIGN_12B_L: + data = ((uint32_t)Data2 << 16U) | Data1; + CW_DAC->DHR12LD = data; + break; + case DAC_ALIGN_8B_R: + data = ((uint32_t)Data2 << 8U) | Data1; + CW_DAC->DHR8RD = data; + break; + default: + break; + } +} + +/** + * @brief DAC读取通道输出幅值 + * @param DAC_Channel : DAC_CHANNEL_1 or DAC_CHANNEL_2 + * + * + * @retval + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + uint16_t ret; + + if (DAC_Channel == DAC_CHANNEL_1) + { + ret = CW_DAC->DOR1 & 0x0FFF; + } + else if (DAC_Channel == DAC_CHANNEL_2) + { + ret = CW_DAC->DOR2 & 0x0FFF; + } + return ret; +} + +/* DMA management functions ***************************************************/ +/** + * @brief DAC的DMA功能控制 + * @param DAC_Channel : DAC_CHANNEL_1 or DAC_CHANNEL_2 + * NewState : ENABLE or DISABLE + * + * @retval + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + if (DAC_Channel == DAC_CHANNEL_1) + { + NewState ? (CW_DAC->CR0_f.DMAEN1 = 1) : (CW_DAC->CR0_f.DMAEN1 = 0); + } + else + { + NewState ? (CW_DAC->CR0_f.DMAEN2 = 1) : (CW_DAC->CR0_f.DMAEN2 = 0); + } +} + +/* Interrupts and flags management functions **********************************/ +/** + * @brief DAC的中断功能配置 + * @param DAC_Channel : DAC_CHANNEL_1 or DAC_CHANNEL_2 + * DAC_IT : DAC_IT_DMA_UNDER + * NewState : ENABLE or DISABLE + * + * @retval + */ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) +{ + if (DAC_Channel == DAC_CHANNEL_1) + { + NewState ? (CW_DAC->CR0_f.DMAUDRIE1 = 1) : (CW_DAC->CR0_f.DMAUDRIE1 = 0); + } + else + { + NewState ? (CW_DAC->CR0_f.DMAUDRIE2 = 1) : (CW_DAC->CR0_f.DMAUDRIE2 = 0); + } +} + +/** + * @brief DAC的标志位读取 + * @param DAC_Channel : DAC_CHANNEL_1 or DAC_CHANNEL_2 + * DAC_FLAG : DAC_IT_DMA_UNDER + * + * @retval + */ +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + FlagStatus ret; + if (DAC_Channel == DAC_CHANNEL_1) + { + if (DAC_FLAG == DAC_IT_DMA_UNDER) + { + ret = (CW_DAC->DOR1 & DAC_FLAG) ? SET :RESET; + } + } + else + { + if (DAC_FLAG == DAC_IT_DMA_UNDER) + { + ret = (CW_DAC->DOR2 & DAC_FLAG) ? SET :RESET; + } + } + return ret; +} + +/** + * @brief DAC的标志清除 + * @param DAC_Channel : DAC_CHANNEL_1 or DAC_CHANNEL_2 + * DAC_FLAG : DAC_IT_DMA_UNDER + * + * @retval + */ +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + if (DAC_Channel == DAC_CHANNEL_1) + { + if (DAC_FLAG == DAC_IT_DMA_UNDER) + { + CW_DAC->DOR1_f.DMAUDR = 0; + } + } + else + { + if (DAC_FLAG == DAC_IT_DMA_UNDER) + { + CW_DAC->DOR2_f.DMAUDR = 0; + } + } +} + +/** + * @brief DAC的中断标志读取 + * @param DAC_Channel : DAC_CHANNEL_1 or DAC_CHANNEL_2 + * DAC_FLAG : DAC_IT_DMA_UNDER + * + * @retval + */ +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + return DAC_GetFlagStatus(DAC_Channel, DAC_IT); +} + +/** + * @brief DAC的中断标志清除 + * @param DAC_Channel : DAC_CHANNEL_1 or DAC_CHANNEL_2 + * DAC_FLAG : DAC_IT_DMA_UNDER + * + * @retval + */ +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + DAC_ClearFlag(DAC_Channel, DAC_IT); +} diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_debug.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_debug.c new file mode 100644 index 0000000..5768bb9 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_debug.c @@ -0,0 +1,69 @@ +/** + * @file cw32l012_debug.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_debug.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief + * + * @param DBGMCU_Periph : DBGMCU_ATIM_STOP DBGMCU_GTIM1_STOP + * DBGMCU_GTIM2_STOP + * DBGMCU_BTIM123_STOP + * DBGMCU_AWT_STOP DBGMCU_RTC_STOP + * DBGMCU_IWDT_STOP DBGMCU_WWDT_STOP + * DBGMCU_LPTIM_STOP + * @param NewState : ENABLE DISABLE + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + CW_SYSCTRL->DEBUG |= DBGMCU_Periph; + } + else + { + CW_SYSCTRL->DEBUG &= ~DBGMCU_Periph; + } +} + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_digitalsign.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_digitalsign.c new file mode 100644 index 0000000..c9c5f89 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_digitalsign.c @@ -0,0 +1,105 @@ +/** + * @file cw32l012_digitalsign.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_digitalsign.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief 获取芯片型号 + * + * @param pChipType : 存放芯片类型的Buffer，最大22字节 + */ +void DIGITALSIGN_GetChipType(uint8_t *pChipType) +{ + uint8_t tmpcnt = 0; + + while( tmpcnt < CHIP_TYPE_LENGTH ) + { + * (uint8_t *)(pChipType + tmpcnt) = *( (uint8_t *) (CHIP_TYPE_BASE + tmpcnt ) ); + tmpcnt ++; + } +} + +/** + * @brief 获取芯片引脚数 + * + * @return uint8_t + */ +uint8_t DIGITALSIGN_GetPinCount(void) +{ + return ( *( (uint8_t *) PIN_COUNT_BASE ) ); +} + +/** + * @brief //获取FLASH容量// + * + * @return uint32_t + */ +uint32_t DIGITALSIGN_GetFlashSize(void) +{ + return ( *( (uint32_t *) FLASH_SIZE_BASE ) ); +} + +/** + * @brief //获取RAM容量// + * + * @return uint16_t + */ +uint16_t DIGITALSIGN_GetRamSize(void) +{ + return ( *( (uint16_t *) RAM_SIZE_BASE ) ); +} + +/** + * @brief 获取芯片UID + * + * @param pChipUid : 存放芯片UID的Buffer的10字节 + */ +void DIGITALSIGN_GetChipUid(uint8_t *pChipUid) +{ + uint8_t tmpcnt = 0; + + while( tmpcnt < CHIP_UID_LENGTH ) + { + * (uint8_t *)(pChipUid + tmpcnt) = *( (uint8_t *) (CHIP_UID_BASE + tmpcnt ) ); + tmpcnt ++; + } +} + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_dma.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_dma.c new file mode 100644 index 0000000..5a48351 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_dma.c @@ -0,0 +1,162 @@ +/** + * @file cw32l012_dma.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_dma.h" +#include "cw32l012_sysctrl.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/******************************************************************************* +// 说明：去初始化 +// 参数： +// 返回值：无 +*******************************************************************************/ + +void DMA_DeInit(DMA_ChannelTypeDef Channel) +{ + __SYSCTRL_DMA_CLK_ENABLE(); + *DMA_CSRy(Channel) = 0x00000000; + *DMA_CNTy(Channel) = 0x00000000; + *DMA_SRCADDRy(Channel) = 0x00000000; + *DMA_DSTADDRy(Channel) = 0x00000000; + *DMA_TRIGy(Channel) = 0x00000000; + *DMA_ICR &= ~((DMA_ICR_TC1_Msk | DMA_ICR_TE1_Msk) << (4*(Channel))); +} + +/******************************************************************************* +// 说明：DMA初始化 +// 参数：Channel +// 参数：DMAInitStruct +// 返回值：无 +*******************************************************************************/ +void DMA_Init(DMA_ChannelTypeDef Channel, DMA_InitTypeDef *DMAInitStruct) +{ + uint32_t Csr = 0; + /* 使能DMA的APB时钟 */ + __SYSCTRL_DMA_CLK_ENABLE(); + + // 配置DMA_CSRy寄存器 + Csr = DMAInitStruct->TransferMode << DMA_CSR1_TRANS_Pos | + DMAInitStruct->SrcIncrement << DMA_CSR1_SRCINC_Pos | + DMAInitStruct->DstIncrement << DMA_CSR1_DSTINC_Pos | + DMAInitStruct->DataSize << DMA_CSR1_SIZE_Pos | + DMAInitStruct->RestartEnable << DMA_CSR1_RESTART_Pos; + + *DMA_CSRy(Channel) = Csr; + + // 配置DMA_CNTy寄存器 + uint32_t Cnt = (DMAInitStruct->TransferCount & 0xFFFF) | ((DMAInitStruct->BlockCount & 0xF) << 16); + *DMA_CNTy(Channel) = Cnt; + + // 配置DMA_SRCADDRy和DMA_DSTADDRy寄存器 + *DMA_SRCADDRy(Channel) = DMAInitStruct->SrcAddress; + *DMA_DSTADDRy(Channel) = DMAInitStruct->DstAddress; + + // 配置DMA_TRIGy寄存器 + uint32_t Trig = (DMAInitStruct->TriggerType << 0) | (DMAInitStruct->TriggerSource << 2); + *DMA_TRIGy(Channel) = Trig; +} + +// 启用DMA通道 +void DMA_Cmd(DMA_ChannelTypeDef channel, FunctionalState state) +{ + state ? (*DMA_CSRy(channel) |= DMA_CSR1_EN_Msk) : (*DMA_CSRy(channel) &= ~DMA_CSR1_EN_Msk); +} + +// 软件启动DMA传输 +void DMA_StartTransfer(DMA_ChannelTypeDef channel) +{ + uint32_t trig_value = *DMA_TRIGy(channel); + + trig_value &= ~(DMA_TRIG1_SOFTSRC_Msk | DMA_TRIG1_TYPE_Msk); + trig_value |= DMA_TRIG1_SOFTSRC_Msk; + *DMA_TRIGy(channel) = trig_value; +} + +// 检查DMA传输状态 +DMA_StatusTypeDef DMA_CheckStatus(DMA_ChannelTypeDef channel) +{ + return (DMA_StatusTypeDef)((*DMA_CSRy(channel) & DMA_CSR1_STATUS_Msk) >> DMA_CSR1_STATUS_Pos); +} + +// 配置DMA触发源 +void DMA_ConfigTriggerSource(DMA_ChannelTypeDef channel, DMA_TriggerTypeDef trigger_type, DMA_TriggerSourceTypeDef trigger_source) +{ + uint32_t trig_value = *DMA_TRIGy(channel); + + trig_value &= DMA_TRIG1_HARDSRC_Msk | DMA_TRIG1_TYPE_Msk; + trig_value |= (trigger_type << DMA_TRIG1_TYPE_Pos) | (trigger_source << DMA_TRIG1_HARDSRC_Pos); + *DMA_TRIGy(channel) = trig_value; +} + +//配置DMA中断 +void DMA_ITConfig(DMA_ChannelTypeDef channel, uint32_t interrupt_type, FunctionalState state) +{ + state ? (*DMA_CSRy(channel) |= (interrupt_type)) :(*DMA_CSRy(channel) &= ~(interrupt_type)); +} + +void DMA_ClearInterruptFlag(DMA_ChannelTypeDef channel, uint32_t interrupt_type) +{ + *DMA_ICR &= ~(interrupt_type << channel); +} + +// 配置DMA通道 +void DMA_ConfigChannel(DMA_ChannelTypeDef channel, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size, uint32_t data_size) +{ + // 先禁止DMA通道，再配置 + *DMA_CSRy(channel) &= ~DMA_CSR1_EN_Msk; + + // 配置源地址 + *DMA_SRCADDRy(channel) = src_addr; + + // 配置目的地址 + *DMA_DSTADDRy(channel) = dst_addr; + + // 配置传输数量 + *DMA_CNTy(channel) = (transfer_size & 0xFFFF); // XFERCNT字段 + + // 配置数据位宽 + uint32_t csr = *DMA_CSRy(channel); + csr &= ~DMA_CSR1_SIZE_Msk; // 清除SIZE字段 + csr |= ((data_size & DMA_CSR1_SIZE_Msk) << DMA_CSR1_SIZE_Pos); // 设置SIZE字段 + *DMA_CSRy(channel) = csr; + + // 启用通道 + *DMA_CSRy(channel) |= DMA_CSR1_EN_Msk; // 设置EN位 +} diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_eau.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_eau.c new file mode 100644 index 0000000..88a1124 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_eau.c @@ -0,0 +1,102 @@ +/** + * @file cw32l012_eau.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_eau.h" +#include "cw32l012_sysctrl.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/******************************************************************************* +// 说明：EAU初始化 +// 参数： +// 参数： +// 返回值：无 +*******************************************************************************/ +// 初始化EAU +void EAU_Init(void) { + // 将控制和状态寄存器清零，确保初始状态 + __SYSCTRL_EAU_CLK_ENABLE(); + CW_EAU->CSR = 0x00000000; +} + +// 设置EAU运算模式 +void EAU_SetMode(EAU_Mode mode) { + // 检查是否忙碌，若忙碌则不修改模式 + if ((CW_EAU->CSR & EAU_CSR_BUSY_Msk) == 0) { + CW_EAU->CSR = (CW_EAU->CSR & ~EAU_CSR_MODE_Msk) | mode; + } +} + +// 开始运算操作 +void EAU_StartOperation(uint32_t dividend, uint32_t divisor) { + // 写入被除数/被开方数 + CW_EAU->DIVIDEND = dividend; + // 写入除数 + CW_EAU->DIVISOR = divisor; +} + +// 获取商/平方根 +uint32_t EAU_GetQuotient(void) { + return CW_EAU->QUOTIENT; +} + +// 获取余数 +uint32_t EAU_GetRemainder(void) { + return CW_EAU->REMAINDER; +} + +// 获取EAU状态 +EAU_Status EAU_GetStatus(void) { + EAU_Status status = EAU_STATUS_IDLE; + + if (CW_EAU->CSR & EAU_CSR_BUSY_Msk) { + status |= EAU_STATUS_BUSY; + } + + if (CW_EAU->CSR & EAU_CSR_ZERO_Msk) { + status |= EAU_STATUS_DIV_ZERO; + } + + if (CW_EAU->CSR & EAU_CSR_OVR_Msk) { + status |= EAU_STATUS_OVERFLOW; + } + + return status; +} + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_flash.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_flash.c new file mode 100644 index 0000000..4509a6e --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_flash.c @@ -0,0 +1,678 @@ +/** + * @file cw32l012_flash.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_flash.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +// 初始化FLASH等待周期 +void FLASH_Init(uint32_t hclk_freq) +{ + // 系统时钟向高频切换时，必须先调用此函数配置FLASH等待周期，否则宕机 + uint32_t wait_cycles; + + // 使能FLASH配置时钟 + CW_SYSCTRL->AHBEN |= (SYSCTRL_AHBEN_FLASH_Msk | 0x5a5a0000); + + // 配置等待周期 + + if (hclk_freq <= 24000000) { + wait_cycles = 0x00; + } else if (hclk_freq <= 48000000) { + wait_cycles = 0x01; + } else if (hclk_freq <= 72000000) { + wait_cycles = 0x02; + } else { + wait_cycles = 0x03; + } + CW_FLASH->CR2 = (FLASH_KEY << FLASH_CR2_KEY_Pos) | (wait_cycles << FLASH_CR2_WAIT_Pos); +} + +/** + * @brief 设置FLASH的读等待周期 + * + * @param FLASH_Latency ：FLASH_Latency_1 FLASH_Latency_2 FLASH_Latency_3 FLASH_Latency_4 + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + // 使能FLASH配置时钟 + CW_SYSCTRL->AHBEN |= (SYSCTRL_AHBEN_FLASH_Msk | 0x5a5a0000); + CW_FLASH->CR2 = (CW_FLASH->CR2 & (~FLASH_CR2_WAIT_Msk)) | (FLASH_KEY << FLASH_CR2_KEY_Pos) | FLASH_Latency; +} + +//设置预取使能 +void FLASH_PrefetchCmd(FunctionalState NewState) +{ + uint32_t RegBack; + + RegBack = CW_FLASH->CR2 & (~FLASH_CR2_FETCH_Msk); + NewState ? RegBack |= FLASH_CR2_FETCH_Msk : RegBack; + CW_FLASH->CR2 = (FLASH_KEY << FLASH_CR2_KEY_Pos) | RegBack; +} + +//设置BUFFER使能 +void FLASH_CacheCmd(FunctionalState NewState) +{ + uint32_t RegBack; + + RegBack = CW_FLASH->CR2 & (~FLASH_CR2_CACHE_Msk); + NewState ? RegBack |= FLASH_CR2_CACHE_Msk : RegBack; + CW_FLASH->CR2 = (FLASH_KEY << FLASH_CR2_KEY_Pos) | RegBack; + +} +//获取FLASH的Fetch状态 +FlagStatus FLASH_GetPrefetchStatus(void) +{ + return CW_FLASH->CR2_f.FETCH ? SET : RESET; +} +//获取FLASH的Cache状态 +FlagStatus FLASH_GetCacheStatus(void) +{ + return CW_FLASH->CR2_f.CACHE ? SET : RESET; +} + + +/** + * @brief 获取当前的读保护等级 + * + * @return uint8_t ：0/1/2/3 + */ +uint8_t FLASH_GetReadOutLevel(void) +{ + return(CW_FLASH->CR1_f.SECURITY); +} + +/** + * @brief 设置MCU的读保护等级,RdLevel的有效取值范围为0,1,2,3 + * //将等级写入MCU后，MCU会自动重启并完成读保护等级修改 + * //如果从非0等级变为等级0，则MCU会擦除FLASH内的所有数据 + * //Level0，ISP可读写，SWD可读写 + * //Level1，ISP可降级，SWD可降级；数据不可读出 + * //Level2，ISP可降级，SWD无功能；数据不可读出 + * //Level3，ISP无功能，SWD无功能；数据不可读出 + * @param RdLevel : FLASH_RDLEVEL0 FLASH_RDLEVEL1 + * : FLASH_RDLEVEL2 FLASH_RDLEVEL3 + */ +void FLASH_SetReadOutLevel(uint16_t RdLevel) +{ + assert_param(IS_FLASH_RDLEVEL(RdLevel)); + + if (FLASH_GetReadOutLevel() != RdLevel) + { + RdLevel = 0x5A50 | (RdLevel & 0x03u); + *((volatile uint32_t*)(0x4000431C)) = RdLevel; + *((volatile uint32_t*)(0x40004370)) = 0x5A5AABCD; //MCU重启以更新读保护等级 + + while (1); //MCU重启以更新保护等级 + } +} + +/** + * @brief 解锁所有页面 + * + */ +void FLASH_UnlockAllPages(void) +{ + CW_FLASH->PAGELOCK = 0x5A5Affff; //解锁所有页面 + +} + +/** + * @brief 锁定所有页面 + * + */ +void FLASH_LockAllPages(void) +{ + CW_FLASH->PAGELOCK = 0x5A5A0000; +} + +/** + * @brief 解锁指定页面 + * + * @param Page_Number : 0 ~ FLASH_PAGES_SIZE-1 + * @return uint8_t : 正常返回0x00 + */ +uint8_t FLASH_UnlockPage(uint16_t Page_Number) +{ + uint16_t Currentlockstatus; + + assert_param(IS_FLASH_PAGE_Number(Page_Number)); + + Currentlockstatus = CW_FLASH->PAGELOCK; //读取当前锁定位 + CW_FLASH->PAGELOCK = 0x5A5A0000 | Currentlockstatus | (1UL << (Page_Number / 8)); //解锁指定页面 + return(0x00); +} + +/** + * @brief 解锁指定地址范围内所有页面,返回0x00代表成功，非0代表失败 + * + * @param StartAddr : 0x00000000 - 0x0000FFFF + * @param EndAddr : 0x00000000 - 0x0000FFFF + * @return uint8_t ：错误返回0x80，正确返回0x00 + */ +uint8_t FLASH_UnlockPages(uint32_t StartAddr, uint32_t EndAddr) +{ + uint16_t Currentlockstatus; + uint16_t UnlockMask, UnlockIdx; + + UnlockMask = 0x00; + + if (StartAddr > EndAddr) + { + return (FLASH_ERROR_ADDR); //待解锁页面地址出错 + } + + if ((StartAddr > FLASH_END_ADDRESS) || (EndAddr > FLASH_END_ADDRESS)) + { + return(FLASH_ERROR_ADDR); + } + + while( StartAddr <= EndAddr ) + { + UnlockIdx = StartAddr / 512 / 8; + UnlockMask |= (1UL << UnlockIdx); + StartAddr += 512; + } + + if (UnlockMask == 0x00) + { + return(FLASH_ERROR_ADDR); //待解锁页面地址出错 + } + + Currentlockstatus = CW_FLASH->PAGELOCK; //读取当前锁定位 + CW_FLASH->PAGELOCK = 0x5A5A0000 | Currentlockstatus | UnlockMask; //解锁页面所在的区块 + return(0x00); +} + +/** + * @brief 擦除指定页 + * + * @param Page_Number : 0 - 127 + * @return uint8_t ：错误返回0x80，正确返回0x00 + */ +uint8_t FLASH_ErasePage(uint16_t Page_Number) +{ + uint16_t CR1BAK, CR2BAK; + + if( ( Page_Number >= FLASH_PAGES_SIZE ) ) + { + return(FLASH_ERROR_ADDR); + } + + while(CW_FLASH->ISR_f.BUSY); //等待上1次操作完成，未作超时处理 + + CW_FLASH->ICR = 0x00; //clear all int flag + CR2BAK = CW_FLASH->CR2; + CR1BAK = CW_FLASH->CR1; + CW_FLASH->CR1 = 0x5A5A0000 | (CR1BAK | 0x02u); // 设置为页擦模式 + + *((volatile uint8_t*)(Page_Number * 512)) = 0x00; //erase page + + while(CW_FLASH->ISR_f.BUSY); //等待操作完成 + + CW_FLASH->CR1 = 0x5A5A0000 | CR1BAK; + CW_FLASH->CR2 = 0x5A5A0000 | CR2BAK; + return(CW_FLASH->ISR); +} + + +/** + * @brief 擦除从STARTADDR到ENDADDR所在的页面,返回0x00代表成功，非0代表失败 + * + * @param StartAddr : 0x00000000 - 0x0000FFFF + * @param EndAddr : 0x00000000 - 0x0000FFFF + * @return uint8_t ：错误返回0x80，正确返回0x00 + */ +uint8_t FLASH_ErasePages(uint32_t StartAddr, uint32_t EndAddr) +{ + uint16_t CR1BAK; + + if ((StartAddr > FLASH_END_ADDRESS) || (EndAddr > FLASH_END_ADDRESS)) + { + return(FLASH_ERROR_ADDR); + } + + while(CW_FLASH->ISR_f.BUSY); //等待上1次操作完成，未作超时处理 + + CW_FLASH->ICR = 0x00; //clear all int flag + CR1BAK = CW_FLASH->CR1; + + CW_FLASH->CR1 = 0x5A5A0000 | ( CR1BAK | 0x02u ); // 设置为页擦模式 + + while( StartAddr <= EndAddr ) + { + *((volatile uint32_t *)(StartAddr)) = 0x00; //erase page + while(CW_FLASH->ISR_f.BUSY); //等待操作完成 + StartAddr += 512; + } + + + CW_FLASH->CR1 = 0x5A5A0000 | CR1BAK;//设置FLASH操作模式为读模式 + return(CW_FLASH->ISR); +} + + +/** + * @brief 以WriteAddr作为起始地址，依次写入pWrBuf内的WrByteCnt个字节的数据 + * //待写入起始地址和结束地址需要位于同一个页面以内 + * //待写入地址的页面已做擦除，并解除保护 + * //返回0x00代表成功，非0代表失败 + * @param WriteAddr : 0x00000000 - 0x0000FFFF + * @param pWrBuf : 数据地址 + * @param WrByteCnt ：1-65535 + * @return uint8_t ：错误返回0x80，正确返回0x00 + */ +uint8_t FLASH_WriteBytes(uint32_t WriteAddr, uint8_t* pWrBuf, uint16_t WrByteCnt) +{ + uint16_t CR1BAK; + + if( WriteAddr + WrByteCnt > FLASH_BYTES_SIZE ) + { + return(FLASH_ERROR_ADDR); + } + + while( CW_FLASH->ISR_f.BUSY); //等待上1次操作完成，未作超时处理 + + CW_FLASH->ICR = 0x00; //clear all int flag + CR1BAK = CW_FLASH->CR1; + CW_FLASH->CR1 = 0x5A5A0000 | ( CR1BAK | 0x01u ); // 设置为页写模式 + + while( WrByteCnt ) + { + *((volatile uint8_t *)(WriteAddr)) = *pWrBuf; //write byte + while( CW_FLASH->ISR_f.BUSY); //等待操作完成 + WriteAddr++; + WrByteCnt--; + pWrBuf++; + } + CW_FLASH->CR1 = 0x5A5A0000 | CR1BAK; + return( CW_FLASH->ISR ); +} + +/** + * @brief 以WriteAddr作为起始地址，依次写入pWrBuf内的WrByteCnt个半字（16bit）的数据 + * + * @param WriteAddr + * @param pWrBuf + * @param WrByteCnt + * @return uint8_t + */ +uint8_t FLASH_WriteHalfWords(uint32_t WriteAddr, uint16_t* pWrBuf, uint16_t WrByteCnt) +{ + uint16_t CR1BAK, CR2BAK; + + if (WriteAddr + WrByteCnt > FLASH_BYTES_SIZE) + { + return(FLASH_ERROR_ADDR); + } + + if ((WriteAddr & 0x00000001) != 0) // 地址未对齐 + { + return(FLASH_ERROR_ADDR); + } + + while( CW_FLASH->ISR_f.BUSY); //等待上1次操作完成，未作超时处理 + + CW_FLASH->ICR = 0x00; //clear all int flag + CR2BAK = CW_FLASH->CR2; + CR1BAK = CW_FLASH->CR1; + CW_FLASH->CR1 = 0x5A5A0000 | (CR1BAK | 0x01u); // 设置为页写模式 + + while (WrByteCnt) + { + *((volatile uint16_t*)(WriteAddr)) = *pWrBuf; //write byte + + while (CW_FLASH->ISR_f.BUSY); //等待操作完成 + + WriteAddr += 2; + WrByteCnt--; + pWrBuf++; + } + + CW_FLASH->CR1 = 0x5A5A0000 | CR1BAK; + CW_FLASH->CR2 = 0x5A5A0000 | CR2BAK; + return(CW_FLASH->ISR); + +} + +/** + * @brief 以WriteAddr作为起始地址，依次写入pWrBuf内的WrByteCnt个字（32bit）的数据 + * + * @param WriteAddr + * @param pWrBuf + * @param WrByteCnt + * @return uint8_t + */ +uint8_t FLASH_WriteWords(uint32_t WriteAddr, uint32_t* pWrBuf, uint16_t WrByteCnt) +{ + uint16_t CR1BAK, CR2BAK; + + if (WriteAddr + WrByteCnt > FLASH_BYTES_SIZE) + { + return(FLASH_ERROR_ADDR); + } + + if ((WriteAddr & 0x00000003) != 0) // 地址未对齐 + { + return(FLASH_ERROR_ADDR); + } + + while (CW_FLASH->ISR_f.BUSY); //等待上1次操作完成，未作超时处理 + + CW_FLASH->ICR = 0x00; //clear all int flag + CR2BAK = CW_FLASH->CR2; + CR1BAK = CW_FLASH->CR1; + CW_FLASH->CR1 = 0x5A5A0000 | (CR1BAK | 0x01u); // 设置为页写模式 + + while (WrByteCnt) + { + *((volatile uint32_t*)(WriteAddr)) = *pWrBuf; //write byte + + while (CW_FLASH->ISR & bv5); //等待操作完成 + + WriteAddr += 4; + WrByteCnt--; + pWrBuf++; + } + + CW_FLASH->CR1 = 0x5A5A0000 | CR1BAK; + CW_FLASH->CR2 = 0x5A5A0000 | CR2BAK; + return(CW_FLASH->ISR); +} +/** + * @brief 锁定指定页面,返回0x00代表成功，非0代表失败 + * + * @param Page_Number : 0 - 127 + * @return uint8_t : 正常返回0x00 + */ +uint8_t FLASH_LockPage(uint16_t Page_Number) +{ + uint16_t Currentlockstatus; + + assert_param(IS_FLASH_PAGE_Number(Page_Number)); + + Currentlockstatus = CW_FLASH->PAGELOCK; //读取当前锁定位 + CW_FLASH->PAGELOCK = (0x5A5A0000 | Currentlockstatus) & (~(1UL << (Page_Number / 8))); //锁定指定页面 + return(0x00); +} + +/** + * @brief 锁定指定地址范围内所有页面,返回0x00代表成功，非0代表失败 + * + * @param StartAddr : 0x00000000 - 0x0000FFFF + * @param EndAddr : 0x00000000 - 0x0000FFFF + * @return uint8_t : 错误返回0x80，正常返回0x00 + */ +uint8_t FLASH_LockPages(uint32_t StartAddr, uint32_t EndAddr) +{ + uint16_t UnlockMask, UnlockIdx; + uint16_t Currentlockstatus; + + UnlockMask = 0x00; + + if (EndAddr > StartAddr) + { + return (FLASH_ERROR_ADDR); //待锁定页面地址出错 + } + + if ((StartAddr > FLASH_END_ADDRESS) || (EndAddr > FLASH_END_ADDRESS)) + { + return(FLASH_ERROR_ADDR); + } + + while( StartAddr <= EndAddr ) + { + UnlockIdx = StartAddr / 512 / 8; + UnlockMask |= (1UL << UnlockIdx); + StartAddr += 512; + } + + if (UnlockMask == 0x00) + { + return(FLASH_ERROR_ADDR); //待锁定页面地址出错 + } + + Currentlockstatus = CW_FLASH->PAGELOCK; //读取当前锁定位 + CW_FLASH->PAGELOCK = ( (0x5A5A0000 | Currentlockstatus) & (~UnlockMask) ); //锁定页面所在的区块 + return(0x00); +} + +/** + * @brief FLASH中断配置 + * + * @param FLASH_IT : FLASH_IT_PROG + * FLASH_IT_PAGELOCK + * FLASH_IT_PC + * @param NewState : ENABLE DISABLE + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + CW_FLASH->IER |= FLASH_IT; + } + else + { + CW_FLASH->IER &= (~FLASH_IT); + } +} + +/** + * @brief 获取FLASH指定中断状态 + * + * @param FLASH_IT : FLASH_IT_PROG + * FLASH_IT_PAGELOCK + * FLASH_IT_PC + * @return ITStatus : SET RESET + */ +ITStatus FLASH_GetITStatus(uint32_t FLASH_IT) +{ + assert_param(IS_FLASH_GET_IT(FLASH_IT)); + + return (ITStatus)(!!(CW_FLASH->ISR & FLASH_IT)); +} + + +/** + * @brief 清除FLASH指定中断标志 + * + * @param FLASH_IT : FLASH_IT_PROG + * FLASH_IT_PAGELOCK + * FLASH_IT_PC + */ +void FLASH_ClearITPendingBit(uint32_t FLASH_IT) +{ + assert_param(IS_FLASH_IT(FLASH_IT)); + + CW_FLASH->ICR &= (~FLASH_IT); +} + +/** + * @brief 获取FLASH模块的状态 + * + * @return uint8_t 00:正常 + * FLASH_FLAG_BSY 忙 + * FLASH_FLAG_PCERR 擦写PC指针所在页错误 + * FLASH_FLAG_WRPRTERR 擦写未解锁保护页错误 + * FLASH_FLAG_PGERR 编程目标地址数据不全为0XFF错误 + */ +uint32_t FLASH_GetStatus(void) +{ + uint32_t flashstatus; + + flashstatus = CW_FLASH->ISR; + + if (flashstatus & FLASH_FLAG_BSY) + { + return FLASH_FLAG_BSY; + } + + if (flashstatus & FLASH_FLAG_PCERR) + { + return FLASH_FLAG_PCERR; + } + + if (flashstatus & FLASH_FLAG_WRPRTERR) + { + return FLASH_FLAG_WRPRTERR; + } + + if (flashstatus & FLASH_FLAG_PGERR) + { + return FLASH_FLAG_PGERR; + } + + return FLASH_FLAG_OK; +} +/******************************************************************************* + * @brief 向OTP的指定地址写入数据 + * @param WriteAddr: 待写入数据的OTP的起始地址 + * @param pWrBuf : 待写入的数据的指针 + * @param WrByteCnt: 待写入的数据的字节数量 + * @retval 0x00 : 代表成功 + * 0x01 : 代表失败 + * @note OTP区域的大小为22字节，掉电后数据不会丢失，每个字节一旦编程后不可再擦除。 + * OTP的起始地址、终止地址请参见手册或cw32l01x_flash.h文件的定义。 + */ +uint8_t OTP_WriteBytes(uint32_t WriteAddr, uint8_t* pWrBuf, uint16_t WrByteCnt) +{ + uint16_t CR1BAK; + + // 验证地址是否合法 + if ((WriteAddr < OTP_START_ADDRESS) || ((WriteAddr + WrByteCnt - 1) > OTP_END_ADDRESS)) + { + return 0x01; + } + + while (CW_FLASH->ISR_f.BUSY); //等待上1次操作完成，未作超时处理 + + CW_FLASH->ICR = 0x00; //clear all int flag + CR1BAK = CW_FLASH->CR1; + + CW_FLASH->CR1 = 0x5A5A0000 | 0x01u; // 设置为写模式 + + while(WrByteCnt) + { + *((volatile uint8_t *)(WriteAddr)) = *pWrBuf; // write byte + while (CW_FLASH->ISR_f.BUSY); + + // 校验 + if (*((volatile uint8_t *)(WriteAddr)) != *pWrBuf) + { + return 0x01; + } + WriteAddr++; + WrByteCnt--; + pWrBuf++; + } + + CW_FLASH->CR1 = 0x5A5A0000 | CR1BAK; + + return 0x00; +} + +/******************************************************************************* + * @brief 安全运行库使能 + * @param Passwords: 密码 + * @param StartPage: 保护区起始页 + * @param EndPage: 保护区结束页 + * @retval 0x00 : 代表成功 + * 0x01 : 代表失败 + * @note + */ +uint8_t FLASH_SafetyLibraryEnable(uint8_t *Passwords, uint8_t StartPage, uint8_t EndPage) +{ + uint8_t FlashSDK_Table[16]; + uint8_t i; + uint8_t *_passwords = Passwords; + volatile uint8_t *ptr = (volatile uint8_t *)(0xfff0); + + CW_SYSCTRL->AHBEN |= 0x5A5A0000 | SYSCTRL_AHBEN_FLASH_Msk; + + if (CW_FLASH->SDKCFR != 0x0000007F) + { + // 已设置安全运行区 + return 0x01; + } + + CW_SYSCTRL->AHBEN |= 0x5A5A0000 | SYSCTRL_AHBEN_CRC_Msk; + CW_CRC->CR = 0x06; // CRC16_X25 + for (i = 0; i<8; i++) + { + CW_CRC->DR = *_passwords; + FlashSDK_Table[i] = *_passwords; + _passwords++; + } + + CW_CRC->DR = StartPage; + FlashSDK_Table[i++] = StartPage; + CW_CRC->DR = EndPage; + FlashSDK_Table[i++] = EndPage; + + CW_CRC->DR =0x5A; + FlashSDK_Table[i++] = 0x5A; + CW_CRC->DR =0x5A; + FlashSDK_Table[i++] = 0x5A; + CW_CRC->DR =0xA5; + FlashSDK_Table[i++] = 0xA5; + CW_CRC->DR =0xA5; + FlashSDK_Table[i++] = 0xA5; + + FlashSDK_Table[i++] = (uint8_t)CW_CRC->RESULT; + FlashSDK_Table[i] = (uint8_t)(CW_CRC->RESULT >> 8); + + CW_FLASH->PAGELOCK = 0x5A5A8000; // 解锁 + CW_FLASH->CR1 = 0x5a5a0001; // 写入 + + for (i = 0; i<16; i++) + { + *ptr = FlashSDK_Table[i]; + while(CW_FLASH->ISR_f.BUSY); + ptr++; + } + CW_FLASH->CR1 = 0x5a5a0000; + + return 0x00; +} diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_gpio.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_gpio.c new file mode 100644 index 0000000..c4916dc --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_gpio.c @@ -0,0 +1,282 @@ +/** + * @file cw32l012_gpio.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2022 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" + +//============================================================================= +//GPIO 初始化，多个引脚 +/** + * @brief GPIO 初始化，可同时设置多个引脚或单个引脚 + * + * @param GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB + * @param GPIO_Init 参见GPIO_InitTypeDef的定义 + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + switch ((uint32_t)GPIOx) + { + case (uint32_t)CW_GPIOA: + CW_SYSCTRL->AHBEN |= SYSCTRL_KEY | SYSCTRL_AHBEN_GPIOA_Msk; + break; + + case (uint32_t)CW_GPIOB: + CW_SYSCTRL->AHBEN |= SYSCTRL_KEY | SYSCTRL_AHBEN_GPIOB_Msk; + break; + case (uint32_t)CW_GPIOC: + CW_SYSCTRL->AHBEN |= SYSCTRL_KEY | SYSCTRL_AHBEN_GPIOC_Msk; + break; + case (uint32_t)CW_GPIOF: + CW_SYSCTRL->AHBEN |= SYSCTRL_KEY | SYSCTRL_AHBEN_GPIOF_Msk; + break; + default: + break; + } + + if (GPIO_Init->Mode == GPIO_MODE_ANALOG) //模拟功能 + { + REGBITS_SET(GPIOx->ANALOG, GPIO_Init->Pins); + } + else + { + REGBITS_CLR(GPIOx->ANALOG, GPIO_Init->Pins); //数字功能 + + if ((GPIO_Init->Mode & GPIO_MODE_INPUT) == GPIO_MODE_INPUT) //输入模式 + { + REGBITS_SET(GPIOx->DIR, GPIO_Init->Pins); + + REGBITS_CLR(GPIOx->PUR, GPIO_Init->Pins); + + if (GPIO_Init->Mode == GPIO_MODE_INPUT_PULLUP) + { + REGBITS_SET(GPIOx->PUR, GPIO_Init->Pins); + } + + REGBITS_CLR(GPIOx->RISEIE, GPIO_Init->Pins); + REGBITS_CLR(GPIOx->FALLIE, GPIO_Init->Pins); + + if ((GPIO_Init->IT & GPIO_IT_RISING) == GPIO_IT_RISING) + { + REGBITS_SET(GPIOx->RISEIE, GPIO_Init->Pins); + } + + if ((GPIO_Init->IT & GPIO_IT_FALLING) == GPIO_IT_FALLING) + { + REGBITS_SET(GPIOx->FALLIE, GPIO_Init->Pins); + } + } + else //输出模式 + { + REGBITS_CLR(GPIOx->DIR, GPIO_Init->Pins); + + if (GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) + { + REGBITS_CLR(GPIOx->OPENDRAIN, GPIO_Init->Pins); + } + else + { + REGBITS_SET(GPIOx->OPENDRAIN, GPIO_Init->Pins); + } + } + } +} + +//============================================================================= +//GPIO 反初始化， 多个引脚 +/** + * @brief GPIO 去初始化，可同时设置多个引脚或单个引脚 + * + * @param GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOC + * + * @param GPIO_Pins 参数取值如下 + * @arg GPIO_PIN_0/1/2.../15/ALL 可通过与运算同时操作多个引脚 + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pins) +{ + REGBITS_SET(GPIOx->ANALOG, GPIO_Pins); + REGBITS_SET(GPIOx->DIR, GPIO_Pins); + REGBITS_CLR(GPIOx->PUR, GPIO_Pins); +// REGBITS_CLR(GPIOx->PDR, GPIO_Pins); + REGBITS_CLR(GPIOx->RISEIE, GPIO_Pins); + REGBITS_CLR(GPIOx->FALLIE, GPIO_Pins); + REGBITS_CLR(GPIOx->OPENDRAIN, GPIO_Pins); +} +//============================================================================= +//获取指定引脚电平，一个引脚 +//注意：建议采用宏函数来获取引脚电平，例PA00_GETVALUE() +/** + * @brief 获取一个引脚的电平 + * + * @param GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOC + * @param GPIO_Pin 参数取值如下 + * @arg GPIO_PIN_0/1/2.../15 + * @return GPIO_PinState 取值如下: + * @arg GPIO_Pin_SET + * @arg GPIO_Pin_RESET + */ +GPIO_PinState GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + if (GPIOx->IDR & GPIO_Pin) + { + return (GPIO_Pin_SET); + } + + return (GPIO_Pin_RESET); +} + +//============================================================================= +//设置指定引脚电平，多个引脚 +//注意：如只操作一只引脚，建议采用宏函数，例PA00_SETHIGH(), PA00_SETLOW() +/** + * @brief 设置指定引脚电平，可同时设置多个引脚 + * + * @param GPIOx GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOC + * @param GPIO_Pins 参数取值如下 + * @arg GPIO_PIN_0/1/2.../15/ALL; + * @param PinState 取值如下: + * @arg GPIO_Pin_SET + * @arg GPIO_Pin_RESET + */ +void GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pins, GPIO_PinState PinState) +{ + if (PinState == GPIO_Pin_SET) + { + GPIOx->BSRR = GPIO_Pins; + } + else + { + GPIOx->BRR = GPIO_Pins; + } +} + +/** + * @brief 设置指定引脚端口的输出值 + * + * @param GPIOx GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOC + * @param Value + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t Value) +{ + GPIOx->ODR = Value; + +} + + +//============================================================================= +//翻转指定引脚电平，多个引脚 +//注意：如只操作一只引脚，建议采用宏函数，例PA00_TOG() +/** + * @brief 翻转指定引脚电平，可同时设置多个引脚 + * + * @param GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOC + * @param GPIO_Pins + */ +void GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pins) +{ + GPIOx->TOG = GPIO_Pins; +} + + +//============================================================================= +//将PA13/PA14设置成GPIO +/** + * @brief 将PA13/PA14设置成GPIO + * + */ +void GPIO_SWD2GPIO(void) +{ + CW_SYSCTRL->CR2 = CW_SYSCTRL->CR2 | (0x5A5A0000 | bv1); +} + +//============================================================================= +//将PA13/PA14设置成SWD +/** + * @brief 将PA13/PA14设置成SWD，PA13/SWDIO PA14/SWCLK + * + */ +void GPIO_GPIO2SWD(void) +{ + CW_SYSCTRL->CR2 = 0x5A5A0000 | (CW_SYSCTRL->CR2 & (~(bv1))); +} + +//============================================================================= +//配置端口滤波 +// FltClk 只能是宏定义中定义的参数 +/** + * @brief 配置端口滤波 + * + * @param GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOC CW_GPIOF + * @param GPIO_Pins + * @param FltClk 只能是宏定义中定义的参数 GPIO_FLTCLK_xxx + */ +void GPIO_ConfigFilter(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pins, uint32_t FltClk) +{ + GPIOx->FILTER = FltClk | GPIO_Pins; +} + +//============================================================================= +//配置端口辅助功能 +/** + * @brief 配置端口辅助功能 + * + * @param GPIOx 参数为下列参数之一： + * @arg CW_GPIOA CW_GPIOB CW_GPIOC CW_GPIOF + * @param GPIO_Pins GPIO_PIN_x + * @param GPIO_AFx 0~9 + */ +void GPIO_SetAlternateFunction(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint16_t GPIO_AFx) +{ + uint8_t i; + + for (i = 0; i < 16; i++) + { + if (GPIO_Pin == (1U << i)) + { + break; + } + } + + if (i >= 16) + return; + if (i < 8) + { + GPIOx->AFRL = (GPIOx->AFRL & (~(0xf << (i * 4)))) | (GPIO_AFx << (i *4)); + } + else + { + GPIOx->AFRH = (GPIOx->AFRH & (~(0xf << ((i-8) * 4)))) | (GPIO_AFx << ((i - 8) *4)); + } +} + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_gtim.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_gtim.c new file mode 100644 index 0000000..52d58be --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_gtim.c @@ -0,0 +1,694 @@ +/** + * @file cw32l012_gtim.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_gtim.h" +#include "cw32l012_sysctrl.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief + * @param GTIMx + */ +void GTIM1_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.GTIM1 = 0; + CW_SYSCTRL->APBRST1_f.GTIM1 = 1; +} + +/** + * @brief + * @param GTIMx + */ +void GTIM2_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.GTIM2 = 0; + CW_SYSCTRL->APBRST1_f.GTIM2 = 1; +} + +/** + * @brief + * @param GTIMx + */ +void GTIM3_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.GTIM3 = 0; + CW_SYSCTRL->APBRST1_f.GTIM3 = 1; +} + +/** + * @brief + * @param GTIMx + */ +void GTIM4_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.GTIM4 = 0; + CW_SYSCTRL->APBRST1_f.GTIM4 = 1; +} + +/** + * @brief GTIM的基础参数初始化 + * @param GTIMx 取值范围：CW_GTIM1 + * @param GTIM_InitStruct 详见GTIM_InitTypeDef的定义 + */ +void GTIM_TimeBaseInit(GTIM_TypeDef *GTIMx, GTIM_InitTypeDef *GTIM_InitStruct) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_ARR_BUFF(GTIM_InitStruct->ARRBuffState)); + assert_param(IS_GTIM_ALIGN_MODE(GTIM_InitStruct->AlignMode)); + assert_param(IS_GTIM_DIRECTION(GTIM_InitStruct->Direction)); + assert_param(IS_GTIM_PULSE_MODE(GTIM_InitStruct->PulseMode)); + assert_param(IS_GTIM_EVENT_OPT(GTIM_InitStruct->EventOption)); + assert_param(IS_GTIM_UPDATE_OPT(GTIM_InitStruct->UpdateOption)); + assert_param(IS_GTIM_PRESCALER(GTIM_InitStruct->Prescaler)); + + REGBITS_MODIFY(GTIMx->CR1, GTIMx_CR1_ARPE_Msk | GTIMx_CR1_CMS_Msk |\ + GTIMx_CR1_DIR_Msk | GTIMx_CR1_OPM_Msk | GTIMx_CR1_URS_Msk |\ + GTIMx_CR1_UDIS_Msk, GTIM_InitStruct->ARRBuffState |\ + GTIM_InitStruct->AlignMode | GTIM_InitStruct->Direction |\ + GTIM_InitStruct->PulseMode | GTIM_InitStruct->EventOption |\ + GTIM_InitStruct->UpdateOption); + + GTIMx->PSC = GTIM_InitStruct->Prescaler; + + GTIMx->ARR = GTIM_InitStruct->ReloadValue; + + GTIMx->SMCR_f.SMS = 0; // 默认禁止从模式 +} + +/** + * @brief GTIM的主模式下的TRGO输出配置 + * @param MasterTRGO + * @arg GTIM_MASTER_TRGO_RESET GTIM_MASTER_TRGO_EN GTIM_MASTER_TRGO_UPDATE + * @arg GTIM_MASTER_TRGO_CCH1~4 + * @arg GTIM_MASTER_TRGO_OC1REF~GTIM_MASTER_TRGO_OC4REF + * @arg GTIM_MASTER_TRGO_OC1REFC~GTIM_MASTER_TRGO_OC4REFC + */ + +void GTIM_MasterTRGOCfg(GTIM_TypeDef *GTIMx, uint32_t MasterTRGO) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + GTIMx->CR2_f.MMS = (MasterTRGO & 0x07); + + GTIMx->CR2_f.MMSH = (MasterTRGO & 0x08) >> 3; +} + + +void GTIM_SlaverModeCfg(GTIM_TypeDef *GTIMx, GTIM_SlaverCfgTypeDef *GTIM_SlaverCfgStruct) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_SLAVER_MODE(GTIM_SlaverCfgStruct->SlaverMode)); + assert_param(IS_GTIM_TRIG_INPUT(GTIM_SlaverCfgStruct->TrigInput)); + assert_param(IS_GTIM_PRELOAD_SOURCE(GTIM_SlaverCfgStruct->PreloadSource)); + + GTIMx->SMCR_f.SMSPS = GTIM_SlaverCfgStruct->PreloadSource; + GTIMx->SMCR_f.SMSPE = GTIM_SlaverCfgStruct->PreloadState; + GTIMx->SMCR_f.TSH = (GTIM_SlaverCfgStruct->TrigInput & 0x18) >> 3; + GTIMx->SMCR_f.TS = (GTIM_SlaverCfgStruct->TrigInput & 0x07); + GTIMx->SMCR_f.SMSH = GTIM_SlaverCfgStruct->SlaverMode >> 3; + GTIMx->SMCR_f.SMS = GTIM_SlaverCfgStruct->SlaverMode & 0x07; +} + +void GTIM_OC1ModeCfg(GTIM_TypeDef *GTIMx, GTIM_OCModeCfgTypeDef *GTIM_OCModeCfgStruct) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_OC_MODE(GTIM_OCModeCfgStruct->OCMode)); + assert_param(IS_GTIM_OC_POLAR(GTIM_OCModeCfgStruct->OCPolarity)); + assert_param(IS_FUNCTIONAL_STATE(GTIM_OCModeCfgStruct->FastMode)); + assert_param(IS_FUNCTIONAL_STATE(GTIM_OCModeCfgStruct->PreloadState)); + + GTIMx->CCER_f.CC1P = GTIM_OCModeCfgStruct->OCPolarity; + GTIMx->CCER_f.CC1NP = 0; + + GTIMx->CCMR1CMP_f.CC1S = 0; + GTIMx->CCMR1CMP_f.OC1FE = GTIM_OCModeCfgStruct->FastMode; + GTIMx->CCMR1CMP_f.OC1PE = GTIM_OCModeCfgStruct->PreloadState; + GTIMx->CCMR1CMP_f.OC1M = GTIM_OCModeCfgStruct->OCMode & 0x07; + GTIMx->CCMR1CMP_f.OC1MH = GTIM_OCModeCfgStruct->OCMode >> 3 ; +} + +void GTIM_OC2ModeCfg(GTIM_TypeDef *GTIMx, GTIM_OCModeCfgTypeDef *GTIM_OCModeCfgStruct) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_OC_MODE(GTIM_OCModeCfgStruct->OCMode)); + assert_param(IS_GTIM_OC_POLAR(GTIM_OCModeCfgStruct->OCPolarity)); + assert_param(IS_FUNCTIONAL_STATE(GTIM_OCModeCfgStruct->FastMode)); + assert_param(IS_FUNCTIONAL_STATE(GTIM_OCModeCfgStruct->PreloadState)); + + GTIMx->CCER_f.CC2P = GTIM_OCModeCfgStruct->OCPolarity; + GTIMx->CCER_f.CC2NP = 0; + + GTIMx->CCMR1CMP_f.CC2S = 0; + GTIMx->CCMR1CMP_f.OC2FE = GTIM_OCModeCfgStruct->FastMode; + GTIMx->CCMR1CMP_f.OC2PE = GTIM_OCModeCfgStruct->PreloadState; + GTIMx->CCMR1CMP_f.OC2M = GTIM_OCModeCfgStruct->OCMode & 0x07; + GTIMx->CCMR1CMP_f.OC2MH = GTIM_OCModeCfgStruct->OCMode >> 3 ; +} +void GTIM_OC3ModeCfg(GTIM_TypeDef *GTIMx, GTIM_OCModeCfgTypeDef *GTIM_OCModeCfgStruct) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_OC_MODE(GTIM_OCModeCfgStruct->OCMode)); + assert_param(IS_GTIM_OC_POLAR(GTIM_OCModeCfgStruct->OCPolarity)); + assert_param(IS_FUNCTIONAL_STATE(GTIM_OCModeCfgStruct->FastMode)); + assert_param(IS_FUNCTIONAL_STATE(GTIM_OCModeCfgStruct->PreloadState)); + + GTIMx->CCER_f.CC3P = GTIM_OCModeCfgStruct->OCPolarity; + GTIMx->CCER_f.CC3NP = 0; + + GTIMx->CCMR2CMP_f.CC3S = 0; + GTIMx->CCMR2CMP_f.OC3FE = GTIM_OCModeCfgStruct->FastMode; + GTIMx->CCMR2CMP_f.OC3PE = GTIM_OCModeCfgStruct->PreloadState; + GTIMx->CCMR2CMP_f.OC3M = GTIM_OCModeCfgStruct->OCMode & 0x07; + GTIMx->CCMR2CMP_f.OC3MH = GTIM_OCModeCfgStruct->OCMode >> 3 ; +} +void GTIM_OC4ModeCfg(GTIM_TypeDef *GTIMx, GTIM_OCModeCfgTypeDef *GTIM_OCModeCfgStruct) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_OC_MODE(GTIM_OCModeCfgStruct->OCMode)); + assert_param(IS_GTIM_OC_POLAR(GTIM_OCModeCfgStruct->OCPolarity)); + assert_param(IS_FUNCTIONAL_STATE(GTIM_OCModeCfgStruct->FastMode)); + assert_param(IS_FUNCTIONAL_STATE(GTIM_OCModeCfgStruct->PreloadState)); + + GTIMx->CCER_f.CC4P = GTIM_OCModeCfgStruct->OCPolarity; + GTIMx->CCER_f.CC4NP = 0; + + GTIMx->CCMR2CMP_f.CC4S = 0; + GTIMx->CCMR2CMP_f.OC4FE = GTIM_OCModeCfgStruct->FastMode; + GTIMx->CCMR2CMP_f.OC4PE = GTIM_OCModeCfgStruct->PreloadState; + GTIMx->CCMR2CMP_f.OC4M = GTIM_OCModeCfgStruct->OCMode & 0x07; + GTIMx->CCMR2CMP_f.OC4MH = GTIM_OCModeCfgStruct->OCMode >> 3 ; +} + +void GTIM_OC1Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + GTIMx->CCER_f.CC1E = NewState; +} + +void GTIM_OC2Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + GTIMx->CCER_f.CC2E = NewState; +} +void GTIM_OC3Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + GTIMx->CCER_f.CC3E = NewState; +} +void GTIM_OC4Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + GTIMx->CCER_f.CC4E = NewState; +} + + +void GTIM_IC1ModeCfg(GTIM_TypeDef* GTIMx, GTIM_ICModeCfgTypeDef *GTIM_ICInitStruct) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_IC_MAP(GTIM_ICInitStruct->ICMap)); + assert_param(IS_GTIM_IC_PRESCALER(GTIM_ICInitStruct->ICPrescaler)); + assert_param(IS_GTIM_IC_FILTER(GTIM_ICInitStruct->ICFilter)); + assert_param(IS_GTIM_ICPolarity(GTIM_ICInitStruct->ICPolarity)); + + GTIMx->CCMR1CAP_f.CC1S = GTIM_ICInitStruct->ICMap; + GTIMx->CCMR1CAP_f.IC1PSC = GTIM_ICInitStruct->ICPrescaler; + GTIMx->CCMR1CAP_f.IC1F = GTIM_ICInitStruct->ICFilter; + + switch(GTIM_ICInitStruct->ICPolarity) + { + default: + case 1: + GTIMx->CCER_f.CC1P = 0; + GTIMx->CCER_f.CC1NP = 0; + break; + case 2: + GTIMx->CCER_f.CC1P = 1; + GTIMx->CCER_f.CC1NP = 0; + break; + case 3: + GTIMx->CCER_f.CC1P = 1; + GTIMx->CCER_f.CC1NP = 1; + break; + } +} + + +void GTIM_IC2ModeCfg(GTIM_TypeDef* GTIMx, GTIM_ICModeCfgTypeDef *GTIM_ICInitStruct) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_IC_MAP(GTIM_ICInitStruct->ICMap)); + assert_param(IS_GTIM_IC_PRESCALER(GTIM_ICInitStruct->ICPrescaler)); + assert_param(IS_GTIM_IC_FILTER(GTIM_ICInitStruct->ICFilter)); + assert_param(IS_GTIM_ICPolarity(GTIM_ICInitStruct->ICPolarity)); + + GTIMx->CCMR1CAP_f.CC2S = GTIM_ICInitStruct->ICMap; + GTIMx->CCMR1CAP_f.IC2PSC = GTIM_ICInitStruct->ICPrescaler; + GTIMx->CCMR1CAP_f.IC2F = GTIM_ICInitStruct->ICFilter; + + switch(GTIM_ICInitStruct->ICPolarity) + { + default: + case 1: + GTIMx->CCER_f.CC2P = 0; + GTIMx->CCER_f.CC2NP = 0; + break; + case 2: + GTIMx->CCER_f.CC2P = 1; + GTIMx->CCER_f.CC2NP = 0; + break; + case 3: + GTIMx->CCER_f.CC2P = 1; + GTIMx->CCER_f.CC2NP = 1; + break; + } +} + + +void GTIM_IC3ModeCfg(GTIM_TypeDef* GTIMx, GTIM_ICModeCfgTypeDef *GTIM_ICInitStruct) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_IC_MAP(GTIM_ICInitStruct->ICMap)); + assert_param(IS_GTIM_IC_PRESCALER(GTIM_ICInitStruct->ICPrescaler)); + assert_param(IS_GTIM_IC_FILTER(GTIM_ICInitStruct->ICFilter)); + assert_param(IS_GTIM_ICPolarity(GTIM_ICInitStruct->ICPolarity)); + + GTIMx->CCMR2CAP_f.CC3S = GTIM_ICInitStruct->ICMap; + GTIMx->CCMR2CAP_f.IC3PSC = GTIM_ICInitStruct->ICPrescaler; + GTIMx->CCMR2CAP_f.IC3F = GTIM_ICInitStruct->ICFilter; + + switch(GTIM_ICInitStruct->ICPolarity) + { + default: + case 1: + GTIMx->CCER_f.CC3P = 0; + GTIMx->CCER_f.CC3NP = 0; + break; + case 2: + GTIMx->CCER_f.CC3P = 1; + GTIMx->CCER_f.CC3NP = 0; + break; + case 3: + GTIMx->CCER_f.CC3P = 1; + GTIMx->CCER_f.CC3NP = 1; + break; + } +} + + +void GTIM_IC4ModeCfg(GTIM_TypeDef* GTIMx, GTIM_ICModeCfgTypeDef *GTIM_ICInitStruct) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_IC_MAP(GTIM_ICInitStruct->ICMap)); + assert_param(IS_GTIM_IC_PRESCALER(GTIM_ICInitStruct->ICPrescaler)); + assert_param(IS_GTIM_IC_FILTER(GTIM_ICInitStruct->ICFilter)); + assert_param(IS_GTIM_ICPolarity(GTIM_ICInitStruct->ICPolarity)); + + GTIMx->CCMR2CAP_f.CC4S = GTIM_ICInitStruct->ICMap; + GTIMx->CCMR2CAP_f.IC4PSC = GTIM_ICInitStruct->ICPrescaler; + GTIMx->CCMR2CAP_f.IC4F = GTIM_ICInitStruct->ICFilter; + + switch(GTIM_ICInitStruct->ICPolarity) + { + default: + case 1: + GTIMx->CCER_f.CC4P = 0; + GTIMx->CCER_f.CC4NP = 0; + break; + case 2: + GTIMx->CCER_f.CC4P = 1; + GTIMx->CCER_f.CC4NP = 0; + break; + case 3: + GTIMx->CCER_f.CC4P = 1; + GTIMx->CCER_f.CC4NP = 1; + break; + } +} + +void GTIM_IC1Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + GTIMx->CCER_f.CC1E = NewState; +} + +void GTIM_IC2Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + GTIMx->CCER_f.CC2E = NewState; +} +void GTIM_IC3Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + GTIMx->CCER_f.CC3E = NewState; +} +void GTIM_IC4Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + GTIMx->CCER_f.CC4E = NewState; +} + + + + +#if 0 + +/** + * @brief 编码模式初始化。 + * @param GTIMx 取值范围：CW_GTIM1,CW_GTIM2, + * @param GTIM_EncodeInitStruct + */ +void GTIM_EncodeInit(GTIM_TypeDef *GTIMx, GTIM_EncodeInitTypeDef *GTIM_EncodeInitStruct) +{ + uint32_t tmp; + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_ENCODE_MODE(GTIM_EncodeInitStruct->EncodeMode)); + assert_param(IS_GTIM_ENCODE_RESET(GTIM_EncodeInitStruct->EncodeResetMode)); + assert_param(IS_GTIM_ENCODE_RELOAD(GTIM_EncodeInitStruct->EncodeReloadMode)); + assert_param(IS_GTIM_CHx_FILTER(GTIM_EncodeInitStruct->CH1Filter)); + assert_param(IS_GTIM_CHx_FILTER(GTIM_EncodeInitStruct->CH2Filter)); + assert_param(IS_GTIM_CHx_FILTER(GTIM_EncodeInitStruct->CH3Filter)); + assert_param(IS_GTIM_CHx_INVERT(GTIM_EncodeInitStruct->CH1Invert)); + assert_param(IS_GTIM_CHx_INVERT(GTIM_EncodeInitStruct->CH2Invert)); + assert_param(IS_GTIM_CHx_INVERT(GTIM_EncodeInitStruct->CH3Invert)); + + REGBITS_MODIFY(GTIMx->CR0, + GTIMx_CR0_ENCRELOAD_Msk | GTIMx_CR0_ENCRESET_Msk | GTIMx_CR0_ENCMODE_Msk, + GTIM_EncodeInitStruct->EncodeMode | GTIM_EncodeInitStruct->EncodeResetMode | + GTIM_EncodeInitStruct->EncodeReloadMode); + + tmp = GTIM_EncodeInitStruct->CH1Filter | GTIM_EncodeInitStruct->CH1Invert | + (GTIM_EncodeInitStruct->CH2Filter << 4) | (GTIM_EncodeInitStruct->CH2Invert << 7) | + (GTIM_EncodeInitStruct->CH3Filter << 8) | (GTIM_EncodeInitStruct->CH3Invert << 11); + REGBITS_MODIFY(GTIMx->CR1, ~(GTIMx_CR1_CH4FLT_Msk | GTIMx_CR1_CH4POL_Msk), tmp); +} + +/** + * @brief 比较输出功能初始化 + * @param GTIMx 取值范围：CW_GTIM1,CW_GTIM2 + * @param CHx 输出通道：CH1~CH4 + * @param OCMode + */ +void GTIM_OCInit(GTIM_TypeDef *GTIMx, uint32_t CHx, uint32_t OCMode) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_CHANNEL(CHx)); + assert_param(IS_GTIM_OC_OUTPUT(OCMode)); + + REGBITS_MODIFY(GTIMx->CMMR, (GTIMx_CMMR_CC1M_Msk << CHx), (OCMode << CHx)); +} + +void GTIM_ICInit(GTIM_TypeDef *GTIMx, GTIM_ICInitTypeDef *GTIM_ICInitStruct) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_CHANNEL(GTIM_ICInitStruct->CHx)); + assert_param(IS_GTIM_ICPolarity(GTIM_ICInitStruct->ICPolarity)); + assert_param(IS_GTIM_CHx_FILTER(GTIM_ICInitStruct->ICFilter)); + assert_param(IS_GTIM_CHx_INVERT(GTIM_ICInitStruct->ICInvert)); + + REGBITS_MODIFY(GTIMx->CMMR, (GTIMx_CMMR_CC1M_Msk << GTIM_ICInitStruct->CHx), + (GTIM_ICInitStruct->ICPolarity << GTIM_ICInitStruct->CHx)); + + REGBITS_MODIFY(GTIMx->CR1, (0xFUL << GTIM_ICInitStruct->CHx), + (GTIM_ICInitStruct->ICFilter | (GTIM_ICInitStruct->ICInvert << 3)) << GTIM_ICInitStruct->CHx); +} + + +/** + * @brief 配置ETR信号的极性和滤波器 + * @param GTIMx + * @param ETRPolarity 极性 + * @param ETRFilter 滤波参数 + */ +void GTIM_ETRConfig(GTIM_TypeDef *GTIMx, uint32_t ETRPolarity, uint32_t ETRFilter) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_ETR_POL(ETRPolarity)); + assert_param(IS_GTIM_ETR_FILTER(ETRFilter)); + + REGBITS_MODIFY(GTIMx->CR0, GTIMx_CR0_TRS_Msk | GTIMx_CR0_POL_Msk, ETRPolarity); + + REGBITS_MODIFY(GTIMx->ETR, GTIMx_ETR_ETRFLT_Msk, ETRFilter); +} + + + +/** + * @brief 配置输入通道的参数 + * @param GTIMx + * @param CHx + * @param CHxFilter + * @param CHxInvert + */ +void GTIM_ICChannelConfig(GTIM_TypeDef *GTIMx, uint32_t CHx, uint32_t CHxFilter, uint32_t CHxInvert) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_CHANNEL(CHx)); + assert_param(IS_GTIM_CHx_FILTER(CHxFilter)); + assert_param(IS_GTIM_CHx_INVERT(CHxInvert)); + + REGBITS_MODIFY(GTIMx->CR1, (0xFUL << CHx), (CHxFilter | (CHxInvert << 3)) << CHx); +} + +#endif +/** + * @brief GTIM使能 + * @param GTIMx + */ +void GTIM_Cmd(GTIM_TypeDef *GTIMx, FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + GTIMx->CR1_f.CEN = NewState; +} + +/** + * @brief GTIM 重映射更新中断标志位到CNT + * @param NewState + * @arg Enable or Disable + */ + +void GTIM_RemapUpdateFlag(GTIM_TypeDef *GTIMx,FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + GTIMx->CR1_f.UIFREMAP = NewState; +} + + +/** + * @brief 设置预分频系数 + * @param GTIMx + * @param GTIMPrescaler + */ +void GTIM_SetPrescaler(GTIM_TypeDef *GTIMx, uint16_t GTIMPrescaler) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_PRESCALER(GTIMPrescaler)); + + GTIMx->PSC = GTIMPrescaler; +} + +/** + * @brief 设置重载值 + * @param GTIMx + * @param ReloadValue 取值范围：0x0000~0xFFFF + */ +void GTIM_SetReloadValue(GTIM_TypeDef *GTIMx, uint16_t ReloadValue) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + GTIMx->ARR = ReloadValue; +} + +/** + * @brief + * @param GTIMx + * @param Value + */ +void GTIM_SetCounterValue(GTIM_TypeDef *GTIMx, uint16_t Value) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + GTIMx->CNT = Value; +} + +void GTIM_SetCompare1(GTIM_TypeDef *GTIMx, uint16_t Value) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + GTIMx->CCR1 = Value; +} + +void GTIM_SetCompare2(GTIM_TypeDef *GTIMx, uint16_t Value) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + GTIMx->CCR2 = Value; +} + +void GTIM_SetCompare3(GTIM_TypeDef *GTIMx, uint16_t Value) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + GTIMx->CCR3 = Value; +} + +void GTIM_SetCompare4(GTIM_TypeDef *GTIMx, uint16_t Value) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + GTIMx->CCR4 = Value; +} + +/** + * @brief + * @param GTIMx + * @return uint16_t + */ +uint16_t GTIM_GetCapture1(GTIM_TypeDef *GTIMx) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + return (uint16_t)GTIMx->CCR1; +} + +/** + * @brief + * @param GTIMx + * @return uint16_t + */ +uint16_t GTIM_GetCapture2(GTIM_TypeDef *GTIMx) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + return (uint16_t)GTIMx->CCR2; +} + +/** + * @brief + * @param GTIMx + * @return uint16_t + */ +uint16_t GTIM_GetCapture3(GTIM_TypeDef *GTIMx) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + return (uint16_t)GTIMx->CCR3; +} + +/** + * @brief + * @param GTIMx + * @return uint16_t + */ +uint16_t GTIM_GetCapture4(GTIM_TypeDef *GTIMx) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + + return (uint16_t)GTIMx->CCR4; +} + +/** + * @brief + * @param GTIMx + * @param GTIM_IT + * @param NewState + */ +void GTIM_ITConfig(GTIM_TypeDef *GTIMx, uint32_t GTIM_IT, FunctionalState NewState) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_IT(GTIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + GTIMx->IER |= GTIM_IT; + } + else + { + GTIMx->IER &= ~GTIM_IT; + } +} + +/** + * @brief + * @param GTIMx + * @param GTIM_IT + * @return ITStatus + */ +ITStatus GTIM_GetITStatus(GTIM_TypeDef *GTIMx, uint32_t GTIM_IT) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_GET_IT(GTIM_IT)); + + return (GTIMx->ISR & GTIM_IT) ? SET : RESET; +} + +/** + * @brief + * @param GTIMx + * @param GTIM_IT + */ +void GTIM_ClearITPendingBit(GTIM_TypeDef *GTIMx, uint32_t GTIM_IT) +{ + assert_param(IS_GTIM_DEFINE(GTIMx)); + assert_param(IS_GTIM_IT(GTIM_IT)); + + GTIMx->ICR = ~GTIM_IT; +} + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_halltim.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_halltim.c new file mode 100644 index 0000000..18b8296 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_halltim.c @@ -0,0 +1,154 @@ +/** + * @file cw32l012_halltim.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_halltim.h" +#include "cw32l012_sysctrl.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/******************************************************************************* +// 说明：初始化 +// 参数： +// 参数： +// 返回值：无 +*******************************************************************************/ +// 初始化EAU +// 初始化HALLTIM模块 +void HALLTIM_Init(HALLTIM_InitTypeDef *init) +{ + __SYSCTRL_HALLTIM_CLK_ENABLE(); + CW_HALLTIM->CR = (init->filter_enable << HALLTIM_CR_FLT1EN_Pos) | + init->clock_division | init->trigger_output | + (init->filter_length << HALLTIM_CR_FLT2LEN_Pos); + + // 配置自动重装载值 + CW_HALLTIM->ARR = init->auto_reload_value; +} + + +// 启用/禁用HALLTIM模块 +void HALLTIM_Cmd(FunctionalState state) +{ + state ? (CW_HALLTIM->CR_f.EN = 1) : (CW_HALLTIM->CR_f.EN = 0); +} + + + +// 设置滤波宽度 +void HALLTIM_SetFilterLength(uint32_t length) +{ + CW_HALLTIM->CR_f.FLT2LEN = length; +} + +// 设置触发输出模式 +void HALLTIM_SetMode(HALLTIM_MMS mode) +{ + CW_HALLTIM->CR = (CW_HALLTIM->CR & ~HALLTIM_CR_MMS_Msk) | mode; +} + +// 设置时钟分频 +void HALLTIM_SetClockDivider(HALLTIM_DIV div) +{ + CW_HALLTIM->CR = (CW_HALLTIM->CR & ~HALLTIM_CR_DIV_Msk) | div; +} + +// 生成软件触发信号 +void HALLTIM_GenerateSoftTrigger(void) +{ + CW_HALLTIM->CR_f.SOFTCAP = 1; +} + +// 设置自动重装载值 +void HALLTIM_SetAutoReloadValue(uint32_t value) +{ + CW_HALLTIM->ARR = value; +} + +// 获取计数值 +uint32_t HALLTIM_GetCounterValue(void) +{ + return CW_HALLTIM->CNT; +} + +// 获取脉冲宽度 +uint32_t HALLTIM_GetPulseWidth(void) +{ + return CW_HALLTIM->WIDTH; +} + +// 设置比较值 +void HALLTIM_SetCompareValue(uint32_t value) +{ + CW_HALLTIM->CCR = value; +} + +// 获取状态标志 +uint32_t HALLTIM_GetStatus(void) +{ + return CW_HALLTIM->ISR; +} + +// 清除状态标志 +void HALLTIM_ClearStatus(uint32_t flags) +{ + CW_HALLTIM->ICR = ~flags; +} + +// 获取未滤波的HALL信号状态 +uint32_t HALLTIM_GetRawStateCH1(void) { + return CW_HALLTIM->STATE_f.CH1S; +} +uint32_t HALLTIM_GetRawStateCH2(void) { + return CW_HALLTIM->STATE_f.CH2S; +} +uint32_t HALLTIM_GetRawStateCH3(void) { + return CW_HALLTIM->STATE_f.CH3S; +} + +// 获取滤波后的HALL信号状态 +uint32_t HALLTIM_GetFilteredStateCH1(void) { + return CW_HALLTIM->STATE_f.CH1F; +} +uint32_t HALLTIM_GetFilteredStateCH2(void) { + return CW_HALLTIM->STATE_f.CH2F; +} +uint32_t HALLTIM_GetFilteredStateCH3(void) { + return CW_HALLTIM->STATE_f.CH3F; +} + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_irmod.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_irmod.c new file mode 100644 index 0000000..5e66724 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_irmod.c @@ -0,0 +1,85 @@ +/** + * @file cw32l012_irmod.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + ****************************************************************************** + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + ****************************************************************************** + */ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "cw32l012_irmod.h" + + +/******************************************************************************* + * @brief 配置红外调制方式 + * @param ModulateMod : 红外调制方式 + @ref IRMOD_IRSW_AND_GTIM1_CH1 + @ref IRMOD_IRSW_OR_GTIM2_CH1 + @ref IRMOD_GTIM1_CH1_AND_GTIM3_CH1 + @ref IRMOD_GTIM2_CH1_OR_GTIM4_CH1 + @ref IRMOD_UART1_TXD_AND_GTIM1_CH2 + @ref IRMOD_UART1_TXD_OR_GTIM2_CH2 + @ref IRMOD_UART1_TXD_AND_GTIM3_CH2 + @ref IRMOD_UART1_TXD_OR_GTIM4_CH2 + @ref IRMOD_UART2_TXD_AND_GTIM1_CH3 + @ref IRMOD_UART2_TXD_OR_GTIM2_CH3 + @ref IRMOD_UART2_TXD_AND_GTIM3_CH3 + @ref IRMOD_UART2_TXD_OR_GTIM4_CH3 + @ref IRMOD_UART3_TXD_AND_GTIM1_CH4 + @ref IRMOD_UART3_TXD_OR_GTIM2_CH4 + @ref IRMOD_UART3_TXD_AND_GTIM3_CH4 + @ref IRMOD_UART3_TXD_OR_GTIM4_CH4 + * @param Polarity : 红外输出极性 + * @retval None + */ +void IRMOD_Config(IRMOD_ModulateModTypeDef ModulateMod, IRMOD_PolarityTypeDef Polarity) +{ + CW_IRMOD->CR = ModulateMod; + REGBITS_MODIFY(CW_IRMOD->CR, + IRMOD_CR_INV_Msk | IRMOD_CR_MOD_Msk, + (uint32_t)ModulateMod | (uint32_t)Polarity); +} + + +/******************************************************************************* + * @brief 设置红外调制软件控制为高 + * @param None + * @retval None + */ +void IRMOD_IRSW_SetHigh(void) +{ + IRMOD_IRSW_SETHIGH(); +} + + +/******************************************************************************* + * @brief 设置红外调制软件控制为低 + * @param None + * @retval None + */ +void IRMOD_IRSW_SetLow(void) +{ + IRMOD_IRSW_SETLOW(); +} + + +/*********************************END OF FILE**********************************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_iwdt.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_iwdt.c new file mode 100644 index 0000000..ab92d52 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_iwdt.c @@ -0,0 +1,252 @@ +/** + * @file cw32l012_iwdt.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_iwdt.h" +#include "cw32l012_sysctrl.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief IWDT去初始化 + */ +void IWDT_DeInit(void) +{ + CW_SYSCTRL->APBRST2_f.IWDT = 0; + CW_SYSCTRL->APBRST2_f.IWDT = 1; +} + +/** + * @brief IWDT初始化 + * @param IWDT_InitStruct 该结构体包含IWDT需要配置的参数 + * @return 0:sucess 1:error + */ +int IWDT_Init(IWDT_InitTypeDef *IWDT_InitStruct) +{ + uint16_t timeout = 0xffff; + assert_param(IS_IWDT_PRESCALER(IWDT_InitStruct->IWDT_Prescaler)); + assert_param(IS_IWDT_ACTION(IWDT_InitStruct->IWDT_OverFlowAction)); + assert_param(IS_IWDT_SLEEP_MODE(IWDT_InitStruct->IWDT_Pause)); + assert_param(IS_IWDT_WINDOW_VALUE(IWDT_InitStruct->IWDT_WindowValue)); + assert_param(IS_IWDT_RELOAD(IWDT_InitStruct->IWDT_ReloadValue)); + + CW_SYSCTRL->APBEN2_f.IWDT = 1; + __IWDT_RUN(); // 需要先启动IWDT后，才能修改其他寄存器 + __IWDT_UNLOCK(); // 解锁寄存器保护 + if (IWDT_InitStruct->IWDT_ITState == ENABLE) + { + CW_IWDT->CR = IWDT_InitStruct->IWDT_Prescaler | \ + IWDT_InitStruct->IWDT_OverFlowAction | \ + IWDT_CR_IE_Msk | IWDT_InitStruct->IWDT_Pause; + } + else + { + CW_IWDT->CR = (IWDT_InitStruct->IWDT_Prescaler | \ + IWDT_InitStruct->IWDT_OverFlowAction | \ + IWDT_InitStruct->IWDT_Pause); + } + + CW_IWDT->ARR = IWDT_InitStruct->IWDT_ReloadValue; + CW_IWDT->WINR = IWDT_InitStruct->IWDT_WindowValue; + + while ((CW_IWDT->SR & (IWDT_SR_CRF_Msk | IWDT_SR_ARRF_Msk | IWDT_SR_WINRF_Msk)) && timeout--); + if (timeout == 0) return 1; + + __IWDT_LOCK(); + return 0; +} + +/** + * @brief 启动IWDT + */ +void inline IWDT_Cmd(void) +{ + __IWDT_RUN(); +} + +/** + * @brief 喂狗 + */ +void inline IWDT_Refresh(void) +{ + __IWDT_REFRESH(); +} + +/** + * @brief 寄存器保护解锁 + */ +void inline IWDT_Unlock(void) +{ + __IWDT_UNLOCK(); +} + +/** + * @brief 寄存器保护上锁 + */ +void inline IWDT_Lock(void) +{ + __IWDT_LOCK(); +} + +/** + * @brief 停止IWDT + */ +void inline IWDT_Stop(void) +{ + __IWDT_STOP(); +} + +/** + * @brief 设置IWDT的预分频因数 + * @param IWDT_Prescaler 取值范围 IWDT_Prescaler_DIV4~IWDT_Prescaler_DIV512 + */ +int IWDT_SetPrescaler(uint32_t IWDT_Prescaler) +{ + uint16_t timeout = 0xffff; + assert_param(IS_IWDT_PRESCALER(IWDT_Prescaler)); + + __IWDT_UNLOCK(); + while ((CW_IWDT->SR & IWDT_SR_CRF_Msk) && timeout--); + if (timeout == 0) return 1; + CW_IWDT->CR_f.PRS = IWDT_Prescaler; + __IWDT_LOCK(); + return 0; +} + +/** + * @brief 设置IWDT的窗口值 + * @param WindowValue 取值范围0x00000000~0x00000FFF,当值为0x00000FFF时，窗口功能不开启 + */ +int IWDT_SetWindowValue(uint32_t WindowValue) +{ + uint16_t timeout = 0xffff; + assert_param(IS_IWDT_WINDOW_VALUE(WindowValue)); + + __IWDT_UNLOCK(); + while ((CW_IWDT->SR & IWDT_SR_WINRF_Msk) && timeout--); + if (timeout == 0) return 1; + CW_IWDT->WINR = WindowValue; + __IWDT_LOCK(); + return 0; +} + +/** + * @brief 设置IWDT的重载寄存器的值 + * @param ReloadValue 取值范围0x00000000~0x00000FFF + */ +int IWDT_SetReloadValue(uint32_t ReloadValue) +{ + uint16_t timeout = 0xffff; + assert_param(IS_IWDT_RELOAD(ReloadValue)); + + __IWDT_UNLOCK(); + while ((CW_IWDT->SR & IWDT_SR_ARRF_Msk) && timeout--); + if (timeout == 0) return 1; + CW_IWDT->ARR = ReloadValue; + __IWDT_LOCK(); + return 0; +} + +/** + * @brief 设置IWDT的中断使能与禁能 + * @param NewState IWDT中断使能位状态 范围：ENABLE或DISABLE + */ +int IWDT_ITConfig(FunctionalState NewState) +{ + uint16_t timeout = 0xffff; + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + __IWDT_UNLOCK(); + while ((CW_IWDT->SR & IWDT_SR_CRF_Msk) && timeout--); + if (timeout == 0) return 1; + NewState ? (CW_IWDT->CR_f.IE = ENABLE) : (CW_IWDT->CR_f.IE = DISABLE); + __IWDT_LOCK(); + return 0; +} + +/** + * @brief 获取IWDT的状态 + * @param StatusBit 状态位的位置,取值范围为：IWDT_SR_CRF_Msk + * IWDT_SR_ARRF_Msk + * IWDT_SR_WINRF_Msk + * IWDT_SR_OV_Msk + * IWDT_SR_RUN_Msk + * IWDT_SR_RELOAD_Msk + * + * @return FlagStatus + */ +FlagStatus IWDT_GetFlagStatus(uint32_t StatusBit) +{ + return (FlagStatus)(CW_IWDT->SR & StatusBit); +} + +/** + * @brief 清除IWDT的溢出标志OV + */ +void inline IWDT_ClearOVFlag(void) +{ + CW_IWDT->SR_f.OV = 0; +} + +/** + * @brief + * @return uint32_t 返回IWDT的计数值 + */ +uint32_t IWDT_GetCounterValue(void) +{ + uint32_t tmp1, tmp2; + do + { + tmp1 = CW_IWDT->CNT; + tmp2 = CW_IWDT->CNT; + } + while(tmp1 != tmp2); + + return tmp1; +} + +/** + * @brief Set IWDT counting period. + * @param counting period: + WDT_5_SECS + WDT_4_SECS + WDT_2_SECS + WDT_1_SECS + WDT_0_5_SECS + WDT_0_25_SECS + * @retval None + */ +void IWDT_SetPeriod(uint32_t period) +{ + IWDT_InitTypeDef IWDT_InitStruct ={0}; + + assert_param(IS_IWDT_PERIOD(period)); + + IWDT_InitStruct.IWDT_ITState = DISABLE; + IWDT_InitStruct.IWDT_OverFlowAction = IWDT_OVERFLOW_ACTION_RESET; + IWDT_InitStruct.IWDT_Pause = IWDT_SLEEP_PAUSE ; + IWDT_InitStruct.IWDT_Prescaler = IWDT_Prescaler_DIV512; // 默认设置为最大分频，计时间隔为51.2ms + IWDT_InitStruct.IWDT_WindowValue = 0xFFF; // 关闭窗口看门狗的功能 + IWDT_InitStruct.IWDT_ReloadValue = period; + + IWDT_Init(&IWDT_InitStruct); + IWDT_Cmd(); + IWDT_Refresh(); +} diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_lpi2c.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_lpi2c.c new file mode 100644 index 0000000..4933ecf --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_lpi2c.c @@ -0,0 +1,3288 @@ +/** + * @file cw32l012_lpi2c.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2022-7-12 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* + * + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + * + *******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_lpi2c.h" +#include "cw32l012_sysctrl.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static status_t LPI2C_MasterWaitForTxReady(I2C_TypeDef *I2Cx); + +static status_t LPI2C_RunTransferStateMachine(I2C_TypeDef *I2Cx, lpi2c_master_handle_t *handle, boolean_t *isDone); + +static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle); + +static status_t LPI2C_SlaveCheckAndClearError(I2C_TypeDef *I2Cx, uint32_t flags); + + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map LPI2C instance number to base pointer. */ +static I2C_TypeDef *const kLpi2cBases[] = LPI2C_BASE_PTRS; + +/*! @brief Array to map LPI2C instance number to IRQ number, used internally for LPI2C master interrupt APIs. */ +IRQn_Type const kLpi2cIrqs[] = LPI2C_IRQS; + +/*! @brief Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt APIs. */ +lpi2c_master_isr_t s_lpi2cMasterIsr; + +/*! @brief Pointers to master handles for each instance, used internally for LPI2C master interrupt APIs. */ +void *s_lpi2cMasterHandle[ARRAY_SZ(kLpi2cBases)]; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static lpi2c_slave_isr_t s_lpi2cSlaveIsr; + +/*! @brief Pointers to slave handles for each instance. */ +static lpi2c_slave_handle_t *s_lpi2cSlaveHandle[ARRAY_SZ(kLpi2cBases)]; + + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief 初始化I2C主设备 + * + * 初始化I2C主设备，包括配置时钟源、调试模式、休眠模式、引脚配置、总线空闲超时、引脚低电平超时等参数。 + * + * @param I2Cx I2C设备指针 + * @param I2C_MasterConfig I2C主设备配置结构体指针 + * @param sourceClock_Hz 主时钟频率（Hz） + * + * @return ErrorStatus 错误状态码 + * - SUCCESS: 初始化成功 + * - ERROR: 初始化失败 + */ +ErrorStatus I2C_MasterInit(I2C_TypeDef *I2Cx, I2C_MasterConfigTypeDef *I2C_MasterConfig, uint32_t sourceClock_Hz) +{ + ErrorStatus RetVal = SUCCESS; + uint32_t prescaler; + uint32_t cycles; + uint32_t cfgr2; + + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + if ((uint32_t)I2Cx == (uint32_t)CW_I2C1) + { + // 打开I2C1模块的时钟 + __SYSCTRL_I2C1_CLK_ENABLE(); + } + else if((uint32_t)I2Cx == (uint32_t)CW_I2C2) + { + // 打开I2C2模块的时钟 + __SYSCTRL_I2C2_CLK_ENABLE(); + } + else + { + return ERROR; + } + + /* 配置前先对I2C Master复位 */ + I2C_MasterSoftReset(I2Cx); + + /* 配置总线输入信号选择寄存器 */ + REGBITS_MODIFY(I2Cx->INSEL, I2Cx_INSEL_SDAINSEL_Msk | I2Cx_INSEL_SCLINSEL_Msk, + ((uint32_t)(I2C_MasterConfig->I2C_SDA_Source)) | ((uint32_t)(I2C_MasterConfig->I2C_SCL_Source))); + + /* 配置时钟源及调试、休眠模式 */ + REGBITS_MODIFY(I2Cx->MCR0, I2Cx_MCR0_CLKSRC_Msk | I2Cx_MCR0_DBGEN_Msk | I2Cx_MCR0_SLEEPEN_Msk, + ((uint32_t)(I2C_MasterConfig->I2C_ClockSouce)) | + (((uint32_t)(I2C_MasterConfig->I2C_InDebugState & 0x01)) << I2Cx_MCR0_DBGEN_Pos) | + (((uint32_t)(I2C_MasterConfig->I2C_InDeepSleepState & 0x01)) << I2Cx_MCR0_SLEEPEN_Pos)); + + /* pin config and ignore ack, MATCFG*/ + REGBITS_MODIFY(I2Cx->MCR2, I2Cx_MCR2_PINCFG_Msk | I2Cx_MCR2_IGNACK_Msk | I2Cx_MCR2_MATCFG_Msk, + (((uint32_t)(I2C_MasterConfig->I2C_PinsConfig & 0x07)) << I2Cx_MCR2_PINCFG_Pos) | + ((uint32_t)(I2C_MasterConfig->ignoreAck) << I2Cx_MCR2_IGNACK_Pos) | + ((I2C_MasterConfig->I2C_DataMatchMode) << I2Cx_MCR2_MATCFG_Pos)); + + /* Configure glitch filters. */ + cfgr2 = I2Cx->MCR3; + + if (0U != (I2C_MasterConfig->sdaGlitchFilterWidth_ns)) + { + /* Calculate SDA filter width. The width is equal to FILTSDA cycles of functional clock. + And set FILTSDA to 0 disables the fileter, so the min value is 1. */ + cycles = I2C_GetCyclesForWidth(sourceClock_Hz, I2C_MasterConfig->sdaGlitchFilterWidth_ns, 1U, + (I2Cx_MCR3_FLTSDA_Msk >> I2Cx_MCR3_FLTSDA_Pos), 0U); + cfgr2 &= ~I2Cx_MCR3_FLTSDA_Msk; + cfgr2 |= I2C_MCR3_FILTSDA(cycles); + } + + if (0U != I2C_MasterConfig->sclGlitchFilterWidth_ns) + { + /* Calculate SDL filter width. The width is equal to FILTSCL cycles of functional clock. + And set FILTSCL to 0 disables the fileter, so the min value is 1. */ + cycles = I2C_GetCyclesForWidth(sourceClock_Hz, I2C_MasterConfig->sclGlitchFilterWidth_ns, 1U, + (I2Cx_MCR3_FLTSCL_Msk >> I2Cx_MCR3_FLTSCL_Pos), 0U); + cfgr2 &= ~I2Cx_MCR3_FLTSCL_Msk; + cfgr2 |= I2C_MCR3_FILTSCL(cycles); + } + + I2Cx->MCR3 = cfgr2; + + /* Configure baudrate after the SDA/SCL glitch filter setting, + since the baudrate calculation needs them as parameter. */ + I2C_MasterSetBaudRate(I2Cx, sourceClock_Hz, I2C_MasterConfig->I2C_BaudRate_Hz); + + /* Configure bus idle and pin low timeouts after baudrate setting, + since the timeout calculation needs prescaler as parameter. */ + prescaler = (I2Cx->MCR2 & I2Cx_MCR2_PRESCALE_Msk) >> I2Cx_MCR2_PRESCALE_Pos; + + if (0U != (I2C_MasterConfig->busIdleTimeout_ns)) + { + /* Calculate bus idle timeout value. The value is equal to BUSIDLE cycles of functional clock divided by + prescaler. And set BUSIDLE to 0 disables the fileter, so the min value is 1. */ + cycles = I2C_GetCyclesForWidth(sourceClock_Hz, I2C_MasterConfig->busIdleTimeout_ns, 1U, + (I2Cx_MCR3_BUSIDLE_Msk >> I2Cx_MCR3_BUSIDLE_Pos), prescaler); + cfgr2 &= ~I2Cx_MCR3_BUSIDLE_Msk; + cfgr2 |= I2C_MCR3_BUSIDLE(cycles); + } + + I2Cx->MCR3 = cfgr2; + + if (0U != I2C_MasterConfig->pinLowTimeout_ns) + { + /* Calculate bus pin low timeout value. The value is equal to PINLOW cycles of functional clock divided by + prescaler. And set PINLOW to 0 disables the fileter, so the min value is 1. */ + cycles = I2C_GetCyclesForWidth(sourceClock_Hz, I2C_MasterConfig->pinLowTimeout_ns / 256U, 1U, + (I2Cx_MCR3_BUSIDLE_Msk >> I2Cx_MCR3_BUSIDLE_Pos), prescaler); + I2Cx->MCR4 = (I2Cx->MCR4 & ~I2Cx_MCR4_PINLOW_Msk) | I2C_MCR4_PINLOW(cycles); + } + + return RetVal; +} + +/** + * @brief 初始化I2C从设备 + * + * 该函数用于初始化I2C从设备，包括设置从设备地址、时钟延展、滤波时钟源等。 + * + * @param I2Cx 指向I2C外设的指针 + * @param I2C_SlaveConfig 指向I2C从设备配置结构体的指针 + * @param sourceClock_Hz I2C外设的时钟源频率，单位为Hz + * + * @return ErrorStatus 返回初始化状态 + * - SUCCESS: 初始化成功 + * - ERROR: 初始化失败 + */ +ErrorStatus I2C_SlaveInit(I2C_TypeDef *I2Cx, I2C_SlaveConfigTypeDef *I2C_SlaveConfig, uint32_t sourceClock_Hz) +{ + ErrorStatus RetVal = SUCCESS; + uint32_t tmpReg; + uint32_t tmpCycle; + + // 检查I2C外设是否有效 + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + // 空指针检查 + if (I2Cx == NULL || I2C_SlaveConfig == NULL) + { + return ERROR; + } + + if ((uint32_t)I2Cx == (uint32_t)CW_I2C1) + { + // 打开I2C1模块的时钟 + __SYSCTRL_I2C1_CLK_ENABLE(); + } + else if ((uint32_t)I2Cx == (uint32_t)CW_I2C2) + { + // 打开I2C2模块的时钟 + __SYSCTRL_I2C2_CLK_ENABLE(); + } + else + { + return ERROR; + } + + /* 配置前先对I2C Slave复位 */ + I2C_SlaveSoftReset(I2Cx); + + /* 配置Slave 从机地址匹配方式 */ + REGBITS_MODIFY(I2Cx->SAMR, I2Cx_SAMR_ADDR1_Msk | I2Cx_SAMR_ADDR0_Msk, + ((((uint32_t)(I2C_SlaveConfig->I2C_Addr1 & MAX_SLAVE_ADDR_10B)) << I2Cx_SAMR_ADDR1_Pos) | + (((uint32_t)(I2C_SlaveConfig->I2C_Addr0 & MAX_SLAVE_ADDR_10B)) << I2Cx_SAMR_ADDR0_Pos))); + + /* 配置Slave SCR1 */ + I2Cx->SCR1 = + I2C_SCR1_ADDRCFG(I2C_SlaveConfig->addressMatchMode) | I2C_SCR1_IGNACK(I2C_SlaveConfig->ignoreAck) | + I2C_SCR1_RXCFG(I2C_SlaveConfig->enableReceivedAddressRead) | I2C_SCR1_GCEN(I2C_SlaveConfig->enableGeneralCall) | + I2C_SCR1_ACKSTALL(I2C_SlaveConfig->sclStall.enableAck) | I2C_SCR1_TXSTALL(I2C_SlaveConfig->sclStall.enableTx) | + I2C_SCR1_RXSTALL(I2C_SlaveConfig->sclStall.enableRx) | + I2C_SCR1_ADRSTALL(I2C_SlaveConfig->sclStall.enableAddress); + + /* Calculate SDA filter width. The width is equal to FILTSDA+3 cycles of functional clock. + And set FILTSDA to 0 disables the fileter, so the min value is 4. */ + tmpReg = I2C_SCR3_FILTSDA( + I2C_GetCyclesForWidth(sourceClock_Hz, I2C_SlaveConfig->sdaGlitchFilterWidth_ns, 4U, + (I2Cx_SCR3_FLTSDA_Msk >> I2Cx_SCR3_FLTSDA_Pos) + 3U, 0U) - 3U); + + /* Calculate SCL filter width. The width is equal to FILTSCL+3 cycles of functional clock. + And set FILTSCL to 0 disables the fileter, so the min value is 4. */ + tmpCycle = I2C_GetCyclesForWidth(sourceClock_Hz, I2C_SlaveConfig->sclGlitchFilterWidth_ns, 4U, + (I2Cx_SCR3_FLTSCL_Msk >> I2Cx_SCR3_FLTSCL_Pos) + 3U, 0U); + tmpReg |= I2C_SCR3_FILTSCL(tmpCycle - 3U); + + /* Calculate data valid time. The time is equal to FILTSCL+DATAVD+3 cycles of functional clock. + So the min value is FILTSCL+3. */ + tmpReg |= I2C_SCR3_DATAVD( + I2C_GetCyclesForWidth(sourceClock_Hz, I2C_SlaveConfig->dataValidDelay_ns, tmpCycle, + tmpCycle + (I2Cx_SCR3_DATAVD_Msk >> I2Cx_SCR3_DATAVD_Pos), 0U) - tmpCycle); + + /* Calculate clock hold time. The time is equal to CLKHOLD+3 cycles of functional clock. + So the min value is 3. */ + I2Cx->SCR3 = + tmpReg | I2C_SCR3_CLKHOLD( + I2C_GetCyclesForWidth(sourceClock_Hz, I2C_SlaveConfig->clockHoldTime_ns, 3U, + (I2Cx_SCR3_CLKHOLD_Msk >> I2Cx_SCR3_CLKHOLD_Pos) + 3U, 0U) - 3U); + + REGBITS_MODIFY( I2Cx->SCR0 , I2Cx_SCR0_FLTEN_Msk, (I2C_SlaveConfig->filterEnable << I2Cx_SCR0_FLTEN_Pos)); + + return RetVal; +} + +/** + * @brief I2C Master模块使能控制 + * + * @param I2Cx + * @param NewState : ENABLE DISABLE + */ +void I2C_MasterCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + if (NewState == ENABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->MCR0_f.MEN = 1; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->MCR0_f.MEN = 0; + } +} + +/** + * @brief I2C Slave模块使能控制 + * + * @param I2Cx + * @param NewState : ENABLE DISABLE + */ +void I2C_SlaveCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + if (NewState == ENABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->SCR0_f.SEN = 1; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->SCR0_f.SEN = 0; + } +} + +/** + * @brief I2C 模块去初始化 + * + * @param I2Cx + */ +void I2C_DeInit(I2C_TypeDef *I2Cx) +{ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + // 复位I2C模块 + if(I2Cx == CW_I2C1) + { + CW_SYSCTRL->APBRST2_f.I2C1 = 0; + CW_SYSCTRL->APBRST2_f.I2C1 = 1; + // 关闭I2C模块的时钟 + __SYSCTRL_I2C1_CLK_DISABLE(); + } + else + { + CW_SYSCTRL->APBRST2_f.I2C2 = 0; + CW_SYSCTRL->APBRST2_f.I2C2 = 1; + // 关闭I2C模块的时钟 + __SYSCTRL_I2C2_CLK_DISABLE(); + } +} + +/** + * @brief 清除I2C主机标志位 + * + * @param I2Cx I2C外设指针 + * @param I2C_FLAG 要清除的标志位，可以是以下值之一及其组合： + * - I2C_IT_MATCH + * - I2C_IT_PINLOW + * - I2C_IT_FIFO + * - I2C_IT_ARBI + * - I2C_IT_NACK + * - I2C_IT_STOP + * - I2C_IT_PACKET + * - I2C_IT_FRAME + * + */ +void I2C_MasterClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + + REGBITS_CLR(I2Cx->MICR, I2C_FLAG); +} + +/** + * @brief I2C主模式轮询标志位函数 + * + * 该函数用于在I2C主模式下，通过轮询方式检查指定的I2C标志位状态。 + * + * @param I2Cx 指向I2C外设的指针 + * @param I2C_FLAG 需要检查的I2C标志位，可以是以下值之一及其组合： + * - I2C_IT_BUSBUSY + * - I2C_IT_MSTBUSY + * - I2C_IT_MATCH + * - I2C_IT_PINLOW + * - I2C_IT_FIFO + * - I2C_IT_ARBI + * - I2C_IT_NACK + * - I2C_IT_STOP + * - I2C_IT_PACKET + * - I2C_IT_FRAME + * - I2C_IT_RXNE + * - I2C_IT_TXE + * @param reverse 标志位检测逻辑，true表示取反检测，false表示直接检测 + * + * @return 如果检测到标志位，返回I2C_Status_Success；否则，返回错误代码 + * + * @note 调用此函数前，需确保传入的I2Cx指针指向有效的I2C外设，I2C_FLAG为有效的I2C标志位。 + * 如果等待超时仍未检测到标志位，返回I2C_Status_Timeout。 + */ +static uint8_t I2C_MasterPollingFlagCommon(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG, boolean_t reverse) +{ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_FLAG(I2C_FLAG)); + + for (uint32_t waitTimes = I2C_WAIT_TIMEOUT; waitTimes > 0; --waitTimes) + { + uint32_t regVal = I2Cx->MISR; + uint32_t flagDetected = reverse ? !(regVal & I2C_FLAG) : (regVal & I2C_FLAG); + + if (flagDetected) + { + return I2C_Status_Success; + } + } + + return I2C_Status_Timeout; +} + +/** + * @brief 查询I2C主机标志位的状态 + * + * @param I2Cx I2C模块指针 + * @param I2C_FLAG 需要查询的标志位 + * + * @return 如果标志位被设置，则返回I2C_Status_Success；否则返回错误代码 + */ +uint8_t I2C_MasterPollingFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + return I2C_MasterPollingFlagCommon(I2Cx, I2C_FLAG, FALSE); +} + +/** + * @brief 反转查询I2C主模式标志位 + * + * @param I2Cx I2C接口指针 + * @param I2C_FLAG 要反转的标志位 + * + * @return 如果标志位未被设置，则返回I2C_Status_Success；否则返回错误代码 + */ +uint8_t I2C_MasterPollingFlagReverse(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + return I2C_MasterPollingFlagCommon(I2Cx, I2C_FLAG, TRUE); +} + +/** + * @brief 获取I2C主模式标志位状态 + * + * @param I2Cx 指向I2C外设的指针 + * @param I2C_FLAG 要检查的I2C标志位 + * + * @return 标志位状态 + * + * @note 调用此函数前，请确保I2Cx和I2C_FLAG参数有效。 + */ +uint32_t I2C_MasterGetFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_FLAG(I2C_FLAG)); + + // 获取并返回指定的标志位状态 + return (I2Cx->MISR & I2C_FLAG); +} + +/** + * @brief 主机发送START信号和从机地址到I2C总线上 + * + * @param I2Cx: I2C + * @param slaveAddr: 7-bit从设备地址 . + * @param dataMode：主机传输的方向，I2C_MODE_WRITE或者I2C_MODE_READ + * @retval + */ +uint8_t I2C_MasterSTART_Addr7b(I2C_TypeDef *I2Cx, uint8_t slaveAddr, I2C_ModeTypeDef dataMode) +{ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(slaveAddr < 0x80); + + if (I2C_MasterGetFlag(I2Cx, I2C_IT_BUSBUSY | I2C_IT_MSTBUSY)) + { + return I2C_Status_Busy; + } + + // 清IT标志 + I2Cx->MICR &= CLEAR_IT_MASK; + + // 发送start+SLA+R/W命令 + I2Cx->MTDR = I2C_Cmd_Tx_RepSTART_Data_Rx_ACK | (slaveAddr << 1) | dataMode; + return (I2C_MasterPollingFlagReverse(I2Cx, I2C_IT_NACK)); +} + +/** + * @brief 主机向I2C从设备发送ReSTART信号和7位地址，并指定数据传输模式 + * + * @param I2Cx I2C外设指针，指向要使用的I2C外设 + * @param slaveAddr 从设备地址，7位地址，范围为0到127 + * @param dataMode 数据传输模式，指定传输方向（读或写） + * + * @return 如果函数成功发送ReSTART信号并设置从设备地址，则返回0；否则返回错误代码 + * + */ +uint8_t I2C_MasterReSTART_Addr7b(I2C_TypeDef *I2Cx, uint8_t slaveAddr, I2C_ModeTypeDef dataMode) +{ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(slaveAddr <= MAX_SLAVE_ADDR_7B); + + // 清IT标志 + I2Cx->MICR &= CLEAR_IT_MASK; + + // 发送start+SLA+R/W命令 + I2Cx->MTDR = I2C_Cmd_Tx_RepSTART_Data_Rx_ACK | (slaveAddr << 1) | dataMode; + return (I2C_MasterPollingFlagReverse(I2Cx, I2C_IT_NACK)); +} + +/** + * @brief 主机向I2C从设备发送10位地址的起始信号和数据模式 + * + * @param I2Cx I2C模块指针，指向要操作的I2C模块 + * @param slaveAddr 从设备的10位地址 + * @param dataMode 数据模式，指定是读操作还是写操作 + * + * @return 返回函数执行状态 + * + */ +uint8_t I2C_MasterSTART_Addr10b(I2C_TypeDef *I2Cx, uint16_t slaveAddr, I2C_ModeTypeDef dataMode) +{ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + if (I2C_MasterGetFlag(I2Cx, I2C_IT_BUSBUSY | I2C_IT_MSTBUSY)) + { + return I2C_Status_Busy; + } + + // 清IT标志 + I2Cx->MICR &= CLEAR_IT_MASK; + + // 发送start+SLA_MSB+R/W命令 + I2Cx->MTDR = I2C_Cmd_Tx_RepSTART_Data_Rx_ACK | ((uint8_t)((slaveAddr & I2C_SLAVE_ADDR10B_MSB_MASK) >> (8 - 1))) | I2C_SLAVE_ADDR10B_MSB | dataMode; + + if (I2C_MasterPollingFlagReverse(I2Cx, I2C_IT_NACK)) + { + return I2C_Status_Nak; + } + + // 发送SLA_LSB命令 + I2Cx->MTDR = (uint8_t)(slaveAddr & I2C_SLAVE_ADDR10B_LSB_MASK); + + return (I2C_MasterPollingFlagReverse(I2Cx, I2C_IT_NACK)); +} + +/** + * @brief 主机发送10位地址的I2C主机ReSTART命令 + * + * @param I2Cx I2C外设的指针 + * @param slaveAddr 从机地址，10位 + * @param dataMode 数据模式，读写标志 + * + * @return 返回状态码，成功返回I2C_Status_Success，NACK响应返回I2C_Status_Nak，超时返回I2C_Status_Timeout + */ +uint8_t I2C_MasterReSTART_Addr10b(I2C_TypeDef *I2Cx, uint16_t slaveAddr, I2C_ModeTypeDef dataMode) +{ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + // 清IT标志 + I2Cx->MICR &= CLEAR_IT_MASK; + + // 发送start+SLA_MSB+R/W命令 + I2Cx->MTDR = I2C_Cmd_Tx_RepSTART_Data_Rx_ACK | ((uint8_t)((slaveAddr & I2C_SLAVE_ADDR10B_MSB_MASK) >> (8 - 1))) | I2C_SLAVE_ADDR10B_MSB | dataMode; + + if (I2C_MasterPollingFlagReverse(I2Cx, I2C_IT_NACK)) + { + return I2C_Status_Nak; + } + + return I2C_Status_Success; +} + +/** + * @brief 主机发送STOP信号到I2C总线 + * + * @retval + */ +uint8_t I2C_MasterSTOP(I2C_TypeDef *I2Cx) +{ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + if (I2C_MasterPollingFlag(I2Cx, I2C_IT_TXE) != I2C_Status_Success) + { + return I2C_Status_Timeout; + } + + // 发送STOP命令 + I2Cx->MTDR = I2C_Cmd_Tx_STOP; + // return I2C_Status_Success; + return (I2C_MasterPollingFlag(I2Cx, I2C_IT_STOP)); +} + +/** + * @brief I2C 主机接收数据 + * + * @param I2Cx + * @param rxBuff: 接收缓存地址 + * @param rxSize： 接收长度 + * @retval 接收状态，成功返回I2C_Status_Success，失败返回I2C_Status_Error或其他错误码 + */ +uint8_t I2C_MasterReceive(I2C_TypeDef *I2Cx, uint8_t *rxBuff, uint16_t rxSize) +{ + uint8_t *buf; + + if ((rxBuff == NULL) || (rxSize == 0)) + { + return I2C_Status_Error; + } + + if (I2C_MasterPollingFlag(I2Cx, I2C_IT_TXE) != I2C_Status_Success) + { + return I2C_Status_Timeout; // 超时错误 + } + + // 发送接收数据命令 + I2Cx->MTDR = I2C_Cmd_Rx_DataToMRDR | (rxSize - 1); + + // 接收数据 + buf = rxBuff; + + while (rxSize--) + { + if (I2C_MasterPollingFlag(I2Cx, I2C_IT_RXNE) != I2C_Status_Success) + { + return I2C_Status_Timeout; // 超时错误 + } + + *buf++ = (uint8_t)I2Cx->MRDR; + } + + return I2C_Status_Success; +} + +/** + * @brief I2C 主机发送数据 + * + * @param I2Cx + * @param txBuff: 发送缓存地址 + * @param txSize： 发送长度 + * @retval 发送状态，成功返回I2C_Status_Success，失败返回I2C_Status_Error或其他错误码 + */ +uint8_t I2C_MasterSend(I2C_TypeDef *I2Cx, uint8_t *txBuff, uint16_t txSize) +{ + uint8_t *buf; + + // 检查输入参数 + if (txBuff == NULL || txSize == 0) + { + return I2C_Status_Error; + } + + buf = txBuff; + + while (txSize--) + { + // 等待TXE标志位被置位，表示发送缓冲区空闲 + if (I2C_MasterPollingFlag(I2Cx, I2C_IT_TXE) != I2C_Status_Success) + { + return I2C_Status_Timeout; // 超时错误 + } + + // 发送数据 + I2Cx->MTDR = *buf++; + + if (I2C_MasterPollingFlagReverse(I2Cx, I2C_IT_NACK) != I2C_Status_Success) + { + return I2C_Status_Timeout; // 超时错误 + } + } + + return I2C_Status_Success; +} + +/** + * @brief MCU对I2C总线进行软件复位 + * + * 该函数用于对指定的I2C总线进行软件复位操作。 + * 将所有主机逻辑和寄存器重置为默认状态，I2C_MCR0 寄存器自身除外 + * + * @param I2Cx 指向I2C控制器的指针 + */ +void I2C_MasterSoftReset(I2C_TypeDef *I2Cx) +{ + I2Cx->MCR0 = I2Cx_MCR0_RESET_Msk; + I2Cx->MCR0 = 0; +} + +/** + * @brief MCU对I2C从设备进行软件复位 + * + * 该函数用于对指定的I2C从设备进行软件复位。 + * 将所有从机逻辑和寄存器重置为默认状态，I2C_SCR0寄存器自身除外。 + * + * @param I2Cx I2C设备的指针，指向需要复位的I2C设备。 + */ +void I2C_SlaveSoftReset(I2C_TypeDef *I2Cx) +{ + I2Cx->SCR0 = I2Cx_SCR0_RESET_Msk; + I2Cx->SCR0 = 0; +} + +/** + * @brief 重置I2C主模式发送FIFO + * + * 该函数用于重置I2C主模式的发送FIFO。 + * 写 1 复位发送 FIFO,FIFO 复位后，该 FIFO 为空。 + + * @param I2Cx I2C模块指针，指向I2C_TypeDef结构体 + */ +void I2C_MasterTxFIFOReset(I2C_TypeDef *I2Cx) +{ + I2Cx->MCR0_f.TXFIFORST = 1; + I2Cx->MCR0_f.TXFIFORST = 0; +} + +/** + * @brief 重置I2C从机接收FIFO + * + * 该函数用于重置指定I2C从机的接收FIFO。 + * + * @param I2Cx I2C控制器指针，指向要操作的I2C控制器。 + */ +void I2C_MasterRxFIFOReset(I2C_TypeDef *I2Cx) +{ + I2Cx->MCR0_f.RXFIFORST = 1; + I2Cx->MCR0_f.RXFIFORST = 0; +} + +/** + * @brief 重置I2C从机发送FIFO + * + * 该函数用于重置I2C从机的发送FIFO。 + * 写 1 复位发送 FIFO,FIFO 复位后，该 FIFO 为空。 + * + * @param I2Cx I2C设备指针 + */ +void I2C_SlaveTxFIFOReset(I2C_TypeDef *I2Cx) +{ + I2Cx->SCR0_f.TXFIFORST = 1; + I2Cx->SCR0_f.TXFIFORST = 0; +} + +/** + * @brief 重置I2C从机接收FIFO + * + * 重置指定的I2C从机接收FIFO。 + * 写 1 复位接收数据寄存器。数据寄存器复位后，该数据寄存器为空。 + * + * @param I2Cx I2C设备指针 + */ +void I2C_SlaveRxFIFOReset(I2C_TypeDef *I2Cx) +{ + I2Cx->SCR0_f.RXFIFORST = 1; + I2Cx->SCR0_f.RXFIFORST = 0; +} + +/** + * @brief 设置I2C总线滤波器 + * + * 该函数用于设置I2C总线的SDA和SCL滤波器的值。 + * + * @param SDAFilter SDA滤波器的值，取值范围为0到15 + * @param SCLFilter SCL滤波器的值，取值范围为0到15 + * + * @return 无返回值 + * + * @note 调用此函数前需确保SDAFilter和SCLFilter的值小于16，否则会触发断言失败 + */ +void I2C_MasterBusFilter(I2C_TypeDef *I2Cx, uint8_t SDAFilter, uint8_t SCLFilter) +{ + assert_param(SDAFilter < 16); + assert_param(SCLFilter < 16); + REGBITS_MODIFY(I2Cx->MCR3, I2Cx_MCR3_FLTSDA_Msk | I2Cx_MCR3_FLTSCL_Msk, + ((SDAFilter & 0x0F) << I2Cx_MCR3_FLTSDA_Pos) | ((SCLFilter & 0x0F) << I2Cx_MCR3_FLTSCL_Pos)); +} + +/** + * @brief 设置I2C从设备总线滤波参数 + * + * 该函数用于设置I2C从设备的SDA和SCL线的滤波参数，以提高通信的稳定性。 + * + * @param SDAFilter SDA线的滤波参数，取值范围为0到15。 + * @param SCLFilter SCL线的滤波参数，取值范围为0到15。 + * + * @note SDAFilter和SCLFilter的值必须小于16，否则会触发断言错误。 + * 如果SDAFilter的值小于SCLFilter，则SDAFilter将被设置为SCLFilter的值。 + * + * @retval 无返回值 + */ +void I2C_SlaveBusFilter(I2C_TypeDef *I2Cx, uint8_t SDAFilter, uint8_t SCLFilter) +{ + assert_param(SDAFilter < 16); + assert_param(SCLFilter < 16); + + if (SDAFilter < SCLFilter) + { + SDAFilter = SCLFilter; + } + + REGBITS_MODIFY(I2Cx->SCR3, I2Cx_SCR3_FLTSDA_Msk | I2Cx_SCR3_FLTSCL_Msk, + ((SDAFilter & 0x0F) << I2Cx_SCR3_FLTSDA_Pos) | ((SCLFilter & 0x0F) << I2Cx_SCR3_FLTSCL_Pos)); +} + +/** + * @brief 使能或禁用I2C主模式接收数据匹配功能 + * + * @param I2Cx I2C模块指针，指向要操作的I2C模块 + * @param NewState 功能状态，使能或禁用接收数据匹配功能 + * - ENABLE: 使能接收数据匹配功能 + * - DISABLE: 禁用接收数据匹配功能 + * + * @return 无 + * + * @note 在调用此函数之前，请确保已经正确初始化了I2C模块。 + */ +void I2C_MasterRxDataMatch(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + // 获取当前状态 + FunctionalState CurrentState = (I2Cx->MCR1_f.RDMO == 1) ? ENABLE : DISABLE; + + // 如果状态需要改变 + if (CurrentState != NewState) + { + // 确保临界区安全 + __disable_irq(); // 禁用全局中断，防止竞态条件 + + if (NewState == ENABLE) + { + /* 从禁止更改为使能时，先清除 MICR.MATCH 标志再使能 RDMO */ + I2Cx->MICR_f.MATCH = 0; + I2Cx->MCR1_f.RDMO = 1; + } + else + { + /* 从使能更改为禁止时，先禁止 RDMO 再清除 MICR.MATCH 标志 */ + I2Cx->MCR1_f.RDMO = 0; + I2Cx->MICR_f.MATCH = 0; + } + + __enable_irq(); // 恢复全局中断 + } +} + +/** + * @brief 设置I2C主设备发送FIFO自动加载功能 + * + * @param I2Cx I2C设备指针，指向要操作的I2C设备 + * @param NewState 新的功能状态，ENABLE表示启用，DISABLE表示禁用 + * + * @retval 无 + */ +void I2C_MasterTxFIFO_Autoload(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + I2Cx->MCR1_f.CIRFIFO = 1; + } + else + { + I2Cx->MCR1_f.CIRFIFO = 0; + } +} + +/** + * @brief 初始化I2C主机配置结构 + * + * 初始化I2C主机配置结构，并将其设置为默认配置。 + * + * @param masterConfig 指向I2C_MasterConfigTypeDef类型的指针，指向需要初始化的配置结构 + */ +void I2C_MasterInitDefault(I2C_MasterConfigTypeDef *masterConfig) +{ + /* Initializes the configure structure to zero. */ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->I2C_BaudRate_Hz = 400000U; + masterConfig->I2C_ClockSouce = I2C_CLK_SRC_PCLK; + masterConfig->I2C_DataMatchMode = I2C_ByteMatch_Prohibit; + masterConfig->I2C_PinsConfig = 0; + masterConfig->I2C_SDA_Source = I2C_SDA_INSRC_GPIO; + masterConfig->I2C_SCL_Source = I2C_SCL_INSRC_GPIO; + masterConfig->I2C_InDebugState = FALSE; + masterConfig->I2C_InDeepSleepState = TRUE; + masterConfig->I2C_RxDataMatch = FALSE; + masterConfig->I2C_TxFIFO_Autoload = FALSE; + masterConfig->ignoreAck = FALSE; + masterConfig->sclGlitchFilterWidth_ns = 0; /* Set to 0 to disable the function */ + masterConfig->sdaGlitchFilterWidth_ns = 0; + masterConfig->busIdleTimeout_ns = 0; + masterConfig->pinLowTimeout_ns = 0; + masterConfig->hostRequest.enable = FALSE; + masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; +} + +/** + * @brief 初始化I2C从设备配置 + * + * 初始化I2C从设备的配置结构，将其重置为默认值。 + * + * @param slaveConfig 指向I2C_SlaveConfigTypeDef结构的指针，用于存储从设备配置 + */ +void I2C_SlaveInitDefault(I2C_SlaveConfigTypeDef *slaveConfig) +{ + /* Initializes the configure structure to zero. */ + (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); + + slaveConfig->addressMatchMode = I2C_Addr0_7bit; + slaveConfig->I2C_Addr0 = 0x00; + slaveConfig->I2C_Addr1 = 0x00; + slaveConfig->I2C_ClockSouce = I2C_CLK_SRC_PCLK_SLV; + slaveConfig->I2C_RegAddr = I2C_REG_ADDR_8BIT; + slaveConfig->filterEnable = TRUE; + slaveConfig->enableGeneralCall = FALSE; + slaveConfig->sclStall.enableAck = FALSE; + slaveConfig->sclStall.enableTx = TRUE; + slaveConfig->sclStall.enableRx = TRUE; + slaveConfig->sclStall.enableAddress = FALSE; + slaveConfig->ignoreAck = FALSE; + slaveConfig->enableReceivedAddressRead = FALSE; + slaveConfig->sdaGlitchFilterWidth_ns = 0U; /* Set to 0 to disable the function */ + slaveConfig->sclGlitchFilterWidth_ns = 0U; + slaveConfig->dataValidDelay_ns = 0U; + /* When enabling the slave tx SCL stall, set the default clock hold time to 250ns according + to I2C spec for standard mode baudrate(100k). User can manually change it to 100ns or 50ns + for fast-mode(400k) or fast-mode+(1M). */ + slaveConfig->clockHoldTime_ns = 100U; //Default fast-mode(400k) +} + +/** + * @brief 从EEPROM读取数据 + * + * 通过I2C总线从EEPROM读取指定地址的数据。 + * + * @param I2Cx I2C接口指针 + * @param regAddr EEPROM中的起始地址 + * @param regAddrType 地址类型，用于指定地址的长度和格式 + * @param pu8Data 存储读取数据的缓冲区指针 + * @param u16Len 要读取的数据长度 + * + * @return 读取操作的状态码，成功为0，失败为非0 + */ +uint8_t I2C_MasterReadEepromData(I2C_TypeDef *I2Cx, uint32_t regAddr, I2C_SlaveRegAddrTypeDef regAddrType, uint8_t *pu8Data, uint16_t u16Len) +{ + uint8_t u8State; + uint8_t dataTemp[4]; + uint8_t j; + + switch (regAddrType) + { + case I2C_REG_ADDR_8BIT: + j = 1; + break; + case I2C_REG_ADDR_16BIT: + j = 2; + break; + case I2C_REG_ADDR_24BIT: + j = 3; + break; + case I2C_REG_ADDR_32BIT: + j = 4; + break; + default: + return I2C_Status_Error; + } + + for (uint8_t i = 0; i < j; i++) + { + dataTemp[i] = (uint8_t)((regAddr >> (8 * (j - 1 - i))) & 0xFF); //MSB first + } + + u8State = I2C_MasterReceiveDataFromSlave(I2Cx, I2C_SLAVEADDRESS_EEPROM, dataTemp, regAddrType, pu8Data, u16Len); + return u8State; +} + +/** + * @brief 向EEPROM写入数据 + * + * 通过I2C总线向EEPROM写入数据。 + * + * @param I2Cx I2C总线接口指针 + * @param regAddr EEPROM寄存器地址 + * @param regAddrType 寄存器地址类型 + * @param pu8Data 待写入的数据指针 + * @param u16Len 待写入的数据长度 + * + * @return 函数执行状态，返回I2C_Status_OK表示成功，否则表示失败 + */ +uint8_t I2C_MasterWriteEepromData(I2C_TypeDef *I2Cx, uint32_t regAddr, I2C_SlaveRegAddrTypeDef regAddrType, uint8_t *pu8Data, uint16_t u16Len) +{ + if (I2Cx == NULL || pu8Data == NULL || u16Len == 0 || u16Len > MAX_DATA_LEN_EEPROM) + { + return I2C_Status_Error; + } + + uint8_t dataTemp[4 + MAX_DATA_LEN_EEPROM]; + uint8_t j; + + switch (regAddrType) + { + case I2C_REG_ADDR_8BIT: + j = 1; + break; + case I2C_REG_ADDR_16BIT: + j = 2; + break; + case I2C_REG_ADDR_24BIT: + j = 3; + break; + case I2C_REG_ADDR_32BIT: + j = 4; + break; + default: + return I2C_Status_Error; + } + + for (uint8_t i = 0; i < j; i++) + { + dataTemp[i] = (uint8_t)((regAddr >> (8 * (j - 1 - i))) & 0xFF); //MSB first + } + + memcpy(dataTemp + j, pu8Data, u16Len); + return I2C_MasterSendDataToSlave(I2Cx, I2C_SLAVEADDRESS_EEPROM, dataTemp, u16Len + j); +} + +/** + * @brief 向I2C从设备发送数据,查询方式。 + * + * 使用I2C总线向指定的从设备发送数据。 + * + * @param I2Cx I2C模块指针，指向具体的I2C模块 + * @param slaveAddr 从设备地址，支持7位和10位地址 + * @param pu8Data 指向要发送的数据的指针 + * @param u16Len 要发送的数据长度 + * + * @return 发送状态，成功返回I2C_Status_Success，失败返回I2C_Status_Error或其他错误码 + */ +uint8_t I2C_MasterSendDataToSlave(I2C_TypeDef *I2Cx, uint16_t slaveAddr, uint8_t *pu8Data, uint16_t u16Len) +{ + uint8_t u8State; + + // 检查输入参数的有效性 + if (I2Cx == NULL || pu8Data == NULL || u16Len == 0 || slaveAddr > MAX_SLAVE_ADDR_10B) + { + return I2C_Status_Error; + } + + // 根据从机地址长度选择对应的起始信号和地址发送函数 + if (slaveAddr & I2C_SLAVE_ADDR10B_MSB_MASK) + { + // 10-bit地址 + u8State = I2C_MasterSTART_Addr10b(I2Cx, slaveAddr, I2C_MODE_WRITE); + } + else + { + // 7-bit地址 + u8State = I2C_MasterSTART_Addr7b(I2Cx, (uint8_t)slaveAddr, I2C_MODE_WRITE); + } + + if (u8State != I2C_Status_Success) + { + return u8State; + } + + // 发送数据: N Byte address + User data, N = 0 ~ 2. + u8State = I2C_MasterSend(I2Cx, pu8Data, u16Len); + + if (u8State != I2C_Status_Success) + { + // 出错时发送停止信号 + I2C_MasterSTOP(I2Cx); + return u8State; + } + + // 发送停止信号并返回成功状态 + u8State = I2C_MasterSTOP(I2Cx); + return u8State; +} + +/** + * @brief 从I2C从设备接收数据 + * + * 该函数通过I2C接口从指定的从设备读取数据:顺序读方式 + * + * @param I2Cx I2C模块指针 + * @param slaveAddr 从设备地址 + * @param pu8RegAddr 数据寄存器的地址指针 + * @param regAddrType 寄存器地址类型（8位或16位） + * @param pu8Data 接收数据的缓冲区指针 + * @param u16Len 要接收的数据长度 + * + * @return 返回I2C操作状态，成功返回I2C_Status_Success，否则返回相应的错误代码 + */ +uint8_t I2C_MasterReceiveDataFromSlave(I2C_TypeDef *I2Cx, uint16_t slaveAddr, uint8_t *pu8RegAddr, I2C_SlaveRegAddrTypeDef regAddrType, uint8_t *pu8Data, uint16_t u16Len) +{ + uint8_t u8State; + uint8_t j; + + // 检查输入参数的有效性 + if (I2Cx == NULL || pu8Data == NULL || u16Len == 0 || slaveAddr > MAX_SLAVE_ADDR_10B || pu8RegAddr == NULL) + { + return I2C_Status_Error; + } + + // 根据从机地址长度选择对应的起始信号和地址发送函数 + if (slaveAddr & I2C_SLAVE_ADDR10B_MSB_MASK) + { + // 10-bit地址 + u8State = I2C_MasterSTART_Addr10b(I2Cx, slaveAddr, I2C_MODE_WRITE); + } + else + { + // 7-bit地址 + u8State = I2C_MasterSTART_Addr7b(I2Cx, (uint8_t)slaveAddr, I2C_MODE_WRITE); + } + + if (u8State != I2C_Status_Success) + { + return u8State; + } + + // 发送Data地址 + switch (regAddrType) + { + case I2C_REG_ADDR_8BIT: + j = 1; + break; + case I2C_REG_ADDR_16BIT: + j = 2; + break; + case I2C_REG_ADDR_24BIT: + j = 3; + break; + case I2C_REG_ADDR_32BIT: + j = 4; + break; + default: + return I2C_Status_Error; + } + + u8State = I2C_MasterSend(I2Cx, pu8RegAddr, j); + if (u8State != I2C_Status_Success) + { + // 出错时发送停止信号 + I2C_MasterSTOP(I2Cx); + return I2C_Status_Error; + } + +#if 1 + /* + *Tip: It is advisable to adjust the delay-time prior to issuing the I2C ReSTART-cmd based on factors such as: + *the MCU's HCLK, the I2C's bps, the compiler used, and the level of optimization. + */ + FirmwareDelay(2000); // delay approximately 340us@48MHz & 100k bps +#endif + + // 发送重复起始信号和从机地址（读模式） + if (slaveAddr & I2C_SLAVE_ADDR10B_MSB_MASK) + { + // 10-bit地址 + u8State = I2C_MasterReSTART_Addr10b(I2Cx, slaveAddr, I2C_MODE_READ); + } + else + { + // 7-bit地址 + u8State = I2C_MasterReSTART_Addr7b(I2Cx, (uint8_t)slaveAddr, I2C_MODE_READ); + } + + if (u8State != I2C_Status_Success) + { + return u8State; + } + + // 接收数据 + u8State = I2C_MasterReceive(I2Cx, pu8Data, u16Len); + + if (u8State != I2C_Status_Success) + { + // 出错时发送停止信号 + I2C_MasterSTOP(I2Cx); + return I2C_Status_Error; + } + + // 发送停止信号并返回成功状态 + u8State = I2C_MasterSTOP(I2Cx); + return u8State; +} + +/** + * @brief I2C从设备接收数据 + * + * 指定的I2C从设备接收数据，并将接收到的数据存储到提供的缓冲区中。 + * + * @param I2Cx I2C设备指针 + * @param rxBuff 存储接收数据的缓冲区指针 + * @param rxSize 存储接收数据量的指针 + * + * @return 接收状态，成功返回I2C_Status_Success，错误则返回相应的错误状态 + * - I2C_Status_Error：函数参数无效 + * - I2C_Status_FifoError：缓冲区即将溢出 + * - I2C_Status_Timeout：接收超时 + */ +uint8_t I2C_SlaveReceive(I2C_TypeDef *I2Cx, uint8_t *rxBuff, uint16_t *rxSize) +{ + uint8_t *buf; + uint32_t cntRx = 0; + uint32_t timeout = I2C_WAIT_TIMEOUT; // 使用定义的超时值，便于调整 + + if ((I2Cx == NULL) || (rxBuff == NULL) || (rxSize == NULL)) + { + return I2C_Status_Error; + } + + buf = rxBuff; + + while (timeout--) + { + uint8_t flagStatus = I2C_SlavePollingFlag(I2Cx, I2C_IT_RXNE_SLV | I2C_IT_STOP_SLV | I2C_IT_RESTART_SLV); + + if (flagStatus == I2C_Status_Success) + { + if (I2C_SlaveGetFlag(I2Cx, I2C_IT_RXNE_SLV)) + { + if (cntRx >= MAX_DATA_LEN_RX) + { + // 缓冲区即将溢出，停止接收并返回错误 + *rxSize = cntRx; + return I2C_Status_FifoError; + } + + *buf++ = (uint8_t)I2Cx->SRDR; + cntRx++; + } + else + { + // 存在 STOP 或 RESTART 标志位，接收结束 + *rxSize = cntRx; + return I2C_Status_Success; + } + } + else if (timeout == 0) + { + // 超时，返回当前接收的数据量 + *rxSize = cntRx; + return I2C_Status_Timeout; + } + } + + // 如果退出循环不是因为成功接收或超时，则返回错误状态 + *rxSize = cntRx; + return I2C_Status_Error; +} + +/** + * @brief I2C从设备发送数据 + * + * 该函数用于从设备通过指定的I2C总线向主机发送数据。 + * + * @param I2Cx I2C总线实例指针 + * @param txBuff 指向要发送数据的缓冲区指针 + * @param txSize 要发送的数据字节数 + * + * @return 发送状态，成功返回I2C_Status_Success，失败返回相应的错误代码 + * - I2C_Status_Error: 输入参数无效 + * - I2C_Status_Timeout: 发送数据时发生超时 + */ +uint8_t I2C_SlaveSend(I2C_TypeDef *I2Cx, uint8_t *txBuff, uint16_t txSize) +{ + uint8_t *buf; + + // 检查输入参数 + if (txBuff == NULL || txSize == 0) + { + return I2C_Status_Error; + } + + buf = txBuff; + + while (txSize--) + { + // 等待TXE标志位被置位，表示发送缓冲区空闲 + if (I2C_SlavePollingFlag(I2Cx, I2C_IT_TXE_SLV) != I2C_Status_Success) + { + return I2C_Status_Timeout; // 超时错误 + } + + // 发送数据 + I2Cx->STDR = *buf++; + } + + return I2C_Status_Success; +} + +/** + * @brief 清除I2C从机标志位 + * + * 该函数用于清除指定的I2C从机标志位。 + * + * @param I2Cx 指向I2C外设的指针 + * @param I2C_FLAG 要清除的I2C从机标志位，可以是以下值之一及其组合： + * - I2C_IT_FIFO_SLV + * - I2C_IT_BIT_SLV + * - I2C_IT_STOP_SLV + * - I2C_IT_RESTART_SLV + * + * @return 无返回值 + */ +void I2C_SlaveClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG_SLV(I2C_FLAG)); + + REGBITS_CLR(I2Cx->SICR, I2C_FLAG); +} + +/** + * @brief 轮询I2C从机状态标志位 + * + * 此函数用于轮询指定的I2C从机状态标志位，并根据输入参数决定是等待标志位被设置还是清除。 + * + * @param I2Cx I2C外设指针 + * @param I2C_FLAG 需要轮询的标志位，可以是以下值之一及其组合： + * - I2C_IT_BUSBUSY_SLV + * - I2C_IT_SLVBUSY_SLV + * - I2C_IT_ALERT_SLV + * - I2C_IT_GC_SLV + * - I2C_IT_AM1_SLV + * - I2C_IT_AM0_SLV + * - I2C_IT_FIFO_SLV + * - I2C_IT_BIT_SLV + * - I2C_IT_STOP_SLV + * - I2C_IT_RESTART_SLV + * - I2C_IT_TACK_SLV + * - I2C_IT_ADDR_SLV + * - I2C_IT_RXNE_SLV + * - I2C_IT_TXE_SLV + * + * @param reverse 标志位检测逻辑：TRUE表示等待标志位清除，FALSE表示等待标志位设置 + * + * @return 返回状态码： + * - I2C_Status_Success：成功检测到标志位状态 + * - I2C_Status_Timeout：轮询超时，未检测到标志位状态 + */ +static uint8_t I2C_SlavePollingFlagCommon(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG, boolean_t reverse) +{ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_FLAG_SLV(I2C_FLAG)); + + for (uint32_t waitTimes = I2C_WAIT_TIMEOUT; waitTimes > 0; --waitTimes) + { + uint32_t regVal = I2Cx->SISR; + uint32_t flagDetected = reverse ? !(regVal & I2C_FLAG) : (regVal & I2C_FLAG); + + if (flagDetected) + { + return I2C_Status_Success; + } + } + + return I2C_Status_Timeout; +} + +/** + * @brief 轮询从机I2C标志位 + * + * 轮询指定的I2C标志位，如果标志位被设置则返回1，否则返回0。 + * + * @param I2Cx I2C接口指针 + * @param I2C_FLAG 需要轮询的标志位 + * + * @return 如果标志位被设置，则返回I2C_Status_Success；否则返回I2C_Status_Timeout + */ +uint8_t I2C_SlavePollingFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + return I2C_SlavePollingFlagCommon(I2Cx, I2C_FLAG, FALSE); +} + +/** + * @brief 反转I2C从设备轮询标志位 + * + * 该函数用于反转I2C从设备的轮询标志位。 + * + * @param I2Cx I2C外设指针 + * @param I2C_FLAG 要轮询的标志位 + * + * @return 反转后的标志位状态，I2C_Status_Success表示未触发，I2C_Status_Timeout表示已触发 + */ +uint8_t I2C_SlavePollingFlagReverse(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + return I2C_SlavePollingFlagCommon(I2Cx, I2C_FLAG, TRUE); +} + +/** + * @brief 获取I2C从设备标志位状态 + * + * 根据提供的I2C外设和标志位，获取并返回该标志位的状态。 + * + * @param I2Cx 指向I2C外设的指针 + * @param I2C_FLAG 要检查的I2C从设备标志位 + * + * @return 如果标志位被设置，则返回非零值；否则返回0 + * + */ +uint32_t I2C_SlaveGetFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_FLAG_SLV(I2C_FLAG)); + + // 获取并返回指定的标志位状态 + return (I2Cx->SISR & I2C_FLAG); +} + +/** + * @brief 设置 I2C 从机在发送响应阶段是否发出 NACK + * + * @param I2Cx 指向 I2C 模块的指针 + * @param stateNAck 是否发出 NACK 的状态 + * - ENABLE: 从机在发送响应阶段发出 NACK + * - DISABLE: 从机在发送响应阶段发出 ACK + */ +void I2C_SlaveTxNAck(I2C_TypeDef *I2Cx, FunctionalState stateNAck) +{ + if (stateNAck == ENABLE) + { + REGBITS_SET(I2Cx->STAR, I2Cx_STAR_TXNACK_Msk); // 从机在发送响应阶段，发出 NACK + } + else + { + REGBITS_CLR(I2Cx->STAR, I2Cx_STAR_TXNACK_Msk); // 从机在发送响应阶段，发出 ACK + } +} + +/** + * @brief 根据给定的时钟频率、脉冲宽度、最小和最大周期数以及预分频器计算I2C总线上的周期数 + * + * @param sourceClock_Hz 源时钟频率（Hz） + * @param width_ns 脉冲宽度（纳秒） + * @param minCycles 最小周期数 + * @param maxCycles 最大周期数 + * @param prescaler 预分频器值 + * + * @return 计算出的周期数 + * + * @note 确保sourceClock_Hz大于0 + */ +static uint32_t I2C_GetCyclesForWidth( + uint32_t sourceClock_Hz, uint32_t width_ns, uint32_t minCycles, uint32_t maxCycles, uint32_t prescaler) +{ + assert_param(sourceClock_Hz > 0U); + + uint32_t divider = 1U; + + while (prescaler != 0U) + { + divider *= 2U; + prescaler--; + } + + uint32_t busCycle_ns = 1000000U / (sourceClock_Hz / divider / 1000U); + /* Calculate the cycle count, round up the calculated value. */ + uint32_t cycles = (width_ns * 10U / busCycle_ns + 5U) / 10U; + + /* If the calculated value is smaller than the minimum value, use the minimum value */ + if (cycles < minCycles) + { + cycles = minCycles; + } + + /* If the calculated value is larger than the maximum value, use the maxmum value */ + if (cycles > maxCycles) + { + cycles = maxCycles; + } + + return cycles; +} + +/** + * @brief 设置I2C主机模式的波特率 + * + * @param I2Cx I2C接口指针，指向I2C_TypeDef结构体 + * @param sourceClock_Hz I2C接口时钟源频率（单位：Hz） + * @param baudRate_Hz 期望的波特率（单位：Hz） + * + * @note 在设置波特率之前，会先禁用I2C主模式，设置完成后会恢复I2C主模式。 + */ +void I2C_MasterSetBaudRate(I2C_TypeDef *I2Cx, uint32_t sourceClock_Hz, uint32_t baudRate_Hz) +{ + boolean_t wasEnabled; + uint8_t filtScl = (uint8_t)((I2Cx->MCR3 & I2Cx_MCR3_FLTSCL_Msk) >> I2Cx_MCR3_FLTSCL_Pos); + + uint8_t divider = 1U; + uint8_t bestDivider = 1U; + uint8_t prescale = 0U; + uint8_t bestPre = 0U; + + uint8_t clkCycle; + uint8_t bestclkCycle = 0U; + + uint32_t absError = 0U; + uint32_t bestError = 0xffffffffu; + uint32_t computedRate; + + uint32_t tmpReg = 0U; + + /* Disable master mode. */ + wasEnabled = (0U != ((I2Cx->MCR0 & I2Cx_MCR0_MEN_Msk) >> I2Cx_MCR0_MEN_Pos)); + I2C_MasterCmd(I2Cx, DISABLE); + + for (prescale = 0U; prescale <= 7U; prescale++) + { + /* Calculate the clkCycle, clkCycle = CLKLO + CLKHI, divider = 2 ^ prescale */ + clkCycle = (uint8_t)((10U * sourceClock_Hz / divider / baudRate_Hz + 5U) / 10U - (2U + filtScl) / divider - 2U); + + if (clkCycle > (120U - (2U + filtScl) / divider)) + { + divider *= 2U; + continue; + } + + /* Calculate the computed baudrate and compare it with the desired baudrate */ + computedRate = (sourceClock_Hz / (uint32_t)divider) / + ((uint32_t)clkCycle + 2U + (2U + (uint32_t)filtScl) / (uint32_t)divider); + absError = baudRate_Hz > computedRate ? baudRate_Hz - computedRate : computedRate - baudRate_Hz; + + if (absError < bestError) + { + bestPre = prescale; + bestDivider = divider; + bestclkCycle = clkCycle; + bestError = absError; + + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0U) + { + break; + } + } + + divider *= 2U; + } + + uint8_t tmpHigh = (bestclkCycle - (2U + filtScl) / bestDivider) / 2U; + + while (tmpHigh > (bestclkCycle - 52U * sourceClock_Hz / baudRate_Hz / bestDivider / 100U + 1U)) + { + tmpHigh = tmpHigh - 1U; + } + + /* Calculate DATAVD and SETHOLD. + To meet the timing requirement of I2C spec for standard mode, fast mode and fast mode plus: */ + uint8_t tmpHold = (uint8_t)(sourceClock_Hz / baudRate_Hz / bestDivider / 2U) - 1U; + + uint8_t tmpDataVd = (uint8_t)(sourceClock_Hz / baudRate_Hz / bestDivider / 4U) - 1U; + + if ((sourceClock_Hz / baudRate_Hz / 20U) > (bestDivider + 2U)) + { + /* Read out the FILTSDA configuration, if it is smaller than expected, change the setting. */ + uint8_t filtSda = (uint8_t)((I2Cx->MCR3 & I2Cx_MCR3_FLTSDA_Msk) >> I2Cx_MCR3_FLTSDA_Pos); + + if (filtSda < (sourceClock_Hz / baudRate_Hz / 20U - bestDivider - 2U)) + { + filtSda = (uint8_t)(sourceClock_Hz / baudRate_Hz / 20U) - bestDivider - 2U; + } + + I2Cx->MCR3 = (I2Cx->MCR3 & ~I2Cx_MCR3_FLTSDA_Msk) | I2C_MCR3_FILTSDA(filtSda); + } + + /* Set CLKHI, CLKLO, SETHOLD, DATAVD value. */ + tmpReg = I2C_MCCR0_CLKHI((uint32_t)tmpHigh) | + I2C_MCCR0_CLKLO((uint32_t)((uint32_t)bestclkCycle - (uint32_t)tmpHigh)) | + I2C_MCCR0_SETHOLD((uint32_t)tmpHold) | I2C_MCCR0_DATAVD((uint32_t)tmpDataVd); + I2Cx->MCCR = tmpReg; + + /* Set PRESCALE value. */ + I2Cx->MCR2 = (I2Cx->MCR2 & ~I2Cx_MCR2_PRESCALE_Msk) | I2C_MCR2_PRESCALE(bestPre); + + /* Restore master mode. */ + if (wasEnabled) + { + I2C_MasterCmd(I2Cx, ENABLE); + } +} + +/** + * @brief 获取LPI2C实例编号 + * + * 根据给定的I2C类型指针获取其对应的LPI2C实例编号。 + * + * @param I2Cx I2C类型指针 + * + * @return 返回LPI2C实例编号，如果找不到对应的实例则返回超出范围的编号 + */ +uint32_t LPI2C_GetInstance(I2C_TypeDef *I2Cx) +{ + uint32_t instance; + for (instance = 0U; instance < ARRAY_SZ(kLpi2cBases); ++instance) + { + if (kLpi2cBases[instance] == I2Cx) + { + break; + } + } + + assert_param(instance < ARRAY_SZ(kLpi2cBases)); + return instance; +} + +/** + * @brief 检查并清除LPI2C主机错误 + * + * 检查并清除LPI2C主机错误。在发生错误时，将自动发送停止信号。必须清除错误才能开始新的传输。 + * + * @param I2Cx LPI2C模块指针 + * @param status LPI2C状态标志 + * + * @return 返回状态码。成功返回kStatus_Success，错误返回对应的错误码。 + */ +status_t LPI2C_MasterCheckAndClearError(I2C_TypeDef *I2Cx, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check for error. These errors cause a stop to automatically be sent. We must */ + /* clear the errors before a new transfer can start. */ + status &= (uint32_t)kLPI2C_MasterErrorFlags; + if (0U != status) + { + /* Select the correct error code. Ordered by severity, with bus issues first. */ + if (0U != (status & (uint32_t)kLPI2C_MasterPinLowTimeoutFlag)) + { + result = kStatus_LPI2C_PinLowTimeout; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterArbitrationLostFlag)) + { + result = kStatus_LPI2C_ArbitrationLost; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterNackDetectFlag)) + { + result = kStatus_LPI2C_Nak; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterFifoErrFlag)) + { + result = kStatus_LPI2C_FifoError; + } + else + { + ; /* Intentional empty */ + } + + /* Clear the flags. */ + I2C_MasterClearFlag(I2Cx, status); + + /* Reset fifos. These flags clear automatically. */ + I2Cx->MCR0 |= I2Cx_MCR0_RXFIFORST_Msk | I2Cx_MCR0_TXFIFORST_Msk; + } + else + { + ; /* Intentional empty */ + } + + return result; +} + +/** + * @brief 等待LPI2C主机发送缓冲区准备就绪 + * + * 该函数等待直到LPI2C主机的发送缓冲区准备就绪，或者发生错误。 + * + * @param I2Cx I2C外设地址 + * + * @return 返回函数执行状态，成功返回kStatus_Success，其他值表示错误。 + */ +static status_t LPI2C_MasterWaitForTxReady(I2C_TypeDef *I2Cx) +{ + status_t result = kStatus_Success; + uint32_t status; + size_t txCount; + size_t txFifoSize = (size_t)FSL_FEATURE_I2C_FIFO_SIZEn(I2Cx); + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + do + { + /* Get the number of words in the tx fifo and compute empty slots. */ + LPI2C_MasterGetFifoCounts(I2Cx, NULL, &txCount); + txCount = txFifoSize - txCount; + + /* Check for error flags. */ + status = LPI2C_MasterGetStatusFlags(I2Cx); + result = LPI2C_MasterCheckAndClearError(I2Cx, status); + if (kStatus_Success != result) + { + break; + } +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == txCount) && (0U != waitTimes)); + + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#else + } while (0U == txCount); +#endif + + return result; +} + +/** + * @brief 检查I2C总线是否繁忙 + * + * 检查指定的I2C总线是否处于繁忙状态。 + * + * @param I2Cx I2C模块指针 + * + * @return 返回状态码 + * - kStatus_Success: 总线不繁忙 + * - kStatus_LPI2C_Busy: 总线繁忙 + */ +status_t LPI2C_CheckForBusyBus(I2C_TypeDef *I2Cx) +{ + status_t ret = kStatus_Success; + + uint32_t status = LPI2C_MasterGetStatusFlags(I2Cx); + if ((0U != (status & (uint32_t)kLPI2C_MasterBusBusyFlag)) && (0U == (status & (uint32_t)kLPI2C_MasterBusyFlag))) + { + ret = kStatus_LPI2C_Busy; + } + + return ret; +} + +/** + * @brief I2C 主模式去初始化函数 + * + * 该函数用于将指定的 I2C 端口从主模式去初始化，恢复到复位状态。 + * + * @param I2Cx I2C 端口指针，指向要操作的 I2C 端口。 + */ +void I2C_MasterDeinit(I2C_TypeDef *I2Cx) +{ + /* Restore to reset state. */ + I2C_MasterSoftReset(I2Cx); + + I2C_DeInit(I2Cx); +} + +/** + * @brief 配置I2C主机模式的数据匹配参数 + * + * 该函数用于配置I2C主机模式的数据匹配参数。 + * + * @param I2Cx I2C模块指针，指向要配置的I2C模块 + * @param matchConfig 指向数据匹配配置参数的指针 + */ +void LPI2C_MasterConfigureDataMatch(I2C_TypeDef *I2Cx, const lpi2c_data_match_config_t *matchConfig) +{ + /* Disable master mode. */ + boolean_t wasEnabled = (0U != ((I2Cx->MCR0 & I2Cx_MCR0_MEN_Msk) >> I2Cx_MCR0_MEN_Pos)); + I2C_MasterCmd(I2Cx, DISABLE); + + I2Cx->MCR2 = (I2Cx->MCR2 & ~I2Cx_MCR2_MATCFG_Pos) | I2C_MCR2_MATCFG(matchConfig->matchMode); + I2Cx->MCR1 = (I2Cx->MCR1 & ~I2Cx_MCR1_RDMO_Msk) | I2C_MCR1_RDMO(matchConfig->rxDataMatchOnly); + I2Cx->MMATCH = I2C_MDMR_MATCH0(matchConfig->match0) | I2C_MDMR_MATCH1(matchConfig->match1); + + /* Restore master mode. */ + if (wasEnabled) + { + I2C_MasterCmd(I2Cx, ENABLE); + } +} + +/** + * @brief 主设备停止I2C总线传输 + * + * 停止指定的I2C总线上的数据传输。 + * + * @param I2Cx I2C设备指针 + * + * @return 返回状态码，成功返回kStatus_Success，失败返回相应的错误码 + */ +status_t LPI2C_MasterStop(I2C_TypeDef *I2Cx) +{ + /* Wait until there is room in the fifo. */ + status_t result = LPI2C_MasterWaitForTxReady(I2Cx); + if (kStatus_Success == result) + { + /* Send the STOP signal */ + I2Cx->MTDR = (uint32_t)kStopCmd; + + /* Wait for the stop detected flag to set, indicating the transfer has completed on the bus. */ + /* Also check for errors while waiting. */ +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + +#if I2C_RETRY_TIMES != 0U + while ((result == kStatus_Success) && (0U != waitTimes)) + { + waitTimes--; +#else + while (result == kStatus_Success) + { +#endif + uint32_t status = LPI2C_MasterGetStatusFlags(I2Cx); + + /* Check for error flags. */ + result = LPI2C_MasterCheckAndClearError(I2Cx, status); + + /* Check if the stop was sent successfully. */ + if ((0U != (status & (uint32_t)kLPI2C_MasterStopDetectFlag)) && + (0U != (status & (uint32_t)kLPI2C_MasterTxReadyFlag))) + { + I2C_MasterClearFlag(I2Cx, (uint32_t)kLPI2C_MasterStopDetectFlag); + break; + } + } + +#if I2C_RETRY_TIMES != 0U + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#endif + } + + return result; +} + +/** + * @brief 主机从I2C总线上接收数据 + * + * 从指定的I2C总线上接收数据，并存储到提供的缓冲区中。 + * + * @param I2Cx I2C设备指针 + * @param rxBuff 用于存储接收到的数据的缓冲区指针 + * @param rxSize 需要接收的数据大小 + * + * @return 返回状态码，成功返回kStatus_Success，失败返回相应的错误码 + */ +status_t LPI2C_MasterReceive(I2C_TypeDef *I2Cx, void *rxBuff, size_t rxSize) +{ + assert_param(NULL != rxBuff); + + status_t result = kStatus_Success; + uint8_t *buf; + size_t tmpRxSize = rxSize; +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes; +#endif + + /* Check transfer data size. */ + if (rxSize > (256UL * (uint32_t)FSL_FEATURE_I2C_FIFO_SIZEn(I2Cx))) + { + return kStatus_InvalidArgument; + } + + /* Handle empty read. */ + if (rxSize != 0U) + { + /* Wait until there is room in the command fifo. */ + result = LPI2C_MasterWaitForTxReady(I2Cx); + if (kStatus_Success == result) + { + /* Issue command to receive data. A single write to MTDR can issue read operation of 0xFFU + 1 byte of data + at most, so when the rxSize is larger than 0x100U, push multiple read commands to MTDR until rxSize is + reached. */ + while (tmpRxSize != 0U) + { + if (tmpRxSize > 256U) + { + I2Cx->MTDR = (uint32_t)(kRxDataCmd) | (uint32_t)I2C_MTDR_DATA(0xFFU); + tmpRxSize -= 256U; + } + else + { + I2Cx->MTDR = (uint32_t)(kRxDataCmd) | (uint32_t)I2C_MTDR_DATA(tmpRxSize - 1U); + tmpRxSize = 0U; + } + } + + /* Receive data */ + buf = (uint8_t *)rxBuff; + while (0U != (rxSize--)) + { +#if I2C_RETRY_TIMES != 0U + waitTimes = I2C_RETRY_TIMES; +#endif + /* Read LPI2C receive fifo register. The register includes a flag to indicate whether */ + /* the FIFO is empty, so we can both get the data and check if we need to keep reading */ + /* using a single register read. */ + uint32_t value = 0U; + do + { + /* Check for errors. */ + result = LPI2C_MasterCheckAndClearError(I2Cx, LPI2C_MasterGetStatusFlags(I2Cx)); + if (kStatus_Success != result) + { + break; + } + + value = I2Cx->MRDR; +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U != (value & I2Cx_MRDR_EMPTY_Msk)) && (0U != waitTimes)); + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#else + } while (0U != (value & I2Cx_MRDR_EMPTY_Msk)); +#endif + if ((status_t)kStatus_Success != result) + { + break; + } + + *buf++ = (uint8_t)(value & I2Cx_MRDR_DATA_Msk); + } + } + } + + return result; +} + +/** + * @brief 主机向 I2C 总线发送数据 + * + * 该函数用于通过 I2C 总线发送数据。 + * + * @param I2Cx I2C 控制器实例指针 + * @param txBuff 指向要发送的数据缓冲区的指针 + * @param txSize 要发送的数据大小（字节数） + * + * @return 发送操作的状态码。如果成功，返回 kStatus_Success；否则返回相应的错误代码。 + */ +status_t LPI2C_MasterSend(I2C_TypeDef *I2Cx, void *txBuff, size_t txSize) +{ + status_t result = kStatus_Success; + uint8_t *buf = (uint8_t *)txBuff; + + assert_param(NULL != txBuff); + + /* Send data buffer */ + while (0U != (txSize--)) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + result = LPI2C_MasterWaitForTxReady(I2Cx); + if (kStatus_Success != result) + { + break; + } + + /* Write byte into LPI2C master data register. */ + I2Cx->MTDR = *buf++; + } + + return result; +} + +/** + * @brief 主机在阻塞模式下通过I2C总线进行主从设备数据传输 + * + * 该函数在阻塞模式下，通过I2C总线进行主从设备之间的数据传输。它支持读写操作， + * 并处理数据传输过程中的各种细节，如子地址的发送、数据传输的开始和结束等。 + * + * @param I2Cx I2C模块的外设基地址指针 + * @param transfer 指向传输配置的指针，包含传输的方向、数据大小、子地址等信息 + * + * @return 传输状态，成功返回kStatus_Success，失败返回相应的错误代码 + */ +status_t LPI2C_MasterTransferBlocking(I2C_TypeDef *I2Cx, lpi2c_master_transfer_t *transfer) +{ + assert_param(NULL != transfer); + assert_param(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + status_t result = kStatus_Success; + uint16_t commandBuffer[7]; + uint32_t cmdCount = 0U; + + /* Check transfer data size in read operation. */ + if ((transfer->direction == I2C_MODE_READ) && + (transfer->dataSize > (256UL * (uint32_t)FSL_FEATURE_I2C_FIFO_SIZEn(I2Cx)))) + { + return kStatus_InvalidArgument; + } + + /* Return an error if the bus is already in use not by us. */ + result = LPI2C_CheckForBusyBus(I2Cx); + if (kStatus_Success == result) + { + /* Clear all flags. */ + I2C_MasterClearFlag(I2Cx, (uint32_t)kLPI2C_MasterClearFlags); + + /* Turn off auto-stop option. */ + I2Cx->MCR2 &= ~I2Cx_MCR2_AUTOSTOP_Msk; + + I2C_ModeTypeDef direction = (0U != transfer->subaddressSize) ? I2C_MODE_WRITE : transfer->direction; + if (0U == (transfer->flags & (uint32_t)kLPI2C_TransferNoStartFlag)) + { + if (transfer->slaveAddress & I2C_SLAVE_ADDR10B_MSB_MASK) + { + //10-bit slave address + //slave MSB address + commandBuffer[cmdCount++] = + (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((((uint16_t)transfer->slaveAddress & I2C_SLAVE_ADDR10B_MSB_MASK) >> (8 - 1)) | I2C_SLAVE_ADDR10B_MSB) | (uint16_t)direction); + + //slave LSB address + commandBuffer[cmdCount++] = + (uint16_t)((uint16_t)transfer->slaveAddress & I2C_SLAVE_ADDR10B_LSB_MASK); + } + else + { + //7-bit slave address + commandBuffer[cmdCount++] = + (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)transfer->slaveAddress << 1U) | (uint16_t)direction); + } + } + + /* Subaddress, MSB first. */ + if (0U != transfer->subaddressSize) + { + uint32_t subaddressRemaining = transfer->subaddressSize; + while (0U != subaddressRemaining--) + { + uint8_t subaddressByte = (uint8_t)((transfer->subaddress >> (8U * subaddressRemaining)) & 0xffU); + commandBuffer[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling. */ + if ((0U != transfer->dataSize) && (transfer->direction == I2C_MODE_READ)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == I2C_MODE_WRITE) + { + if (transfer->slaveAddress & I2C_SLAVE_ADDR10B_MSB_MASK) + { + //10-bit slave address + //slave MSB address + commandBuffer[cmdCount++] = + (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((((uint16_t)transfer->slaveAddress & I2C_SLAVE_ADDR10B_MSB_MASK) >> (8 - 1)) | I2C_SLAVE_ADDR10B_MSB) | (uint16_t)I2C_MODE_READ); + } + else + { + //7-bit slave address + commandBuffer[cmdCount++] = + (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)transfer->slaveAddress << 1U) | (uint16_t)I2C_MODE_READ); + } + } + } + + /* Send command buffer */ + uint32_t index = 0U; + while (0U != cmdCount--) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + result = LPI2C_MasterWaitForTxReady(I2Cx); + if (kStatus_Success != result) + { + break; + } + + /* Write byte into LPI2C master data register. */ + I2Cx->MTDR = commandBuffer[index]; + index++; + } + + if (kStatus_Success == result) + { + /* Transmit data. */ + if ((transfer->direction == I2C_MODE_WRITE) && (transfer->dataSize > 0U)) + { + /* Send Data. */ + result = LPI2C_MasterSend(I2Cx, transfer->data, transfer->dataSize); + } + + /* Receive Data. */ + if ((transfer->direction == I2C_MODE_READ) && (transfer->dataSize > 0U)) + { + result = LPI2C_MasterReceive(I2Cx, transfer->data, transfer->dataSize); + } + + if (kStatus_Success == result) + { + if ((transfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U) + { + result = LPI2C_MasterStop(I2Cx); + } + } + } + } + + return result; +} + +/** + * @brief 创建I2C主设备传输句柄 + * + * 该函数用于初始化并创建一个I2C主设备传输句柄，并设置相关的回调函数和用户数据。 + * + * @param I2Cx I2C设备实例指针 + * @param handle 指向I2C主设备传输句柄的指针 + * @param callback I2C主设备传输完成的回调函数 + * @param userData 用户自定义数据指针，将传递给回调函数 + */ +void LPI2C_MasterTransferCreateHandle(I2C_TypeDef *I2Cx, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert_param(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = LPI2C_GetInstance(I2Cx); + + /* Save base and instance. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_lpi2cMasterHandle[instance] = handle; + + /* Set irq handler. */ + s_lpi2cMasterIsr = LPI2C_MasterTransferHandleIRQ; + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + LPI2C_MasterDisableInterrupts(I2Cx, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC.*/ + NVIC_ClearPendingIRQ(kLpi2cIrqs[instance]); + NVIC_EnableIRQ(kLpi2cIrqs[instance]); +} + +/** + * @brief 运行I2C传输状态机 + * + * 此函数用于控制I2C传输状态机，包括发送命令、发送/接收数据以及发送停止命令等状态。 + * + * @param I2Cx I2C模块基地址指针 + * @param handle I2C主模式句柄指针 + * @param isDone 用于指示传输是否完成的布尔指针 + * + * @return 返回状态码，kStatus_Success表示成功，其他值表示错误 + */ +static status_t LPI2C_RunTransferStateMachine(I2C_TypeDef *I2Cx, lpi2c_master_handle_t *handle, boolean_t *isDone) +{ + uint32_t status; + status_t result = kStatus_Success; + lpi2c_master_transfer_t *xfer; + size_t txCount; + size_t rxCount; + size_t txFifoSize = (size_t)FSL_FEATURE_I2C_FIFO_SIZEn(I2Cx); + boolean_t state_complete = FALSE; + uint16_t sendval; + + /* Set default isDone return value. */ + *isDone = FALSE; + + /* Check for errors. */ + status = LPI2C_MasterGetStatusFlags(I2Cx); + + /* Get fifo counts. */ + LPI2C_MasterGetFifoCounts(I2Cx, &rxCount, &txCount); + + /* Get pointer to private data. */ + xfer = &handle->transfer; + + /* For the last byte, nack flag is expected. + Do not check and clear kLPI2C_MasterNackDetectFlag for the last byte, + in case FIFO is emptied when stop command has not been sent. */ + if (handle->remainingBytes == 0U) + { + /* When data size is not zero which means it is not only one byte of address is sent, and */ + /* when the txfifo is empty, or have one byte which is the stop command, then the nack status can be ignored. */ + if ((xfer->dataSize != 0U) && + ((txCount == 0U) || ((txCount == 1U) && (handle->state == (uint8_t)kWaitForCompletionState) && + ((xfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U)))) + { + status &= ~(uint32_t)kLPI2C_MasterNackDetectFlag; + } + } + + result = LPI2C_MasterCheckAndClearError(I2Cx, status); + + if (kStatus_Success == result) + { + /* Compute room in tx fifo */ + txCount = txFifoSize - txCount; + + while (!state_complete) + { + /* Execute the state. */ + switch (handle->state) + { + case (uint8_t)kSendCommandState: + /* Make sure there is room in the tx fifo for the next command. */ + if (0U == txCount--) + { + state_complete = TRUE; + break; + } + + /* Issue command. buf is a uint8_t* pointing at the uint16 command array. */ + sendval = ((uint16_t)handle->buf[0]) | (((uint16_t)handle->buf[1]) << 8U); + I2Cx->MTDR = sendval; + handle->buf++; + handle->buf++; + + /* Count down until all commands are sent. */ + if (--handle->remainingBytes == 0U) + { + /* Choose next state and set up buffer pointer and count. */ + if (0U != xfer->dataSize) + { + /* Either a send or receive transfer is next. */ + handle->state = (uint8_t)kTransferDataState; + handle->buf = (uint8_t *)xfer->data; + handle->remainingBytes = (uint16_t)xfer->dataSize; + if (xfer->direction == I2C_MODE_READ) + { + /* Disable TX interrupt */ + LPI2C_MasterDisableInterrupts(I2Cx, (uint32_t)kLPI2C_MasterTxReadyFlag); + /* Issue command to receive data. A single write to MTDR can issue read operation of + 0xFFU + 1 byte of data at most, so when the dataSize is larger than 0x100U, push + multiple read commands to MTDR until dataSize is reached. */ + size_t tmpRxSize = xfer->dataSize; + while (tmpRxSize != 0U) + { + LPI2C_MasterGetFifoCounts(I2Cx, NULL, &txCount); + while (txFifoSize == txCount) + { + LPI2C_MasterGetFifoCounts(I2Cx, NULL, &txCount); + } + + if (tmpRxSize > 256U) + { + I2Cx->MTDR = (uint32_t)(kRxDataCmd) | (uint32_t)I2C_MTDR_DATA(0xFFU); + tmpRxSize -= 256U; + } + else + { + I2Cx->MTDR = (uint32_t)(kRxDataCmd) | (uint32_t)I2C_MTDR_DATA(tmpRxSize - 1U); + tmpRxSize = 0U; + } + } + } + } + else + { + /* No transfer, so move to stop state. */ + handle->state = (uint8_t)kStopState; + } + } + break; + + case (uint8_t)kIssueReadCommandState: + /* Make sure there is room in the tx fifo for the read command. */ + if (0U == txCount--) + { + state_complete = TRUE; + break; + } + + I2Cx->MTDR = (uint32_t)kRxDataCmd | I2C_MTDR_DATA(xfer->dataSize - 1U); + + /* Move to transfer state. */ + handle->state = (uint8_t)kTransferDataState; + if (xfer->direction == I2C_MODE_READ) + { + /* Disable TX interrupt */ + LPI2C_MasterDisableInterrupts(I2Cx, (uint32_t)kLPI2C_MasterTxReadyFlag); + } + break; + + case (uint8_t)kTransferDataState: + if (xfer->direction == I2C_MODE_WRITE) + { + /* Make sure there is room in the tx fifo. */ + if (0U == txCount--) + { + state_complete = TRUE; + break; + } + + /* Put byte to send in fifo. */ + I2Cx->MTDR = *(handle->buf)++; + } + else + { + /* XXX handle receive sizes > 256, use kIssueReadCommandState */ + /* Make sure there is data in the rx fifo. */ + if (0U == rxCount--) + { + state_complete = TRUE; + break; + } + + /* Read byte from fifo. */ + *(handle->buf)++ = (uint8_t)(I2Cx->MRDR & I2Cx_MRDR_DATA_Msk); + } + + /* Move to stop when the transfer is done. */ + if (--handle->remainingBytes == 0U) + { + if (xfer->direction == I2C_MODE_WRITE) + { + state_complete = TRUE; + } + handle->state = (uint8_t)kStopState; + } + break; + + case (uint8_t)kStopState: + /* Only issue a stop transition if the caller requested it. */ + if ((xfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U) + { + /* Make sure there is room in the tx fifo for the stop command. */ + if (0U == txCount--) + { + state_complete = TRUE; + break; + } + + I2Cx->MTDR = (uint32_t)kStopCmd; + } + else + { + /* If all data is read and no stop flag is required to send, we are done. */ + if (xfer->direction == I2C_MODE_READ) + { + *isDone = TRUE; + } + state_complete = TRUE; + } + handle->state = (uint8_t)kWaitForCompletionState; + break; + + case (uint8_t)kWaitForCompletionState: + if ((xfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U) + { + /* We stay in this state until the stop state is detected. */ + if (0U != (status & (uint32_t)kLPI2C_MasterStopDetectFlag)) + { + *isDone = TRUE; + } + } + else + { + /* If all data is pushed to FIFO and no stop flag is required to send, we need to make sure they + are all send out to bus. */ + if ((xfer->direction == I2C_MODE_WRITE) && ((I2Cx->MFIFOSR & I2Cx_MFIFOSR_TXCNT_Msk) == 0U)) + { + /* We stay in this state until the data is sent out to bus. */ + *isDone = TRUE; + } + } + state_complete = TRUE; + break; + default: + assert_param(FALSE); + break; + } + } + } + return result; +} + +/** + * @brief 初始化I2C传输状态机 + * + * 该函数用于初始化I2C传输状态机，根据传入的参数设置传输的状态、数据和地址等信息。 + * + * @param handle I2C传输句柄指针 + */ +static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle) +{ + lpi2c_master_transfer_t *xfer = &handle->transfer; + + /* Handle no start option. */ + if (0U != (xfer->flags & (uint32_t)kLPI2C_TransferNoStartFlag)) + { + if (xfer->direction == I2C_MODE_READ) + { + /* Need to issue read command first. */ + handle->state = (uint8_t)kIssueReadCommandState; + } + else + { + /* Start immediately in the data transfer state. */ + handle->state = (uint8_t)kTransferDataState; + } + + handle->buf = (uint8_t *)xfer->data; + handle->remainingBytes = (uint16_t)xfer->dataSize; + } + else + { + uint16_t *cmd = (uint16_t *)&handle->commandBuffer; + uint32_t cmdCount = 0U; + + /* Initial direction depends on whether a subaddress was provided, and of course the actual */ + /* data transfer direction. */ + I2C_ModeTypeDef direction = (0U != xfer->subaddressSize) ? I2C_MODE_WRITE : xfer->direction; + + /* Start command. */ + if(xfer->slaveAddress & I2C_SLAVE_ADDR10B_MSB_MASK) + { + // 10-bit slave address + cmd[cmdCount++] = + (uint16_t)kStartCmd | (uint16_t)((uint16_t)((((uint16_t)xfer->slaveAddress & I2C_SLAVE_ADDR10B_MSB_MASK) >> (8 - 1)) | I2C_SLAVE_ADDR10B_MSB) | (uint16_t)direction); + cmd[cmdCount++] = + (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress & I2C_SLAVE_ADDR10B_LSB_MASK)); + } + else + { + // 7-bit slave address + cmd[cmdCount++] = + (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)direction); + } + + /* Subaddress, MSB first. */ + if (0U != xfer->subaddressSize) + { + uint32_t subaddressRemaining = xfer->subaddressSize; + while (0U != (subaddressRemaining--)) + { + uint8_t subaddressByte = (uint8_t)((xfer->subaddress >> (8U * subaddressRemaining)) & 0xffU); + cmd[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling. */ + if ((0U != xfer->dataSize) && (xfer->direction == I2C_MODE_READ)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == I2C_MODE_WRITE) + { + if(xfer->slaveAddress & I2C_SLAVE_ADDR10B_MSB_MASK) + { + // 10-bit slave address + cmd[cmdCount++] = + (uint16_t)kStartCmd | (uint16_t)((uint16_t)((((uint16_t)xfer->slaveAddress & I2C_SLAVE_ADDR10B_MSB_MASK) >> (8 - 1)) | I2C_SLAVE_ADDR10B_MSB) | (uint16_t)I2C_MODE_READ); + } + else + { + // 7-bit slave address + cmd[cmdCount++] = (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)I2C_MODE_READ); + } + } + } + + /* Set up state machine for transferring the commands. */ + handle->state = (uint8_t)kSendCommandState; + handle->remainingBytes = (uint16_t)cmdCount; + handle->buf = (uint8_t *)&handle->commandBuffer; + } +} + +/** + * @brief 以非阻塞方式执行I2C主机传输 + * + * 此函数用于以非阻塞方式通过I2C主机接口执行数据传输。它可以处理读操作和写操作。 + * + * @param I2Cx I2C模块的外设基地址 + * @param handle 指向I2C主机句柄的指针，该句柄包含传输的状态信息 + * @param transfer 指向包含传输配置的指针 + * + * @return 返回操作的状态码。可能的状态码包括： + * - kStatus_Success: 操作成功 + * - kStatus_InvalidArgument: 参数无效，例如传输的数据大小超出限制 + * - kStatus_LPI2C_Busy: I2C总线正在忙，无法启动新的传输 + */ +status_t LPI2C_MasterTransferNonBlocking(I2C_TypeDef *I2Cx, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_t *transfer) +{ + assert_param(NULL != handle); + assert_param(NULL != transfer); + assert_param(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + status_t result; + + /* Check transfer data size in read operation. */ + if ((transfer->direction == I2C_MODE_READ) && + (transfer->dataSize > (256U * (uint32_t)FSL_FEATURE_I2C_FIFO_SIZEn(I2Cx)))) + { + return kStatus_InvalidArgument; + } + + /* Return busy if another transaction is in progress. */ + if (handle->state != (uint8_t)kIdleState) + { + result = kStatus_LPI2C_Busy; + } + else + { + result = LPI2C_CheckForBusyBus(I2Cx); + } + + if ((status_t)kStatus_Success == result) + { + /* Disable LPI2C IRQ sources while we configure stuff. */ + LPI2C_MasterDisableInterrupts(I2Cx, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Reset FIFO in case there are data. */ + I2Cx->MCR0 |= I2Cx_MCR0_RXFIFORST_Msk | I2Cx_MCR0_TXFIFORST_Msk; + + /* Save transfer into handle. */ + handle->transfer = *transfer; + + /* Generate commands to send. */ + LPI2C_InitTransferStateMachine(handle); + + /* Clear all flags. */ + I2C_MasterClearFlag(I2Cx, (uint32_t)kLPI2C_MasterClearFlags); + + /* Turn off auto-stop option. */ + I2Cx->MCR2 &= ~I2Cx_MCR2_AUTOSTOP_Msk; + + /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + LPI2C_MasterEnableInterrupts(I2Cx, (uint32_t)kLPI2C_MasterIrqFlags); + } + + return result; +} + +/** + * @brief 获取I2C主机在传输过程中已传输的字节数 + * + * 该函数用于获取I2C主机在传输过程中已经传输的字节数。 + * + * @param I2Cx I2C模块的指针 + * @param handle I2C主机传输句柄 + * @param count 指向一个size_t类型的指针，用于存储已传输的字节数 + * + * @return 返回操作状态，成功时返回kStatus_Success，失败时返回相应的错误码 + * - kStatus_Success: 操作成功 + * - kStatus_InvalidArgument: 输入参数无效 + * - kStatus_NoTransferInProgress: 当前没有正在进行的传输 + */ +status_t LPI2C_MasterTransferGetCount(I2C_TypeDef *I2Cx, lpi2c_master_handle_t *handle, size_t *count) +{ + status_t result = kStatus_Success; + + assert_param(NULL != handle); + + if (NULL == count) + { + result = kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + else if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + result = kStatus_NoTransferInProgress; + } + else + { + uint8_t state; + uint16_t remainingBytes; + uint32_t dataSize; + + /* Cache some fields with IRQs disabled. This ensures all field values */ + /* are synchronized with each other during an ongoing transfer. */ + uint32_t irqs = LPI2C_MasterGetEnabledInterrupts(I2Cx); + LPI2C_MasterDisableInterrupts(I2Cx, irqs); + state = handle->state; + remainingBytes = handle->remainingBytes; + dataSize = handle->transfer.dataSize; + LPI2C_MasterEnableInterrupts(I2Cx, irqs); + + /* Get transfer count based on current transfer state. */ + switch (state) + { + case (uint8_t)kIdleState: + case (uint8_t)kSendCommandState: + case (uint8_t) + kIssueReadCommandState: /* XXX return correct value for this state when >256 reads are supported */ + *count = 0; + break; + + case (uint8_t)kTransferDataState: + *count = dataSize - remainingBytes; + break; + + case (uint8_t)kStopState: + case (uint8_t)kWaitForCompletionState: + default: + *count = dataSize; + break; + } + } + + return result; +} + +/** + * @brief 中止I2C主机传输 + * + * 中止I2C主机传输，并重置相关状态。 + * + * @param I2Cx I2C模块指针 + * @param handle I2C主机句柄指针 + */ +void LPI2C_MasterTransferAbort(I2C_TypeDef *I2Cx, lpi2c_master_handle_t *handle) +{ + if (handle->state != (uint8_t)kIdleState) + { + /* Disable internal IRQ enables. */ + LPI2C_MasterDisableInterrupts(I2Cx, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Reset fifos. */ + I2Cx->MCR0 |= I2Cx_MCR0_RXFIFORST_Msk | I2Cx_MCR0_TXFIFORST_Msk; + + /* If master is still busy and has not send out stop signal yet. */ + if ((LPI2C_MasterGetStatusFlags(I2Cx) & ((uint32_t)kLPI2C_MasterStopDetectFlag | + (uint32_t)kLPI2C_MasterBusyFlag)) == (uint32_t)kLPI2C_MasterBusyFlag) + { + /* Send a stop command to finalize the transfer. */ + I2Cx->MTDR = (uint32_t)kStopCmd; + } + + /* Reset handle. */ + handle->state = (uint8_t)kIdleState; + } +} + +/** + * @brief 处理LPI2C主模式传输的中断请求 + * + * 该函数处理LPI2C主模式传输的中断请求，调用状态机处理传输，并根据处理结果进行相应的操作。 + * + * @param I2Cx LPI2C模块指针 + * @param lpi2cMasterHandle LPI2C主模式句柄指针 + */ +void LPI2C_MasterTransferHandleIRQ(I2C_TypeDef *I2Cx, void *lpi2cMasterHandle) +{ + assert_param(lpi2cMasterHandle != NULL); + + lpi2c_master_handle_t *handle = (lpi2c_master_handle_t*) lpi2cMasterHandle; + boolean_t isDone = FALSE; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL != handle) + { + if (handle->state != (uint8_t)kIdleState) + { + result = LPI2C_RunTransferStateMachine(I2Cx, handle, &isDone); + + if ((result != kStatus_Success) || isDone) + { + /* Handle error, terminate xfer */ + if (result != kStatus_Success) + { + LPI2C_MasterTransferAbort(I2Cx, handle); + } + + /* Disable internal IRQ enables. */ + LPI2C_MasterDisableInterrupts(I2Cx, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Set handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Invoke callback. */ + if (NULL != handle->completionCallback) + { + handle->completionCallback(I2Cx, handle, result, handle->userData); + } + } + } + } +} + +/** + * @brief I2C从设备去初始化函数 + * + * 该函数用于停止I2C从设备并将其关闭。 + * + * @param I2Cx I2C外设指针，指向需要停止并关闭的I2C外设。 + */ +void I2C_SlaveDeinit(I2C_TypeDef *I2Cx) +{ + I2C_SlaveSoftReset(I2Cx); + + I2C_DeInit(I2Cx); +} + +/** + * @brief 检查并清除LPI2C从机错误 + * + * 检查指定I2C设备上的从机错误标志，并清除这些错误。 + * + * @param I2Cx 指向I2C设备的指针 + * @param flags 需要检查的错误标志位掩码 + * + * @return 如果检测到错误，则返回相应的错误状态码；否则返回kStatus_Success + */ +static status_t LPI2C_SlaveCheckAndClearError(I2C_TypeDef *I2Cx, uint32_t flags) +{ + status_t result = kStatus_Success; + + flags &= (uint32_t)kLPI2C_SlaveErrorFlags; + if (0U != flags) + { + if (0U != (flags & (uint32_t)kLPI2C_SlaveBitErrFlag)) + { + result = kStatus_LPI2C_BitError; + } + else if (0U != (flags & (uint32_t)kLPI2C_SlaveFifoErrFlag)) + { + result = kStatus_LPI2C_FifoError; + } + else + { + ; /* Intentional empty */ + } + + /* Clear the errors. */ + I2C_SlaveClearFlag(I2Cx, flags); + } + else + { + ; /* Intentional empty */ + } + + return result; +} + +/** + * @brief I2C从设备以查询方式发送数据 + * + * 使用I2C从设备发送数据。此函数会尝试将数据从缓冲区txBuff发送出去，直到所有数据被发送完毕或发生错误。 + * + * @param I2Cx I2C模块指针 + * @param txBuff 待发送数据的缓冲区指针 + * @param txSize 待发送数据的字节数 + * @param actualTxSize 实际发送的字节数指针（可以为NULL） + * + * @return 发送状态，成功返回kStatus_Success，否则返回相应的错误码 + */ +status_t LPI2C_SlaveSend(I2C_TypeDef *I2Cx, void *txBuff, size_t txSize, size_t *actualTxSize) +{ + status_t result = kStatus_Success; + uint8_t *buf = (uint8_t *)txBuff; + size_t remaining = txSize; + + assert_param(NULL != txBuff); + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + /* Clear stop flag. */ + I2C_SlaveClearFlag(I2Cx, + (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag); + + while (0U != remaining) + { + uint32_t flags; + + /* Wait until we can transmit. */ + do + { + /* Check for errors */ + flags = LPI2C_SlaveGetStatusFlags(I2Cx); + result = LPI2C_SlaveCheckAndClearError(I2Cx, flags); + if (kStatus_Success != result) + { + if (NULL != actualTxSize) + { + *actualTxSize = txSize - remaining; + } + break; + } +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == (flags & ((uint32_t)kLPI2C_SlaveTxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | + (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && + (0U != waitTimes)); + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#else + } while (0U == (flags & ((uint32_t)kLPI2C_SlaveTxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | + (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))); +#endif + + if (kStatus_Success != result) + { + break; + } + + /* Send a byte. */ + if (0U != (flags & (uint32_t)kLPI2C_SlaveTxReadyFlag)) + { + I2Cx->STDR = *buf++; + --remaining; + } + + /* Exit loop if we see a stop or restart in transfer*/ + if ((0U != (flags & ((uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && + (remaining != 0U)) + { + I2C_SlaveClearFlag( + I2Cx, (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag); + break; + } + } + + if (NULL != actualTxSize) + { + *actualTxSize = txSize - remaining; + } + + return result; +} + +/** + * @brief I2C从设备以查询方式接收数据 + * + * 该函数指定的I2C从设备接收指定数量的字节数据。 + * + * @param I2Cx I2C设备指针，指向要操作的I2C设备。 + * @param rxBuff 接收数据的缓冲区指针。 + * @param rxSize 要接收的数据字节数。 + * @param actualRxSize 实际接收到的数据字节数指针（可选）。 + * + * @return 接收操作的状态。成功返回kStatus_Success，失败返回相应的错误代码。 + */ +status_t LPI2C_SlaveReceive(I2C_TypeDef *I2Cx, void *rxBuff, size_t rxSize, size_t *actualRxSize) +{ + status_t result = kStatus_Success; + uint8_t *buf = (uint8_t *)rxBuff; + size_t remaining = rxSize; + + assert_param(NULL != rxBuff); + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + /* Clear stop flag. */ + I2C_SlaveClearFlag(I2Cx, + (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag); + + while (0U != remaining) + { + uint32_t flags; + + /* Wait until we can receive. */ + do + { + /* Check for errors */ + flags = LPI2C_SlaveGetStatusFlags(I2Cx); + result = LPI2C_SlaveCheckAndClearError(I2Cx, flags); + if (kStatus_Success != result) + { + if (NULL != actualRxSize) + { + *actualRxSize = rxSize - remaining; + } + break; + } +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == (flags & ((uint32_t)kLPI2C_SlaveRxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | + (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && + (0U != waitTimes)); + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#else + } while (0U == (flags & ((uint32_t)kLPI2C_SlaveRxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | + (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))); +#endif + + if ((status_t)kStatus_Success != result) + { + break; + } + + /* Receive a byte. */ + if (0U != (flags & (uint32_t)kLPI2C_SlaveRxReadyFlag)) + { + *buf++ = (uint8_t)(I2Cx->SRDR & I2Cx_SRDR_DATA_Msk); + --remaining; + } + + /* Exit loop if we see a stop or restart */ + if ((0U != (flags & ((uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && + (remaining != 0U)) + { + I2C_SlaveClearFlag( + I2Cx, (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag); + break; + } + } + + if (NULL != actualRxSize) + { + *actualRxSize = rxSize - remaining; + } + + return result; +} + +/** + * @brief 创建I2C从设备传输句柄 + * + * 创建一个I2C从设备传输句柄，并初始化相关参数。 + * + * @param I2Cx I2C设备指针，指向一个I2C_TypeDef类型的结构体，表示要使用的I2C设备。 + * @param handle 指向一个lpi2c_slave_handle_t类型的指针，用于存储句柄信息。 + * @param callback 指向一个lpi2c_slave_transfer_callback_t类型的回调函数，用于处理传输完成后的回调。 + * @param userData 用户自定义数据指针，可以在回调函数中使用。 + */ +void LPI2C_SlaveTransferCreateHandle(I2C_TypeDef *I2Cx, + lpi2c_slave_handle_t *handle, + lpi2c_slave_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert_param(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = LPI2C_GetInstance(I2Cx); + + /* Save base and instance. */ + handle->callback = callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_lpi2cSlaveHandle[instance] = handle; + + /* Set irq handler. */ + s_lpi2cSlaveIsr = LPI2C_SlaveTransferHandleIRQ; + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + LPI2C_SlaveDisableInterrupts(I2Cx, (uint32_t)kLPI2C_SlaveIrqFlags); + //(void)EnableIRQ(kLpi2cIrqs[instance]); + NVIC_ClearPendingIRQ(kLpi2cIrqs[instance]); + NVIC_EnableIRQ(kLpi2cIrqs[instance]); + + /* Nack by default. */ + I2Cx->STAR = I2Cx_STAR_TXNACK_Msk; +} + +/** + * @brief 以非阻塞方式执行从设备I2C传输 + * + * 该函数用于以非阻塞方式执行从设备的I2C传输操作。如果当前没有正在进行的传输，函数将配置传输，并启动传输过程。 + * 如果当前有传输正在进行或总线已被其他设备占用，则返回相应的错误状态。 + * + * @param I2Cx I2C模块指针，指向要使用的I2C模块的寄存器地址 + * @param handle 从设备句柄，指向存储从设备配置和状态的结构体 + * @param eventMask 事件掩码，指定需要监听的事件类型 + * + * @return 函数执行状态。如果成功，则返回kStatus_Success；如果失败，则返回相应的错误代码 + */ +status_t LPI2C_SlaveTransferNonBlocking(I2C_TypeDef *I2Cx, lpi2c_slave_handle_t *handle, uint32_t eventMask) +{ + status_t result = kStatus_Success; + + assert_param(NULL != handle); + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + result = kStatus_LPI2C_Busy; + } + else + { + /* Return an error if the bus is already in use not by us. */ + uint32_t status = LPI2C_SlaveGetStatusFlags(I2Cx); + if ((0U != (status & (uint32_t)kLPI2C_SlaveBusBusyFlag)) && (0U == (status & (uint32_t)kLPI2C_SlaveBusyFlag))) + { + result = kStatus_LPI2C_Busy; + } + } + + if ((status_t)kStatus_Success == result) + { + /* Disable LPI2C IRQ sources while we configure stuff. */ + LPI2C_SlaveDisableInterrupts(I2Cx, (uint32_t)kLPI2C_SlaveIrqFlags); + + /* Clear transfer in handle. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Record that we're busy. */ + handle->isBusy = TRUE; + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | (uint32_t)kLPI2C_SlaveTransmitEvent | (uint32_t)kLPI2C_SlaveReceiveEvent; + + /* Ack by default. */ + I2Cx->STAR = 0U; + + /* Clear all flags. */ + I2C_SlaveClearFlag(I2Cx, (uint32_t)kLPI2C_SlaveClearFlags); + + /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + LPI2C_SlaveEnableInterrupts(I2Cx, (uint32_t)kLPI2C_SlaveIrqFlags); + } + + return result; +} + +/** + * @brief 获取 I2C 从设备传输的数据量 + * + * 此函数用于获取 I2C 从设备当前传输的数据量。 + * + * @param I2Cx I2C 外设的基地址指针 + * @param handle I2C 从设备的句柄指针 + * @param count 用于存储获取到的传输数据量的指针 + * + * @return 函数执行状态。 + * - kStatus_Success: 成功获取传输数据量。 + * - kStatus_InvalidArgument: 传入参数无效。 + * - kStatus_NoTransferInProgress: 当前没有传输正在进行。 + */ +status_t LPI2C_SlaveTransferGetCount(I2C_TypeDef *I2Cx, lpi2c_slave_handle_t *handle, size_t *count) +{ + status_t status = kStatus_Success; + + assert_param(NULL != handle); + + if (count == NULL) + { + status = kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + else if (!handle->isBusy) + { + *count = 0; + status = kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + else + { + *count = handle->transferredCount; + } + + return status; +} + +/** + * @brief 终止LPI2C从机传输 + * + * 终止指定的LPI2C从机传输。 + * + * @param I2Cx LPI2C模块指针 + * @param handle 从机传输句柄指针 + */ +void LPI2C_SlaveTransferAbort(I2C_TypeDef *I2Cx, lpi2c_slave_handle_t *handle) +{ + assert_param(NULL != handle); + + /* Return idle if no transaction is in progress. */ + if (handle->isBusy) + { + /* Disable LPI2C IRQ sources. */ + LPI2C_SlaveDisableInterrupts(I2Cx, (uint32_t)kLPI2C_SlaveIrqFlags); + + /* Nack by default. */ + I2Cx->STAR = I2Cx_STAR_TXNACK_Msk; + + /* Reset transfer info. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* We're no longer busy. */ + handle->isBusy = FALSE; + } +} + +/** + * @brief 处理I2C从机传输中断 + * + * 处理I2C从机传输中断，根据中断状态进行相应的处理。 + * + * @param I2Cx I2C模块指针 + * @param handle I2C从机传输句柄指针 + */ +void LPI2C_SlaveTransferHandleIRQ(I2C_TypeDef *I2Cx, lpi2c_slave_handle_t *handle) +{ + uint32_t flags; + lpi2c_slave_transfer_t *xfer; + + /* Check for a valid handle in case of a spurious interrupt. */ + if (NULL != handle) + { + xfer = &handle->transfer; + + /* Get status flags. */ + flags = LPI2C_SlaveGetStatusFlags(I2Cx); + + if (0U != (flags & ((uint32_t)kLPI2C_SlaveBitErrFlag | (uint32_t)kLPI2C_SlaveFifoErrFlag))) + { + xfer->event = kLPI2C_SlaveCompletionEvent; + xfer->completionStatus = LPI2C_SlaveCheckAndClearError(I2Cx, flags); + + if ((0U != (handle->eventMask & (uint32_t)kLPI2C_SlaveCompletionEvent)) && (NULL != handle->callback)) + { + handle->callback(I2Cx, xfer, handle->userData); + } + } + else + { + if (0U != + (flags & (((uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag) | ((uint32_t)kLPI2C_SlaveStopDetectFlag)))) + { + xfer->event = (0U != (flags & (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag)) ? + kLPI2C_SlaveRepeatedStartEvent : + kLPI2C_SlaveCompletionEvent; + xfer->receivedAddress = 0U; + xfer->completionStatus = kStatus_Success; + xfer->transferredCount = handle->transferredCount; + + if (xfer->event == kLPI2C_SlaveCompletionEvent) + { + handle->isBusy = FALSE; + } + + if (handle->wasTransmit) + { + /* Subtract one from the transmit count to offset the fact that LPI2C asserts the */ + /* tx flag before it sees the nack from the master-receiver, thus causing one more */ + /* count that the master actually receives. */ + --xfer->transferredCount; + handle->wasTransmit = FALSE; + } + + /* Clear the flag. */ + I2C_SlaveClearFlag(I2Cx, flags & ((uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag | + (uint32_t)kLPI2C_SlaveStopDetectFlag)); + + /* Revert to sending an Ack by default, in case we sent a Nack for receive. */ + I2Cx->STAR = 0U; + + if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback)) + { + handle->callback(I2Cx, xfer, handle->userData); + } + + if (0U != (flags & (uint32_t)kLPI2C_SlaveStopDetectFlag)) + { + /* Clean up transfer info on completion, after the callback has been invoked. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + } + } + if (0U != (flags & (uint32_t)kLPI2C_SlaveAddressValidFlag)) + { + xfer->event = kLPI2C_SlaveAddressMatchEvent; + xfer->receivedAddress = (uint8_t)(I2Cx->SASR & I2Cx_SASR_RADDR_Msk); + + /* Update handle status to busy because slave is addressed. */ + handle->isBusy = TRUE; + if ((0U != (handle->eventMask & (uint32_t)kLPI2C_SlaveAddressMatchEvent)) && (NULL != handle->callback)) + { + handle->callback(I2Cx, xfer, handle->userData); + } + } + if (0U != (flags & (uint32_t)kLPI2C_SlaveTransmitAckFlag)) + { + xfer->event = kLPI2C_SlaveTransmitAckEvent; + + if ((0U != (handle->eventMask & (uint32_t)kLPI2C_SlaveTransmitAckEvent)) && (NULL != handle->callback)) + { + handle->callback(I2Cx, xfer, handle->userData); + } + } + + /* Handle transmit and receive. */ + if (0U != (flags & (uint32_t)kLPI2C_SlaveTxReadyFlag)) + { + handle->wasTransmit = TRUE; + + /* If we're out of data, invoke callback to get more. */ + if ((NULL == xfer->data) || (0U == xfer->dataSize)) + { + xfer->event = kLPI2C_SlaveTransmitEvent; + if (NULL != handle->callback) + { + handle->callback(I2Cx, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + handle->transferredCount = 0U; + } + + /* Transmit a byte. */ + if ((NULL != xfer->data) && (0U != xfer->dataSize)) + { + I2Cx->STDR = *xfer->data++; + --xfer->dataSize; + ++handle->transferredCount; + } + } + if (0U != (flags & (uint32_t)kLPI2C_SlaveRxReadyFlag)) + { + /* If we're out of room in the buffer, invoke callback to get another. */ + if ((NULL == xfer->data) || (0U == xfer->dataSize)) + { + xfer->event = kLPI2C_SlaveReceiveEvent; + if (NULL != handle->callback) + { + handle->callback(I2Cx, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + handle->transferredCount = 0U; + } + + /* Receive a byte. */ + if ((NULL != xfer->data) && (0U != xfer->dataSize)) + { + *xfer->data++ = (uint8_t)I2Cx->SRDR; + --xfer->dataSize; + ++handle->transferredCount; + } + else + { + /* We don't have any room to receive more data, so send a nack. */ + I2Cx->STAR = I2Cx_STAR_TXNACK_Msk; + } + } + } + } +} + +/** + * @brief 通用I2C中断处理函数 + * + * 此函数用于处理I2C总线的中断请求。根据I2C的工作模式（主模式或从模式），调用相应的中断服务程序。 + * + * @param I2Cx 指向I2C模块的指针 + * @param instance I2C实例编号 + */ +void LPI2C_CommonIRQHandler(I2C_TypeDef *I2Cx, uint32_t instance) +{ + /* Check for master IRQ. */ + if ((0U != (I2Cx->MCR0 & I2Cx_MCR0_MEN_Msk)) && (NULL != s_lpi2cMasterIsr)) + { + /* Master mode. */ + s_lpi2cMasterIsr(I2Cx, s_lpi2cMasterHandle[instance]); + } + + /* Check for slave IRQ. */ + if ((0U != (I2Cx->SCR0 & I2Cx_SCR0_SEN_Msk)) && (NULL != s_lpi2cSlaveIsr)) + { + /* Slave mode. */ + s_lpi2cSlaveIsr(I2Cx, s_lpi2cSlaveHandle[instance]); + } + +} + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_lptim.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_lptim.c new file mode 100644 index 0000000..2dd624d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_lptim.c @@ -0,0 +1,258 @@ +/** + * @file cw32l012_lptim.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2022 + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_lptim.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief LPTIM复位 + * + */ +void LPTIM_DeInit(void) +{ + CW_SYSCTRL->APBRST2_f.LPTIM = 0; + CW_SYSCTRL->APBRST2_f.LPTIM = 1; +} + +/** + * @brief LPTIM 初始化函数 + * + * @param LPTIM_InitStruct + */ +void LPTIM_Init(LPTIM_InitTypeDef* LPTIM_InitStruct) +{ + assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->LPTIM_ClockSource)); + assert_param(IS_LPTIM_COUNTER_MODE(LPTIM_InitStruct->LPTIM_CounterMode)); + assert_param(IS_LPTIM_PRS(LPTIM_InitStruct->LPTIM_Prescaler)); + + CW_LPTIM->ARR = LPTIM_InitStruct->LPTIM_Period; + CW_LPTIM->CFGR = LPTIM_InitStruct->LPTIM_Prescaler | LPTIM_InitStruct->LPTIM_ClockSource | LPTIM_InitStruct->LPTIM_CounterMode; +} + +/** + * @brief 设置预分配系数 + * + * @param Prescaler LPTIM_PRS_DIV1 LPTIM_PRS_DIV2 LPTIM_PRS_DIV4 LPTIM_PRS_DIV8 + * LPTIM_PRS_DIV16 LPTIM_PRS_DIV32 LPTIM_PRS_DIV64 LPTIM_PRS_DIV128 + */ +void LPTIM_PrescalerConfig(uint32_t Prescaler) +{ + assert_param(IS_LPTIM_PRS(Prescaler)); + + REGBITS_MODIFY(CW_LPTIM->CFGR, LPTIM_CFGR_PRS_Msk, Prescaler); +} + +/** + * @brief 设置LPTIM的计数模式为定时模式或计数模式 + * + * @param LPTIM_CounterMode LPTIM_COUNTER_MODE_TIME LPTIM_COUNTER_MODE_COUNT + * + */ +void LPTIM_CounterModeConfig(uint32_t LPTIM_CounterMode) +{ + assert_param(IS_LPTIM_COUNTER_MODE(LPTIM_CounterMode)); + REGBITS_MODIFY(CW_LPTIM->CFGR, LPTIM_CFGR_COUNTMD_Msk, LPTIM_CounterMode); +} + +/** + * @brief 设置LPTIM的ARR值与更新方式 + * + * @param Autoreload 0x0000~0xFFFF + * @param ReloadMode LPTIM_RELOAD_MODE_UPDATE LPTIM_RELOAD_MODE_IMMEDIATE + */ +void LPTIM_SetAutoreload(uint16_t Autoreload, uint32_t ReloadMode) +{ + assert_param(IS_LPTIM_RELOAD_MODE(ReloadMode)); + + CW_LPTIM->ARR = Autoreload; + REGBITS_MODIFY(CW_LPTIM->CFGR, LPTIM_CFGR_PRELOAD_Msk, ReloadMode); +} + +/** + * @brief 获取LPTIM的CNT值, 连续两次读到相同值才认为读出数据 + * + */ +uint32_t LPTIM_GetCounter(void) +{ + uint32_t TmpCNT = 0; + do + { + TmpCNT = CW_LPTIM->CNT; + } + while (TmpCNT != CW_LPTIM->CNT); + + return TmpCNT; +} + +/** + * @brief 获取LPTIM的分频值 + * + * @return uint8_t + */ +uint8_t TIM_GetPrescaler(void) +{ + return CW_LPTIM->CFGR_f.PRS; +} + +/** + * @brief 设置LPTIM工作模式为单脉冲模式或连续运行模式 + * + * @param LPTIM_OPMode LPTIM_OPERATION_SINGLE LPTIM_OPERATION_REPETITIVE + */ +void LPTIM_SelectOnePulseMode(uint16_t LPTIM_OPMode) +{ + assert_param(IS_LPTIM_OPERATION_MODE(LPTIM_OPMode)); + REGBITS_MODIFY(CW_LPTIM->CR0, LPTIM_CR0_CNTSTART_Msk | LPTIM_CR0_SNGSTART_Msk, LPTIM_OPMode); + +} + +/** + * @brief 打开或关闭LPTIM + * + * @param NewState + */ +void LPTIM_Cmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + CW_LPTIM->CR0_f.EN = NewState; +} + +/** + * @brief 配置内部时钟源 + * + * @param LPTIM_ICLK_Source LPTIM_ICLK_PCLK LPTIM_ICLK_LSE LPTIM_ICLK_LSI + */ +void LPTIM_InternalClockConfig(uint32_t LPTIM_ICLK_Source) +{ + assert_param(IS_LPTIM_ICLK(LPTIM_ICLK_Source)); + + REGBITS_MODIFY(CW_LPTIM->CFGR, LPTIM_CFGR_ICLKSRC_Msk, LPTIM_ICLK_Source); +} + +/** + * @brief 设置PWM输出 + * + * @param Period 周期 + * @param Pulse 脉宽 + * @param Polarity 波形极性 + */ +void LPTIM_PWMStart(uint32_t Period, uint32_t Pulse, uint32_t Polarity) +{ + assert_param(IS_LPTIM_PWM_POL(Polarity)); + + CW_LPTIM->ARR = Period; + CW_LPTIM->CMP = Pulse; + + REGBITS_MODIFY(CW_LPTIM->CFGR, LPTIM_CFGR_WAVPOL_Msk, Polarity); + CW_LPTIM->CFGR_f.WAVE = 0; + LPTIM_Cmd(ENABLE); + LPTIM_SelectOnePulseMode(LPTIM_OPERATION_REPETITIVE); +} + + +/** + * @brief 设置LPTIM的中断使能或禁能，可同时设置多个中断使能位，用“|”连接 + * + * @param LPTIM_IT LPTIM_IT_CMPM LPTIM_IT_ARRM LPTIM_IT_EXTTRIG LPTIM_IT_CMPOK + * LPTIM_IT_ARROK LPTIM_IT_UP LPTIM_IT_DOWN + * @param NewState ENABLE DISABLE + */ +void LPTIM_ITConfig(uint32_t LPTIM_IT, FunctionalState NewState) +{ + assert_param(IS_LPTIM_IT(LPTIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + CW_LPTIM->IER |= LPTIM_IT; + } + else + { + CW_LPTIM->IER &= ~LPTIM_IT; + } +} + +/** + * @brief 获得LPTIM的状态位 + * + * @param LPTIM_FLAG LPTIM_FLAG_CMPM LPTIM_FLAG_ARRM LPTIM_FLAG_EXTTRIG + * LPTIM_FLAG_CMPOK LPTIM_FLAG_ARROK LPTIM_FLAG_UP LPTIM_FLAG_DOWN + * @return FlagStatus SET RESET + */ +FlagStatus LPTIM_GetFlagStatus(uint32_t LPTIM_FLAG) +{ + assert_param(IS_LPTIM_GET_FLAG(LPTIM_FLAG)); + + return (FlagStatus)(!!(CW_LPTIM->ISR & LPTIM_FLAG)); +} + +/** + * @brief 清除LPTIM的标志位 + * + * @param LPTIM_FLAG LPTIM_FLAG_CMPM LPTIM_FLAG_ARRM LPTIM_FLAG_EXTTRIG + * LPTIM_FLAG_CMPOK LPTIM_FLAG_ARROK LPTIM_FLAG_UP LPTIM_FLAG_DOWN + */ +void LPTIM_ClearFlag(uint32_t LPTIM_FLAG) +{ + assert_param(IS_LPTIM_GET_FLAG(LPTIM_FLAG)); + CW_LPTIM->ICR = ~LPTIM_FLAG; + +} + +/** + * @brief 获取LPTIM的中断标志位 + * + * @param LPTIM_IT LPTIM_IT_CMPM LPTIM_IT_ARRM LPTIM_IT_EXTTRIG LPTIM_IT_CMPOK + * LPTIM_IT_ARROK LPTIM_IT_UP LPTIM_IT_DOWN + * @return ITStatus SET RESET + */ +ITStatus LPTIM_GetITStatus(uint32_t LPTIM_IT) +{ + assert_param(IS_LPTIM_GET_FLAG(LPTIM_IT)); + + return (ITStatus)!!(CW_LPTIM->ISR & LPTIM_IT); +} + +/** + * @brief 清除LPTIM的中断标志位 + * + * @param LPTIM_IT LPTIM_IT_CMPM LPTIM_IT_ARRM LPTIM_IT_EXTTRIG LPTIM_IT_CMPOK + * LPTIM_IT_ARROK LPTIM_IT_UP LPTIM_IT_DOWN + */ +void LPTIM_ClearITPendingBit(uint32_t LPTIM_IT) +{ + assert_param(IS_LPTIM_GET_FLAG(LPTIM_IT)); + CW_LPTIM->ICR = ~LPTIM_IT; +} + +/** + * @brief 获取LPTIM在编码器模式下的状态 + * + * @return ENCStatus DOWN_STOP UP_STOP DOWN_RUN UP_RUN + */ +ENCStatus LPTIM_GetENCStatus(void) +{ + return (ENCStatus)((CW_LPTIM->ISR & 0x00000180) >> 7); +} + + + + + + +/************************ END OF FILE************************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_lvd.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_lvd.c new file mode 100644 index 0000000..09c25b3 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_lvd.c @@ -0,0 +1,295 @@ +/** + * @file cw32l012_lvd.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "cw32l012.h" +#include "cw32l012_lvd.h" + +/** + ****************************************************************************** + ** \addtogroup LvdGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#define IS_VALID_INPUT(x) ( (x) <= LvdInputPB11 ) + +#define IS_VALID_THRESHOLD(x) ( (x) <= LvdTH3p3V ) + +#define IS_VALID_CLK(x) ( (x) <= LvdFilterHsi ) + +#define IS_VALID_FILTER(x) ( (x) <= LvdFilter4095Clk ) + +#define IS_VALID_IRQTYPE(x) ( (x) <= LvdIrqFall ) + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') * + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** + * @brief + * 使能NVIC的LVD中断 + * + * @param intPriority:0~3 + * + * @return 无 + */ +void LVD_EnableNvic(uint8_t intPriority) +{ + NVIC_ClearPendingIRQ(LVD_IRQn); + NVIC_SetPriority(LVD_IRQn, intPriority); + NVIC_EnableIRQ(LVD_IRQn); +} + +/** + * @brief + * 停止NVIC的LVD中断 + * + * @param 无 + * + * @return 无 + */ +void LVD_DisableNvic(void) +{ + NVIC_ClearPendingIRQ(LVD_IRQn); + NVIC_DisableIRQ(LVD_IRQn); +} + +/** + * @brief + * 配置LVD中断/系统复位触发方式 + * + * @param LVD_TRIG: + * @arg LVD_TRIG_LEVEL + * @arg LVD_TRIG_FALL + * @arg LVD_TRIG_RISE + * @param NewState: + * @arg DISABLE + * @arg ENABLE + * + * @return 无 + */ +void LVD_TrigConfig(uint16_t LVD_TRIG, FunctionalState NewState) +{ + uint8_t itMask = 0; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_LVD_TRIG(LVD_TRIG)); + /* Get the LVD TRIG index */ + itMask = (uint8_t) LVD_TRIG; + if (NewState != DISABLE) + { + /* Enable the selected LVD interrupts */ + CW_LVD->CR1 |= itMask; + } + else + { + /* Disable the selected LVD interrupts */ + CW_LVD->CR1 &= (~(uint32_t) itMask); + } +} + +/** + * @brief + * 使能LVD中断 + * + * @param intPriority:0~3 + * + * @return + */ +void LVD_EnableIrq(uint8_t intPriority) +{ + REGBITS_SET(CW_LVD->CR1, LVD_CR1_IE_Msk); + LVD_EnableNvic(intPriority); +} + +/** + * @brief + * 禁止LVD中断 + * + * @param 无 + * + * @return 无 + */ +void LVD_DisableIrq(void) +{ + LVD_DisableNvic(); + REGBITS_CLR(CW_LVD->CR1, LVD_CR1_IE_Msk); + REGBITS_CLR(CW_LVD->CR1, LVD_CR1_LEVEL_Msk | LVD_CR1_FALL_Msk | LVD_CR1_RISE_Msk); +} + +/** + * @brief + * LVD初始化 + * + * @param LVD_InitStruct + * + * @return 无 + */ +void LVD_Init(LVD_InitTypeDef* LVD_InitStruct) +{ + ASSERT(LVD_InitStruct) + assert_param(IS_LVD_ACTION(LVD_InitStruct->LVD_Action)); + assert_param(IS_LVD_SOURCE(LVD_InitStruct->LVD_Source)); + assert_param(IS_LVD_THRESHOLD(LVD_InitStruct->LVD_Threshold)); + assert_param(IS_LVD_FILTER_CLK(LVD_InitStruct->LVD_FilterClk)); + assert_param(IS_LVD_FILTER_TIME(LVD_InitStruct->LVD_FilterTime)); + //Need to DISABLE first. + LVD_Disable(); + LVD_DisableIrq(); + + REGBITS_MODIFY( CW_LVD->CR1, LVD_CR1_FLTTIME_Msk , \ + ( LVD_InitStruct->LVD_FilterTime)); + + REGBITS_MODIFY( CW_LVD->CR0, LVD_CR0_VTH_Msk | LVD_CR0_SOURCE_Msk | LVD_CR0_ACTION_Msk | LVD_CR0_FLTCLK_Msk, \ + (LVD_InitStruct->LVD_Threshold | \ + LVD_InitStruct->LVD_Source | \ + LVD_InitStruct->LVD_Action| \ + LVD_InitStruct->LVD_FilterClk)); +} + +/** + * @brief + * LVD deinit + * + * @param 无 + * + * @return 无 + */ +void LVD_DeInit(void) +{ + LVD_DisableIrq(); + LVD_Disable(); +} + +/** + * @brief + * 使能LVD + * + * @param 无 + * + * @return 无 + */ +void LVD_Enable(void) +{ + REGBITS_SET(CW_LVD->CR0, LVD_CR0_EN_Msk); +} + +/** + * @brief + * 停止LVD + * + * @param 无 + * + * @return 无 + */ +void LVD_Disable(void) +{ + REGBITS_CLR(CW_LVD->CR0, LVD_CR0_EN_Msk); +} + +/** + * @brief + * 获取LVD中断标志 + * + * @param 无 + * + * @return boolean_t: TRUE or FALSE + */ +boolean_t LVD_GetIrqStatus(void) +{ + return (boolean_t)(REGBITS_GET(CW_LVD->SR, LVD_SR_INTF_Msk)); +} + +/** + * @brief + * 获取LVD指定的中断状态 + * + * @param LVD_FLAG: + * @arg LVD_FLAG_FLTV + * @arg LVD_FLAG_INTF + * + * @return FlagStatus: SET or RESET + */ +FlagStatus LVD_GetFlagStatus(uint16_t LVD_FLAG) +{ + assert_param(IS_LVD_GET_FLAG(LVD_FLAG)); + return (REGBITS_GET(CW_LVD->SR, LVD_FLAG) ? SET : RESET); +} + +/** + * @brief + * 清除LVD中断标志 + * + * @param 无 + * + * @return 无 + */ +void LVD_ClearIrq(void) +{ + REGBITS_CLR(CW_LVD->SR, LVD_SR_INTF_Msk); +} + +/** + * @brief + * 获取Filter结果 + * + * @param 无 + * + * @return boolean_t: TRUE or FALSE + */ +boolean_t LVD_GetFilterResult(void) +{ + return (boolean_t)(REGBITS_GET(CW_LVD->SR, LVD_SR_FLTV_Msk)); +} +//@} // LvdGroup + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_opa.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_opa.c new file mode 100644 index 0000000..7c761ff --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_opa.c @@ -0,0 +1,189 @@ +/** + * @file cw32l012_opa.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* + 表格 1. OPA 正向 / 反向 输入端列表: + +--------------------------------------------------------------------------+ + | | | OPA1 | OPA2 | + |-----------------|--------|--------------|--------------| + | INN | INN1 | PA04 | PA05 | + | | INN2 | PA07 | PA07 | + |-----------------|--------|--------------|--------------| + | | INP1 | PA03 | PA04 | + | INP | INP2 | PA06 | PA06 | + | | INP3 | PB01 | PB00 | + | | INP4 | DAC1_OUTINTL | DAC2_OUTINTL | + +--------------------------------------------------------------------------+ + + 表格 2. OPA 输出端列表: + +--------------------------------------------------------------------------+ + | | | OPA1 | OPA2 | + |-----------------|--------|--------------|--------------| + | Output | | PB00 | PB01 | + |-----------------|--------|--------------|--------------| + | Internal output | | ADC1_CH13 | ADC1_CH12 | + | to ADCs | | ADC2_CH13 | ADC2_CH12 | + |-----------------|--------|--------------|--------------| + | output to ADCs | |ADC1_IN8(PB00)|ADC1_IN9(PB01)| + | input on GPIO | |ADC2_IN3(PB00)|ADC2_IN4(PB01)| + |-----------------|--------|--------------|--------------| + | output to VCs | |VC1_INP3(PB00)|VC2_INP3(PB01)| + | input on GPIO | |VC3_INP3(PB00)|VC4_INP3(PB01)| + +--------------------------------------------------------------------------+ +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_opa.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ +/******************************************************************************* + * @brief OPA 初始化 + * @param OPAx : CW_OPA1/CW_OPA2, + * OPA_InitStruct :见结构体的定义 + * @retval + * @note 需通过APBENx寄存器使能OPA的时钟后，才可调用该函数 + */ +void OPA_Init(OPA_TypeDef *OPAx, OPA_InitTypeDef *OPA_InitStruct) +{ + uint32_t tmpInputP = OPA_InitStruct->InputP & OPA_INP_MASK; + uint32_t tmpInputN = (OPA_InitStruct->WorkMode == OPA_WORKMODE_FOLLOWER) ?\ + 0UL : (OPA_InitStruct->InputN & OPA_INN_MASK); + + OPAx->CR = tmpInputP | tmpInputN |\ + (uint32_t)OPA_InitStruct->Bias |\ + (uint32_t)OPA_InitStruct->PgaGain |\ + (uint32_t)OPA_InitStruct->WorkMode; + OPAx->CAL = 0; +} + +/******************************************************************************* + * @brief OPA 反初始化 + * @param OPAx : CW_OPA1/CW_OPA2 + * @retval none + * @note 需通过APBENx寄存器使能OPA的时钟后，才可调用该函数 + */ +void OPA_DeInit(OPA_TypeDef *OPAx) +{ + OPAx->CR = OPA_CR0_RESET_VALUE; + OPAx->CAL = 0; + + // 重置OPA外设 + REGBITS_CLR(CW_SYSCTRL->APBRST2, SYSCTRL_APBRST2_OPA_Msk); + REGBITS_SET(CW_SYSCTRL->APBRST2, SYSCTRL_APBRST2_OPA_Msk); +} + +/******************************************************************************* + * @brief 启动OPA + * @param OPAx : CW_OPA1/CW_OPA2 + * @retval none + */ +void OPA_Start(OPA_TypeDef *OPAx) +{ + REGBITS_SET(OPAx->CR, OPAx_CR_EN_Msk); +} + +/******************************************************************************* + * @brief 停止OPA + * @param OPAx : CW_OPA1/CW_OPA2 + * @retval none + */ +void OPA_Stop(OPA_TypeDef *OPAx) +{ + REGBITS_CLR(OPAx->CR, OPAx_CR_EN_Msk); +} + +/******************************************************************************* + * @brief OPA软件校正模式开始校正 + * @param OPAx : CW_OPA1/CW_OPA2 + * @retval none + * @note 1. 软件校正启动后由用户控制校正时间 + * @note 2. 校正完成后需要使用 OPA_AutoZeroSoft_Stop 以停止校正 + */ +void OPA_AutoZeroSoft_Start(OPA_TypeDef *OPAx) +{ + REGBITS_MODIFY(OPAx->CAL, OPAx_CAL_SOFTTRIG_Msk, + OPAx_CAL_START_Msk | OPAx_CAL_CALMODE_Msk | OPAx_CAL_CALEN_Msk); +} + +/******************************************************************************* + * @brief OPA软件校正模式结束校正 + * @param OPAx : CW_OPA1/CW_OPA2 + * @retval none + * @note 需要配合OPA_AutoZeroSoft_Start 使用 + */ +void OPA_AutoZeroSoft_Stop(OPA_TypeDef *OPAx) +{ + REGBITS_CLR(OPAx->CAL, OPAx_CAL_START_Msk | OPAx_CAL_CALMODE_Msk); + // 结束校正后需要10uS才可使用 + FirmwareDelay(SystemCoreClock / 1000000); +} + +/******************************************************************************* + * @brief OPA触发校正模式配置 + * @param OPAx : CW_OPA1/CW_OPA2 + * @param AutoZeroClk : OPA触发校正时钟 + * @param AutoZeroPeriod : OPA触发校正时长 + * @param AutoZeroTrigSrc: OPA触发校正触发源 + * @retval none + * @note 需要在调用初始化之后再调用本函数 + */ +void OPA_AutoZeroTrig_Config(OPA_TypeDef *OPAx, + OPA_AutoZeroClockTypeDef AutoZeroClk, + OPA_AutoZeroPeriodTypeDef AutoZeroPeriod, + uint32_t AutoZeroTrigSrc) +{ + OPAx->CAL = AutoZeroTrigSrc | + (uint32_t)AutoZeroClk | + (uint32_t)AutoZeroPeriod | + OPAx_CAL_CALEN_Msk; +} + + +/******************************************************************************* + * @brief OPA触发校正模式创建软件触发校正事件 + * @param OPAx : CW_OPA1/CW_OPA2 + * @retval none + * @note 需要配置为触发校正模式，且触发源为软件触发 + */ +void OPA_AutoZeroTrig_SoftEvent(OPA_TypeDef *OPAx) +{ + if ((OPAx->CAL & (OPAx_CAL_CALMODE_Msk | OPAx_CAL_CALEN_Msk)) == OPAx_CAL_CALEN_Msk) + { + OPA_AUTOZEROTRIG_SOFTEVENT(OPAx); + } +} + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_pwr.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_pwr.c new file mode 100644 index 0000000..e2227be --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_pwr.c @@ -0,0 +1,107 @@ +/** + * @file cw32l012_pwr.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "cw32l012.h" +#include "cw32l012_pwr.h" + +/** + ******************************************************************************* + ** \addtogroup LpmGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +/* +#define IS_VALID_SEVONPEND(x) (SevPndDisable == (x) ||\ + SevPndEnable == (x)) +#define IS_VALID_SLEEPDEEP(x) (SlpDpDisable == (x) ||\ + SlpDpEnable == (x)) +#define IS_VALID_SLEEPONEXIT(x) (SlpExtDisable == (x) ||\ + SlpExtEnable == (x)) +*/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief 低功耗模式配置 + * + * @param PWR_InitStruct 低功耗模式配置结构体指针 + * + * @return + */ +void PWR_Config(PWR_InitTypeDef* PWR_InitStruct) +{ + ASSERT(NULL != PWR_InitStruct) + assert_param(IS_PWR_SEVONPEND(PWR_InitStruct->PWR_Sevonpend)); + assert_param(IS_PWR_SLEEPDEEP(PWR_InitStruct->PWR_SleepDeep)); + assert_param(IS_PWR_SLEEPONEXIT(PWR_InitStruct->PWR_SleepOnExit)); + + REGBITS_MODIFY(SCB->SCR, SCB_SCR_SEVONPEND_Msk | \ + SCB_SCR_SLEEPDEEP_Msk | \ + SCB_SCR_SLEEPONEXIT_Msk, \ + PWR_InitStruct->PWR_Sevonpend | \ + PWR_InitStruct->PWR_SleepDeep | \ + PWR_InitStruct->PWR_SleepOnExit); +} + +/** + * @brief 进入睡眠模式 + * + * @return + */ +void PWR_GotoLpmMode(void) +{ + __WFI(); +} + +//@} // LpmGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_ram.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_ram.c new file mode 100644 index 0000000..7bc76c4 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_ram.c @@ -0,0 +1,99 @@ +/** + * @file cw32l012_ram.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_ram.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief RAM中断配置 + * + * @param RAM_IT : RAM_IT_PARITY + * @param NewState : ENABLE DISABLE + */ +void RAM_ITConfig(uint32_t RAM_IT, FunctionalState NewState) +{ + assert_param(IS_RAM_IT(RAM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + CW_RAM->IER |= RAM_IT; + } + else + { + CW_RAM->IER &= (~RAM_IT); + } +} + +/** + * @brief 获取RAM中断标志 + * + * @param RAM_IT : RAM_IT_PARITY + * @return ITStatus : SET RESET + */ +ITStatus RAM_GetITStatus(uint32_t RAM_IT) +{ + assert_param(IS_RAM_GET_IT(RAM_IT)); + + return (CW_RAM->ISR & RAM_IT) ? SET : RESET; +} + +/** + * @brief 清除RAM中断标志 + * + * @param RAM_IT : RAM_IT_PARITY + */ +void RAM_ClearITPendingBit(uint32_t RAM_IT) +{ + assert_param(IS_RAM_IT(RAM_IT)); + + CW_RAM->ICR &= (~RAM_IT); +} + +/** + * @brief 获取发生奇偶校验错的RAM地址 + * + * @return uint32_t + */ +uint32_t RAM_GetErrorAddress(void) +{ + return (CW_RAM->ADDR); +} + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_rtc.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_rtc.c new file mode 100644 index 0000000..ea3c12d --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_rtc.c @@ -0,0 +1,616 @@ +/** + * @file cw32l012_rtc.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_rtc.h" +#include "cw32l012_sysctrl.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief RTC去初始化 + * + */ +void RTC_DeInit(void) +{ + /* 解锁RTC寄存器的写保护 */ + CW_RTC->KEY_f.KEY = RTC_KEY_WORD1; + CW_RTC->KEY_f.KEY = RTC_KEY_WORD2; + + /* 对除RTC_CR0、RTC_CR1、RTC_CR2和RTC_COMPEN外，其他的RTC寄存器赋默认值 */ + CW_RTC->DATE = RTC_DATE_RESET_VALUE; + CW_RTC->TIME = RTC_TIME_RESET_VALUE; + CW_RTC->ALARMA = RTC_ALARMA_RESET_VALUE; + CW_RTC->ALARMB = RTC_ALARMB_RESET_VALUE; + CW_RTC->AWTARR = RTC_AWTARR_RESET_VALUE; + CW_RTC->IER = RTC_IER_RESET_VALUE; + CW_RTC->ICR = 0UL; // 清除中断标志位 + + /* 使能RTC寄存器的写保护 */ + CW_RTC->KEY_f.KEY = RTC_KEY_WORD1; + CW_RTC->KEY_f.KEY = RTC_KEY_LOCKW; + + /* 复位RTC模块，RTC_CR0、RTC_CR1、RTC_CR2和RTC_COMPEN复位为默认值 */ + CW_SYSCTRL->APBRST2_f.RTC = 0; + + /* 关闭RTC模块的时钟 */ + CW_SYSCTRL->APBEN2_f.RTC = 0; +} + +/** + * @brief RTC模块初始化 + * + * @param 初始化RTC模块，用户需首先启动启动RTC时钟源！！！自动运行RTC + * + * @return ErrorStatus 返回值为SUCCESS或ERROR + */ +ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) +{ + assert_param(IS_RTC_RTCCLK_SOURCE(RTC_InitStruct->RTC_ClockSource)); + //CW_SYSCTRL->APBEN2_f.RTC = 1; // 启动RTC外设时钟，使能RTC模块 + __SYSCTRL_RTC_CLK_ENABLE(); + if ((SYSCTRL_GetAllRstFlag() & SYSCTRL_RESETFLAG_POR) != SYSCTRL_RESETFLAG_POR) //不是上电复位，直接退出 + { + SYSCTRL_ClearRstFlag(SYSCTRL_RESETFLAG_ALL); + return SUCCESS; + } + + + RTC_Cmd(DISABLE); // 停止RTC，保证正确访问RTC寄存器 + + RTC_SetClockSource(RTC_InitStruct->RTC_ClockSource); // 设置RTC时钟源, 用户需首先启动RTC时钟源！！！ + RTC_SetDate(&RTC_InitStruct->DateStruct); + RTC_SetTime(&RTC_InitStruct->TimeStruct); + + RTC_Cmd(ENABLE); + SYSCTRL_ClearRstFlag(SYSCTRL_RESETFLAG_ALL); + + return SUCCESS; +} + + +void RTC_Cmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + RTC_UNLOCK(); + + CW_RTC->CR0_f.START = NewState; + + RTC_LOCK(); +} + +/** + * @brief 读取中断RTC状态 + * + * @param RTC_ITState + * @return ITStatus + */ + +ITStatus RTC_GetITState(uint32_t RTC_ITState) +{ + uint32_t RegTmp; + assert_param(IS_RTC_GET_IT(RTC_ITState)); + do + { + RegTmp = CW_RTC->ISR; + } + while (RegTmp != CW_RTC->ISR); + + return (RegTmp & RTC_ITState) ? SET : RESET; +} + +/** + * @brief 设置中断使能 + * + * @param RTC_IT + * @param NewState + */ +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) +{ + assert_param(IS_RTC_CONFIG_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + RTC_UNLOCK(); + + if (!NewState) + { + CW_RTC->IER &= ~RTC_IT; + } + else + { + CW_RTC->IER |= RTC_IT; + } + + RTC_LOCK(); +} + +/** + * @brief 清除中断标志 + * + * @param RTC_IT + */ +void RTC_ClearITPendingBit(uint32_t RTC_IT) +{ + assert_param(IS_RTC_CLAER_IT(RTC_IT)); + + RTC_UNLOCK(); + + // CW_RTC->CR1_f.ACCESS = 1; + // while (!CW_RTC->CR1_f.WINDOW); + + CW_RTC->ICR = ~RTC_IT; + + // CW_RTC->CR1_f.ACCESS = 0; + RTC_LOCK(); +} + +/** + * @brief 设置时间，HOUR、MINIUTE、SECOND必须为BCD方式，用户须保证HOUR、AMPM、H24之间的关联正确性 + * + * @param RTC_TimeStruct + */ +void RTC_SetTime(RTC_TimeTypeDef* RTC_TimeStruct) +{ + assert_param(IS_RTC_SECONDS(RTC_BCDToBin(RTC_TimeStruct->Second))); + assert_param(IS_RTC_MINUTES(RTC_BCDToBin(RTC_TimeStruct->Minute))); + if (RTC_TimeStruct->H24 == RTC_HOUR12) + assert_param(IS_RTC_HOUR12(RTC_BCDToBin(RTC_TimeStruct->Hour))); + else + assert_param(IS_RTC_HOUR24(RTC_BCDToBin(RTC_TimeStruct->Hour))); + + RTC_UNLOCK(); + + CW_RTC->CR0_f.H24 = RTC_TimeStruct->H24; + if (RTC_TimeStruct->H24 == RTC_HOUR12) + { + CW_RTC->TIME = ((uint32_t)(RTC_TimeStruct->AMPM) << 21) | + ((uint32_t)(RTC_TimeStruct->Hour) << 16) | + ((uint32_t)(RTC_TimeStruct->Minute) << 8) | + ((uint32_t)(RTC_TimeStruct->Second)); + } + else + { + CW_RTC->TIME = ((uint32_t)(RTC_TimeStruct->Hour) << 16) | + ((uint32_t)(RTC_TimeStruct->Minute) << 8) | + ((uint32_t)(RTC_TimeStruct->Second)); + } + + RTC_LOCK(); +} + +/** + * @brief + * 设置日期，DAY、MONTH、YEAR必须为BCD方，星期为0~6，代表星期日，星期一至星期六 + * @param RTC_DateStruct + */ +void RTC_SetDate(RTC_DateTypeDef* RTC_DateStruct) +{ + assert_param(IS_RTC_YEAR(RTC_BCDToBin(RTC_DateStruct->Year))); + assert_param(IS_RTC_MONTH(RTC_BCDToBin(RTC_DateStruct->Month))); + assert_param(IS_RTC_DAY(RTC_BCDToBin(RTC_DateStruct->Day))); + assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->Week)); + + RTC_UNLOCK(); + + CW_RTC->DATE = ((uint32_t)(RTC_DateStruct->Week) << 24) | + ((uint32_t)(RTC_DateStruct->Year) << 16) | + ((uint32_t)(RTC_DateStruct->Month) << 8) | + ((uint32_t)(RTC_DateStruct->Day)); + + RTC_LOCK(); +} + +/** + * @brief 获取当前时间，BCD格式 + * + * @param RTC_TimeStruct + */ +void RTC_GetTime(RTC_TimeTypeDef* RTC_TimeStruct) +{ + uint32_t RegTmp = 0; + + RTC_TimeStruct->H24 = CW_RTC->CR0_f.H24; // 读CR0是否需要连读两次，待硬件检测 + + RegTmp = CW_RTC->TIME; + while (RegTmp != CW_RTC->TIME) + { + RegTmp = CW_RTC->TIME; // 连续两次读取的内容一致，认为读取成功 + } + + RTC_TimeStruct->Hour = (uint8_t)((RegTmp & RTC_TIME_HOUR_Msk) >> 16); + RTC_TimeStruct->Minute = (uint8_t)((RegTmp & RTC_TIME_MINUTE_Msk) >> 8); + RTC_TimeStruct->Second = (uint8_t)(RegTmp & RTC_TIME_SECOND_Msk); + if (RTC_TimeStruct->H24 == RTC_HOUR12) + { + RTC_TimeStruct->AMPM = RTC_TimeStruct->Hour >> 5; + RTC_TimeStruct->Hour &= 0x1f; + } +} + + +/** + * @brief 获取用当前日期，BCD格式 + * + * @param RTC_Date + */ +void RTC_GetDate(RTC_DateTypeDef* RTC_Date) +{ + uint32_t RegTmp = 0; + + RegTmp = CW_RTC->DATE; + while (RegTmp != CW_RTC->DATE) + { + RegTmp = CW_RTC->DATE; // 连续两次读取的内容一致，认为读取成功 + } + + RTC_Date->Day = (uint8_t)(RegTmp & RTC_DATE_DAY_Msk); + RTC_Date->Month = (uint8_t)((RegTmp & RTC_DATE_MONTH_Msk) >> 8); + RTC_Date->Year = (uint8_t)((RegTmp & RTC_DATE_YEAR_Msk) >> 16); + RTC_Date->Week = (uint8_t)((RegTmp & RTC_DATE_WEEK_Msk) >> 24); +} + +/** + * @brief 设置闹钟，BCD格式。 || + * RTC_AlarmMask：bit32~24:WeeksMask，bit23:HourMask，bit15:MinuteMask，bit7:SecondMask || + * 闹钟时间，HOUR、MINIUTE、SECOND必须为BCD方式，用户须保证HOUR、AMPM、H24之间的关联正确性 + * + * @param RTC_Alarm + * @param RTC_AlarmStruct + */ +void RTC_SetAlarm(uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + uint32_t RegTmp = 0; + + assert_param(IS_RTC_ALARM(RTC_Alarm)); + assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); + assert_param(IS_RTC_SECONDS(RTC_BCDToBin(RTC_AlarmStruct->RTC_AlarmTime.Second))); + assert_param(IS_RTC_MINUTES(RTC_BCDToBin(RTC_AlarmStruct->RTC_AlarmTime.Minute))); + if (RTC_AlarmStruct->RTC_AlarmTime.H24 == RTC_HOUR12) + assert_param(IS_RTC_HOUR12(RTC_BCDToBin(RTC_AlarmStruct->RTC_AlarmTime.Hour))); + else + assert_param(IS_RTC_HOUR24(RTC_BCDToBin(RTC_AlarmStruct->RTC_AlarmTime.Hour))); + + RegTmp = RTC_AlarmStruct->RTC_AlarmMask | + (uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.Hour << 16) | + (uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.Minute << 8) | + (uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.Second); + + RTC_UNLOCK(); + + if (RTC_Alarm == RTC_Alarm_A) + { + CW_RTC->ALARMA = RegTmp; + } + else + { + CW_RTC->ALARMB = RegTmp; + } + + RTC_LOCK(); +} + +/** + * @brief 获取闹钟的设置，时间为BCD格式。 + * + * @param RTC_Alarm + * @param RTC_AlarmStruct + */ +void RTC_GetAlarm(uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + uint32_t RegTmp = 0; + + assert_param(IS_RTC_ALARM(RTC_Alarm)); + + if (RTC_Alarm == RTC_Alarm_A) + { + RegTmp = CW_RTC->ALARMA; + while (RegTmp != CW_RTC->ALARMA) + { + RegTmp = CW_RTC->ALARMA; + } + } + else + { + RegTmp = CW_RTC->ALARMB; + while (RegTmp != CW_RTC->ALARMB) + { + RegTmp = CW_RTC->ALARMB; + } + } + + RTC_AlarmStruct->RTC_AlarmMask = RegTmp & RTC_AlarmMask_All; + + RTC_AlarmStruct->RTC_AlarmTime.H24 = CW_RTC->CR0_f.H24; // 读CR0是否需要连读两次，待硬件检测 + + RTC_AlarmStruct->RTC_AlarmTime.Hour = (uint8_t)((RegTmp & RTC_TIME_HOUR_Msk) >> 16); + RTC_AlarmStruct->RTC_AlarmTime.Minute = (uint8_t)((RegTmp & RTC_TIME_MINUTE_Msk) >> 8); + RTC_AlarmStruct->RTC_AlarmTime.Second = (uint8_t)(RegTmp & RTC_TIME_SECOND_Msk); + if (RTC_AlarmStruct->RTC_AlarmTime.H24 == RTC_HOUR12) + { + RTC_AlarmStruct->RTC_AlarmTime.AMPM = RTC_AlarmStruct->RTC_AlarmTime.Hour >> 5; + RTC_AlarmStruct->RTC_AlarmTime.Hour &= 0x1f; + } +} + +void RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) +{ + assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + RTC_UNLOCK(); + + if (RTC_Alarm == RTC_Alarm_A) + { + CW_RTC->CR2_f.ALARMAEN = NewState; + } + else + { + CW_RTC->CR2_f.ALARMBEN = NewState; + } + + RTC_LOCK(); +} + +void RTC_TamperTriggerConfig(uint32_t RTC_TamperTrigger) +{ + assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); + + RTC_UNLOCK(); + + CW_RTC->CR2_f.TAMPEDGE = RTC_TamperTrigger; + + RTC_LOCK(); +} + +void RTC_TamperCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + RTC_UNLOCK(); + + CW_RTC->CR2_f.TAMPEN = NewState; + + RTC_LOCK(); +} + +void RTC_GetTamperDate(RTC_DateTypeDef* RTC_Date) +{ + uint32_t RegTmp = 0; + + do + { + RegTmp = CW_RTC->TAMPDATE; + } + while (RegTmp != CW_RTC->TAMPDATE); + + RTC_Date->Week = (uint8_t)((RegTmp & RTC_TAMPDATE_WEEK_Msk) >> 13); + RTC_Date->Month = (uint8_t)((RegTmp & RTC_TAMPDATE_MONTH_Msk) >> 8); + RTC_Date->Day = (uint8_t)(RegTmp & RTC_TAMPDATE_DAY_Msk); +} + +void RTC_GetTamperTime(RTC_TimeTypeDef* RTC_TimeStruct) +{ + uint32_t RegTmp = 0; + + do + { + RegTmp = CW_RTC->TAMPTIME; + } + while (RegTmp != CW_RTC->TAMPTIME); // 连续两次读取的内容一致，认为读取成功 + + RTC_TimeStruct->Second = (uint8_t)((RegTmp & RTC_TAMPTIME_SECOND_Msk) >> 16); + RTC_TimeStruct->Minute = (uint8_t)((RegTmp & RTC_TAMPTIME_MINUTE_Msk) >> 8); + RTC_TimeStruct->Hour = (uint8_t)(RegTmp & RTC_TAMPTIME_HOUR_Msk); + + RTC_TimeStruct->H24 = CW_RTC->CR0_f.H24; // 读CR0是否需要连读两次，待硬件检测 + if (RTC_TimeStruct->H24 == RTC_HOUR12) + { + RTC_TimeStruct->AMPM = RTC_TimeStruct->Hour >> 5; + RTC_TimeStruct->Hour &= 0x1f; + } + +} + + +/** + * @brief 设置RTC的OUTPUT的信号源 + * + * @param RTC_Output + */ +void RTC_OutputConfig(uint8_t RTC_Output) +{ + assert_param(IS_RTC_RTCOUT_SOURCE(RTC_Output)); + + RTC_UNLOCK(); + + CW_RTC->CR2_f.RTCOUT = RTC_Output; + + RTC_LOCK(); +} + +/** + * @brief RTC的自动唤醒定时器设置 + * + * @param RCT_AWTStruct + */ +void RTC_AWTConfig(RTC_AWTTypeDef* RCT_AWTStruct) +{ + assert_param(IS_RTC_AWTTIMER_SOURCE(RCT_AWTStruct->AWT_ClockSource)); + + RTC_UNLOCK(); + + CW_RTC->CR2_f.AWTSRC = RCT_AWTStruct->AWT_ClockSource; + CW_RTC->AWTARR = (uint32_t)RCT_AWTStruct->AWT_ARRValue; + + RTC_LOCK(); +} + +/** + * @brief 使能或禁止AWT功能 + * + * @param NewState + */ +void RTC_AWTCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + RTC_UNLOCK(); + + CW_RTC->CR2_f.AWTEN = NewState; + + RTC_LOCK(); +} + +/** + * @brief + * + * @param Period + */ +void RTC_SetInterval(uint8_t Period) +{ + assert_param(IS_RTC_INTERVAL_PERIOD(Period)); + + RTC_UNLOCK(); + + CW_RTC->CR0_f.INTERVAL = Period; + + RTC_LOCK(); +} + +/** + * @brief 设置RTC的计时时钟来源 + * + * @param RTC_ClockSource ：只能是RTC_RTCCLK_FROM_LSE、LSI、HEX有效值，字操作，影响WINDOW、ACCESS位 + * 用户须先启动RTC时钟源 + */ +void RTC_SetClockSource(uint32_t RTC_ClockSource) +{ + assert_param(IS_RTC_RTCCLK_SOURCE(RTC_ClockSource)); + + RTC_UNLOCK(); /* 解除RTC寄存器的写保护 */ + +// CW_RTC->CR1_f.SOURCE = RTC_ClockSource; // 设置RTC时钟源 + CW_RTC->CR1 = RTC_ClockSource; // 设置RTC时钟源,同时将WINDOWS、ACCESS位清零 + + RTC_LOCK(); +} + +/** + * @brief 设置校准时钟参数：FREQ、STEP、SIGN、COMPEN || + * 注:RTC_CalibStruct->Step 为 0 时，要保证 RTC_CalibStruct->RefClock 大于 4MHz || + * RTC_CalibStruct->Step 为 1 时，要保证 RTC_CalibStruct->RefClock 大于 12MHz || + * RTC_CalibStruct->Step 为 2 时，要保证 RTC_CalibStruct->RefClock 大于 24MHz + * + * @param RTC_CalibStruct + */ +void RTC_CalibrationConfig(RTC_CalibTypeDef* RTC_CalibStruct) +{ + assert_param(IS_RTC_COMPEN_FREQ(RTC_CalibStruct->Freq)); + assert_param(IS_RTC_COMPEN_STEP(RTC_CalibStruct->Step)); + assert_param(IS_RTC_COMPEN_SIGN(RTC_CalibStruct->Sign)); + assert_param(IS_RTC_COMPEN_VALUE(RTC_CalibStruct->CompensationValue)); + + RTC_UNLOCK(); + + CW_RTC->COMPCFR1 = (RTC_CalibStruct->Sign << 14) | + (RTC_CalibStruct->Step << 12) | + RTC_CalibStruct->CompensationValue; + + RTC_LOCK(); +} + +void RTC_CalibrationCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + RTC_UNLOCK(); + + CW_RTC->COMPCFR1_f.EN = NewState; + + RTC_LOCK(); +} + +/** + * @brief RTC的自动唤醒定时器PSC1 PSC2设置 + * + * @param + */ +void RTC_AWT_PSC_set(uint8_t PSC1A,uint32_t PSC2A) +{ +// assert_param(IS_RTC_AWTTIMER_SOURCE(RCT_AWTStruct->AWT_ClockSource)); + + RTC_UNLOCK(); + + CW_RTC->PSC_f.PSC1 = PSC1A; + CW_RTC->PSC_f.PSC2 = PSC2A; + + RTC_LOCK(); +} +/** + * @brief Convert a 2 digit decimal to BCD format. + * @param Value Byte to be converted + * @retval Converted byte + */ +uint8_t RTC_BinToBCD(uint8_t Value) +{ + uint32_t bcdhigh = 0U; + uint8_t Param = Value; + + while (Param >= 10U) + { + bcdhigh++; + Param -= 10U; + } + + return ((uint8_t)(bcdhigh << 4U) | Param); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value BCD value to be converted + * @retval Converted byte + */ +uint8_t RTC_BCDToBin(uint8_t Value) +{ + uint32_t tmp; + tmp = (((uint32_t)Value & 0xF0U) >> 4U) * 10U; + return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU)); +} + +/** + * @} + */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_spi.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_spi.c new file mode 100644 index 0000000..9dadecf --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_spi.c @@ -0,0 +1,448 @@ +/** + * @file cw32l012_spi.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2022 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_spi.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief 通过SPIx发送一个数据(4 ~ 16bit) + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1 + * @param Data :待发送的数据 + */ +void SPI_SendData(SPI_TypeDef* SPIx, uint16_t Data) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + SPIx->DR = Data; +} + +/** + * @brief 通过SPIx接收一个数据(4 ~ 16bit) + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1 + * @return uint16_t :接收的数据 + */ +uint16_t SPI_ReceiveData(SPI_TypeDef* SPIx) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + return (uint16_t)(SPIx->DR); +} + +/** + * @brief 通过SPIx发送一个数据(4 ~ 16bit)，同时接收一个数据(4 ~ 16bit) + * 该函数会等待发送缓冲区为空，然后发送数据，然后等待接收缓冲区非空， + * 最后返回接收到的数据 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1、CW_SPI2、CW_SPI3 + * @param Data :待发送的数据 + * @return uint16_t :接收的数据 + */ +uint16_t SPI_TransmitReceive(SPI_TypeDef* SPIx, uint16_t Data) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + // 等待发送缓冲区为空 + while((SPIx->ISR & SPIx_ISR_TXE_Msk) == 0); + SPIx->DR = Data; + // 等待接收缓冲区非空 + while((SPIx->ISR & SPIx_ISR_RXNE_Msk) == 0); + + return (uint16_t)(SPIx->DR); +} +/** + * @brief 根据SPI_InitStruct中指定的参数初始化SPIx外设 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1 + * @param SPI_InitStruct :指向SPI_InitTypeDef类型结构体的指针 + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_SPEED(SPI_InitStruct->SPI_Speed)); + + REGBITS_MODIFY(SPIx->CR1, SPIx_CR1_MODE_Msk |\ + SPIx_CR1_WIDTH_Msk | SPIx_CR1_SSM_Msk |\ + SPIx_CR1_SMP_Msk | SPIx_CR1_LSBF_Msk |\ + SPIx_CR1_BR_Msk | SPIx_CR1_MSTR_Msk |\ + SPIx_CR1_CPOL_Msk | SPIx_CR1_CPHA_Msk \ + ,\ + SPI_InitStruct->SPI_Direction |\ + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_NSS |\ + SPI_InitStruct->SPI_Speed | SPI_InitStruct->SPI_FirstBit |\ + (SPI_InitStruct->SPI_BaudRatePrescaler << SPIx_CR1_BR_Pos)| SPI_InitStruct->SPI_Mode |\ + SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA); +} + +/** + * @brief 默认值赋值SPI_InitStruct结构体成员 + * + * @param SPI_InitStruct :指向SPI_InitTypeDef类型结构体的指针 + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ + /* SPI_InitStruct members default value */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + SPI_InitStruct->SPI_BaudRatePrescaler = 0; // PCLK/2, SCK = PCLK/(2*(n+1)) + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_Speed = SPI_Speed_Low; +} + +/** + * @brief SPI1去初始化 + * + */ +void SPI1_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.SPI1 = 0; + CW_SYSCTRL->APBRST1_f.SPI1 = 1; +} + +/** + * @brief 使能或禁止SPIx + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1 + * @param NewState :ENABLE or DISABLE + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + SPIx->CR2_f.EN = NewState; +} + +/** + * @brief 使能/失能SPIx中断 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1 + * @param SPI_IT :中断源 + * 参数可以是: + * @arg SPI_IT_MODF: 模式错误中断 + * @arg SPI_IT_SSERR: 从机模式下的从机选择错误中断 + * @arg SPI_IT_OV: 接收缓冲上溢错误中断 + * @arg SPI_IT_UD: 从机模式下发送缓冲下溢错误中断 + * @arg SPI_IT_SSR: 从机选择输入上升沿中断 + * @arg SPI_IT_SSF: 从机选择输入下降沿中断 + * @arg SPI_IT_RXNE: 接收缓冲非空中断 + * @arg SPI_IT_TXE: 发送缓冲空中断 + * @param NewState :ENABLE or DISABLE + */ +void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_IT(SPI_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SPIx->IER |= SPI_IT; + } + else + { + SPIx->IER &= ~SPI_IT; + } +} + +/** + * @brief 获取SPIx中断标志位 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1 + * @param SPI_IT :中断源 + * 参数可以是: + * @arg SPI_IT_MODF: 模式错误中断 + * @arg SPI_IT_SSERR: 从机模式下的从机选择错误中断 + * @arg SPI_IT_OV: 接收缓冲上溢错误中断 + * @arg SPI_IT_UD: 从机模式下发送缓冲下溢错误中断 + * @arg SPI_IT_SSR: 从机选择输入上升沿中断 + * @arg SPI_IT_SSF: 从机选择输入下降沿中断 + * @arg SPI_IT_RXNE: 接收缓冲非空中断 + * @arg SPI_IT_TXE: 发送缓冲空中断 + * @return ITStatus :SPI_IT当前状态 (SET or RESET) + */ +ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_IT(SPI_IT)); + + return ((SPIx->ISR & SPI_IT) ? SET : RESET); +} + +/** + * @brief 清除SPIx中断标志位 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1 + * @param SPI_IT :中断源 + * 参数可以是: + * @arg SPI_IT_MODF: 模式错误中断 + * @arg SPI_IT_SSERR: 从机模式下的从机选择错误中断 + * @arg SPI_IT_OV: 接收缓冲上溢错误中断 + * @arg SPI_IT_UD: 从机模式下发送缓冲下溢错误中断 + * @arg SPI_IT_SSR: 从机选择输入上升沿中断 + * @arg SPI_IT_SSF: 从机选择输入下降沿中断 + * @arg SPI_IT_RXNE: 接收缓冲非空中断 + * @note + * -TXE中断标志位只能通过写SPI_DR寄存器来清除 + */ +void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CLEAR_IT(SPI_IT)); + + SPIx->ICR &= ~SPI_IT; +} + +/** + * @brief 获取SPIx标志位 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1 + * @param SPI_FLAG :标志位 + * 参数可以是: + * @arg SPI_FLAG_SSLVL: 从机选择信号状态 + * @arg SPI_FLAG_BUSY: 总线忙标志 + * @arg SPI_FLAG_MODF: 模式错误标志 + * @arg SPI_FLAG_SSERR: 从机模式下的从机选择错误标志 + * @arg SPI_FLAG_OV: 接收缓冲上溢错误中断 + * @arg SPI_FLAG_UD: 从机模式下发送缓冲下溢错误标志 + * @arg SPI_FLAG_SSR: 从机选择输入上升沿标志 + * @arg SPI_FLAG_SSF: 从机选择输入下降沿标志 + * @arg SPI_FLAG_RXNE: 接收缓冲非空标志 + * @arg SPI_FLAG_TXE: 发送缓冲空标志 + * @return FlagStatus :SPI_FLAG当前状态 (SET or RESET) + */ +FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_FLAG(SPI_FLAG)); + + return ((SPIx->ISR & SPI_FLAG) ? SET : RESET); +} + +/** + * @brief 清除SPIx标志位 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1 + * @param SPI_FLAG :标志位 + * 参数可以是: + * @arg SPI_FLAG_MODF: 模式错误标志 + * @arg SPI_FLAG_SSERR: 从机模式下的从机选择错误标志 + * @arg SPI_FLAG_OV: 接收缓冲上溢错误中断 + * @arg SPI_FLAG_UD: 从机模式下发送缓冲下溢错误标志 + * @arg SPI_FLAG_SSR: 从机选择输入上升沿标志 + * @arg SPI_FLAG_SSF: 从机选择输入下降沿标志 + * @arg SPI_FLAG_RXNE: 接收缓冲非空标志 + * @note + * -SSLVL、BUSY标志位由硬件自动设置和清除 + * -TXE标志位只能通过写SPI_DR寄存器来清除 + * -RXNE标志位也可以通过读SPI_DR寄存器来清除 + * @return FlagStatus :SPI_FLAG当前状态 (SET or RESET) + */ +void SPI_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_FLAG) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CLEAR_FLAG(SPI_FLAG)); + + SPIx->ICR &= ~SPI_FLAG; +} + +/** + * @brief 单线半双工数据传输方向配置 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1 + * @param SPI_Direction :发送/接收 + * 参数可以是： + * @arg SPI_Direction_Tx: 发送 + * @arg SPI_Direction_Rx: 接收 + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint8_t SPI_Direction) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + + SPIx->CR3 = SPI_Direction; +} + +/** + * @brief 使能/失能SPIx DMA + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1 + * @param SPI_DMAReq :DMA请求 + * 参数可以是： + * @arg SPI_DMAReq_Tx: DMA发送请求 + * @arg SPI_DMAReq_Rx: DMA接收请求 + * @param NewState :ENABLE or DISABLE + */ +void SPI_DMACmd(SPI_TypeDef* SPIx, uint32_t SPI_DMAReq, FunctionalState NewState) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DMAREQ(SPI_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SPIx->CR2 |= SPI_DMAReq; + } + else + { + SPIx->CR2 &= ~SPI_DMAReq; + } +} + +/** + * @brief 软件内部配置NSS + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1 + * @param SPI_NSSInternalSoft :NSS状态 + * 参数可以是： + * @arg SPI_NSSInternalSoft_Set: Set NSS + * @arg SPI_NSSInternalSoft_Reset: Reset NSS + * @note + * -SPI_CR1.SSM = 1时有效，即软件NSS(SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) + * -主机时：0 - CS输出低 1 - CS输出高 + * -从机时：0 - 本机被选中 1 - 本机未被选中 + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint8_t SPI_NSSInternalSoft) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + + SPIx->SSI = SPI_NSSInternalSoft; +} + +/** + * @brief 设置数据帧的位宽 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1 + * @param SPI_DataSize :数据帧宽度 + * 参数可以是： + * @arg SPI_DataSize_4b + * @arg SPI_DataSize_5b + * @arg SPI_DataSize_6b + * @arg SPI_DataSize_7b + * @arg SPI_DataSize_8b + * @arg SPI_DataSize_9b + * @arg SPI_DataSize_10b + * @arg SPI_DataSize_11b + * @arg SPI_DataSize_12b + * @arg SPI_DataSize_13b + * @arg SPI_DataSize_14b + * @arg SPI_DataSize_15b + * @arg SPI_DataSize_16b + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + + REGBITS_MODIFY(SPIx->CR1, SPIx_CR1_WIDTH_Msk, SPI_DataSize); +} + +/** + * @brief 从模式MISO输出配置 + * + * @param SPIx :SPIx外设 + * 参数可以是: + * CW_SPI1 + * @param SPI_MISOOutput :MISO输出配置 + * 参数可以是： + * @arg SPI_MISOOutput_HD: 从机被选中时 MISO 为 COMS 输出，未被选中时为高阻输出 + * @arg SPI_MISOOutput_CMOS: MISO 始终为 COMS 输出 + */ +void SPI_MISOOutputConfig(SPI_TypeDef* SPIx, uint8_t SPI_MISOOutput) +{ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_MISOOUTPUT(SPI_MISOOutput)); + + SPIx->CR1_f.MISOHD = SPI_MISOOutput; +} + +/** + * @brief 清空发送缓冲区和移位寄存器 + * + */ +void SPI_FlushSendBuff(SPI_TypeDef* SPIx) +{ + SPIx->ICR_f.FLUSH=0; +} + + + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_sysctrl.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_sysctrl.c new file mode 100644 index 0000000..e7c5277 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_sysctrl.c @@ -0,0 +1,1090 @@ +/** + * @file cw32l012_sysctrl.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_sysctrl.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +const uint32_t hsiprs_tbl[] = {32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 16, 20, 24, 28}; +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief 配置SysClk 到 HCLK的分频系数 + * + * @param HCLKPRS ：SYSCTRL_HCLK_DIV1/2/4/8/16/32/64/128 + */ +void SYSCTRL_HCLKPRS_Config(uint32_t HCLKPRS) +{ + assert_param(IS_SYSCTRL_HCLKPRS(HCLKPRS)); + CW_SYSCTRL->CR0 = ((CW_SYSCTRL->CR0 & (~(SYSCTRL_KEY_MASK | SYSCTRL_CR0_HCLKPRS_Msk))) | SYSCTRL_KEY | HCLKPRS); +} +/** + * @brief 配置HCLK 到 PCLK的分频系数 + * + * @param PCLKPRS ：SYSCTRL_PCLK_DIV1/2/4/8 + */ +void SYSCTRL_PCLKPRS_Config(uint32_t PCLKPRS) +{ + assert_param(IS_SYSCTRL_HCLKPRS(PCLKPRS)); + CW_SYSCTRL->CR0 = ((CW_SYSCTRL->CR0 & (~(SYSCTRL_KEY_MASK | SYSCTRL_CR0_PCLKPRS_Msk))) | SYSCTRL_KEY | PCLKPRS); +} + +/** + * @brief 配置SysClk的时钟源 + * + * @param SYSCLKSRC ：SYSCTRL_SYSCLKSRC_HSI SYSCTRL_SYSCLKSRC_HSE SYSCTRL_SYSCLKSRC_PLL + * SYSCTRL_SYSCLKSRC_LSI SYSCTRL_SYSCLKSRC_LSE + */ +void SYSCTRL_SYSCLKSRC_Config(uint32_t SYSCLKSRC) +{ + assert_param(IS_SYSCTRL_SYSCLKSRC(SYSCLKSRC)); + CW_SYSCTRL->CR0 = ((CW_SYSCTRL->CR0 & (~(SYSCTRL_KEY_MASK | SYSCTRL_CR0_SYSCLK_Msk))) | SYSCTRL_KEY | SYSCLKSRC); + SYSCTRL_SystemCoreClockUpdate(SYSCTRL_GetHClkFreq()); +} + +/** + * @brief 配置CLKCCS LSECCS 功能 + * + * @param CCS ：SYSCTRL_LSECCSEN SYSCTRL_CLKCCSEN SYSCTRL_HSECCSEN + * @param NewState :ENABLE DISABLE + */ +void SYSCTRL_CCS_Config(uint32_t CCS, FunctionalState NewState) +{ + assert_param(IS_SYSCTRL_CCS_STATUS(CCS)); + + if (NewState != DISABLE) + { + CW_SYSCTRL->CR1 = (((CW_SYSCTRL->CR1 & (~SYSCTRL_KEY_MASK)) | SYSCTRL_KEY) | CCS); + } + else + { + CW_SYSCTRL->CR1 = (((CW_SYSCTRL->CR1 & (~SYSCTRL_KEY_MASK)) | SYSCTRL_KEY) & (~CCS)); + } +} + +/** + * @brief 配置LSELOCK功能：使能后软件无法关闭LSE时钟 + * + * @param LSELOCK ： SYSCTRL_LSELOCKEN SYSCTRL_LSELOCKDIS + */ +void SYSCTRL_LSELOCK_Config(uint32_t LSELOCK) +{ + assert_param(IS_SYSCTRL_LSELOCK_STATUS(LSELOCK)); + CW_SYSCTRL->CR1 = ((CW_SYSCTRL->CR1 & (~SYSCTRL_KEY_MASK)) | SYSCTRL_KEY | LSELOCK); +} + +/** + * @brief 配置WAKEUPCLK功能:决定从深度休眠模式唤醒后所使用的系统时钟源 + * + * @param WAKEUPCLK ：SYSCTRL_WAKEUPCLKEN SYSCTRL_WAKEUPCLKDIS + */ +void SYSCTRL_WAKEUPCLK_Config(uint32_t WAKEUPCLK) +{ + assert_param(IS_SYSCTRL_WAKEUPCLK_STATUS(WAKEUPCLK)); + CW_SYSCTRL->CR2 = ((CW_SYSCTRL->CR2 & (~(SYSCTRL_KEY_MASK | SYSCTRL_CR2_WAKEUPCLK_Msk))) | SYSCTRL_KEY | WAKEUPCLK); +} + +/** + * @brief 配置LOCK功能：决定异常故障后是否产生LOCKUP复位 + * + * @param LOCKUP ：SYSCTRL_LOCKUPEN SYSCTRL_LOCKUPDIS + */ +void SYSCTRL_LOCKUP_Config(uint32_t LOCKUP) +{ + assert_param(IS_SYSCTRL_LOCKUP_STATUS(LOCKUP)); + CW_SYSCTRL->CR2 = ((CW_SYSCTRL->CR2 & (~(SYSCTRL_KEY_MASK | SYSCTRL_CR2_LOCKUP_Msk))) | SYSCTRL_KEY | LOCKUP); +} + +/** + * @brief 配置端口SWDIO功能 + * + * @param SWDIO ：SYSCTRL_SWDIOEN SYSCTRL_SWDIODIS + */ +void SYSCTRL_SWDIO_Config(uint32_t SWDIO) +{ + assert_param(IS_SYSCTRL_SWDIO_STATUS(SWDIO)); + CW_SYSCTRL->CR2 = ((CW_SYSCTRL->CR2 & (~(SYSCTRL_KEY_MASK | SYSCTRL_CR2_SWDIO_Msk))) | SYSCTRL_KEY | SWDIO); +} + +/** + * @brief Resets the SYSCTRL clock configuration to the default reset state. + * @param None + * @retval 0:success, 1:fault + * CAUTION: + * 1、LSEEN Bit Not Changed ,so it will not affect RTC,BUT LSELOCK BIT Changed. + * 2、Before CALL this funciton,we should set FLASH_CR2.WAT + */ +int SYSCTRL_DeInit(void) +{ + uint16_t timeout = 0xffff; + /* HSIEN Enable*/ + CW_SYSCTRL->CR1 = ((CW_SYSCTRL->CR1 & (~SYSCTRL_KEY_MASK)) | SYSCTRL_KEY | SYSCTRL_HSIEN); + + //Here need wait HSI STBALE + while (((CW_SYSCTRL->HSI & SYSCTRL_HSI_STABLE_Msk) == 0) && timeout) + { + timeout--; + } //Wait stable + + if (timeout == 0) return 1; + + /* SWITCH TO HSI*/ + CW_SYSCTRL->CR0 = ((CW_SYSCTRL->CR0 & (~SYSCTRL_KEY_MASK)) | SYSCTRL_KEY | SYSCTRL_SYSCLKSRC_HSI); + + /* HCLKPRS SET TO 000,PCLKPRS SET TO 00*/ + CW_SYSCTRL->CR0 = ((CW_SYSCTRL->CR0 & (~SYSCTRL_KEY_MASK)) | SYSCTRL_KEY | SYSCTRL_HCLK_DIV1 | \ + SYSCTRL_PCLK_DIV1 | SYSCTRL_SYSCLKSRC_HSI); + + /* CLKCCS/LSECCS/LSELOCK/LSIEN/HEXEN Disable CLKCCS / LSEEN NO CHANGE*/ + CW_SYSCTRL->CR1 = (((CW_SYSCTRL->CR1 & (~SYSCTRL_KEY_MASK)) | SYSCTRL_KEY | SYSCTRL_HSIEN) \ + & (~SYSCTRL_CLKCCSEN) & (~SYSCTRL_LSECCSEN) \ + & (~SYSCTRL_LSELOCKEN) & (~SYSCTRL_LSIEN) & (~SYSCTRL_HSEEN)); + + /* SWDIO Enable,LOCKUP/WAKEUPCLK Disable*/ + CW_SYSCTRL->CR2 = (((((CW_SYSCTRL->CR2 & (~SYSCTRL_KEY_MASK)) | SYSCTRL_KEY) \ + & (~SYSCTRL_SWDIOEN)) & (~SYSCTRL_LOCKUPEN)) & (~SYSCTRL_WAKEUPCLKEN)); + + /* Disable all interrupts */ + CW_SYSCTRL->IER = 0x5A5AFE00; //IER have KEY attribute + + /* Clear all pending bits */ + CW_SYSCTRL->ICR &= 0xFFFFFE00; + + return 0; + +} + +/** + * @brief + * + * @param NewFreq + */ +void SYSCTRL_SystemCoreClockUpdate(uint32_t NewFreq) +{ + SystemCoreClock = NewFreq; +} + +/** + * @brief 获得系统时钟（HCLK）频率值 + * + * @return uint32_t HCLK频率值(Hz) + */ +uint32_t SYSCTRL_GetHClkFreq(void) +{ + uint32_t u32rtnVal = 0; + uint32_t sysclksource = 0; + uint32_t hsiprs = 0; + uint32_t pll_div = 0; + uint32_t pll_src = 0; + uint32_t pll_mul = 0; + + sysclksource = CW_SYSCTRL->CR0_f.SYSCLK; + + switch (sysclksource) + { + case 0x00: /* HSI used as system clock */ + hsiprs = CW_SYSCTRL->HSI_f.DIV; + u32rtnVal = (HSIOSC_VALUE / hsiprs_tbl[hsiprs]); + break; + + case 0x01: /* HSE used as system clock */ + u32rtnVal = HSE_VALUE; + break; + + case 0x02: /* PLL used as system clock */ + pll_div = CW_SYSCTRL->PLL_f.DIV; + pll_src = CW_SYSCTRL->PLL_f.SOURCE; + pll_mul = CW_SYSCTRL->PLL_f.MUL; + + if (pll_src) // HSE + { + u32rtnVal = HSE_VALUE / (pll_div + 1) / 2 * pll_mul ; + } + else + { + u32rtnVal = HSIOSC_VALUE / 2 / (pll_div + 1) / 2 * pll_mul; + } + + break; + + case 0x03: /* LSI used as system clock */ + u32rtnVal = LSI_VALUE; + break; + + case 0x04: /* LSE used as system clock */ + u32rtnVal = LSE_VALUE; + break; + + default: + u32rtnVal = (HSIOSC_VALUE / hsiprs_tbl[hsiprs]); + break; + } + + u32rtnVal = (u32rtnVal >> CW_SYSCTRL->CR0_f.HCLKPRS); + return u32rtnVal; +} + +/** + * @brief 获得外设时钟（PCLK）频率值 + * + * @return uint32_t PCLK频率值(Hz) + */ +uint32_t SYSCTRL_GetPClkFreq(void) +{ + uint32_t u32Val = 0; + + u32Val = SYSCTRL_GetHClkFreq(); + u32Val = (u32Val >> (CW_SYSCTRL->CR0_f.PCLKPRS)); + return u32Val; +} + +/** +* @brief Enable HSI +* @param HSIDiv: +* SYSCTRL_HSIOSC_DIV1 +* SYSCTRL_HSIOSC_DIV2 +* SYSCTRL_HSIOSC_DIV3 +* SYSCTRL_HSIOSC_DIV4 +* SYSCTRL_HSIOSC_DIV5 +* SYSCTRL_HSIOSC_DIV6 +* SYSCTRL_HSIOSC_DIV7 +* SYSCTRL_HSIOSC_DIV8 +* SYSCTRL_HSIOSC_DIV9 +* SYSCTRL_HSIOSC_DIV10 +* SYSCTRL_HSIOSC_DIV12 +* SYSCTRL_HSIOSC_DIV16 +* SYSCTRL_HSIOSC_DIV20 +* SYSCTRL_HSIOSC_DIV24 +* SYSCTRL_HSIOSC_DIV28 +* SYSCTRL_HSIOSC_DIV32 +* +* @retval 0:success, 1:fault +*/ +int SYSCTRL_HSI_Enable(uint32_t HSIDiv) +{ +#if defined (HSI_STARTUP_TIMEOUT) + uint16_t timeout = HSI_STARTUP_TIMEOUT; +#else + uint16_t timeout = 0xffff; +#endif + + assert_param(IS_SYSCTRL_HSIOSC_DIV(HSIDiv)); + + if (HSIDiv == SYSCTRL_HSIOSC_DIV1) // 96MHz + { + REGBITS_SET(CW_SYSCTRL->CR2,0x5A5A0000 | bv4 | bv5); // 防止直接切入高速时钟时，FLASH没有加入等待周期，造成宕机 + } + else if (HSIDiv == SYSCTRL_HSIOSC_DIV2 || HSIDiv == SYSCTRL_HSIOSC_DIV3) // 24~48MHz + { + if (CW_SYSCTRL->HSI_f.DIV == 1) // 当前为96MHz，向低速切换，先降频，再改FLASH的等待配置 + { + CW_SYSCTRL->HSI = (HSIDiv) | ((*((volatile uint16_t*)SYSCTRL_HSI_TRIMCODEADDR)) & 0x7FF); + } + + REGBITS_SET(CW_SYSCTRL->CR2,0x5A5A0000 | bv4); // 防止直接切入高速时钟时，FLASH没有加入等待周期，造成宕机 + + } + else // <=24 + { + if (CW_SYSCTRL->HSI_f.DIV <= 3) // 向低速切换，先降频，再改FLASH的等待配置 + { + CW_SYSCTRL->HSI = (HSIDiv) | ((*((volatile uint16_t*)SYSCTRL_HSI_TRIMCODEADDR)) & 0x7FF); + } + + CW_SYSCTRL->CR2 = 0x5A5A0000 | (CW_SYSCTRL->CR2 & (~(0xFFFF0000|bv4|bv5|bv6))); + } + + CW_SYSCTRL->HSI = (HSIDiv) | ((*((volatile uint16_t*)SYSCTRL_HSI_TRIMCODEADDR)) & 0x7FF); + + CW_SYSCTRL->CR1 |= SYSCTRL_KEY | SYSCTRL_CR1_HSIEN_Msk; //Enable HSI + + while (((CW_SYSCTRL->HSI & SYSCTRL_HSI_STABLE_Msk) == 0) && timeout) + { + timeout--; + }//Wait stable + + if (timeout == 0) return 1; + + return 0; +} + +/** +* @brief Disable HSI +* @param None. +* @retval 0:success, 1:fault +*/ +void SYSCTRL_HSI_Disable(void) +{ + CW_SYSCTRL->CR1 = (((CW_SYSCTRL->CR1 & (~SYSCTRL_KEY_MASK)) | SYSCTRL_KEY) & \ + (~SYSCTRL_CR1_HSIEN_Msk)); +} + + +/** +* @brief Enable LSI +* @param None: +* @retval None +*/ +int SYSCTRL_LSI_Enable(void) +{ + uint16_t timeout = 0xffff; + + CW_SYSCTRL->LSI |= SYSCTRL_LSI_WAITCYCLE_258; //WaitCycle = 258 + CW_SYSCTRL->CR1 |= SYSCTRL_KEY | SYSCTRL_CR1_LSIEN_Msk; //Enable LSI + + while (((CW_SYSCTRL->LSI & SYSCTRL_LSI_STABLE_Msk) == 0) && timeout) + { + timeout--; + } //Wait stable + + if (timeout == 0) return 1; + + return 0; +} + +/** +* @brief Disable LSI +* @param None. +* @retval None. +*/ +void SYSCTRL_LSI_Disable(void) +{ + CW_SYSCTRL->CR1 = (((CW_SYSCTRL->CR1 & (~SYSCTRL_KEY_MASK)) | SYSCTRL_KEY) & \ + (~SYSCTRL_CR1_LSIEN_Msk)); +} + +/** +* @brief Set the HSE WAITCYCLE +* @param WaitClock: SYSCTRL_HSE_WAITCYCLE_8192,SYSCTRL_HSE_WAITCYCLE_32768, +* SYSCTRL_HSE_WAITCYCLE_131072, SYSCTRL_HSE_WAITCYCLE_262144 +* @retval None. +*/ +void SYSCTRL_HSEWaitClockSet(uint32_t WaitClock) +{ + + REGBITS_MODIFY(CW_SYSCTRL->HSE, SYSCTRL_HSE_WAITCYCLE_Msk, WaitClock); +} + +/** +* @brief Set the HEX enable pin polarity +* @param Polarity: SYSCTRL_HEX_ENPOL_HIGH,SYSCTRL_HEX_ENPOL_LOW +* +* @retval None. +*/ +void SYSCTRL_HEXEnablePinPolSet(uint32_t Polarity) +{ + // HEXEN pin PA05 + CW_SYSCTRL->AHBEN |= SYSCTRL_KEY | SYSCTRL_AHBEN_GPIOA_Msk; + CW_GPIOA->DIR_f.PIN5 = 0; + CW_GPIOA->ANALOG_f.PIN5 = 0; + CW_GPIOA->AFRL_f.PIN5 = 5; + + REGBITS_MODIFY(CW_SYSCTRL->HSE, SYSCTRL_HSE_HEXENPOL_Msk, Polarity); +} + +/** +* @brief Enable HSE +* @param Mode: SYSCTRL_HSE_MODE_OSC: Oscillator, +* SYSCTRL_HSE_MODE_CLK: Input Clk +* +* @param FreqIn: 4000000Hz ~ 32000000Hz +* +* @param Driver: SYSCTRL_HSE_DRIVER_LEVEL0~SYSCTRL_HSE_DRIVER_LEVEL9 0:最小 +* +* @param Flt: SYSCTRL_HSE_FLT_OPEN, +* SYSCTRL_HSE_FLT_CLOSE +* +* @retval None + +注意：1、选择负载电容小的晶体更容易起振。 +2、Flt: 强干扰环境打开,一般不打开 +*/ +int SYSCTRL_HSE_Enable(uint32_t Mode, uint32_t FreqIn, uint8_t Driver, uint32_t Flt) +{ + uint16_t timeout = 0xffff; + uint16_t AHBEN_GPIO_Msk; + //参数断言 + assert_param(IS_SYSCTRL_HSE_MODE(Mode)); + + //根据HSE模式设置IO口功能 + if (HSE_PIN_PORT == CW_GPIOA) + { + AHBEN_GPIO_Msk = SYSCTRL_AHBEN_GPIOA_Msk; + } + else if (HSE_PIN_PORT == CW_GPIOB) + { + AHBEN_GPIO_Msk = SYSCTRL_AHBEN_GPIOB_Msk; + } + else if (HSE_PIN_PORT == CW_GPIOC) + { + AHBEN_GPIO_Msk = SYSCTRL_AHBEN_GPIOC_Msk; + } + else if (HSE_PIN_PORT == CW_GPIOF) + { + AHBEN_GPIO_Msk = SYSCTRL_AHBEN_GPIOF_Msk; + } + + CW_SYSCTRL->AHBEN |= SYSCTRL_KEY | AHBEN_GPIO_Msk; //Open GPIO Clk + + if (Mode == SYSCTRL_HSE_MODE_OSC) //Oscillator + { + HSE_PIN_PORT->ANALOG |= HSE_PIN_IN | HSE_PIN_OUT; + } + else //Input clk + { + CW_GPIOA->ANALOG &= ~HSE_PIN_IN; + CW_GPIOA->DIR |= HSE_PIN_IN; + CW_GPIOA->PUR &= ~HSE_PIN_IN; + } + + //设置HSE参数 + CW_SYSCTRL->HSE = 0x00200000 /* PDRIVER = 01 */ | ((8000000000 / FreqIn) << SYSCTRL_HSE_DETCNT_Pos) | \ + (Mode) | \ + (SYSCTRL_HSE_WAITCYCLE_131072) | \ + (Driver) | \ + (Flt); + //使能HSE,同时使能CLKCCS和HSECCS，使能时钟失效切换 + CW_SYSCTRL->CR1 |= SYSCTRL_KEY | SYSCTRL_CR1_CLKCCS_Msk | SYSCTRL_CR1_HSECCS_Msk | SYSCTRL_CR1_HSEEN_Msk; //Enable HSE + + //等待HSE稳定 + while (((CW_SYSCTRL->HSE & SYSCTRL_HSE_STABLE_Msk) != SYSCTRL_HSE_STABLE_Msk) && timeout) + { + timeout--; //Wait stable + } + + if (timeout == 0) return 1; + + return 0; +} + +/** +* @brief Disable HSE +* @param None. +* @retval None. +*/ +void SYSCTRL_HSE_Disable(void) +{ + CW_SYSCTRL->CR1 = (((CW_SYSCTRL->CR1 & (~ SYSCTRL_CR1_KEY_Msk)) | SYSCTRL_KEY) & \ + (~SYSCTRL_CR1_HSEEN_Msk)); +} + + +/** +* @brief Enable LSE +* @param Mode: SYSCTRL_LSE_MODE_OSC: Oscillator, +* SYSCTRL_LSE_MODE_CLK: Input Clk +* @param Driver: SYSCTRL_LSE_DRIVER_LEVEL0~15 +* +* @retval 0：succes， 1：fault + +驱动配置建议： +Driver：SYSCTRL_LSE_DRIVER_LEVEL2 +*/ + +int SYSCTRL_LSE_Enable(uint32_t Mode, uint8_t Driver) +{ + uint32_t timeout = 0x4ffff; + uint16_t AHBEN_GPIO_Msk; + //参数断言 + assert_param(IS_SYSCTRL_LSE_MODE(Mode)); + assert_param(IS_SYSCTRL_LSE_DRIVER(Driver)); + + //根据LSE模式，设置IO功能 + if (LSE_PIN_PORT == CW_GPIOA) + { + AHBEN_GPIO_Msk = SYSCTRL_AHBEN_GPIOA_Msk; + } + else if (LSE_PIN_PORT == CW_GPIOB) + { + AHBEN_GPIO_Msk = SYSCTRL_AHBEN_GPIOB_Msk; + } + else if (LSE_PIN_PORT == CW_GPIOC) + { + AHBEN_GPIO_Msk = SYSCTRL_AHBEN_GPIOC_Msk; + } + else if (LSE_PIN_PORT == CW_GPIOF) + { + AHBEN_GPIO_Msk = SYSCTRL_AHBEN_GPIOF_Msk; + } + + CW_SYSCTRL->AHBEN |= SYSCTRL_KEY | AHBEN_GPIO_Msk; + + if (Mode == SYSCTRL_LSE_MODE_OSC) //Oscillator + { + LSE_PIN_PORT->ANALOG |= LSE_PIN_IN | LSE_PIN_OUT; + } + else //Input clk + { + LSE_PIN_PORT->ANALOG &= ~LSE_PIN_IN; + LSE_PIN_PORT->DIR |= LSE_PIN_IN; + LSE_PIN_PORT->PUR &= LSE_PIN_IN; + } + + //设置LSE参数 + CW_SYSCTRL->LSE = 0x00000A20 | (Mode) | (Driver); + + //LSE使能,同时使能CLKCCS和LSECCS，使能时钟失效切换 + CW_SYSCTRL->CR1 |= SYSCTRL_KEY | SYSCTRL_CLKCCSEN | SYSCTRL_CR1_LSECCS_Msk | SYSCTRL_CR1_LSEEN_Msk; //Enable LSE + + //等待LSE稳定 + while ((CW_SYSCTRL->LSE_f.STABLE == 0) && timeout) + { + timeout--; + }//Wait stable + + if (timeout == 0) return 1; + + return 0; +} + +/** +* @brief Disable LSE +* @param None +* @retval None +*/ +void SYSCTRL_LSE_Disable(void) +{ + CW_SYSCTRL->CR1 = (((CW_SYSCTRL->CR1 & (~SYSCTRL_KEY_MASK)) | SYSCTRL_KEY) & \ + (~SYSCTRL_CR1_LSEEN_Msk)); +} + +/** +* @brief Enable PLL +* @param PLL_InitStruct: +* .ClockSource SYSCTRL_PLL_SOURCE_HSI_48M, SYSCTRL_PLL_SOURCE_HSE +* .SourceFreq <= 80 000 000Hz +* .PLL_OutFreq 36000000 <= PLL_OutFreq<= 96 000 000Hz +* .WaitCycle SYSCTRL_PLL_WAIT_CYCLE_128~16384 +* @retval 0:success, 1:fault +*/ + +int SYSCTRL_PLL_Enable(PLL_InitTypeDef *PLL_InitStruct) +{ + uint8_t i, j, mul, div,mul_array[60], mul_tmp, div_tmp; + uint16_t timeout = 0xffff; + uint32_t res, div_res, diff_tmp, diff = 0xFFFFFFFF; + + #define ABS(a,b) (a)>(b) ? (a)-(b): (b)-(a) + // 计算mul + for (i = 0, mul = 24; ; mul++) + { + res = PLL_InitStruct->PLL_OutFreq / mul; + + if (res > 2500000) + { + continue; + } + + if (res < 1500000) + { + break; + } + + mul_array[i] = mul; + i++; + } + + for (j = 0; j < i; j++) + { + mul_tmp = mul_array[j]; + res = PLL_InitStruct->PLL_OutFreq / mul_tmp; + res <<= 1; + + for (div_tmp = 0; div_tmp < 16; div_tmp++) + { + div_res = PLL_InitStruct->SourceFreq / (div_tmp + 1); + + if (div_res == res) + { + div = div_tmp; + mul = mul_tmp; + + goto RESULT; + } + diff_tmp = ABS(res, div_res); + if (diff_tmp < diff) + { + diff = diff_tmp; + div = div_tmp; + mul = mul_tmp; + } + } + } + +RESULT: + // 停止PLL + CW_SYSCTRL->CR1 = (CW_SYSCTRL->CR1 & (~SYSCTRL_CR1_PLLEN_Msk)) | SYSCTRL_KEY; + + //设置PLL参数 + CW_SYSCTRL->PLL = PLL_InitStruct->WaitCycle | \ + mul << SYSCTRL_PLL_MUL_Pos | \ + div << SYSCTRL_PLL_DIV_Pos | \ + PLL_InitStruct->ClockSource; + + //使能PLL + CW_SYSCTRL->CR1 |= SYSCTRL_KEY | SYSCTRL_CR1_PLLEN_Msk; //Enable PLL + + //等待PLL时钟稳定 + while (((CW_SYSCTRL->PLL & SYSCTRL_PLL_STABLE_Msk) != SYSCTRL_PLL_STABLE_Msk) && timeout) + { + timeout--; + } + + if (timeout == 0) return 1; + + return 0; +} + +/** +* @brief Disable PLL +* @param None +* @retval None +*/ +void SYSCTRL_PLL_Disable(void) +{ + CW_SYSCTRL->CR1 = (CW_SYSCTRL->CR1 & (~SYSCTRL_CR1_PLLEN_Msk)) | SYSCTRL_KEY; +} + + + +/** +* @brief CLKSRC switch +* @param NewClk: +* SYSCTRL_SYSCLKSRC_HSI, +* SYSCTRL_SYSCLKSRC_HSE, +* SYSCTRL_SYSCLKSRC_LSI, +* SYSCTRL_SYSCLKSRC_LSE +* @retval 0: PASS, 1: Fail +* +* NOTE:调用此函数之前需要保证新时钟源已经使能（ENABLE函数中已包含等待时钟稳定过程）。 +*/ + +int SYSCTRL_SysClk_Switch(uint32_t NewClk) +{ + assert_param(IS_SYSCTRL_SYSCLKSRC(NewClk)); + + switch (NewClk) + { + default: + case SYSCTRL_SYSCLKSRC_HSI: + if ((CW_SYSCTRL->ISR_f.HSIRDY == 0) || (CW_SYSCTRL->ISR_f.HSISTABLE == 0)) + return 1; + + break; + + case SYSCTRL_SYSCLKSRC_HSE: + if (CW_SYSCTRL->ISR_f.HSESTABLE == 0) + return 1; + + break; + + case SYSCTRL_SYSCLKSRC_PLL: + if (CW_SYSCTRL->ISR_f.PLLSTABLE == 0) + return 1; + + break; + + case SYSCTRL_SYSCLKSRC_LSI: + if ((CW_SYSCTRL->ISR_f.LSIRDY == 0) || (CW_SYSCTRL->ISR_f.LSISTABLE == 0)) + return 1; + + break; + + case SYSCTRL_SYSCLKSRC_LSE: + if ((CW_SYSCTRL->ISR_f.LSEFAIL == 1) || (CW_SYSCTRL->ISR_f.LSERDY == 0) || \ + (CW_SYSCTRL->ISR_f.LSESTABLE == 0) || (CW_SYSCTRL->ISR_f.LSEFAIL == 1)) + return 1; + + break; + } + + CW_SYSCTRL->CR0 = (CW_SYSCTRL->CR0 & (~SYSCTRL_CR0_SYSCLK_Msk)) | (NewClk) | SYSCTRL_KEY; + + SYSCTRL_SystemCoreClockUpdate(SYSCTRL_GetHClkFreq()); + + return (((CW_SYSCTRL->CR0 & SYSCTRL_CR0_SYSCLK_Msk) == NewClk) ? 0U : 1U); +} + +/** + * @brief SYSCTRL中断配置 + * + * @param SYSCTRL_IT ：SYSCTRL_IT_LSEFAULT SYSCTRL_IT_LSEFAIL + * SYSCTRL_IT_LSERDY SYSCTRL_IT_LSIRDY + * SYSCTRL_IT_HSIRDY + * @param NewState :ENABLE DISABLE + */ +void SYSCTRL_ITConfig(uint32_t SYSCTRL_IT, FunctionalState NewState) +{ + assert_param(IS_SYSCTRL_IT(SYSCTRL_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) //IER have KEY attribute + { + CW_SYSCTRL->IER = ((CW_SYSCTRL->IER & (~SYSCTRL_KEY_MASK)) | SYSCTRL_KEY) | SYSCTRL_IT; + } + else //IER have KEY attribute + { + CW_SYSCTRL->IER = ((CW_SYSCTRL->IER & (~SYSCTRL_KEY_MASK)) | SYSCTRL_KEY) & (~SYSCTRL_IT); + } +} + +/** + * @brief 获取SYSCTRL指定中断状态 + * + * @param SYSCTRL_IT ： SYSCTRL_IT_LSEFAULT SYSCTRL_IT_LSEFAIL + * SYSCTRL_IT_LSERDY SYSCTRL_IT_LSIRDY + * SYSCTRL_IT_HSIRDY + * + * @return ITStatus : SET RESET + */ +ITStatus SYSCTRL_GetITStatus(uint32_t SYSCTRL_IT) +{ + assert_param(IS_SYSCTRL_GET_IT(SYSCTRL_IT)); + + return (CW_SYSCTRL->ISR & SYSCTRL_IT) ? SET : RESET; +} + + +/** + * @brief 清除SYSCTRL指定中断标志 + * + * @param SYSCTRL_IT ：SYSCTRL_IT_LSEFAULT SYSCTRL_IT_LSEFAIL + * SYSCTRL_IT_LSERDY SYSCTRL_IT_LSIRDY + * SYSCTRL_IT_HSIRDY + * + */ +void SYSCTRL_ClearITPendingBit(uint32_t SYSCTRL_IT) +{ + assert_param(IS_SYSCTRL_GET_IT(SYSCTRL_IT)); + + CW_SYSCTRL->ICR &= (~SYSCTRL_IT); +} + +/** + * @brief 获取指定时钟源稳定标志 + * + * @param SYSCTRL_STABLEFLAG ：SYSCTRL_FLAG_HSISTABLE SYSCTRL_FLAG_HEXSTABLE + * SYSCTRL_FLAG_LSESTABLE + * SYSCTRL_FLAG_LSISTABLE + * @return FlagStatus ：SET RESET + */ +FlagStatus SYSCTRL_GetStableFlag(uint32_t SYSCTRL_STABLEFLAG) +{ + assert_param(IS_SYSCTRL_STABLEFLAG(SYSCTRL_STABLEFLAG)); + + return (((CW_SYSCTRL->ISR) & SYSCTRL_STABLEFLAG) ? SET : RESET); +} + +/** + * @brief 获取所有时钟源稳定标志 + * + * @return uint32_t ：返回ISR寄存器内容 + */ +uint32_t SYSCTRL_GetAllStableFlag(void) +{ + return (CW_SYSCTRL->ISR); +} + + +/** + * @brief AHB外设时钟设置 + * + * @param Periph ：SYSCTRL_AHB_PERIPH_GPIOA SYSCTRL_AHB_PERIPH_GPIOB + * SYSCTRL_AHB_PERIPH_CRC SYSCTRL_AHB_PERIPH_FLASH + * @param NewState ENABLE DISABLE + */ +void SYSCTRL_AHBPeriphClk_Enable(uint32_t Periph, FunctionalState NewState) +{ + assert_param(IS_SYSCTRL_AHB_PERIPH(Periph)); + + if (NewState != DISABLE) + { + CW_SYSCTRL->AHBEN |= SYSCTRL_KEY | Periph; + } + else + { + CW_SYSCTRL->AHBEN = SYSCTRL_KEY | (CW_SYSCTRL->AHBEN & (~Periph)); + } +} + +/** + * @brief APB外设时钟设置1 + * + * @param Periph ： SYSCTRL_APB1_PERIPH_ATIM SYSCTRL_APB1_PERIPH_GTIM1 + * SYSCTRL_APB1_PERIPH_UART2 SYSCTRL_APB1_PERIPH_UART1 + * SYSCTRL_APB1_PERIPH_SPI SYSCTRL_APB1_PERIPH_VC + * SYSCTRL_APB1_PERIPH_ADC + * @param NewState ENABLE DISABLE + */ +void SYSCTRL_APBPeriphClk_Enable1(uint32_t Periph, FunctionalState NewState) +{ + assert_param(IS_SYSCTRL_APB1_PERIPH(Periph)); + + if (NewState != DISABLE) + { + CW_SYSCTRL->APBEN1 |= SYSCTRL_KEY | Periph; + } + else + { + CW_SYSCTRL->APBEN1 = SYSCTRL_KEY | (CW_SYSCTRL->APBEN1 & (~Periph)); + } +} + +/** + * @brief APB外设时钟设置2 + * + * @param Periph ： SYSCTRL_APB2_PERIPH_I2C SYSCTRL_APB2_PERIPH_LPTIM + * SYSCTRL_APB2_PERIPH_IWDT SYSCTRL_APB2_PERIPH_RTC + * SYSCTRL_APB2_PERIPH_BTIM123 + * @param NewState : ENABLE DISABLE + */ +void SYSCTRL_APBPeriphClk_Enable2(uint32_t Periph, FunctionalState NewState) +{ + assert_param(IS_SYSCTRL_APB2_PERIPH(Periph)); + + if (NewState != DISABLE) + { + CW_SYSCTRL->APBEN2 |= SYSCTRL_KEY | Periph; + } + else + { + CW_SYSCTRL->APBEN2 = SYSCTRL_KEY | (CW_SYSCTRL->APBEN2 & (~Periph)); + } +} + +/** + * @brief AHB外设复位设置 + * + * @param Periph ：SYSCTRL_AHB_PERIPH_GPIOA SYSCTRL_AHB_PERIPH_GPIOB + * SYSCTRL_AHB_PERIPH_CRC SYSCTRL_AHB_PERIPH_FLASH + * @param NewState : ENABLE DISABLE + */ +void SYSCTRL_AHBPeriphReset(uint32_t Periph, FunctionalState NewState) +{ + assert_param(IS_SYSCTRL_AHB_PERIPH(Periph)); + + if (NewState != DISABLE) + { + CW_SYSCTRL->AHBRST |= Periph; + } + else + { + CW_SYSCTRL->AHBRST &= (~Periph); + } +} + +/** + * @brief APB外设复位设置1 + * + * @param Periph ： SYSCTRL_APB1_PERIPH_ATIM SYSCTRL_APB1_PERIPH_GTIM1 + * SYSCTRL_APB1_PERIPH_UART2 SYSCTRL_APB1_PERIPH_UART1 + * SYSCTRL_APB1_PERIPH_SPI1 SYSCTRL_APB1_PERIPH_VC + * SYSCTRL_APB1_PERIPH_ADC + * @param NewState : ENABLE DISABLE + */ +void SYSCTRL_APBPeriphReset1(uint32_t Periph, FunctionalState NewState) +{ + assert_param(IS_SYSCTRL_APB1_PERIPH(Periph)); + + if (NewState != ENABLE) + { + CW_SYSCTRL->APBRST1 |= Periph; + } + else + { + CW_SYSCTRL->APBRST1 &= (~Periph); + } +} + +/** + * @brief APB外设复位设置2 + * + * @param Periph ： SYSCTRL_APB2_PERIPH_I2C SYSCTRL_APB2_PERIPH_LPTIM + * SYSCTRL_APB2_PERIPH_IWDT SYSCTRL_APB2_PERIPH_RTC + * SYSCTRL_APB2_PERIPH_BTIM123 + * @param NewState : ENABLE DISABLE + */ +void SYSCTRL_APBPeriphReset2(uint32_t Periph, FunctionalState NewState) +{ + assert_param(IS_SYSCTRL_APB1_PERIPH(Periph)); + + if (NewState != ENABLE) + { + CW_SYSCTRL->APBRST2 |= Periph; + } + else + { + CW_SYSCTRL->APBRST2 &= (~Periph); + } +} + +/** + * @brief 获取指定的系统复位标志 + * + * @param SYSCTRL_RSTFLAG ：SYSCTRL_FLAG_PORRST SYSCTRL_FLAG_SYSRESETREQRST + * SYSCTRL_FLAG_LVDRST SYSCTRL_FLAG_LOCKUPRST + * SYSCTRL_FLAG_IWDTRST SYSCTRL_FLAG_RSTBRST + * @return FlagStatus SET RESET + */ +FlagStatus SYSCTRL_GetRstFlag(uint32_t SYSCTRL_RSTFLAG) +{ + assert_param(IS_SYSCTRL_RSTFLAG(SYSCTRL_RSTFLAG)); + + return (((CW_SYSCTRL->RESETFLAG) & SYSCTRL_RSTFLAG) ? SET : RESET); +} + +/** + * @brief 获取复位标志寄存器内容 + * + * @return uint32_t + */ +uint32_t SYSCTRL_GetAllRstFlag(void) +{ + return (CW_SYSCTRL->RESETFLAG); +} + +/** + * @brief 清除指定或者全部复位标志 + * + * @param SYSCTRL_RSTFLAG ：SYSCTRL_FLAG_PORRST SYSCTRL_FLAG_SYSRESETREQRST + * SYSCTRL_FLAG_LVDRST SYSCTRL_FLAG_LOCKUPRST + * SYSCTRL_FLAG_IWDTRST SYSCTRL_FLAG_RSTBRST + * @return + */ +void SYSCTRL_ClearRstFlag(uint32_t SYSCTRL_RSTFLAG) +{ + assert_param(IS_SYSCTRL_RSTFLAG(SYSCTRL_RSTFLAG)); + CW_SYSCTRL->RESETFLAG &= (~SYSCTRL_RSTFLAG); +} + +/** + * @brief 配置PCLK_OUT引脚(PA02)输出PCLK时钟 + * + */ +void SYSCTRL_PCLK_OUT(void) +{ + int16_t AHBEN_GPIO_Msk; + + if (PCLK_OUT_PIN_PORT == CW_GPIOA) + { + AHBEN_GPIO_Msk = SYSCTRL_AHBEN_GPIOA_Msk; + } + else if (PCLK_OUT_PIN_PORT == CW_GPIOB) + { + AHBEN_GPIO_Msk = SYSCTRL_AHBEN_GPIOB_Msk; + } + else if (PCLK_OUT_PIN_PORT == CW_GPIOC) + { + AHBEN_GPIO_Msk = SYSCTRL_AHBEN_GPIOC_Msk; + } + else if (PCLK_OUT_PIN_PORT == CW_GPIOF) + { + AHBEN_GPIO_Msk = SYSCTRL_AHBEN_GPIOF_Msk; + } + + CW_SYSCTRL->AHBEN |= SYSCTRL_KEY | AHBEN_GPIO_Msk; + PCLK_OUT_PIN_PORT->ANALOG &= ~PCLK_OUT_PIN; //Digit + PCLK_OUT_PIN_PORT->DIR &= ~PCLK_OUT_PIN; //Output + GPIO_SetAlternateFunction(PCLK_OUT_PIN_PORT, PCLK_OUT_PIN, PCLK_OUT_PIN_AF); +} + +/** + * @brief 配置MCO_OUT引脚(PA04)输出指定的时钟源及分频比 + * + * @param Source ：SYSCTRL_MCO_SRC_NONE SYSCTRL_MCO_SRC_HCLK + * SYSCTRL_MCO_SRC_PCLK SYSCTRL_MCO_SRC_HSI + * SYSCTRL_MCO_SRC_LSI SYSCTRL_MCO_SRC_HSE + * SYSCTRL_MCO_SRC_LSE + * + * @param Div ：SYSCTRL_MCO_DIV1/2/8/64/128/256/512/1024 + */ +void SYSCTRL_MCO_OUT(uint8_t Source, uint8_t Div) +{ + uint16_t AHBEN_GPIO_Msk; + + assert_param(IS_SYSCTRL_MCO_SRC(Source)); + assert_param(IS_SYSCTRL_MCO_DIV(Div)); + + if (MCO_PIN_PORT == CW_GPIOA) + { + AHBEN_GPIO_Msk = SYSCTRL_AHBEN_GPIOA_Msk; + } + else if (MCO_PIN_PORT == CW_GPIOB) + { + AHBEN_GPIO_Msk = SYSCTRL_AHBEN_GPIOB_Msk; + } + else if (MCO_PIN_PORT == CW_GPIOC) + { + AHBEN_GPIO_Msk = SYSCTRL_AHBEN_GPIOC_Msk; + } + else if (MCO_PIN_PORT == CW_GPIOF) + { + AHBEN_GPIO_Msk = SYSCTRL_AHBEN_GPIOF_Msk; + } + + CW_SYSCTRL->AHBEN |= SYSCTRL_KEY | AHBEN_GPIO_Msk; + MCO_PIN_PORT->ANALOG &= ~MCO_PIN; //Digit + MCO_PIN_PORT->DIR &= ~MCO_PIN; //Output + GPIO_SetAlternateFunction(MCO_PIN_PORT, MCO_PIN, MCO_PIN_AF); + + CW_SYSCTRL->MCO = (uint32_t)(Source | Div); +} +void SYSCTRL_GotoSleep(void) +{ + SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); + __DSB(); + __WFI(); +} + +void SYSCTRL_GotoDeepSleep(void) +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __WFI(); +} + +void SYSCTRL_ConfigSleepOnExit(FunctionalState state) +{ + if (state == ENABLE) + { + SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; + } + else + { + SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; + } +} diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_systick.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_systick.c new file mode 100644 index 0000000..7a0d179 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_systick.c @@ -0,0 +1,169 @@ +/** + * @file cw32l012_systick.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ + +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_systick.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +TickFreqTypeDef uwTickFreq = TICK_FREQ_DEFAULT; /* 1KHz */ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_SYSCTRL_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __Weak to be overwritten in case of other + * implementation in user file. + * @param system hclk freq. + * @retval HAL status + */ +__WEAK void InitTick(uint32_t HclkFreq) +{ + + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (SysTick_Config(HclkFreq / (1000U / uwTickFreq)) > 0U) + { + return ; + } + + /* Configure the SysTick IRQ priority */ + if (TICK_INT_PRIORITY < (1UL << __NVIC_PRIO_BITS)) + { + NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY); + uwTickPrio = TICK_INT_PRIORITY; + } + else + { + return ; + } + +} + + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __WEAK to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__WEAK uint32_t GetTick(void) +{ + return uwTick; +} + + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note ThiS function is declared as __WEAK to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__WEAK void SysTickDelay(uint32_t Delay) +{ + uint32_t tickstart = GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < MAX_SYSTICK_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while((GetTick() - tickstart) < wait) + { + } +} + + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __WEAK to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__WEAK void SuspendTick(void) + +{ + /* Disable SysTick Interrupt */ + REGBITS_CLR(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __WEAK to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__WEAK void ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + REGBITS_SET(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn */ + uwTick += uwTickFreq; + /* USER CODE END SysTick_IRQn */ +} diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_uart.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_uart.c new file mode 100644 index 0000000..35ac2b5 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_uart.c @@ -0,0 +1,1164 @@ +/** + * @file cw32l012_uart.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2022 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_uart.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ +volatile boolean_t txComplete = TRUE; +volatile boolean_t rxComplete = TRUE; +volatile uint8_t *rxDataPtr; +volatile uint8_t *txDataPtr; +volatile uint32_t rxDataLen; +volatile uint32_t txDataLen; +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief 通过UARTx发送一个数据(8bit/9bit) + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param Data :待发送的数据 + */ +void UART_SendData(UART_TypeDef* UARTx, uint16_t Data) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + UARTx->TDR = Data; +} + +/** + * @brief 发送字符串 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param String :待发送的字符串 + */ +void UART_SendString(UART_TypeDef* UARTx, char* String) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + while (*String != '\0') + { + UARTx->TDR = *String; + while (!UARTx->ISR_f.TXE); + String++; + } + while (UARTx->ISR_f.TXBUSY); +} + +/** + * @brief 通过UARTx接收一个数据(8bit/9bit) + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @return uint16_t :接收的数据 + */ +uint16_t UART_ReceiveData(UART_TypeDef* UARTx) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + return UARTx->RDR; +} + +/** + * @brief 发送一组数据 + * + * @param UARTx :UARTx外设 + * 参数可以是: CW_UART1、CW_UART2、CW_UART3 + * @param String :发送的字符串 + * @param length :发送字符串的长度 + */ +UART_StatusTypeDef UART_TransmitPolling(UART_TypeDef* UARTx, uint8_t *Data, uint32_t length) +{ + UART_StatusTypeDef status = UART_STATUS_OK; + // 检查传入的UART外设参数是否合法 + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + // 检查传入的数据指针是否为空 + if (Data == NULL) + { + return UART_STATUS_ERROR; + } + + if (UARTx->ISR_f.TXBUSY) + { + return UART_STATUS_BUSY; + } + + UARTx->CR1_f.TXEN = 1; + while (length > 0) + { + UARTx->TDR = *Data; + while (!UARTx->ISR_f.TXE); + Data++; + length--; + } + while (UARTx->ISR_f.TXBUSY); + UARTx->CR1_f.TXEN = 0; + return status; +} + +UART_StatusTypeDef UART_ReceivePolling(UART_TypeDef* UARTx, uint8_t *Data, uint32_t length) +{ + UART_StatusTypeDef status = UART_STATUS_OK; + // 检查传入的UART外设参数是否合法 + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + // 检查传入的数据指针是否为空 + if (Data == NULL) + { + return UART_STATUS_ERROR; + } + + UARTx->ICR_f.RC = 0; + UARTx->CR1_f.RXEN = 1; + while (length > 0) + { + while (!UARTx->ISR_f.RC); + *Data = UARTx->RDR; + Data++; + length--; + UARTx->ICR_f.RC = 0; + } + UARTx->CR1_f.RXEN = 0; + return status; +} + +/** + * @brief 通过UARTx以中断方式发送数据 + * + * @param UARTx : UARTx外设，参数可以是 CW_UART1、CW_UART2、CW_UART3 等 + * @param Data : 待发送数据的指针 + * @param length : 待发送数据的个数 + * @note 中断服务函数中需要完成数据的再次发送和标志位的清除 + */ +UART_StatusTypeDef UART_TransmitInterrupt(UART_TypeDef* UARTx, uint8_t *Data, uint32_t length) +{ + UART_StatusTypeDef status = UART_STATUS_OK; + // 检查传入的UART外设参数是否合法 + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + // 检查传入的数据指针是否为空 + if (Data == NULL) + { + return UART_STATUS_ERROR; + } + + if (UARTx->ISR_f.TXBUSY) + { + return UART_STATUS_BUSY; + } + + if (txComplete == FALSE) + { + return UART_STATUS_BUSY; + } + txDataPtr = Data; + txDataLen = length; + txComplete = FALSE; + UARTx->ICR_f.TC = 1; + UARTx->IER_f.TC = 1; + UARTx->CR1_f.TXEN = 1; + UARTx->TDR = *txDataPtr; + txDataLen--; + return status; +} + +/** + * @brief 通过UARTx以中断方式接收数据 + * + * @param UARTx : UARTx外设，参数可以是 CW_UART1、CW_UART2、CW_UART3 等 + * @param Data : 待接收数据的指针 + * @param length : 待接收数据的个数 + * @note 中断服务函数中需要完成数据的接收和标志位的清除 + */ +UART_StatusTypeDef UART_ReceiveInterrupt(UART_TypeDef* UARTx, uint8_t *Data, uint32_t length) +{ + UART_StatusTypeDef status = UART_STATUS_OK; + // 检查传入的UART外设参数是否合法 + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + // 检查传入的数据指针是否为空 + if (Data == NULL) + { + return UART_STATUS_ERROR; + } + + if (rxComplete == FALSE) + { + return UART_STATUS_BUSY; + } + if (length == 0) + { + return UART_STATUS_ERROR; + } + rxDataPtr = Data; + rxDataLen = length; + rxComplete = FALSE; + UARTx->ICR_f.RC = 1; + UARTx->IER_f.RC = 1; + UARTx->CR1_f.RXEN = 1; + return status; +} + +/** + * @brief 通过UARTx以DMA方式发送数据 + * + * @param UARTx : UARTx外设，参数可以是 CW_UART1、CW_UART2、CW_UART3 等 + * @param DMACHx : DMA通道，参数可以是 DMA_CHANNEL_1、DMA_CHANNEL_2、DMA_CHANNEL_3、DMA_CHANNEL_4 等 + * @param Data : 待发送数据的指针 + * @param length : 待发送数据的个数 + */ +UART_StatusTypeDef UART_TransmitDMA(UART_TypeDef* UARTx, DMA_ChannelTypeDef DMACHx, uint8_t *Data, uint32_t length) +{ + UART_StatusTypeDef status = UART_STATUS_OK; + // 检查传入的UART外设参数是否合法 + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + // 检查传入的数据指针是否为空 + if (Data == NULL) + { + return UART_STATUS_ERROR; + } + + if (UARTx->ISR_f.TXBUSY) // 检查UART是否忙 + { + return UART_STATUS_BUSY; + } + + CW_SYSCTRL->AHBEN |= 0x5a5a0000 | SYSCTRL_AHBEN_DMA_Msk; // 使能DMA时钟 + CW_SYSCTRL->AHBRST_f.DMA = 0; // 复位DMA + CW_SYSCTRL->AHBRST_f.DMA = 1; // 使能DMA + + *DMA_CNTy(DMACHx) = length | 1 << DMA_CNT1_REPEAT_Pos ; // 设置DMA传输的数据长度 + *DMA_SRCADDRy(DMACHx) = (uint32_t)Data; // 设置DMA源地址 + *DMA_DSTADDRy(DMACHx) = (uint32_t)&UARTx->TDR; // 设置DMA目的地址 + + switch ((uint32_t)UARTx) + { + case (uint32_t)CW_UART1: + *DMA_TRIGy(DMACHx) = DMA_TRIGGER_SRC_UART1_TX << DMACHx_TRIG_HARDSRC_Pos | DMA_TRIGGER_HARDWARE << DMACHx_TRIG_TYPE_Pos; // 设置DMA触发源 + break; + case (uint32_t)CW_UART2: + *DMA_TRIGy(DMACHx) = DMA_TRIGGER_SRC_UART2_TX << DMACHx_TRIG_HARDSRC_Pos | DMA_TRIGGER_HARDWARE << DMACHx_TRIG_TYPE_Pos; // 设置DMA触发源 + break; + case (uint32_t)CW_UART3: + *DMA_TRIGy(DMACHx) = DMA_TRIGGER_SRC_UART3_TX << DMACHx_TRIG_HARDSRC_Pos | DMA_TRIGGER_HARDWARE << DMACHx_TRIG_TYPE_Pos; // 设置DMA触发源 + break; + } + *DMA_CSRy(DMACHx) = DISABLE << DMACHx_CSR_DSTLOAD_Pos | DISABLE << DMACHx_CSR_SRCLOAD_Pos |\ + DISABLE << DMACHx_CSR_RESTART_Pos | DMA_DATA_SIZE_8BITS << DMACHx_CSR_SIZE_Pos |\ + DMA_ADDRESS_FIXED << DMACHx_CSR_DSTINC_Pos | DMA_ADDRESS_INCREMENT << DMACHx_CSR_SRCINC_Pos |\ + DMA_MODE_BLOCK << DMACHx_CSR_TRANS_Pos | ENABLE << DMACHx_CSR_EN_Pos; // 配置DMA通道 + + UARTx->CR1_f.TXEN = 1; // 使能UART发送 + UARTx->CR2_f.DMATX = 1; // 使能UART DMA发送 + return status; +} + +/** + * @brief 通过UARTx以DMA方式接收数据 + * + * @param UARTx : UARTx外设，参数可以是 CW_UART1、CW_UART2、CW_UART3 等 + * @param DMACHx : DMA通道，参数可以是 DMA_CHANNEL_1、DMA_CHANNEL_2、DMA_CHANNEL_3、DMA_CHANNEL_4 等 + * @param Data : 待接收数据的指针 + * @param length : 待接收数据的个数 + */ +UART_StatusTypeDef UART_ReceiveDMA(UART_TypeDef* UARTx, DMA_ChannelTypeDef DMACHx, uint8_t *Data, uint32_t length) +{ + UART_StatusTypeDef status = UART_STATUS_OK; + // 检查传入的UART外设参数是否合法 + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + // 检查传入的数据指针是否为空 + if (Data == NULL) + { + return UART_STATUS_ERROR; + } + + CW_SYSCTRL->AHBEN |= 0x5a5a0000 | SYSCTRL_AHBEN_DMA_Msk; // 使能DMA时钟 + CW_SYSCTRL->AHBRST_f.DMA = 0; // 复位DMA + CW_SYSCTRL->AHBRST_f.DMA = 1; // 使能DMA + *DMA_CNTy(DMACHx) = length | 1 << DMA_CNT1_REPEAT_Pos ; // 设置DMA传输的数据长度 + *DMA_SRCADDRy(DMACHx) = (uint32_t)&UARTx->RDR; // 设置DMA源地址 + *DMA_DSTADDRy(DMACHx) = (uint32_t)Data; // 设置DMA目的地址 + + switch ((uint32_t)UARTx) + { + case (uint32_t)CW_UART1: + *DMA_TRIGy(DMACHx) = DMA_TRIGGER_SRC_UART1_RX << DMACHx_TRIG_HARDSRC_Pos | DMA_TRIGGER_HARDWARE << DMACHx_TRIG_TYPE_Pos; // 设置DMA触发源 + break; + case (uint32_t)CW_UART2: + *DMA_TRIGy(DMACHx) = DMA_TRIGGER_SRC_UART2_RX << DMACHx_TRIG_HARDSRC_Pos | DMA_TRIGGER_HARDWARE << DMACHx_TRIG_TYPE_Pos; // 设置DMA触发源 + break; + case (uint32_t)CW_UART3: + *DMA_TRIGy(DMACHx) = DMA_TRIGGER_SRC_UART3_RX << DMACHx_TRIG_HARDSRC_Pos | DMA_TRIGGER_HARDWARE << DMACHx_TRIG_TYPE_Pos; // 设置DMA触发源 + break; + } + *DMA_CSRy(DMACHx) = DISABLE << DMACHx_CSR_DSTLOAD_Pos | DISABLE << DMACHx_CSR_SRCLOAD_Pos |\ + DISABLE << DMACHx_CSR_RESTART_Pos | DMA_DATA_SIZE_8BITS << DMACHx_CSR_SIZE_Pos |\ + DMA_ADDRESS_INCREMENT << DMACHx_CSR_DSTINC_Pos | DMA_ADDRESS_FIXED << DMACHx_CSR_SRCINC_Pos |\ + DMA_MODE_BLOCK << DMACHx_CSR_TRANS_Pos | ENABLE << DMACHx_CSR_EN_Pos; // 配置DMA通道 + + UARTx->CR1_f.RXEN = 1; // 使能UART接收 + UARTx->CR2_f.DMARX = 1; // 使能UART DMA接收 + return status; +} + + +/** + * @brief 在同步模式下通过UARTx发送数据(8bit) + * @param UARTx :UARTx外设 + * @param Data :待发送的数据的指针 + * @param length :待发送的数据的个数 + */ +void UART_SyncMode_SendDataPolling(UART_TypeDef* UARTx, uint8_t *Data, uint32_t length) +{ + uint8_t *ptr = Data; + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + UARTx->ICR = 0; + + UARTx->CR1_f.TXEN = 1; + + while (length) + { + UARTx->TDR_f.TDR = *ptr; + ptr++; + length--; + while (UARTx->ISR_f.TXE == 0); + } + while (UARTx->ISR_f.TXBUSY == 1); + UARTx->CR1_f.TXEN = 0; +} + +/** + * @brief 在同步模式下通过UARTx接收数据(8bit) + * @param UARTx :UARTx外设 + * @param Data :待接收的数据缓存的指针 + * @param length :待接收的数据的个数 + * @return uint8_t :接收的数据 + */ +void UART_SyncMode_ReceiveDataPolling(UART_TypeDef* UARTx, uint8_t *Data, uint32_t length) +{ + uint8_t *ptr = Data; + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + UARTx->ICR_f.RC = 0; + + UARTx->CR1_f.RXEN = 1; + + while (length) + { + while (UARTx->ISR_f.RC == 0); + *ptr = UARTx->RDR; + ptr++; + length--; + UARTx->ICR_f.RC = 0; + } + UARTx->CR1_f.RXEN = 0; +} + + +/** + * @brief 根据UART_InitStruct中指定的参数初始化UARTx外设 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param UART_InitStruct :指向UART_InitTypeDef类型结构体的指针 + */ +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct) +{ + uint16_t integerdivider = 0x00; + uint16_t fractionaldivider = 0x00; + float32_t temp = 0; + + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_BAUDRATE(UART_InitStruct->UART_BaudRate)); + assert_param(IS_UART_Over(UART_InitStruct->UART_Over)); + assert_param(IS_UART_Source(UART_InitStruct->UART_Source)); + assert_param(IS_UART_UCLKFREQ(UART_InitStruct->UART_UclkFreq)); + assert_param(IS_UART_StartBit(UART_InitStruct->UART_StartBit)); + assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits)); + assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity)); + assert_param(IS_UART_MODE(UART_InitStruct->UART_Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(UART_InitStruct->UART_HardwareFlowControl)); + + switch ((uint32_t)UARTx) + { + case (uint32_t)CW_UART1: + CW_SYSCTRL->APBEN1 = (CW_SYSCTRL->APBEN1 & 0x0000FFFF) | 0x5a5a0000 | SYSCTRL_APBEN1_UART1_Msk; + break; + case (uint32_t)CW_UART2: + CW_SYSCTRL->APBEN1 = (CW_SYSCTRL->APBEN1 & 0x0000FFFF) | 0x5a5a0000 | SYSCTRL_APBEN1_UART2_Msk; + break; + case (uint32_t)CW_UART3: + CW_SYSCTRL->APBEN1 = (CW_SYSCTRL->APBEN1 & 0x0000FFFF) | 0x5a5a0000 | SYSCTRL_APBEN1_UART3_Msk; + break; + default: + break; + } + + /* UARTx_CR1 */ + REGBITS_MODIFY(UARTx->CR1, UARTx_CR1_SOURCE_Msk | UARTx_CR1_OVER_Msk | UARTx_CR1_START_Msk | \ + UARTx_CR1_STOP_Msk | UARTx_CR1_PARITY_Msk | \ + UARTx_CR1_RXEN_Msk | UARTx_CR1_TXEN_Msk \ + , \ + UART_InitStruct->UART_Source | \ + (uint32_t)UART_InitStruct->UART_Over | \ + UART_InitStruct->UART_StartBit | \ + UART_InitStruct->UART_StopBits | \ + UART_InitStruct->UART_Parity | \ + UART_InitStruct->UART_Mode); + + /* UARTx_CR2 */ + REGBITS_MODIFY(UARTx->CR2, UARTx_CR2_RTSEN_Msk | \ + UARTx_CR2_CTSEN_Msk \ + , \ + UART_InitStruct->UART_HardwareFlowControl); + /* 校验位 */ + if (UART_InitStruct->UART_Parity != UART_Parity_No) + { + UARTx->CR1_f.CHLEN = 1; + } + else + { + UARTx->CR1_f.CHLEN = 0; + } + + /* 波特率设置 */ + if (UART_Over_16 == UART_InitStruct->UART_Over) + { + /* 16倍采样 */ + temp = (float32_t)(UART_InitStruct->UART_UclkFreq) / (16 * (UART_InitStruct->UART_BaudRate)); + integerdivider = (uint16_t)temp; + fractionaldivider = (uint16_t)((temp - integerdivider) * 16 + 0.5); + UARTx->BRRI = (uint16_t)integerdivider; + UARTx->BRRF = (uint16_t)fractionaldivider; + } + else if (UART_Over_8 == UART_InitStruct->UART_Over) + { + /* 8倍采样 */ + integerdivider = (uint16_t)((float32_t)(UART_InitStruct->UART_UclkFreq) / (8 * (UART_InitStruct->UART_BaudRate)) + 0.5); + UARTx->BRRI = (uint16_t)integerdivider; + } + else if (UART_Over_4 == UART_InitStruct->UART_Over) + { + /* 4倍采样 */ + integerdivider = (uint16_t)((float32_t)(UART_InitStruct->UART_UclkFreq) / (4 * (UART_InitStruct->UART_BaudRate)) + 0.5); + UARTx->BRRI = (uint16_t)integerdivider; + } + else + { + /* 专用采样 */ + /* 专用采样仅适合传输时钟源为LSE或者LSI时，进行2400bps、4800bps或9600bps波特率下的UART通信 */ + integerdivider = (uint16_t)((float32_t)(UART_InitStruct->UART_UclkFreq) * 256 / (UART_InitStruct->UART_BaudRate) + 0.5); + UARTx->BRRI = (uint16_t)integerdivider; + } +} + +/** + * @brief 默认值赋值UART_InitStruct结构体成员 + * + * @param UART_InitStruct :指向UART_InitTypeDef类型结构体的指针 + */ +void UART_StructInit(UART_InitTypeDef* UART_InitStruct) +{ + /* UART_InitStruct members default value */ + UART_InitStruct->UART_BaudRate = 9600; + UART_InitStruct->UART_Over = UART_Over_16; + UART_InitStruct->UART_Source = UART_Source_PCLK; + UART_InitStruct->UART_StartBit = UART_StartBit_FE; + UART_InitStruct->UART_StopBits = UART_StopBits_1; + UART_InitStruct->UART_Parity = UART_Parity_No ; + UART_InitStruct->UART_Mode = UART_Mode_Rx | UART_Mode_Tx; + UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None; +} + +/** + * @brief UARTx同步模式初始化，CPOL=1、CPHA=1，只能做主机 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param UART_ClockInitStruct :指向UART_ClockInitTypeDef类型结构体的指针 + */ +void UART_ClockInit(UART_TypeDef* UARTx, UART_ClockInitTypeDef* UART_ClockInitStruct) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_CLOCK(UART_ClockInitStruct->UART_Clock)); + assert_param(IS_UART_Source(UART_ClockInitStruct->UART_Source)); + + REGBITS_MODIFY(UARTx->CR1, UARTx_CR1_SYNC_Msk | UARTx_CR1_SOURCE_Msk, \ + (uint32_t)UART_ClockInitStruct->UART_Clock | \ + (uint32_t)UART_ClockInitStruct->UART_Source); +} + +/** + * @brief 默认值赋值UART_ClockInitStruct结构体成员 + * + * @param UART_ClockInitStruct :指向UART_ClockInitTypeDef类型结构体的指针 + */ +void UART_ClockStructInit(UART_ClockInitTypeDef* UART_ClockInitStruct) +{ + /* UART_ClockInitStruct members default value */ + UART_ClockInitStruct->UART_Clock = UART_Clock_Disable; + UART_ClockInitStruct->UART_Source = UART_Source_PCLK; +} + +/** + * @brief UARTx同步模式初始化，CPOL=1、CPHA=1，只能做主机 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param UART_SyncModeInitStruct :指向UART_SyncModeInitTypeDef类型结构体的指针 + */ +void UART_SyncMode_Init(UART_TypeDef* UARTx, UART_SyncModeInitTypeDef *UART_SyncModeInitStruct) +{ + uint32_t BRRI; + + if (UART_SyncModeInitStruct->UART_BaudRate == 0) + { + return; + } + BRRI = UART_SyncModeInitStruct->UART_ClockFreq / (UART_SyncModeInitStruct->UART_BaudRate << 1); + if (BRRI > 0xFF) + { + BRRI = 0xFF; // 低8位有效 + } + // 打开UART时钟 + switch ((uint32_t)UARTx) + { + case (uint32_t)CW_UART1: + CW_SYSCTRL->APBEN1 = (CW_SYSCTRL->APBEN1 & 0x0000FFFF) | 0x5a5a0000 | SYSCTRL_APBEN1_UART1_Msk; + break; + case (uint32_t)CW_UART2: + CW_SYSCTRL->APBEN1 = (CW_SYSCTRL->APBEN1 & 0x0000FFFF) | 0x5a5a0000 | SYSCTRL_APBEN1_UART2_Msk; + break; + case (uint32_t)CW_UART3: + CW_SYSCTRL->APBEN1 = (CW_SYSCTRL->APBEN1 & 0x0000FFFF) | 0x5a5a0000 | SYSCTRL_APBEN1_UART3_Msk; + break; + default: + break; + } + + // + UARTx->CR1 = UARTx_CR1_SYNC_Msk | \ + UART_SyncModeInitStruct->UART_ClockSource | \ + UART_SyncModeInitStruct->UART_TransmitOrder; + UARTx->CR2_f.ADDREN = 0; + UARTx->BRRI = BRRI; +} + + +/** + * @brief UART1去初始化 + * + */ +void UART1_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.UART1 = 0; + CW_SYSCTRL->APBRST1_f.UART1 = 1; +} + +/** + * @brief UART2去初始化 + * + */ +void UART2_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.UART2 = 0; + CW_SYSCTRL->APBRST1_f.UART2 = 1; +} + +/** + * @brief UART3去初始化 + * + */ +void UART3_DeInit(void) +{ + CW_SYSCTRL->APBRST1_f.UART3 = 0; + CW_SYSCTRL->APBRST1_f.UART3 = 1; +} + + +/** + * @brief 使能/失能UARTx中断 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param UART_IT :中断源 + * 参数可以是: + * @arg UART_IT_RXMATCH: 接收匹配中断 + * @arg UART_IT_ORE: 溢出错误中断 + * @arg UART_IT_NE: 噪声错误中断 + * @arg UART_IT_PE: 奇偶校验错误中断 + * @arg UART_IT_FE: 帧结构错误中断 + * @arg UART_IT_CTS: CTS信号变化中断 + * @arg UART_IT_TIMOV: 定时器溢出中断 + * @arg UART_IT_BAUD: 自动波特率检测完成中断 + * @arg UART_IT_RXBRK: 间隔段接收完成中断 + * @arg UART_IT_RXIDLE: 接收空闲中断 + * @arg UART_IT_RC: 接收完成中断 + * @arg UART_IT_TC: 发送完成中断 + * @arg UART_IT_TXE: 发送缓冲空中断 + * @param NewState :ENABLE or DISABLE + */ +void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_IT(UART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + NewState ? (UARTx->IER |= UART_IT) : (UARTx->IER &= (uint16_t)~UART_IT); + + // if (NewState != DISABLE) + // { + // UARTx->IER |= UART_IT; + // } + // else + // { + // UARTx->IER &= (uint16_t)~UART_IT; + // } +} + +/** + * @brief 获取UARTx中断标志位 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param UART_IT :中断源 + * 参数可以是： + * @arg UART_IT_RXMATCH: 接收匹配中断 + * @arg UART_IT_ORE: 溢出错误中断 + * @arg UART_IT_NE: 噪声错误中断 + * @arg UART_IT_PE: 奇偶校验错误中断 + * @arg UART_IT_FE: 帧结构错误中断 + * @arg UART_IT_CTS: CTS信号变化中断 + * @arg UART_IT_TIMOV: 定时器溢出中断 + * @arg UART_IT_BAUD: 自动波特率检测完成中断 + * @arg UART_IT_RXBRK: 间隔段接收完成中断 + * @arg UART_IT_RXIDLE: 接收空闲中断 + * @arg UART_IT_RC: 接收完成中断 + * @arg UART_IT_TC: 发送完成中断 + * @arg UART_IT_TXE: 发送缓冲空中断 + * @return ITStatus :UART_IT当前状态 (SET or RESET) + */ +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_IT(UART_IT)); + + return (REGBITS_GET(UARTx->ISR, UART_IT) ? SET : RESET); +} + +/** + * @brief 清除UARTx中断标志位 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param UART_IT :中断源 + * 参数可以是： + * @arg UART_IT_RXMATCH: 接收匹配中断 + * @arg UART_IT_ORE: 溢出错误中断 + * @arg UART_IT_NE: 噪声错误中断 + * @arg UART_IT_PE: 奇偶校验错误中断 + * @arg UART_IT_FE: 帧结构错误中断 + * @arg UART_IT_CTS: CTS信号变化中断 + * @arg UART_IT_TIMOV: 定时器溢出中断 + * @arg UART_IT_BAUD: 自动波特率检测完成中断 + * @arg UART_IT_RXBRK: 间隔段接收完成中断 + * @arg UART_IT_RXIDLE: 接收空闲中断 + * @arg UART_IT_RC: 接收完成中断 + * @arg UART_IT_TC: 发送完成中断 + * @arg UART_IT_TXE: 发送缓冲空中断 + * @note + * -TXE中断标志位只能通过写UARTx_TDR寄存器来清除 + * -RC中断标志位只能软件清除，不能通过读UARTx_RDR寄存器来清除 + */ +void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_CLEAR_IT(UART_IT)); + + REGBITS_CLR(UARTx->ICR, UART_IT); +} + +/** + * @brief 获取UARTx标志位 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param UART_FLAG :标志 + * 参数可以是： + * @arg UART_FLAG_RXBRK: 间隔段接收完成中断 + * @arg UART_FLAG_BAUD: 自动波特率检测完成中断 + * @arg UART_FLAG_TIMOV: 定时器溢出中断 + * @arg UART_FLAG_TXBUSY: 发送忙标志 + * @arg UART_FLAG_CTSLV: CTS信号电平状态标志 + * @arg UART_FLAG_CTS: CTS信号变化标志 + * @arg UART_FLAG_RXMATCH: 从机地址匹配标志 + * @arg UART_FLAG_PE: 奇偶校验错误标志 + * @arg UART_FLAG_FE: 帧结构错误标志 + * @arg UART_FLAG_RC: 接收完成标志 + * @arg UART_FLAG_TC: 发送完成标志 + * @arg UART_FLAG_TXE: 发送缓冲器空标志 + * @return FlagStatus :UART_FLAG当前状态 (SET or RESET) + */ +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_FLAG(UART_FLAG)); + + return (REGBITS_GET(UARTx->ISR, UART_FLAG) ? SET : RESET); +} + +/** + * @brief 清除UARTx标志位 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param UART_FLAG :标志 + * 参数可以是： + * @arg UART_FLAG_RXBRK: 间隔段接收完成中断 + * @arg UART_FLAG_BAUD: 自动波特率检测完成中断 + * @arg UART_FLAG_TIMOV: 定时器溢出中断 + * @arg UART_FLAG_TXBUSY: 发送忙标志 + * @arg UART_FLAG_CTSLV: CTS信号电平状态标志 + * @arg UART_FLAG_CTS: CTS信号变化标志 + * @arg UART_FLAG_RXMATCH: 从机地址匹配标志 + * @arg UART_FLAG_PE: 奇偶校验错误标志 + * @arg UART_FLAG_FE: 帧结构错误标志 + * @arg UART_FLAG_RC: 接收完成标志 + * @arg UART_FLAG_TC: 发送完成标志 + * @arg UART_FLAG_TXE: 发送缓冲器空标志 + * @note + * -TXBUSY、CTSLV、SLVMATCH标志位由硬件自动设置和清除 + * -TXE标志位只能通过写UARTx_TDR寄存器来清除 + * -RC标志位只能软件清除，不能通过读UARTx_RDR寄存器来清除 + */ +void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_CLEAR_FLAG(UART_FLAG)); + + REGBITS_CLR(UARTx->ICR, UART_FLAG); +} + +/** + * @brief 使能/失能TXD输出、RXD输入 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param UART_DirectionMode :传输方向 + * 参数可以是： + * @arg UART_Mode_Tx: TXD输出 + * @arg UART_Mode_Rx: RXD输入 + * @param NewState :ENABLE or DISABLE + */ +void UART_DirectionModeCmd(UART_TypeDef* UARTx, uint16_t UART_DirectionMode, FunctionalState NewState) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_MODE(UART_DirectionMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + NewState ? (UARTx->CR1 |= UART_DirectionMode) : (UARTx->CR1 &= (uint16_t)~UART_DirectionMode); + + // if (NewState != DISABLE) + // { + // UARTx->CR1 |= UART_DirectionMode; + // } + // else + // { + // UARTx->CR1 &= (uint16_t)~UART_DirectionMode; + // } +} + +/** + * @brief 使能/失能TXD输出信号、RXD输入信号反相 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param UART_InvPin :反相引脚 + * 参数可以是： + * @arg UART_InvPin_Tx: TXD引脚输出信号反相 + * @arg UART_InvPin_Rx: RXD引脚输入信号反相 + * @param NewState :ENABLE or DISABLE + */ +void UART_InvPinCmd(UART_TypeDef* UARTx, uint16_t UART_InvPin, FunctionalState NewState) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_INVERSTION_PIN(UART_InvPin)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + NewState ? (UARTx->CR2 |= UART_InvPin) : (UARTx->CR2 &= (uint16_t)~UART_InvPin); + + // if (NewState != DISABLE) + // { + // UARTx->CR2 |= UART_InvPin; + // } + // else + // { + // UARTx->CR2 &= (uint16_t)~UART_InvPin; + // } +} + +/** + * @brief 使能/失能UARTx半双工通信 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param NewState :ENABLE or DISABLE + */ + +void UART_HalfDuplexCmd(UART_TypeDef* UARTx, FunctionalState NewState) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + UARTx->CR1_f.SIGNAL = NewState; +} + +/** + * @brief 使能/失能UARTx DMA + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param UART_DMAReq :DMA请求 + * 参数可以是： + * @arg UART_DMAReq_Tx: DMA发送请求 + * @arg UART_DMAReq_Rx: DMA接收请求 + * @param NewState :ENABLE or DISABLE + */ +void UART_DMACmd(UART_TypeDef* UARTx, uint16_t UART_DMAReq, FunctionalState NewState) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_DMAREQ(UART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + NewState ? (UARTx->CR2 |= UART_DMAReq) : (UARTx->CR2 &= (uint16_t)~UART_DMAReq); +} + +/** + * @brief UARTx多机通信配置 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param UART_Address :从机地址 + * @param UART_AddressMsK :从机地址掩码 + * @note + * 主机和从机均需配置为自定义校验 + */ +void UART_SetMultiMode(UART_TypeDef* UARTx, uint8_t UART_Address, uint8_t UART_AddressMsK) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_ADDRESS(UART_Address)); + assert_param(IS_UART_ADDRESSMSK(UART_AddressMsK)); + + REGBITS_SET(UARTx->CR2, UARTx_CR2_ADDREN_Msk); + REGBITS_MODIFY(UARTx->ADDR, UARTx_ADDR_ADDR_Msk, (uint32_t)UART_Address); + REGBITS_MODIFY(UARTx->MASK, UARTx_MASK_MASK_Msk, (uint32_t)UART_AddressMsK); +} + +/** + * @brief 使能/失能LIN模式 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、 + * @param NewState :ENABLE or DISABLE + */ +void UART_LINCmd(UART_TypeDef* UARTx, FunctionalState NewState) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + UARTx->CR3_f.LIN = NewState; + UARTx->CR1_f.SIGNAL = 0; + UARTx->CR1_f.SYNC = 0; + UARTx->CR1_f.STOP = 0; + UARTx->CR1_f.PARITY = 0; +} + +/** + * @brief 发送LIN中断 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param BreakLength :间隔段长度 一般大于13bit + */ +void UART_LINSendBreak(UART_TypeDef* UARTx, UART_LINBreakSendLengthTypeDef BreakLength) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + UARTx->TDR = BreakLength; +} +/** + * @brief 设置LIN模式接收间隔段的长度阈值 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、 + * @param UART_LINBreakDetectLength :间隔段长度阈值 + * 参数可以是： + * @arg UART_LIN_BREAK_DETECT_LENGTH_10B: 10bit + * @arg UART_LIN_BREAK_DETECT_LENGTH_11B: 11bit + */ +void UART_LINBreakDetectLengthConfig(UART_TypeDef* UARTx, UART_LINBreakDetectLengthTypeDef UART_LINBreakDetectLength) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + UARTx->CR3_f.BRKL = UART_LINBreakDetectLength; +} + +/** + * @brief 定时器工作模式配置 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、 + * @param UART_TimerMode :定时器工作模式 + * 参数可以是： + * @arg UART_TimerMode_Stop: 停止定时器 + * @arg UART_TimerMode_TimeOut: 等待超时检测模式 + * @arg UART_TimerMode_Idle: 接收空闲检测模式 + * @arg UART_TimerMode_AutoBaudRate1: 自动波特率侦测模式1 + * @arg UART_TimerMode_AutoBaudRate2: 自动波特率侦测模式2 + * @arg UART_TimerMode_GeneralTimer: 通用定时功能 + */ +void UART_TimerModeConfig(UART_TypeDef* UARTx, uint16_t UART_TimerMode) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_TIMER_MODE(UART_TimerMode)); + + REGBITS_MODIFY(UARTx->CR2, UARTx_CR2_TIMCR_Msk, (uint32_t)UART_TimerMode); +} + +/** + * @brief 设置定时器重载值 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、 + * @param Autoreload :定时器重载值 范围0x000000~0xFFFFFF + */ +void UART_SetAutoReload(UART_TypeDef* UARTx, uint32_t AutoReload) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_AUTORELOAD(AutoReload)); + + UARTx->TIMARR = AutoReload; +} + +/** + * @brief 获取定时器当前计数值 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、 + * @return uint32_t :定时器当前计数值 + */ +uint32_t UART_GetCounter(UART_TypeDef* UARTx) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + return UARTx->TIMCNT; +} + + +/** + * @brief 交换UARTx引脚功能 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param NewState : 使能或禁用引脚交换，ENABLE 表示启用交换，DISABLE 表示恢复默认 + */ +void UART_PinSwapCmd(UART_TypeDef* UARTx, FunctionalState NewState) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + // 根据不同的UART外设，配置对应的引脚交换 + UARTx->CR2_f.SWAP = NewState; +} + +/** + * @brief 启用自动波特率检测 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param AutoBaudRateMode : 自动波特率检测模式，UART_AutoBaudRateModeTypeDef 类型的枚举值 + * @note + * - 确保在调用此函数之前已经配置了 UART 模块的时钟源 + * - 此函数会启用自动波特率检测功能，并根据指定的模式进行配置 + * - 自动波特率检测模式包括： + * - UART_AUTO_BAUD_RATE_MODE_1: RXD下降沿使定时器启动从0开始计数，上升沿停止定时器；计数时钟为UCLK；检测完成自动停止 + * - UART_AUTO_BAUD_RATE_MODE_2: RXD下降沿使定时器启动从0开始计数，第4个下升沿停止定时器；计数时钟为UCLK；检测完成自动停止 + */ +void UART_EnableAutoBaudRateDetection(UART_TypeDef* UARTx,UART_AutoBaudRateModeTypeDef AutoBaudRateMode) + { + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + UARTx->ICR_f.BAUD = 0; // 清除自动波特率检测完成标志 + UARTx->TIMARR = 0xFFFFFF; // 设置定时器重载值为最大值，确保定时器不会溢出 + + if (AutoBaudRateMode == UART_AUTO_BAUD_RATE_MODE_1) + { + // 配置定时器工作模式为 UART_AUTO_BAUD_RATE_MODE_1 + UART_TimerModeConfig(UARTx, UART_TimerMode_AutoBaudRate1); + } + else if (AutoBaudRateMode == UART_AUTO_BAUD_RATE_MODE_2) + { + // 配置定时器工作模式为 UART_AUTO_BAUD_RATE_MODE_2 + UART_TimerModeConfig(UARTx, UART_TimerMode_AutoBaudRate2); + } +} + +/** + * @brief 禁用自动波特率检测 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @note + * - 此函数会停止自动波特率检测功能，并禁用定时器 + */ +void UART_DisableAutoBaudRateDetection(UART_TypeDef* UARTx) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + UARTx->ICR_f.BAUD = 0; // 清除自动波特率检测完成标志 + UART_TimerModeConfig(UARTx, UART_TimerMode_Stop); // 停止定时器 +} + + +// 检查自动波特率检测是否完成 +boolean_t UART_AutoBaudRateDetectionComplete(UART_TypeDef* UARTx) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + return (boolean_t)UARTx->ISR_f.BAUD; // 检查自动波特率检测完成标志 +} + +// 获取检测到的波特率 +uint32_t UART_GetDetectedBaudRate(UART_TypeDef* UARTx) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + return UARTx->TIMCNT; +} + +/** + * @brief 使能UARTx数据匹配 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @note + * - 此函数会使能UARTx的数据匹配功能 + */ +void UART_EnableDataMatch(UART_TypeDef* UARTx) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + UARTx->CR2_f.RXMATCHEN = 1; +} + +/** + * @brief 禁用UARTx数据匹配 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @note + * - 此函数会禁用UARTx的数据匹配功能 + */ +void UART_DisableDataMatch(UART_TypeDef* UARTx) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + UARTx->CR2_f.RXMATCHEN = 0; +} + +/** + * @brief 设置UARTx数据匹配值 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @param DataMatch : 数据匹配值，范围为0x000~0x1FF + * @note DataMach的最高位为奇偶校验位 + */ +void UART_SetDataMatch(UART_TypeDef* UARTx, uint16_t DataMatch) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + UARTx->RXMATCH = DataMatch; +} + +/** + * @brief 获取UARTx数据匹配标志 + * + * @param UARTx :UARTx外设 + * 参数可以是: + * CW_UART1、CW_UART2、CW_UART3 + * @return boolean_t : 数据匹配标志，TRUE 表示数据匹配，FALSE 表示数据不匹配 + */ +boolean_t UART_GetDataMatchFlag(UART_TypeDef* UARTx) +{ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + return (boolean_t)UARTx->ISR_f.RXMATCH; +} + + + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_vc.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_vc.c new file mode 100644 index 0000000..ff257e5 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_vc.c @@ -0,0 +1,266 @@ +/** + * @file cw32l012_vc.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "cw32l012_sysctrl.h" +#include "cw32l012_vc.h" + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + /** + * @brief + * 初始化VC模块 + * + * @param VCx: + * @arg CW_VC1, @arg CW_VC2, @arg CW_VC3, @arg CW_VC4 + * + * @param VC_InitStruct: + * + */ +void VC_Init(VC_TypeDef *VCx, VC_InitTypeDef* VC_InitStruct) +{ + __SYSCTRL_VC_CLK_ENABLE(); + // 配置参考电压 + VC_SetRefVoltage(VCx, VC_InitStruct->RefVoltage, VC_InitStruct->div); + + // 配置输入信号 + VC_SetInputSignals(VCx, VC_InitStruct->inputPositive, VC_InitStruct->inputNegative); + + // 配置中断模式 + VC_SetInterruptMode(VCx, VC_InitStruct->interruptMode); + + // 配置滤波器 + VC_SetFilterConfig(VCx, &VC_InitStruct->filterConfig); + + // 配置其他控制寄存器 + VCx->CR0_f.POL = VC_InitStruct->polarityInvert; + VCx->CR0_f.HYS = VC_InitStruct->hysteresisEnable; + VCx->CR0_f.RESP = VC_InitStruct->responseSpeed; +} + + +/** + * @brief + * VC模块开启或关闭 + * + * @param VCx: + * @arg CW_VC1, @arg CW_VC2, @arg CW_VC3, @arg CW_VC4 + * + * @param state: EANBLE DISABLE + * + */ +void VC_Cmd(VC_TypeDef *VCx, FunctionalState state) +{ + state ? (VCx->CR0_f.EN = 1) : (VCx->CR0_f.EN = 0); +} + +/** + * @brief + * 配置参考电压 + * + * @param VCx: + * @arg CW_VC1, @arg CW_VC2, @arg CW_VC3, @arg CW_VC4 + * + * @param RefVoltage: + * + * @param div: + * + */ + +void VC_SetRefVoltage(VC_TypeDef *VCx, VC_RefVoltage RefVoltage, VC_Divider div) +{ + if ((uint32_t)VCx == VC1_BASE || (uint32_t)VCx == VC2_BASE) + { + CW_VC12REF->REF = (RefVoltage << VC12REF_DIV_EN_Pos) | div; + } + else if ((uint32_t)VCx == VC3_BASE || (uint32_t)VCx == VC4_BASE) + { + CW_VC34REF->REF = (RefVoltage << VC12REF_DIV_EN_Pos) | div; + } +} + +/** + * @brief + * 配置输入信号 + * + * @param VCx: + * @arg CW_VC1, @arg CW_VC2, @arg CW_VC3, @arg CW_VC4 + * + * @param inputPositive: + * + * @param inputNegative: + * + */ +void VC_SetInputSignals(VC_TypeDef *VCx, VC_PosInputSignal inputPositive, VC_NegInputSignal inputNegative) +{ + uint32_t cr0 = VCx->CR0; + cr0 = (cr0 & ~VCx_CR0_INP_Msk) | (inputPositive << VCx_CR0_INP_Pos); // 设置正端输入 + cr0 = (cr0 & ~VCx_CR0_INN_Msk) | (inputNegative << VCx_CR0_INN_Pos); // 设置负端输入 + VCx->CR0 = cr0; +} + +/** + * @brief + * 配置中断模式 + * + * @param VCx: + * @arg CW_VC1, @arg CW_VC2, @arg CW_VC3, @arg CW_VC4 + * + * @param mode: + * + */ +void VC_SetInterruptMode(VC_TypeDef *VCx, VC_InterruptMode mode) +{ + uint32_t cr1 = VCx->CR1; + + if (mode == VC_INT_DISABLE) + { + VCx->CR0_f.IE = 0; + } + else + { + VCx->CR0_f.IE = 1; + cr1 = (cr1 & ~(0x3 << 5)) | (mode << 5); // 设置中断模式 + VCx->CR1 = cr1; + } +} + +/** + * @brief + * 设置滤波器配置 + * + * @param VCx: + * @arg CW_VC1, @arg CW_VC2, @arg CW_VC3, @arg CW_VC4 + * + * @param config: + * + */ +void VC_SetFilterConfig(VC_TypeDef *VCx, VC_FilterConfig *config) +{ + uint32_t cr1 = VCx->CR1; + + cr1 = (cr1 & ~VCx_CR1_FLTCLK_Msk) | (config->FilterClock << VCx_CR1_FLTCLK_Pos); + cr1 = (cr1 & ~VCx_CR1_FLTTIME_Msk) | (config->FilterTime << VCx_CR1_FLTTIME_Pos); + VCx->CR1 = cr1; +} + +/** + * @brief + * 获取中断标志 + * + * @param VCx: + * @arg CW_VC1, @arg CW_VC2, @arg CW_VC3, @arg CW_VC4 + * + * + */ +uint8_t VC_GetInterruptFlag(VC_TypeDef *VCx) +{ + return VCx->SR_f.INTF; +} + +/** + * @brief + * 清除中断标志 + * + * @param VCx: + * @arg CW_VC1, @arg CW_VC2, @arg CW_VC3, @arg CW_VC4 + * + * + */ +void VC_ClearInterruptFlag(VC_TypeDef *VCx) +{ + VCx->SR_f.INTF = 0; +} + +/** + * @brief + * 获取数字滤波器输出 + * + * @param VCx: + * @arg CW_VC1, @arg CW_VC2, @arg CW_VC3, @arg CW_VC4 + * + * + */ +uint8_t VC_GetFilterOutput(VC_TypeDef *VCx) +{ + return VCx->SR_f.FLTV; +} + +/** + * @brief + * BLANK窗口配置 + * + * @param VCx: + * @arg CW_VC1, @arg CW_VC2, @arg CW_VC3, @arg CW_VC4 + * + * + */ +void VC_SetBlankWindow(VC_TypeDef *VCx, VC_BlankWindowCfg *config) +{ + uint32_t cr1 = VCx->CR1; + + cr1 = (cr1 & ~VCx_CR1_BLANKLVL_Msk) | (config->BlankOutput << VCx_CR1_BLANKLVL_Pos); + cr1 = (cr1 & ~VCx_CR1_BLANKTIME_Msk) | (config->BlankTime << VCx_CR1_BLANKTIME_Pos); + VCx->CR1 = cr1; + + VCx->CR2 = config->BlankTrigSource; +} + +//@} // VcGroup + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_wwdt.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_wwdt.c new file mode 100644 index 0000000..8c3827a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/cw32l012_wwdt.c @@ -0,0 +1,72 @@ +/** + * @file cw32l012_wwdt.c + * @author WHXY + * @brief WWDT (Window Watchdog Timer) driver for CW32L012 + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * 代码许可和免责信息 + * 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 + * 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 + * 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 + * 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 + * 或条件。 + * 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， + * 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 + * 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 + * 损失。 + * 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 + * 全部上述排除或限制可能并不适用于您。 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "cw32l012_wwdt.h" + +/* Private_TypesDefinitions --------------------------------------------------*/ + +/* Private_Defines -----------------------------------------------------------*/ + +/* Private_Variables ---------------------------------------------------------*/ + +/* Private_FunctionPrototypes ------------------------------------------------*/ + +/* Private_Functions ---------------------------------------------------------*/ + +/* Public_Functions ----------------------------------------------------------*/ + +/** + * @brief 初始化窗口看门狗 + * @details 该函数用于初始化窗口看门狗，包括使能窗口看门狗时钟、配置预分频器、窗口值和计数器初始值，最后使能窗口看门狗。 + * @param WWDT_InitStruct + * @return 无 + */ + +void WWDT_Init(const WWDT_InitTypeDef *WWDT_InitStruct) +{ + // 使能窗口看门狗时钟 + CW_SYSCTRL->APBEN2 |= SYSCTRL_KEY | SYSCTRL_APBEN2_WWDT_Msk; + // 配置预分频器 + CW_WWDT->CR1_f.PRS = WWDT_InitStruct->Prescaler; + // 配置窗口值 + CW_WWDT->CR1_f.WINR = WWDT_InitStruct->WindowValue; + // 配置中断使能 + CW_WWDT->CR1_f.IE = WWDT_InitStruct->PreOvInt; + // 配置计数器初始值 + CW_WWDT->CR0_f.WCNT = WWDT_InitStruct->CounterValue; + + // 使能窗口看门狗 + CW_WWDT->CR0_f.EN = 1; +} + +/** + * @brief 执行窗口看门狗的喂狗操作 + * @details 该操作通过向窗口看门狗的控制寄存器写入特定值来刷新计数器，防止看门狗超时复位。 + * @param ReloadCnt: WWDT的重载值, 0x41 ~ 0x7F + * @return 无 + */ +void WWDT_Feed(uint8_t ReloadCnt) +{ + + CW_WWDT->CR0_f.WCNT = ReloadCnt; +} diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/system_cw32l012.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/system_cw32l012.c new file mode 100644 index 0000000..eb2516a --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/Libraries/src/system_cw32l012.c @@ -0,0 +1,75 @@ +/****************************************************************************** +* Include files * +******************************************************************************/ +#include "system_cw32l012.h" + +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS 0x20000000U /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS 0x00000000U /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +/****************************************************************************** + ** System Clock Frequency (Core Clock) Variable according CMSIS + ******************************************************************************/ + +uint32_t SystemCoreClock = 4000000; + +void SystemCoreClockUpdate(void) // Update SystemCoreClock variable +{ + SystemCoreClock = 4000000; +} + +/** + ****************************************************************************** + ** \brief Setup the microcontroller system. Initialize the System and update + ** the SystemCoreClock variable. + ** + ** \param none + ** \return none + ******************************************************************************/ +void SystemInit(void) +{ +/* Configure the Vector Table location add offset address ------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + + //Load TrimCode in this. + CW_SYSCTRL->HSI_f.TRIM = *((volatile uint16_t *)SYSCTRL_HSI_TRIMCODEADDR); + CW_SYSCTRL->LSI_f.TRIM = *((volatile uint16_t *)SYSCTRL_LSI_TRIMCODEADDR); + if (CW_SYSCTRL->HSI_f.TRIM == 0x7FF) + { + CW_SYSCTRL->HSI_f.TRIM = 0x77A; + } + if (CW_SYSCTRL->LSI_f.TRIM == 0x1FF) + { + CW_SYSCTRL->LSI_f.TRIM= 0x0059; + } + + SystemCoreClockUpdate(); + + //Init Hide thing. + //... +} + +void FirmwareDelay(uint32_t DlyCnt) +{ + volatile uint32_t thisCnt = DlyCnt; + while( thisCnt-- ) + { + ; + } +} diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/StartKit_Board/cw32l012_startkit.c b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/StartKit_Board/cw32l012_startkit.c new file mode 100644 index 0000000..becde98 --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/StartKit_Board/cw32l012_startkit.c @@ -0,0 +1,267 @@ +/** + * @file cw32l012_startkit.c + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2021 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "cw32l012_startkit.h" + +KEY_TypeDef KEY1 = {.Port = BSP_KEY1_PORT, .Pin = BSP_KEY1_PIN}; +KEY_TypeDef KEY2 = {.Port = BSP_KEY2_PORT, .Pin = BSP_KEY2_PIN}; +LED_TypeDef LED1 = {.Port = BSP_LED1_PORT, .Pin = BSP_LED1_PIN}; +LED_TypeDef LED2 = {.Port = BSP_LED2_PORT, .Pin = BSP_LED2_PIN}; + + + +/******************************************************************************* + * @brief 用于支持Printf打印的函数， + * @retval None + * @note 需要使用microlib库 + */ +#if (__ARMCC_VERSION > 6000000) + __asm (".global __use_no_semihosting\n\t"); + void _sys_exit(int x) + { + x = x; + } + /* __use_no_semihosting was requested, but _ttywrch was */ + void _ttywrch(int ch) + { + ch = ch; + } + FILE __stdout; +#else + #ifdef __CC_ARM + #pragma import(__use_no_semihosting) + struct __FILE + { + int handle; + }; + FILE __stdout; + void _sys_exit(int x) + { + x = x; + } + /* __use_no_semihosting was requested, but _ttywrch was */ + void _ttywrch(int ch) + { + ch = ch; + } + #endif +#endif + +// 检测 IAR 版本 +#if defined(__IAR_SYSTEMS_ICC__) && (__VER__ >= 9000000) + // IAR 9.x 版本 + #define IAR_VERSION 9 +#elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ >= 8000000) + // IAR 8.x 版本 + #define IAR_VERSION 8 +#endif + +#if defined (__GNUC__) && !defined (__clang__) + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif + +// 发送单个字符 +void UART_SendChar(char ch) +{ + while ((BSP_UART->ISR & UARTx_ISR_TXBUSY_Msk) == UARTx_ISR_TXBUSY_Msk); // 等待发送完成 + BSP_UART->TDR = ch; // 发送字符 +} +/******************************************************************************* + * @brief 重定向C库中Printf函数到UART. + * @retval None + * @note None + */ +__weak PUTCHAR_PROTOTYPE +{ + UART_SendChar((char)ch); + return ch; +} + +// IAR 9.x 使用 __write 重定向 +#if IAR_VERSION == 9 +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + for (size_t i = 0; i < size; i++) + { + UART_SendChar(buffer[i]); + } + return size; +} +#endif + +/******************************************************************************* + * @brief 板载UART打印初始化 + * @param pclkFreq: pclk freq + * @param baudRate: uart baudrate + * @retval none + * @note + */ +void Bsp_Uart_Init(uint32_t pclkFreq, uint32_t baudRate) +{ + uint32_t BRR; + /* configure the uart txd pin */ + BSP_UART_TXD_PORT_PERIPH_CLK_ENABLE(); + BSP_UART_TXD_AF(); + BSP_UART_TXD_PORT->ANALOG &= ~(BSP_UART_TXD_PIN); + + /* configure the uart rxd pin */ + BSP_UART_RXD_PORT_PERIPH_CLK_ENABLE(); + BSP_UART_RXD_AF(); + BSP_UART_RXD_PORT->ANALOG &= ~(BSP_UART_RXD_PIN); + + /* configure uart */ + BSP_UART_PERIPH_CLK_ENABLE(); + BSP_UART_PERIPH_RST_ENABLE(); + BSP_UART_PERIPH_RST_DISABLE(); + + BRR = (pclkFreq + (baudRate >> 1) )/ baudRate; // 加0.5倍的baudRate，相对于4舍5入 + BSP_UART->BRRI = BRR >> 4; + BSP_UART->BRRF = BRR % 16; + BSP_UART->CR1 = UARTx_CR1_TXEN_Msk | UARTx_CR1_RXEN_Msk; +} + +void Bsp_Uart_Closed(void) +{ + BSP_UART_PERIPH_CLK_DISABLE(); + + BSP_UART_TXD_PORT->ANALOG |= (BSP_UART_TXD_PIN); + BSP_UART_RXD_PORT->ANALOG |= (BSP_UART_RXD_PIN); + + BSP_UART_TXD_PORT_PERIPH_CLK_DISABLE(); + BSP_UART_RXD_PORT_PERIPH_CLK_DISABLE(); +} + +/******************************************************************************* + * @brief 板载按键初始化 + * @param KEY + * @retval None + * @note + */ +void Bsp_Key_Init(KEY_TypeDef *KEY) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + GPIO_InitStruct.IT = GPIO_IT_FALLING; // 下降沿中断使能 + GPIO_InitStruct.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_InitStruct.Pins = KEY->Pin; + + GPIO_Init(KEY->Port, &GPIO_InitStruct); + +// NVIC_ClearPendingIRQ(BSP_KEY_IRQn); +// NVIC_EnableIRQ(BSP_KEY_IRQn); + +} + + +/******************************************************************************* + * @brief 读取板载按键的状态 + * @param none + * @retval 返回板载按键的电平状态 + * + */ +KeyStateTypeDef Bsp_Read_Key(KEY_TypeDef *KEY) +{ + uint32_t currentInput; + + currentInput= !!(KEY->Port->IDR & KEY->Pin); // 读取引脚状态  + + return currentInput ? KEY_STATE_RELEASED : KEY_STATE_PRESSED; +} + + +/******************************************************************************* + * @brief 板载LED初始化 + * @param LED + * @retval None + * @note + */ +void Bsp_Led_Init(LED_TypeDef *LED) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = LED->Pin; + + GPIO_Init(LED->Port, &GPIO_InitStruct); + + Bsp_Led_Off(LED); +} + + +/******************************************************************************* + * @brief 点亮板载LED + * @param LED + * @retval None + */ +void Bsp_Led_On(LED_TypeDef *LED) +{ + LED->Port->BSRR |= LED->Pin; +} + + +/******************************************************************************* + * @brief 熄灭板载LED + * @param LED + * @retval None + */ +void Bsp_Led_Off(LED_TypeDef *LED) +{ + LED->Port->BRR |= LED->Pin; +} + + +/******************************************************************************* + * @brief 翻转板载LED + * @param LED + * @retval None + */ +void Bsp_Led_Tog(LED_TypeDef *LED) +{ + LED->Port->TOG |= LED->Pin; +} + + +/******************************************************************************* + * @brief 板载硬件接口初始化 + * @param None + * @retval None + */ + void Bsp_Init(uint32_t ClkFreq) + { + Bsp_Led_Init(&LED1); + Bsp_Led_Init(&LED2); + Bsp_Key_Init(&KEY1); + Bsp_Key_Init(&KEY2); + Bsp_Uart_Init(ClkFreq, 115200); + } + +/************************ (C) COPYRIGHT *****END OF FILE*************/ + diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/StartKit_Board/cw32l012_startkit.h b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/StartKit_Board/cw32l012_startkit.h new file mode 100644 index 0000000..3163d5b --- /dev/null +++ b/新单片机-CW32L012/MCU厂资料/CW32L012_StandardPeripheralLib_V1.0.3/StartKit_Board/cw32l012_startkit.h @@ -0,0 +1,151 @@ +/** + * @file cw32l012_startkit.h + * @author WHXY + * @brief + * @version 0.1 + * @date 2024-08-07 + * + * @copyright Copyright (c) 2022 + * + */ +/******************************************************************************* +* +* 代码许可和免责信息 +* 武汉芯源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此 +* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉芯源半 +* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗 +* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证 +* 或条件。 +* 无论何种情形，武汉芯源半导体有限公司及其程序开发商或供应商均不对下列各项负责， +* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的 +* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的 +* 损失。 +* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或 +* 全部上述排除或限制可能并不适用于您。 +* +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CW32L012_STARTKIT_H +#define __CW32L012_STARTKIT_H + +/* Includes ------------------------------------------------------------------*/ +#include +#include "cw32l012_gpio.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_uart.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Global type definitions */ +/******************************************************************************/ +typedef enum{ + KEY_STATE_PRESSED, // 按下 + KEY_STATE_RELEASED // 释放 +} KeyStateTypeDef; + + +typedef struct +{ + GPIO_TypeDef* Port; + uint32_t Pin; +}LED_TypeDef, KEY_TypeDef; + + + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +//StartKit硬件资源配置： + +/********************* 配置LED端口信息 ****************************************/ +#define BSP_LED1_PIN GPIO_PIN_9 +#define BSP_LED1_PORT CW_GPIOB +#define BSP_LED1_PERIPH_CLK_ENABLE() __SYSCTRL_GPIOB_CLK_ENABLE() +#define BSP_LED1_PERIPH_CLK_DISABLE() __SYSCTRL_GPIOB_CLK_DISABLE() +#define BSP_LED1_SETHIGH() PB09_SETHIGH() +#define BSP_LED1_SETLOW() PB09_SETLOW() +#define BSP_LED1_TOG() PB09_TOG() + +#define BSP_LED2_PIN GPIO_PIN_8 +#define BSP_LED2_PORT CW_GPIOB +#define BSP_LED2_PERIPH_CLK_ENABLE() __SYSCTRL_GPIOB_CLK_ENABLE() +#define BSP_LED2_PERIPH_CLK_DISABLE() __SYSCTRL_GPIOB_CLK_DISABLE() +#define BSP_LED2_SETHIGH() PB08_SETHIGH() +#define BSP_LED2_SETLOW() PB08_SETLOW() +#define BSP_LED2_TOG() PB08_TOG() + + +/******************* 配置用户按键端口信息 *************************************/ +#define BSP_KEY1_PIN GPIO_PIN_0 +#define BSP_KEY1_PORT CW_GPIOA +#define BSP_KEY1_PERIPH_CLK_ENABLE() __SYSCTRL_GPIOA_CLK_ENABLE() +#define BSP_KEY1_PERIPH_CLK_DISABLE() __SYSCTRL_GPIOA_CLK_DISABLE() +#define BSP_KEY1_GETVALUE() PA00_GETVALUE() +#define BSP_KEY1_IRQn GPIOA_IRQn + +#define BSP_KEY2_PIN GPIO_PIN_1 +#define BSP_KEY2_PORT CW_GPIOA +#define BSP_KEY2_PERIPH_CLK_ENABLE() __SYSCTRL_GPIOA_CLK_ENABLE() +#define BSP_KEY2_PERIPH_CLK_DISABLE() __SYSCTRL_GPIOA_CLK_DISABLE() +#define BSP_KEY2_GETVALUE() PA01_GETVALUE() +#define BSP_KEY2_IRQn GPIOA_IRQn + +/******************* 配置用于Printf的端口和外设和信息 *************************/ +#define BSP_UART_TXD_PIN GPIO_PIN_8 +#define BSP_UART_TXD_PORT CW_GPIOA +#define BSP_UART_TXD_AF() PA08_AFx_UART3TXD() +#define BSP_UART_TXD_PORT_PERIPH_CLK_ENABLE() __SYSCTRL_GPIOA_CLK_ENABLE() +#define BSP_UART_TXD_PORT_PERIPH_CLK_DISABLE() __SYSCTRL_GPIOA_CLK_DISABLE() + +#define BSP_UART_RXD_PIN GPIO_PIN_9 +#define BSP_UART_RXD_PORT CW_GPIOA +#define BSP_UART_RXD_IRQn GPIOA_IRQn +#define BSP_UART_RXD_AF() PA09_AFx_UART3RXD() +#define BSP_UART_RXD_PORT_PERIPH_CLK_ENABLE() __SYSCTRL_GPIOA_CLK_ENABLE() +#define BSP_UART_RXD_PORT_PERIPH_CLK_DISABLE() __SYSCTRL_GPIOA_CLK_DISABLE() + +#define BSP_UART CW_UART3 +#define BSP_UART_IRQn UART3_IRQn +#define BSP_UART_PERIPH_CLK_ENABLE() __SYSCTRL_UART3_CLK_ENABLE() +#define BSP_UART_PERIPH_CLK_DISABLE() __SYSCTRL_UART3_CLK_DISABLE() +#define BSP_UART_PERIPH_RST_ENABLE() __SYSCTRL_UART3_RST_ENABLE() +#define BSP_UART_PERIPH_RST_DISABLE() __SYSCTRL_UART3_RST_DISABLE() + + +/******************************************************************************/ +/* Global macro function */ +/******************************************************************************/ + + +/******************************************************************************/ +/* Exported variables ('extern', definition in C source) */ +/******************************************************************************/ +extern LED_TypeDef LED1, LED2; +extern KEY_TypeDef KEY1, KEY2; + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ +extern void Bsp_Uart_Init(uint32_t pclkFreq, uint32_t baudRate); +extern void Bsp_Uart_Closed(void); + +extern void Bsp_Key_Init(KEY_TypeDef *KEY); +extern KeyStateTypeDef Bsp_Read_Key(KEY_TypeDef *KEY); + +extern void Bsp_Led_Init(LED_TypeDef *LED); +extern void Bsp_Led_On(LED_TypeDef *LED); +extern void Bsp_Led_Off(LED_TypeDef *LED); +extern void Bsp_Led_Tog(LED_TypeDef *LED); + +extern void Bsp_Init(uint32_t ClkFreq); + +#ifdef __cplusplus +} +#endif + +#endif /* __CW32L012_STARTKIT_H */ diff --git a/新单片机-CW32L012/MCU厂资料/CW32L012_UserManual_CN_V1.3.pdf b/新单片机-CW32L012/MCU厂资料/CW32L012_UserManual_CN_V1.3.pdf new file mode 100644 index 0000000..f793a23 Binary files /dev/null and b/新单片机-CW32L012/MCU厂资料/CW32L012_UserManual_CN_V1.3.pdf differ diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/MDK/QQT912_L012.uvprojx b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/MDK/QQT912_L012.uvprojx new file mode 100644 index 0000000..fff69b6 --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/MDK/QQT912_L012.uvprojx @@ -0,0 +1,264 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + CW32L012C8 + WHXY + WHXY.CW32L012_DFP.1.0.0 + IRAM(0x20000000,0x02000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(64000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashCW32L012_TEST -FS00 -FL010000 -FP0($$Device:CW32L012C8$Flash\FlashCW32L012_TEST.FLM)) + 0 + $$Device:CW32L012C8$Device\Include\cw32l012.h + .\Objects\ + QQT912_L012 + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + "Cortex-M0+" + 1 + 1 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 1 + 1 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x20000000 + 0x2000 + + + + + 1 + 1 + 0 + 1 + + ..\..\..\..\MCU厂资料\CW32L012_StandardPeripheralLib_V1.0.3\IDEsupport\MDK;..\..\..\..\MCU厂资料\CW32L012_StandardPeripheralLib_V1.0.3\Libraries\inc;..\USER\inc + + + + 1 + 0x00000000 + 0x20000000 + + + + + + Startup + + + startup_cw32l012.s + 2 + ..\..\..\..\MCU厂资料\CW32L012_StandardPeripheralLib_V1.0.3\IDEsupport\MDK\startup_cw32l012.s + + + system_cw32l012.c + 1 + ..\..\..\..\MCU厂资料\CW32L012_StandardPeripheralLib_V1.0.3\Libraries\src\system_cw32l012.c + + + + + User + + + main.c + 1 + ..\USER\src\main.c + + + init.c + 1 + ..\USER\src\init.c + + + motor.c + 1 + ..\USER\src\motor.c + + + globalv.c + 1 + ..\USER\src\globalv.c + + + control.c + 1 + ..\USER\src\control.c + + + compu.c + 1 + ..\USER\src\compu.c + + + pid.c + 1 + ..\USER\src\pid.c + + + interrupts_cw32l012.c + 1 + ..\USER\src\interrupts_cw32l012.c + + + + + Driver + + + cw32l012_sysctrl.c + 1 + ..\..\..\..\MCU厂资料\CW32L012_StandardPeripheralLib_V1.0.3\Libraries\src\cw32l012_sysctrl.c + + + cw32l012_gpio.c + 1 + ..\..\..\..\MCU厂资料\CW32L012_StandardPeripheralLib_V1.0.3\Libraries\src\cw32l012_gpio.c + + + cw32l012_atim.c + 1 + ..\..\..\..\MCU厂资料\CW32L012_StandardPeripheralLib_V1.0.3\Libraries\src\cw32l012_atim.c + + + cw32l012_gtim.c + 1 + ..\..\..\..\MCU厂资料\CW32L012_StandardPeripheralLib_V1.0.3\Libraries\src\cw32l012_gtim.c + + + cw32l012_btim.c + 1 + ..\..\..\..\MCU厂资料\CW32L012_StandardPeripheralLib_V1.0.3\Libraries\src\cw32l012_btim.c + + + cw32l012_adc.c + 1 + ..\..\..\..\MCU厂资料\CW32L012_StandardPeripheralLib_V1.0.3\Libraries\src\cw32l012_adc.c + + + cw32l012_uart.c + 1 + ..\..\..\..\MCU厂资料\CW32L012_StandardPeripheralLib_V1.0.3\Libraries\src\cw32l012_uart.c + + + cw32l012_flash.c + 1 + ..\..\..\..\MCU厂资料\CW32L012_StandardPeripheralLib_V1.0.3\Libraries\src\cw32l012_flash.c + + + cw32l012_systick.c + 1 + ..\..\..\..\MCU厂资料\CW32L012_StandardPeripheralLib_V1.0.3\Libraries\src\cw32l012_systick.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/compu.h b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/compu.h new file mode 100644 index 0000000..d5fd06b --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/compu.h @@ -0,0 +1,4 @@ +#include "globalv.h" + +void SampleSpeed(void); +void SampleVI(void); diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/control.h b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/control.h new file mode 100644 index 0000000..a744ee2 --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/control.h @@ -0,0 +1,20 @@ +#include "globalv.h" +#include "compu.h" +#include "motor.h" +#include "pid.h" + +void MotorStartCheck(void); +void MotorStartDealy(void); +void MotorStartOPEN(void); +void MotorRunOPEN(void); +void MotorStartPID(void); +void MotorRunPID(void); +void MotorStop(void); +void MotorError(void); +void MotorErrorOver(void); +void MotorBreak(void); +void WaitStart(void); +void EnDirCheck(void); + +extern void Send_Value(void); + diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/globalv.h b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/globalv.h new file mode 100644 index 0000000..0784f17 --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/globalv.h @@ -0,0 +1,130 @@ +#include "main.h" + +#define LED_GPIO_PIN GPIO_PIN_13 +#define LED_GPIO_PORT CW_GPIOC +#define LEDON() {GPIO_WritePin(LED_GPIO_PORT, LED_GPIO_PIN, GPIO_Pin_RESET);} +#define LEDOFF() {GPIO_WritePin(LED_GPIO_PORT, LED_GPIO_PIN, GPIO_Pin_SET);} +#define LEDTOG() {GPIO_TogglePin(LED_GPIO_PORT, LED_GPIO_PIN);} + +#define BKIN_GPIO_PIN GPIO_PIN_11 +#define BKIN_GPIO_PORT CW_GPIOA + +#define DR_GPIO_PIN GPIO_PIN_5 +#define DR_GPIO_PORT CW_GPIOB + +#define EN_GPIO_PIN GPIO_PIN_14 +#define EN_GPIO_PORT CW_GPIOC + +#define VOUT_EN_GPIO_PIN GPIO_PIN_6 +#define VOUT_EN_GPIO_PORT CW_GPIOF + +#define LEDDIR_GPIO_PIN GPIO_PIN_12 +#define LEDDIR_GPIO_PORT CW_GPIOA + +#define LEDSTSTO_GPIO_PIN GPIO_PIN_11 +#define LEDSTSTO_GPIO_PORT CW_GPIOB + +#define PWM_AP_PORT (CW_GPIOA) +#define PWM_AP_PIN (GPIO_PIN_8) +#define PWM_AN_PORT (CW_GPIOB) +#define PWM_AN_PIN (GPIO_PIN_13) + +#define PWM_BP_PORT (CW_GPIOA) +#define PWM_BP_PIN (GPIO_PIN_9) +#define PWM_BN_PORT (CW_GPIOB) +#define PWM_BN_PIN (GPIO_PIN_14) + +#define PWM_CP_PORT (CW_GPIOA) +#define PWM_CP_PIN (GPIO_PIN_10) +#define PWM_CN_PORT (CW_GPIOB) +#define PWM_CN_PIN (GPIO_PIN_15) + +#define PWM_AH_OFF GPIO_WritePin(PWM_AP_PORT, PWM_AP_PIN, GPIO_Pin_RESET) +#define PWM_BH_OFF GPIO_WritePin(PWM_BP_PORT, PWM_BP_PIN, GPIO_Pin_RESET) +#define PWM_CH_OFF GPIO_WritePin(PWM_CP_PORT, PWM_CP_PIN, GPIO_Pin_RESET) + +#define PWM_AH_ON GPIO_WritePin(PWM_AP_PORT, PWM_AP_PIN, GPIO_Pin_SET) +#define PWM_BH_ON GPIO_WritePin(PWM_BP_PORT, PWM_BP_PIN, GPIO_Pin_SET) +#define PWM_CH_ON GPIO_WritePin(PWM_CP_PORT, PWM_CP_PIN, GPIO_Pin_SET) + +#define PWM_AL_OFF GPIO_WritePin(PWM_AN_PORT, PWM_AN_PIN, GPIO_Pin_RESET) +#define PWM_BL_OFF GPIO_WritePin(PWM_BN_PORT, PWM_BN_PIN, GPIO_Pin_RESET) +#define PWM_CL_OFF GPIO_WritePin(PWM_CN_PORT, PWM_CN_PIN, GPIO_Pin_RESET) + +#define PWM_AL_ON GPIO_WritePin(PWM_AN_PORT, PWM_AN_PIN, GPIO_Pin_SET) +#define PWM_BL_ON GPIO_WritePin(PWM_BN_PORT, PWM_BN_PIN, GPIO_Pin_SET) +#define PWM_CL_ON GPIO_WritePin(PWM_CN_PORT, PWM_CN_PIN, GPIO_Pin_SET) + +/* 20 kHz PWM @ 64 MHz */ +#define PWM_PERIOD 3199 +#define OnepercentPWM ((PWM_PERIOD + 1) / 100) + +#define STATESTARTCHECK 0 +#define STATESTARTPID 1 +#define STATERUNPID 2 +#define STATESTOP 3 +#define STATEERROR 5 +#define STATEERROROVER 6 + +#define NMAXVD 2950 +#define NMINVD 750 + +#define RS (float)0.005 +#define AP 21 +#define Ikvalue (float)1200 / (float)AP / RS +#define NumErr 2 +#define RV1 1 +#define RV2 20 +#define Kvvalue (float)1.2 / RV1 * (RV1 + RV2) + +extern unsigned int TimeCountCompuSpeed, TimeCountTemp, TimeCountkey; +extern unsigned int TimeCountRealSpd, TimeCountPID, TimeCountAvgSpd, TimeCountVI; + +extern unsigned char MOTORSTATE; + +extern const unsigned int PWM_EN_TAB[6]; +extern const unsigned char STEP_TAB[2][6]; + +extern uint16_t SampleData[4]; + +extern unsigned char ErrorCode; +extern unsigned int Motor_Start_F; +extern unsigned int Cur_step; +extern unsigned char Dir; + +extern unsigned int HALLcount, HALLcount1, HALLcountTemp; +extern unsigned int TargS1; +extern unsigned int RealS1; +extern unsigned int RealS; +extern unsigned int SetSpeed; +extern float KKN, KPWMN; + +extern unsigned int OutPwmValue; + +extern unsigned char ErrCleFlag; + +extern unsigned int SpeedD; + +extern unsigned int DIin; +extern unsigned int CanshuV; +extern unsigned int CanshuI; + +extern unsigned int MPolePairs; +extern unsigned int MAXSPEED; +extern unsigned int CanshuTimeDelay; + +extern unsigned int ISH; +extern unsigned int VSH; +extern unsigned int LSH; + +extern unsigned int PWMMin; +extern unsigned int PWMMax; +extern unsigned int TImeUP; + +extern unsigned int MINSPEED; +extern unsigned int CanshuSTT; +extern unsigned int SP, SI, SD; + +extern unsigned int STEP_last; +extern unsigned int startflag, dirflag; +extern unsigned int LevelSet; diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/init.h b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/init.h new file mode 100644 index 0000000..131dcb0 --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/init.h @@ -0,0 +1,3 @@ +#include "init.h" + +void ADC1_SampleCallback(void); diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/interrupts_cw32l012.h b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/interrupts_cw32l012.h new file mode 100644 index 0000000..24ae109 --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/interrupts_cw32l012.h @@ -0,0 +1,12 @@ +#ifndef __INTERRUPTS_CW32L012_H +#define __INTERRUPTS_CW32L012_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __INTERRUPTS_CW32L012_H */ diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/main.h b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/main.h new file mode 100644 index 0000000..8115271 --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/main.h @@ -0,0 +1,27 @@ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "cw32l012.h" +#include "system_cw32l012.h" +#include "interrupts_cw32l012.h" +#include "cw32l012_sysctrl.h" +#include "cw32l012_gpio.h" +#include "cw32l012_adc.h" +#include "cw32l012_atim.h" +#include "cw32l012_btim.h" +#include "cw32l012_dma.h" +#include "cw32l012_flash.h" +#include "cw32l012_gtim.h" +#include "cw32l012_uart.h" +#include "cw32l012_systick.h" + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/motor.h b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/motor.h new file mode 100644 index 0000000..c0f9d33 --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/motor.h @@ -0,0 +1,14 @@ +#include "main.h" + +#include "globalv.h" +#include "init.h" + +void PWMtimer_init(void); +void Halltimer_init(void); + +void Commutation(unsigned int step,unsigned int PWM_ON_flag); +void UPPWM(void); +unsigned char HALL_Check(void); +//void Halltimer_ioinit(void); +void HALL_MOTOR_START(void); +void MOTOR_STOP0(void); diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/pid.h b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/pid.h new file mode 100644 index 0000000..9a25f8b --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/inc/pid.h @@ -0,0 +1,6 @@ +#include "motor.h" +#include "globalv.h" + +void PID_init(void); +void PIDcompute(unsigned int Target,unsigned int Real); +void PIDIcompute(unsigned int Target,unsigned int Real); diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/compu.c b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/compu.c new file mode 100644 index 0000000..4c00cea --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/compu.c @@ -0,0 +1,76 @@ +#include "compu.h" + +void SampleSpeed(void) +{ + unsigned int tem=0; + unsigned int st=0; + + st=SampleData[2]; + + if(st=ISH*1000&&ErrorCode==0) // + { + + IErCount++; + if(IErCount>=NumErr) + { + ErrorCode=4; + + } + } + else IErCount=0; + + t =SampleData[3]; + t=t/4096*5.0/RV1*(RV1+RV2); + CanshuV=t*10; //ɼĸߵѹŴ10 + + if(CanshuV>=VSH*10&&ErrorCode==0) //ѹж + { + VErCount++; + if(VErCount>=NumErr) + {ErrorCode=6;} + } + else VErCount=0; + +} diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/control.c b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/control.c new file mode 100644 index 0000000..f7412db --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/control.c @@ -0,0 +1,133 @@ +#include "control.h" + +extern unsigned char save_flag; +extern void Flash_Save(void); + +void MotorStartCheck(void) +{ + if(MOTORSTATE==STATEERROR)return; + + if(SetSpeed>0&&startflag==1) + { + MOTORSTATE=STATESTARTPID; + Dir=dirflag; + HALLcount=0; + HALLcount1=0; + HALLcountTemp=0; + } +} + +void MotorStartPID(void) +{ + if(MOTORSTATE==STATEERROR)return; + + PID_init(); + PIDcompute(MINSPEED,0); + HALL_MOTOR_START(); + + TargS1=SetSpeed; + MOTORSTATE=STATERUNPID; +} + +void MotorRunPID(void) +{ + + if(MOTORSTATE==STATEERROR)return; + if(SetSpeed==0||startflag==0) //ֹͣź + { + MOTORSTATE=STATESTOP; + } + + TargS1=SetSpeed; + if(TimeCountPID>=20)//ʵʱٶȲʱPID + { + TimeCountPID=0; + RealS1=HALLcountTemp*500/MPolePairs;//HALLcount*100*60/6/POLEPAIRS; + PIDcompute(TargS1,RealS1); + } +} + +void MotorStop(void) +{ + if(MOTORSTATE==STATEERROR)return; + Motor_Start_F=0; + MOTOR_STOP0(); + + if(RealS==0) + { + MOTORSTATE=STATESTARTCHECK; //ͣл + } +} + +void MotorError(void) +{ + MOTOR_STOP0(); + Motor_Start_F=0; + MOTORSTATE=STATEERROROVER; + printf("MotorError\n"); +} + +void MotorBreak(void) +{ + unsigned int dd; + if(GPIO_ReadPin(BKIN_GPIO_PORT,BKIN_GPIO_PIN)==GPIO_Pin_RESET) + { + for(dd=0;dd<500;dd++) + {;} + if(GPIO_ReadPin(BKIN_GPIO_PORT,BKIN_GPIO_PIN)==GPIO_Pin_RESET) + { + MOTOR_STOP0(); + Motor_Start_F=0; + while(GPIO_ReadPin(BKIN_GPIO_PORT,BKIN_GPIO_PIN)==GPIO_Pin_RESET); + } + } +} + +void MotorErrorOver(void) +{ + unsigned char times=0; + + times=0; + + LEDOFF();TimeCountTemp=0; + while(TimeCountTemp<200); + while(1) //ϣָʾ˸ + { + SampleSpeed(); + if(SetSpeed == 0) //ʱٺָ + { + ErrorCode = 0; + WaitStart(); + GPIO_WritePin(VOUT_EN_GPIO_PORT,VOUT_EN_GPIO_PIN,GPIO_Pin_SET); + break; + } + + } +} + +void WaitStart(void) +{ + if(SetSpeed==0) MOTORSTATE=STATESTARTCHECK; +} + +void EnDirCheck(void) +{ + + + if((GPIO_ReadPin(EN_GPIO_PORT,EN_GPIO_PIN)==GPIO_Pin_SET)\ + &&(GPIO_ReadPin(DR_GPIO_PORT,DR_GPIO_PIN)==GPIO_Pin_SET) ) + { + LevelSet = 2; + } + else if((GPIO_ReadPin(EN_GPIO_PORT,EN_GPIO_PIN)==GPIO_Pin_RESET)\ + &&(GPIO_ReadPin(DR_GPIO_PORT,DR_GPIO_PIN)==GPIO_Pin_SET) ) + { + LevelSet = 3; + } + if((GPIO_ReadPin(EN_GPIO_PORT,EN_GPIO_PIN)==GPIO_Pin_SET)\ + &&(GPIO_ReadPin(DR_GPIO_PORT,DR_GPIO_PIN)==GPIO_Pin_RESET) ) + { + LevelSet = 1; + } + printf("Level=%d\n",LevelSet); +} diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/globalv.c b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/globalv.c new file mode 100644 index 0000000..2ff4f0c --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/globalv.c @@ -0,0 +1,44 @@ +#include "globalv.h" + +unsigned int TimeCountCompuSpeed = 0, TimeCountTemp = 0, TimeCountkey = 0; +unsigned int TimeCountRealSpd = 0, TimeCountPID = 0, TimeCountAvgSpd = 0, TimeCountVI = 0; + +unsigned char MOTORSTATE = STATESTARTCHECK; + +const unsigned int PWM_EN_TAB[6] = {0x001, 0x001, 0x010, 0x010, 0x100, 0x100}; +const unsigned char STEP_TAB[2][6] = {{1, 3, 2, 5, 0, 4}, {4, 0, 5, 2, 3, 1}}; + +uint16_t SampleData[4]; + +unsigned char ErrorCode = 0; +unsigned int Motor_Start_F = 0; +unsigned int Cur_step = 0; +unsigned char Dir = 1; + +unsigned int HALLcount = 0, HALLcount1 = 0, HALLcountTemp; +unsigned int TargS1 = 150; +unsigned int RealS1 = 0; +unsigned int RealS = 0; +unsigned int SetSpeed = 0; +float KKN = 0, KPWMN = 0; + +unsigned int OutPwmValue = 0; + +unsigned int DIin = 0; +unsigned int CanshuV = 0; +unsigned int CanshuI = 0; + +unsigned int MPolePairs = 15; +unsigned int MAXSPEED = 680; + +unsigned int ISH = 8; +unsigned int VSH = 40; +unsigned int LSH = 9; + +unsigned int MINSPEED = 10; +unsigned int SP = 50, SI = 50, SD = 50; + +unsigned int STEP_last; + +unsigned int startflag = 0, dirflag = 1; +unsigned int LevelSet = 1; diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/init.c b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/init.c new file mode 100644 index 0000000..9c8374a --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/init.c @@ -0,0 +1,133 @@ +#include "globalv.h" +#include "init.h" + +void RCC_Configuration(void) +{ + PLL_InitTypeDef PLL_InitStruct = { + .ClockSource = SYSCTRL_PLL_SOURCE_HSI_48M, + .PLL_OutFreq = 64000000, + .SourceFreq = 48000000, + .WaitCycle = SYSCTRL_PLL_WAIT_CYCLE_2048 + }; + + SYSCTRL_HSI_Enable(HSIOSC_TO_HSI96MHZ); + SYSCTRL_HCLKPRS_Config(SYSCTRL_HCLK_DIV1); + SYSCTRL_PCLKPRS_Config(SYSCTRL_PCLK_DIV1); + + __SYSCTRL_FLASH_CLK_ENABLE(); + FLASH_SetLatency(FLASH_Latency_3); + + if (SYSCTRL_PLL_Enable(&PLL_InitStruct) == 0) + { + SYSCTRL_SysClk_Switch(SYSCTRL_SYSCLKSRC_PLL); + SYSCTRL_SystemCoreClockUpdate(64000000); + } + else + { + SYSCTRL_SystemCoreClockUpdate(96000000); + } +} + +void GPIOInit(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + __SYSCTRL_GPIOC_CLK_ENABLE(); + __SYSCTRL_GPIOF_CLK_ENABLE(); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + + GPIO_InitStruct.Pins = LED_GPIO_PIN; + GPIO_Init(LED_GPIO_PORT, &GPIO_InitStruct); + + GPIO_InitStruct.Pins = VOUT_EN_GPIO_PIN; + GPIO_Init(VOUT_EN_GPIO_PORT, &GPIO_InitStruct); + GPIO_WritePin(VOUT_EN_GPIO_PORT, VOUT_EN_GPIO_PIN, GPIO_Pin_RESET); + + GPIO_InitStruct.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_InitStruct.Pins = EN_GPIO_PIN; + GPIO_Init(EN_GPIO_PORT, &GPIO_InitStruct); + GPIO_InitStruct.Pins = DR_GPIO_PIN; + GPIO_Init(DR_GPIO_PORT, &GPIO_InitStruct); + GPIO_InitStruct.Pins = BKIN_GPIO_PIN; + GPIO_Init(BKIN_GPIO_PORT, &GPIO_InitStruct); +} + +static void ADC_UpdateSampleBuffer(void) +{ + SampleData[0] = ADC_GetConversionValue(CW_ADC1, 0); + SampleData[1] = ADC_GetConversionValue(CW_ADC1, 1); + SampleData[2] = ADC_GetConversionValue(CW_ADC1, 2); + SampleData[3] = ADC_GetConversionValue(CW_ADC1, 3); +} + +void ADC1_SampleCallback(void) +{ + if (ADC_GetITStatus(CW_ADC1, ADC_IT_EOS) != RESET) + { + ADC_ClearITPendingBit(CW_ADC1, ADC_IT_EOS); + ADC_UpdateSampleBuffer(); + } +} + +void ADC_Configuration(void) +{ + ADC_InitTypeDef ADC_InitStruct = {0}; + + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_ADC_CLK_ENABLE(); + + PA04_ANALOG_ENABLE(); + PA05_ANALOG_ENABLE(); + PA06_ANALOG_ENABLE(); + PA07_ANALOG_ENABLE(); + + ADC_InitStruct.ADC_ClkDiv = ADC_Clk_Div2; + ADC_InitStruct.ADC_SlaveMod = ADC_SlaveMode_Disable; + ADC_InitStruct.ADC_ConvertMode = ADC_ConvertMode_Once; + ADC_InitStruct.ADC_SQREns = ADC_SqrEns0to3; + ADC_InitStruct.ADC_IN0.ADC_InputChannel = ADC_InputCH5; + ADC_InitStruct.ADC_IN0.ADC_SampTime = ADC_SampTime70Clk; + ADC_InitStruct.ADC_IN1.ADC_InputChannel = ADC_InputCH6; + ADC_InitStruct.ADC_IN1.ADC_SampTime = ADC_SampTime70Clk; + ADC_InitStruct.ADC_IN2.ADC_InputChannel = ADC_InputCH7; + ADC_InitStruct.ADC_IN2.ADC_SampTime = ADC_SampTime70Clk; + ADC_InitStruct.ADC_IN3.ADC_InputChannel = ADC_InputCH4; + ADC_InitStruct.ADC_IN3.ADC_SampTime = ADC_SampTime70Clk; + ADC_Init(CW_ADC1, &ADC_InitStruct); + ADC_ClearITPendingAll(CW_ADC1); + + ADC_ExtTrigCfg(CW_ADC1, ADC_TRIG_ATIMOC4REFC, ENABLE); + ADC_ITConfig(CW_ADC1, ADC_IT_EOS, ENABLE); + ADC_Enable(CW_ADC1); + + __disable_irq(); + NVIC_EnableIRQ(ADC1_IRQn); + __enable_irq(); + + ADC_SoftwareStartConvCmd(CW_ADC1, ENABLE); +} + +void BTIM_init(void) +{ + BTIM_TimeBaseInitTypeDef BTIM_InitStruct = {0}; + + __SYSCTRL_BTIM123_CLK_ENABLE(); + + __disable_irq(); + NVIC_EnableIRQ(BTIM1_IRQn); + __enable_irq(); + + BTIM_InitStruct.BTIM_Mode = BTIM_MODE_TIMER; + BTIM_InitStruct.BTIM_CountMode = BTIM_COUNT_MODE_REPETITIVE; + BTIM_InitStruct.BTIM_Period = 3999; + BTIM_InitStruct.BTIM_Prescaler = 15; + BTIM_TimeBaseInit(CW_BTIM1, &BTIM_InitStruct); + + BTIM_ITConfig(CW_BTIM1, BTIM_IT_UPDATE, ENABLE); + BTIM_Cmd(CW_BTIM1, ENABLE); +} diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/interrupts_cw32l012.c b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/interrupts_cw32l012.c new file mode 100644 index 0000000..4f27d92 --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/interrupts_cw32l012.c @@ -0,0 +1,138 @@ +#include "../inc/main.h" +#include "../inc/init.h" + +void NMI_Handler(void) +{ +} + +void HardFault_Handler(void) +{ + while (1) + { + } +} + +void SVC_Handler(void) +{ +} + +void PendSV_Handler(void) +{ +} + +void WDT_IRQHandler(void) +{ +} + +void LVD_IRQHandler(void) +{ +} + +void RTC_IRQHandler(void) +{ +} + +void FLASHRAM_IRQHandler(void) +{ +} + +void SYSCTRL_IRQHandler(void) +{ +} + +void GPIOA_IRQHandler(void) +{ +} + +void GPIOB_IRQHandler(void) +{ +} + +void GPIOC_IRQHandler(void) +{ +} + +void GPIOF_IRQHandler(void) +{ +} + +void DMACH12_IRQHandler(void) +{ +} + +void DMACH34_IRQHandler(void) +{ +} + +void CORDIC_IRQHandler(void) +{ +} + +void ADC1_IRQHandler(void) +{ + ADC1_SampleCallback(); +} + +void VC13_IRQHandler(void) +{ +} + +void VC24_IRQHandler(void) +{ +} + +void GTIM1_IRQHandler(void) +{ +} + +void GTIM34_IRQHandler(void) +{ +} + +void LPTIM_IRQHandler(void) +{ +} + +void BTIM2_IRQHandler(void) +{ +} + +void BTIM3_HALLTIM_IRQHandler(void) +{ +} + +void I2C1_IRQHandler(void) +{ +} + +void I2C2_IRQHandler(void) +{ +} + +void SPI1_IRQHandler(void) +{ +} + +void SPI23_IRQHandler(void) +{ +} + +void UART1_IRQHandler(void) +{ +} + +void UART2_IRQHandler(void) +{ +} + +void UART3_IRQHandler(void) +{ +} + +void ADC2_DAC_IRQHandler(void) +{ +} + +void CLKFAULT_IRQHandler(void) +{ +} diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/main.c b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/main.c new file mode 100644 index 0000000..78e4f22 --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/main.c @@ -0,0 +1,284 @@ +/* +2页菜单：1：设定速度、实时速度； 2：母线电压、电流显示。 +Designed by Cache.lee from UET company +Ported to CW32L012 +*/ +#include "main.h" +#include "motor.h" +#include "globalv.h" +#include "init.h" +#include "pid.h" +#include "compu.h" +#include "control.h" + +unsigned int Menu = 0; + +#define DEBUG_UARTx CW_UART3 +#define DEBUG_UART_CLK SYSCTRL_APB1_PERIPH_UART3 +#define DEBUG_UART_APBClkENx SYSCTRL_APBPeriphClk_Enable1 +#define DEBUG_UART_BaudRate 115200 +#define DEBUG_UART_UclkFreq 64000000 + +#define DEBUG_UART_GPIO_CLK SYSCTRL_AHB_PERIPH_GPIOB +#define DEBUG_UART_TX_GPIO_PORT CW_GPIOB +#define DEBUG_UART_TX_GPIO_PIN GPIO_PIN_6 +#define DEBUG_UART_RX_GPIO_PORT CW_GPIOB +#define DEBUG_UART_RX_GPIO_PIN GPIO_PIN_7 + +#define DEBUG_UART_AFTX PB06_AFx_UART3TXD() +#define DEBUG_UART_AFRX PB07_AFx_UART3RXD() + +#ifdef __GNUC__ +#define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else +#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif + +void UART_Configuration(void) +{ + UART_InitTypeDef UART_InitStructure = {0}; + GPIO_InitTypeDef GPIO_InitStructure = {0}; + + SYSCTRL_AHBPeriphClk_Enable(DEBUG_UART_GPIO_CLK, ENABLE); + DEBUG_UART_APBClkENx(DEBUG_UART_CLK, ENABLE); + + DEBUG_UART_AFTX; + DEBUG_UART_AFRX; + + GPIO_InitStructure.Pins = DEBUG_UART_TX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_Init(DEBUG_UART_TX_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pins = DEBUG_UART_RX_GPIO_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_Init(DEBUG_UART_RX_GPIO_PORT, &GPIO_InitStructure); + + UART_InitStructure.UART_BaudRate = DEBUG_UART_BaudRate; + UART_InitStructure.UART_Over = UART_Over_16; + UART_InitStructure.UART_Source = UART_Source_PCLK; + UART_InitStructure.UART_UclkFreq = DEBUG_UART_UclkFreq; + UART_InitStructure.UART_StartBit = UART_StartBit_FE; + UART_InitStructure.UART_StopBits = UART_StopBits_1; + UART_InitStructure.UART_Parity = UART_Parity_No; + UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStructure.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; + UART_Init(DEBUG_UARTx, &UART_InitStructure); +} + +PUTCHAR_PROTOTYPE +{ + UART_SendData(DEBUG_UARTx, (uint8_t)ch); + while (UART_GetFlagStatus(DEBUG_UARTx, UART_FLAG_TXE) == RESET) + { + } + return ch; +} + +#ifdef USE_FULL_ASSERT +void assert_failed(uint8_t *file, uint32_t line) +{ + (void)file; + (void)line; +} +#endif + +void PowerOnDelay(void) +{ + unsigned int i; + + for (i = 0; i < 6; i++) + { + volatile unsigned int j; + for (j = 0; j < 60000; j++) + { + } + } + + KKN = (MAXSPEED - MINSPEED); + KKN = KKN / (NMAXVD - NMINVD); +} + +unsigned int hte = 0; + +int main(void) +{ + unsigned char DZCount = 0; + char temp_buff[100], temp_buff1[50]; + + PowerOnDelay(); + RCC_Configuration(); + UART_Configuration(); + GPIOInit(); + LEDON(); + ADC_Configuration(); + PWMtimer_init(); + BTIM_init(); + Halltimer_init(); + + PWM_AL_ON; + PWM_BL_ON; + PWM_CL_ON; + TimeCountTemp = 0; + while (TimeCountTemp < 50) + { + } + TimeCountTemp = 0; + PWM_AL_OFF; + PWM_BL_OFF; + PWM_CL_OFF; + + printf("Update %s %s\r\n", __DATE__, __TIME__); + printf("CW32L012 BLDC Hall PID\r\n"); + printf("ADC[0]:%d ADC[1]:%d ADC[2]:%d ADC[3]:%d\r\n", + SampleData[0], SampleData[1], SampleData[2], SampleData[3]); + + SampleVI(); + startflag = 1; + EnDirCheck(); + + DIin = 0x500; + if (SampleData[1] > 1117 && SampleData[1] <= 1500) + { + DIin = SampleData[1]; + } + else + { + printf("Current read err\r\n"); + } + if (SampleData[2] > 3000 || SampleData[2] < 700) + { + printf("Speed read err\r\n"); + } + if (HALL_Check() == 0 || HALL_Check() == 7) + { + printf("HALL Read Err\r\n"); + } + if (CanshuV < 30) + { + printf("Votage read err\r\n"); + } + sprintf(temp_buff1, "Set :%4d RPM ", SetSpeed); + sprintf(temp_buff, "Real:%4d RPM ", RealS); + printf("%s\r\n", temp_buff); + printf("%s\r\n", temp_buff1); + sprintf(temp_buff1, "Vbus :%d.%d V ", CanshuV / 10, CanshuV % 10); + sprintf(temp_buff, "I(MA):%d ", CanshuI); + printf("%s\r\n", temp_buff); + printf("%s\r\n", temp_buff1); + GPIO_WritePin(VOUT_EN_GPIO_PORT, VOUT_EN_GPIO_PIN, GPIO_Pin_SET); + + while (1) + { + if (TimeCountCompuSpeed > 20) + { + TimeCountCompuSpeed = 0; + SampleSpeed(); + HALL_Check(); + } + + if (TimeCountVI >= 200) + { + printf("ADC[0]:%d ADC[1]:%d ADC[2]:%d ADC[3]:%d\r\n", + SampleData[0], SampleData[1], SampleData[2], SampleData[3]); + + TimeCountVI = 0; + SampleVI(); + + RealS = hte * 50 / MPolePairs; + + if (MOTORSTATE == STATESTARTPID || MOTORSTATE == STATERUNPID) + { + if (RealS == 0) + { + DZCount++; + if (DZCount >= 10) + { + DZCount = 0; + ErrorCode = 7; + } + } + else + { + DZCount = 0; + } + } + } + + if (ErrorCode != 0 && MOTORSTATE != STATEERROR && MOTORSTATE != STATEERROROVER) + { + MOTORSTATE = STATEERROR; + printf("ErrorCode=%d\r\n", ErrorCode); + GPIO_WritePin(VOUT_EN_GPIO_PORT, VOUT_EN_GPIO_PIN, GPIO_Pin_RESET); + } + + if (TimeCountkey >= 500) + { + LEDTOG(); + TimeCountkey = 0; + sprintf(temp_buff1, "Set :%4d RPM ", SetSpeed); + sprintf(temp_buff, "Real:%4d RPM ", RealS); + printf("%s\r\n", temp_buff); + printf("%s\r\n", temp_buff1); + sprintf(temp_buff1, "Vbus :%d.%d V ", CanshuV / 10, CanshuV % 10); + sprintf(temp_buff, "I(MA):%d ", CanshuI); + printf("%s\r\n", temp_buff); + printf("%s\r\n", temp_buff1); + } + + MotorBreak(); + EnDirCheck(); + + switch (MOTORSTATE) + { + case STATESTARTCHECK: + MotorStartCheck(); + break; + case STATESTARTPID: + MotorStartPID(); + break; + case STATERUNPID: + MotorRunPID(); + break; + case STATESTOP: + MotorStop(); + break; + case STATEERROR: + MotorError(); + break; + case STATEERROROVER: + MotorErrorOver(); + break; + default: + break; + } + } +} + +void BTIM1_IRQHandler(void) +{ + if (BTIM_GetITStatus(CW_BTIM1, BTIM_IT_UPDATE) != RESET) + { + BTIM_ClearITPendingBit(CW_BTIM1, BTIM_IT_UPDATE); + + TimeCountTemp++; + TimeCountCompuSpeed++; + TimeCountRealSpd++; + if (TimeCountAvgSpd >= 200) + { + hte = HALLcount1; + HALLcount1 = 0; + TimeCountAvgSpd = 0; + } + if (TimeCountRealSpd >= 20) + { + HALLcountTemp = HALLcount; + HALLcount = 0; + TimeCountRealSpd = 0; + } + TimeCountPID++; + TimeCountAvgSpd++; + TimeCountVI++; + TimeCountkey++; + } +} diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/motor.c b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/motor.c new file mode 100644 index 0000000..c58cf39 --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/motor.c @@ -0,0 +1,289 @@ +#include "motor.h" +#include "globalv.h" + +static void MotorPwmSetCompare(unsigned int ch1, unsigned int ch2, unsigned int ch3) +{ + ATIM_SetCompare1((uint16_t)ch1); + ATIM_SetCompare2((uint16_t)ch2); + ATIM_SetCompare3((uint16_t)ch3); +} + +void PWMtimer_init(void) +{ + ATIM_InitTypeDef ATIM_InitStruct = {0}; + ATIM_OCInitTypeDef ATIM_OCInitStruct = {0}; + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + __SYSCTRL_ATIM_CLK_ENABLE(); + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + + PA08_AFx_ATIMCH1(); + PA09_AFx_ATIMCH2(); + PA10_AFx_ATIMCH3(); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pins = GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + + PWM_AH_OFF; + PWM_BH_OFF; + PWM_CH_OFF; + + ATIM_InitStruct.BufferState = ENABLE; + ATIM_InitStruct.CounterAlignedMode = ATIM_COUNT_ALIGN_MODE_EDGE; + ATIM_InitStruct.CounterDirection = ATIM_COUNTING_UP; + ATIM_InitStruct.CounterOPMode = ATIM_OP_MODE_REPETITIVE; + ATIM_InitStruct.Prescaler = 0; + ATIM_InitStruct.ReloadValue = PWM_PERIOD; + ATIM_InitStruct.RepetitionCounter = 0; + ATIM_Init(&ATIM_InitStruct); + + ATIM_OCInitStruct.BufferState = DISABLE; + ATIM_OCInitStruct.OCComplement = DISABLE; + ATIM_OCInitStruct.OCFastMode = ATIM_OC_FAST_MODE_DISABLE; + ATIM_OCInitStruct.OCInterruptState = DISABLE; + ATIM_OCInitStruct.OCMode = ATIM_OCMODE_PWM1; + ATIM_OCInitStruct.OCPolarity = ATIM_OCPOLARITY_NONINVERT; + ATIM_OC1Init(&ATIM_OCInitStruct); + ATIM_OC2Init(&ATIM_OCInitStruct); + ATIM_OC3Init(&ATIM_OCInitStruct); + ATIM_OC4Init(&ATIM_OCInitStruct); + + MotorPwmSetCompare(0, 0, 0); + ATIM_SetCompare4((uint16_t)(PWM_PERIOD / 2)); + + ATIM_CH1Config(ENABLE); + ATIM_CH2Config(ENABLE); + ATIM_CH3Config(ENABLE); + ATIM_CH4Config(ENABLE); + + ATIM_Cmd(ENABLE); + ATIM_CtrlPWMOutputs(ENABLE); +} + +void ATIM_IRQHandler(void) +{ + if (ATIM_GetITStatus(ATIM_IT_UIE) != RESET) + { + ATIM_ClearITPendingBit(ATIM_IT_UIE); + } +} + +void Commutation(unsigned int step, unsigned int PWM_ON_flag) +{ + if (PWM_ON_flag == 0 || MOTORSTATE == STATEERROR || MOTORSTATE == STATEERROROVER) + { + MotorPwmSetCompare(0, 0, 0); + PWM_AL_OFF; + PWM_BL_OFF; + PWM_CL_OFF; + return; + } + + if (step == 0 || step == 5) + { + PWM_AL_OFF; + PWM_CL_OFF; + } + else if (step == 1 || step == 2) + { + PWM_AL_OFF; + PWM_BL_OFF; + } + else if (step == 3 || step == 4) + { + PWM_BL_OFF; + PWM_CL_OFF; + } + + if (step == 0 || step == 1) + { + MotorPwmSetCompare(OutPwmValue, 0, 0); + } + if (step == 2 || step == 3) + { + MotorPwmSetCompare(0, OutPwmValue, 0); + } + if (step == 4 || step == 5) + { + MotorPwmSetCompare(0, 0, OutPwmValue); + } + + if (step == 0 || step == 5) + { + PWM_BL_ON; + } + else if (step == 1 || step == 2) + { + PWM_CL_ON; + } + else if (step == 3 || step == 4) + { + PWM_AL_ON; + } + + STEP_last = step; +} + +void UPPWM(void) +{ + if (STEP_last == 0 || STEP_last == 1) + { + MotorPwmSetCompare(OutPwmValue, 0, 0); + } + if (STEP_last == 2 || STEP_last == 3) + { + MotorPwmSetCompare(0, OutPwmValue, 0); + } + if (STEP_last == 4 || STEP_last == 5) + { + MotorPwmSetCompare(0, 0, OutPwmValue); + } +} + +void Halltimer_init(void) +{ + GTIM_InitTypeDef GTIM_InitStruct = {0}; + GTIM_ICModeCfgTypeDef GTIM_ICInitStruct = {0}; + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + __SYSCTRL_GTIM2_CLK_ENABLE(); + __SYSCTRL_GPIOA_CLK_ENABLE(); + __SYSCTRL_GPIOB_CLK_ENABLE(); + + GPIO_InitStruct.IT = GPIO_IT_NONE; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT_PULLUP; + GPIO_InitStruct.Pins = GPIO_PIN_15 | GPIO_PIN_1; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_Init(CW_GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pins = GPIO_PIN_10; + GPIO_Init(CW_GPIOB, &GPIO_InitStruct); + + PA15_AFx_GTIM2CH1(); + PA01_AFx_GTIM2CH2(); + PB10_AFx_GTIM2CH3(); + + __disable_irq(); + NVIC_EnableIRQ(GTIM2_IRQn); + __enable_irq(); + + GTIM_InitStruct.AlignMode = GTIM_ALIGN_MODE_EDGE; + GTIM_InitStruct.ARRBuffState = GTIM_ARR_BUFF_DIS; + GTIM_InitStruct.Direction = GTIM_DIRECTION_UP; + GTIM_InitStruct.EventOption = GTIM_EVENT_NORMAL; + GTIM_InitStruct.Prescaler = 0; + GTIM_InitStruct.PulseMode = GTIM_PULSE_MODE_DIS; + GTIM_InitStruct.ReloadValue = 0xFFFF; + GTIM_InitStruct.UpdateOption = GTIM_UPDATE_EN; + GTIM_TimeBaseInit(CW_GTIM2, >IM_InitStruct); + + GTIM_ICInitStruct.ICMap = GTIM_IC1_MAP_TI1; + GTIM_ICInitStruct.ICPrescaler = GTIM_IC_PRESCALER_DIV1; + GTIM_ICInitStruct.ICFilter = GTIM_IC_FILTER_PCLK_N2; + GTIM_ICInitStruct.ICPolarity = GTIM_ICPolarity_BothEdge; + GTIM_IC1ModeCfg(CW_GTIM2, >IM_ICInitStruct); + GTIM_IC1Cmd(CW_GTIM2, ENABLE); + + GTIM_ICInitStruct.ICMap = GTIM_IC2_MAP_TI2; + GTIM_IC2ModeCfg(CW_GTIM2, >IM_ICInitStruct); + GTIM_IC2Cmd(CW_GTIM2, ENABLE); + + GTIM_ICInitStruct.ICMap = GTIM_IC3_MAP_TI3; + GTIM_IC3ModeCfg(CW_GTIM2, >IM_ICInitStruct); + GTIM_IC3Cmd(CW_GTIM2, ENABLE); + + GTIM_ITConfig(CW_GTIM2, GTIM_IT_CC1 | GTIM_IT_CC2 | GTIM_IT_CC3, ENABLE); + GTIM_Cmd(CW_GTIM2, ENABLE); +} + +unsigned char HALL_Check(void) +{ + static unsigned char hallerrnum = 0; + unsigned char x = 0; + + if (GPIO_ReadPin(CW_GPIOA, GPIO_PIN_15) != 0) + { + x = 1; + } + if (GPIO_ReadPin(CW_GPIOA, GPIO_PIN_1) != 0) + { + x |= 0x2; + } + if (GPIO_ReadPin(CW_GPIOB, GPIO_PIN_10) != 0) + { + x |= 0x4; + } + + if (x == 0 || x == 7) + { + hallerrnum++; + if (hallerrnum >= 10) + { + hallerrnum = 10; + ErrorCode = 2; + } + } + else + { + hallerrnum = 0; + } + + return x; +} + +void GTIM2_IRQHandler(void) +{ + unsigned char x = 0; + + if (GTIM_GetITStatus(CW_GTIM2, GTIM_IT_CC1) != RESET) + { + GTIM_ClearITPendingBit(CW_GTIM2, GTIM_IT_CC1); + } + if (GTIM_GetITStatus(CW_GTIM2, GTIM_IT_CC2) != RESET) + { + GTIM_ClearITPendingBit(CW_GTIM2, GTIM_IT_CC2); + } + if (GTIM_GetITStatus(CW_GTIM2, GTIM_IT_CC3) != RESET) + { + GTIM_ClearITPendingBit(CW_GTIM2, GTIM_IT_CC3); + } + + x = HALL_Check(); + if (x == 0 || x == 7) + { + return; + } + + HALLcount++; + HALLcount1++; + Cur_step = STEP_TAB[Dir][x - 1]; + if (Motor_Start_F == 1 && ErrorCode == 0) + { + Commutation(Cur_step, Motor_Start_F); + } +} + +void HALL_MOTOR_START(void) +{ + unsigned char x = 0; + + x = HALL_Check(); + if (x == 0 || x == 7) + { + return; + } + Cur_step = STEP_TAB[Dir][x - 1]; + RealS1 = 0; + Motor_Start_F = 1; + Commutation(Cur_step, Motor_Start_F); +} + +void MOTOR_STOP0(void) +{ + Motor_Start_F = 0; + Commutation(0, 0); +} diff --git a/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/pid.c b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/pid.c new file mode 100644 index 0000000..52b6e06 --- /dev/null +++ b/新单片机-CW32L012/原项目程序/SW/12 CW32 BLDC haLL pid OK/USER/src/pid.c @@ -0,0 +1,96 @@ +#include "PID.h" + +float SPEED_P,SPEED_I,SPEED_D=0; + +double SSumError=0,SPrevError=0,SLastError=0; +int SdError=0,SError=0; + +void PID_init(void) +{ + SError=0;SSumError=0;SLastError=0; + + + SPEED_P=(float)SP/1000; + SPEED_I=(float)SI/1000; + SPEED_D=(float)SD/1000; + +// SSumError=OutPwmValue; +// SSumError=SSumError/SPEED_I; +} + +void PIDcompute(unsigned int Target, unsigned int Real) +{ + float j = 0.0f; + + if(Target * MPolePairs < 600) Target = 600 / MPolePairs; + + SError = (Target - Real); + + // ĽĻ + float temp_integral = SSumError + SError; + float integral_limit = PWM_PERIOD / SPEED_I; + + // ޷ + if(temp_integral > integral_limit) { + SSumError = integral_limit; + } else if(temp_integral < -integral_limit) { + SSumError = -integral_limit; + } else { + SSumError = temp_integral; + } + + // ΢ + SdError = SError - SLastError; + SLastError = SError; + + // PID + j = SPEED_P * SError + SPEED_I * SSumError + SPEED_D * SdError; + + // ޷ + if(j > PWM_PERIOD) { + OutPwmValue = PWM_PERIOD; + } else if(j < 1) { + OutPwmValue = 1; + } else { + OutPwmValue = (int)j; + } + + UPPWM(); +} +/* +void PIDcompute(unsigned int Target,unsigned int Real) +{ + float j=0.0,i; + + + if(Target*MPolePairs<600)Target=600/MPolePairs; //٣4Լ150RPM + + SError =(Target-Real); //ƫ + + if(SSumError<500)SSumError=500; + else if(SSumError*SPEED_I>PWM_PERIOD) + { + SSumError=PWM_PERIOD; + SSumError=SSumError/SPEED_I; + } // ֵ󣬲ۼƫֱ + else SSumError +=SError; + + + SdError=SError-SLastError; //΢ƫı仯 + SLastError=SError; //¼ƫ´μ + + i=SPEED_P; + j=SError*i; + i=SPEED_I; + j=j+SSumError*i; + i=SPEED_D; + j=j+SdError*i; + + if(j>PWM_PERIOD)OutPwmValue=PWM_PERIOD; + else if(j<1)OutPwmValue=1; + else OutPwmValue=j; + + + UPPWM(); +} +*/