258 lines
9.6 KiB
ArmAsm
258 lines
9.6 KiB
ArmAsm
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;/*****************************************************************************/
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;/* Startup for ARM */
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;/* Version V1.0 */
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;/* Date 2021-03-12 */
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;/* Target-mcu {MCU_PN_H} */
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;/*****************************************************************************/
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; Stack Configuration
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; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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Stack_Size EQU 0x00000200
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; Heap Configuration
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; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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Heap_Size EQU 0x00000200
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors
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DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ;< -15 Reset Vector, invoked on Power up and warm reset
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DCD NMI_Handler ;< -14 Non maskable Interrupt, cannot be stopped or preempted
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DCD HardFault_Handler ;< -13 Hard Fault, all classes of Fault
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DCD 0 ;< -12 Reserved
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DCD 0 ;< -11 Reserved
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DCD 0 ;< -10 Reserved
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DCD 0 ;< -9 Reserved
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DCD 0 ;< -8 Reserved
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DCD 0 ;< -7 Reserved
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DCD 0 ;< -6 Reserved
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DCD SVC_Handler ;< -5 System Service Call via SVC instruction
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DCD 0 ;< -4 Reserved
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DCD 0 ;< -3 Reserved
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DCD PendSV_Handler ;< -2 Pendable request for system service
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DCD SysTick_Handler ;< -1 System Tick Timer
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DCD WDT_IRQHandler ;< 0 Watch Dog Timer Interrupt Handler
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DCD LVD_IRQHandler ;< 1 Low Voltage Detect Interrupt Handler
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DCD RTC_IRQHandler ;< 2 Real Time Clock Interrupt Handler
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DCD FLASHRAM_IRQHandler ;< 3 Flash/RAM Interrupt Handler
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DCD RCC_IRQHandler ;< 4 RCC Interupt Handler
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DCD GPIOA_IRQHandler ;< 5 GPIOA Interrupt Handler
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DCD GPIOB_IRQHandler ;< 6 GPIOB Interrupt Handler
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DCD GPIOC_IRQHandler ;< 7 GPIOC Interrupt Handler
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DCD GPIOF_IRQHandler ;< 8 GPIOF Interrupt Handler
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DCD DMACH1_IRQHandler ;< 9 DMA Channel 1 Interrupt Handler
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DCD DMACH23_IRQHandler ;< 10 DMA Channel 2/3 Interrupt Handler
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DCD DMACH45_IRQHandler ;< 11 DMA Channel 4/5 Interrupt Handler
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DCD ADC_IRQHandler ;< 12 ADC Interrupt Handler
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DCD ATIM_IRQHandler ;< 13 Advanced Timer Interrupt Handler
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DCD VC1_IRQHandler ;< 14 Voltage Comparator 1 Interrupt Handler
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DCD VC2_IRQHandler ;< 15 Voltage Comparator 2 Interrupt Handler
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DCD GTIM1_IRQHandler ;< 16 General Timer1 Interrupt Handler
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DCD GTIM2_IRQHandler ;< 17 General Timer2 Interrupt Handler
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DCD GTIM3_IRQHandler ;< 18 General Timer3 Interrupt Handler
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DCD GTIM4_IRQHandler ;< 19 General Timer4 Interrupt Handler
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DCD BTIM1_IRQHandler ;< 20 Base Timer1 Interrupt Handler
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DCD BTIM2_IRQHandler ;< 21 Base Timer2 Interrupt Handler
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DCD BTIM3_IRQHandler ;< 22 Base Timer3 Interrupt Handler
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DCD I2C1_IRQHandler ;< 23 I2C1 Interrupt Handler
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DCD I2C2_IRQHandler ;< 24 I2C2 Interrupt Handler
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DCD SPI1_IRQHandler ;< 25 SPI1 Interrupt Handler
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DCD SPI2_IRQHandler ;< 26 SPI2 Interrupt Handler
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DCD UART1_IRQHandler ;< 27 UART1 Interrupt Handler
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DCD UART2_IRQHandler ;< 28 UART2 Interrupt Handler
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DCD UART3_IRQHandler ;< 29 UART3 Interrupt Handler
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DCD AWT_IRQHandler ;< 30 Auto Wakeup Timer Handler
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DCD FAULT_IRQHandler ;< 31 FAULT Interrupt Handler
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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;reset NVIC if in rom debug
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LDR R0, =0x20000000
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LDR R2, =0x0
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MOVS R1, #0 ; for warning,
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ADD R1, PC,#0 ; for A1609W,
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CMP R1, R0
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BLS RAMCODE
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; ram code base address.
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ADD R2, R0,R2
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RAMCODE
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; reset Vector table address.
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LDR R0, =0xE000ED08
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STR R2, [R0]
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT WDT_IRQHandler [WEAK]
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EXPORT LVD_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT FLASHRAM_IRQHandler [WEAK]
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EXPORT RCC_IRQHandler [WEAK]
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EXPORT GPIOA_IRQHandler [WEAK]
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EXPORT GPIOB_IRQHandler [WEAK]
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EXPORT GPIOC_IRQHandler [WEAK]
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EXPORT GPIOF_IRQHandler [WEAK]
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EXPORT DMACH1_IRQHandler [WEAK]
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EXPORT DMACH23_IRQHandler [WEAK]
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EXPORT DMACH45_IRQHandler [WEAK]
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EXPORT ADC_IRQHandler [WEAK]
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EXPORT ATIM_IRQHandler [WEAK]
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EXPORT VC1_IRQHandler [WEAK]
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EXPORT VC2_IRQHandler [WEAK]
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EXPORT GTIM1_IRQHandler [WEAK]
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EXPORT GTIM2_IRQHandler [WEAK]
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EXPORT GTIM3_IRQHandler [WEAK]
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EXPORT GTIM4_IRQHandler [WEAK]
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EXPORT BTIM1_IRQHandler [WEAK]
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EXPORT BTIM2_IRQHandler [WEAK]
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EXPORT BTIM3_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT I2C2_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT UART1_IRQHandler [WEAK]
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EXPORT UART2_IRQHandler [WEAK]
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EXPORT UART3_IRQHandler [WEAK]
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EXPORT AWT_IRQHandler [WEAK]
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EXPORT FAULT_IRQHandler [WEAK]
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WDT_IRQHandler
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LVD_IRQHandler
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RTC_IRQHandler
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FLASHRAM_IRQHandler
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RCC_IRQHandler
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GPIOA_IRQHandler
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GPIOB_IRQHandler
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GPIOC_IRQHandler
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GPIOF_IRQHandler
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DMACH1_IRQHandler
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DMACH23_IRQHandler
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DMACH45_IRQHandler
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ADC_IRQHandler
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ATIM_IRQHandler
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VC1_IRQHandler
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VC2_IRQHandler
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GTIM1_IRQHandler
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GTIM2_IRQHandler
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GTIM3_IRQHandler
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GTIM4_IRQHandler
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BTIM1_IRQHandler
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BTIM2_IRQHandler
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BTIM3_IRQHandler
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I2C1_IRQHandler
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I2C2_IRQHandler
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SPI1_IRQHandler
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SPI2_IRQHandler
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UART1_IRQHandler
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UART2_IRQHandler
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UART3_IRQHandler
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AWT_IRQHandler
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FAULT_IRQHandler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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ENDIF
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END
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