258 lines
13 KiB
C
258 lines
13 KiB
C
/**
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* @file cw32f030_dma.h
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* @author your name (you@domain.com)
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* @brief
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* @version 0.1
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* @date 2021-05-17
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*
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* @copyright Copyright (c) 2021
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*
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*/
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/*******************************************************************************
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*
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* 代码许可和免责信息
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* 武汉力源半导体有限公司授予您使用所有编程代码示例的非专属的版权许可，您可以由此
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* 生成根据您的特定需要而定制的相似功能。根据不能被排除的任何法定保证，武汉力源半
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* 导体有限公司及其程序开发商和供应商对程序或技术支持（如果有）不提供任何明示或暗
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* 含的保证或条件，包括但不限于暗含的有关适销性、适用于某种特定用途和非侵权的保证
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* 或条件。
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* 无论何种情形，武汉力源半导体有限公司及其程序开发商或供应商均不对下列各项负责，
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* 即使被告知其发生的可能性时，也是如此：数据的丢失或损坏；直接的、特别的、附带的
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* 或间接的损害，或任何后果性经济损害；或利润、业务、收入、商誉或预期可节省金额的
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* 损失。
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* 某些司法辖区不允许对直接的、附带的或后果性的损害有任何的排除或限制，因此某些或
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* 全部上述排除或限制可能并不适用于您。
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*
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*******************************************************************************/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __CW32F03x_DMA_H__
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#define __CW32F03x_DMA_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*****************************************************************************/
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/* Include files */
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/*****************************************************************************/
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#include "base_types.h"
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#include "cw32f030.h"
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#include "system_cw32f030.h"
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/*****************************************************************************/
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/* Global pre-processor symbols/macros ('#define') */
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/*****************************************************************************/
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//============================================================
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typedef struct
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{
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uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
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This parameter can be a value of */
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uint32_t DMA_TransferWidth; ///transfer data width
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uint32_t DMA_SrcInc; /*!< Specifies whether the SRC address register is incremented or not.
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This parameter can be a value of @ref DMA_memory_incremented_mode */
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uint32_t DMA_DstInc; /*!< Specifies whether the DST address register is incremented or not.
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This parameter can be a value of @ref DMA_peripheral_incremented_mode */
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uint32_t TrigMode ;
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uint32_t HardTrigSource ;
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uint32_t DMA_TransferCnt; ///< Transfer counter
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uint32_t DMA_SrcAddress; ///< Source address>
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uint32_t DMA_DstAddress; ///< Dest address>
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}DMA_InitTypeDef;
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#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == CW_DMACHANNEL1) || \
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((PERIPH) == CW_DMACHANNEL2) || \
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((PERIPH) == CW_DMACHANNEL3) || \
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((PERIPH) == CW_DMACHANNEL4) || \
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((PERIPH) == CW_DMACHANNEL5))
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#define DMA_MODE_BULK 0x00UL
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#define DMA_MODE_BLOCK 0x08UL
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#define IS_DMA_MODE(MODE) (((MODE) == DMA_MODE_BULK) || \
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((MODE) == DMA_MODE_BLOCK))
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#define DMA_SrcAddress_Fix 0x00UL
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#define DMA_SrcAddress_Increase 0x10UL
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#define IS_DMA_SRCADDRESS_INC(INSTRANCE) (((INSTRANCE) == DMA_SrcAddress_Increase) || \
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((INSTRANCE) == DMA_SrcAddress_Fix))
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#define DMA_DstAddress_Fix 0x00UL
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#define DMA_DstAddress_Increase 0x20UL
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#define IS_DMA_DSTADDRESS_INC(INSTRANCE) (((INSTRANCE) == DMA_DstAddress_Increase) || \
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((INSTRANCE) == DMA_DstAddress_Fix))
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#define DMA_TRANSFER_WIDTH_8BIT 0x00UL
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#define DMA_TRANSFER_WIDTH_16BIT 0x40UL
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#define DMA_TRANSFER_WIDTH_32BIT 0x80UL
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#define IS_DMA_TRANSFER_WIDTH(INSTRANCE) (((INSTRANCE) == DMA_TRANSFER_WIDTH_8BIT) || \
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((INSTRANCE) == DMA_TRANSFER_WIDTH_16BIT) || \
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((INSTRANCE) == DMA_TRANSFER_WIDTH_32BIT))
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#define IS_DMA_TRANSFERCNT(CNT) (((CNT)>= 1) && ((CNT)<= 65535))
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#define DMA_SWTrig 0x00UL
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#define DMA_HardTrig 0x01UL
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#define IS_DMA_TRIG(TRIG) (((TRIG) == DMA_SWTrig) || \
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((TRIG) == DMA_HardTrig))
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#define DMA_HardTrig_UART1_RXBufferNE (uint32_t)(0x00UL << 2)
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#define DMA_HardTrig_UART1_TXBufferE (uint32_t)(0x01UL << 2)
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#define DMA_HardTrig_UART2_RXBufferNE (uint32_t)(0x02UL << 2)
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#define DMA_HardTrig_UART2_TXBufferE (uint32_t)(0x03UL << 2)
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#define DMA_HardTrig_UART3_RXBufferNE (uint32_t)(0x04UL << 2)
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#define DMA_HardTrig_UART3_TXBufferE (uint32_t)(0x05UL << 2)
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#define DMA_HardTrig_SPI1_RXBufferNE (uint32_t)(0x06UL << 2)
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#define DMA_HardTrig_SPI1_TXBufferE (uint32_t)(0x07UL << 2)
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#define DMA_HardTrig_SPI2_RXBufferNE (uint32_t)(0x08UL << 2)
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#define DMA_HardTrig_SPI2_TXBufferE (uint32_t)(0x09UL << 2)
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#define DMA_HardTrig_ADC_TRANSCOMPLETE (uint32_t)(0x0AUL << 2)
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#define DMA_HardTrig_BTIM1_OVERINT (uint32_t)(0x0BUL << 2)
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#define DMA_HardTrig_BTIM1_TRIGINT (uint32_t)(0x0CUL << 2)
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#define DMA_HardTrig_BTIM2_OVERINT (uint32_t)(0x0DUL << 2)
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#define DMA_HardTrig_BTIM2_TRIGINT (uint32_t)(0x0EUL << 2)
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#define DMA_HardTrig_BTIM3_OVERINT (uint32_t)(0x0FUL << 2)
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#define DMA_HardTrig_BTIM3_TRIGINT (uint32_t)(0x10UL << 2)
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#define DMA_HardTrig_ATIM_CH1A2A3A4 (uint32_t)(0x11UL << 2)
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#define DMA_HardTrig_ATIM_CH1B2B3B (uint32_t)(0x12UL << 2)
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#define DMA_HardTrig_GTIM1_OVERINT (uint32_t)(0x13UL << 2)
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#define DMA_HardTrig_GTIM1_TRIGINT (uint32_t)(0x14UL << 2)
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#define DMA_HardTrig_GTIM1_CH1COMINT (uint32_t)(0x15UL << 2)
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#define DMA_HardTrig_GTIM1_CH2COMINT (uint32_t)(0x16UL << 2)
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#define DMA_HardTrig_GTIM1_CH3COMINT (uint32_t)(0x17UL << 2)
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#define DMA_HardTrig_GTIM1_CH4COMINT (uint32_t)(0x18UL << 2)
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#define DMA_HardTrig_GTIM2_OVERINT (uint32_t)(0x19UL << 2)
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#define DMA_HardTrig_GTIM2_TRIGINT (uint32_t)(0x1AUL << 2)
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#define DMA_HardTrig_GTIM2_CH1COMINT (uint32_t)(0x1BUL << 2)
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#define DMA_HardTrig_GTIM2_CH2COMINT (uint32_t)(0x1CUL << 2)
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#define DMA_HardTrig_GTIM2_CH3COMINT (uint32_t)(0x1DUL << 2)
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#define DMA_HardTrig_GTIM2_CH4COMINT (uint32_t)(0x1EUL << 2)
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#define DMA_HardTrig_GTIM3_OVERINT (uint32_t)(0x1FUL << 2)
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#define DMA_HardTrig_GTIM3_TRIGINT (uint32_t)(0x20UL << 2)
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#define DMA_HardTrig_GTIM3_CH1COMINT (uint32_t)(0x21UL << 2)
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#define DMA_HardTrig_GTIM3_CH2COMINT (uint32_t)(0x22UL << 2)
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#define DMA_HardTrig_GTIM3_CH3COMINT (uint32_t)(0x23UL << 2)
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#define DMA_HardTrig_GTIM3_CH4COMINT (uint32_t)(0x24UL << 2)
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#define DMA_HardTrig_GTIM4_OVERINT (uint32_t)(0x25UL << 2)
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#define DMA_HardTrig_GTIM4_TRIGINT (uint32_t)(0x26UL << 2)
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#define DMA_HardTrig_GTIM4_CH1COMINT (uint32_t)(0x27UL << 2)
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#define DMA_HardTrig_GTIM4_CH2COMINT (uint32_t)(0x28UL << 2)
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#define DMA_HardTrig_GTIM4_CH3COMINT (uint32_t)(0x29UL << 2)
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#define DMA_HardTrig_GTIM4_CH4COMINT (uint32_t)(0x2AUL << 2)
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#define IS_DMA_HARD_TRIGSRC(TRIGSRC) (((TRIGSRC) == DMA_HardTrig_UART1_RXBufferNE)|| \
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((TRIGSRC) == DMA_HardTrig_UART1_TXBufferE)|| \
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((TRIGSRC) == DMA_HardTrig_UART2_RXBufferNE)|| \
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((TRIGSRC) == DMA_HardTrig_UART2_TXBufferE)|| \
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((TRIGSRC) == DMA_HardTrig_UART3_RXBufferNE)|| \
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((TRIGSRC) == DMA_HardTrig_UART3_TXBufferE)|| \
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((TRIGSRC) == DMA_HardTrig_SPI1_RXBufferNE)|| \
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((TRIGSRC) == DMA_HardTrig_SPI1_TXBufferE)|| \
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((TRIGSRC) == DMA_HardTrig_SPI2_RXBufferNE)|| \
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((TRIGSRC) == DMA_HardTrig_SPI2_TXBufferE)|| \
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((TRIGSRC) == DMA_HardTrig_ADC_TRANSCOMPLETE)|| \
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((TRIGSRC) == DMA_HardTrig_BTIM1_OVERINT)|| \
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((TRIGSRC) == DMA_HardTrig_BTIM1_TRIGINT)|| \
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((TRIGSRC) == DMA_HardTrig_BTIM2_OVERINT)|| \
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((TRIGSRC) == DMA_HardTrig_BTIM2_TRIGINT)|| \
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((TRIGSRC) == DMA_HardTrig_BTIM3_OVERINT)|| \
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((TRIGSRC) == DMA_HardTrig_BTIM3_TRIGINT)|| \
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((TRIGSRC) == DMA_HardTrig_ATIM_CH1A2A3A4)|| \
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((TRIGSRC) == DMA_HardTrig_ATIM_CH1B2B3B)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM1_OVERINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM1_TRIGINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM1_CH1COMINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM1_CH2COMINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM1_CH3COMINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM1_CH4COMINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM2_OVERINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM2_TRIGINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM2_CH1COMINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM2_CH2COMINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM2_CH3COMINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM2_CH4COMINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM3_OVERINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM3_TRIGINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM3_CH1COMINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM3_CH2COMINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM3_CH3COMINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM3_CH4COMINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM4_OVERINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM4_TRIGINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM4_CH1COMINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM4_CH2COMINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM4_CH3COMINT)|| \
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((TRIGSRC) == DMA_HardTrig_GTIM4_CH4COMINT))
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#define DMA_CHANNEL_EN bv0 //DMA CHANNEL ENABLE
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#define DMA_SOFTTRIG_EN bv1 //Soft Trig Trans Start Now
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#define CSR_CLEAR_Mask (uint32_t)0xFFFFFF07
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#define TRIG_CLEAR_Mask (uint32_t)0xFFFFFF00
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#define CNT_CLEAR_Mask (uint32_t)0xFFFF0000
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#define DMA_IT_TC ((uint32_t)0x00000002)
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#define DMA_IT_TE ((uint32_t)0x00000004)
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#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF9) == 0x00) && ((IT) != 0x00))
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#define DMA_IT_TC1 ((uint32_t)0x00000001)
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#define DMA_IT_TE1 ((uint32_t)0x00000002)
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#define DMA_IT_TC2 ((uint32_t)0x00000010)
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#define DMA_IT_TE2 ((uint32_t)0x00000020)
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#define DMA_IT_TC3 ((uint32_t)0x00000100)
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#define DMA_IT_TE3 ((uint32_t)0x00000200)
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#define DMA_IT_TC4 ((uint32_t)0x00001000)
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#define DMA_IT_TE4 ((uint32_t)0x00002000)
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#define DMA_IT_TC5 ((uint32_t)0x00010000)
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#define DMA_IT_TE5 ((uint32_t)0x00020000)
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#define DMA_IT_ALL ((uint32_t)0x00033333)
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#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xFFFCCCCC) == 0x00) && ((IT) != 0x00))
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#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TC1) || ((IT) == DMA_IT_TE1) || \
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((IT) == DMA_IT_TC2) || ((IT) == DMA_IT_TE2) || \
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((IT) == DMA_IT_TC3) || ((IT) == DMA_IT_TE3) || \
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((IT) == DMA_IT_TC4) || ((IT) == DMA_IT_TE4) || \
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((IT) == DMA_IT_TC5) || ((IT) == DMA_IT_TE5))
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#define DMA_CHANNEL_STATUS_INIT ((uint8_t)0x00)
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#define DMA_CHANNEL_STATUS_ADDRESSOUTRANGE ((uint8_t)0x01)
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#define DMA_CHANNEL_STATUS_STOPREQ ((uint8_t)0x02)
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#define DMA_CHANNEL_STATUS_SRCADDERR ((uint8_t)0x03)
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#define DMA_CHANNEL_STATUS_DSTADDERR ((uint8_t)0x04)
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#define DMA_CHANNEL_STATUS_TRANSCOMPLETE ((uint8_t)0x05)
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//============================================================
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void DMA_DeInit(DMACHANNEL_TypeDef* DMAy_Channelx);
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void DMA_Init(DMACHANNEL_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
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void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
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void DMA_Cmd(DMACHANNEL_TypeDef* DMAy_Channelx, FunctionalState NewState);
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void DMA_SWTrigCmd(DMACHANNEL_TypeDef* DMAy_Channelx);
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void DMA_ITConfig(DMACHANNEL_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
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ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
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void DMA_ClearITPendingBit(uint32_t DMAy_IT);
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uint8_t DMA_GetFlagStatus(DMACHANNEL_TypeDef* DMAy_Channelx);
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//============================================================
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#ifdef __cplusplus
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}
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#endif
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#endif
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